| Paul Menzel | 2628571 | 2017-04-17 10:57:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Intel ACPI Component Architecture |
| 3 | * AML/ASL+ Disassembler version 20160831-64 |
| 4 | * Copyright (c) 2000 - 2016 Intel Corporation |
| 5 | * |
| 6 | * Disassembling to symbolic ASL+ operators |
| 7 | * |
| 8 | * Disassembly of ssdt2.dat, Mon Jan 2 15:19:14 2017 |
| 9 | * |
| 10 | * Original Table Header: |
| 11 | * Signature "SSDT" |
| 12 | * Length 0x00000143 (323) |
| 13 | * Revision 0x01 |
| 14 | * Checksum 0x77 |
| 15 | * OEM ID "AMI" |
| 16 | * OEM Table ID "CPU2PM" |
| 17 | * OEM Revision 0x00000001 (1) |
| 18 | * Compiler ID "INTL" |
| 19 | * Compiler Version 0x20060113 (537264403) |
| 20 | */ |
| 21 | DefinitionBlock ("", "SSDT", 1, "AMI", "CPU2PM", 0x00000001) |
| 22 | { |
| 23 | External (_PR_.CPU1._PPC, IntObj) |
| 24 | External (_PR_.CPU1._PSS, IntObj) |
| 25 | External (_PR_.CPU2, DeviceObj) |
| 26 | External (CFGD, UnknownObj) |
| 27 | External (NCPU, UnknownObj) |
| 28 | External (TYPE, UnknownObj) |
| 29 | |
| 30 | Scope (\_PR.CPU2) |
| 31 | { |
| 32 | Name (NPCT, Package (0x02) |
| 33 | { |
| 34 | ResourceTemplate () |
| 35 | { |
| 36 | Register (FFixedHW, |
| 37 | 0x40, // Bit Width |
| 38 | 0x00, // Bit Offset |
| 39 | 0x0000000000000199, // Address |
| 40 | ,) |
| 41 | }, |
| 42 | |
| 43 | ResourceTemplate () |
| 44 | { |
| 45 | Register (FFixedHW, |
| 46 | 0x10, // Bit Width |
| 47 | 0x00, // Bit Offset |
| 48 | 0x0000000000000198, // Address |
| 49 | ,) |
| 50 | } |
| 51 | }) |
| 52 | Name (SPCT, Package (0x02) |
| 53 | { |
| 54 | ResourceTemplate () |
| 55 | { |
| 56 | Register (SystemIO, |
| 57 | 0x10, // Bit Width |
| 58 | 0x00, // Bit Offset |
| 59 | 0x0000000000000904, // Address |
| 60 | ,) |
| 61 | }, |
| 62 | |
| 63 | ResourceTemplate () |
| 64 | { |
| 65 | Register (SystemIO, |
| 66 | 0x10, // Bit Width |
| 67 | 0x00, // Bit Offset |
| 68 | 0x0000000000000906, // Address |
| 69 | ,) |
| 70 | } |
| 71 | }) |
| 72 | Method (_PCT, 0, NotSerialized) // _PCT: Performance Control |
| 73 | { |
| 74 | If ((TYPE & 0x01) == 0x01) |
| 75 | { |
| 76 | Return (NPCT) /* \_PR_.CPU2.NPCT */ |
| 77 | } |
| 78 | Else |
| 79 | { |
| 80 | Return (SPCT) /* \_PR_.CPU2.SPCT */ |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | Name (XPSS, 0x00) |
| 85 | Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States |
| 86 | { |
| 87 | Return (\_PR.CPU1._PSS) /* External reference */ |
| 88 | } |
| 89 | |
| 90 | Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities |
| 91 | { |
| 92 | Return (\_PR.CPU1._PPC) /* External reference */ |
| 93 | } |
| 94 | |
| 95 | Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies |
| 96 | { |
| 97 | If (CFGD & 0x01000000) |
| 98 | { |
| 99 | If (TYPE & 0x0800) |
| 100 | { |
| 101 | Return (Package (0x01) |
| 102 | { |
| 103 | Package (0x05) |
| 104 | { |
| 105 | 0x05, |
| 106 | 0x00, |
| 107 | 0x00, |
| 108 | 0xFE, |
| 109 | NCPU |
| 110 | } |
| 111 | }) |
| 112 | } |
| 113 | |
| 114 | Return (Package (0x01) |
| 115 | { |
| 116 | Package (0x05) |
| 117 | { |
| 118 | 0x05, |
| 119 | 0x00, |
| 120 | 0x00, |
| 121 | 0xFC, |
| 122 | NCPU |
| 123 | } |
| 124 | }) |
| 125 | } |
| 126 | |
| 127 | Return (Package (0x01) |
| 128 | { |
| 129 | Package (0x05) |
| 130 | { |
| 131 | 0x05, |
| 132 | 0x00, |
| 133 | 0x00, |
| 134 | 0xFC, |
| 135 | NCPU |
| 136 | } |
| 137 | }) |
| 138 | } |
| 139 | } |
| 140 | } |
| 141 | |