| Paul Menzel | c0b847f | 2017-08-23 09:36:59 +0200 | [diff] [blame] | 1 | # This image was built using coreboot TIMELESS |
| 2 | CONFIG_COLLECT_TIMESTAMPS=y |
| 3 | CONFIG_VENDOR_ASROCK=y |
| 4 | CONFIG_VGA_BIOS=y |
| 5 | CONFIG_VGA_BIOS_FILE="pci1002,9802.rom.lzma" |
| 6 | CONFIG_BOARD_ASROCK_E350M1=y |
| 7 | CONFIG_PCIEXP_L1_SUB_STATE=y |
| 8 | CONFIG_NO_POST=y |
| 9 | CONFIG_PCIEXP_ASPM=y |
| 10 | # CONFIG_CONSOLE_SERIAL is not set |
| 11 | CONFIG_SEABIOS_MASTER=y |
| 12 | CONFIG_COREINFO_SECONDARY_PAYLOAD=y |
| 13 | CONFIG_MEMTEST_SECONDARY_PAYLOAD=y |
| 14 | CONFIG_NVRAMCUI_SECONDARY_PAYLOAD=y |
| 15 | CONFIG_TINT_SECONDARY_PAYLOAD=y |