Stefan Ott | 798f446 | 2020-06-10 03:47:09 +0200 | [diff] [blame^] | 1 | |
| 2 | coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 bootblock starting (log level: 6)... |
| 3 | FMAP: Found "FLASH" version 1.1 at 0x710000. |
| 4 | FMAP: base = 0xff800000 size = 0x800000 #areas = 4 |
| 5 | FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| 6 | CBFS: Locating 'fallback/romstage' |
| 7 | CBFS: Found @ offset 80 size 1067c |
| 8 | BS: bootblock times (exec / console): total (unknown) / 1 ms |
| 9 | |
| 10 | |
| 11 | coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 romstage starting (log level: 6)... |
| 12 | Setting up static southbridge registers... done. |
| 13 | Disabling Watchdog reboot... done. |
| 14 | Setting up static northbridge registers... done. |
| 15 | SMBus controller enabled |
| 16 | Setting up Chipset Initialization Registers (CIR) |
| 17 | SB: Resume from S3 detected. |
| 18 | Intel ME early init |
| 19 | Intel ME firmware is ready |
| 20 | ME: Requested 32MB UMA |
| 21 | FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| 22 | SMM Memory Map |
| 23 | SMRAM : 0xbf800000 0x800000 |
| 24 | Subregion 0: 0xbf800000 0x700000 |
| 25 | Subregion 1: 0xbff00000 0x100000 |
| 26 | Subregion 2: 0xc0000000 0x0 |
| 27 | MTRR Range: Start=bf000000 End=bf800000 (Size 800000) |
| 28 | MTRR Range: Start=bf800000 End=c0000000 (Size 800000) |
| 29 | MTRR Range: Start=ff800000 End=0 (Size 800000) |
| 30 | BS: romstage times (exec / console): total (unknown) / 1 ms |
| 31 | |
| 32 | |
| 33 | coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 postcar starting (log level: 6)... |
| 34 | Jumping to image. |
| 35 | |
| 36 | |
| 37 | coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 ramstage starting (log level: 6)... |
| 38 | S3 Resume |
| 39 | Disabling PEG10. |
| 40 | Enumerating buses... |
| 41 | Root Device scanning... |
| 42 | CPU_CLUSTER: 0 enabled |
| 43 | DOMAIN: 0000 enabled |
| 44 | DOMAIN: 0000 scanning... |
| 45 | PCI: pci_scan_bus for bus 00 |
| 46 | PCI: 00:00.0 [8086/0044] enabled |
| 47 | PCI: 00:02.0 [8086/0046] enabled |
| 48 | PCI: 00:16.0 [8086/3b64] enabled |
| 49 | PCI: 00:16.1: Disabling device |
| 50 | PCI: 00:16.2: Disabling device |
| 51 | PCI: 00:16.3: Disabling device |
| 52 | PCI: 00:19.0 [8086/10ea] enabled |
| 53 | PCI: 00:1a.0 [8086/3b3c] enabled |
| 54 | PCI: 00:1b.0 [8086/3b56] enabled |
| 55 | PCI: 00:1c.0 subordinate bus PCI Express |
| 56 | PCI: 00:1c.0 [8086/3b42] enabled |
| 57 | PCI: 00:1c.1 subordinate bus PCI Express |
| 58 | PCI: 00:1c.1 [8086/3b44] enabled |
| 59 | PCI: 00:1c.2: Disabling device |
| 60 | PCI: 00:1c.2 [8086/3b46] disabled No operations |
| 61 | PCI: 00:1c.3 subordinate bus PCI Express |
| 62 | PCI: 00:1c.3 [8086/3b48] enabled |
| 63 | PCI: 00:1c.4 subordinate bus PCI Express |
| 64 | PCI: 00:1c.4 [8086/3b4a] enabled |
| 65 | PCI: 00:1c.5: Disabling device |
| 66 | PCI: 00:1c.5 [8086/3b4c] disabled No operations |
| 67 | PCI: 00:1c.6: Disabling device |
| 68 | PCI: 00:1c.6 [8086/3b4e] disabled No operations |
| 69 | PCI: 00:1c.7: Disabling device |
| 70 | PCI: 00:1c.7 [8086/3b50] disabled No operations |
| 71 | PCI: 00:1d.0 [8086/3b34] enabled |
| 72 | PCI: 00:1e.0 [8086/2448] enabled |
| 73 | PCI: 00:1f.0 [8086/3b07] enabled |
| 74 | PCI: 00:1f.2 [8086/3b2e] enabled |
| 75 | PCI: 00:1f.3 [8086/3b30] enabled |
| 76 | PCI: 00:1f.4: Disabling device |
| 77 | PCI: 00:1f.5: Disabling device |
| 78 | PCI: 00:1f.5 [8086/3b2d] disabled No operations |
| 79 | PCI: 00:1f.6 [8086/3b32] enabled |
| 80 | PCI: Leftover static devices: |
| 81 | PCI: 00:01.0 |
| 82 | PCI: 00:16.1 |
| 83 | PCI: 00:16.2 |
| 84 | PCI: 00:16.3 |
| 85 | PCI: 00:1f.4 |
| 86 | PCI: Check your devicetree.cb. |
| 87 | PCI: 00:1c.0 scanning... |
| 88 | PCI: pci_scan_bus for bus 01 |
| 89 | scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| 90 | PCI: 00:1c.1 scanning... |
| 91 | PCI: pci_scan_bus for bus 02 |
| 92 | scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| 93 | PCI: 00:1c.3 scanning... |
| 94 | PCI: pci_scan_bus for bus 03 |
| 95 | scan_bus: bus PCI: 00:1c.3 finished in 0 msecs |
| 96 | PCI: 00:1c.4 scanning... |
| 97 | PCI: pci_scan_bus for bus 04 |
| 98 | PCI: 04:00.0 [168c/002a] enabled |
| 99 | Enabling Common Clock Configuration |
| 100 | ASPM: Enabled L1 |
| 101 | PCIe: Max_Payload_Size adjusted to 128 |
| 102 | Failed to enable LTR for dev = PCI: 04:00.0 |
| 103 | scan_bus: bus PCI: 00:1c.4 finished in 0 msecs |
| 104 | PCI: 00:1e.0 scanning... |
| 105 | PCI: pci_scan_bus for bus 05 |
| 106 | scan_bus: bus PCI: 00:1e.0 finished in 0 msecs |
| 107 | PCI: 00:1f.0 scanning... |
| 108 | PNP: 164e.3 enabled |
| 109 | PNP: 164e.2 disabled |
| 110 | PNP: 164e.7 disabled |
| 111 | PNP: 164e.19 disabled |
| 112 | PNP: 0c31.0 enabled |
| 113 | PMH7: ID 04 Revision 01 |
| 114 | PNP: 00ff.1 enabled |
| 115 | H8: EC Firmware ID 6QHT34WW-3.18, Version 5.01B |
| 116 | H8: BDC not installed |
| 117 | H8: WWAN detection not implemented. Assuming WWAN installed |
| 118 | dock is connected |
| 119 | PNP: 00ff.2 enabled |
| 120 | scan_bus: bus PCI: 00:1f.0 finished in 7 msecs |
| 121 | PCI: 00:1f.3 scanning... |
| 122 | bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| 123 | bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| 124 | bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| 125 | bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| 126 | bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| 127 | bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| 128 | bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| 129 | bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| 130 | scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| 131 | scan_bus: bus DOMAIN: 0000 finished in 7 msecs |
| 132 | scan_bus: bus Root Device finished in 7 msecs |
| 133 | done |
| 134 | BS: BS_DEV_ENUMERATE run times (exec / console): 8 / 0 ms |
| 135 | FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| 136 | MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| 137 | Manufacturer: c2 |
| 138 | SF: Detected c2 2017 with sector size 0x1000, total 0x800000 |
| 139 | found VGA at PCI: 00:02.0 |
| 140 | Setting up VGA for PCI: 00:02.0 |
| 141 | Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| 142 | Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| 143 | Allocating resources... |
| 144 | Reading resources... |
| 145 | Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000. |
| 146 | ram_before_4g_top: 0xbf800000 |
| 147 | TOUUD: 0x2380 |
| 148 | PNP: 00ff.1 missing read_resources |
| 149 | PNP: 00ff.2 missing read_resources |
| 150 | Done reading resources. |
| 151 | skipping PNP: 164e.3@29 fixed resource, size=0! |
| 152 | skipping PNP: 164e.3@f0 fixed resource, size=0! |
| 153 | skipping PNP: 00ff.2@60 fixed resource, size=0! |
| 154 | skipping PNP: 00ff.2@62 fixed resource, size=0! |
| 155 | skipping PNP: 00ff.2@64 fixed resource, size=0! |
| 156 | skipping PNP: 00ff.2@66 fixed resource, size=0! |
| 157 | Setting resources... |
| 158 | PCI: 00:02.0 10 <- [0x00cf800000 - 0x00cfbfffff] size 0x00400000 gran 0x16 mem64 |
| 159 | PCI: 00:02.0 20 <- [0x0000001840 - 0x0000001847] size 0x00000008 gran 0x03 io |
| 160 | PCI: 00:16.0 10 <- [0x00cfd2a000 - 0x00cfd2a00f] size 0x00000010 gran 0x04 mem64 |
| 161 | PCI: 00:19.0 10 <- [0x00cfd00000 - 0x00cfd1ffff] size 0x00020000 gran 0x11 mem |
| 162 | PCI: 00:19.0 14 <- [0x00cfd24000 - 0x00cfd24fff] size 0x00001000 gran 0x0c mem |
| 163 | PCI: 00:19.0 18 <- [0x0000001800 - 0x000000181f] size 0x00000020 gran 0x05 io |
| 164 | PCI: 00:1a.0 10 <- [0x00cfd27000 - 0x00cfd273ff] size 0x00000400 gran 0x0a mem |
| 165 | PCI: 00:1b.0 10 <- [0x00cfd20000 - 0x00cfd23fff] size 0x00004000 gran 0x0e mem64 |
| 166 | PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| 167 | PCI: 00:1c.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| 168 | PCI: 00:1c.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 mem |
| 169 | PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| 170 | PCI: 00:1c.1 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| 171 | PCI: 00:1c.1 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 mem |
| 172 | PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| 173 | PCI: 00:1c.3 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| 174 | PCI: 00:1c.3 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 mem |
| 175 | PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| 176 | PCI: 00:1c.4 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| 177 | PCI: 00:1c.4 20 <- [0x00cfc00000 - 0x00cfcfffff] size 0x00100000 gran 0x14 bus 04 mem |
| 178 | PCI: 04:00.0 10 <- [0x00cfc00000 - 0x00cfc0ffff] size 0x00010000 gran 0x10 mem64 |
| 179 | PCI: 00:1d.0 10 <- [0x00cfd28000 - 0x00cfd283ff] size 0x00000400 gran 0x0a mem |
| 180 | PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io |
| 181 | PCI: 00:1e.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 prefmem |
| 182 | PCI: 00:1e.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 mem |
| 183 | PNP: 164e.3 60 <- [0x0000000200 - 0x0000000207] size 0x00000008 gran 0x03 io |
| 184 | PNP: 164e.3 29 <- [0x00000000b0 - 0x00000000af] size 0x00000000 gran 0x00 irq |
| 185 | PNP: 164e.3 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq |
| 186 | PNP: 164e.3 f0 <- [0x0000000082 - 0x0000000081] size 0x00000000 gran 0x00 irq |
| 187 | PNP: 00ff.1 missing set_resources |
| 188 | PNP: 00ff.2 missing set_resources |
| 189 | PCI: 00:1f.2 10 <- [0x0000001848 - 0x000000184f] size 0x00000008 gran 0x03 io |
| 190 | PCI: 00:1f.2 14 <- [0x0000001858 - 0x000000185b] size 0x00000004 gran 0x02 io |
| 191 | PCI: 00:1f.2 18 <- [0x0000001850 - 0x0000001857] size 0x00000008 gran 0x03 io |
| 192 | PCI: 00:1f.2 1c <- [0x000000185c - 0x000000185f] size 0x00000004 gran 0x02 io |
| 193 | PCI: 00:1f.2 20 <- [0x0000001820 - 0x000000183f] size 0x00000020 gran 0x05 io |
| 194 | PCI: 00:1f.2 24 <- [0x00cfd26000 - 0x00cfd267ff] size 0x00000800 gran 0x0b mem |
| 195 | PCI: 00:1f.3 10 <- [0x00cfd29000 - 0x00cfd290ff] size 0x00000100 gran 0x08 mem64 |
| 196 | PCI: 00:1f.6 10 <- [0x00cfd25000 - 0x00cfd25fff] size 0x00001000 gran 0x0c mem64 |
| 197 | Done setting resources. |
| 198 | Done allocating resources. |
| 199 | BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms |
| 200 | Enabling resources... |
| 201 | PCI: 00:00.0 subsystem <- 17aa/2193 |
| 202 | PCI: 00:00.0 cmd <- 06 |
| 203 | PCI: 00:02.0 subsystem <- 17aa/215a |
| 204 | PCI: 00:02.0 cmd <- 03 |
| 205 | PCI: 00:16.0 subsystem <- 8086/3b64 |
| 206 | PCI: 00:16.0 cmd <- 02 |
| 207 | PCI: 00:19.0 subsystem <- 17aa/2153 |
| 208 | PCI: 00:19.0 cmd <- 103 |
| 209 | PCI: 00:1a.0 subsystem <- 17aa/2163 |
| 210 | PCI: 00:1a.0 cmd <- 102 |
| 211 | PCI: 00:1b.0 subsystem <- 17aa/215e |
| 212 | PCI: 00:1b.0 cmd <- 102 |
| 213 | PCI: 00:1c.0 bridge ctrl <- 0013 |
| 214 | PCI: 00:1c.0 cmd <- 100 |
| 215 | PCI: 00:1c.1 bridge ctrl <- 0013 |
| 216 | PCI: 00:1c.1 cmd <- 100 |
| 217 | PCI: 00:1c.3 bridge ctrl <- 0013 |
| 218 | PCI: 00:1c.3 cmd <- 100 |
| 219 | PCI: 00:1c.4 bridge ctrl <- 0013 |
| 220 | PCI: 00:1c.4 cmd <- 106 |
| 221 | PCI: 00:1d.0 subsystem <- 17aa/2163 |
| 222 | PCI: 00:1d.0 cmd <- 102 |
| 223 | PCI: 00:1e.0 bridge ctrl <- 0013 |
| 224 | PCI: 00:1e.0 subsystem <- 8086/2448 |
| 225 | PCI: 00:1e.0 cmd <- 100 |
| 226 | PCI: 00:1f.0 subsystem <- 17aa/2166 |
| 227 | PCI: 00:1f.0 cmd <- 107 |
| 228 | PCI: 00:1f.2 subsystem <- 17aa/2168 |
| 229 | PCI: 00:1f.2 cmd <- 03 |
| 230 | PCI: 00:1f.3 subsystem <- 17aa/2167 |
| 231 | PCI: 00:1f.3 cmd <- 103 |
| 232 | PCI: 00:1f.6 subsystem <- 8086/3b32 |
| 233 | PCI: 00:1f.6 cmd <- 02 |
| 234 | PCI: 04:00.0 cmd <- 02 |
| 235 | done. |
| 236 | Found TPM ST33ZP24 by ST Microelectronics |
| 237 | TPM: Handle S3 resume. |
| 238 | TPM: Resume |
| 239 | TPM: command 0x99 returned 0x9 |
| 240 | TPM: Resume failed (0x9). |
| 241 | BS: BS_DEV_INIT entry times (exec / console): 4 / 0 ms |
| 242 | Initializing devices... |
| 243 | CPU_CLUSTER: 0 init |
| 244 | MTRR: Physical address space: |
| 245 | 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 246 | 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 247 | 0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 |
| 248 | 0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 |
| 249 | 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 250 | 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 251 | 0x0000000100000000 - 0x0000000238000000 size 0x138000000 type 6 |
| 252 | MTRR: Fixed MSR 0x250 0x0606060606060606 |
| 253 | MTRR: Fixed MSR 0x258 0x0606060606060606 |
| 254 | MTRR: Fixed MSR 0x259 0x0000000000000000 |
| 255 | MTRR: Fixed MSR 0x268 0x0606060606060606 |
| 256 | MTRR: Fixed MSR 0x269 0x0606060606060606 |
| 257 | MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| 258 | MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| 259 | MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| 260 | MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| 261 | MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| 262 | MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| 263 | CPU physical address size: 36 bits |
| 264 | MTRR: default type WB/UC MTRR counts: 4/6. |
| 265 | MTRR: WB selected as default type. |
| 266 | MTRR: 0 base 0x00000000bf800000 mask 0x0000000fff800000 type 0 |
| 267 | MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| 268 | MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| 269 | MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| 270 | |
| 271 | MTRR check |
| 272 | Fixed MTRRs : Enabled |
| 273 | Variable MTRRs: Enabled |
| 274 | |
| 275 | CPU has 2 cores, 4 threads enabled. |
| 276 | Setting up SMI for CPU |
| 277 | Will perform SMM setup. |
| 278 | FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| 279 | CBFS: Locating 'cpu_microcode_blob.bin' |
| 280 | CBFS: Found @ offset 10780 size 3400 |
| 281 | microcode: sig=0x20652 pf=0x10 revision=0x11 |
| 282 | CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| 283 | Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 |
| 284 | Processing 16 relocs. Offset value of 0x00030000 |
| 285 | Attempting to start 3 APs |
| 286 | Waiting for 10ms after sending INIT. |
| 287 | Waiting for 1st SIPI to complete...done. |
| 288 | Waiting for 2nd SIPI to complete...AP: slot 1 apic_id 1. |
| 289 | done. |
| 290 | AP: slot 2 apic_id 5. |
| 291 | AP: slot 3 apic_id 4. |
| 292 | Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b0 memsize: 0x1b0 |
| 293 | Processing 13 relocs. Offset value of 0x00038000 |
| 294 | SMM Module: stub loaded at 0x00038000. Will call 0xbf7a8c97(0x00000000) |
| 295 | Installing SMM handler to 0xbf800000 |
| 296 | Loading module at 0xbf810000 with entry 0xbf81029a. filesize: 0x1590 memsize: 0x55b8 |
| 297 | Processing 66 relocs. Offset value of 0xbf810000 |
| 298 | Loading module at 0xbf808000 with entry 0xbf808000. filesize: 0x1b0 memsize: 0x1b0 |
| 299 | Processing 13 relocs. Offset value of 0xbf808000 |
| 300 | SMM Module: placing jmp sequence at 0xbf807c00 rel16 0x03fd |
| 301 | SMM Module: placing jmp sequence at 0xbf807800 rel16 0x07fd |
| 302 | SMM Module: placing jmp sequence at 0xbf807400 rel16 0x0bfd |
| 303 | SMM Module: stub loaded at 0xbf808000. Will call 0xbf81029a(0x00000000) |
| 304 | Initializing Southbridge SMI... |
| 305 | |
| 306 | New SMBASE 0xbf800000 |
| 307 | In relocation handler: cpu 0 |
| 308 | New SMBASE=0xbf800000 |
| 309 | Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| 310 | Relocation complete. |
| 311 | New SMBASE 0xbf7ffc00 |
| 312 | microcode: Update skipped, already up-to-date |
| 313 | In relocation handler: cpu 1 |
| 314 | New SMBASE=0xbf7ffc00 |
| 315 | Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| 316 | Relocation complete. |
| 317 | New SMBASE 0xbf7ff400 |
| 318 | In relocation handler: cpu 3 |
| 319 | New SMBASE=0xbf7ff400 |
| 320 | Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| 321 | microcode: Update skipped, already up-to-date |
| 322 | Relocation complete. |
| 323 | microcode: Update skipped, already up-to-date |
| 324 | New SMBASE 0xbf7ff800 |
| 325 | In relocation handler: cpu 2 |
| 326 | New SMBASE=0xbf7ff800 |
| 327 | Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| 328 | Relocation complete. |
| 329 | microcode: Update skipped, already up-to-date |
| 330 | Initializing CPU #0 |
| 331 | CPU: vendor Intel device 20652 |
| 332 | CPU: family 06, model 25, stepping 02 |
| 333 | Enabling cache |
| 334 | CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| 335 | CPU:lapic=0, boot_cpu=1 |
| 336 | Setting up local APIC... |
| 337 | apic_id: 0x00 done. |
| 338 | VMX status: enabled |
| 339 | IA32_FEATURE_CONTROL status: locked |
| 340 | model_x06ax: frequency set to 2527 |
| 341 | Turbo is available and visible |
| 342 | CPU #0 initialized |
| 343 | Initializing CPU #1 |
| 344 | Initializing CPU #3 |
| 345 | CPU: vendor Intel device 20652 |
| 346 | CPU: family 06, model 25, stepping 02 |
| 347 | Initializing CPU #2 |
| 348 | Enabling cache |
| 349 | CPU: vendor Intel device 20652 |
| 350 | CPU: vendor Intel device 20652 |
| 351 | CPU: family 06, model 25, stepping 02 |
| 352 | CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| 353 | CPU: family 06, model 25, stepping 02 |
| 354 | CPU:lapic=1, boot_cpu=0 |
| 355 | Enabling cache |
| 356 | Setting up local APIC... |
| 357 | Enabling cache |
| 358 | apic_id: 0x01 done. |
| 359 | VMX status: enabled |
| 360 | CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| 361 | IA32_FEATURE_CONTROL status: locked |
| 362 | CPU:lapic=4, boot_cpu=0 |
| 363 | CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| 364 | Setting up local APIC... |
| 365 | model_x06ax: frequency set to 2527 |
| 366 | apic_id: 0x04 done. |
| 367 | CPU #1 initialized |
| 368 | VMX status: enabled |
| 369 | CPU:lapic=5, boot_cpu=0 |
| 370 | IA32_FEATURE_CONTROL status: locked |
| 371 | Setting up local APIC... |
| 372 | apic_id: 0x05 done. |
| 373 | model_x06ax: frequency set to 2527 |
| 374 | VMX status: enabled |
| 375 | CPU #3 initialized |
| 376 | IA32_FEATURE_CONTROL status: locked |
| 377 | model_x06ax: frequency set to 2527 |
| 378 | CPU #2 initialized |
| 379 | bsp_do_flight_plan done after 6 msecs. |
| 380 | Initializing southbridge SMI... |
| 381 | SMI_STS: |
| 382 | GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO2 GPIO0 |
| 383 | ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| 384 | TCO_STS: |
| 385 | Locking SMM. |
| 386 | CPU_CLUSTER: 0 init finished in 16 msecs |
| 387 | PCI: 00:00.0 init |
| 388 | PCI: 00:00.0 init finished in 0 msecs |
| 389 | PCI: 00:02.0 init |
| 390 | GT Power Management Init (post VBIOS) |
| 391 | PCI: 00:02.0 init finished in 0 msecs |
| 392 | PCI: 00:16.0 init |
| 393 | ME: BIOS path: S3 Wake |
| 394 | PCI: 00:16.0: Disabling device |
| 395 | PCI: 00:16.0 init finished in 0 msecs |
| 396 | PCI: 00:19.0 init |
| 397 | PCI: 00:19.0 init finished in 0 msecs |
| 398 | PCI: 00:1a.0 init |
| 399 | EHCI: Setting up controller.. done. |
| 400 | PCI: 00:1a.0 init finished in 0 msecs |
| 401 | PCI: 00:1b.0 init |
| 402 | Azalia: base = cfd20000 |
| 403 | Azalia: V1CTL disabled. |
| 404 | Azalia: codec_mask = 09 |
| 405 | Azalia: Initializing codec #3 |
| 406 | Azalia: codec viddid: 80862804 |
| 407 | Azalia: verb_size: 16 |
| 408 | Azalia: verb loaded. |
| 409 | Azalia: Initializing codec #0 |
| 410 | Azalia: codec viddid: 14f15069 |
| 411 | Azalia: verb_size: 44 |
| 412 | Azalia: verb loaded. |
| 413 | PCI: 00:1b.0 init finished in 4 msecs |
| 414 | PCI: 00:1d.0 init |
| 415 | EHCI: Setting up controller.. done. |
| 416 | PCI: 00:1d.0 init finished in 0 msecs |
| 417 | PCI: 00:1e.0 init |
| 418 | PCI init. |
| 419 | PCI: 00:1e.0 init finished in 0 msecs |
| 420 | PCI: 00:1f.0 init |
| 421 | pch: lpc_init |
| 422 | IOAPIC: Initializing IOAPIC at 0xfec00000 |
| 423 | IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| 424 | IOAPIC: ID = 0x01 |
| 425 | Set power off after power failure. |
| 426 | NMI sources disabled. |
| 427 | Mobile 5 PM init |
| 428 | rtc_failed = 0x0 |
| 429 | PCI: 00:1f.0 init finished in 0 msecs |
| 430 | PCI: 00:1f.2 init |
| 431 | SATA: Initializing... |
| 432 | SATA: Controller in AHCI mode. |
| 433 | ABAR: 0xcfd26000 |
| 434 | PCI: 00:1f.2 init finished in 0 msecs |
| 435 | PCI: 00:1f.3 init |
| 436 | PCI: 00:1f.3 init finished in 0 msecs |
| 437 | PCI: 00:1f.6 init |
| 438 | Thermal init start. |
| 439 | Thermal init done. |
| 440 | PCI: 00:1f.6 init finished in 0 msecs |
| 441 | PCI: 04:00.0 init |
| 442 | PCI: 04:00.0 init finished in 0 msecs |
| 443 | PNP: 164e.3 init |
| 444 | PNP: 164e.3 init finished in 0 msecs |
| 445 | PNP: 00ff.2 init |
| 446 | PNP: 00ff.2 init finished in 0 msecs |
| 447 | smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| 448 | I2C: 01:54 init finished in 0 msecs |
| 449 | smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| 450 | I2C: 01:55 init finished in 0 msecs |
| 451 | smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| 452 | I2C: 01:56 init finished in 0 msecs |
| 453 | smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| 454 | I2C: 01:57 init finished in 0 msecs |
| 455 | smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| 456 | Locking EEPROM RFID |
| 457 | init EEPROM done |
| 458 | I2C: 01:5c init finished in 26 msecs |
| 459 | smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| 460 | I2C: 01:5d init finished in 0 msecs |
| 461 | smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| 462 | I2C: 01:5e init finished in 0 msecs |
| 463 | smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| 464 | I2C: 01:5f init finished in 0 msecs |
| 465 | Devices initialized |
| 466 | BS: BS_DEV_INIT run times (exec / console): 49 / 0 ms |
| 467 | Finalize devices... |
| 468 | PCI: 00:1f.0 final |
| 469 | Devices finalized |
| 470 | Trying to find the wakeup vector... |
| 471 | Looking on 0x000f6750 for valid checksum |
| 472 | Checksum 1 passed |
| 473 | Checksum 2 passed all OK |
| 474 | RSDP found at 0x000f6750 |
| 475 | RSDT found at 0xbf74f030 ends at 0xbf74f06c |
| 476 | FADT found at 0xbf752d80 |
| 477 | FACS found at 0xbf74f240 |
| 478 | OS waking vector is 0x0009a1d0 |
| 479 | Restore GNVS pointer to 0xbf74e000 |
| 480 | |