Paul Menzel | 2628571 | 2017-04-17 10:57:51 +0200 | [diff] [blame] | 1 | CPU: ID 0x6fd, Processor Type 0x0, Family 0x6, Model 0xf, Stepping 0xd |
| 2 | Northbridge: 8086:2770 (945P) |
| 3 | Southbridge: 8086:27b8 (ICH7) |
| 4 | IGD: 8086:2772 (unknown) |
| 5 | |
| 6 | ===================== SHARED MSRs (All Cores) ===================== |
| 7 | MSR 0x00000017 = 0x00000000:0x8B008A27 (IA32_PLATFORM_ID) |
| 8 | MSR 0x0000002A = 0x00000000:0x42880000 (EBL_CR_POWERON) |
| 9 | MSR 0x0000003F = 0x00000000:0x000000EA (IA32_TEMPERATURE_OFFSET) |
| 10 | MSR 0x000000A8 = 0x00000000:0x0000061D (EMTTM_CR_TABLE0) |
| 11 | MSR 0x000000A9 = 0x00000000:0x0000061D (EMTTM_CR_TABLE1) |
| 12 | MSR 0x000000AA = 0x00000000:0x0000061D (EMTTM_CR_TABLE2) |
| 13 | MSR 0x000000AB = 0x00000000:0x0000061D (EMTTM_CR_TABLE3) |
| 14 | MSR 0x000000AC = 0x00000000:0x0000061D (EMTTM_CR_TABLE4) |
| 15 | MSR 0x000000AD = 0x00000000:0x0000061D (EMTTM_CR_TABLE5) |
| 16 | MSR 0x000000CD = 0x00000000:0x00000802 (FSB_CLOCK_STS) |
| 17 | MSR 0x000000E2 = 0x00000000:0x00263A04 (PMG_CST_CONFIG_CONTROL) |
| 18 | MSR 0x000000E3 = 0x00000000:0x00000000 (PMG_IO_BASE_ADDR) |
| 19 | MSR 0x000000E4 = 0x00000000:0x00000000 (PMG_IO_CAPTURE_ADDR) |
| 20 | MSR 0x000000EE = 0xA8000000:0xC37D4700 (EXT_CONFIG) |
| 21 | MSR 0x0000011E = 0x00000000:0xBE702105 (BBL_CR_CTL3) |
| 22 | MSR 0x00000194 = 0x00000000:0x00000000 (CLOCK_FLEX_MAX) |
| 23 | MSR 0x00000198 = 0x0A270A27:0x06000A27 (IA32_PERF_STATUS) |
| 24 | MSR 0x000001A0 = 0x00000040:0x62972489 (IA32_MISC_ENABLES) |
| 25 | MSR 0x000001AA = 0x00000000:0x7E7F042F (PIC_SENS_CFG) |
| 26 | MSR 0x00000400 = 0x00000000:0x42880000 (IA32_MC0_CTL) |
| 27 | MSR 0x00000401 = 0x10000000:0x00000000 (IA32_MC0_STATUS) |
| 28 | MSR 0x00000402 = 0x00000000:0xFEE01000 (IA32_MC0_ADDR) |
| 29 | MSR 0x0000040C = 0x00000000:0x00000001 (IA32_MC4_CTL) |
| 30 | MSR 0x0000040D = 0x00200000:0x00000000 (IA32_MC4_STATUS) |
| 31 | MSR 0x0000040E = 0x000000B7:0xF0A02660 (IA32_MC4_ADDR) |
| 32 | |
| 33 | ====================== UNIQUE MSRs (core 0) ====================== |
| 34 | MSR 0x00000010 = 0x00000207:0x8E44C914 (IA32_TIME_STAMP_COUNTER) |
| 35 | MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE) |
| 36 | MSR 0x0000003A = 0x00000000:0x00000001 (IA32_FEATURE_CONTROL) |
| 37 | MSR 0x0000008B = 0x000000A1:0x00000000 (IA32_BIOS_SIGN_ID) |
| 38 | MSR 0x000000E1 = 0x00000000:0xF0F00000 (SMM_CST_MISC_INFO) |
| 39 | MSR 0x000000E7 = 0x000000A0:0x920F94F6 (IA32_MPERF) |
| 40 | MSR 0x000000E8 = 0x000000A5:0x74404586 (IA32_APERF) |
| 41 | MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP) |
| 42 | MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| 43 | MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| 44 | MSR 0x00000199 = 0x00000000:0x00000A27 (IA32_PERF_CONTROL) |
| 45 | MSR 0x0000019A = 0x00000000:0x00000002 (IA32_THERM_CTL) |
| 46 | MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| 47 | MSR 0x0000019C = 0x00000000:0x88220000 (IA32_THERM_STATUS) |
| 48 | MSR 0x0000019D = 0x00000000:0x0000061D (MSR_THERM2_CTL) |
| 49 | MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL) |
| 50 | MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0) |
| 51 | MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0) |
| 52 | MSR 0x00000202 = 0x00000000:0x7F800000 (IA32_MTRR_PHYSBASE1) |
| 53 | MSR 0x00000203 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK1) |
| 54 | MSR 0x00000204 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE2) |
| 55 | MSR 0x00000205 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK2) |
| 56 | MSR 0x00000206 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE3) |
| 57 | MSR 0x00000207 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK3) |
| 58 | MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| 59 | MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| 60 | MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| 61 | MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| 62 | MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| 63 | MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| 64 | MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| 65 | MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| 66 | MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| 67 | MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| 68 | MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| 69 | MSR 0x00000268 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C0000) |
| 70 | MSR 0x00000269 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C8000) |
| 71 | MSR 0x0000026A = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D0000) |
| 72 | MSR 0x0000026B = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D8000) |
| 73 | MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000) |
| 74 | MSR 0x0000026D = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E8000) |
| 75 | MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000) |
| 76 | MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000) |
| 77 | MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| 78 | |
| 79 | ====================== UNIQUE MSRs (core 1) ====================== |
| 80 | MSR 0x00000010 = 0x00000207:0x8E495F92 (IA32_TIME_STAMP_COUNTER) |
| 81 | MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE) |
| 82 | MSR 0x0000003A = 0x00000000:0x00000001 (IA32_FEATURE_CONTROL) |
| 83 | MSR 0x0000008B = 0x000000A1:0x00000000 (IA32_BIOS_SIGN_ID) |
| 84 | MSR 0x000000E1 = 0x00000000:0xF0F00000 (SMM_CST_MISC_INFO) |
| 85 | MSR 0x000000E7 = 0x000000A1:0x782C5082 (IA32_MPERF) |
| 86 | MSR 0x000000E8 = 0x000000A0:0x3A1FAAD8 (IA32_APERF) |
| 87 | MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP) |
| 88 | MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| 89 | MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| 90 | MSR 0x00000199 = 0x00000000:0x00000A27 (IA32_PERF_CONTROL) |
| 91 | MSR 0x0000019A = 0x00000000:0x00000002 (IA32_THERM_CTL) |
| 92 | MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| 93 | MSR 0x0000019C = 0x00000000:0x88220000 (IA32_THERM_STATUS) |
| 94 | MSR 0x0000019D = 0x00000000:0x0000061D (MSR_THERM2_CTL) |
| 95 | MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL) |
| 96 | MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0) |
| 97 | MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0) |
| 98 | MSR 0x00000202 = 0x00000000:0x7F800000 (IA32_MTRR_PHYSBASE1) |
| 99 | MSR 0x00000203 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK1) |
| 100 | MSR 0x00000204 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE2) |
| 101 | MSR 0x00000205 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK2) |
| 102 | MSR 0x00000206 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE3) |
| 103 | MSR 0x00000207 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK3) |
| 104 | MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| 105 | MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| 106 | MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| 107 | MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| 108 | MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| 109 | MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| 110 | MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| 111 | MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| 112 | MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| 113 | MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| 114 | MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| 115 | MSR 0x00000268 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C0000) |
| 116 | MSR 0x00000269 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C8000) |
| 117 | MSR 0x0000026A = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D0000) |
| 118 | MSR 0x0000026B = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D8000) |
| 119 | MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000) |
| 120 | MSR 0x0000026D = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E8000) |
| 121 | MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000) |
| 122 | MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000) |
| 123 | MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| 124 | |
| 125 | |