lenovo/x230/4.5-1437-ge912d933df/2017-03-29T08_02_58Z/coreboot_console.txt

对不起，请重试。
对不起，请重试。


coreboot-4.5-1437-ge912d933df Wed Mar 29 08:02:58 UTC 2017 romstage starting...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
Back from sandybridge_early_initialization()
POST: 0x38
SMBus controller enabled.
POST: 0x39
POST: 0x3a
CPU id(306a9): Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz
AES supported, TXT supported, VT supported
PCH type: QM77, device id: 1e55, rev id 4
Intel ME early init
Intel ME firmware is ready
ME: Requested 32MB UMA
Starting native Platform init
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'mrc.cache'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS:  Unmatched 'cmos_layout.bin' at 21e00
CBFS: Checking offset 22600
CBFS: File @ offset 22600 size 660
CBFS:  Unmatched 'payload_config' at 22600
CBFS: Checking offset 22cc0
CBFS: File @ offset 22cc0 size ea
CBFS:  Unmatched 'payload_revision' at 22cc0
CBFS: Checking offset 22e00
CBFS: File @ offset 22e00 size 8
CBFS:  Unmatched 'etc/ps2-keyboard-spinup' at 22e00
CBFS: Checking offset 22e40
CBFS: File @ offset 22e40 size f
CBFS:  Unmatched 'bootorder' at 22e40
CBFS: Checking offset 22ec0
CBFS: File @ offset 22ec0 size 8
CBFS:  Unmatched 'etc/show-boot-menu' at 22ec0
CBFS: Checking o

*** Log truncated, 371652 characters dropped. ***

Relocate MRC DATA from fefff9fc to bffdc000 (1440 bytes)
CBMEM entry for DIMM info: 0xbfffe880
POST: 0x3b
POST: 0x3c
POST: 0x3d
TPM initialization.
TPM: Init
Found TPM ST33ZP24 by ST Microelectronics
TPM: Open
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: OK.
POST: 0x3f
Smashed stack detected in romstage!
Smashed stack detected in romstage!
Smashed stack detected in romstage!
Smashed stack detected in romstage!
MTRR Range: Start=ff000000 End=0 (Size 1000000)
MTRR Range: Start=0 End=1000000 (Size 1000000)
MTRR Range: Start=bf800000 End=c0000000 (Size 800000)
MTRR Range: Start=c0000000 End=c0800000 (Size 800000)
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS:  Unmatched 'cmos_layout.bin' at 21e00
CBFS: Checking offset 22600
CBFS: File @ offset 22600 size 660
CBFS:  Unmatched 'payload_config' at 22600
CBFS: Checking offset 22cc0
CBFS: File @ offset 22cc0 size ea
CBFS:  Unmatched 'payload_revision' at 22cc0
CBFS: Checking offset 22e00
CBFS: File @ offset 22e00 size 8
CBFS:  Unmatched 'etc/ps2-keyboard-spinup' at 22e00
CBFS: Checking offset 22e40
CBFS: File @ offset 22e40 size f
CBFS:  Unmatched 'bootorder' at 22e40
CBFS: Checking offset 22ec0
CBFS: File @ offset 22ec0 size 8
CBFS:  Unmatched 'etc/show-boot-menu' at 22ec0
CBFS: Checking offset 22f00
CBFS: File @ offset 22f00 size 11f2
CBFS:  Unmatched 'grub.cfg' at 22f00
CBFS: Checking offset 24140
CBFS: File @ offset 24140 size d58
CBFS:  Unmatched '' at 24140
CBFS: Checking offset 24ec0
CBFS: File @ offset 24ec0 size 10000
CBFS:  Unmatched 'mrc.cache' at 24ec0
CBFS: Checking offset 34f00
CBFS: File @ offset 34f00 size 1748d
CBFS: Found @ offset 34f00 size 1748d
Decompressing stage fallback/ramstage @ 0xbff92fc0 (277392 bytes)
Loading module at bff93000 with entry bff93000. filesize: 0x32eb0 memsize: 0x43b50
Processing 3195 relocs. Offset value of 0xbfe93000


coreboot-4.5-1437-ge912d933df Wed Mar 29 08:02:58 UTC 2017 ramstage starting...
POST: 0x39
POST: 0x80
Normal boot.
POST: 0x70
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
POST: 0x71
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 0
PCI: 00:02.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 0
PCI: 00:1c.4: enabled 0
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
  APIC: acac: enabled 0
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 0
  PCI: 00:02.0: enabled 1
  PCI: 00:14.0: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:16.1: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:16.3: enabled 0
  PCI: 00:19.0: enabled 1
  PCI: 00:1a.0: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 1
   PCI: 00:00.0: enabled 1
  PCI: 00:1c.1: enabled 1
  PCI: 00:1c.2: enabled 1
  PCI: 00:1c.3: enabled 0
  PCI: 00:1c.4: enabled 0
  PCI: 00:1c.5: enabled 0
  PCI: 00:1c.6: enabled 0
  PCI: 00:1c.7: enabled 0
  PCI: 00:1d.0: enabled 1
  PCI: 00:1e.0: enabled 0
  PCI: 00:1f.0: enabled 1
   PNP: 00ff.1: enabled 1
   PNP: 0c31.0: enabled 1
   PNP: 00ff.2: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
   I2C: 00:54: enabled 1
   I2C: 00:55: enabled 1
   I2C: 00:56: enabled 1
   I2C: 00:57: enabled 1
   I2C: 00:5c: enabled 1
   I2C: 00:5d: enabled 1
   I2C: 00:5e: enabled 1
   I2C: 00:5f: enabled 1
  PCI: 00:1f.5: enabled 0
  PCI: 00:1f.6: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [8086/0154] ops
PCI: 00:00.0 [8086/0154] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0151] disabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0166] enabled
memalign Enter, boundary 8, size 152, free_mem_ptr bffd2b50
memalign bffd2b50
PCI: 00:04.0 [8086/0153] enabled
PCI: 00:14.0 [8086/0000] ops
PCI: 00:14.0 [8086/1e31] enabled
PCI: 00:16.0 [8086/1e3a] ops
PCI: 00:16.0 [8086/1e3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.2: Disabling device
PCI: 00:16.3: Disabling device
PCI: 00:19.0 [8086/1502] enabled
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1e2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1e20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0 [8086/0000] bus ops
PCI: 00:1c.0 [8086/1e10] enabled
PCI: 00:1c.1 [8086/0000] bus ops
PCI: 00:1c.1 [8086/1e12] enabled
PCI: 00:1c.2 [8086/0000] bus ops
PCI: 00:1c.2 [8086/1e14] enabled
PCI: 00:1c.3: Disabling device
PCI: 00:1c.4: Disabling device
PCI: 00:1c.4: check set enabled
PCI: 00:1c.5: Disabling device
PCI: 00:1c.6: Disabling device
PCI: 00:1c.7: Disabling device
PCH: RPFN 0x76543210 -> 0xfedcb210
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1e26] enabled
PCI: 00:1e.0: Disabling device
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1e55] enabled
PCI: 00:1f.2 [8086/0000] ops
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
PCI: 00:1f.2 [8086/1e01] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1e22] enabled
PCI: 00:1f.5: Disabling device
PCI: Static device PCI: 00:1f.6 not found, disabling it.
POST: 0x25
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [1180/0000] ops
PCI: 01:00.0 [1180/e823] enabled
POST: 0x25
POST: 0x55
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.0 took 234 usecs
PCI: 00:1c.1 scanning...
do_pci_scan_bridge for PCI: 00:1c.1
memalign Enter, boundary 8, size 36, free_mem_ptr bffd2be8
memalign bffd2be8
PCI: pci_scan_bus for bus 02
POST: 0x24
memalign Enter, boundary 8, size 152, free_mem_ptr bffd2c0c
memalign bffd2c10
PCI: 02:00.0 [168c/0030] enabled
POST: 0x25
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpointASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.1 took 208 usecs
PCI: 00:1c.2 scanning...
do_pci_scan_bridge for PCI: 00:1c.2
memalign Enter, boundary 8, size 36, free_mem_ptr bffd2ca8
memalign bffd2ca8
PCI: pci_scan_bus for bus 03
POST: 0x24
POST: 0x25
POST: 0x55
memalign Enter, boundary 8, size 152, free_mem_ptr bffd2ccc
memalign bffd2cd0
scan_bus: scanning of bus PCI: 00:1c.2 took 51 usecs
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
memalign Enter, boundary 8, size 2560, free_mem_ptr bffd2d68
memalign bffd2d68
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
PNP: 00ff.1 enabled
PNP: 0c31.0 enabled
recv_ec_data: 0x47
recv_ec_data: 0x32
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x35
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x16
recv_ec_data: 0x03
recv_ec_data: 0x40
recv_ec_data: 0x11
EC Firmware ID G2HT35WW-3.22, Version 4.01B
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0x00
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0x00
recv_ec_data: 0x90
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0x20
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0x30
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0x00
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0xa6
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
recv_ec_data: 0xa6
recv_ec_data: 0x70
PNP: 00ff.2 enabled
scan_lpc_bus for PCI: 00:1f.0 done
scan_bus: scanning of bus PCI: 00:1f.0 took 4805 usecs
PCI: 00:1f.3 scanning...
scan_generic_bus for PCI: 00:1f.3
bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_generic_bus for PCI: 00:1f.3 done
scan_bus: scanning of bus PCI: 00:1f.3 took 18 usecs
POST: 0x55
scan_bus: scanning of bus DOMAIN: 0000 took 5782 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 5787 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 5885 exit 0
POST: 0x73
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
PCI: 00:1a.0 EHCI BAR hook registered
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.1 read_resources bus 2 link: 0
PCI: 00:1c.1 read_resources bus 2 link: 0 done
PCI: 00:1c.2 read_resources bus 3 link: 0
PCI: 00:1c.2 read_resources bus 3 link: 0 done
More than one caller of pci_ehci_read_resources from PCI: 00:1d.0
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI: 00:1f.3 read_resources bus 1 link: 0
PCI: 00:1f.3 read_resources bus 1 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
   PCI: 00:01.0
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
   PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
   PCI: 00:04.0
   PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.0
   PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
   PCI: 00:16.1
   PCI: 00:16.2
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
   PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
   PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:1c.1 child on link 0 PCI: 02:00.0
   PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
    PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
   PCI: 00:1c.2Unknown device path type: 0
 child on link 0 
   PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
Unknown device path type: 0
    
Unknown device path type: 0
     resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10
Unknown device path type: 0
     resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14
Unknown device path type: 0
     resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18
   PCI: 00:1c.3
   PCI: 00:1c.4
   PCI: 00:1c.5
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 00ff.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
   PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
    PNP: 00ff.1
    PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
    PNP: 0c31.0
    PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
    PNP: 00ff.2
    PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
    PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
    PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
    PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3 child on link 0 I2C: 01:54
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
    I2C: 01:54
    I2C: 01:55
    I2C: 01:56
    I2C: 01:57
    I2C: 01:5c
    I2C: 01:5d
    I2C: 01:5e
    I2C: 01:5f
   PCI: 00:1f.5
   PCI: 00:1f.6
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
Unknown device path type: 0
 18 *  [0x0 - 0xfff] io
PCI: 00:1c.2 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.2 1c *  [0x0 - 0xfff] io
PCI: 00:02.0 20 *  [0x1000 - 0x103f] io
PCI: 00:19.0 18 *  [0x1040 - 0x105f] io
PCI: 00:1f.2 20 *  [0x1060 - 0x107f] io
PCI: 00:1f.2 10 *  [0x1080 - 0x1087] io
PCI: 00:1f.2 18 *  [0x1088 - 0x108f] io
PCI: 00:1f.2 14 *  [0x1090 - 0x1093] io
PCI: 00:1f.2 1c *  [0x1094 - 0x1097] io
DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0xff] mem
PCI: 00:1c.0 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0x1ffff] mem
PCI: 02:00.0 30 *  [0x20000 - 0x2ffff] mem
PCI: 00:1c.1 mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
Unknown device path type: 0
 14 *  [0x0 - 0x7fffff] prefmem
PCI: 00:1c.2 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
Unknown device path type: 0
 10 *  [0x0 - 0x7fffff] mem
PCI: 00:1c.2 mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 *  [0x0 - 0xfffffff] prefmem
PCI: 00:1c.2 24 *  [0x10000000 - 0x107fffff] prefmem
PCI: 00:1c.2 20 *  [0x10800000 - 0x10ffffff] mem
PCI: 00:02.0 10 *  [0x11000000 - 0x113fffff] mem
PCI: 00:1c.0 20 *  [0x11400000 - 0x114fffff] mem
PCI: 00:1c.1 20 *  [0x11500000 - 0x115fffff] mem
PCI: 00:19.0 10 *  [0x11600000 - 0x1161ffff] mem
PCI: 00:14.0 10 *  [0x11620000 - 0x1162ffff] mem
PCI: 00:04.0 10 *  [0x11630000 - 0x11637fff] mem
PCI: 00:1b.0 10 *  [0x11638000 - 0x1163bfff] mem
PCI: 00:19.0 14 *  [0x1163c000 - 0x1163cfff] mem
PCI: 00:1f.2 24 *  [0x1163d000 - 0x1163d7ff] mem
PCI: 00:1a.0 10 *  [0x1163e000 - 0x1163e3ff] mem
PCI: 00:1d.0 10 *  [0x1163f000 - 0x1163f3ff] mem
PCI: 00:1f.3 10 *  [0x11640000 - 0x116400ff] mem
PCI: 00:16.0 10 *  [0x11641000 - 0x1164100f] mem
DOMAIN: 0000 mem: base: 11641010 size: 11641010 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 60 base f8000000 limit fbffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
skipping PNP: 00ff.2@60 fixed resource, size=0!
skipping PNP: 00ff.2@62 fixed resource, size=0!
skipping PNP: 00ff.2@64 fixed resource, size=0!
skipping PNP: 00ff.2@66 fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff
Setting resources...
DOMAIN: 0000 io: base:167c size:1098 align:12 gran:0 limit:ffff
PCI: 00:1c.2 1c *  [0x2000 - 0x2fff] io
PCI: 00:02.0 20 *  [0x3000 - 0x303f] io
PCI: 00:19.0 18 *  [0x3040 - 0x305f] io
PCI: 00:1f.2 20 *  [0x3060 - 0x307f] io
PCI: 00:1f.2 10 *  [0x3080 - 0x3087] io
PCI: 00:1f.2 18 *  [0x3088 - 0x308f] io
PCI: 00:1f.2 14 *  [0x3090 - 0x3093] io
PCI: 00:1f.2 1c *  [0x3094 - 0x3097] io
DOMAIN: 0000 io: next_base: 3098 size: 1098 align: 12 gran: 0 done
PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.2 io: base:2000 size:1000 align:12 gran:12 limit:2fff
Unknown device path type: 0
 18 *  [0x2000 - 0x2fff] io
PCI: 00:1c.2 io: next_base: 3000 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e0000000 size:11641010 align:28 gran:0 limit:f7ffffff
PCI: 00:02.0 18 *  [0xe0000000 - 0xefffffff] prefmem
PCI: 00:1c.2 24 *  [0xf0000000 - 0xf07fffff] prefmem
PCI: 00:1c.2 20 *  [0xf0800000 - 0xf0ffffff] mem
PCI: 00:02.0 10 *  [0xf1000000 - 0xf13fffff] mem
PCI: 00:1c.0 20 *  [0xf1400000 - 0xf14fffff] mem
PCI: 00:1c.1 20 *  [0xf1500000 - 0xf15fffff] mem
PCI: 00:19.0 10 *  [0xf1600000 - 0xf161ffff] mem
PCI: 00:14.0 10 *  [0xf1620000 - 0xf162ffff] mem
PCI: 00:04.0 10 *  [0xf1630000 - 0xf1637fff] mem
PCI: 00:1b.0 10 *  [0xf1638000 - 0xf163bfff] mem
PCI: 00:19.0 14 *  [0xf163c000 - 0xf163cfff] mem
PCI: 00:1f.2 24 *  [0xf163d000 - 0xf163d7ff] mem
PCI: 00:1a.0 10 *  [0xf163e000 - 0xf163e3ff] mem
PCI: 00:1d.0 10 *  [0xf163f000 - 0xf163f3ff] mem
PCI: 00:1f.3 10 *  [0xf1640000 - 0xf16400ff] mem
PCI: 00:16.0 10 *  [0xf1641000 - 0xf164100f] mem
DOMAIN: 0000 mem: next_base: f1641010 size: 11641010 align: 28 gran: 0 done
PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 mem: base:f1400000 size:100000 align:20 gran:20 limit:f14fffff
PCI: 01:00.0 10 *  [0xf1400000 - 0xf14000ff] mem
PCI: 00:1c.0 mem: next_base: f1400100 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.1 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.1 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 mem: base:f1500000 size:100000 align:20 gran:20 limit:f15fffff
PCI: 02:00.0 10 *  [0xf1500000 - 0xf151ffff] mem
PCI: 02:00.0 30 *  [0xf1520000 - 0xf152ffff] mem
PCI: 00:1c.1 mem: next_base: f1530000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.2 prefmem: base:f0000000 size:800000 align:22 gran:20 limit:f07fffff
Unknown device path type: 0
 14 *  [0xf0000000 - 0xf07fffff] prefmem
PCI: 00:1c.2 prefmem: next_base: f0800000 size: 800000 align: 22 gran: 20 done
PCI: 00:1c.2 mem: base:f0800000 size:800000 align:22 gran:20 limit:f0ffffff
Unknown device path type: 0
 10 *  [0xf0800000 - 0xf0ffffff] mem
PCI: 00:1c.2 mem: next_base: f1000000 size: 800000 align: 22 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x42f600000 TOLUD 0xcea00000 TOM 0x400000000
MEBASE 0x3fe000000
IGD decoded, subtracting 224M UMA and 2M GTT
TSEG base 0xc0000000 size 8M
Available memory below 4GB: 3072M
Available memory above 4GB: 13046M
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:02.0 10 <- [0x00f1000000 - 0x00f13fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x00f1630000 - 0x00f1637fff] size 0x00008000 gran 0x0f mem64
PCI: 00:14.0 10 <- [0x00f1620000 - 0x00f162ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:16.0 10 <- [0x00f1641000 - 0x00f164100f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00f1600000 - 0x00f161ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00f163c000 - 0x00f163cfff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 EHCI Debug Port hook triggered
PCI: 00:1a.0 10 <- [0x00f163e000 - 0x00f163e3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1a.0 10 <- [0x00f163e000 - 0x00f163e3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1a.0 EHCI Debug Port relocated
PCI: 00:1b.0 10 <- [0x00f1638000 - 0x00f163bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00f1400000 - 0x00f14fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f1400000 - 0x00f14000ff] size 0x00000100 gran 0x08 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x00f1500000 - 0x00f15fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00f1500000 - 0x00f151ffff] size 0x00020000 gran 0x11 mem64
PCI: 02:00.0 30 <- [0x00f1520000 - 0x00f152ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:1c.2 24 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x14 bus 03 prefmem
PCI: 00:1c.2 20 <- [0x00f0800000 - 0x00f0ffffff] size 0x00800000 gran 0x14 bus 03 mem
PCI: 00:1c.2 assign_resources, bus 3 link: 0
Unknown device path type: 0
 missing set_resources
PCI: 00:1c.2 assign_resources, bus 3 link: 0
PCI: 00:1d.0 10 <- [0x00f163f000 - 0x00f163f3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00f163d000 - 0x00f163d7ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00f1640000 - 0x00f16400ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.3 assign_resources, bus 1 link: 0
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 167c size 1098 align 12 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base e0000000 size 11641010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
  DOMAIN: 0000 resource base 100000000 size 32f600000 align 0 gran 0 limit 0 flags e0004200 index 5
  DOMAIN: 0000 resource base c0000000 size ea00000 align 0 gran 0 limit 0 flags f0000200 index 6
  DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
  DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8
  DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
  DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
   PCI: 00:00.0
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
   PCI: 00:01.0
   PCI: 00:02.0
   PCI: 00:02.0 resource base f1000000 size 400000 align 22 gran 22 limit f13fffff flags 60000201 index 10
   PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
   PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20
   PCI: 00:04.0
   PCI: 00:04.0 resource base f1630000 size 8000 align 15 gran 15 limit f1637fff flags 60000201 index 10
   PCI: 00:14.0
   PCI: 00:14.0 resource base f1620000 size 10000 align 16 gran 16 limit f162ffff flags 60000201 index 10
   PCI: 00:16.0
   PCI: 00:16.0 resource base f1641000 size 10 align 12 gran 4 limit f164100f flags 60000201 index 10
   PCI: 00:16.1
   PCI: 00:16.2
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:19.0 resource base f1600000 size 20000 align 17 gran 17 limit f161ffff flags 60000200 index 10
   PCI: 00:19.0 resource base f163c000 size 1000 align 12 gran 12 limit f163cfff flags 60000200 index 14
   PCI: 00:19.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 18
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base f163e000 size 400 align 12 gran 10 limit f163e3ff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base f1638000 size 4000 align 14 gran 14 limit f163bfff flags 60000201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base f1400000 size 100000 align 20 gran 20 limit f14fffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base f1400000 size 100 align 12 gran 8 limit f14000ff flags 60000200 index 10
   PCI: 00:1c.1 child on link 0 PCI: 02:00.0
   PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.1 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
   PCI: 00:1c.1 resource base f1500000 size 100000 align 20 gran 20 limit f15fffff flags 60080202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base f1500000 size 20000 align 17 gran 17 limit f151ffff flags 60000201 index 10
    PCI: 02:00.0 resource base f1520000 size 10000 align 16 gran 16 limit f152ffff flags 60002200 index 30
   PCI: 00:1c.2Unknown device path type: 0
 child on link 0 
   PCI: 00:1c.2 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
   PCI: 00:1c.2 resource base f0000000 size 800000 align 22 gran 20 limit f07fffff flags 60081202 index 24
   PCI: 00:1c.2 resource base f0800000 size 800000 align 22 gran 20 limit f0ffffff flags 60080202 index 20
Unknown device path type: 0
    
Unknown device path type: 0
     resource base f0800000 size 800000 align 22 gran 22 limit f0ffffff flags 40000200 index 10
Unknown device path type: 0
     resource base f0000000 size 800000 align 22 gran 22 limit f07fffff flags 40001200 index 14
Unknown device path type: 0
     resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18
   PCI: 00:1c.3
   PCI: 00:1c.4
   PCI: 00:1c.5
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base f163f000 size 400 align 12 gran 10 limit f163f3ff flags 60000200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 00ff.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
   PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
    PNP: 00ff.1
    PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
    PNP: 0c31.0
    PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
    PNP: 00ff.2
    PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
    PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
    PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
    PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10
   PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14
   PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18
   PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c
   PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20
   PCI: 00:1f.2 resource base f163d000 size 800 align 12 gran 11 limit f163d7ff flags 60000200 index 24
   PCI: 00:1f.3 child on link 0 I2C: 01:54
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base f1640000 size 100 align 12 gran 8 limit f16400ff flags 60000201 index 10
    I2C: 01:54
    I2C: 01:55
    I2C: 01:56
    I2C: 01:57
    I2C: 01:5c
    I2C: 01:5d
    I2C: 01:5e
    I2C: 01:5f
   PCI: 00:1f.5
   PCI: 00:1f.6
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 2202 exit 0
POST: 0x74
Enabling resources...
PCI: 00:00.0 subsystem <- 17aa/21fa
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 17aa/21fa
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 cmd <- 02
PCI: 00:14.0 subsystem <- 17aa/21fa
PCI: 00:14.0 cmd <- 102
PCI: 00:16.0 subsystem <- 17aa/21fa
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 17aa/21f3
PCI: 00:19.0 cmd <- 103
PCI: 00:1a.0 subsystem <- 17aa/21fa
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 17aa/21fa
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 17aa/21fa
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 subsystem <- 17aa/21fa
PCI: 00:1c.1 cmd <- 106
PCI: 00:1c.2 bridge ctrl <- 0003
PCI: 00:1c.2 subsystem <- 17aa/21fa
PCI: 00:1c.2 cmd <- 107
PCI: 00:1d.0 subsystem <- 17aa/21fa
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 17aa/21fa
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 17aa/21fa
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 17aa/21fa
PCI: 00:1f.3 cmd <- 103
PCI: 01:00.0 subsystem <- 17aa/21fa
PCI: 01:00.0 cmd <- 06
PCI: 02:00.0 cmd <- 02
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 124 exit 0
read 6000 from 07e4
wrote 00000004 to 0890
read 03040103 from 0894
read 00000000 from 0880
wrote 00000000 to 0880
POST: 0x75
Initializing devices...
Root Device init ...
Root Device init finished in 0 usecs
POST: 0x75
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
Setting up SMI for CPU
Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x00038000
Adjusting 00038002: 0x00000024 -> 0x00038024
Adjusting 0003801d: 0x0000003c -> 0x0003803c
Adjusting 00038026: 0x00000024 -> 0x00038024
Adjusting 00038054: 0x000000d8 -> 0x000380d8
Adjusting 00038066: 0x00000160 -> 0x00038160
Adjusting 0003806d: 0x000000c0 -> 0x000380c0
Adjusting 00038075: 0x000000c4 -> 0x000380c4
Adjusting 0003807e: 0x000000d0 -> 0x000380d0
Adjusting 00038085: 0x000000cc -> 0x000380cc
Adjusting 0003808b: 0x000000c8 -> 0x000380c8
SMM Module: stub loaded at 00038000. Will call bffadcd5(bffd2ac0)
Installing SMM handler to 0xc0000000
Loading module at c0010000 with entry c0011589. filesize: 0x3aa0 memsize: 0x7ac0
Processing 229 relocs. Offset value of 0xc0010000
Adjusting c0010592: 0x00002fc4 -> 0xc0012fc4
Adjusting c00105b1: 0x00002fc4 -> 0xc0012fc4
Adjusting c001066e: 0x000032a5 -> 0xc00132a5
Adjusting c0010685: 0x00002fc4 -> 0xc0012fc4
Adjusting c00106f6: 0x00002fd4 -> 0xc0012fd4
Adjusting c0010729: 0x00002fef -> 0xc0012fef
Adjusting c001075e: 0x00002ff8 -> 0xc0012ff8
Adjusting c00107b5: 0x00003019 -> 0xc0013019
Adjusting c001082c: 0x0000302e -> 0xc001302e
Adjusting c0010863: 0x0000304c -> 0xc001304c
Adjusting c0010887: 0x0000306d -> 0xc001306d
Adjusting c00108a0: 0x00003090 -> 0xc0013090
Adjusting c0010a7a: 0x00003a80 -> 0xc0013a80
Adjusting c0010a89: 0x000030bc -> 0xc00130bc
Adjusting c0010a8e: 0x00003a80 -> 0xc0013a80
Adjusting c0010a94: 0x00003a80 -> 0xc0013a80
Adjusting c0010aa9: 0x000032e0 -> 0xc00132e0
Adjusting c0010aae: 0x000032fd -> 0xc00132fd
Adjusting c0010ab3: 0x00003300 -> 0xc0013300
Adjusting c0010ab8: 0x000030c8 -> 0xc00130c8
Adjusting c0010aeb: 0x00003a84 -> 0xc0013a84
Adjusting c0010b01: 0x00000ac7 -> 0xc0010ac7
Adjusting c0010b15: 0x00003a84 -> 0xc0013a84
Adjusting c0010b27: 0x00003a84 -> 0xc0013a84
Adjusting c0010b3a: 0x00003111 -> 0xc0013111
Adjusting c0010b43: 0x000030ec -> 0xc00130ec
Adjusting c001106f: 0x00003136 -> 0xc0013136
Adjusting c00112bb: 0x00003aa0 -> 0xc0013aa0
Adjusting c00112d5: 0x00003aa8 -> 0xc0013aa8
Adjusting c00112e0: 0x00003315 -> 0xc0013315
Adjusting c00112fa: 0x00003aa8 -> 0xc0013aa8
Adjusting c0011313: 0x0000313d -> 0xc001313d
Adjusting c0011340: 0x00003156 -> 0xc0013156
Adjusting c0011369: 0x00003a98 -> 0xc0013a98
Adjusting c0011383: 0x00003a00 -> 0xc0013a00
Adjusting c0011397: 0x00003905 -> 0xc0013905
Adjusting c00113b6: 0x00003936 -> 0xc0013936
Adjusting c00113cd: 0x00003940 -> 0xc0013940
Adjusting c00113e4: 0x00003945 -> 0xc0013945
Adjusting c00113fb: 0x0000394e -> 0xc001394e
Adjusting c0011412: 0x0000395b -> 0xc001395b
Adjusting c0011429: 0x00003967 -> 0xc0013967
Adjusting c0011440: 0x00003974 -> 0xc0013974
Adjusting c0011457: 0x0000397f -> 0xc001397f
Adjusting c001146e: 0x0000398b -> 0xc001398b
Adjusting c0011485: 0x00003995 -> 0xc0013995
Adjusting c001149c: 0x0000399a -> 0xc001399a
Adjusting c00114b3: 0x000039a2 -> 0xc00139a2
Adjusting c00114ca: 0x000039a9 -> 0xc00139a9
Adjusting c00114e1: 0x000039ae -> 0xc00139ae
Adjusting c00114f8: 0x000039b4 -> 0xc00139b4
Adjusting c001150e: 0x000039b9 -> 0xc00139b9
Adjusting c0011524: 0x000039c4 -> 0xc00139c4
Adjusting c001153a: 0x000039c9 -> 0xc00139c9
Adjusting c0011550: 0x000039d2 -> 0xc00139d2
Adjusting c0011566: 0x000039de -> 0xc00139de
Adjusting c0011577: 0x000032a3 -> 0xc00132a3
Adjusting c0011593: 0x00003aa0 -> 0xc0013aa0
Adjusting c00115a1: 0x00003aa0 -> 0xc0013aa0
Adjusting c00115b2: 0x00003168 -> 0xc0013168
Adjusting c00115c6: 0x00003a88 -> 0xc0013a88
Adjusting c00115d1: 0x00003a88 -> 0xc0013a88
Adjusting c00115e4: 0x00003aa4 -> 0xc0013aa4
Adjusting c00115f0: 0x00003195 -> 0xc0013195
Adjusting c0011600: 0x00003a8c -> 0xc0013a8c
Adjusting c0011609: 0x00003a8c -> 0xc0013a8c
Adjusting c0011626: 0x00003aa4 -> 0xc0013aa4
Adjusting c001162f: 0x00003a88 -> 0xc0013a88
Adjusting c001165f: 0x00003327 -> 0xc0013327
Adjusting c0011737: 0x000031a0 -> 0xc00131a0
Adjusting c001174a: 0x000031b0 -> 0xc00131b0
Adjusting c001178a: 0x000031ef -> 0xc00131ef
Adjusting c001187a: 0x00003a94 -> 0xc0013a94
Adjusting c001189c: 0x0000320e -> 0xc001320e
Adjusting c00118b4: 0x00003210 -> 0xc0013210
Adjusting c00118ce: 0x00003a94 -> 0xc0013a94
Adjusting c00118f9: 0x00003a94 -> 0xc0013a94
Adjusting c001191b: 0x0000320e -> 0xc001320e
Adjusting c0011933: 0x0000323d -> 0xc001323d
Adjusting c001194d: 0x00003a90 -> 0xc0013a90
Adjusting c001196b: 0x00003a94 -> 0xc0013a94
Adjusting c001198a: 0x0000320e -> 0xc001320e
Adjusting c001199d: 0x0000327d -> 0xc001327d
Adjusting c00119b7: 0x00003a90 -> 0xc0013a90
Adjusting c00119ca: 0x00003267 -> 0xc0013267
Adjusting c0011a90: 0x00003a94 -> 0xc0013a94
Adjusting c0011a95: 0x00003a90 -> 0xc0013a90
Adjusting c0011aa8: 0x00002fb0 -> 0xc0012fb0
Adjusting c0011ad2: 0x00002fa8 -> 0xc0012fa8
Adjusting c0011ad7: 0x000032ba -> 0xc00132ba
Adjusting c0011e20: 0x00003aac -> 0xc0013aac
Adjusting c0011e4f: 0x00003ab0 -> 0xc0013ab0
Adjusting c0011e62: 0x00003aac -> 0xc0013aac
Adjusting c0011e85: 0x00003ab0 -> 0xc0013ab0
Adjusting c0011ed3: 0x00003336 -> 0xc0013336
Adjusting c0011f20: 0x00003336 -> 0xc0013336
Adjusting c0011f6a: 0x00003aac -> 0xc0013aac
Adjusting c0012000: 0x00003352 -> 0xc0013352
Adjusting c001208e: 0x0000337a -> 0xc001337a
Adjusting c0012123: 0x00003490 -> 0xc0013490
Adjusting c0012168: 0x000033e2 -> 0xc00133e2
Adjusting c0012179: 0x0000342a -> 0xc001342a
Adjusting c00121c5: 0x0000344a -> 0xc001344a
Adjusting c00121f5: 0x0000346e -> 0xc001346e
Adjusting c001221d: 0x000033a6 -> 0xc00133a6
Adjusting c0012252: 0x000033c4 -> 0xc00133c4
Adjusting c0012268: 0x00003ab0 -> 0xc0013ab0
Adjusting c00122e3: 0x0000358c -> 0xc001358c
Adjusting c00122e8: 0x000034c9 -> 0xc00134c9
Adjusting c0012315: 0x000034d1 -> 0xc00134d1
Adjusting c0012344: 0x00003352 -> 0xc0013352
Adjusting c00123d3: 0x0000337a -> 0xc001337a
Adjusting c00123f5: 0x00003ab0 -> 0xc0013ab0
Adjusting c0012481: 0x00003490 -> 0xc0013490
Adjusting c00124c6: 0x0000351b -> 0xc001351b
Adjusting c00124d7: 0x0000342a -> 0xc001342a
Adjusting c00124f7: 0x00003ab0 -> 0xc0013ab0
Adjusting c001252b: 0x00003562 -> 0xc0013562
Adjusting c0012570: 0x000033a6 -> 0xc00133a6
Adjusting c001259b: 0x000034f4 -> 0xc00134f4
Adjusting c0012664: 0x00003a98 -> 0xc0013a98
Adjusting c0012673: 0x0000359d -> 0xc001359d
Adjusting c0012691: 0x000035a8 -> 0xc00135a8
Adjusting c00126ae: 0x000035b0 -> 0xc00135b0
Adjusting c00126c5: 0x000035b6 -> 0xc00135b6
Adjusting c00126dc: 0x000035be -> 0xc00135be
Adjusting c00126f3: 0x000035c4 -> 0xc00135c4
Adjusting c001270a: 0x000035c9 -> 0xc00135c9
Adjusting c0012721: 0x000035d1 -> 0xc00135d1
Adjusting c0012738: 0x000035da -> 0xc00135da
Adjusting c001274e: 0x000035de -> 0xc00135de
Adjusting c0012764: 0x000035e7 -> 0xc00135e7
Adjusting c001277a: 0x000035f0 -> 0xc00135f0
Adjusting c0012790: 0x00003961 -> 0xc0013961
Adjusting c00127a6: 0x000035f6 -> 0xc00135f6
Adjusting c00127bc: 0x000035fc -> 0xc00135fc
Adjusting c00127d2: 0x00003603 -> 0xc0013603
Adjusting c00127e8: 0x0000360c -> 0xc001360c
Adjusting c00127f9: 0x000032a3 -> 0xc00132a3
Adjusting c001286a: 0x00003ab8 -> 0xc0013ab8
Adjusting c00128a1: 0x0000361d -> 0xc001361d
Adjusting c00128c0: 0x0000362b -> 0xc001362b
Adjusting c00128d6: 0x00003648 -> 0xc0013648
Adjusting c00128f5: 0x00003655 -> 0xc0013655
Adjusting c0012905: 0x00003662 -> 0xc0013662
Adjusting c0012914: 0x00003617 -> 0xc0013617
Adjusting c001291f: 0x00003612 -> 0xc0013612
Adjusting c0012928: 0x00003673 -> 0xc0013673
Adjusting c0012942: 0x00003685 -> 0xc0013685
Adjusting c001295f: 0x00003a98 -> 0xc0013a98
Adjusting c0012987: 0x000036a5 -> 0xc00136a5
Adjusting c0012998: 0x00003a98 -> 0xc0013a98
Adjusting c00129c5: 0x000036c7 -> 0xc00136c7
Adjusting c00129e3: 0x000036b6 -> 0xc00136b6
Adjusting c00129ec: 0x00003a98 -> 0xc0013a98
Adjusting c00129fe: 0x000036d8 -> 0xc00136d8
Adjusting c0012a14: 0x00003a98 -> 0xc0013a98
Adjusting c0012a26: 0x000036ee -> 0xc00136ee
Adjusting c0012a30: 0x00003abc -> 0xc0013abc
Adjusting c0012a3a: 0x00003703 -> 0xc0013703
Adjusting c0012a79: 0x00003ab4 -> 0xc0013ab4
Adjusting c0012a83: 0x0000372e -> 0xc001372e
Adjusting c0012aa6: 0x00003ab4 -> 0xc0013ab4
Adjusting c0012ac7: 0x00003abc -> 0xc0013abc
Adjusting c0012ace: 0x00003747 -> 0xc0013747
Adjusting c0012ad3: 0x00003ab8 -> 0xc0013ab8
Adjusting c0012ade: 0x00003a98 -> 0xc0013a98
Adjusting c0012af0: 0x00003761 -> 0xc0013761
Adjusting c0012b02: 0x00003a98 -> 0xc0013a98
Adjusting c0012b42: 0x00003770 -> 0xc0013770
Adjusting c0012b5d: 0x00003786 -> 0xc0013786
Adjusting c0012b72: 0x00003a98 -> 0xc0013a98
Adjusting c0012b84: 0x00003794 -> 0xc0013794
Adjusting c0012b9b: 0x00003a98 -> 0xc0013a98
Adjusting c0012ba9: 0x000037aa -> 0xc00137aa
Adjusting c0012bc1: 0x000037ba -> 0xc00137ba
Adjusting c0012bd8: 0x000037b4 -> 0xc00137b4
Adjusting c0012bef: 0x000037bf -> 0xc00137bf
Adjusting c0012c06: 0x000037c8 -> 0xc00137c8
Adjusting c0012c21: 0x000037cd -> 0xc00137cd
Adjusting c0012c37: 0x000037d5 -> 0xc00137d5
Adjusting c0012c4d: 0x000037da -> 0xc00137da
Adjusting c0012c63: 0x000037de -> 0xc00137de
Adjusting c0012c74: 0x000032a3 -> 0xc00132a3
Adjusting c0012c81: 0x00003a98 -> 0xc0013a98
Adjusting c0012c92: 0x000037e5 -> 0xc00137e5
Adjusting c0012ca7: 0x00003a98 -> 0xc0013a98
Adjusting c0012cd0: 0x000037f1 -> 0xc00137f1
Adjusting c0012ced: 0x00003a98 -> 0xc0013a98
Adjusting c0012d06: 0x00003805 -> 0xc0013805
Adjusting c0012d1e: 0x000039e4 -> 0xc00139e4
Adjusting c0012d23: 0x00003ab8 -> 0xc0013ab8
Adjusting c0012da7: 0x000038e4 -> 0xc00138e4
Adjusting c0012dae: 0x00003819 -> 0xc0013819
Adjusting c0012dba: 0x00003831 -> 0xc0013831
Adjusting c0012dc6: 0x00003855 -> 0xc0013855
Adjusting c0012e15: 0x00003879 -> 0xc0013879
Adjusting c0012e1e: 0x0000389e -> 0xc001389e
Adjusting c0012e2c: 0x00003a98 -> 0xc0013a98
Adjusting c0012e5f: 0x000038c2 -> 0xc00138c2
Adjusting c0012e70: 0x00003a98 -> 0xc0013a98
Adjusting c0012e9c: 0x00003a98 -> 0xc0013a98
Adjusting c0012ec0: 0x00003a98 -> 0xc0013a98
Adjusting c0012f5b: 0x000038fc -> 0xc00138fc
Adjusting c0012f67: 0x00003ab8 -> 0xc0013ab8
Adjusting c0012f7e: 0x00003a98 -> 0xc0013a98
Adjusting c0012fa8: 0x00002f90 -> 0xc0012f90
Adjusting c0012fb0: 0x0000057d -> 0xc001057d
Adjusting c0012fb4: 0x00002f90 -> 0xc0012f90
Adjusting c0012fbc: 0x000005ee -> 0xc00105ee
Adjusting c0012fc8: 0x000030a8 -> 0xc00130a8
Adjusting c00130a8: 0x000008e9 -> 0xc00108e9
Adjusting c00130ac: 0x000008f5 -> 0xc00108f5
Adjusting c00130b0: 0x000008f8 -> 0xc00108f8
Adjusting c00138e4: 0x00002dab -> 0xc0012dab
Adjusting c00138e8: 0x00002db7 -> 0xc0012db7
Adjusting c00138ec: 0x00002e5c -> 0xc0012e5c
Adjusting c00138f0: 0x00002dc3 -> 0xc0012dc3
Adjusting c00138f4: 0x00002e12 -> 0xc0012e12
Adjusting c00138f8: 0x00002e1b -> 0xc0012e1b
Adjusting c0013a10: 0x00002cb8 -> 0xc0012cb8
Adjusting c0013a14: 0x000029a8 -> 0xc00129a8
Adjusting c0013a20: 0x00002b93 -> 0xc0012b93
Adjusting c0013a24: 0x0000265c -> 0xc001265c
Adjusting c0013a28: 0x00002958 -> 0xc0012958
Adjusting c0013a2c: 0x00002b70 -> 0xc0012b70
Adjusting c0013a34: 0x00002aff -> 0xc0012aff
Adjusting c0013a38: 0x00002adc -> 0xc0012adc
Adjusting c0013a54: 0x0000280a -> 0xc001280a
Loading module at c0008000 with entry c0008000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0xc0008000
Adjusting c0008002: 0x00000024 -> 0xc0008024
Adjusting c000801d: 0x0000003c -> 0xc000803c
Adjusting c0008026: 0x00000024 -> 0xc0008024
Adjusting c0008054: 0x000000d8 -> 0xc00080d8
Adjusting c0008066: 0x00000160 -> 0xc0008160
Adjusting c000806d: 0x000000c0 -> 0xc00080c0
Adjusting c0008075: 0x000000c4 -> 0xc00080c4
Adjusting c000807e: 0x000000d0 -> 0xc00080d0
Adjusting c0008085: 0x000000cc -> 0xc00080cc
Adjusting c000808b: 0x000000c8 -> 0xc00080c8
SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd
SMM Module: placing jmp sequence at c0007800 rel16 0x07fd
SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd
SMM Module: stub loaded at c0008000. Will call c0011589(00000000)
Initializing southbridge SMI... ... pmbase = 0x0500

SMI_STS: PERIODIC MCSMI PM1 
PM1_STS: WAK PWRBTN TMROF 
GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW 
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 
TCO_STS: INTRD_DET 
  ... raise SMI#
In relocation handler: cpu 0
New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00
Writing SMRR. base = 0xc0000006, mask=0xff800800
Relocation complete.
Locking SMM.
Initializing CPU #0
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
POST: 0x60
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS: Found @ offset 15340 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3768
memalign bffd3768
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3780
memalign bffd3780
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3798
memalign bffd3798
memalign Enter, boundary 8, size 24, free_mem_ptr bffd37b0
memalign bffd37b0
memalign Enter, boundary 8, size 24, free_mem_ptr bffd37c8
memalign bffd37c8
memalign Enter, boundary 8, size 24, free_mem_ptr bffd37e0
memalign bffd37e0
memalign Enter, boundary 8, size 24, free_mem_ptr bffd37f8
memalign bffd37f8
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3810
memalign bffd3810
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3828
memalign bffd3828
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3840
memalign bffd3840
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3858
memalign bffd3858
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3870
memalign bffd3870
memalign Enter, boundary 8, size 24, free_mem_ptr bffd3888
memalign bffd3888
memalign Enter, boundary 8, size 24, free_mem_ptr bffd38a0
memalign bffd38a0
memalign Enter, boundary 8, size 24, free_mem_ptr bffd38b8
memalign bffd38b8
memalign Enter, boundary 8, size 24, free_mem_ptr bffd38d0
memalign bffd38d0
memalign Enter, boundary 8, size 24, free_mem_ptr bffd38e8
memalign bffd38e8
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
0x00000000c0000000 - 0x00000000e0000000 size 0x20000000 type 0
0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1
0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0
0x0000000100000000 - 0x000000042f600000 size 0x32f600000 type 6
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR addr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc1 set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd2-0xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTRR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type @ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 3/9.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0
MTRR: 1 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
MTRR: 2 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local APIC... apic_id: 0x00 done.
POST: 0x9b
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
Turbo is available but hidden
Turbo has been enabled
CPU: 0 has 2 cores, 2 threads per core
memalign Enter, boundary 8, size 152, free_mem_ptr bffd3900
memalign bffd3900
CPU: 0 has core 1
CPU1: stack_base bffcc000, stack_end bffccff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
In relocation handler: cpu 1
New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00
Writing SMRR. base = 0xc0000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
memalign Enter, boundary 8, size 152, free_mem_ptr bffd3998
CPU: vendor Intel device 306a9
memalign bffd3998
CPU: family 06, model 3a, stepping 09
CPU: 0 has core 2
POST: 0x60
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS: Found @ offset 15340 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local APIC... apic_id: 0x01 done.
POST: 0x9b
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
CPU #1 initialized
CPU2: stack_base bffcb000, stack_end bffcbff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
In relocation handler: cpu 2
Startup point 1.
Waiting for send to finish...
+New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00
Sending STARTUP #2 to 2.
After apic_write.
Writing SMRR. base = 0xc0000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
memalign Enter, boundary 8, size 152, free_mem_ptr bffd3a30
memalign bffd3a30
CPU: 0 has core 3
Initializing CPU #2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
POST: 0x60
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS: Found @ offset 15340 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local APIC... apic_id: 0x02 done.
POST: 0x9b
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
CPU #2 initialized
CPU3: stack_base bffca000, stack_end bffcaff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
In relocation handler: cpu 3
New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00
Writing SMRR. base = 0xc0000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU #0 initialized
Waiting for 1 CPUS to stop
Initializing CPU #3
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
POST: 0x60
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS: Found @ offset 15340 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local APIC... apic_id: 0x03 done.
POST: 0x9b
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2600
CPU #3 initialized
All AP CPUs stopped (396 loops)
CPU0: stack: bffcd000 - bffce000, lowest used address bffcda20, stack used: 1504 bytes
CPU1: stack: bffcc000 - bffcd000, lowest used address bffccc54, stack used: 940 bytes
CPU2: stack: bffcb000 - bffcc000, lowest used address bffcbc54, stack used: 940 bytes
CPU3: stack: bffca000 - bffcb000, lowest used address bffcac54, stack used: 940 bytes
CPU_CLUSTER: 0 init finished in 81103 usecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling PEG10.
Disabling PEG60.
Disabling PEG IO clock.
Set BIOS_RESET_CPL
CPU TDP: 35 Watts
PCI: 00:00.0 init finished in 1012 usecs
POST: 0x75
POST: 0x75
PCI: 00:02.0 init ...
GT Power Management Init
IVB GT2 25W-35W Power Meter Weights
GT Power Management Init (post VBIOS)
Initializing VGA without OPROM.
EDID:
00 ff ff ff ff ff ff 00 30 e4 d8 02 00 00 00 00 
00 16 01 03 80 1c 10 78 ea 88 55 99 5b 55 8f 26 
1d 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 
01 01 01 01 01 01 60 1d 56 d8 50 00 18 30 30 40 
47 00 15 9c 10 00 00 1b 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 4c 
47 20 44 69 73 70 6c 61 79 0a 20 20 00 00 00 fe 
00 4c 50 31 32 35 57 48 32 2d 53 4c 42 33 00 59 
Extracted contents:
header:          00 ff ff ff ff ff ff 00
serial number:   30 e4 d8 02 00 00 00 00 00 16
version:         01 03
basic params:    80 1c 10 78 ea
chroma info:     88 55 99 5b 55 8f 26 1d 50 54
established:     00 00 00
standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1:    60 1d 56 d8 50 00 18 30 30 40 47 00 15 9c 10 00 00 1b
descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
descriptor 3:    00 00 00 fe 00 4c 47 20 44 69 73 70 6c 61 79 0a 20 20
descriptor 4:    00 00 00 fe 00 4c 50 31 32 35 57 48 32 2d 53 4c 42 33
extensions:      00
checksum:        59

Manufacturer: LGD Model 2d8 Serial Number 0
Made week 0 of 2012
EDID version: 1.3
Digital display
Maximum image size: 28 cm x 16 cm
Gamma: 220%
Check DPMS levels
DPMS levels: Standby Suspend Off
Supported color formats: RGB 4:4:4, YCrCb 4:2:2
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 601d56d85000183030404700159c1000001b
Detailed mode (IN HEX): Clock 75200 KHz, 115 mm x 9c mm
               0556 0586 05c6 062e hborder 0
               0300 0304 030b 0318 vborder 0
               +hsync -vsync 
Did detailed timing
Hex of detail: 000000000000000000000000000000000000
Manufacturer-specified data, tag 0
Hex of detail: 000000fe004c4720446973706c61790a2020
ASCII string: LG Display
Hex of detail: 000000fe004c503132355748322d534c4233
ASCII string: LP125WH2-SLB3
Checksum
Checksum: 0x59 (valid)
WARNING: EDID block does NOT fully conform to EDID 1.3.
	Missing name descriptor
	Missing monitor ranges
bringing up panel at resolution 1376 x 768
Borders 0 x 0
Blank 216 x 24
Sync 64 x 7
Front porch 48 x 4
Spread spectrum clock
Single channel
Polarities 0, 1
Data M1=5256861, N1=8388608
Link frequency 270000 kHz
Link M1=146023, N1=524288
Pixel N=9, M1=14, M2=9, P1=1
Pixel clock 150476 kHz
waiting for panel powerup
panel powered up
PCI: 00:02.0 init finished in 42624 usecs
POST: 0x75
PCI: 00:04.0 init ...
PCI: 00:04.0 init finished in 0 usecs
POST: 0x75
PCI: 00:14.0 init ...
XHCI: Setting up controller.. done.
PCI: 00:14.0 init finished in 6 usecs
POST: 0x75
PCI: 00:16.0 init ...
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : YES
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Recovery
ME: Current Operation State : M0 without UMA but with error
ME: Current Operation Mode  : Normal
ME: Error Code              : Debug Failure
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : 0x17
ME: BIOS path: Error
PCI: 00:16.0 init finished in 14 usecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:19.0 init ...
PCI: 00:19.0 init finished in 0 usecs
POST: 0x75
PCI: 00:1a.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 12 usecs
POST: 0x75
PCI: 00:1b.0 init ...
Azalia: base = f1638000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862806
Azalia: verb_size: 16
Azalia: verb loaded.
Azalia: Initializing codec #0
Azalia: codec viddid: 10ec0269
Azalia: verb_size: 76
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 5971 usecs
POST: 0x75
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 10 usecs
POST: 0x75
PCI: 00:1c.1 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.1 init finished in 10 usecs
POST: 0x75
PCI: 00:1c.2 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.2 init finished in 13 usecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:1d.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 12 usecs
POST: 0x75
POST: 0x75
PCI: 00:1f.0 init ...
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
  reg 0x0000: 0x02000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
Set power off after power failure.
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
NMI sources enabled.
PantherPoint PM init
rtc_failed = 0x0
RTC Init
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 1651 usecs
POST: 0x75
PCI: 00:1f.2 init ...
SATA: Initializing...
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS: Found @ offset 21e00 size 7a0
SATA: Controller in AHCI mode.
ABAR: f163d000
PCI: 00:1f.2 init finished in 432 usecs
POST: 0x75
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 7 usecs
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 14 usecs
POST: 0x75
PCI: 02:00.0 init ...
PCI: 02:00.0 init finished in 0 usecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PNP: 00ff.2 init ...
PNP: 00ff.2 init finished in 0 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
I2C: 01:54 init finished in 1 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
I2C: 01:55 init finished in 0 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
I2C: 01:56 init finished in 0 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
I2C: 01:57 init finished in 0 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init finished in 25511 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
I2C: 01:5d init finished in 0 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
I2C: 01:5e init finished in 0 usecs
POST: 0x75
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
I2C: 01:5f init finished in 0 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 0
PCI: 00:02.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 01:00.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 0
PCI: 00:1c.4: enabled 0
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:5c: enabled 1
I2C: 01:5d: enabled 1
I2C: 01:5e: enabled 1
I2C: 01:5f: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 0
PCI: 00:04.0: enabled 1
PCI: 02:00.0: enabled 1
Unknown device path type: 0
: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
BS: BS_DEV_INIT times (us): entry 10 run 158555 exit 0
POST: 0x76
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (us): entry 1 run 4 exit 0
POST: 0x77
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3 exit 0
Updating MRC cache data.
CBFS: 'Master Header Locator' located CBFS at [1b100:bfffc0)
CBFS: Locating 'mrc.cache'
CBFS: Checking offset 0
CBFS: File @ offset 0 size 20
CBFS:  Unmatched 'cbfs master header' at 0
CBFS: Checking offset 80
CBFS: File @ offset 80 size 15244
CBFS:  Unmatched 'fallback/romstage' at 80
CBFS: Checking offset 15340
CBFS: File @ offset 15340 size 5800
CBFS:  Unmatched 'cpu_microcode_blob.bin' at 15340
CBFS: Checking offset 1abc0
CBFS: File @ offset 1abc0 size 6a00
CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 1abc0
CBFS: Checking offset 21640
CBFS: File @ offset 21640 size 3c5
CBFS:  Unmatched 'config' at 21640
CBFS: Checking offset 21a40
CBFS: File @ offset 21a40 size 240
CBFS:  Unmatched 'revision' at 21a40
CBFS: Checking offset 21cc0
CBFS: File @ offset 21cc0 size 100
CBFS:  Unmatched 'cmos.default' at 21cc0
CBFS: Checking offset 21e00
CBFS: File @ offset 21e00 size 7a0
CBFS:  Unmatched 'cmos_layout.bin' at 21e00
CBFS: Checking offset 22600
CBFS: File @ offset 22600 size 660
CBFS:  Unmatched 'payload_config' at 22600
CBFS: Checking offset 22cc0
CBFS: File @ offset 22cc0 size ea
CBFS:  Unmatched 'payload_revision' at 22cc0
CBFS: Checking offset 22e00
CBFS: File @ offset 22e00 size 8
CBFS:  Unmatched 'etc/ps2-keyboard-spinup' at 22e00
CBFS: Checking offset 22e40
CBFS: File @ offset 22e40 size f
CBFS:  Unmatched 'bootorder' at 22e40
CBFS: Checking offset 22ec0
CBFS: File @ offset 22ec0 size 8
CBFS:  Unmatched 'etc/show-boot-menu' at 22ec0
CBFS: Checking offset 22f00
CBFS: File @ offset 22f00 size 11f2
CBFS:  Unmatched 'grub.cfg' at 22f00
CBFS: Checking offset 24140
CBFS: File @ offset 24140 size d58
CBFS:  Unmatched '' at 24140
CBFS: Checking offset 24ec0
CBFS: File @ offset 24ec0 size 10000
CBFS: Found @ offset 24ec0 size 10000
find_current_mrc_cache_local: No valid MRC cache found.
read 6008 from 07e4
wrote 00000004 to 0890
read 03040103 from 0894
read 00000000 from 0880
wrote 00000000 to 0880
memalign Enter, boundary 8, size 44, free_mem_ptr bffd3ac8
memalign bffd3ac8
read 00000000 from 07e8
wrote 00000000 to 07e8
wrote 00001000 to 0890
read 4990001c from 0894
flash size 0xc00000 bytes
SF: Detected Opaque HW-sequencing with sector size 0x1000, total 0xc00000
Need to erase the MRC cache region of 65536 bytes at ff440000
read 6008 from 07e4
wrote 6008 to 07e4
read 00000000 from 07e8
wrote 00040000 to 07e8
read 0000 from 07e6
wrote 0007 to 07e6
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 from 07e4
read 6028 
1455230 bytes lost