sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/coreboot_console.txt

*** Pre-CBMEM romstage console overflowed, log truncated! ***
S          : 24T
Selected tWR           : 12T
Selected tFAW          : 24T
Selected tRRD          : 5T
Selected tRTP          : 6T
Selected tWTR          : 6T
Selected tRFC          : 208T
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 4
PCI(0, 0, 0)[bc] = 82a00000
PCI(0, 0, 0)[a8] = 7c600000
PCI(0, 0, 0)[ac] = 4
PCI(0, 0, 0)[b8] = 80000000
PCI(0, 0, 0)[b0] = 80a00000
PCI(0, 0, 0)[b4] = 80800000
PCI(0, 0, 0)[7c] = 7f
PCI(0, 0, 0)[70] = ff000000
PCI(0, 0, 0)[74] = 3
PCI(0, 0, 0)[78] = ff000c00
Done memory map
Done io registers
Done jedec reset
Done MRS commands
t123: 1767, 6000, 7620
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Recovery
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : Waiting for DID BIOS message
ME: FWS2: 0x161f0172
ME:  Bist in progress: 0x0
ME:  ICC Status      : 0x1
ME:  Invoke MEBx     : 0x0
ME:  CPU replaced    : 0x1
ME:  MBP ready       : 0x1
ME:  MFS failure     : 0x1
ME:  Warm reset req  : 0x0
ME:  CPU repl valid  : 0x1
ME:  (Reserved)      : 0x0
ME:  FW update req   : 0x0
ME:  (Reserved)      : 0x0
ME:  Current state   : 0x1f
ME:  Current PM event: 0x6
ME:  Progress code   : 0x1
Full training required
PASSED! Tell ME that DRAM is ready
ME: FWS2: 0x162c0172
ME:  Bist in progress: 0x0
ME:  ICC Status      : 0x1
ME:  Invoke MEBx     : 0x0
ME:  CPU replaced    : 0x1
ME:  MBP ready       : 0x1
ME:  MFS failure     : 0x1
ME:  Warm reset req  : 0x0
ME:  CPU repl valid  : 0x1
ME:  (Reserved)      : 0x0
ME:  FW update req   : 0x0
ME:  (Reserved)      : 0x0
ME:  Current state   : 0x2c
ME:  Current PM event: 0x6
ME:  Progress code   : 0x1
ME: Requested BIOS Action: Continue to boot
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Recovery
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : 0x2c
memcfg DDR3 ref clock 133 MHz
memcfg DDR3 clock 1596 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 dual rank, selected
   DIMMB 0 MB width x8 single rank
memcfg channel[1] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 dual rank, selected
   DIMMB 0 MB width x8 single rank
CBMEM:
IMD: root @ 7ffff000 254 entries.
IMD: root @ 7fffec00 62 entries.
Relocate MRC DATA from fefff9fc to 7ffdc000 (1440 bytes)
CBMEM entry for DIMM info: 0x7fffe960
MTRR Range: Start=ffc00000 End=0 (Size 400000)
MTRR Range: Start=0 End=1000000 (Size 1000000)
MTRR Range: Start=7f800000 End=80000000 (Size 800000)
MTRR Range: Start=80000000 End=80800000 (Size 800000)
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 2ff00 size 164ae
Decompressing stage fallback/ramstage @ 0x7ff95fc0 (264496 bytes)
Loading module at 7ff96000 with entry 7ff96000. filesize: 0x2ec70 memsize: 0x408f0
Processing 2915 relocs. Offset value of 0x7fe96000


coreboot-4.6-1237-g3f3025d7f1 Sat Aug 26 16:30:37 UTC 2017 ramstage starting...
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 0
PCI: 00:1c.3: enabled 0
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 1
PCI: 00:1c.6: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1f.0: enabled 1
PNP: 004e.1: enabled 0
PNP: 004e.4: enabled 1
PNP: 004e.5: enabled 0
PNP: 004e.6: enabled 1
PNP: 004e.7: enabled 1
PNP: 004e.8: enabled 0
PNP: 004e.a: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 0
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
  APIC: acac: enabled 0
 DOMAIN: 0000: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:16.1: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:16.3: enabled 0
  PCI: 00:19.0: enabled 0
  PCI: 00:1a.0: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 1
  PCI: 00:1c.1: enabled 0
  PCI: 00:1c.2: enabled 0
  PCI: 00:1c.3: enabled 0
  PCI: 00:1c.4: enabled 1
  PCI: 00:1c.5: enabled 1
  PCI: 00:1c.6: enabled 0
  PCI: 00:1c.7: enabled 0
  PCI: 00:1d.0: enabled 1
  PCI: 00:1e.0: enabled 0
  PCI: 00:1f.0: enabled 1
   PNP: 004e.1: enabled 0
   PNP: 004e.4: enabled 1
   PNP: 004e.5: enabled 0
   PNP: 004e.6: enabled 1
   PNP: 004e.7: enabled 1
   PNP: 004e.8: enabled 0
   PNP: 004e.a: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
  PCI: 00:1f.5: enabled 0
  PCI: 00:1f.6: enabled 0
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:02.0: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0150] ops
PCI: 00:00.0 [8086/0150] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0151] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0162] enabled
PCI: 00:16.0 [8086/1c3a] ops
PCI: 00:16.0 [8086/1c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.3: Disabling device
PCI: 00:19.0: Disabling device
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1c2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1c20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0 [8086/0000] bus ops
PCI: 00:1c.0 [8086/1c10] enabled
PCI: 00:1c.1: Disabling device
PCI: 00:1c.2: Disabling device
PCI: 00:1c.3: Disabling device
PCH: Remap PCIe function 4 to 1
PCI: 00:1c.4 [8086/0000] bus ops
PCI: 00:1c.4 [8086/1c18] enabled
PCH: Remap PCIe function 5 to 1
PCI: 00:1c.5 [8086/0000] bus ops
PCI: 00:1c.5 [8086/1c1a] enabled
PCI: 00:1c.6: Disabling device
PCI: 00:1c.7: Disabling device
PCH: RPFN 0x76543210 -> 0xfe41bad0
PCH: PCIe map 1c.1 -> 1c.5
PCH: PCIe map 1c.4 -> 1c.1
PCH: PCIe map 1c.5 -> 1c.4
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1c26] enabled
PCI: 00:1e.0: Disabling device
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1c5c] enabled
PCI: 00:1f.2 [8086/0000] ops
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 46400 size 5b0
PCI: 00:1f.2 [8086/1c00] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1c22] enabled
PCI: 00:1f.5: Disabling device
PCI: 00:1f.6: Disabling device
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [10de/1401] enabled
PCI: 01:00.1 [10de/0fba] enabled
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Enabling Common Clock Configuration
ASPM: Enabled None
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Enabling Common Clock Configuration
ASPM: Enabled None
scan_bus: scanning of bus PCI: 00:01.0 took 249 usecs
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:1c.0 took 50 usecs
PCI: 00:1c.1 scanning...
do_pci_scan_bridge for PCI: 00:1c.1
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [1b21/1042] enabled
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x68
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
scan_bus: scanning of bus PCI: 00:1c.1 took 205 usecs
PCI: 00:1c.4 scanning...
do_pci_scan_bridge for PCI: 00:1c.4
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [11ab/4380] enabled
Capability: type 0x01 @ 0x48
Capability: type 0x05 @ 0x5c
Capability: type 0x10 @ 0xc0
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.4 took 199 usecs
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
PNP: 004e.1 disabled
PNP: 004e.4 enabled
PNP: 004e.5 disabled
PNP: 004e.6 enabled
PNP: 004e.7 enabled
PNP: 004e.8 disabled
PNP: 004e.a enabled
scan_lpc_bus for PCI: 00:1f.0 done
scan_bus: scanning of bus PCI: 00:1f.0 took 115 usecs
PCI: 00:1f.3 scanning...
scan_generic_bus for PCI: 00:1f.3
scan_generic_bus for PCI: 00:1f.3 done
scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 1145 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 1150 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 1219 exit 0
found VGA at PCI: 00:02.0
found VGA at PCI: 01:00.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:1c.0 read_resources bus 2 link: 0
PCI: 00:1c.0 read_resources bus 2 link: 0 done
PCI: 00:1c.1 read_resources bus 3 link: 0
PCI: 00:1c.1 read_resources bus 3 link: 0 done
PCI: 00:1c.4 read_resources bus 4 link: 0
PCI: 00:1c.4 read_resources bus 4 link: 0 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
   PCI: 00:01.0 child on link 0 PCI: 01:00.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
    PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14
    PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c
    PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
    PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
    PCI: 01:00.1
    PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
   PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
   PCI: 00:16.1
   PCI: 00:16.2
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1c.5
   PCI: 00:1c.2
   PCI: 00:1c.3
   PCI: 00:1c.1 child on link 0 PCI: 03:00.0
   PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 03:00.0
    PCI: 03:00.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.4 child on link 0 PCI: 04:00.0
   PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 04:00.0
    PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
    PCI: 04:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 18
    PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 004e.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
    PNP: 004e.1
    PNP: 004e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 004e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.4
    PNP: 004e.4 resource base 295 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 1f size 0 align 0 gran 0 limit 0 flags c0000400 index c5
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.7
    PNP: 004e.7 resource base a00 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.8
    PNP: 004e.8 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 004e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.a
    PNP: 004e.a resource base 90 size 0 align 0 gran 0 limit 0 flags c0000400 index e0
    PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags c0000400 index f8
    PNP: 004e.a resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index f9
    PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags c0000400 index fa
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1f.5
   PCI: 00:1f.6
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 24 *  [0x0 - 0x7f] io
PCI: 00:01.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 04:00.0 18 *  [0x0 - 0xff] io
PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:1c.4 1c *  [0x1000 - 0x1fff] io
PCI: 00:02.0 20 *  [0x2000 - 0x203f] io
PCI: 00:1f.2 20 *  [0x2040 - 0x205f] io
PCI: 00:1f.2 10 *  [0x2060 - 0x2067] io
PCI: 00:1f.2 18 *  [0x2068 - 0x206f] io
PCI: 00:1f.2 14 *  [0x2070 - 0x2073] io
PCI: 00:1f.2 1c *  [0x2074 - 0x2077] io
DOMAIN: 0000 io: base: 2078 size: 2078 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 01:00.0 14 *  [0x0 - 0xfffffff] prefmem
PCI: 01:00.0 1c *  [0x10000000 - 0x11ffffff] prefmem
PCI: 00:01.0 prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0xffffff] mem
PCI: 01:00.0 30 *  [0x1000000 - 0x107ffff] mem
PCI: 01:00.1 10 *  [0x1080000 - 0x1083fff] mem
PCI: 00:01.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 10 *  [0x0 - 0x7fff] mem
PCI: 00:1c.1 mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 04:00.0 10 *  [0x20000 - 0x23fff] mem
PCI: 00:1c.4 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 *  [0x0 - 0x11ffffff] prefmem
PCI: 00:02.0 18 *  [0x20000000 - 0x2fffffff] prefmem
PCI: 00:01.0 20 *  [0x30000000 - 0x310fffff] mem
PCI: 00:02.0 10 *  [0x31400000 - 0x317fffff] mem
PCI: 00:1c.1 20 *  [0x31800000 - 0x318fffff] mem
PCI: 00:1c.4 20 *  [0x31900000 - 0x319fffff] mem
PCI: 00:1b.0 10 *  [0x31a00000 - 0x31a03fff] mem
PCI: 00:1f.2 24 *  [0x31a04000 - 0x31a047ff] mem
PCI: 00:1a.0 10 *  [0x31a05000 - 0x31a053ff] mem
PCI: 00:1d.0 10 *  [0x31a06000 - 0x31a063ff] mem
PCI: 00:1f.3 10 *  [0x31a07000 - 0x31a070ff] mem
PCI: 00:16.0 10 *  [0x31a08000 - 0x31a0800f] mem
DOMAIN: 0000 mem: base: 31a08010 size: 31a08010 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 60 base f8000000 limit fbffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
skipping PNP: 004e.6@c5 fixed resource, size=0!
skipping PNP: 004e.a@e0 fixed resource, size=0!
skipping PNP: 004e.a@f8 fixed resource, size=0!
skipping PNP: 004e.a@f9 fixed resource, size=0!
skipping PNP: 004e.a@fa fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit f7ffffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:2078 align:12 gran:0 limit:ffff
PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:1c.4 1c *  [0x2000 - 0x2fff] io
PCI: 00:02.0 20 *  [0x3000 - 0x303f] io
PCI: 00:1f.2 20 *  [0x3040 - 0x305f] io
PCI: 00:1f.2 10 *  [0x3060 - 0x3067] io
PCI: 00:1f.2 18 *  [0x3068 - 0x306f] io
PCI: 00:1f.2 14 *  [0x3070 - 0x3073] io
PCI: 00:1f.2 1c *  [0x3074 - 0x3077] io
DOMAIN: 0000 io: next_base: 3078 size: 2078 align: 12 gran: 0 done
PCI: 00:01.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
PCI: 01:00.0 24 *  [0x1000 - 0x107f] io
PCI: 00:01.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.4 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 04:00.0 18 *  [0x2000 - 0x20ff] io
PCI: 00:1c.4 io: next_base: 2100 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:c0000000 size:31a08010 align:28 gran:0 limit:f7ffffff
PCI: 00:01.0 24 *  [0xc0000000 - 0xd1ffffff] prefmem
PCI: 00:02.0 18 *  [0xe0000000 - 0xefffffff] prefmem
PCI: 00:01.0 20 *  [0xf0000000 - 0xf10fffff] mem
PCI: 00:02.0 10 *  [0xf1400000 - 0xf17fffff] mem
PCI: 00:1c.1 20 *  [0xf1800000 - 0xf18fffff] mem
PCI: 00:1c.4 20 *  [0xf1900000 - 0xf19fffff] mem
PCI: 00:1b.0 10 *  [0xf1a00000 - 0xf1a03fff] mem
PCI: 00:1f.2 24 *  [0xf1a04000 - 0xf1a047ff] mem
PCI: 00:1a.0 10 *  [0xf1a05000 - 0xf1a053ff] mem
PCI: 00:1d.0 10 *  [0xf1a06000 - 0xf1a063ff] mem
PCI: 00:1f.3 10 *  [0xf1a07000 - 0xf1a070ff] mem
PCI: 00:16.0 10 *  [0xf1a08000 - 0xf1a0800f] mem
DOMAIN: 0000 mem: next_base: f1a08010 size: 31a08010 align: 28 gran: 0 done
PCI: 00:01.0 prefmem: base:c0000000 size:12000000 align:28 gran:20 limit:d1ffffff
PCI: 01:00.0 14 *  [0xc0000000 - 0xcfffffff] prefmem
PCI: 01:00.0 1c *  [0xd0000000 - 0xd1ffffff] prefmem
PCI: 00:01.0 prefmem: next_base: d2000000 size: 12000000 align: 28 gran: 20 done
PCI: 00:01.0 mem: base:f0000000 size:1100000 align:24 gran:20 limit:f10fffff
PCI: 01:00.0 10 *  [0xf0000000 - 0xf0ffffff] mem
PCI: 01:00.0 30 *  [0xf1000000 - 0xf107ffff] mem
PCI: 01:00.1 10 *  [0xf1080000 - 0xf1083fff] mem
PCI: 00:01.0 mem: next_base: f1084000 size: 1100000 align: 24 gran: 20 done
PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.1 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 mem: base:f1800000 size:100000 align:20 gran:20 limit:f18fffff
PCI: 03:00.0 10 *  [0xf1800000 - 0xf1807fff] mem
PCI: 00:1c.1 mem: next_base: f1808000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.4 mem: base:f1900000 size:100000 align:20 gran:20 limit:f19fffff
PCI: 04:00.0 30 *  [0xf1900000 - 0xf191ffff] mem
PCI: 04:00.0 10 *  [0xf1920000 - 0xf1923fff] mem
PCI: 00:1c.4 mem: next_base: f1924000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x47c600000 TOLUD 0x82a00000 TOM 0x400000000
MEBASE 0x3ff000000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0x80000000 size 8M
Available memory below 4GB: 2048M
Available memory above 4GB: 14278M
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00d1ffffff] size 0x12000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem
PCI: 01:00.0 14 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 01:00.0 1c <- [0x00d0000000 - 0x00d1ffffff] size 0x02000000 gran 0x19 prefmem64
PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io
PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f107ffff] size 0x00080000 gran 0x13 romem
PCI: 01:00.1 10 <- [0x00f1080000 - 0x00f1083fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:02.0 10 <- [0x00f1400000 - 0x00f17fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
PCI: 00:16.0 10 <- [0x00f1a08000 - 0x00f1a0800f] size 0x00000010 gran 0x04 mem64
PCI: 00:1a.0 10 <- [0x00f1a05000 - 0x00f1a053ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00f1a00000 - 0x00f1a03fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.1 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.1 20 <- [0x00f1800000 - 0x00f18fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:1c.1 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00f1800000 - 0x00f1807fff] size 0x00008000 gran 0x0f mem64
PCI: 00:1c.1 assign_resources, bus 3 link: 0
PCI: 00:1c.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:1c.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:1c.4 20 <- [0x00f1900000 - 0x00f19fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:1c.4 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00f1920000 - 0x00f1923fff] size 0x00004000 gran 0x0e mem64
PCI: 04:00.0 18 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 04:00.0 30 <- [0x00f1900000 - 0x00f191ffff] size 0x00020000 gran 0x11 romem
PCI: 00:1c.4 assign_resources, bus 4 link: 0
PCI: 00:1d.0 10 <- [0x00f1a06000 - 0x00f1a063ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 004e.4 60 <- [0x0000000295 - 0x000000029c] size 0x00000008 gran 0x03 io
PNP: 004e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq
PNP: 004e.6 c5 <- [0x000000001f - 0x000000001e] size 0x00000000 gran 0x00 irq
ERROR: PNP: 004e.6 70 irq size: 0x0000000001 not assigned
PNP: 004e.7 60 <- [0x0000000a00 - 0x0000000a07] size 0x00000008 gran 0x03 io
PNP: 004e.a e0 <- [0x0000000090 - 0x000000008f] size 0x00000000 gran 0x00 irq
PNP: 004e.a f8 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
PNP: 004e.a f9 <- [0x0000000009 - 0x0000000008] size 0x00000000 gran 0x00 irq
PNP: 004e.a fa <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00f1a04000 - 0x00f1a047ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00f1a07000 - 0x00f1a070ff] size 0x00000100 gran 0x08 mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 1000 size 2078 align 12 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base c0000000 size 31a08010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4
  DOMAIN: 0000 resource base 100000000 size 37c600000 align 0 gran 0 limit 0 flags e0004200 index 5
  DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
  DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
  DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8
  DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
  DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
   PCI: 00:00.0
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
   PCI: 00:01.0 child on link 0 PCI: 01:00.0
   PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
   PCI: 00:01.0 resource base c0000000 size 12000000 align 28 gran 20 limit d1ffffff flags 60081202 index 24
   PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit f10fffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit f0ffffff flags 60000200 index 10
    PCI: 01:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 14
    PCI: 01:00.0 resource base d0000000 size 2000000 align 25 gran 25 limit d1ffffff flags 60001201 index 1c
    PCI: 01:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24
    PCI: 01:00.0 resource base f1000000 size 80000 align 19 gran 19 limit f107ffff flags 60002200 index 30
    PCI: 01:00.1
    PCI: 01:00.1 resource base f1080000 size 4000 align 14 gran 14 limit f1083fff flags 60000200 index 10
   PCI: 00:02.0
   PCI: 00:02.0 resource base f1400000 size 400000 align 22 gran 22 limit f17fffff flags 60000201 index 10
   PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
   PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base f1a08000 size 10 align 12 gran 4 limit f1a0800f flags 60000201 index 10
   PCI: 00:16.1
   PCI: 00:16.2
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base f1a05000 size 400 align 12 gran 10 limit f1a053ff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base f1a00000 size 4000 align 14 gran 14 limit f1a03fff flags 60000201 index 10
   PCI: 00:1c.0
   PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
   PCI: 00:1c.5
   PCI: 00:1c.2
   PCI: 00:1c.3
   PCI: 00:1c.1 child on link 0 PCI: 03:00.0
   PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.1 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
   PCI: 00:1c.1 resource base f1800000 size 100000 align 20 gran 20 limit f18fffff flags 60080202 index 20
    PCI: 03:00.0
    PCI: 03:00.0 resource base f1800000 size 8000 align 15 gran 15 limit f1807fff flags 60000201 index 10
   PCI: 00:1c.4 child on link 0 PCI: 04:00.0
   PCI: 00:1c.4 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
   PCI: 00:1c.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
   PCI: 00:1c.4 resource base f1900000 size 100000 align 20 gran 20 limit f19fffff flags 60080202 index 20
    PCI: 04:00.0
    PCI: 04:00.0 resource base f1920000 size 4000 align 14 gran 14 limit f1923fff flags 60000201 index 10
    PCI: 04:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 18
    PCI: 04:00.0 resource base f1900000 size 20000 align 17 gran 17 limit f191ffff flags 60002200 index 30
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base f1a06000 size 400 align 12 gran 10 limit f1a063ff flags 60000200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 004e.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
    PNP: 004e.1
    PNP: 004e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 004e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.4
    PNP: 004e.4 resource base 295 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 1f size 0 align 0 gran 0 limit 0 flags e0000400 index c5
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.7
    PNP: 004e.7 resource base a00 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 004e.8
    PNP: 004e.8 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 004e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.a
    PNP: 004e.a resource base 90 size 0 align 0 gran 0 limit 0 flags e0000400 index e0
    PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags e0000400 index f8
    PNP: 004e.a resource base 9 size 0 align 0 gran 0 limit 0 flags e0000400 index f9
    PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags e0000400 index fa
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10
   PCI: 00:1f.2 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14
   PCI: 00:1f.2 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18
   PCI: 00:1f.2 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c
   PCI: 00:1f.2 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 20
   PCI: 00:1f.2 resource base f1a04000 size 800 align 12 gran 11 limit f1a047ff flags 60000200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base f1a07000 size 100 align 12 gran 8 limit f1a070ff flags 60000201 index 10
   PCI: 00:1f.5
   PCI: 00:1f.6
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 2234 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 174b/1007
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 07
PCI: 00:02.0 subsystem <- 8086/2010
PCI: 00:02.0 cmd <- 03
PCI: 00:16.0 subsystem <- 174b/1007
PCI: 00:16.0 cmd <- 02
PCI: 00:1a.0 subsystem <- 174b/1007
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 8086/1c20
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 174b/1007
PCI: 00:1c.0 cmd <- 100
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 subsystem <- 174b/1007
PCI: 00:1c.1 cmd <- 106
PCI: 00:1c.4 bridge ctrl <- 0003
PCI: 00:1c.4 subsystem <- 174b/1007
PCI: 00:1c.4 cmd <- 107
PCI: 00:1d.0 subsystem <- 174b/1007
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 174b/1007
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 174b/1007
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 174b/1007
PCI: 00:1f.3 cmd <- 103
PCI: 01:00.0 cmd <- 03
PCI: 01:00.1 cmd <- 02
PCI: 03:00.0 cmd <- 02
PCI: 04:00.0 cmd <- 03
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 169 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 0 usecs
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
Setting up SMI for CPU
Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
Processing 12 relocs. Offset value of 0x00038000
Adjusting 00038002: 0x00000024 -> 0x00038024
Adjusting 0003801d: 0x0000003c -> 0x0003803c
Adjusting 00038026: 0x00000024 -> 0x00038024
Adjusting 00038054: 0x00000120 -> 0x00038120
Adjusting 00038066: 0x000001a8 -> 0x000381a8
Adjusting 0003806f: 0x00000100 -> 0x00038100
Adjusting 00038077: 0x00000104 -> 0x00038104
Adjusting 00038081: 0x00000110 -> 0x00038110
Adjusting 0003808a: 0x00000114 -> 0x00038114
Adjusting 000380ab: 0x00000118 -> 0x00038118
Adjusting 000380b2: 0x0000010c -> 0x0003810c
Adjusting 000380b8: 0x00000108 -> 0x00038108
SMM Module: stub loaded at 00038000. Will call 7ffb0fa3(7ffd2880)
Installing SMM handler to 0x80000000
Loading module at 80010000 with entry 80010554. filesize: 0x15d0 memsize: 0x55f0
Processing 68 relocs. Offset value of 0x80010000
Adjusting 80010036: 0x000014bc -> 0x800114bc
Adjusting 80010055: 0x000014bc -> 0x800114bc
Adjusting 80010108: 0x000014bc -> 0x800114bc
Adjusting 8001019d: 0x000014cc -> 0x800114cc
Adjusting 800104cb: 0x000015d0 -> 0x800115d0
Adjusting 80010521: 0x000015c8 -> 0x800115c8
Adjusting 80010537: 0x00001520 -> 0x80011520
Adjusting 8001055d: 0x000015d0 -> 0x800115d0
Adjusting 8001056b: 0x000015d0 -> 0x800115d0
Adjusting 80010578: 0x000015c0 -> 0x800115c0
Adjusting 80010583: 0x000015c0 -> 0x800115c0
Adjusting 80010597: 0x000015c4 -> 0x800115c4
Adjusting 8001059d: 0x000015d4 -> 0x800115d4
Adjusting 800105a5: 0x000015c4 -> 0x800115c4
Adjusting 800105c2: 0x000015d4 -> 0x800115d4
Adjusting 800105cb: 0x000015c0 -> 0x800115c0
Adjusting 800105e2: 0x000015d8 -> 0x800115d8
Adjusting 800105f2: 0x000015d8 -> 0x800115d8
Adjusting 80010618: 0x000015d8 -> 0x800115d8
Adjusting 80010680: 0x000014ec -> 0x800114ec
Adjusting 80010792: 0x000014a8 -> 0x800114a8
Adjusting 80010a8e: 0x000015dc -> 0x800115dc
Adjusting 80010abd: 0x000015e0 -> 0x800115e0
Adjusting 80010ad0: 0x000015dc -> 0x800115dc
Adjusting 80010af3: 0x000015e0 -> 0x800115e0
Adjusting 80010bb6: 0x000015dc -> 0x800115dc
Adjusting 80010dee: 0x000015e0 -> 0x800115e0
Adjusting 80010ff5: 0x000015e0 -> 0x800115e0
Adjusting 800110d4: 0x000015c8 -> 0x800115c8
Adjusting 800110e4: 0x000015c8 -> 0x800115c8
Adjusting 800110f9: 0x000015c8 -> 0x800115c8
Adjusting 8001111a: 0x000015c8 -> 0x800115c8
Adjusting 80011147: 0x000015c8 -> 0x800115c8
Adjusting 80011167: 0x000015c8 -> 0x800115c8
Adjusting 8001117d: 0x000015ec -> 0x800115ec
Adjusting 800111cb: 0x000015ec -> 0x800115ec
Adjusting 800111d1: 0x000015e8 -> 0x800115e8
Adjusting 800111d9: 0x000015e4 -> 0x800115e4
Adjusting 800111f6: 0x000015e4 -> 0x800115e4
Adjusting 80011211: 0x000015c8 -> 0x800115c8
Adjusting 80011267: 0x000015e8 -> 0x800115e8
Adjusting 800112bd: 0x000014fc -> 0x800114fc
Adjusting 800112da: 0x000015c8 -> 0x800115c8
Adjusting 800112f9: 0x00001510 -> 0x80011510
Adjusting 800112fe: 0x000015e8 -> 0x800115e8
Adjusting 800113cf: 0x000015c8 -> 0x800115c8
Adjusting 800113fd: 0x000015c8 -> 0x800115c8
Adjusting 8001142b: 0x000015c8 -> 0x800115c8
Adjusting 80011451: 0x000015c8 -> 0x800115c8
Adjusting 8001145e: 0x000015e8 -> 0x800115e8
Adjusting 80011472: 0x000015c8 -> 0x800115c8
Adjusting 800114a0: 0x00001488 -> 0x80011488
Adjusting 800114a8: 0x00000021 -> 0x80010021
Adjusting 800114ac: 0x00001488 -> 0x80011488
Adjusting 800114b4: 0x00000092 -> 0x80010092
Adjusting 800114c0: 0x000014d8 -> 0x800114d8
Adjusting 800114d8: 0x000002d5 -> 0x800102d5
Adjusting 800114dc: 0x000002e1 -> 0x800102e1
Adjusting 800114e0: 0x000002e4 -> 0x800102e4
Adjusting 80011530: 0x000012a4 -> 0x800112a4
Adjusting 80011534: 0x0000112a -> 0x8001112a
Adjusting 80011540: 0x00001428 -> 0x80011428
Adjusting 80011544: 0x000010d1 -> 0x800110d1
Adjusting 80011548: 0x000010f2 -> 0x800110f2
Adjusting 8001154c: 0x000010ed -> 0x800110ed
Adjusting 80011554: 0x0000120e -> 0x8001120e
Adjusting 80011558: 0x000010e1 -> 0x800110e1
Adjusting 80011574: 0x00001252 -> 0x80011252
Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8
Processing 12 relocs. Offset value of 0x80008000
Adjusting 80008002: 0x00000024 -> 0x80008024
Adjusting 8000801d: 0x0000003c -> 0x8000803c
Adjusting 80008026: 0x00000024 -> 0x80008024
Adjusting 80008054: 0x00000120 -> 0x80008120
Adjusting 80008066: 0x000001a8 -> 0x800081a8
Adjusting 8000806f: 0x00000100 -> 0x80008100
Adjusting 80008077: 0x00000104 -> 0x80008104
Adjusting 80008081: 0x00000110 -> 0x80008110
Adjusting 8000808a: 0x00000114 -> 0x80008114
Adjusting 800080ab: 0x00000118 -> 0x80008118
Adjusting 800080b2: 0x0000010c -> 0x8000810c
Adjusting 800080b8: 0x00000108 -> 0x80008108
SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 80007800 rel16 0x07fd
SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd
SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd
SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd
SMM Module: placing jmp sequence at 80006800 rel16 0x17fd
SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd
SMM Module: stub loaded at 80008000. Will call 80010554(00000000)
Initializing southbridge SMI... ... pmbase = 0x0500

SMI_STS: PM1 
PM1_STS: WAK PWRBTN 
GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
TCO_STS: 
  ... raise SMI#
In relocation handler: cpu 0
New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
Locking SMM.
Initializing CPU #0
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x1b
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000c0000000 size 0x40000000 type 0
0x00000000c0000000 - 0x00000000d2000000 size 0x12000000 type 1
0x00000000d2000000 - 0x00000000e0000000 size 0x0e000000 type 0
0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1
0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0
0x0000000100000000 - 0x000000047c600000 size 0x37c600000 type 6
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR addr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc1 set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd2-0xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTRR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type @ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 8/11.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 1
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ffe000000 type 1
MTRR: 3 base 0x00000000d2000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d4000000 mask 0x0000000ffc000000 type 0
MTRR: 5 base 0x00000000d8000000 mask 0x0000000ff8000000 type 0
MTRR: 6 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
MTRR: 7 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x00 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
Turbo is available but hidden
Turbo has been enabled
CPU: 0 has 4 cores, 2 threads per core
CPU: 0 has core 1
CPU1: stack_base 7ffcb000, stack_end 7ffcbff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
In relocation handler: cpu 1
New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: 0 has core 2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x1b
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x01 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #1 initialized
CPU2: stack_base 7ffca000, stack_end 7ffcaff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
In relocation handler: cpu 2
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 2.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 3
Initializing CPU #2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x02 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #2 initialized
CPU3: stack_base 7ffc9000, stack_end 7ffc9ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
In relocation handler: cpu 3
New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 4
CPU4: stack_base 7ffc8000, stack_end 7ffc8ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 4.
After apic_write.
In relocation handler: cpu 4
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 4.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 5
Initializing CPU #4
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x04 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #4 initialized
CPU5: stack_base 7ffc7000, stack_end 7ffc7ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 5.
After apic_write.
In relocation handler: cpu 5
New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 5.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 6
CPU6: stack_base 7ffc6000, stack_end 7ffc6ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 6.
After apic_write.
In relocation handler: cpu 6
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 6.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 7
Initializing CPU #3
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x1b
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x03 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #3 initialized
CPU7: stack_base 7ffc5000, stack_end 7ffc5ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 7.
After apic_write.
In relocation handler: cpu 7
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 7.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU #0 initialized
Waiting for 3 CPUS to stop
Initializing CPU #5
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x1b
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x05 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #5 initialized
Waiting for 2 CPUS to stop
Initializing CPU #6
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x06 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #6 initialized
Waiting for 1 CPUS to stop
Initializing CPU #7
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13140 size 5800
microcode: sig=0x306a9 pf=0x2 revision=0x1b
CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x07 done.
VMX status: enabled, locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3400
CPU #7 initialized
All AP CPUs stopped (4102 loops)
CPU0: stack: 7ffcc000 - 7ffcd000, lowest used address 7ffccaa0, stack used: 1376 bytes
CPU1: stack: 7ffcb000 - 7ffcc000, lowest used address 7ffcbc80, stack used: 896 bytes
CPU2: stack: 7ffca000 - 7ffcb000, lowest used address 7ffcac80, stack used: 896 bytes
CPU3: stack: 7ffc9000 - 7ffca000, lowest used address 7ffc9c80, stack used: 896 bytes
CPU4: stack: 7ffc8000 - 7ffc9000, lowest used address 7ffc8c80, stack used: 896 bytes
CPU5: stack: 7ffc7000 - 7ffc8000, lowest used address 7ffc7c80, stack used: 896 bytes
CPU6: stack: 7ffc6000 - 7ffc7000, lowest used address 7ffc6c80, stack used: 896 bytes
CPU7: stack: 7ffc5000 - 7ffc6000, lowest used address 7ffc5c80, stack used: 896 bytes
CPU_CLUSTER: 0 init finished in 188813 usecs
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling Device 4.
Disabling PEG60.
Disabling Device 7.
Set BIOS_RESET_CPL
CPU TDP: 77 Watts
PCI: 00:00.0 init finished in 1010 usecs
PCI: 00:02.0 init ...
GT Power Management Init
IVB GT2 35W Power Meter Weights
GT Power Management Init (post VBIOS)
Initializing VGA without OPROM.

[0.210223] CONFIG =>
[0.210223]   (Primary   =>
[0.210224]      (Port => Analog  ,
[0.210224]       Framebuffer =>
[0.210224]         (Width  => 640,
[0.210225]          Height => 400,
[0.210225]          Stride => 320,
[0.210226]          Offset => 0xffffffff,
[0.210226]          BPC    => 5),
[0.210227]       Mode =>
[0.210227]         (Dotclock           => 148500000,
[0.210228]          H_Visible          => 1920,
[0.210228]          H_Sync_Begin       => 2008,
[0.210229]          H_Sync_End         => 2052,
[0.210229]          H_Total            => 2200,
[0.210230]          V_Visible          => 1080,
[0.210230]          V_Sync_Begin       => 1084,
[0.210231]          V_Sync_End         => 1089,
[0.210231]          V_Total            => 1125,
[0.210232]          H_Sync_Active_High => True,
[0.210232]          V_Sync_Active_High => True,
[0.210233]          BPC                => 5)),
[0.210233]    Secondary =>
[0.210234]      (Port => Disabled,
[0.210234]       Framebuffer =>
[0.210234]         (Width  => 1,
[0.210235]          Height => 1,
[0.210235]          Stride => 1,
[0.210235]          Offset => 0x00000000,
[0.210236]          BPC    => 8),
[0.210236]       Mode =>
[0.210236]         (Dotclock           => 24000000,
[0.210237]          H_Visible          => 1,
[0.210237]          H_Sync_Begin       => 1,
[0.210238]          H_Sync_End         => 1,
[0.210238]          H_Total            => 1,
[0.210239]          V_Visible          => 1,
[0.210239]          V_Sync_Begin       => 1,
[0.210240]          V_Sync_End         => 1,
[0.210240]          V_Total            => 1,
[0.210241]          H_Sync_Active_High => False,
[0.210241]          V_Sync_Active_High => False,
[0.210242]          BPC                => 5)),
[0.210242]    Tertiary  =>
[0.210242]      (Port => Disabled,
[0.210243]       Framebuffer =>
[0.210243]         (Width  => 1,
[0.210243]          Height => 1,
[0.210244]          Stride => 1,
[0.210244]          Offset => 0x00000000,
[0.210244]          BPC    => 8),
[0.210245]       Mode =>
[0.210245]         (Dotclock           => 24000000,
[0.210246]          H_Visible          => 1,
[0.210246]          H_Sync_Begin       => 1,
[0.210247]          H_Sync_End         => 1,
[0.210247]          H_Total            => 1,
[0.210248]          V_Visible          => 1,
[0.210248]          V_Sync_Begin       => 1,
[0.210249]          V_Sync_End         => 1,
[0.210249]          V_Total            => 1,
[0.210250]          H_Sync_Active_High => False,
[0.210250]          V_Sync_Active_High => False,
[0.210251]          BPC                => 5)));
PCI: 00:02.0 init finished in 17331 usecs
PCI: 00:16.0 init ...
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : YES
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Recovery
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : Image Failure
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : M0 kernel load
ME: BIOS path: Error
PCI: 00:16.0 init finished in 14 usecs
PCI: 00:1a.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 12 usecs
PCI: 00:1b.0 init ...
Azalia: base = f1a00000
Azalia: codec_mask = 0c
Azalia: Initializing codec #3
Azalia: codec viddid: 80862805
Azalia: verb_size: 16
Azalia: verb loaded.
Azalia: Initializing codec #2
Azalia: codec viddid: 10ec0892
Azalia: verb_size: 60
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 5263 usecs
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 10 usecs
PCI: 00:1c.1 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.1 init finished in 7 usecs
PCI: 00:1c.4 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.4 init finished in 8 usecs
PCI: 00:1d.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 11 usecs
PCI: 00:1f.0 init ...
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
  reg 0x0000: 0x02000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 46400 size 5b0
Set power on after power failure.
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 46400 size 5b0
NMI sources enabled.
CougarPoint PM init
rtc_failed = 0x0
RTC Init
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 1175 usecs
PCI: 00:1f.2 init ...
SATA: Initializing...
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 46400 size 5b0
SATA: Controller in AHCI mode.
ABAR: f1a04000
PCI: 00:1f.2 init finished in 447 usecs
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 7 usecs
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 0 usecs
PCI: 01:00.1 init ...
PCI: 01:00.1 init finished in 0 usecs
PCI: 03:00.0 init ...
PCI: 03:00.0 init finished in 0 usecs
PCI: 04:00.0 init ...
PCI: 04:00.0 init finished in 0 usecs
PNP: 004e.4 init ...
PNP: 004e.4 init finished in 67 usecs
PNP: 004e.6 init ...
PNP: 004e.6 init finished in 0 usecs
PNP: 004e.7 init ...
PNP: 004e.7 init finished in 0 usecs
PNP: 004e.a init ...
PNP: 004e.a init finished in 0 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.2: enabled 0
PCI: 00:1c.3: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.6: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1f.0: enabled 1
PNP: 004e.1: enabled 0
PNP: 004e.4: enabled 1
PNP: 004e.5: enabled 0
PNP: 004e.6: enabled 1
PNP: 004e.7: enabled 1
PNP: 004e.8: enabled 0
PNP: 004e.a: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 0
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 01:00.0: enabled 1
PCI: 01:00.1: enabled 1
PCI: 03:00.0: enabled 1
PCI: 04:00.0: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
APIC: 06: enabled 1
APIC: 07: enabled 1
BS: BS_DEV_INIT times (us): entry 5 run 214298 exit 0
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 4 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3 exit 0
Updating MRC cache data.
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset 1fec0 size 10000
find_current_mrc_cache_local: No valid MRC cache found.
Manufacturer: bf
Unrecognized SPI transaction type 0xff
SF: SST: status = ffffffff
SF: Detected SST25VF032B with sector size 0x1000, total 0x400000
Need to erase the MRC cache region of 65536 bytes at ffc40000
SF: Successfully erased 65536 bytes @ 0x40000
Finally: write MRC cache update to flash at ffc40000
Successfully wrote MRC cache
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 46a00 size 27e7
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7ff18000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
Found 1 CPU(s) with 8 core(s) each.
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
PSS: 3401MHz power 77000 control 0x2700 status 0x2700
PSS: 3400MHz power 77000 control 0x2200 status 0x2200
PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
PSS: 2400MHz power 48259 control 0x1800 status 0x1800
PSS: 2000MHz power 38348 control 0x1400 status 0x1400
PSS: 1600MHz power 29132 control 0x1000 status 0x1000
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI:    * TCPA
TCPA log created at 7ff07000
ACPI: added table 3/32, length now 48
ACPI:    * MADT
ACPI: added table 4/32, length now 52
current = 7ff1d3f0
ACPI:     * DMAR
ACPI: added table 5/32, length now 56
current = 7ff1d4a0
ACPI:    * HPET
ACPI: added table 6/32, length now 60
GET_VBIOS: 80f8 6e4c 2a f 36
VBIOS not found.
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'pci10de,1401.rom'
CBFS: 'pci10de,1401.rom' not found.
PCI Option ROM loading disabled for PCI: 01:00.0
ACPI: done.
ACPI tables: 21728 bytes.
smbios_write_tables: 7ff06000
Create SMBIOS type 17
Root Device (Sapphire Pure Platinum H61)
CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
APIC: 00 (unknown)
APIC: acac (Intel SandyBridge/IvyBridge CPU)
DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PNP: 004e.1 (Fintek F71808A Super I/O)
PNP: 004e.4 (Fintek F71808A Super I/O)
PNP: 004e.5 (Fintek F71808A Super I/O)
PNP: 004e.6 (Fintek F71808A Super I/O)
PNP: 004e.7 (Fintek F71808A Super I/O)
PNP: 004e.8 (Fintek F71808A Super I/O)
PNP: 004e.a (Fintek F71808A Super I/O)
PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 01:00.0 (unknown)
PCI: 01:00.1 (unknown)
PCI: 03:00.0 (unknown)
PCI: 04:00.0 (unknown)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
APIC: 06 (unknown)
APIC: 07 (unknown)
SMBIOS tables: 562 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum bfea
Writing coreboot table at 0x7ff3c000
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 46400 size 5b0
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000007ff05fff: RAM
 4. 000000007ff06000-000000007fffffff: CONFIGURATION TABLES
 5. 0000000080000000-00000000829fffff: RESERVED
 6. 00000000f8000000-00000000fbffffff: RESERVED
 7. 00000000fed90000-00000000fed91fff: RESERVED
 8. 0000000100000000-000000047c5fffff: RAM
Manufacturer: bf
Unrecognized SPI transaction type 0xff
SF: SST: status = ffffffff
SF: Detected SST25VF032B with sector size 0x1000, total 0x400000
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
FMAP: Found "FLASH" version 1.1 at 20000.
FMAP: base = ffc00000 size = 400000 #areas = 3
Wrote coreboot table at: 7ff3c000, 0x920 bytes, checksum 3626
coreboot table: 2360 bytes.
IMD ROOT    0. 7ffff000 00001000
IMD SMALL   1. 7fffe000 00001000
CONSOLE     2. 7ffde000 00020000
TIME STAMP  3. 7ffdd000 00000400
MRC DATA    4. 7ffdc000 000005b0
ROMSTG STCK 5. 7ffd7000 00005000
RAMSTAGE    6. 7ff95000 00042000
57a9e100    7. 7ff54000 000408f0
SMM BACKUP  8. 7ff44000 00010000
COREBOOT    9. 7ff3c000 00008000
ACPI       10. 7ff18000 00024000
ACPI GNVS  11. 7ff17000 00001000
TCPA LOG   12. 7ff07000 00010000
SMBIOS     13. 7ff06000 00000800
IMD small region:
  IMD ROOT    0. 7fffec00 00000400
  CAR GLOBALS 1. 7fffeac0 00000140
  MEM INFO    2. 7fffe960 00000141
  ROMSTAGE    3. 7fffe940 00000004
  57a9e000    4. 7fffe920 00000010
BS: BS_WRITE_TABLES times (us): entry 289378 run 4993 exit 0
CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 84a80 size f65f
Loading segment from ROM address 0xffca4bb8
  code (compression=1)
  New segment dstaddr 0xe31c0 memsize 0x1ce40 srcaddr 0xffca4bf0 filesize 0xf627
Loading segment from ROM address 0xffca4bd4
  Entry Point 0x000ff06e
Payload being loaded at below 1MiB without region being marked as RAM usable.
Loading Segment: addr: 0x00000000000e31c0 memsz: 0x000000000001ce40 filesz: 0x000000000000f627
lb: [0x000000007ff96000, 0x000000007ffd68f0)
Post relocation: addr: 0x00000000000e31c0 memsz: 0x000000000001ce40 filesz: 0x000000000000f627
using LZMA
[ 0x000e31c0, 00100000, 0x00100000) <- ffca4bf0
dest 000e31c0, end 00100000, bouncebuffer ffffffff
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 19482 exit 0
PCH watchdog disabled
Jumping to boot code at 000ff06e(7ff3c000)
CPU0: stack: 7ffcc000 - 7ffcd000, lowest used address 7ffcc9c4, stack used: 1596 bytes
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU Binutils) 2.28
Found coreboot cbmem console @ 7ffde000
Found mainboard Sapphire Pure Platinum H61
Relocating init from 0x000e4740 to 0x7feb9da0 (size 49600)
Found CBFS header at 0xffc20138
multiboot: eax=7ffc45e0, ebx=7ffc4594
Found 17 PCI devices (max PCI bus is 04)
Copying SMBIOS entry point from 0x7ff06000 to 0x000f08e0
Copying ACPI RSDP from 0x7ff18000 to 0x000f08b0
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
pmm call arg1=0
Turning on vga text mode console
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
XHCI init on dev 03:00.0: regs @ 0xf1800000, 4 ports, 32 slots, 32 byte contexts
XHCI    extcap 0x1 @ 0xf1800800
XHCI    protocol USB  3.00, 2 ports (offset 1), def 0
XHCI    protocol USB  2.00, 2 ports (offset 3), def 1
EHCI init on dev 00:1a.0 (regs=0xf1a05020)
EHCI init on dev 00:1d.0 (regs=0xf1a06020)
WARNING - Timeout at i8042_flush:71!
AHCI controller at 00:1f.2, iobase 0xf1a04000, irq 10
Found 0 lpt ports
Found 0 serial ports
Searching bootorder for: /rom@img/memtest
Searching bootorder for: /rom@img/tint
Searching bootorder for: /rom@img/nvramcui
Searching bootorder for: /rom@img/coreinfo
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
AHCI/0: Set transfer mode to UDMA-6
AHCI/0: registering: "AHCI/0: KINGSTON SH103S3120G ATA-8 Hard-Disk (111 GiBytes)"
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0
AHCI/1: Set transfer mode to UDMA-6
AHCI/1: registering: "AHCI/1: KINGSTON SH103S3120G ATA-8 Hard-Disk (111 GiBytes)"
XHCI no devices found
Initialized USB HUB (0 ports used)
USB keyboard initialized
USB mouse initialized
Initialized USB HUB (2 ports used)
Initialized USB HUB (1 ports used)
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@5/disk@0
AHCI/5: Set transfer mode to UDMA-6
AHCI/5: registering: "AHCI/5: SAMSUNG HD502HI ATA-7 Hard-Disk (465 GiBytes)"
All threads complete.
Scan for option roms

Press ESC for boot menu.

Searching bootorder for: HALT
drive 0x000f0840: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648
drive 0x000f07f0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648
drive 0x000f07a0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168
Space available for UMB: c6800-ea800, f0000-f07a0
Returned 245760 bytes of ZoneHigh
e820 map has 8 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000007ff02000 = 1 RAM
  4: 000000007ff02000 - 0000000082a00000 = 2 RESERVED
  5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
  6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
  7: 0000000100000000 - 000000047c600000 = 1 RAM
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00