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review.coreboot.org / board-status / 0911f2818b6be0e0f0caee7eee1cfb6fd99ea1f6 / . / asus / kgpe-d16 / 4.5-1206-g589fc3473e / 2017-03-10T10_20_39Z / coreboot_console_serial.txt
blob: fde5727b3b4d86c850f1beb75053c86d30197952 [file] [log] [blame]
Paul Menzel0911f282017-03-10 16:42:24 +0100[diff] [blame^]1
2
3======= Fri Mar 10 15:32:19 2017 (adjust=86.8us)
400.000: <00>
500.190:
600.190:
700.190: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
800.190: Initial stack pointer: 000dffb8
900.191: CPU APICID 00 start flag set
1000.193: BSP Family_Model: 00600f12
1100.193: *sysinfo range: [000c2d20,000cd28c]
1200.193: bsp_apicid = 00
1300.193: cpu_init_detectedx = 00000000
1400.193: sb700 reset flags: 0020
1500.193: WARNING: MC4 Machine Check Exception detected on node 0!
1600.193: Signature: e300000400190127
1700.194: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1800.194: CBFS: Locating 'microcode_amd.bin'
1900.195: CBFS: Found @ offset d0000 size 318c
2000.196: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2100.196: CBFS: Locating 'microcode_amd_fam15h.bin'
2200.196: CBFS: Found @ offset d3200 size 1ec4
2300.217: [microcode] patch id to apply = 0x0600063d
2400.218: [microcode] updated to patch id = 0x0600063d success
2500.218: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2600.220: CBFS: Locating 'cmos_layout.bin'
2700.221: CBFS: Found @ offset 2b0c0 size e88
2800.222: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2900.222: CBFS: Locating 'cmos_layout.bin'
3000.222: CBFS: Found @ offset 2b0c0 size e88
3100.223: done
3200.223: Enter amd_ht_init
3300.226: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
3400.227: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
3500.227: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
3600.230: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
3700.230: CBFS: Locating 'cmos_layout.bin'
3800.231: CBFS: Found @ offset 2b0c0 size e88
3900.231: Forcing HT links to isochronous mode due to enabled IOMMU
4000.231: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
4100.232: CBFS: Locating 'cmos_layout.bin'
4200.232: CBFS: Found @ offset 2b0c0 size e88
4300.233: Exit amd_ht_init
4400.233: amd_ht_fixup
4500.233: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
4600.234: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
4700.234: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
4800.234: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
4900.235: cpuSetAMDPCI 00 done
5000.237: cpuSetAMDPCI 01 done
5100.238: cpuSetAMDPCI 02 done
5200.238: cpuSetAMDPCI 03 done
5300.239: Prep FID/VID Node:00
5400.239: F3x80: e20be281
5500.239: F3x84: 01e200e2
5600.239: F3xD4: c3312f18
5700.239: F3xD8: 03000016
5800.240: F3xDC: 05475632
5900.240: Prep FID/VID Node:01
6000.240: F3x80: e20be281
6100.240: F3x84: 01e200e2
6200.240: F3xD4: c3312f18
6300.240: F3xD8: 03000016
6400.240: F3xDC: 05475632
6500.240: Prep FID/VID Node:02
6600.240: F3x80: e20be281
6700.240: F3x84: 01e200e2
6800.240: F3xD4: c3312f18
6900.240: F3xD8: 03000016
7000.240: F3xDC: 05475632
7100.240: Prep FID/VID Node:03
7200.241: F3x80: e20be281
7300.241: F3x84: 01e200e2
7400.241: F3xD4: c3312f18
7500.241: F3xD8: 03000016
7600.241: F3xDC: 05475632
7700.241: setup_remote_node: 01 done
7800.241: Start node 01 done.
7900.241: setup_remote_node: 02 done
8000.242: Start node 02 done.
8100.242: setup_remote_node: 03 done
8200.243: Start node 03 done.
8300.245: WARNING: MC4 Machine Check Exception detected on node 1!
8400.251: Signature: f627f7fe561fd7bf
8500.252: WARNING: MC4 Machine Check Exception detected on node 2!
8600.255: Signature: fa1008e3ca054c0f
8700.257: WARNING: MC4 Machine Check Exception detected on node 3!
8800.258: Signature: f20512f100010e0f
8900.259: core0 started: 01 02 03
9000.259: sr5650_early_setup()
9100.259: get_cpu_rev EAX=0x600f12.
9200.259: CPU Rev is Fam 15.
9300.259: NB Revision is A12.
9400.259: fam10_optimization()
9500.260: sr5650_por_init
9600.265: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
9700.266: CBFS: Locating 'cmos_layout.bin'
9800.266: CBFS: Found @ offset 2b0c0 size e88
9900.266: Enabling IOMMU
10000.268: sb700_early_setup()
10100.268: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
10200.268: CBFS: Locating 'cmos_layout.bin'
10300.270: CBFS: Found @ offset 2b0c0 size e88
10400.272: sb700_devices_por_init()
10500.273: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
10600.275: SMBus controller enabled, sb revision is A15
10700.275: sb700_devices_por_init: Disabling ISA DMA support
10800.275: sb700_devices_por_init(): IDE Device, BDF:0-20-1
10900.278: sb700_devices_por_init(): LPC Device, BDF:0-20-3
11000.279: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
11100.280: sb700_devices_por_init(): SATA Device, BDF:0-17-0
11200.280: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
11300.280: CBFS: Locating 'cmos_layout.bin'
11400.281: CBFS: Found @ offset 2b0c0 size e88
11500.281: sb700_pmio_por_init()
11600.281: start_other_cores()
11700.282: init node: 00 cores: 07 pass 1
11800.282: Start other core - nodeid: 00 cores: 07
11900.282: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
12000.336: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
12100.363: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
12200.386: init node: 01 cores: 07 pass 1
12300.389: Start other core - nodeid: 01 cores: 07
12400.394: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
12500.494: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
12600.520: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
12700.545: init node: 02 cores: 07 pass 1
12800.547: Start other core - nodeid: 02 cores: 07
12900.549: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
13000.758: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
13100.782: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
13200.833: init node: 03 cores: 07 pass 1
13300.837: Start other core - nodeid: 03 cores: 07
13400.842: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
13501.105: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
13601.105: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
13701.106: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
13801.109: * AP 01started
13901.110: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
14001.114: * AP 02started
14101.117: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
14201.117: * AP 03started
14301.118: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
14401.118: * AP 04started
14501.118: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
14601.118: * AP 05started
14701.118: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
14801.118: * AP 06started
14901.120: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
15001.123: * AP 07started
15101.123: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
15201.123: * AP 09started
15301.123: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
15401.124: * AP 0astarted
15501.124: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
15601.124: * AP 0bstarted
15701.124: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
15801.127: * AP 0cstarted
15901.127: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
16001.128: * AP 0dstarted
16101.128: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
16201.129: * AP 0estarted
16301.129: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
16401.129: * AP 0fstarted
16501.129: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
16601.131: * AP 21started
16701.132: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
16801.133: * AP 22started
16901.133: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
17001.134: * AP 23started
17101.134: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
17201.134: * AP 24started
17301.134: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
17401.135: * AP 25started
17501.136: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
17601.137: * AP 26started
17701.137: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
17801.137: * AP 27started
17901.137: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
18001.137: * AP 29started
18101.137: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
18201.137: * AP 2astarted
18301.137: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
18401.138: * AP 2bstarted
18501.138: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
18601.138: * AP 2cstarted
18701.138: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
18801.138: * AP 2dstarted
18901.138: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
19001.138: * AP 2estarted
19101.138: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
19201.139: * AP 2fstarted
19301.139:
19401.139:
19501.139: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c06644c
19601.139: FIDVID on BSP, APIC_id: 00
19701.140: BSP fid = 0
19801.140: get_boot_apic_id: using 0 as APIC ID for node 0, core 0
19901.140: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
20001.140: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
20101.140: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
20201.140: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
20301.140: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
20401.141: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
20501.141: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
20601.141: get_boot_apic_id: using 8 as APIC ID for node 1, core 0
20701.141: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
20801.141: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
20901.141: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
21001.142: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
21101.142: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
21201.142: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
21301.142: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
21401.142: get_boot_apic_id: using 32 as APIC ID for node 2, core 0
21501.142: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
21601.143: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
21701.143: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
21801.143: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
21901.143: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
22001.143: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
22101.143: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
22201.144: get_boot_apic_id: using 40 as APIC ID for node 3, core 0
22301.144: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
22401.144: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
22501.144: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
22601.144: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
22701.144: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
22801.145: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
22901.145: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
23001.145: Wait for AP stage 1: ap_apicid = 1
23101.145: <09>readback = 1000014
23201.145: <09>common_fid(packed) = 0
23301.145: Wait for AP stage 1: ap_apicid = 2
23401.145: <09>readback = 2000014
23501.146: <09>common_fid(packed) = 0
23601.146: Wait for AP stage 1: ap_apicid = 3
23701.146: <09>readback = 3000014
23801.146: <09>common_fid(packed) = 0
23901.146: Wait for AP stage 1: ap_apicid = 4
24001.146: <09>readback = 4000014
24101.146: <09>common_fid(packed) = 0
24201.146: Wait for AP stage 1: ap_apicid = 5
24301.146: <09>readback = 5000014
24401.146: <09>common_fid(packed) = 0
24501.146: Wait for AP stage 1: ap_apicid = 6
24601.146: <09>readback = 6000014
24701.147: <09>common_fid(packed) = 0
24801.147: Wait for AP stage 1: ap_apicid = 7
24901.147: <09>readback = 7000014
25001.147: <09>common_fid(packed) = 0
25101.147: Wait for AP stage 1: ap_apicid = 8
25201.147: <09>readback = 8000014
25301.147: <09>common_fid(packed) = 0
25401.147: Wait for AP stage 1: ap_apicid = 9
25501.147: <09>readback = 9000014
25601.147: <09>common_fid(packed) = 0
25701.147: Wait for AP stage 1: ap_apicid = a
25801.148: <09>readback = a000014
25901.148: <09>common_fid(packed) = 0
26001.148: Wait for AP stage 1: ap_apicid = b
26101.148: <09>readback = b000014
26201.148: <09>common_fid(packed) = 0
26301.148: Wait for AP stage 1: ap_apicid = c
26401.148: <09>readback = c000014
26501.148: <09>common_fid(packed) = 0
26601.148: Wait for AP stage 1: ap_apicid = d
26701.148: <09>readback = d000014
26801.148: <09>common_fid(packed) = 0
26901.148: Wait for AP stage 1: ap_apicid = e
27001.149: <09>readback = e000014
27101.149: <09>common_fid(packed) = 0
27201.149: Wait for AP stage 1: ap_apicid = f
27301.149: <09>readback = f000014
27401.149: <09>common_fid(packed) = 0
27501.149: Wait for AP stage 1: ap_apicid = 20
27601.149: <09>readback = 20000014
27701.149: <09>common_fid(packed) = 0
27801.150: Wait for AP stage 1: ap_apicid = 21
27901.149: <09>readback = 21000014
28001.149: <09>common_fid(packed) = 0
28101.150: Wait for AP stage 1: ap_apicid = 22
28201.150: <09>readback = 22000014
28301.150: <09>common_fid(packed) = 0
28401.150: Wait for AP stage 1: ap_apicid = 23
28501.150: <09>readback = 23000014
28601.150: <09>common_fid(packed) = 0
28701.150: Wait for AP stage 1: ap_apicid = 24
28801.150: <09>readback = 24000014
28901.150: <09>common_fid(packed) = 0
29001.150: Wait for AP stage 1: ap_apicid = 25
29101.150: <09>readback = 25000014
29201.150: <09>common_fid(packed) = 0
29301.151: Wait for AP stage 1: ap_apicid = 26
29401.151: <09>readback = 26000014
29501.151: <09>common_fid(packed) = 0
29601.151: Wait for AP stage 1: ap_apicid = 27
29701.151: <09>readback = 27000014
29801.151: <09>common_fid(packed) = 0
29901.151: Wait for AP stage 1: ap_apicid = 28
30001.151: <09>readback = 28000014
30101.151: <09>common_fid(packed) = 0
30201.151: Wait for AP stage 1: ap_apicid = 29
30301.151: <09>readback = 29000014
30401.152: <09>common_fid(packed) = 0
30501.152: Wait for AP stage 1: ap_apicid = 2a
30601.152: <09>readback = 2a000014
30701.152: <09>common_fid(packed) = 0
30801.152: Wait for AP stage 1: ap_apicid = 2b
30901.152: <09>readback = 2b000014
31001.152: <09>common_fid(packed) = 0
31101.152: Wait for AP stage 1: ap_apicid = 2c
31201.152: <09>readback = 2c000014
31301.152: <09>common_fid(packed) = 0
31401.152: Wait for AP stage 1: ap_apicid = 2d
31501.153: <09>readback = 2d000014
31601.153: <09>common_fid(packed) = 0
31701.153: Wait for AP stage 1: ap_apicid = 2e
31801.153: <09>readback = 2e000014
31901.153: <09>common_fid(packed) = 0
32001.153: Wait for AP stage 1: ap_apicid = 2f
32101.153: <09>readback = 2f000014
32201.153: <09>common_fid(packed) = 0
32301.153: common_fid = 0
32401.153: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c06644c
32501.154: sr5650_htinit: Node 0 Link 1, HT freq=e.
32601.154: sr5650_htinit: HT3 mode
32701.154: ...WARM RESET...
32801.154:
32901.154:
33001.154: <00>
33101.266:
33201.266:
33301.266: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
33401.266: Initial stack pointer: 000dffb8
33501.267: CPU APICID 00 start flag set
33601.268: BSP Family_Model: 00600f12
33701.268: *sysinfo range: [000c2d20,000cd28c]
33801.268: bsp_apicid = 00
33901.268: cpu_init_detectedx = 00000000
34001.268: sb700 reset flags: 0004
34101.269: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
34201.269: CBFS: Locating 'microcode_amd.bin'
34301.269: CBFS: Found @ offset d0000 size 318c
34401.270: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
34501.270: CBFS: Locating 'microcode_amd_fam15h.bin'
34601.270: CBFS: Found @ offset d3200 size 1ec4
34701.292: [microcode] patch id to apply = 0x0600063d
34801.293: [microcode] updated to patch id = 0x0600063d success
34901.293: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
35001.295: CBFS: Locating 'cmos_layout.bin'
35101.295: CBFS: Found @ offset 2b0c0 size e88
35201.296: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
35301.296: CBFS: Locating 'cmos_layout.bin'
35401.296: CBFS: Found @ offset 2b0c0 size e88
35501.296: done
35601.296: Enter amd_ht_init
35701.299: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
35801.300: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
35901.300: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
36001.302: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
36101.303: CBFS: Locating 'cmos_layout.bin'
36201.303: CBFS: Found @ offset 2b0c0 size e88
36301.303: Forcing HT links to isochronous mode due to enabled IOMMU
36401.303: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
36501.303: CBFS: Locating 'cmos_layout.bin'
36601.303: CBFS: Found @ offset 2b0c0 size e88
36701.304: Exit amd_ht_init
36801.304: amd_ht_fixup
36901.304: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
37001.305: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
37101.305: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
37201.305: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
37301.305: cpuSetAMDPCI 00 done
37401.307: cpuSetAMDPCI 01 done
37501.308: cpuSetAMDPCI 02 done
37601.308: cpuSetAMDPCI 03 done
37701.308: Prep FID/VID Node:00
37801.308: F3x80: e20be281
37901.308: F3x84: 01e200e2
38001.308: F3xD4: c3312f18
38101.308: F3xD8: 03000016
38201.308: F3xDC: 05475632
38301.308: Prep FID/VID Node:01
38401.308: F3x80: e20be281
38501.309: F3x84: 01e200e2
38601.309: F3xD4: c3312f18
38701.309: F3xD8: 03000016
38801.309: F3xDC: 05475632
38901.309: Prep FID/VID Node:02
39001.309: F3x80: e20be281
39101.309: F3x84: 01e200e2
39201.309: F3xD4: c3312f18
39301.309: F3xD8: 03000016
39401.309: F3xDC: 05475632
39501.309: Prep FID/VID Node:03
39601.309: F3x80: e20be281
39701.309: F3x84: 01e200e2
39801.309: F3xD4: c3312f18
39901.309: F3xD8: 03000016
40001.309: F3xDC: 05475632
40101.309: setup_remote_node: 01 done
40201.309: Start node 01 done.
40301.309: setup_remote_node: 02 done
40401.310: Start node 02 done.
40501.310: setup_remote_node: 03 done
40601.311: Start node 03 done.
40701.315: core0 started: 01 02 03
40801.317: sr5650_early_setup()
40901.318: get_cpu_rev EAX=0x600f12.
41001.319: CPU Rev is Fam 15.
41101.320: NB Revision is A12.
41201.321: fam10_optimization()
41301.323: sr5650_por_init
41401.324: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41501.325: CBFS: Locating 'cmos_layout.bin'
41601.325: CBFS: Found @ offset 2b0c0 size e88
41701.326: Enabling IOMMU
41801.326: sb700_early_setup()
41901.326: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
42001.329: CBFS: Locating 'cmos_layout.bin'
42101.329: CBFS: Found @ offset 2b0c0 size e88
42201.330: sb700_devices_por_init()
42301.331: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
42401.332: SMBus controller enabled, sb revision is A15
42501.332: sb700_devices_por_init: Disabling ISA DMA support
42601.333: sb700_devices_por_init(): IDE Device, BDF:0-20-1
42701.337: sb700_devices_por_init(): LPC Device, BDF:0-20-3
42801.338: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
42901.338: sb700_devices_por_init(): SATA Device, BDF:0-17-0
43001.339: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
43101.338: CBFS: Locating 'cmos_layout.bin'
43201.339: CBFS: Found @ offset 2b0c0 size e88
43301.340: sb700_pmio_por_init()
43401.341: start_other_cores()
43501.342: init node: 00 cores: 07 pass 1
43601.342: Start other core - nodeid: 00 cores: 07
43701.342: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
43801.423: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
43901.423: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
44001.440: init node: 01 cores: 07 pass 1
44101.443: Start other core - nodeid: 01 cores: 07
44201.446: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
44301.635: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
44401.658: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
44501.658: init node: 02 cores: 07 pass 1
44601.659: Start other core - nodeid: 02 cores: 07
44701.661: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
44801.838: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
44901.838: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
45001.855: init node: 03 cores: 07 pass 1
45101.856: Start other core - nodeid: 03 cores: 07
45201.858: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
45302.011: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
45402.035: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
45502.058: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
45602.062: * AP 01started
45702.063: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
45802.065: * AP 02started
45902.069: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
46002.070: * AP 03started
46102.070: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
46202.070: * AP 04started
46302.071: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
46402.072: * AP 05started
46502.073: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
46602.075: * AP 06started
46702.075: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
46802.075: * AP 07started
46902.075: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
47002.077: * AP 09started
47102.077: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
47202.079: * AP 0astarted
47302.079: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
47402.079: * AP 0bstarted
47502.079: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
47602.081: * AP 0cstarted
47702.082: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
47802.083: * AP 0dstarted
47902.083: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
48002.083: * AP 0estarted
48102.083: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
48202.085: * AP 0fstarted
48302.085: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
48402.085: * AP 21started
48502.085: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
48602.085: * AP 22started
48702.085: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
48802.085: * AP 23started
48902.086: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
49002.086: * AP 24started
49102.086: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
49202.086: * AP 25started
49302.086: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
49402.086: * AP 26started
49502.086: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
49602.086: * AP 27started
49702.086: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
49802.086: * AP 29started
49902.086: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
50002.086: * AP 2astarted
50102.086: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
50202.086: * AP 2bstarted
50302.086: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
50402.086: * AP 2cstarted
50502.086: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
50602.086: * AP 2dstarted
50702.086: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
50802.086: * AP 2estarted
50902.086: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
51002.086: * AP 2fstarted
51102.086:
51202.086:
51302.086: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
51402.086: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
51502.087: sr5650_htinit: Node 0 Link 1, HT freq=e.
51602.087: sr5650_htinit: HT3 mode
51702.087: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
51802.087: CBFS: Locating 'cmos_layout.bin'
51902.087: CBFS: Found @ offset 2b0c0 size e88
52002.087: ...WARM RESET...
52102.087:
52202.087:
52302.088: <00>
52402.191:
52502.191:
52602.191: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
52702.192: Initial stack pointer: 000dffb8
52802.193: CPU APICID 00 start flag set
52902.194: BSP Family_Model: 00600f12
53002.194: *sysinfo range: [000c2d20,000cd28c]
53102.194: bsp_apicid = 00
53202.194: cpu_init_detectedx = 00000000
53302.194: sb700 reset flags: 0004
53402.195: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
53502.195: CBFS: Locating 'microcode_amd.bin'
53602.195: CBFS: Found @ offset d0000 size 318c
53702.195: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
53802.195: CBFS: Locating 'microcode_amd_fam15h.bin'
53902.196: CBFS: Found @ offset d3200 size 1ec4
54002.210: [microcode] patch id to apply = 0x0600063d
54102.210: [microcode] updated to patch id = 0x0600063d success
54202.210: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
54302.212: CBFS: Locating 'cmos_layout.bin'
54402.212: CBFS: Found @ offset 2b0c0 size e88
54502.213: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
54602.213: CBFS: Locating 'cmos_layout.bin'
54702.213: CBFS: Found @ offset 2b0c0 size e88
54802.214: done
54902.214: Enter amd_ht_init
55002.217: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
55102.217: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
55202.217: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
55302.220: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
55402.220: CBFS: Locating 'cmos_layout.bin'
55502.220: CBFS: Found @ offset 2b0c0 size e88
55602.221: Forcing HT links to isochronous mode due to enabled IOMMU
55702.221: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
55802.221: CBFS: Locating 'cmos_layout.bin'
55902.221: CBFS: Found @ offset 2b0c0 size e88
56002.222: Exit amd_ht_init
56102.222: amd_ht_fixup
56202.222: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
56302.222: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
56402.222: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
56502.222: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
56602.223: cpuSetAMDPCI 00 done
56702.225: cpuSetAMDPCI 01 done
56802.225: cpuSetAMDPCI 02 done
56902.225: cpuSetAMDPCI 03 done
57002.225: Prep FID/VID Node:00
57102.226: F3x80: e20be281
57202.226: F3x84: 01e200e2
57302.226: F3xD4: c3312f18
57402.226: F3xD8: 03000016
57502.226: F3xDC: 05475632
57602.226: Prep FID/VID Node:01
57702.226: F3x80: e20be281
57802.226: F3x84: 01e200e2
57902.226: F3xD4: c3312f18
58002.226: F3xD8: 03000016
58102.226: F3xDC: 05475632
58202.226: Prep FID/VID Node:02
58302.226: F3x80: e20be281
58402.226: F3x84: 01e200e2
58502.226: F3xD4: c3312f18
58602.226: F3xD8: 03000016
58702.226: F3xDC: 05475632
58802.226: Prep FID/VID Node:03
58902.226: F3x80: e20be281
59002.226: F3x84: 01e200e2
59102.226: F3xD4: c3312f18
59202.226: F3xD8: 03000016
59302.226: F3xDC: 05475632
59402.226: setup_remote_node: 01 done
59502.226: Start node 01 done.
59602.226: setup_remote_node: 02 done
59702.227: Start node 02 done.
59802.227: setup_remote_node: 03 done
59902.228: Start node 03 done.
60002.232: core0 started: 01 02 03
60102.234: sr5650_early_setup()
60202.235: get_cpu_rev EAX=0x600f12.
60302.236: CPU Rev is Fam 15.
60402.237: NB Revision is A12.
60502.238: fam10_optimization()
60602.240: sr5650_por_init
60702.241: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60802.242: CBFS: Locating 'cmos_layout.bin'
60902.243: CBFS: Found @ offset 2b0c0 size e88
61002.243: Enabling IOMMU
61102.249: sb700_early_setup()
61202.250: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
61302.251: CBFS: Locating 'cmos_layout.bin'
61402.251: CBFS: Found @ offset 2b0c0 size e88
61502.251: sb700_devices_por_init()
61602.251: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
61702.257: SMBus controller enabled, sb revision is A15
61802.258: sb700_devices_por_init: Disabling ISA DMA support
61902.258: sb700_devices_por_init(): IDE Device, BDF:0-20-1
62002.260: sb700_devices_por_init(): LPC Device, BDF:0-20-3
62102.261: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
62202.261: sb700_devices_por_init(): SATA Device, BDF:0-17-0
62302.261: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62402.261: CBFS: Locating 'cmos_layout.bin'
62502.261: CBFS: Found @ offset 2b0c0 size e88
62602.262: sb700_pmio_por_init()
62702.262: start_other_cores()
62802.262: init node: 00 cores: 07 pass 1
62902.262: Start other core - nodeid: 00 cores: 07
63002.263: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
63102.330: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
63202.330: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
63302.340: init node: 01 cores: 07 pass 1
63402.342: Start other core - nodeid: 01 cores: 07
63502.347: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
63602.489: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
63702.506: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
63802.507: init node: 02 cores: 07 pass 1
63902.508: Start other core - nodeid: 02 cores: 07
64002.510: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
64102.657: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
64202.674: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
64302.688: init node: 03 cores: 07 pass 1
64402.689: Start other core - nodeid: 03 cores: 07
64502.691: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
64602.813: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
64702.852: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
64802.866: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
64902.869: * AP 01started
65002.870: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
65102.875: * AP 02started
65202.875: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
65302.876: * AP 03started
65402.876: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
65502.876: * AP 04started
65602.876: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
65702.879: * AP 05started
65802.880: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
65902.880: * AP 06started
66002.880: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
66102.880: * AP 07started
66202.880: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
66302.884: * AP 09started
66402.884: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
66502.884: * AP 0astarted
66602.884: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
66702.884: * AP 0bstarted
66802.885: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
66902.888: * AP 0cstarted
67002.888: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
67102.888: * AP 0dstarted
67202.889: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
67302.889: * AP 0estarted
67402.890: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
67502.891: * AP 0fstarted
67602.891: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
67702.891: * AP 21started
67802.891: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
67902.891: * AP 22started
68002.891: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
68102.891: * AP 23started
68202.891: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
68302.891: * AP 24started
68402.891: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
68502.891: * AP 25started
68602.891: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
68702.891: * AP 26started
68802.891: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
68902.891: * AP 27started
69002.891: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
69102.891: * AP 29started
69202.891: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
69302.891: * AP 2astarted
69402.892: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
69502.892: * AP 2bstarted
69602.892: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
69702.892: * AP 2cstarted
69802.892: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
69902.892: * AP 2dstarted
70002.892: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
70102.892: * AP 2estarted
70202.892: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
70302.892: * AP 2fstarted
70402.892:
70502.892:
70602.892: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
70702.892: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
70802.893: sr5650_htinit: Node 0 Link 1, HT freq=e.
70902.893: sr5650_htinit: HT3 mode
71002.893: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
71102.893: CBFS: Locating 'cmos_layout.bin'
71202.893: CBFS: Found @ offset 2b0c0 size e88
71302.893: Node 00 DIMM voltage set to index 00
71402.893: Node 01 DIMM voltage set to index 00
71502.893: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
71602.893: CBFS: Locating 'cmos_layout.bin'
71702.893: CBFS: Found @ offset 2b0c0 size e88
71802.894: stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
71902.894: * AP 01stopped
72002.894: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
72102.894: * AP 02stopped
72202.894: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
72302.894: * AP 03stopped
72402.894: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
72502.894: * AP 04stopped
72602.894: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
72702.894: * AP 05stopped
72802.894: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
72902.894: * AP 06stopped
73002.894: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
73102.894: * AP 07stopped
73202.894: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
73302.894: * AP 09stopped
73402.894: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
73502.894: * AP 0astopped
73602.894: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
73702.894: * AP 0bstopped
73802.894: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
73902.894: * AP 0cstopped
74002.894: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
74102.894: * AP 0dstopped
74202.894: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
74302.894: * AP 0estopped
74402.894: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
74502.894: * AP 0fstopped
74602.894: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
74702.894: * AP 21stopped
74802.894: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
74902.894: * AP 22stopped
75002.894: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
75102.894: * AP 23stopped
75202.894: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
75302.894: * AP 24stopped
75402.894: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
75502.894: * AP 25stopped
75602.894: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
75702.894: * AP 26stopped
75802.894: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
75902.895: * AP 27stopped
76002.895: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
76102.895: * AP 29stopped
76202.895: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
76302.895: * AP 2astopped
76402.895: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
76502.895: * AP 2bstopped
76602.895: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
76702.895: * AP 2cstopped
76802.895: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
76902.895: * AP 2dstopped
77002.895: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
77102.895: * AP 2estopped
77202.895: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
77302.895: * AP 2fstopped
77402.895:
77502.895: fill_mem_ctrl() detected 4 nodes
77602.895: raminit_amdmct()
77702.895: raminit_amdmct begin:
77802.896: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
77902.896: CBFS: Locating 'cmos_layout.bin'
78002.896: CBFS: Found @ offset 2b0c0 size e88
78102.896: mctAutoInitMCT_D: mct_init Node 0
78202.897: mctAutoInitMCT_D: mct_InitialMCT_D
78302.897: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
78402.897: mctAutoInitMCT_D: mctSMBhub_Init
78502.897: activate_spd_rom() for node 00
78602.897: enable_spd_node0()
78702.897: mctAutoInitMCT_D: mct_preInitDCT
78802.898: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
78902.898: CBFS: Locating 'cmos_layout.bin'
79002.898: CBFS: Found @ offset 2b0c0 size e88
79104.507: <09> DIMMPresence: DIMMValid=f
79204.507: <09> DIMMPresence: DIMMPresent=f
79304.507: <09> DIMMPresence: RegDIMMPresent=f
79404.507: <09> DIMMPresence: LRDIMMPresent=0
79504.507: <09> DIMMPresence: DimmECCPresent=f
79604.507: <09> DIMMPresence: DimmPARPresent=0
79704.507: <09> DIMMPresence: Dimmx4Present=f
79804.507: <09> DIMMPresence: Dimmx8Present=0
79904.507: <09> DIMMPresence: Dimmx16Present=0
80004.507: <09> DIMMPresence: DimmPlPresent=0
80104.507: <09> DIMMPresence: DimmDRPresent=f
80204.507: <09> DIMMPresence: DimmQRPresent=0
80304.507: <09> DIMMPresence: DATAload[0]=4
80404.507: <09> DIMMPresence: MAload[0]=40
80504.507: <09> DIMMPresence: MAdimms[0]=2
80604.507: <09> DIMMPresence: DATAload[1]=4
80704.507: <09> DIMMPresence: MAload[1]=40
80804.507: <09> DIMMPresence: MAdimms[1]=2
80904.507: <09> DIMMPresence: Status 2005
81004.507: <09> DIMMPresence: ErrStatus 0
81104.507: <09> DIMMPresence: ErrCode 0
81204.507: <09> DIMMPresence: Done
81304.507:
81404.507: <09><09>DCTPreInit_D: mct_DIMMPresence Done
81504.508: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
81604.508: CBFS: Locating 's3nv'
81704.508: CBFS: Found @ offset 2fec0 size 10000
81804.508: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
81904.508: CBFS: Locating 's3nv'
82004.508: CBFS: Found @ offset 2fec0 size 10000
82104.508: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
82204.508: CBFS: Locating 'cmos_layout.bin'
82304.508: CBFS: Found @ offset 2b0c0 size e88
82404.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
82504.509: CBFS: Locating 'cmos_layout.bin'
82604.509: CBFS: Found @ offset 2b0c0 size e88
82704.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
82804.509: CBFS: Locating 'cmos_layout.bin'
82904.509: CBFS: Found @ offset 2b0c0 size e88
83004.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
83104.509: CBFS: Locating 'cmos_layout.bin'
83204.509: CBFS: Found @ offset 2b0c0 size e88
83304.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
83404.509: CBFS: Locating 'cmos_layout.bin'
83504.509: CBFS: Found @ offset 2b0c0 size e88
83604.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
83704.510: CBFS: Locating 'cmos_layout.bin'
83804.510: CBFS: Found @ offset 2b0c0 size e88
83904.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
84004.510: CBFS: Locating 'cmos_layout.bin'
84104.510: CBFS: Found @ offset 2b0c0 size e88
84204.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
84304.510: CBFS: Locating 'cmos_layout.bin'
84404.510: CBFS: Found @ offset 2b0c0 size e88
84504.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
84604.510: CBFS: Locating 'cmos_layout.bin'
84704.510: CBFS: Found @ offset 2b0c0 size e88
84804.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
84904.510: CBFS: Locating 'cmos_layout.bin'
85004.510: CBFS: Found @ offset 2b0c0 size e88
85104.511: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
85204.511: CBFS: Locating 'cmos_layout.bin'
85304.511: CBFS: Found @ offset 2b0c0 size e88
85404.511: mctAutoInitMCT_D: mct_init Node 1
85504.511: mctAutoInitMCT_D: mct_InitialMCT_D
85604.511: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
85704.511: mctAutoInitMCT_D: mctSMBhub_Init
85804.511: activate_spd_rom() for node 01
85904.511: enable_spd_node1()
86004.511: mctAutoInitMCT_D: mct_preInitDCT
86104.511: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
86204.511: CBFS: Locating 'cmos_layout.bin'
86304.511: CBFS: Found @ offset 2b0c0 size e88
86406.119: <09> DIMMPresence: DIMMValid=f
86506.119: <09> DIMMPresence: DIMMPresent=f
86606.119: <09> DIMMPresence: RegDIMMPresent=f
86706.119: <09> DIMMPresence: LRDIMMPresent=0
86806.119: <09> DIMMPresence: DimmECCPresent=f
86906.119: <09> DIMMPresence: DimmPARPresent=0
87006.119: <09> DIMMPresence: Dimmx4Present=f
87106.119: <09> DIMMPresence: Dimmx8Present=0
87206.119: <09> DIMMPresence: Dimmx16Present=0
87306.119: <09> DIMMPresence: DimmPlPresent=0
87406.119: <09> DIMMPresence: DimmDRPresent=f
87506.119: <09> DIMMPresence: DimmQRPresent=0
87606.119: <09> DIMMPresence: DATAload[0]=4
87706.119: <09> DIMMPresence: MAload[0]=40
87806.119: <09> DIMMPresence: MAdimms[0]=2
87906.119: <09> DIMMPresence: DATAload[1]=4
88006.119: <09> DIMMPresence: MAload[1]=40
88106.119: <09> DIMMPresence: MAdimms[1]=2
88206.119: <09> DIMMPresence: Status 2005
88306.119: <09> DIMMPresence: ErrStatus 0
88406.119: <09> DIMMPresence: ErrCode 0
88506.119: <09> DIMMPresence: Done
88606.119:
88706.119: <09><09>DCTPreInit_D: mct_DIMMPresence Done
88806.119: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
88906.119: CBFS: Locating 's3nv'
89006.119: CBFS: Found @ offset 2fec0 size 10000
89106.119: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
89206.119: CBFS: Locating 's3nv'
89306.120: CBFS: Found @ offset 2fec0 size 10000
89406.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
89506.120: CBFS: Locating 'cmos_layout.bin'
89606.120: CBFS: Found @ offset 2b0c0 size e88
89706.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
89806.120: CBFS: Locating 'cmos_layout.bin'
89906.120: CBFS: Found @ offset 2b0c0 size e88
90006.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
90106.120: CBFS: Locating 'cmos_layout.bin'
90206.120: CBFS: Found @ offset 2b0c0 size e88
90306.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
90406.120: CBFS: Locating 'cmos_layout.bin'
90506.120: CBFS: Found @ offset 2b0c0 size e88
90606.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
90706.120: CBFS: Locating 'cmos_layout.bin'
90806.120: CBFS: Found @ offset 2b0c0 size e88
90906.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
91006.121: CBFS: Locating 'cmos_layout.bin'
91106.121: CBFS: Found @ offset 2b0c0 size e88
91206.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
91306.121: CBFS: Locating 'cmos_layout.bin'
91406.121: CBFS: Found @ offset 2b0c0 size e88
91506.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
91606.121: CBFS: Locating 'cmos_layout.bin'
91706.121: CBFS: Found @ offset 2b0c0 size e88
91806.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
91906.121: CBFS: Locating 'cmos_layout.bin'
92006.121: CBFS: Found @ offset 2b0c0 size e88
92106.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
92206.121: CBFS: Locating 'cmos_layout.bin'
92306.121: CBFS: Found @ offset 2b0c0 size e88
92406.122: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
92506.122: CBFS: Locating 'cmos_layout.bin'
92606.122: CBFS: Found @ offset 2b0c0 size e88
92706.122: mctAutoInitMCT_D: mct_init Node 2
92806.122: mctAutoInitMCT_D: mct_InitialMCT_D
92906.122: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
93006.122: mctAutoInitMCT_D: mctSMBhub_Init
93106.122: activate_spd_rom() for node 02
93206.122: enable_spd_node2()
93306.122: mctAutoInitMCT_D: mct_preInitDCT
93406.122: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
93506.122: CBFS: Locating 'cmos_layout.bin'
93606.122: CBFS: Found @ offset 2b0c0 size e88
93707.730: <09> DIMMPresence: DIMMValid=f
93807.730: <09> DIMMPresence: DIMMPresent=f
93907.730: <09> DIMMPresence: RegDIMMPresent=f
94007.730: <09> DIMMPresence: LRDIMMPresent=0
94107.730: <09> DIMMPresence: DimmECCPresent=f
94207.730: <09> DIMMPresence: DimmPARPresent=0
94307.730: <09> DIMMPresence: Dimmx4Present=f
94407.730: <09> DIMMPresence: Dimmx8Present=0
94507.730: <09> DIMMPresence: Dimmx16Present=0
94607.730: <09> DIMMPresence: DimmPlPresent=0
94707.730: <09> DIMMPresence: DimmDRPresent=f
94807.730: <09> DIMMPresence: DimmQRPresent=0
94907.730: <09> DIMMPresence: DATAload[0]=4
95007.730: <09> DIMMPresence: MAload[0]=40
95107.730: <09> DIMMPresence: MAdimms[0]=2
95207.730: <09> DIMMPresence: DATAload[1]=4
95307.730: <09> DIMMPresence: MAload[1]=40
95407.730: <09> DIMMPresence: MAdimms[1]=2
95507.730: <09> DIMMPresence: Status 2005
95607.730: <09> DIMMPresence: ErrStatus 0
95707.730: <09> DIMMPresence: ErrCode 0
95807.730: <09> DIMMPresence: Done
95907.730:
96007.730: <09><09>DCTPreInit_D: mct_DIMMPresence Done
96107.730: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
96207.730: CBFS: Locating 's3nv'
96307.730: CBFS: Found @ offset 2fec0 size 10000
96407.730: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
96507.730: CBFS: Locating 's3nv'
96607.730: CBFS: Found @ offset 2fec0 size 10000
96707.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
96807.731: CBFS: Locating 'cmos_layout.bin'
96907.731: CBFS: Found @ offset 2b0c0 size e88
97007.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
97107.731: CBFS: Locating 'cmos_layout.bin'
97207.731: CBFS: Found @ offset 2b0c0 size e88
97307.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
97407.731: CBFS: Locating 'cmos_layout.bin'
97507.731: CBFS: Found @ offset 2b0c0 size e88
97607.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
97707.731: CBFS: Locating 'cmos_layout.bin'
97807.731: CBFS: Found @ offset 2b0c0 size e88
97907.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
98007.731: CBFS: Locating 'cmos_layout.bin'
98107.731: CBFS: Found @ offset 2b0c0 size e88
98207.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
98307.732: CBFS: Locating 'cmos_layout.bin'
98407.732: CBFS: Found @ offset 2b0c0 size e88
98507.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
98607.732: CBFS: Locating 'cmos_layout.bin'
98707.732: CBFS: Found @ offset 2b0c0 size e88
98807.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
98907.732: CBFS: Locating 'cmos_layout.bin'
99007.732: CBFS: Found @ offset 2b0c0 size e88
99107.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
99207.732: CBFS: Locating 'cmos_layout.bin'
99307.732: CBFS: Found @ offset 2b0c0 size e88
99407.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
99507.732: CBFS: Locating 'cmos_layout.bin'
99607.732: CBFS: Found @ offset 2b0c0 size e88
99707.733: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
99807.733: CBFS: Locating 'cmos_layout.bin'
99907.733: CBFS: Found @ offset 2b0c0 size e88
100007.733: mctAutoInitMCT_D: mct_init Node 3
100107.733: mctAutoInitMCT_D: mct_InitialMCT_D
100207.733: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
100307.733: mctAutoInitMCT_D: mctSMBhub_Init
100407.733: activate_spd_rom() for node 03
100507.733: enable_spd_node3()
100607.733: mctAutoInitMCT_D: mct_preInitDCT
100707.733: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
100807.733: CBFS: Locating 'cmos_layout.bin'
100907.733: CBFS: Found @ offset 2b0c0 size e88
101009.341: <09> DIMMPresence: DIMMValid=f
101109.341: <09> DIMMPresence: DIMMPresent=f
101209.341: <09> DIMMPresence: RegDIMMPresent=f
101309.341: <09> DIMMPresence: LRDIMMPresent=0
101409.341: <09> DIMMPresence: DimmECCPresent=f
101509.341: <09> DIMMPresence: DimmPARPresent=0
101609.341: <09> DIMMPresence: Dimmx4Present=f
101709.341: <09> DIMMPresence: Dimmx8Present=0
101809.341: <09> DIMMPresence: Dimmx16Present=0
101909.341: <09> DIMMPresence: DimmPlPresent=0
102009.341: <09> DIMMPresence: DimmDRPresent=f
102109.341: <09> DIMMPresence: DimmQRPresent=0
102209.341: <09> DIMMPresence: DATAload[0]=4
102309.341: <09> DIMMPresence: MAload[0]=40
102409.341: <09> DIMMPresence: MAdimms[0]=2
102509.341: <09> DIMMPresence: DATAload[1]=4
102609.341: <09> DIMMPresence: MAload[1]=40
102709.341: <09> DIMMPresence: MAdimms[1]=2
102809.341: <09> DIMMPresence: Status 2005
102909.341: <09> DIMMPresence: ErrStatus 0
103009.341: <09> DIMMPresence: ErrCode 0
103109.341: <09> DIMMPresence: Done
103209.341:
103309.341: <09><09>DCTPreInit_D: mct_DIMMPresence Done
103409.341: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
103509.341: CBFS: Locating 's3nv'
103609.342: CBFS: Found @ offset 2fec0 size 10000
103709.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
103809.342: CBFS: Locating 's3nv'
103909.342: CBFS: Found @ offset 2fec0 size 10000
104009.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
104109.342: CBFS: Locating 'cmos_layout.bin'
104209.342: CBFS: Found @ offset 2b0c0 size e88
104309.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
104409.342: CBFS: Locating 'cmos_layout.bin'
104509.342: CBFS: Found @ offset 2b0c0 size e88
104609.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
104709.342: CBFS: Locating 'cmos_layout.bin'
104809.342: CBFS: Found @ offset 2b0c0 size e88
104909.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
105009.342: CBFS: Locating 'cmos_layout.bin'
105109.342: CBFS: Found @ offset 2b0c0 size e88
105209.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
105309.343: CBFS: Locating 'cmos_layout.bin'
105409.343: CBFS: Found @ offset 2b0c0 size e88
105509.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
105609.343: CBFS: Locating 'cmos_layout.bin'
105709.343: CBFS: Found @ offset 2b0c0 size e88
105809.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
105909.343: CBFS: Locating 'cmos_layout.bin'
106009.343: CBFS: Found @ offset 2b0c0 size e88
106109.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
106209.343: CBFS: Locating 'cmos_layout.bin'
106309.343: CBFS: Found @ offset 2b0c0 size e88
106409.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
106509.343: CBFS: Locating 'cmos_layout.bin'
106609.343: CBFS: Found @ offset 2b0c0 size e88
106709.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
106809.344: CBFS: Locating 'cmos_layout.bin'
106909.344: CBFS: Found @ offset 2b0c0 size e88
107009.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
107109.344: CBFS: Locating 'cmos_layout.bin'
107209.344: CBFS: Found @ offset 2b0c0 size e88
107309.344: mctAutoInitMCT_D: mct_init Node 4
107409.344: mctAutoInitMCT_D: mct_init Node 5
107509.344: mctAutoInitMCT_D: mct_init Node 6
107609.344: mctAutoInitMCT_D: mct_init Node 7
107709.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
107809.344: CBFS: Locating 'cmos_layout.bin'
107909.345: CBFS: Found @ offset 2b0c0 size e88
108009.345: mctAutoInitMCT_D: DIMMSetVoltage
108109.345: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
108209.345: CBFS: Locating 'cmos_layout.bin'
108309.345: CBFS: Found @ offset 2b0c0 size e88
108409.346: Node 00 DIMM voltage set to index 00
108509.346: Node 01 DIMM voltage set to index 00
108609.446: mctAutoInitMCT_D: mctSMBhub_Init
108709.446: activate_spd_rom() for node 00
108809.446: enable_spd_node0()
108909.446: mctAutoInitMCT_D: mct_initDCT
109009.446: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
109109.446: CBFS: Locating 'cmos_layout.bin'
109209.446: CBFS: Found @ offset 2b0c0 size e88
109309.446: SPDCalcWidth: Status 2005
109409.446: SPDCalcWidth: ErrStatus 0
109509.446: SPDCalcWidth: ErrCode 0
109609.447: SPDCalcWidth: Done
109709.447: <09><09>DCTInit_D: mct_SPDCalcWidth Done
109809.447: AutoCycTiming_D: Start
109909.447: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
110009.447: CBFS: Locating 'cmos_layout.bin'
110109.447: CBFS: Found @ offset 2b0c0 size e88
110209.447: GetPresetmaxF_D: Start
110309.447: GetPresetmaxF_D: Done
110409.447: SPDGetTCL_D: Start
110509.448: SPDGetTCL_D: DIMMCASL 5
110609.448: SPDGetTCL_D: DIMMAutoSpeed 4
110709.448: SPDGetTCL_D: Status 2005
110809.448: SPDGetTCL_D: ErrStatus 0
110909.448: SPDGetTCL_D: ErrCode 0
111009.448: SPDGetTCL_D: Done
111109.448:
111209.448: SPD2ndTiming: Start
111309.449: SPD2ndTiming: Done
111409.449: AutoCycTiming: Status 2005
111509.449: AutoCycTiming: ErrStatus 0
111609.449: AutoCycTiming: ErrCode 0
111709.449: AutoCycTiming: Done
111809.449:
111909.449: <09><09>DCTInit_D: AutoCycTiming_D Done
112009.450: SPDSetBanks: CSPresent f
112109.450: SPDSetBanks: Status 2005
112209.450: SPDSetBanks: ErrStatus 0
112309.450: SPDSetBanks: ErrCode 0
112409.450: SPDSetBanks: Done
112509.450:
112609.450: AfterStitch pDCTstat->NodeSysBase = 0
112709.450: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
112809.450: StitchMemory: Status 2005
112909.450: StitchMemory: ErrStatus 0
113009.450: StitchMemory: ErrCode 0
113109.450: StitchMemory: Done
113209.450:
113309.450: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
113409.450: CBFS: Locating 'cmos_layout.bin'
113509.450: CBFS: Found @ offset 2b0c0 size e88
113609.451: InterleaveBanks_D: Status 2005
113709.451: InterleaveBanks_D: ErrStatus 0
113809.451: InterleaveBanks_D: ErrCode 0
113909.451: InterleaveBanks_D: Done
114009.451:
114109.451: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
114209.451: CBFS: Locating 'cmos_layout.bin'
114309.451: CBFS: Found @ offset 2b0c0 size e88
114409.452: AutoConfig_D: DramControl: 00002a06
114509.452: AutoConfig_D: DramTimingLo: 00000000
114609.452: AutoConfig_D: DramConfigMisc: 00000000
114709.452: AutoConfig_D: DramConfigMisc2: 00000000
114809.452: AutoConfig_D: DramConfigLo: 03083000
114909.452: AutoConfig_D: DramConfigHi: 0f090084
115009.452: InitDDRPhy: Start
115109.453: InitDDRPhy: Done
115209.453: mct_SetDramConfigHi_D: Start
115309.454: set_2t_configuration: Start
115409.454: set_2t_configuration: Done
115509.454: mct_BeforePlatformSpec: Start
115609.454: mct_BeforePlatformSpec: Done
115709.454: mct_PlatformSpec: Start
115809.454: Programmed DCT 0 timing/termination pattern 00000000 10222222
115909.454: mct_PlatformSpec: Done
116009.454: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
116109.454: *
116209.454: mct_SetDramConfigHi_D: Done
116309.454: mct_EarlyArbEn_D: Start
116409.454: mct_EarlyArbEn_D: Done
116509.454: AutoConfig: Status 2005
116609.454: AutoConfig: ErrStatus 0
116709.454: AutoConfig: ErrCode 0
116809.454: AutoConfig: Done
116909.454:
117009.454: <09><09>DCTInit_D: AutoConfig_D Done
117109.454: <09><09>DCTInit_D: PlatformSpec_D Done
117209.454: <09><09>DCTFinalInit_D: StartupDCT_D Start
117309.455: mct_BeforeDramInit_Prod_D: Start
117409.455: mct_ProgramODT_D: Start
117509.455: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
117609.455: mct_ProgramODT_D: Done
117709.455: mct_BeforeDramInit_Prod_D: Done
117809.455: mct_DramInit_Sw_D: Start
117909.455: mct_DCTAccessDone: Start
118009.455: mct_DCTAccessDone: Done
118109.456: mct_DramControlReg_Init_D: Start
118209.457: mct_DramControlReg_Init_D: F2xA8: 00000300
118309.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
118409.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
118509.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
118609.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
118709.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
118809.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
118909.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
119009.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
119109.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
119209.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
119309.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
119409.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
119509.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
119609.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
119709.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
119809.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
119909.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
120009.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
120109.457: mct_DramControlReg_Init_D: F2xA8: 00000c00
120209.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
120309.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
120409.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
120509.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
120609.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
120709.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
120809.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
120909.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
121009.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
121109.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
121209.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
121309.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
121409.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
121509.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
121609.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
121709.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
121809.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
121909.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
122009.457: mct_DramControlReg_Init_D: Done
122109.458: DIMM 0 RttWr: 2
122209.458: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
122309.458: mct_SendMrsCmd: Start
122409.458: mct_SendMrsCmd: Done
122509.458: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
122609.458: mct_SendMrsCmd: Start
122709.458: mct_SendMrsCmd: Done
122809.459: DIMM 0 RttNom: 3
122909.459: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
123009.459: mct_SendMrsCmd: Start
123109.459: mct_SendMrsCmd: Done
123209.459: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
123309.459: mct_SendMrsCmd: Start
123409.459: mct_SendMrsCmd: Done
123509.459: DIMM 0 RttWr: 2
123609.459: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
123709.459: mct_SendMrsCmd: Start
123809.459: mct_SendMrsCmd: Done
123909.459: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
124009.459: mct_SendMrsCmd: Start
124109.459: mct_SendMrsCmd: Done
124209.459: DIMM 0 RttNom: 3
124309.459: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
124409.459: mct_SendMrsCmd: Start
124509.459: mct_SendMrsCmd: Done
124609.459: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
124709.459: mct_SendMrsCmd: Start
124809.459: mct_SendMrsCmd: Done
124909.459: DIMM 1 RttWr: 2
125009.459: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
125109.459: mct_SendMrsCmd: Start
125209.459: mct_SendMrsCmd: Done
125309.459: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
125409.459: mct_SendMrsCmd: Start
125509.459: mct_SendMrsCmd: Done
125609.459: DIMM 1 RttNom: 3
125709.459: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
125809.459: mct_SendMrsCmd: Start
125909.459: mct_SendMrsCmd: Done
126009.459: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
126109.459: mct_SendMrsCmd: Start
126209.459: mct_SendMrsCmd: Done
126309.459: DIMM 1 RttWr: 2
126409.459: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
126509.459: mct_SendMrsCmd: Start
126609.459: mct_SendMrsCmd: Done
126709.459: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
126809.459: mct_SendMrsCmd: Start
126909.459: mct_SendMrsCmd: Done
127009.459: DIMM 1 RttNom: 3
127109.459: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
127209.459: mct_SendMrsCmd: Start
127309.459: mct_SendMrsCmd: Done
127409.459: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
127509.459: mct_SendMrsCmd: Start
127609.459: mct_SendMrsCmd: Done
127709.459: mct_SendZQCmd: Start
127809.459: mct_SendZQCmd: Done
127909.459: mct_SendZQCmd: Start
128009.459: mct_SendZQCmd: Done
128109.459: mct_DCTAccessDone: Start
128209.460: mct_DCTAccessDone: Done
128309.460: mct_DramInit_Sw_D: Done
128409.460: <09><09>DCTFinalInit_D: StartupDCT_D Done
128509.460: SPDCalcWidth: Status 2005
128609.460: SPDCalcWidth: ErrStatus 0
128709.460: SPDCalcWidth: ErrCode 0
128809.460: SPDCalcWidth: Done
128909.460: <09><09>DCTInit_D: mct_SPDCalcWidth Done
129009.460: AutoCycTiming_D: Start
129109.460: SPD2ndTiming: Start
129209.460: SPD2ndTiming: Done
129309.460: AutoCycTiming: Status 2005
129409.460: AutoCycTiming: ErrStatus 0
129509.460: AutoCycTiming: ErrCode 0
129609.460: AutoCycTiming: Done
129709.460:
129809.460: <09><09>DCTInit_D: AutoCycTiming_D Done
129909.460: <09><09>DCTInit_D: enabling intra-channel clock skew
130009.460: SPDSetBanks: CSPresent f
130109.460: SPDSetBanks: Status 2005
130209.460: SPDSetBanks: ErrStatus 0
130309.460: SPDSetBanks: ErrCode 0
130409.460: SPDSetBanks: Done
130509.460:
130609.460: AfterStitch pDCTstat->NodeSysBase = 0
130709.460: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
130809.460: StitchMemory: Status 2005
130909.460: StitchMemory: ErrStatus 0
131009.460: StitchMemory: ErrCode 0
131109.460: StitchMemory: Done
131209.460:
131309.461: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
131409.461: CBFS: Locating 'cmos_layout.bin'
131509.461: CBFS: Found @ offset 2b0c0 size e88
131609.461: InterleaveBanks_D: Status 2005
131709.461: InterleaveBanks_D: ErrStatus 0
131809.461: InterleaveBanks_D: ErrCode 0
131909.461: InterleaveBanks_D: Done
132009.461:
132109.461: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
132209.461: CBFS: Locating 'cmos_layout.bin'
132309.461: CBFS: Found @ offset 2b0c0 size e88
132409.461: AutoConfig_D: DramControl: 00002a06
132509.461: AutoConfig_D: DramTimingLo: 00000000
132609.461: AutoConfig_D: DramConfigMisc: 00000000
132709.461: AutoConfig_D: DramConfigMisc2: 00000000
132809.461: AutoConfig_D: DramConfigLo: 03083000
132909.461: AutoConfig_D: DramConfigHi: 0f090084
133009.461: InitDDRPhy: Start
133109.461: InitDDRPhy: Done
133209.462: mct_SetDramConfigHi_D: Start
133309.462: set_2t_configuration: Start
133409.462: set_2t_configuration: Done
133509.462: mct_BeforePlatformSpec: Start
133609.462: mct_BeforePlatformSpec: Done
133709.462: mct_PlatformSpec: Start
133809.462: Programmed DCT 1 timing/termination pattern 00000000 10222222
133909.462: mct_PlatformSpec: Done
134009.462: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
134109.462: *
134209.462: mct_SetDramConfigHi_D: Done
134309.462: mct_EarlyArbEn_D: Start
134409.462: mct_EarlyArbEn_D: Done
134509.462: AutoConfig: Status 2005
134609.462: AutoConfig: ErrStatus 0
134709.462: AutoConfig: ErrCode 0
134809.462: AutoConfig: Done
134909.462:
135009.462: <09><09>DCTInit_D: AutoConfig_D Done
135109.462: <09><09>DCTInit_D: PlatformSpec_D Done
135209.462: <09><09>DCTFinalInit_D: StartupDCT_D Start
135309.462: mct_BeforeDramInit_Prod_D: Start
135409.462: mct_ProgramODT_D: Start
135509.462: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
135609.462: mct_ProgramODT_D: Done
135709.462: mct_BeforeDramInit_Prod_D: Done
135809.462: mct_DramInit_Sw_D: Start
135909.462: mct_DCTAccessDone: Start
136009.462: mct_DCTAccessDone: Done
136109.463: mct_DramControlReg_Init_D: Start
136209.463: mct_DramControlReg_Init_D: F2xA8: 00000300
136309.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
136409.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
136509.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
136609.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
136709.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
136809.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
136909.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
137009.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
137109.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
137209.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
137309.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
137409.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
137509.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
137609.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
137709.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
137809.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
137909.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
138009.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
138109.463: mct_DramControlReg_Init_D: F2xA8: 00000c00
138209.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
138309.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
138409.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
138509.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
138609.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
138709.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
138809.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
138909.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
139009.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
139109.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
139209.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
139309.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
139409.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
139509.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
139609.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
139709.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
139809.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
139909.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
140009.463: mct_DramControlReg_Init_D: Done
140109.464: DIMM 0 RttWr: 2
140209.464: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
140309.464: mct_SendMrsCmd: Start
140409.464: mct_SendMrsCmd: Done
140509.464: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
140609.464: mct_SendMrsCmd: Start
140709.464: mct_SendMrsCmd: Done
140809.464: DIMM 0 RttNom: 3
140909.464: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
141009.464: mct_SendMrsCmd: Start
141109.464: mct_SendMrsCmd: Done
141209.464: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
141309.464: mct_SendMrsCmd: Start
141409.464: mct_SendMrsCmd: Done
141509.464: DIMM 0 RttWr: 2
141609.464: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
141709.464: mct_SendMrsCmd: Start
141809.464: mct_SendMrsCmd: Done
141909.464: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
142009.464: mct_SendMrsCmd: Start
142109.464: mct_SendMrsCmd: Done
142209.464: DIMM 0 RttNom: 3
142309.464: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
142409.464: mct_SendMrsCmd: Start
142509.464: mct_SendMrsCmd: Done
142609.464: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
142709.464: mct_SendMrsCmd: Start
142809.464: mct_SendMrsCmd: Done
142909.464: DIMM 1 RttWr: 2
143009.464: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
143109.464: mct_SendMrsCmd: Start
143209.464: mct_SendMrsCmd: Done
143309.464: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
143409.464: mct_SendMrsCmd: Start
143509.464: mct_SendMrsCmd: Done
143609.464: DIMM 1 RttNom: 3
143709.464: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
143809.464: mct_SendMrsCmd: Start
143909.464: mct_SendMrsCmd: Done
144009.464: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
144109.464: mct_SendMrsCmd: Start
144209.464: mct_SendMrsCmd: Done
144309.464: DIMM 1 RttWr: 2
144409.464: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
144509.464: mct_SendMrsCmd: Start
144609.464: mct_SendMrsCmd: Done
144709.464: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
144809.464: mct_SendMrsCmd: Start
144909.464: mct_SendMrsCmd: Done
145009.464: DIMM 1 RttNom: 3
145109.465: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
145209.465: mct_SendMrsCmd: Start
145309.465: mct_SendMrsCmd: Done
145409.465: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
145509.465: mct_SendMrsCmd: Start
145609.465: mct_SendMrsCmd: Done
145709.465: mct_SendZQCmd: Start
145809.465: mct_SendZQCmd: Done
145909.465: mct_SendZQCmd: Start
146009.465: mct_SendZQCmd: Done
146109.465: mct_DCTAccessDone: Start
146209.465: mct_DCTAccessDone: Done
146309.465: mct_DramInit_Sw_D: Done
146409.465: <09><09>DCTFinalInit_D: StartupDCT_D Done
146509.465: mctAutoInitMCT_D: mctSMBhub_Init
146609.465: activate_spd_rom() for node 01
146709.465: enable_spd_node1()
146809.465: mctAutoInitMCT_D: mct_initDCT
146909.465: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
147009.465: CBFS: Locating 'cmos_layout.bin'
147109.465: CBFS: Found @ offset 2b0c0 size e88
147209.465: SPDCalcWidth: Status 2005
147309.465: SPDCalcWidth: ErrStatus 0
147409.465: SPDCalcWidth: ErrCode 0
147509.465: SPDCalcWidth: Done
147609.465: <09><09>DCTInit_D: mct_SPDCalcWidth Done
147709.465: AutoCycTiming_D: Start
147809.465: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
147909.465: CBFS: Locating 'cmos_layout.bin'
148009.465: CBFS: Found @ offset 2b0c0 size e88
148109.466: GetPresetmaxF_D: Start
148209.466: GetPresetmaxF_D: Done
148309.466: SPDGetTCL_D: Start
148409.466: SPDGetTCL_D: DIMMCASL 5
148509.466: SPDGetTCL_D: DIMMAutoSpeed 4
148609.466: SPDGetTCL_D: Status 2005
148709.466: SPDGetTCL_D: ErrStatus 0
148809.466: SPDGetTCL_D: ErrCode 0
148909.466: SPDGetTCL_D: Done
149009.466:
149109.466: SPD2ndTiming: Start
149209.466: SPD2ndTiming: Done
149309.466: AutoCycTiming: Status 2005
149409.466: AutoCycTiming: ErrStatus 0
149509.466: AutoCycTiming: ErrCode 0
149609.466: AutoCycTiming: Done
149709.466:
149809.466: <09><09>DCTInit_D: AutoCycTiming_D Done
149909.466: SPDSetBanks: CSPresent f
150009.466: SPDSetBanks: Status 2005
150109.466: SPDSetBanks: ErrStatus 0
150209.466: SPDSetBanks: ErrCode 0
150309.466: SPDSetBanks: Done
150409.466:
150509.466: AfterStitch pDCTstat->NodeSysBase = 0
150609.466: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
150709.466: StitchMemory: Status 2005
150809.466: StitchMemory: ErrStatus 0
150909.466: StitchMemory: ErrCode 0
151009.466: StitchMemory: Done
151109.466:
151209.466: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
151309.466: CBFS: Locating 'cmos_layout.bin'
151409.466: CBFS: Found @ offset 2b0c0 size e88
151509.467: InterleaveBanks_D: Status 2005
151609.467: InterleaveBanks_D: ErrStatus 0
151709.467: InterleaveBanks_D: ErrCode 0
151809.467: InterleaveBanks_D: Done
151909.467:
152009.467: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
152109.467: CBFS: Locating 'cmos_layout.bin'
152209.467: CBFS: Found @ offset 2b0c0 size e88
152309.467: AutoConfig_D: DramControl: 00002a06
152409.467: AutoConfig_D: DramTimingLo: 00000000
152509.467: AutoConfig_D: DramConfigMisc: 00000000
152609.467: AutoConfig_D: DramConfigMisc2: 00000000
152709.467: AutoConfig_D: DramConfigLo: 03083000
152809.467: AutoConfig_D: DramConfigHi: 0f090084
152909.467: InitDDRPhy: Start
153009.467: InitDDRPhy: Done
153109.467: mct_SetDramConfigHi_D: Start
153209.467: set_2t_configuration: Start
153309.467: set_2t_configuration: Done
153409.467: mct_BeforePlatformSpec: Start
153509.467: mct_BeforePlatformSpec: Done
153609.467: mct_PlatformSpec: Start
153709.467: Programmed DCT 0 timing/termination pattern 00000000 10222222
153809.468: mct_PlatformSpec: Done
153909.467: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
154009.468: *
154109.468: mct_SetDramConfigHi_D: Done
154209.468: mct_EarlyArbEn_D: Start
154309.468: mct_EarlyArbEn_D: Done
154409.468: AutoConfig: Status 2005
154509.468: AutoConfig: ErrStatus 0
154609.468: AutoConfig: ErrCode 0
154709.468: AutoConfig: Done
154809.468:
154909.468: <09><09>DCTInit_D: AutoConfig_D Done
155009.468: <09><09>DCTInit_D: PlatformSpec_D Done
155109.468: <09><09>DCTFinalInit_D: StartupDCT_D Start
155209.468: mct_BeforeDramInit_Prod_D: Start
155309.468: mct_ProgramODT_D: Start
155409.468: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
155509.468: mct_ProgramODT_D: Done
155609.468: mct_BeforeDramInit_Prod_D: Done
155709.468: mct_DramInit_Sw_D: Start
155809.468: mct_DCTAccessDone: Start
155909.468: mct_DCTAccessDone: Done
156009.469: mct_DramControlReg_Init_D: Start
156109.469: mct_DramControlReg_Init_D: F2xA8: 00000300
156209.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
156309.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
156409.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
156509.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
156609.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
156709.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
156809.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
156909.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
157009.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
157109.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
157209.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
157309.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
157409.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
157509.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
157609.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
157709.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
157809.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
157909.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
158009.469: mct_DramControlReg_Init_D: F2xA8: 00000c00
158109.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
158209.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
158309.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
158409.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
158509.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
158609.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
158709.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
158809.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
158909.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
159009.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
159109.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
159209.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
159309.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
159409.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
159509.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
159609.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
159709.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
159809.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
159909.469: mct_DramControlReg_Init_D: Done
160009.469: DIMM 0 RttWr: 2
160109.469: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
160209.469: mct_SendMrsCmd: Start
160309.470: mct_SendMrsCmd: Done
160409.470: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
160509.470: mct_SendMrsCmd: Start
160609.470: mct_SendMrsCmd: Done
160709.470: DIMM 0 RttNom: 3
160809.470: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
160909.470: mct_SendMrsCmd: Start
161009.470: mct_SendMrsCmd: Done
161109.470: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
161209.470: mct_SendMrsCmd: Start
161309.470: mct_SendMrsCmd: Done
161409.470: DIMM 0 RttWr: 2
161509.470: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
161609.470: mct_SendMrsCmd: Start
161709.470: mct_SendMrsCmd: Done
161809.470: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
161909.470: mct_SendMrsCmd: Start
162009.470: mct_SendMrsCmd: Done
162109.470: DIMM 0 RttNom: 3
162209.470: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
162309.470: mct_SendMrsCmd: Start
162409.470: mct_SendMrsCmd: Done
162509.470: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
162609.470: mct_SendMrsCmd: Start
162709.470: mct_SendMrsCmd: Done
162809.470: DIMM 1 RttWr: 2
162909.470: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
163009.470: mct_SendMrsCmd: Start
163109.470: mct_SendMrsCmd: Done
163209.470: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
163309.470: mct_SendMrsCmd: Start
163409.470: mct_SendMrsCmd: Done
163509.470: DIMM 1 RttNom: 3
163609.470: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
163709.470: mct_SendMrsCmd: Start
163809.470: mct_SendMrsCmd: Done
163909.470: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
164009.470: mct_SendMrsCmd: Start
164109.470: mct_SendMrsCmd: Done
164209.470: DIMM 1 RttWr: 2
164309.470: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
164409.470: mct_SendMrsCmd: Start
164509.470: mct_SendMrsCmd: Done
164609.470: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
164709.470: mct_SendMrsCmd: Start
164809.470: mct_SendMrsCmd: Done
164909.470: DIMM 1 RttNom: 3
165009.470: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
165109.470: mct_SendMrsCmd: Start
165209.470: mct_SendMrsCmd: Done
165309.471: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
165409.471: mct_SendMrsCmd: Start
165509.471: mct_SendMrsCmd: Done
165609.471: mct_SendZQCmd: Start
165709.471: mct_SendZQCmd: Done
165809.471: mct_SendZQCmd: Start
165909.471: mct_SendZQCmd: Done
166009.471: mct_DCTAccessDone: Start
166109.471: mct_DCTAccessDone: Done
166209.471: mct_DramInit_Sw_D: Done
166309.471: <09><09>DCTFinalInit_D: StartupDCT_D Done
166409.471: SPDCalcWidth: Status 2005
166509.471: SPDCalcWidth: ErrStatus 0
166609.471: SPDCalcWidth: ErrCode 0
166709.471: SPDCalcWidth: Done
166809.471: <09><09>DCTInit_D: mct_SPDCalcWidth Done
166909.471: AutoCycTiming_D: Start
167009.471: SPD2ndTiming: Start
167109.471: SPD2ndTiming: Done
167209.471: AutoCycTiming: Status 2005
167309.471: AutoCycTiming: ErrStatus 0
167409.471: AutoCycTiming: ErrCode 0
167509.471: AutoCycTiming: Done
167609.471:
167709.471: <09><09>DCTInit_D: AutoCycTiming_D Done
167809.471: <09><09>DCTInit_D: enabling intra-channel clock skew
167909.471: SPDSetBanks: CSPresent f
168009.471: SPDSetBanks: Status 2005
168109.471: SPDSetBanks: ErrStatus 0
168209.471: SPDSetBanks: ErrCode 0
168309.471: SPDSetBanks: Done
168409.471:
168509.471: AfterStitch pDCTstat->NodeSysBase = 0
168609.471: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
168709.471: StitchMemory: Status 2005
168809.471: StitchMemory: ErrStatus 0
168909.471: StitchMemory: ErrCode 0
169009.472: StitchMemory: Done
169109.471:
169209.472: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
169309.472: CBFS: Locating 'cmos_layout.bin'
169409.472: CBFS: Found @ offset 2b0c0 size e88
169509.472: InterleaveBanks_D: Status 2005
169609.472: InterleaveBanks_D: ErrStatus 0
169709.472: InterleaveBanks_D: ErrCode 0
169809.472: InterleaveBanks_D: Done
169909.472:
170009.472: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
170109.472: CBFS: Locating 'cmos_layout.bin'
170209.472: CBFS: Found @ offset 2b0c0 size e88
170309.472: AutoConfig_D: DramControl: 00002a06
170409.472: AutoConfig_D: DramTimingLo: 00000000
170509.472: AutoConfig_D: DramConfigMisc: 00000000
170609.472: AutoConfig_D: DramConfigMisc2: 00000000
170709.472: AutoConfig_D: DramConfigLo: 03083000
170809.472: AutoConfig_D: DramConfigHi: 0f090084
170909.472: InitDDRPhy: Start
171009.472: InitDDRPhy: Done
171109.472: mct_SetDramConfigHi_D: Start
171209.472: set_2t_configuration: Start
171309.472: set_2t_configuration: Done
171409.473: mct_BeforePlatformSpec: Start
171509.472: mct_BeforePlatformSpec: Done
171609.473: mct_PlatformSpec: Start
171709.473: Programmed DCT 1 timing/termination pattern 00000000 10222222
171809.473: mct_PlatformSpec: Done
171909.473: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
172009.473: *
172109.473: mct_SetDramConfigHi_D: Done
172209.473: mct_EarlyArbEn_D: Start
172309.473: mct_EarlyArbEn_D: Done
172409.473: AutoConfig: Status 2005
172509.473: AutoConfig: ErrStatus 0
172609.473: AutoConfig: ErrCode 0
172709.473: AutoConfig: Done
172809.473:
172909.473: <09><09>DCTInit_D: AutoConfig_D Done
173009.473: <09><09>DCTInit_D: PlatformSpec_D Done
173109.473: <09><09>DCTFinalInit_D: StartupDCT_D Start
173209.473: mct_BeforeDramInit_Prod_D: Start
173309.473: mct_ProgramODT_D: Start
173409.473: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
173509.473: mct_ProgramODT_D: Done
173609.473: mct_BeforeDramInit_Prod_D: Done
173709.473: mct_DramInit_Sw_D: Start
173809.473: mct_DCTAccessDone: Start
173909.473: mct_DCTAccessDone: Done
174009.474: mct_DramControlReg_Init_D: Start
174109.474: mct_DramControlReg_Init_D: F2xA8: 00000300
174209.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
174309.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
174409.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
174509.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
174609.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
174709.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
174809.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
174909.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
175009.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
175109.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
175209.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
175309.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
175409.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
175509.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
175609.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
175709.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
175809.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
175909.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
176009.474: mct_DramControlReg_Init_D: F2xA8: 00000c00
176109.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
176209.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
176309.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
176409.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
176509.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
176609.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
176709.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
176809.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
176909.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
177009.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
177109.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
177209.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
177309.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
177409.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
177509.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
177609.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
177709.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
177809.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
177909.474: mct_DramControlReg_Init_D: Done
178009.474: DIMM 0 RttWr: 2
178109.475: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
178209.475: mct_SendMrsCmd: Start
178309.475: mct_SendMrsCmd: Done
178409.475: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
178509.475: mct_SendMrsCmd: Start
178609.475: mct_SendMrsCmd: Done
178709.475: DIMM 0 RttNom: 3
178809.475: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
178909.475: mct_SendMrsCmd: Start
179009.475: mct_SendMrsCmd: Done
179109.475: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
179209.475: mct_SendMrsCmd: Start
179309.475: mct_SendMrsCmd: Done
179409.475: DIMM 0 RttWr: 2
179509.475: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
179609.475: mct_SendMrsCmd: Start
179709.475: mct_SendMrsCmd: Done
179809.475: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
179909.475: mct_SendMrsCmd: Start
180009.475: mct_SendMrsCmd: Done
180109.475: DIMM 0 RttNom: 3
180209.475: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
180309.475: mct_SendMrsCmd: Start
180409.475: mct_SendMrsCmd: Done
180509.475: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
180609.475: mct_SendMrsCmd: Start
180709.475: mct_SendMrsCmd: Done
180809.475: DIMM 1 RttWr: 2
180909.475: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
181009.475: mct_SendMrsCmd: Start
181109.475: mct_SendMrsCmd: Done
181209.475: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
181309.475: mct_SendMrsCmd: Start
181409.475: mct_SendMrsCmd: Done
181509.475: DIMM 1 RttNom: 3
181609.475: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
181709.475: mct_SendMrsCmd: Start
181809.475: mct_SendMrsCmd: Done
181909.475: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
182009.475: mct_SendMrsCmd: Start
182109.475: mct_SendMrsCmd: Done
182209.475: DIMM 1 RttWr: 2
182309.475: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
182409.475: mct_SendMrsCmd: Start
182509.475: mct_SendMrsCmd: Done
182609.475: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
182709.475: mct_SendMrsCmd: Start
182809.475: mct_SendMrsCmd: Done
182909.475: DIMM 1 RttNom: 3
183009.475: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
183109.475: mct_SendMrsCmd: Start
183209.475: mct_SendMrsCmd: Done
183309.476: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
183409.476: mct_SendMrsCmd: Start
183509.476: mct_SendMrsCmd: Done
183609.476: mct_SendZQCmd: Start
183709.476: mct_SendZQCmd: Done
183809.476: mct_SendZQCmd: Start
183909.476: mct_SendZQCmd: Done
184009.476: mct_DCTAccessDone: Start
184109.476: mct_DCTAccessDone: Done
184209.476: mct_DramInit_Sw_D: Done
184309.476: <09><09>DCTFinalInit_D: StartupDCT_D Done
184409.476: mctAutoInitMCT_D: mctSMBhub_Init
184509.476: activate_spd_rom() for node 02
184609.476: enable_spd_node2()
184709.476: mctAutoInitMCT_D: mct_initDCT
184809.476: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
184909.476: CBFS: Locating 'cmos_layout.bin'
185009.476: CBFS: Found @ offset 2b0c0 size e88
185109.476: SPDCalcWidth: Status 2005
185209.476: SPDCalcWidth: ErrStatus 0
185309.476: SPDCalcWidth: ErrCode 0
185409.476: SPDCalcWidth: Done
185509.476: <09><09>DCTInit_D: mct_SPDCalcWidth Done
185609.476: AutoCycTiming_D: Start
185709.476: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
185809.476: CBFS: Locating 'cmos_layout.bin'
185909.476: CBFS: Found @ offset 2b0c0 size e88
186009.476: GetPresetmaxF_D: Start
186109.476: GetPresetmaxF_D: Done
186209.476: SPDGetTCL_D: Start
186309.477: SPDGetTCL_D: DIMMCASL 5
186409.477: SPDGetTCL_D: DIMMAutoSpeed 4
186509.477: SPDGetTCL_D: Status 2005
186609.477: SPDGetTCL_D: ErrStatus 0
186709.477: SPDGetTCL_D: ErrCode 0
186809.477: SPDGetTCL_D: Done
186909.477:
187009.477: SPD2ndTiming: Start
187109.477: SPD2ndTiming: Done
187209.477: AutoCycTiming: Status 2005
187309.477: AutoCycTiming: ErrStatus 0
187409.477: AutoCycTiming: ErrCode 0
187509.477: AutoCycTiming: Done
187609.477:
187709.477: <09><09>DCTInit_D: AutoCycTiming_D Done
187809.477: SPDSetBanks: CSPresent f
187909.477: SPDSetBanks: Status 2005
188009.477: SPDSetBanks: ErrStatus 0
188109.477: SPDSetBanks: ErrCode 0
188209.477: SPDSetBanks: Done
188309.477:
188409.477: AfterStitch pDCTstat->NodeSysBase = 0
188509.477: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
188609.477: StitchMemory: Status 2005
188709.477: StitchMemory: ErrStatus 0
188809.477: StitchMemory: ErrCode 0
188909.477: StitchMemory: Done
189009.477:
189109.477: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
189209.477: CBFS: Locating 'cmos_layout.bin'
189309.477: CBFS: Found @ offset 2b0c0 size e88
189409.478: InterleaveBanks_D: Status 2005
189509.478: InterleaveBanks_D: ErrStatus 0
189609.478: InterleaveBanks_D: ErrCode 0
189709.478: InterleaveBanks_D: Done
189809.478:
189909.478: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
190009.478: CBFS: Locating 'cmos_layout.bin'
190109.478: CBFS: Found @ offset 2b0c0 size e88
190209.478: AutoConfig_D: DramControl: 00002a06
190309.478: AutoConfig_D: DramTimingLo: 00000000
190409.478: AutoConfig_D: DramConfigMisc: 00000000
190509.478: AutoConfig_D: DramConfigMisc2: 00000000
190609.478: AutoConfig_D: DramConfigLo: 03083000
190709.478: AutoConfig_D: DramConfigHi: 0f090084
190809.478: InitDDRPhy: Start
190909.478: InitDDRPhy: Done
191009.478: mct_SetDramConfigHi_D: Start
191109.478: set_2t_configuration: Start
191209.478: set_2t_configuration: Done
191309.478: mct_BeforePlatformSpec: Start
191409.478: mct_BeforePlatformSpec: Done
191509.478: mct_PlatformSpec: Start
191609.478: Programmed DCT 0 timing/termination pattern 00000000 10222222
191709.478: mct_PlatformSpec: Done
191809.478: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
191909.478: *
192009.478: mct_SetDramConfigHi_D: Done
192109.478: mct_EarlyArbEn_D: Start
192209.478: mct_EarlyArbEn_D: Done
192309.478: AutoConfig: Status 2005
192409.479: AutoConfig: ErrStatus 0
192509.478: AutoConfig: ErrCode 0
192609.479: AutoConfig: Done
192709.478:
192809.479: <09><09>DCTInit_D: AutoConfig_D Done
192909.479: <09><09>DCTInit_D: PlatformSpec_D Done
193009.479: <09><09>DCTFinalInit_D: StartupDCT_D Start
193109.479: mct_BeforeDramInit_Prod_D: Start
193209.479: mct_ProgramODT_D: Start
193309.479: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
193409.479: mct_ProgramODT_D: Done
193509.479: mct_BeforeDramInit_Prod_D: Done
193609.479: mct_DramInit_Sw_D: Start
193709.479: mct_DCTAccessDone: Start
193809.479: mct_DCTAccessDone: Done
193909.480: mct_DramControlReg_Init_D: Start
194009.480: mct_DramControlReg_Init_D: F2xA8: 00000300
194109.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
194209.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
194309.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
194409.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
194509.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
194609.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
194709.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
194809.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
194909.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
195009.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
195109.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
195209.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
195309.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
195409.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
195509.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
195609.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
195709.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
195809.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
195909.480: mct_DramControlReg_Init_D: F2xA8: 00000c00
196009.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
196109.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
196209.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
196309.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
196409.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
196509.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
196609.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
196709.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
196809.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
196909.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
197009.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
197109.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
197209.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
197309.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
197409.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
197509.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
197609.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
197709.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
197809.480: mct_DramControlReg_Init_D: Done
197909.480: DIMM 0 RttWr: 2
198009.480: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
198109.480: mct_SendMrsCmd: Start
198209.480: mct_SendMrsCmd: Done
198309.480: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
198409.480: mct_SendMrsCmd: Start
198509.480: mct_SendMrsCmd: Done
198609.481: DIMM 0 RttNom: 3
198709.481: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
198809.481: mct_SendMrsCmd: Start
198909.481: mct_SendMrsCmd: Done
199009.481: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
199109.481: mct_SendMrsCmd: Start
199209.481: mct_SendMrsCmd: Done
199309.481: DIMM 0 RttWr: 2
199409.481: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
199509.481: mct_SendMrsCmd: Start
199609.481: mct_SendMrsCmd: Done
199709.481: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
199809.481: mct_SendMrsCmd: Start
199909.481: mct_SendMrsCmd: Done
200009.481: DIMM 0 RttNom: 3
200109.481: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
200209.481: mct_SendMrsCmd: Start
200309.481: mct_SendMrsCmd: Done
200409.481: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
200509.481: mct_SendMrsCmd: Start
200609.481: mct_SendMrsCmd: Done
200709.481: DIMM 1 RttWr: 2
200809.481: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
200909.481: mct_SendMrsCmd: Start
201009.481: mct_SendMrsCmd: Done
201109.481: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
201209.481: mct_SendMrsCmd: Start
201309.481: mct_SendMrsCmd: Done
201409.481: DIMM 1 RttNom: 3
201509.481: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
201609.481: mct_SendMrsCmd: Start
201709.481: mct_SendMrsCmd: Done
201809.481: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
201909.481: mct_SendMrsCmd: Start
202009.481: mct_SendMrsCmd: Done
202109.481: DIMM 1 RttWr: 2
202209.481: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
202309.481: mct_SendMrsCmd: Start
202409.481: mct_SendMrsCmd: Done
202509.481: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
202609.481: mct_SendMrsCmd: Start
202709.481: mct_SendMrsCmd: Done
202809.481: DIMM 1 RttNom: 3
202909.481: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
203009.481: mct_SendMrsCmd: Start
203109.481: mct_SendMrsCmd: Done
203209.481: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
203309.481: mct_SendMrsCmd: Start
203409.481: mct_SendMrsCmd: Done
203509.481: mct_SendZQCmd: Start
203609.481: mct_SendZQCmd: Done
203709.481: mct_SendZQCmd: Start
203809.481: mct_SendZQCmd: Done
203909.481: mct_DCTAccessDone: Start
204009.481: mct_DCTAccessDone: Done
204109.481: mct_DramInit_Sw_D: Done
204209.481: <09><09>DCTFinalInit_D: StartupDCT_D Done
204309.481: SPDCalcWidth: Status 2005
204409.481: SPDCalcWidth: ErrStatus 0
204509.482: SPDCalcWidth: ErrCode 0
204609.481: SPDCalcWidth: Done
204709.482: <09><09>DCTInit_D: mct_SPDCalcWidth Done
204809.482: AutoCycTiming_D: Start
204909.482: SPD2ndTiming: Start
205009.482: SPD2ndTiming: Done
205109.482: AutoCycTiming: Status 2005
205209.482: AutoCycTiming: ErrStatus 0
205309.482: AutoCycTiming: ErrCode 0
205409.482: AutoCycTiming: Done
205509.482:
205609.482: <09><09>DCTInit_D: AutoCycTiming_D Done
205709.482: <09><09>DCTInit_D: enabling intra-channel clock skew
205809.482: SPDSetBanks: CSPresent f
205909.482: SPDSetBanks: Status 2005
206009.482: SPDSetBanks: ErrStatus 0
206109.482: SPDSetBanks: ErrCode 0
206209.482: SPDSetBanks: Done
206309.482:
206409.482: AfterStitch pDCTstat->NodeSysBase = 0
206509.482: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
206609.482: StitchMemory: Status 2005
206709.482: StitchMemory: ErrStatus 0
206809.482: StitchMemory: ErrCode 0
206909.482: StitchMemory: Done
207009.482:
207109.482: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
207209.482: CBFS: Locating 'cmos_layout.bin'
207309.482: CBFS: Found @ offset 2b0c0 size e88
207409.483: InterleaveBanks_D: Status 2005
207509.483: InterleaveBanks_D: ErrStatus 0
207609.483: InterleaveBanks_D: ErrCode 0
207709.483: InterleaveBanks_D: Done
207809.483:
207909.483: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
208009.483: CBFS: Locating 'cmos_layout.bin'
208109.483: CBFS: Found @ offset 2b0c0 size e88
208209.483: AutoConfig_D: DramControl: 00002a06
208309.483: AutoConfig_D: DramTimingLo: 00000000
208409.483: AutoConfig_D: DramConfigMisc: 00000000
208509.483: AutoConfig_D: DramConfigMisc2: 00000000
208609.483: AutoConfig_D: DramConfigLo: 03083000
208709.483: AutoConfig_D: DramConfigHi: 0f090084
208809.483: InitDDRPhy: Start
208909.483: InitDDRPhy: Done
209009.483: mct_SetDramConfigHi_D: Start
209109.483: set_2t_configuration: Start
209209.483: set_2t_configuration: Done
209309.483: mct_BeforePlatformSpec: Start
209409.483: mct_BeforePlatformSpec: Done
209509.483: mct_PlatformSpec: Start
209609.483: Programmed DCT 1 timing/termination pattern 00000000 10222222
209709.483: mct_PlatformSpec: Done
209809.483: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
209909.483: *
210009.483: mct_SetDramConfigHi_D: Done
210109.483: mct_EarlyArbEn_D: Start
210209.483: mct_EarlyArbEn_D: Done
210309.483: AutoConfig: Status 2005
210409.483: AutoConfig: ErrStatus 0
210509.483: AutoConfig: ErrCode 0
210609.483: AutoConfig: Done
210709.483:
210809.483: <09><09>DCTInit_D: AutoConfig_D Done
210909.484: <09><09>DCTInit_D: PlatformSpec_D Done
211009.484: <09><09>DCTFinalInit_D: StartupDCT_D Start
211109.484: mct_BeforeDramInit_Prod_D: Start
211209.484: mct_ProgramODT_D: Start
211309.484: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
211409.484: mct_ProgramODT_D: Done
211509.484: mct_BeforeDramInit_Prod_D: Done
211609.484: mct_DramInit_Sw_D: Start
211709.484: mct_DCTAccessDone: Start
211809.484: mct_DCTAccessDone: Done
211909.485: mct_DramControlReg_Init_D: Start
212009.485: mct_DramControlReg_Init_D: F2xA8: 00000300
212109.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
212209.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
212309.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
212409.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
212509.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
212609.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
212709.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
212809.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
212909.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
213009.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
213109.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
213209.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
213309.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
213409.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
213509.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
213609.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
213709.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
213809.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
213909.485: mct_DramControlReg_Init_D: F2xA8: 00000c00
214009.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
214109.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
214209.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
214309.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
214409.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
214509.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
214609.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
214709.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
214809.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
214909.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
215009.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
215109.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
215209.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
215309.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
215409.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
215509.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
215609.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
215709.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
215809.485: mct_DramControlReg_Init_D: Done
215909.485: DIMM 0 RttWr: 2
216009.485: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
216109.485: mct_SendMrsCmd: Start
216209.485: mct_SendMrsCmd: Done
216309.485: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
216409.485: mct_SendMrsCmd: Start
216509.485: mct_SendMrsCmd: Done
216609.485: DIMM 0 RttNom: 3
216709.486: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
216809.486: mct_SendMrsCmd: Start
216909.486: mct_SendMrsCmd: Done
217009.486: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
217109.486: mct_SendMrsCmd: Start
217209.486: mct_SendMrsCmd: Done
217309.486: DIMM 0 RttWr: 2
217409.486: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
217509.486: mct_SendMrsCmd: Start
217609.486: mct_SendMrsCmd: Done
217709.486: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
217809.486: mct_SendMrsCmd: Start
217909.486: mct_SendMrsCmd: Done
218009.486: DIMM 0 RttNom: 3
218109.486: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
218209.486: mct_SendMrsCmd: Start
218309.486: mct_SendMrsCmd: Done
218409.486: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
218509.486: mct_SendMrsCmd: Start
218609.486: mct_SendMrsCmd: Done
218709.486: DIMM 1 RttWr: 2
218809.486: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
218909.486: mct_SendMrsCmd: Start
219009.486: mct_SendMrsCmd: Done
219109.486: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
219209.486: mct_SendMrsCmd: Start
219309.486: mct_SendMrsCmd: Done
219409.486: DIMM 1 RttNom: 3
219509.486: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
219609.486: mct_SendMrsCmd: Start
219709.486: mct_SendMrsCmd: Done
219809.486: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
219909.486: mct_SendMrsCmd: Start
220009.486: mct_SendMrsCmd: Done
220109.486: DIMM 1 RttWr: 2
220209.486: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
220309.486: mct_SendMrsCmd: Start
220409.486: mct_SendMrsCmd: Done
220509.486: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
220609.486: mct_SendMrsCmd: Start
220709.486: mct_SendMrsCmd: Done
220809.486: DIMM 1 RttNom: 3
220909.486: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
221009.486: mct_SendMrsCmd: Start
221109.486: mct_SendMrsCmd: Done
221209.486: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
221309.486: mct_SendMrsCmd: Start
221409.486: mct_SendMrsCmd: Done
221509.486: mct_SendZQCmd: Start
221609.486: mct_SendZQCmd: Done
221709.486: mct_SendZQCmd: Start
221809.486: mct_SendZQCmd: Done
221909.486: mct_DCTAccessDone: Start
222009.486: mct_DCTAccessDone: Done
222109.486: mct_DramInit_Sw_D: Done
222209.486: <09><09>DCTFinalInit_D: StartupDCT_D Done
222309.486: mctAutoInitMCT_D: mctSMBhub_Init
222409.486: activate_spd_rom() for node 03
222509.486: enable_spd_node3()
222609.486: mctAutoInitMCT_D: mct_initDCT
222709.486: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
222809.486: CBFS: Locating 'cmos_layout.bin'
222909.486: CBFS: Found @ offset 2b0c0 size e88
223009.487: SPDCalcWidth: Status 2005
223109.487: SPDCalcWidth: ErrStatus 0
223209.487: SPDCalcWidth: ErrCode 0
223309.487: SPDCalcWidth: Done
223409.487: <09><09>DCTInit_D: mct_SPDCalcWidth Done
223509.487: AutoCycTiming_D: Start
223609.487: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
223709.487: CBFS: Locating 'cmos_layout.bin'
223809.487: CBFS: Found @ offset 2b0c0 size e88
223909.487: GetPresetmaxF_D: Start
224009.487: GetPresetmaxF_D: Done
224109.487: SPDGetTCL_D: Start
224209.487: SPDGetTCL_D: DIMMCASL 5
224309.487: SPDGetTCL_D: DIMMAutoSpeed 4
224409.487: SPDGetTCL_D: Status 2005
224509.487: SPDGetTCL_D: ErrStatus 0
224609.487: SPDGetTCL_D: ErrCode 0
224709.487: SPDGetTCL_D: Done
224809.487:
224909.487: SPD2ndTiming: Start
225009.487: SPD2ndTiming: Done
225109.487: AutoCycTiming: Status 2005
225209.487: AutoCycTiming: ErrStatus 0
225309.487: AutoCycTiming: ErrCode 0
225409.487: AutoCycTiming: Done
225509.487:
225609.487: <09><09>DCTInit_D: AutoCycTiming_D Done
225709.488: SPDSetBanks: CSPresent f
225809.488: SPDSetBanks: Status 2005
225909.488: SPDSetBanks: ErrStatus 0
226009.488: SPDSetBanks: ErrCode 0
226109.488: SPDSetBanks: Done
226209.488:
226309.488: AfterStitch pDCTstat->NodeSysBase = 0
226409.488: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
226509.488: StitchMemory: Status 2005
226609.488: StitchMemory: ErrStatus 0
226709.488: StitchMemory: ErrCode 0
226809.488: StitchMemory: Done
226909.488:
227009.488: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
227109.488: CBFS: Locating 'cmos_layout.bin'
227209.488: CBFS: Found @ offset 2b0c0 size e88
227309.488: InterleaveBanks_D: Status 2005
227409.488: InterleaveBanks_D: ErrStatus 0
227509.488: InterleaveBanks_D: ErrCode 0
227609.488: InterleaveBanks_D: Done
227709.488:
227809.488: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
227909.488: CBFS: Locating 'cmos_layout.bin'
228009.488: CBFS: Found @ offset 2b0c0 size e88
228109.489: AutoConfig_D: DramControl: 00002a06
228209.489: AutoConfig_D: DramTimingLo: 00000000
228309.489: AutoConfig_D: DramConfigMisc: 00000000
228409.489: AutoConfig_D: DramConfigMisc2: 00000000
228509.489: AutoConfig_D: DramConfigLo: 03083000
228609.489: AutoConfig_D: DramConfigHi: 0f090084
228709.489: InitDDRPhy: Start
228809.489: InitDDRPhy: Done
228909.489: mct_SetDramConfigHi_D: Start
229009.489: set_2t_configuration: Start
229109.489: set_2t_configuration: Done
229209.489: mct_BeforePlatformSpec: Start
229309.489: mct_BeforePlatformSpec: Done
229409.489: mct_PlatformSpec: Start
229509.489: Programmed DCT 0 timing/termination pattern 00000000 10222222
229609.489: mct_PlatformSpec: Done
229709.489: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
229809.489: *
229909.489: mct_SetDramConfigHi_D: Done
230009.489: mct_EarlyArbEn_D: Start
230109.489: mct_EarlyArbEn_D: Done
230209.489: AutoConfig: Status 2005
230309.489: AutoConfig: ErrStatus 0
230409.489: AutoConfig: ErrCode 0
230509.489: AutoConfig: Done
230609.489:
230709.489: <09><09>DCTInit_D: AutoConfig_D Done
230809.489: <09><09>DCTInit_D: PlatformSpec_D Done
230909.489: <09><09>DCTFinalInit_D: StartupDCT_D Start
231009.489: mct_BeforeDramInit_Prod_D: Start
231109.489: mct_ProgramODT_D: Start
231209.489: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
231309.489: mct_ProgramODT_D: Done
231409.489: mct_BeforeDramInit_Prod_D: Done
231509.489: mct_DramInit_Sw_D: Start
231609.489: mct_DCTAccessDone: Start
231709.489: mct_DCTAccessDone: Done
231809.490: mct_DramControlReg_Init_D: Start
231909.490: mct_DramControlReg_Init_D: F2xA8: 00000300
232009.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
232109.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
232209.490: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
232309.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
232409.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
232509.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
232609.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
232709.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
232809.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
232909.490: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
233009.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
233109.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
233209.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
233309.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
233409.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
233509.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
233609.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
233709.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
233809.490: mct_DramControlReg_Init_D: F2xA8: 00000c00
233909.490: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
234009.490: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
234109.491: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
234209.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
234309.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
234409.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
234509.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
234609.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
234709.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
234809.491: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
234909.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
235009.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
235109.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
235209.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
235309.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
235409.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
235509.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
235609.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
235709.491: mct_DramControlReg_Init_D: Done
235809.491: DIMM 0 RttWr: 2
235909.491: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
236009.491: mct_SendMrsCmd: Start
236109.491: mct_SendMrsCmd: Done
236209.491: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
236309.491: mct_SendMrsCmd: Start
236409.491: mct_SendMrsCmd: Done
236509.491: DIMM 0 RttNom: 3
236609.491: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
236709.491: mct_SendMrsCmd: Start
236809.491: mct_SendMrsCmd: Done
236909.491: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
237009.491: mct_SendMrsCmd: Start
237109.491: mct_SendMrsCmd: Done
237209.491: DIMM 0 RttWr: 2
237309.492: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
237409.492: mct_SendMrsCmd: Start
237509.492: mct_SendMrsCmd: Done
237609.492: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
237709.492: mct_SendMrsCmd: Start
237809.492: mct_SendMrsCmd: Done
237909.492: DIMM 0 RttNom: 3
238009.492: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
238109.492: mct_SendMrsCmd: Start
238209.492: mct_SendMrsCmd: Done
238309.492: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
238409.492: mct_SendMrsCmd: Start
238509.492: mct_SendMrsCmd: Done
238609.492: DIMM 1 RttWr: 2
238709.492: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
238809.492: mct_SendMrsCmd: Start
238909.492: mct_SendMrsCmd: Done
239009.492: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
239109.492: mct_SendMrsCmd: Start
239209.492: mct_SendMrsCmd: Done
239309.492: DIMM 1 RttNom: 3
239409.492: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
239509.492: mct_SendMrsCmd: Start
239609.492: mct_SendMrsCmd: Done
239709.492: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
239809.492: mct_SendMrsCmd: Start
239909.492: mct_SendMrsCmd: Done
240009.492: DIMM 1 RttWr: 2
240109.492: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
240209.492: mct_SendMrsCmd: Start
240309.492: mct_SendMrsCmd: Done
240409.492: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
240509.492: mct_SendMrsCmd: Start
240609.492: mct_SendMrsCmd: Done
240709.492: DIMM 1 RttNom: 3
240809.492: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
240909.492: mct_SendMrsCmd: Start
241009.492: mct_SendMrsCmd: Done
241109.492: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
241209.492: mct_SendMrsCmd: Start
241309.492: mct_SendMrsCmd: Done
241409.492: mct_SendZQCmd: Start
241509.492: mct_SendZQCmd: Done
241609.492: mct_SendZQCmd: Start
241709.492: mct_SendZQCmd: Done
241809.492: mct_DCTAccessDone: Start
241909.492: mct_DCTAccessDone: Done
242009.492: mct_DramInit_Sw_D: Done
242109.492: <09><09>DCTFinalInit_D: StartupDCT_D Done
242209.492: SPDCalcWidth: Status 2005
242309.492: SPDCalcWidth: ErrStatus 0
242409.492: SPDCalcWidth: ErrCode 0
242509.492: SPDCalcWidth: Done
242609.492: <09><09>DCTInit_D: mct_SPDCalcWidth Done
242709.492: AutoCycTiming_D: Start
242809.492: SPD2ndTiming: Start
242909.492: SPD2ndTiming: Done
243009.492: AutoCycTiming: Status 2005
243109.492: AutoCycTiming: ErrStatus 0
243209.492: AutoCycTiming: ErrCode 0
243309.492: AutoCycTiming: Done
243409.492:
243509.492: <09><09>DCTInit_D: AutoCycTiming_D Done
243609.492: <09><09>DCTInit_D: enabling intra-channel clock skew
243709.493: SPDSetBanks: CSPresent f
243809.493: SPDSetBanks: Status 2005
243909.493: SPDSetBanks: ErrStatus 0
244009.493: SPDSetBanks: ErrCode 0
244109.493: SPDSetBanks: Done
244209.493:
244309.493: AfterStitch pDCTstat->NodeSysBase = 0
244409.493: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
244509.493: StitchMemory: Status 2005
244609.493: StitchMemory: ErrStatus 0
244709.493: StitchMemory: ErrCode 0
244809.493: StitchMemory: Done
244909.493:
245009.493: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245109.493: CBFS: Locating 'cmos_layout.bin'
245209.493: CBFS: Found @ offset 2b0c0 size e88
245309.493: InterleaveBanks_D: Status 2005
245409.493: InterleaveBanks_D: ErrStatus 0
245509.493: InterleaveBanks_D: ErrCode 0
245609.493: InterleaveBanks_D: Done
245709.493:
245809.494: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245909.494: CBFS: Locating 'cmos_layout.bin'
246009.494: CBFS: Found @ offset 2b0c0 size e88
246109.494: AutoConfig_D: DramControl: 00002a06
246209.494: AutoConfig_D: DramTimingLo: 00000000
246309.494: AutoConfig_D: DramConfigMisc: 00000000
246409.494: AutoConfig_D: DramConfigMisc2: 00000000
246509.494: AutoConfig_D: DramConfigLo: 03083000
246609.494: AutoConfig_D: DramConfigHi: 0f090084
246709.494: InitDDRPhy: Start
246809.494: InitDDRPhy: Done
246909.494: mct_SetDramConfigHi_D: Start
247009.494: set_2t_configuration: Start
247109.494: set_2t_configuration: Done
247209.494: mct_BeforePlatformSpec: Start
247309.494: mct_BeforePlatformSpec: Done
247409.494: mct_PlatformSpec: Start
247509.494: Programmed DCT 1 timing/termination pattern 00000000 10222222
247609.494: mct_PlatformSpec: Done
247709.494: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
247809.494: *
247909.494: mct_SetDramConfigHi_D: Done
248009.494: mct_EarlyArbEn_D: Start
248109.494: mct_EarlyArbEn_D: Done
248209.494: AutoConfig: Status 2005
248309.494: AutoConfig: ErrStatus 0
248409.494: AutoConfig: ErrCode 0
248509.494: AutoConfig: Done
248609.494:
248709.494: <09><09>DCTInit_D: AutoConfig_D Done
248809.494: <09><09>DCTInit_D: PlatformSpec_D Done
248909.494: <09><09>DCTFinalInit_D: StartupDCT_D Start
249009.494: mct_BeforeDramInit_Prod_D: Start
249109.494: mct_ProgramODT_D: Start
249209.494: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
249309.494: mct_ProgramODT_D: Done
249409.494: mct_BeforeDramInit_Prod_D: Done
249509.494: mct_DramInit_Sw_D: Start
249609.494: mct_DCTAccessDone: Start
249709.494: mct_DCTAccessDone: Done
249809.495: mct_DramControlReg_Init_D: Start
249909.495: mct_DramControlReg_Init_D: F2xA8: 00000300
250009.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
250109.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
250209.495: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
250309.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
250409.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
250509.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
250609.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
250709.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
250809.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
250909.495: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
251009.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
251109.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
251209.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
251309.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
251409.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
251509.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
251609.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
251709.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
251809.496: mct_DramControlReg_Init_D: F2xA8: 00000c00
251909.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
252009.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
252109.496: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
252209.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
252309.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
252409.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
252509.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
252609.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
252709.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
252809.496: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
252909.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
253009.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
253109.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
253209.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
253309.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
253409.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
253509.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
253609.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
253709.496: mct_DramControlReg_Init_D: Done
253809.496: DIMM 0 RttWr: 2
253909.496: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
254009.496: mct_SendMrsCmd: Start
254109.496: mct_SendMrsCmd: Done
254209.496: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
254309.496: mct_SendMrsCmd: Start
254409.496: mct_SendMrsCmd: Done
254509.496: DIMM 0 RttNom: 3
254609.496: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
254709.496: mct_SendMrsCmd: Start
254809.496: mct_SendMrsCmd: Done
254909.496: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
255009.496: mct_SendMrsCmd: Start
255109.496: mct_SendMrsCmd: Done
255209.497: DIMM 0 RttWr: 2
255309.497: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
255409.497: mct_SendMrsCmd: Start
255509.497: mct_SendMrsCmd: Done
255609.497: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
255709.497: mct_SendMrsCmd: Start
255809.497: mct_SendMrsCmd: Done
255909.497: DIMM 0 RttNom: 3
256009.497: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
256109.497: mct_SendMrsCmd: Start
256209.497: mct_SendMrsCmd: Done
256309.497: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
256409.497: mct_SendMrsCmd: Start
256509.497: mct_SendMrsCmd: Done
256609.497: DIMM 1 RttWr: 2
256709.497: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
256809.497: mct_SendMrsCmd: Start
256909.497: mct_SendMrsCmd: Done
257009.497: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
257109.497: mct_SendMrsCmd: Start
257209.497: mct_SendMrsCmd: Done
257309.497: DIMM 1 RttNom: 3
257409.497: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
257509.497: mct_SendMrsCmd: Start
257609.497: mct_SendMrsCmd: Done
257709.497: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
257809.497: mct_SendMrsCmd: Start
257909.497: mct_SendMrsCmd: Done
258009.497: DIMM 1 RttWr: 2
258109.497: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
258209.497: mct_SendMrsCmd: Start
258309.497: mct_SendMrsCmd: Done
258409.497: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
258509.497: mct_SendMrsCmd: Start
258609.497: mct_SendMrsCmd: Done
258709.497: DIMM 1 RttNom: 3
258809.497: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
258909.497: mct_SendMrsCmd: Start
259009.497: mct_SendMrsCmd: Done
259109.497: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
259209.497: mct_SendMrsCmd: Start
259309.497: mct_SendMrsCmd: Done
259409.497: mct_SendZQCmd: Start
259509.497: mct_SendZQCmd: Done
259609.497: mct_SendZQCmd: Start
259709.497: mct_SendZQCmd: Done
259809.497: mct_DCTAccessDone: Start
259909.497: mct_DCTAccessDone: Done
260009.497: mct_DramInit_Sw_D: Done
260109.497: <09><09>DCTFinalInit_D: StartupDCT_D Done
260209.497: mctAutoInitMCT_D: SyncDCTsReady_D
260309.497: mctAutoInitMCT_D: HTMemMapInit_D
260409.497: Node: 00 base: 00 limit: fffffff BottomIO: c00000
260509.498: Node: 00 base: 03 limit: 103fffff
260609.498: Node: 01 base: 10400000 limit: 203fffff BottomIO: c00000
260709.498: Node: 01 base: 10400003 limit: 203fffff
260809.498: Node: 02 base: 20400000 limit: 303fffff BottomIO: c00000
260909.498: Node: 02 base: 20400003 limit: 303fffff
261009.498: Node: 03 base: 30400000 limit: 403fffff BottomIO: c00000
261109.498: Node: 03 base: 30400003 limit: 403fffff
261209.498: Node: 04 base: 00 limit: 00
261309.498: Node: 05 base: 00 limit: 00
261409.498: Node: 06 base: 00 limit: 00
261509.498: Node: 07 base: 00 limit: 00
261609.498: Copy dram map from Node 0 to Node 01
261709.498: Copy dram map from Node 0 to Node 02
261809.498: Copy dram map from Node 0 to Node 03
261909.498: mctAutoInitMCT_D: mctHookAfterCPU
262009.498: mctAutoInitMCT_D: DQSTiming_D
262109.498: phyAssistedMemFnceTraining: Start
262209.498: phyAssistedMemFnceTraining: training node 0 DCT 0
262309.499: phyAssistedMemFnceTraining: done training node 0 DCT 0
262409.499: phyAssistedMemFnceTraining: training node 0 DCT 1
262509.499: phyAssistedMemFnceTraining: done training node 0 DCT 1
262609.499: phyAssistedMemFnceTraining: training node 1 DCT 0
262709.499: phyAssistedMemFnceTraining: done training node 1 DCT 0
262809.499: phyAssistedMemFnceTraining: training node 1 DCT 1
262909.499: phyAssistedMemFnceTraining: done training node 1 DCT 1
263009.499: phyAssistedMemFnceTraining: training node 2 DCT 0
263109.499: phyAssistedMemFnceTraining: done training node 2 DCT 0
263209.499: phyAssistedMemFnceTraining: training node 2 DCT 1
263309.499: phyAssistedMemFnceTraining: done training node 2 DCT 1
263409.499: phyAssistedMemFnceTraining: training node 3 DCT 0
263509.500: phyAssistedMemFnceTraining: done training node 3 DCT 0
263609.500: phyAssistedMemFnceTraining: training node 3 DCT 1
263709.500: phyAssistedMemFnceTraining: done training node 3 DCT 1
263809.500: phyAssistedMemFnceTraining: Done
263909.500: InitPhyCompensation: DCT 0: Start
264009.501: Waiting for predriver calibration to be applied...done!
264109.501: InitPhyCompensation: DCT 0: Done
264209.501: InitPhyCompensation: DCT 1: Start
264309.501: Waiting for predriver calibration to be applied...done!
264409.501: InitPhyCompensation: DCT 1: Done
264509.501: InitPhyCompensation: DCT 0: Start
264609.501: Waiting for predriver calibration to be applied...done!
264709.501: InitPhyCompensation: DCT 0: Done
264809.501: InitPhyCompensation: DCT 1: Start
264909.501: Waiting for predriver calibration to be applied...done!
265009.501: InitPhyCompensation: DCT 1: Done
265109.501: InitPhyCompensation: DCT 0: Start
265209.501: Waiting for predriver calibration to be applied...done!
265309.501: InitPhyCompensation: DCT 0: Done
265409.501: InitPhyCompensation: DCT 1: Start
265509.501: Waiting for predriver calibration to be applied...done!
265609.501: InitPhyCompensation: DCT 1: Done
265709.501: InitPhyCompensation: DCT 0: Start
265809.501: Waiting for predriver calibration to be applied...done!
265909.502: InitPhyCompensation: DCT 0: Done
266009.501: InitPhyCompensation: DCT 1: Start
266109.502: Waiting for predriver calibration to be applied...done!
266209.502: InitPhyCompensation: DCT 1: Done
266309.502: activate_spd_rom() for node 00
266409.502: enable_spd_node0()
266509.504: AgesaHwWlPhase1: training nibble 0
266609.504: DIMM 0 RttNom: 3
266709.504: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
266809.504: DIMM 0 RttWr: 2
266909.504: DIMM 0 RttWr: 2
267009.504: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
267109.504: DIMM 0 RttWr: 2
267209.504: DIMM 0 RttNom: 3
267309.504: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
267409.504: DIMM 0 RttNom: 3
267509.504: DIMM 0 RttWr: 2
267609.504: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
267709.504: DIMM 0 RttWr: 2
267809.505: DIMM 1 RttNom: 3
267909.505: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
268009.505: DIMM 0 RttNom: 3
268109.505: DIMM 1 RttWr: 2
268209.505: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
268309.505: DIMM 0 RttWr: 2
268409.505: DIMM 1 RttNom: 3
268509.505: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
268609.505: DIMM 0 RttNom: 3
268709.505: DIMM 1 RttWr: 2
268809.505: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
268909.505: DIMM 0 RttWr: 2
269009.506: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
269109.506: <09>Lane 00 initial seed: 0041
269209.506: <09>Lane 01 initial seed: 0041
269309.506: <09>Lane 02 initial seed: 0041
269409.506: <09>Lane 03 initial seed: 0041
269509.506: <09>Lane 04 initial seed: 0041
269609.506: <09>Lane 05 initial seed: 0041
269709.506: <09>Lane 06 initial seed: 0041
269809.506: <09>Lane 07 initial seed: 0041
269909.506: <09>Lane 08 initial seed: 0041
270009.507: <09>Lane 00 nibble 0 raw readback: 004c
270109.507: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
270209.507: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
270309.507: <09>Lane 01 nibble 0 raw readback: 0047
270409.507: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
270509.507: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
270609.507: <09>Lane 02 nibble 0 raw readback: 0045
270709.507: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
270809.507: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
270909.507: <09>Lane 03 nibble 0 raw readback: 0041
271009.507: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0041
271109.507: <09>Lane 03 nibble 0 adjusted value (post nibble): 0041
271209.507: <09>Lane 04 nibble 0 raw readback: 0039
271309.507: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
271409.507: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
271509.507: <09>Lane 05 nibble 0 raw readback: 003d
271609.507: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
271709.507: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
271809.507: <09>Lane 06 nibble 0 raw readback: 003f
271909.507: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
272009.507: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
272109.507: <09>Lane 07 nibble 0 raw readback: 0041
272209.507: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
272309.507: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
272409.507: <09>Lane 08 nibble 0 raw readback: 003c
272509.507: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
272609.507: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
272709.507: AgesaHwWlPhase1: training nibble 1
272809.507: DIMM 0 RttNom: 3
272909.507: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
273009.507: DIMM 0 RttWr: 2
273109.507: DIMM 0 RttWr: 2
273209.507: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
273309.507: DIMM 0 RttWr: 2
273409.507: DIMM 0 RttNom: 3
273509.507: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
273609.507: DIMM 0 RttNom: 3
273709.507: DIMM 0 RttWr: 2
273809.507: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
273909.507: DIMM 0 RttWr: 2
274009.507: DIMM 1 RttNom: 3
274109.507: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
274209.507: DIMM 0 RttNom: 3
274309.507: DIMM 1 RttWr: 2
274409.507: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
274509.507: DIMM 0 RttWr: 2
274609.507: DIMM 1 RttNom: 3
274709.507: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
274809.507: DIMM 0 RttNom: 3
274909.507: DIMM 1 RttWr: 2
275009.507: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
275109.507: DIMM 0 RttWr: 2
275209.507: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
275309.507: <09>Lane 00 initial seed: 0041
275409.507: <09>Lane 01 initial seed: 0041
275509.507: <09>Lane 02 initial seed: 0041
275609.507: <09>Lane 03 initial seed: 0041
275709.507: <09>Lane 04 initial seed: 0041
275809.507: <09>Lane 05 initial seed: 0041
275909.507: <09>Lane 06 initial seed: 0041
276009.507: <09>Lane 07 initial seed: 0041
276109.507: <09>Lane 08 initial seed: 0041
276209.507: <09>Lane 00 nibble 1 raw readback: 004c
276309.508: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004c
276409.508: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
276509.508: <09>Lane 01 nibble 1 raw readback: 0047
276609.508: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
276709.508: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
276809.508: <09>Lane 02 nibble 1 raw readback: 0046
276909.508: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
277009.508: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
277109.508: <09>Lane 03 nibble 1 raw readback: 0043
277209.508: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
277309.508: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
277409.508: <09>Lane 04 nibble 1 raw readback: 003a
277509.508: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
277609.508: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
277709.508: <09>Lane 05 nibble 1 raw readback: 003e
277809.508: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
277909.508: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
278009.508: <09>Lane 06 nibble 1 raw readback: 0040
278109.508: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
278209.508: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
278309.508: <09>Lane 07 nibble 1 raw readback: 0041
278409.508: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
278509.508: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
278609.508: <09>Lane 08 nibble 1 raw readback: 003c
278709.508: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
278809.508: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
278909.508: <09>original critical gross delay: 0
279009.508: <09>new critical gross delay: 0
279109.508: DIMM 0 RttNom: 3
279209.508: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
279309.508: DIMM 0 RttNom: 3
279409.508: DIMM 0 RttWr: 2
279509.508: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
279609.508: DIMM 0 RttWr: 2
279709.508: DIMM 0 RttNom: 3
279809.508: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
279909.508: DIMM 0 RttNom: 3
280009.508: DIMM 0 RttWr: 2
280109.508: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
280209.508: DIMM 0 RttWr: 2
280309.508: DIMM 1 RttNom: 3
280409.508: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
280509.508: DIMM 0 RttNom: 3
280609.508: DIMM 1 RttWr: 2
280709.508: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
280809.508: DIMM 0 RttWr: 2
280909.509: DIMM 1 RttNom: 3
281009.508: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
281109.509: DIMM 0 RttNom: 3
281209.509: DIMM 1 RttWr: 2
281309.509: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
281409.509: DIMM 0 RttWr: 2
281509.509: AgesaHwWlPhase1: training nibble 0
281609.509: DIMM 1 RttNom: 3
281709.509: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
281809.509: DIMM 1 RttWr: 2
281909.509: DIMM 1 RttWr: 2
282009.509: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
282109.509: DIMM 1 RttWr: 2
282209.509: DIMM 1 RttNom: 3
282309.509: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
282409.509: DIMM 1 RttNom: 3
282509.509: DIMM 1 RttWr: 2
282609.509: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
282709.509: DIMM 1 RttWr: 2
282809.509: DIMM 0 RttNom: 3
282909.509: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
283009.509: DIMM 1 RttNom: 3
283109.509: DIMM 0 RttWr: 2
283209.509: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
283309.509: DIMM 1 RttWr: 2
283409.509: DIMM 0 RttNom: 3
283509.509: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
283609.509: DIMM 1 RttNom: 3
283709.509: DIMM 0 RttWr: 2
283809.509: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
283909.509: DIMM 1 RttWr: 2
284009.509: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
284109.509: <09>Lane 00 initial seed: 0041
284209.509: <09>Lane 01 initial seed: 0041
284309.509: <09>Lane 02 initial seed: 0041
284409.509: <09>Lane 03 initial seed: 0041
284509.509: <09>Lane 04 initial seed: 0041
284609.509: <09>Lane 05 initial seed: 0041
284709.509: <09>Lane 06 initial seed: 0041
284809.509: <09>Lane 07 initial seed: 0041
284909.509: <09>Lane 08 initial seed: 0041
285009.509: <09>Lane 00 nibble 0 raw readback: 003f
285109.509: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
285209.509: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
285309.509: <09>Lane 01 nibble 0 raw readback: 003a
285409.509: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003a
285509.509: <09>Lane 01 nibble 0 adjusted value (post nibble): 003a
285609.509: <09>Lane 02 nibble 0 raw readback: 0038
285709.509: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
285809.509: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
285909.509: <09>Lane 03 nibble 0 raw readback: 0035
286009.509: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0035
286109.509: <09>Lane 03 nibble 0 adjusted value (post nibble): 0035
286209.509: <09>Lane 04 nibble 0 raw readback: 002e
286309.509: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
286409.509: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
286509.509: <09>Lane 05 nibble 0 raw readback: 0032
286609.509: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
286709.509: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
286809.509: <09>Lane 06 nibble 0 raw readback: 0033
286909.509: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
287009.509: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
287109.509: <09>Lane 07 nibble 0 raw readback: 0035
287209.509: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0035
287309.509: <09>Lane 07 nibble 0 adjusted value (post nibble): 0035
287409.509: <09>Lane 08 nibble 0 raw readback: 002f
287509.509: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
287609.509: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
287709.509: AgesaHwWlPhase1: training nibble 1
287809.509: DIMM 1 RttNom: 3
287909.509: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
288009.509: DIMM 1 RttWr: 2
288109.509: DIMM 1 RttWr: 2
288209.509: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
288309.510: DIMM 1 RttWr: 2
288409.510: DIMM 1 RttNom: 3
288509.510: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
288609.510: DIMM 1 RttNom: 3
288709.510: DIMM 1 RttWr: 2
288809.510: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
288909.510: DIMM 1 RttWr: 2
289009.510: DIMM 0 RttNom: 3
289109.510: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
289209.510: DIMM 1 RttNom: 3
289309.510: DIMM 0 RttWr: 2
289409.510: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
289509.510: DIMM 1 RttWr: 2
289609.510: DIMM 0 RttNom: 3
289709.510: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
289809.510: DIMM 1 RttNom: 3
289909.510: DIMM 0 RttWr: 2
290009.510: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
290109.510: DIMM 1 RttWr: 2
290209.510: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
290309.510: <09>Lane 00 initial seed: 0041
290409.510: <09>Lane 01 initial seed: 0041
290509.510: <09>Lane 02 initial seed: 0041
290609.510: <09>Lane 03 initial seed: 0041
290709.510: <09>Lane 04 initial seed: 0041
290809.510: <09>Lane 05 initial seed: 0041
290909.510: <09>Lane 06 initial seed: 0041
291009.510: <09>Lane 07 initial seed: 0041
291109.510: <09>Lane 08 initial seed: 0041
291209.510: <09>Lane 00 nibble 1 raw readback: 003f
291309.510: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
291409.510: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
291509.510: <09>Lane 01 nibble 1 raw readback: 003b
291609.510: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003b
291709.510: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
291809.510: <09>Lane 02 nibble 1 raw readback: 003a
291909.510: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003a
292009.510: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
292109.510: <09>Lane 03 nibble 1 raw readback: 0036
292209.510: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
292309.510: <09>Lane 03 nibble 1 adjusted value (post nibble): 003b
292409.510: <09>Lane 04 nibble 1 raw readback: 002e
292509.510: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
292609.510: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
292709.510: <09>Lane 05 nibble 1 raw readback: 0032
292809.510: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
292909.510: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
293009.510: <09>Lane 06 nibble 1 raw readback: 0033
293109.510: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
293209.510: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
293309.510: <09>Lane 07 nibble 1 raw readback: 0036
293409.510: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
293509.510: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
293609.510: <09>Lane 08 nibble 1 raw readback: 002f
293709.510: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
293809.510: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
293909.510: <09>original critical gross delay: 0
294009.510: <09>new critical gross delay: 0
294109.510: DIMM 1 RttNom: 3
294209.510: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
294309.510: DIMM 1 RttNom: 3
294409.510: DIMM 1 RttWr: 2
294509.510: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
294609.510: DIMM 1 RttWr: 2
294709.511: DIMM 1 RttNom: 3
294809.511: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
294909.511: DIMM 1 RttNom: 3
295009.511: DIMM 1 RttWr: 2
295109.511: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
295209.511: DIMM 1 RttWr: 2
295309.511: DIMM 0 RttNom: 3
295409.511: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
295509.511: DIMM 1 RttNom: 3
295609.511: DIMM 0 RttWr: 2
295709.511: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
295809.511: DIMM 1 RttWr: 2
295909.511: DIMM 0 RttNom: 3
296009.511: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
296109.511: DIMM 1 RttNom: 3
296209.511: DIMM 0 RttWr: 2
296309.511: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
296409.511: DIMM 1 RttWr: 2
296509.511: AgesaHwWlPhase1: training nibble 0
296609.511: DIMM 0 RttNom: 3
296709.511: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
296809.511: DIMM 0 RttWr: 2
296909.511: DIMM 0 RttWr: 2
297009.511: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
297109.511: DIMM 0 RttWr: 2
297209.511: DIMM 0 RttNom: 3
297309.511: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
297409.511: DIMM 0 RttNom: 3
297509.511: DIMM 0 RttWr: 2
297609.511: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
297709.511: DIMM 0 RttWr: 2
297809.511: DIMM 1 RttNom: 3
297909.511: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
298009.511: DIMM 0 RttNom: 3
298109.511: DIMM 1 RttWr: 2
298209.511: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
298309.511: DIMM 0 RttWr: 2
298409.511: DIMM 1 RttNom: 3
298509.511: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
298609.511: DIMM 0 RttNom: 3
298709.511: DIMM 1 RttWr: 2
298809.511: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
298909.511: DIMM 0 RttWr: 2
299009.511: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
299109.511: <09>Lane 00 initial seed: 0041
299209.511: <09>Lane 01 initial seed: 0041
299309.511: <09>Lane 02 initial seed: 0041
299409.511: <09>Lane 03 initial seed: 0041
299509.511: <09>Lane 04 initial seed: 0041
299609.511: <09>Lane 05 initial seed: 0041
299709.511: <09>Lane 06 initial seed: 0041
299809.511: <09>Lane 07 initial seed: 0041
299909.511: <09>Lane 08 initial seed: 0041
300009.511: <09>Lane 00 nibble 0 raw readback: 0049
300109.511: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0049
300209.511: <09>Lane 00 nibble 0 adjusted value (post nibble): 0049
300309.511: <09>Lane 01 nibble 0 raw readback: 0046
300409.511: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0046
300509.511: <09>Lane 01 nibble 0 adjusted value (post nibble): 0046
300609.511: <09>Lane 02 nibble 0 raw readback: 0043
300709.511: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
300809.511: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
300909.511: <09>Lane 03 nibble 0 raw readback: 0040
301009.511: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0040
301109.511: <09>Lane 03 nibble 0 adjusted value (post nibble): 0040
301209.511: <09>Lane 04 nibble 0 raw readback: 0039
301309.511: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
301409.511: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
301509.511: <09>Lane 05 nibble 0 raw readback: 003b
301609.511: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
301709.511: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
301809.511: <09>Lane 06 nibble 0 raw readback: 003d
301909.511: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
302009.511: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
302109.512: <09>Lane 07 nibble 0 raw readback: 003f
302209.512: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
302309.512: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
302409.512: <09>Lane 08 nibble 0 raw readback: 003a
302509.512: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
302609.512: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
302709.512: AgesaHwWlPhase1: training nibble 1
302809.512: DIMM 0 RttNom: 3
302909.512: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
303009.512: DIMM 0 RttWr: 2
303109.512: DIMM 0 RttWr: 2
303209.512: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
303309.512: DIMM 0 RttWr: 2
303409.512: DIMM 0 RttNom: 3
303509.512: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
303609.512: DIMM 0 RttNom: 3
303709.512: DIMM 0 RttWr: 2
303809.512: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
303909.512: DIMM 0 RttWr: 2
304009.512: DIMM 1 RttNom: 3
304109.512: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
304209.512: DIMM 0 RttNom: 3
304309.512: DIMM 1 RttWr: 2
304409.512: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
304509.512: DIMM 0 RttWr: 2
304609.512: DIMM 1 RttNom: 3
304709.512: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
304809.512: DIMM 0 RttNom: 3
304909.512: DIMM 1 RttWr: 2
305009.512: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
305109.512: DIMM 0 RttWr: 2
305209.512: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
305309.512: <09>Lane 00 initial seed: 0041
305409.512: <09>Lane 01 initial seed: 0041
305509.512: <09>Lane 02 initial seed: 0041
305609.512: <09>Lane 03 initial seed: 0041
305709.512: <09>Lane 04 initial seed: 0041
305809.512: <09>Lane 05 initial seed: 0041
305909.512: <09>Lane 06 initial seed: 0041
306009.512: <09>Lane 07 initial seed: 0041
306109.512: <09>Lane 08 initial seed: 0041
306209.512: <09>Lane 00 nibble 1 raw readback: 0049
306309.512: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0049
306409.512: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
306509.512: <09>Lane 01 nibble 1 raw readback: 0045
306609.512: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0045
306709.512: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
306809.512: <09>Lane 02 nibble 1 raw readback: 0044
306909.512: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
307009.512: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
307109.512: <09>Lane 03 nibble 1 raw readback: 0040
307209.512: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0040
307309.512: <09>Lane 03 nibble 1 adjusted value (post nibble): 0040
307409.512: <09>Lane 04 nibble 1 raw readback: 0038
307509.512: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
307609.512: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
307709.512: <09>Lane 05 nibble 1 raw readback: 003a
307809.512: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
307909.512: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
308009.512: <09>Lane 06 nibble 1 raw readback: 003d
308109.512: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
308209.512: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
308309.512: <09>Lane 07 nibble 1 raw readback: 003f
308409.512: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
308509.512: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
308609.512: <09>Lane 08 nibble 1 raw readback: 0039
308709.512: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
308809.512: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
308909.512: <09>original critical gross delay: 0
309009.512: <09>new critical gross delay: 0
309109.513: DIMM 0 RttNom: 3
309209.512: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
309309.513: DIMM 0 RttNom: 3
309409.513: DIMM 0 RttWr: 2
309509.513: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
309609.513: DIMM 0 RttWr: 2
309709.513: DIMM 0 RttNom: 3
309809.513: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
309909.513: DIMM 0 RttNom: 3
310009.513: DIMM 0 RttWr: 2
310109.513: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
310209.513: DIMM 0 RttWr: 2
310309.513: DIMM 1 RttNom: 3
310409.513: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
310509.513: DIMM 0 RttNom: 3
310609.513: DIMM 1 RttWr: 2
310709.513: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
310809.513: DIMM 0 RttWr: 2
310909.513: DIMM 1 RttNom: 3
311009.513: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
311109.513: DIMM 0 RttNom: 3
311209.513: DIMM 1 RttWr: 2
311309.513: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
311409.513: DIMM 0 RttWr: 2
311509.513: AgesaHwWlPhase1: training nibble 0
311609.513: DIMM 1 RttNom: 3
311709.513: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
311809.513: DIMM 1 RttWr: 2
311909.513: DIMM 1 RttWr: 2
312009.513: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
312109.513: DIMM 1 RttWr: 2
312209.513: DIMM 1 RttNom: 3
312309.513: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
312409.513: DIMM 1 RttNom: 3
312509.513: DIMM 1 RttWr: 2
312609.513: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
312709.513: DIMM 1 RttWr: 2
312809.513: DIMM 0 RttNom: 3
312909.513: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
313009.513: DIMM 1 RttNom: 3
313109.513: DIMM 0 RttWr: 2
313209.513: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
313309.513: DIMM 1 RttWr: 2
313409.513: DIMM 0 RttNom: 3
313509.513: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
313609.513: DIMM 1 RttNom: 3
313709.513: DIMM 0 RttWr: 2
313809.513: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
313909.513: DIMM 1 RttWr: 2
314009.513: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
314109.513: <09>Lane 00 initial seed: 0041
314209.513: <09>Lane 01 initial seed: 0041
314309.513: <09>Lane 02 initial seed: 0041
314409.513: <09>Lane 03 initial seed: 0041
314509.513: <09>Lane 04 initial seed: 0041
314609.513: <09>Lane 05 initial seed: 0041
314709.513: <09>Lane 06 initial seed: 0041
314809.513: <09>Lane 07 initial seed: 0041
314909.513: <09>Lane 08 initial seed: 0041
315009.513: <09>Lane 00 nibble 0 raw readback: 003f
315109.513: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
315209.513: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
315309.513: <09>Lane 01 nibble 0 raw readback: 003e
315409.513: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
315509.513: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
315609.513: <09>Lane 02 nibble 0 raw readback: 0038
315709.513: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
315809.513: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
315909.513: <09>Lane 03 nibble 0 raw readback: 0037
316009.513: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0037
316109.513: <09>Lane 03 nibble 0 adjusted value (post nibble): 0037
316209.513: <09>Lane 04 nibble 0 raw readback: 002e
316309.513: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
316409.513: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
316509.514: <09>Lane 05 nibble 0 raw readback: 0031
316609.513: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0031
316709.514: <09>Lane 05 nibble 0 adjusted value (post nibble): 0031
316809.514: <09>Lane 06 nibble 0 raw readback: 0033
316909.514: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
317009.514: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
317109.514: <09>Lane 07 nibble 0 raw readback: 0036
317209.514: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
317309.514: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
317409.514: <09>Lane 08 nibble 0 raw readback: 0030
317509.514: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
317609.514: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
317709.514: AgesaHwWlPhase1: training nibble 1
317809.514: DIMM 1 RttNom: 3
317909.514: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
318009.514: DIMM 1 RttWr: 2
318109.514: DIMM 1 RttWr: 2
318209.514: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
318309.514: DIMM 1 RttWr: 2
318409.514: DIMM 1 RttNom: 3
318509.514: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
318609.514: DIMM 1 RttNom: 3
318709.514: DIMM 1 RttWr: 2
318809.514: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
318909.514: DIMM 1 RttWr: 2
319009.514: DIMM 0 RttNom: 3
319109.514: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
319209.514: DIMM 1 RttNom: 3
319309.514: DIMM 0 RttWr: 2
319409.514: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
319509.514: DIMM 1 RttWr: 2
319609.514: DIMM 0 RttNom: 3
319709.514: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
319809.514: DIMM 1 RttNom: 3
319909.514: DIMM 0 RttWr: 2
320009.514: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
320109.514: DIMM 1 RttWr: 2
320209.514: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
320309.514: <09>Lane 00 initial seed: 0041
320409.514: <09>Lane 01 initial seed: 0041
320509.514: <09>Lane 02 initial seed: 0041
320609.514: <09>Lane 03 initial seed: 0041
320709.514: <09>Lane 04 initial seed: 0041
320809.514: <09>Lane 05 initial seed: 0041
320909.514: <09>Lane 06 initial seed: 0041
321009.514: <09>Lane 07 initial seed: 0041
321109.514: <09>Lane 08 initial seed: 0041
321209.514: <09>Lane 00 nibble 1 raw readback: 0040
321309.514: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0040
321409.514: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
321509.514: <09>Lane 01 nibble 1 raw readback: 003d
321609.514: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003d
321709.514: <09>Lane 01 nibble 1 adjusted value (post nibble): 003f
321809.514: <09>Lane 02 nibble 1 raw readback: 0039
321909.514: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
322009.514: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
322109.514: <09>Lane 03 nibble 1 raw readback: 0039
322209.514: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0039
322309.514: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
322409.514: <09>Lane 04 nibble 1 raw readback: 002f
322509.514: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002f
322609.514: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
322709.514: <09>Lane 05 nibble 1 raw readback: 0032
322809.514: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
322909.514: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
323009.514: <09>Lane 06 nibble 1 raw readback: 0033
323109.514: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
323209.514: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
323309.514: <09>Lane 07 nibble 1 raw readback: 0036
323409.514: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
323509.514: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
323609.514: <09>Lane 08 nibble 1 raw readback: 0030
323709.514: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0030
323809.514: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
323909.514: <09>original critical gross delay: 0
324009.514: <09>new critical gross delay: 0
324109.515: DIMM 1 RttNom: 3
324209.515: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
324309.515: DIMM 1 RttNom: 3
324409.515: DIMM 1 RttWr: 2
324509.515: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
324609.515: DIMM 1 RttWr: 2
324709.515: DIMM 1 RttNom: 3
324809.515: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
324909.515: DIMM 1 RttNom: 3
325009.515: DIMM 1 RttWr: 2
325109.515: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
325209.515: DIMM 1 RttWr: 2
325309.515: DIMM 0 RttNom: 3
325409.515: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
325509.515: DIMM 1 RttNom: 3
325609.515: DIMM 0 RttWr: 2
325709.515: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
325809.515: DIMM 1 RttWr: 2
325909.515: DIMM 0 RttNom: 3
326009.515: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
326109.515: DIMM 1 RttNom: 3
326209.515: DIMM 0 RttWr: 2
326309.515: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
326409.515: DIMM 1 RttWr: 2
326509.515: activate_spd_rom() for node 01
326609.515: enable_spd_node1()
326709.515: AgesaHwWlPhase1: training nibble 0
326809.515: DIMM 0 RttNom: 3
326909.515: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
327009.515: DIMM 0 RttWr: 2
327109.515: DIMM 0 RttWr: 2
327209.516: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
327309.515: DIMM 0 RttWr: 2
327409.515: DIMM 0 RttNom: 3
327509.516: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
327609.516: DIMM 0 RttNom: 3
327709.516: DIMM 0 RttWr: 2
327809.516: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
327909.516: DIMM 0 RttWr: 2
328009.516: DIMM 1 RttNom: 3
328109.516: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
328209.516: DIMM 0 RttNom: 3
328309.516: DIMM 1 RttWr: 2
328409.516: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
328509.516: DIMM 0 RttWr: 2
328609.516: DIMM 1 RttNom: 3
328709.516: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
328809.516: DIMM 0 RttNom: 3
328909.516: DIMM 1 RttWr: 2
329009.516: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
329109.516: DIMM 0 RttWr: 2
329209.516: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
329309.516: <09>Lane 00 initial seed: 0041
329409.516: <09>Lane 01 initial seed: 0041
329509.516: <09>Lane 02 initial seed: 0041
329609.516: <09>Lane 03 initial seed: 0041
329709.516: <09>Lane 04 initial seed: 0041
329809.516: <09>Lane 05 initial seed: 0041
329909.516: <09>Lane 06 initial seed: 0041
330009.516: <09>Lane 07 initial seed: 0041
330109.516: <09>Lane 08 initial seed: 0041
330209.516: <09>Lane 00 nibble 0 raw readback: 003a
330309.516: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003a
330409.516: <09>Lane 00 nibble 0 adjusted value (post nibble): 003a
330509.516: <09>Lane 01 nibble 0 raw readback: 0037
330609.516: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
330709.516: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
330809.516: <09>Lane 02 nibble 0 raw readback: 0034
330909.516: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0034
331009.516: <09>Lane 02 nibble 0 adjusted value (post nibble): 0034
331109.516: <09>Lane 03 nibble 0 raw readback: 0032
331209.516: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0032
331309.516: <09>Lane 03 nibble 0 adjusted value (post nibble): 0032
331409.516: <09>Lane 04 nibble 0 raw readback: 0030
331509.516: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
331609.516: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
331709.516: <09>Lane 05 nibble 0 raw readback: 0032
331809.516: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
331909.516: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
332009.516: <09>Lane 06 nibble 0 raw readback: 0034
332109.516: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0034
332209.516: <09>Lane 06 nibble 0 adjusted value (post nibble): 0034
332309.516: <09>Lane 07 nibble 0 raw readback: 0038
332409.516: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0038
332509.516: <09>Lane 07 nibble 0 adjusted value (post nibble): 0038
332609.516: <09>Lane 08 nibble 0 raw readback: 002f
332709.516: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
332809.516: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
332909.516: AgesaHwWlPhase1: training nibble 1
333009.516: DIMM 0 RttNom: 3
333109.516: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
333209.516: DIMM 0 RttWr: 2
333309.516: DIMM 0 RttWr: 2
333409.516: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
333509.516: DIMM 0 RttWr: 2
333609.516: DIMM 0 RttNom: 3
333709.516: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
333809.517: DIMM 0 RttNom: 3
333909.517: DIMM 0 RttWr: 2
334009.517: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
334109.517: DIMM 0 RttWr: 2
334209.517: DIMM 1 RttNom: 3
334309.517: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
334409.517: DIMM 0 RttNom: 3
334509.517: DIMM 1 RttWr: 2
334609.517: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
334709.517: DIMM 0 RttWr: 2
334809.517: DIMM 1 RttNom: 3
334909.517: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
335009.517: DIMM 0 RttNom: 3
335109.517: DIMM 1 RttWr: 2
335209.517: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
335309.517: DIMM 0 RttWr: 2
335409.517: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
335509.517: <09>Lane 00 initial seed: 0041
335609.517: <09>Lane 01 initial seed: 0041
335709.517: <09>Lane 02 initial seed: 0041
335809.517: <09>Lane 03 initial seed: 0041
335909.517: <09>Lane 04 initial seed: 0041
336009.517: <09>Lane 05 initial seed: 0041
336109.517: <09>Lane 06 initial seed: 0041
336209.517: <09>Lane 07 initial seed: 0041
336309.517: <09>Lane 08 initial seed: 0041
336409.517: <09>Lane 00 nibble 1 raw readback: 0039
336509.517: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0039
336609.517: <09>Lane 00 nibble 1 adjusted value (post nibble): 003d
336709.517: <09>Lane 01 nibble 1 raw readback: 0037
336809.517: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
336909.517: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
337009.517: <09>Lane 02 nibble 1 raw readback: 0033
337109.517: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0033
337209.517: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
337309.517: <09>Lane 03 nibble 1 raw readback: 0032
337409.517: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0032
337509.517: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
337609.517: <09>Lane 04 nibble 1 raw readback: 0030
337709.517: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
337809.517: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
337909.517: <09>Lane 05 nibble 1 raw readback: 0032
338009.517: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
338109.517: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
338209.517: <09>Lane 06 nibble 1 raw readback: 0035
338309.517: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
338409.517: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
338509.517: <09>Lane 07 nibble 1 raw readback: 0038
338609.517: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0038
338709.517: <09>Lane 07 nibble 1 adjusted value (post nibble): 003c
338809.517: <09>Lane 08 nibble 1 raw readback: 002e
338909.517: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002e
339009.517: <09>Lane 08 nibble 1 adjusted value (post nibble): 0037
339109.517: <09>original critical gross delay: 0
339209.517: <09>new critical gross delay: 0
339309.517: DIMM 0 RttNom: 3
339409.517: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
339509.517: DIMM 0 RttNom: 3
339609.517: DIMM 0 RttWr: 2
339709.517: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
339809.517: DIMM 0 RttWr: 2
339909.518: DIMM 0 RttNom: 3
340009.518: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
340109.518: DIMM 0 RttNom: 3
340209.518: DIMM 0 RttWr: 2
340309.518: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
340409.518: DIMM 0 RttWr: 2
340509.518: DIMM 1 RttNom: 3
340609.518: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
340709.518: DIMM 0 RttNom: 3
340809.518: DIMM 1 RttWr: 2
340909.518: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
341009.518: DIMM 0 RttWr: 2
341109.518: DIMM 1 RttNom: 3
341209.518: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
341309.518: DIMM 0 RttNom: 3
341409.518: DIMM 1 RttWr: 2
341509.518: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
341609.518: DIMM 0 RttWr: 2
341709.518: AgesaHwWlPhase1: training nibble 0
341809.518: DIMM 1 RttNom: 3
341909.518: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
342009.518: DIMM 1 RttWr: 2
342109.518: DIMM 1 RttWr: 2
342209.518: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
342309.518: DIMM 1 RttWr: 2
342409.518: DIMM 1 RttNom: 3
342509.518: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
342609.518: DIMM 1 RttNom: 3
342709.518: DIMM 1 RttWr: 2
342809.518: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
342909.518: DIMM 1 RttWr: 2
343009.518: DIMM 0 RttNom: 3
343109.518: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
343209.518: DIMM 1 RttNom: 3
343309.518: DIMM 0 RttWr: 2
343409.518: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
343509.518: DIMM 1 RttWr: 2
343609.518: DIMM 0 RttNom: 3
343709.518: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
343809.518: DIMM 1 RttNom: 3
343909.518: DIMM 0 RttWr: 2
344009.518: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
344109.518: DIMM 1 RttWr: 2
344209.518: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
344309.518: <09>Lane 00 initial seed: 0041
344409.518: <09>Lane 01 initial seed: 0041
344509.518: <09>Lane 02 initial seed: 0041
344609.518: <09>Lane 03 initial seed: 0041
344709.518: <09>Lane 04 initial seed: 0041
344809.518: <09>Lane 05 initial seed: 0041
344909.518: <09>Lane 06 initial seed: 0041
345009.518: <09>Lane 07 initial seed: 0041
345109.518: <09>Lane 08 initial seed: 0041
345209.518: <09>Lane 00 nibble 0 raw readback: 0043
345309.518: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
345409.518: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
345509.518: <09>Lane 01 nibble 0 raw readback: 003e
345609.518: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
345709.518: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
345809.518: <09>Lane 02 nibble 0 raw readback: 003b
345909.518: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
346009.519: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
346109.518: <09>Lane 03 nibble 0 raw readback: 003a
346209.518: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
346309.518: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
346409.518: <09>Lane 04 nibble 0 raw readback: 0038
346509.519: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
346609.519: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
346709.518: <09>Lane 05 nibble 0 raw readback: 003c
346809.519: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
346909.519: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
347009.519: <09>Lane 06 nibble 0 raw readback: 003c
347109.519: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003c
347209.519: <09>Lane 06 nibble 0 adjusted value (post nibble): 003c
347309.519: <09>Lane 07 nibble 0 raw readback: 0040
347409.519: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
347509.519: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
347609.519: <09>Lane 08 nibble 0 raw readback: 0036
347709.519: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
347809.519: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
347909.519: AgesaHwWlPhase1: training nibble 1
348009.519: DIMM 1 RttNom: 3
348109.519: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
348209.519: DIMM 1 RttWr: 2
348309.519: DIMM 1 RttWr: 2
348409.519: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
348509.519: DIMM 1 RttWr: 2
348609.519: DIMM 1 RttNom: 3
348709.519: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
348809.519: DIMM 1 RttNom: 3
348909.519: DIMM 1 RttWr: 2
349009.519: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
349109.519: DIMM 1 RttWr: 2
349209.519: DIMM 0 RttNom: 3
349309.519: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
349409.519: DIMM 1 RttNom: 3
349509.519: DIMM 0 RttWr: 2
349609.519: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
349709.519: DIMM 1 RttWr: 2
349809.519: DIMM 0 RttNom: 3
349909.519: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
350009.519: DIMM 1 RttNom: 3
350109.519: DIMM 0 RttWr: 2
350209.519: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
350309.519: DIMM 1 RttWr: 2
350409.519: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
350509.519: <09>Lane 00 initial seed: 0041
350609.519: <09>Lane 01 initial seed: 0041
350709.519: <09>Lane 02 initial seed: 0041
350809.519: <09>Lane 03 initial seed: 0041
350909.519: <09>Lane 04 initial seed: 0041
351009.519: <09>Lane 05 initial seed: 0041
351109.519: <09>Lane 06 initial seed: 0041
351209.519: <09>Lane 07 initial seed: 0041
351309.519: <09>Lane 08 initial seed: 0041
351409.519: <09>Lane 00 nibble 1 raw readback: 0043
351509.519: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
351609.519: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
351709.519: <09>Lane 01 nibble 1 raw readback: 003e
351809.519: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003e
351909.519: <09>Lane 01 nibble 1 adjusted value (post nibble): 003f
352009.519: <09>Lane 02 nibble 1 raw readback: 003b
352109.519: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003b
352209.519: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
352309.519: <09>Lane 03 nibble 1 raw readback: 003a
352409.519: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
352509.519: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
352609.519: <09>Lane 04 nibble 1 raw readback: 0036
352709.519: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
352809.519: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
352909.519: <09>Lane 05 nibble 1 raw readback: 003a
353009.519: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
353109.519: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
353209.519: <09>Lane 06 nibble 1 raw readback: 003c
353309.519: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003c
353409.519: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
353509.519: <09>Lane 07 nibble 1 raw readback: 003f
353609.519: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
353709.519: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
353809.519: <09>Lane 08 nibble 1 raw readback: 0036
353909.519: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
354009.519: <09>Lane 08 nibble 1 adjusted value (post nibble): 003b
354109.520: <09>original critical gross delay: 0
354209.520: <09>new critical gross delay: 0
354309.520: DIMM 1 RttNom: 3
354409.520: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
354509.520: DIMM 1 RttNom: 3
354609.520: DIMM 1 RttWr: 2
354709.520: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
354809.520: DIMM 1 RttWr: 2
354909.520: DIMM 1 RttNom: 3
355009.520: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
355109.520: DIMM 1 RttNom: 3
355209.520: DIMM 1 RttWr: 2
355309.520: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
355409.520: DIMM 1 RttWr: 2
355509.520: DIMM 0 RttNom: 3
355609.520: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
355709.520: DIMM 1 RttNom: 3
355809.520: DIMM 0 RttWr: 2
355909.520: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
356009.520: DIMM 1 RttWr: 2
356109.520: DIMM 0 RttNom: 3
356209.520: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
356309.520: DIMM 1 RttNom: 3
356409.520: DIMM 0 RttWr: 2
356509.520: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
356609.520: DIMM 1 RttWr: 2
356709.520: AgesaHwWlPhase1: training nibble 0
356809.520: DIMM 0 RttNom: 3
356909.520: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
357009.520: DIMM 0 RttWr: 2
357109.520: DIMM 0 RttWr: 2
357209.520: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
357309.520: DIMM 0 RttWr: 2
357409.520: DIMM 0 RttNom: 3
357509.520: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
357609.520: DIMM 0 RttNom: 3
357709.520: DIMM 0 RttWr: 2
357809.520: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
357909.520: DIMM 0 RttWr: 2
358009.520: DIMM 1 RttNom: 3
358109.520: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
358209.520: DIMM 0 RttNom: 3
358309.520: DIMM 1 RttWr: 2
358409.520: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
358509.520: DIMM 0 RttWr: 2
358609.520: DIMM 1 RttNom: 3
358709.520: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
358809.520: DIMM 0 RttNom: 3
358909.520: DIMM 1 RttWr: 2
359009.520: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
359109.520: DIMM 0 RttWr: 2
359209.520: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
359309.520: <09>Lane 00 initial seed: 0041
359409.520: <09>Lane 01 initial seed: 0041
359509.520: <09>Lane 02 initial seed: 0041
359609.520: <09>Lane 03 initial seed: 0041
359709.520: <09>Lane 04 initial seed: 0041
359809.520: <09>Lane 05 initial seed: 0041
359909.520: <09>Lane 06 initial seed: 0041
360009.521: <09>Lane 07 initial seed: 0041
360109.521: <09>Lane 08 initial seed: 0041
360209.521: <09>Lane 00 nibble 0 raw readback: 003c
360309.521: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003c
360409.521: <09>Lane 00 nibble 0 adjusted value (post nibble): 003c
360509.521: <09>Lane 01 nibble 0 raw readback: 0037
360609.521: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
360709.521: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
360809.521: <09>Lane 02 nibble 0 raw readback: 0034
360909.521: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0034
361009.521: <09>Lane 02 nibble 0 adjusted value (post nibble): 0034
361109.521: <09>Lane 03 nibble 0 raw readback: 0032
361209.521: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0032
361309.521: <09>Lane 03 nibble 0 adjusted value (post nibble): 0032
361409.521: <09>Lane 04 nibble 0 raw readback: 0030
361509.521: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
361609.521: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
361709.521: <09>Lane 05 nibble 0 raw readback: 0034
361809.521: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0034
361909.521: <09>Lane 05 nibble 0 adjusted value (post nibble): 0034
362009.521: <09>Lane 06 nibble 0 raw readback: 0036
362109.521: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0036
362209.521: <09>Lane 06 nibble 0 adjusted value (post nibble): 0036
362309.521: <09>Lane 07 nibble 0 raw readback: 0039
362409.521: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
362509.521: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
362609.521: <09>Lane 08 nibble 0 raw readback: 002f
362709.521: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
362809.521: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
362909.521: AgesaHwWlPhase1: training nibble 1
363009.521: DIMM 0 RttNom: 3
363109.521: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
363209.521: DIMM 0 RttWr: 2
363309.521: DIMM 0 RttWr: 2
363409.521: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
363509.521: DIMM 0 RttWr: 2
363609.521: DIMM 0 RttNom: 3
363709.521: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
363809.521: DIMM 0 RttNom: 3
363909.521: DIMM 0 RttWr: 2
364009.521: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
364109.521: DIMM 0 RttWr: 2
364209.521: DIMM 1 RttNom: 3
364309.521: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
364409.521: DIMM 0 RttNom: 3
364509.521: DIMM 1 RttWr: 2
364609.521: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
364709.521: DIMM 0 RttWr: 2
364809.521: DIMM 1 RttNom: 3
364909.521: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
365009.521: DIMM 0 RttNom: 3
365109.521: DIMM 1 RttWr: 2
365209.521: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
365309.521: DIMM 0 RttWr: 2
365409.521: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
365509.521: <09>Lane 00 initial seed: 0041
365609.521: <09>Lane 01 initial seed: 0041
365709.521: <09>Lane 02 initial seed: 0041
365809.521: <09>Lane 03 initial seed: 0041
365909.521: <09>Lane 04 initial seed: 0041
366009.521: <09>Lane 05 initial seed: 0041
366109.521: <09>Lane 06 initial seed: 0041
366209.521: <09>Lane 07 initial seed: 0041
366309.521: <09>Lane 08 initial seed: 0041
366409.521: <09>Lane 00 nibble 1 raw readback: 003b
366509.521: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003b
366609.521: <09>Lane 00 nibble 1 adjusted value (post nibble): 003e
366709.521: <09>Lane 01 nibble 1 raw readback: 0037
366809.521: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
366909.521: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
367009.521: <09>Lane 02 nibble 1 raw readback: 0034
367109.521: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0034
367209.521: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
367309.522: <09>Lane 03 nibble 1 raw readback: 0032
367409.522: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0032
367509.522: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
367609.522: <09>Lane 04 nibble 1 raw readback: 0030
367709.522: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
367809.522: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
367909.522: <09>Lane 05 nibble 1 raw readback: 0033
368009.522: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0033
368109.522: <09>Lane 05 nibble 1 adjusted value (post nibble): 003a
368209.522: <09>Lane 06 nibble 1 raw readback: 0035
368309.522: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
368409.522: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
368509.522: <09>Lane 07 nibble 1 raw readback: 0039
368609.522: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
368709.522: <09>Lane 07 nibble 1 adjusted value (post nibble): 003d
368809.522: <09>Lane 08 nibble 1 raw readback: 002e
368909.522: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002e
369009.522: <09>Lane 08 nibble 1 adjusted value (post nibble): 0037
369109.522: <09>original critical gross delay: 0
369209.522: <09>new critical gross delay: 0
369309.522: DIMM 0 RttNom: 3
369409.522: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
369509.522: DIMM 0 RttNom: 3
369609.522: DIMM 0 RttWr: 2
369709.522: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
369809.522: DIMM 0 RttWr: 2
369909.522: DIMM 0 RttNom: 3
370009.522: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
370109.522: DIMM 0 RttNom: 3
370209.522: DIMM 0 RttWr: 2
370309.522: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
370409.522: DIMM 0 RttWr: 2
370509.522: DIMM 1 RttNom: 3
370609.522: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
370709.522: DIMM 0 RttNom: 3
370809.522: DIMM 1 RttWr: 2
370909.522: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
371009.522: DIMM 0 RttWr: 2
371109.522: DIMM 1 RttNom: 3
371209.522: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
371309.522: DIMM 0 RttNom: 3
371409.522: DIMM 1 RttWr: 2
371509.522: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
371609.522: DIMM 0 RttWr: 2
371709.522: AgesaHwWlPhase1: training nibble 0
371809.522: DIMM 1 RttNom: 3
371909.522: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
372009.522: DIMM 1 RttWr: 2
372109.522: DIMM 1 RttWr: 2
372209.522: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
372309.522: DIMM 1 RttWr: 2
372409.522: DIMM 1 RttNom: 3
372509.522: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
372609.522: DIMM 1 RttNom: 3
372709.522: DIMM 1 RttWr: 2
372809.522: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
372909.522: DIMM 1 RttWr: 2
373009.522: DIMM 0 RttNom: 3
373109.522: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
373209.522: DIMM 1 RttNom: 3
373309.522: DIMM 0 RttWr: 2
373409.523: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
373509.522: DIMM 1 RttWr: 2
373609.523: DIMM 0 RttNom: 3
373709.523: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
373809.523: DIMM 1 RttNom: 3
373909.523: DIMM 0 RttWr: 2
374009.523: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
374109.523: DIMM 1 RttWr: 2
374209.523: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
374309.523: <09>Lane 00 initial seed: 0041
374409.523: <09>Lane 01 initial seed: 0041
374509.523: <09>Lane 02 initial seed: 0041
374609.523: <09>Lane 03 initial seed: 0041
374709.523: <09>Lane 04 initial seed: 0041
374809.523: <09>Lane 05 initial seed: 0041
374909.523: <09>Lane 06 initial seed: 0041
375009.523: <09>Lane 07 initial seed: 0041
375109.523: <09>Lane 08 initial seed: 0041
375209.523: <09>Lane 00 nibble 0 raw readback: 0042
375309.523: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0042
375409.523: <09>Lane 00 nibble 0 adjusted value (post nibble): 0042
375509.523: <09>Lane 01 nibble 0 raw readback: 0040
375609.523: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
375709.523: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
375809.523: <09>Lane 02 nibble 0 raw readback: 003c
375909.523: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
376009.523: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
376109.523: <09>Lane 03 nibble 0 raw readback: 0039
376209.523: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0039
376309.523: <09>Lane 03 nibble 0 adjusted value (post nibble): 0039
376409.523: <09>Lane 04 nibble 0 raw readback: 0038
376509.523: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
376609.523: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
376709.523: <09>Lane 05 nibble 0 raw readback: 003b
376809.523: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
376909.523: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
377009.523: <09>Lane 06 nibble 0 raw readback: 003e
377109.523: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
377209.523: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
377309.523: <09>Lane 07 nibble 0 raw readback: 0040
377409.523: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
377509.523: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
377609.523: <09>Lane 08 nibble 0 raw readback: 0036
377709.523: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
377809.523: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
377909.523: AgesaHwWlPhase1: training nibble 1
378009.523: DIMM 1 RttNom: 3
378109.523: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
378209.523: DIMM 1 RttWr: 2
378309.523: DIMM 1 RttWr: 2
378409.523: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
378509.523: DIMM 1 RttWr: 2
378609.523: DIMM 1 RttNom: 3
378709.523: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
378809.523: DIMM 1 RttNom: 3
378909.523: DIMM 1 RttWr: 2
379009.523: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
379109.523: DIMM 1 RttWr: 2
379209.523: DIMM 0 RttNom: 3
379309.523: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
379409.523: DIMM 1 RttNom: 3
379509.523: DIMM 0 RttWr: 2
379609.523: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
379709.523: DIMM 1 RttWr: 2
379809.523: DIMM 0 RttNom: 3
379909.523: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
380009.523: DIMM 1 RttNom: 3
380109.523: DIMM 0 RttWr: 2
380209.523: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
380309.523: DIMM 1 RttWr: 2
380409.524: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
380509.523: <09>Lane 00 initial seed: 0041
380609.523: <09>Lane 01 initial seed: 0041
380709.523: <09>Lane 02 initial seed: 0041
380809.524: <09>Lane 03 initial seed: 0041
380909.524: <09>Lane 04 initial seed: 0041
381009.524: <09>Lane 05 initial seed: 0041
381109.524: <09>Lane 06 initial seed: 0041
381209.524: <09>Lane 07 initial seed: 0041
381309.524: <09>Lane 08 initial seed: 0041
381409.524: <09>Lane 00 nibble 1 raw readback: 0043
381509.524: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
381609.524: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
381709.524: <09>Lane 01 nibble 1 raw readback: 003f
381809.524: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
381909.524: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
382009.524: <09>Lane 02 nibble 1 raw readback: 003c
382109.524: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
382209.524: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
382309.524: <09>Lane 03 nibble 1 raw readback: 003a
382409.524: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
382509.524: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
382609.524: <09>Lane 04 nibble 1 raw readback: 0038
382709.524: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
382809.524: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
382909.524: <09>Lane 05 nibble 1 raw readback: 003a
383009.524: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
383109.524: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
383209.524: <09>Lane 06 nibble 1 raw readback: 003f
383309.524: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
383409.524: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
383509.524: <09>Lane 07 nibble 1 raw readback: 0041
383609.524: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
383709.524: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
383809.524: <09>Lane 08 nibble 1 raw readback: 0037
383909.524: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
384009.524: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
384109.524: <09>original critical gross delay: 0
384209.524: <09>new critical gross delay: 0
384309.524: DIMM 1 RttNom: 3
384409.524: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
384509.524: DIMM 1 RttNom: 3
384609.524: DIMM 1 RttWr: 2
384709.524: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
384809.524: DIMM 1 RttWr: 2
384909.524: DIMM 1 RttNom: 3
385009.524: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
385109.524: DIMM 1 RttNom: 3
385209.524: DIMM 1 RttWr: 2
385309.524: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
385409.524: DIMM 1 RttWr: 2
385509.524: DIMM 0 RttNom: 3
385609.524: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
385709.524: DIMM 1 RttNom: 3
385809.524: DIMM 0 RttWr: 2
385909.524: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
386009.524: DIMM 1 RttWr: 2
386109.524: DIMM 0 RttNom: 3
386209.524: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
386309.524: DIMM 1 RttNom: 3
386409.524: DIMM 0 RttWr: 2
386509.524: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
386609.524: DIMM 1 RttWr: 2
386709.525: activate_spd_rom() for node 02
386809.525: enable_spd_node2()
386909.525: AgesaHwWlPhase1: training nibble 0
387009.525: DIMM 0 RttNom: 3
387109.525: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
387209.525: DIMM 0 RttWr: 2
387309.525: DIMM 0 RttWr: 2
387409.525: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
387509.525: DIMM 0 RttWr: 2
387609.525: DIMM 0 RttNom: 3
387709.525: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
387809.525: DIMM 0 RttNom: 3
387909.525: DIMM 0 RttWr: 2
388009.525: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
388109.525: DIMM 0 RttWr: 2
388209.525: DIMM 1 RttNom: 3
388309.525: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
388409.525: DIMM 0 RttNom: 3
388509.525: DIMM 1 RttWr: 2
388609.525: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
388709.525: DIMM 0 RttWr: 2
388809.525: DIMM 1 RttNom: 3
388909.525: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
389009.525: DIMM 0 RttNom: 3
389109.525: DIMM 1 RttWr: 2
389209.525: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
389309.525: DIMM 0 RttWr: 2
389409.525: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
389509.525: <09>Lane 00 initial seed: 0041
389609.525: <09>Lane 01 initial seed: 0041
389709.525: <09>Lane 02 initial seed: 0041
389809.525: <09>Lane 03 initial seed: 0041
389909.525: <09>Lane 04 initial seed: 0041
390009.525: <09>Lane 05 initial seed: 0041
390109.525: <09>Lane 06 initial seed: 0041
390209.525: <09>Lane 07 initial seed: 0041
390309.525: <09>Lane 08 initial seed: 0041
390409.525: <09>Lane 00 nibble 0 raw readback: 004c
390509.525: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
390609.525: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
390709.525: <09>Lane 01 nibble 0 raw readback: 0045
390809.525: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0045
390909.525: <09>Lane 01 nibble 0 adjusted value (post nibble): 0045
391009.525: <09>Lane 02 nibble 0 raw readback: 0044
391109.525: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0044
391209.525: <09>Lane 02 nibble 0 adjusted value (post nibble): 0044
391309.525: <09>Lane 03 nibble 0 raw readback: 0042
391409.525: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
391509.525: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
391609.525: <09>Lane 04 nibble 0 raw readback: 003a
391709.525: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
391809.525: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
391909.525: <09>Lane 05 nibble 0 raw readback: 003d
392009.525: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
392109.526: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
392209.526: <09>Lane 06 nibble 0 raw readback: 0040
392309.526: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
392409.526: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
392509.526: <09>Lane 07 nibble 0 raw readback: 0042
392609.526: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
392709.526: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
392809.526: <09>Lane 08 nibble 0 raw readback: 003b
392909.526: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
393009.526: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
393109.526: AgesaHwWlPhase1: training nibble 1
393209.526: DIMM 0 RttNom: 3
393309.526: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
393409.526: DIMM 0 RttWr: 2
393509.526: DIMM 0 RttWr: 2
393609.526: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
393709.526: DIMM 0 RttWr: 2
393809.526: DIMM 0 RttNom: 3
393909.526: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
394009.526: DIMM 0 RttNom: 3
394109.526: DIMM 0 RttWr: 2
394209.526: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
394309.526: DIMM 0 RttWr: 2
394409.526: DIMM 1 RttNom: 3
394509.526: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
394609.526: DIMM 0 RttNom: 3
394709.526: DIMM 1 RttWr: 2
394809.526: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
394909.526: DIMM 0 RttWr: 2
395009.526: DIMM 1 RttNom: 3
395109.526: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
395209.526: DIMM 0 RttNom: 3
395309.526: DIMM 1 RttWr: 2
395409.526: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
395509.526: DIMM 0 RttWr: 2
395609.526: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
395709.526: <09>Lane 00 initial seed: 0041
395809.526: <09>Lane 01 initial seed: 0041
395909.526: <09>Lane 02 initial seed: 0041
396009.526: <09>Lane 03 initial seed: 0041
396109.526: <09>Lane 04 initial seed: 0041
396209.526: <09>Lane 05 initial seed: 0041
396309.526: <09>Lane 06 initial seed: 0041
396409.526: <09>Lane 07 initial seed: 0041
396509.526: <09>Lane 08 initial seed: 0041
396609.526: <09>Lane 00 nibble 1 raw readback: 004a
396709.526: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
396809.526: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
396909.526: <09>Lane 01 nibble 1 raw readback: 0046
397009.526: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0046
397109.526: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
397209.526: <09>Lane 02 nibble 1 raw readback: 0045
397309.526: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0045
397409.526: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
397509.526: <09>Lane 03 nibble 1 raw readback: 0041
397609.526: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0041
397709.526: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
397809.526: <09>Lane 04 nibble 1 raw readback: 0039
397909.526: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
398009.526: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
398109.526: <09>Lane 05 nibble 1 raw readback: 003c
398209.526: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
398309.526: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
398409.526: <09>Lane 06 nibble 1 raw readback: 003f
398509.526: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
398609.526: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
398709.527: <09>Lane 07 nibble 1 raw readback: 0041
398809.526: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
398909.526: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
399009.527: <09>Lane 08 nibble 1 raw readback: 003a
399109.527: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
399209.527: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
399309.527: <09>original critical gross delay: 0
399409.527: <09>new critical gross delay: 0
399509.527: DIMM 0 RttNom: 3
399609.527: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
399709.527: DIMM 0 RttNom: 3
399809.527: DIMM 0 RttWr: 2
399909.527: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
400009.527: DIMM 0 RttWr: 2
400109.527: DIMM 0 RttNom: 3
400209.527: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
400309.527: DIMM 0 RttNom: 3
400409.527: DIMM 0 RttWr: 2
400509.527: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
400609.527: DIMM 0 RttWr: 2
400709.527: DIMM 1 RttNom: 3
400809.527: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
400909.527: DIMM 0 RttNom: 3
401009.527: DIMM 1 RttWr: 2
401109.527: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
401209.527: DIMM 0 RttWr: 2
401309.527: DIMM 1 RttNom: 3
401409.527: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
401509.527: DIMM 0 RttNom: 3
401609.527: DIMM 1 RttWr: 2
401709.527: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
401809.527: DIMM 0 RttWr: 2
401909.527: AgesaHwWlPhase1: training nibble 0
402009.527: DIMM 1 RttNom: 3
402109.527: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
402209.527: DIMM 1 RttWr: 2
402309.527: DIMM 1 RttWr: 2
402409.527: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
402509.527: DIMM 1 RttWr: 2
402609.527: DIMM 1 RttNom: 3
402709.527: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
402809.527: DIMM 1 RttNom: 3
402909.527: DIMM 1 RttWr: 2
403009.527: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
403109.527: DIMM 1 RttWr: 2
403209.527: DIMM 0 RttNom: 3
403309.527: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
403409.527: DIMM 1 RttNom: 3
403509.527: DIMM 0 RttWr: 2
403609.527: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
403709.527: DIMM 1 RttWr: 2
403809.527: DIMM 0 RttNom: 3
403909.527: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
404009.527: DIMM 1 RttNom: 3
404109.527: DIMM 0 RttWr: 2
404209.527: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
404309.527: DIMM 1 RttWr: 2
404409.527: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
404509.527: <09>Lane 00 initial seed: 0041
404609.527: <09>Lane 01 initial seed: 0041
404709.528: <09>Lane 02 initial seed: 0041
404809.528: <09>Lane 03 initial seed: 0041
404909.528: <09>Lane 04 initial seed: 0041
405009.528: <09>Lane 05 initial seed: 0041
405109.528: <09>Lane 06 initial seed: 0041
405209.528: <09>Lane 07 initial seed: 0041
405309.528: <09>Lane 08 initial seed: 0041
405409.528: <09>Lane 00 nibble 0 raw readback: 0040
405509.528: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0040
405609.528: <09>Lane 00 nibble 0 adjusted value (post nibble): 0040
405709.528: <09>Lane 01 nibble 0 raw readback: 003b
405809.528: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003b
405909.528: <09>Lane 01 nibble 0 adjusted value (post nibble): 003b
406009.528: <09>Lane 02 nibble 0 raw readback: 0039
406109.528: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
406209.528: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
406309.528: <09>Lane 03 nibble 0 raw readback: 0036
406409.528: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
406509.528: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
406609.528: <09>Lane 04 nibble 0 raw readback: 002e
406709.528: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
406809.528: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
406909.528: <09>Lane 05 nibble 0 raw readback: 0032
407009.528: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
407109.528: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
407209.528: <09>Lane 06 nibble 0 raw readback: 0034
407309.528: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0034
407409.528: <09>Lane 06 nibble 0 adjusted value (post nibble): 0034
407509.528: <09>Lane 07 nibble 0 raw readback: 0036
407609.528: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
407709.528: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
407809.528: <09>Lane 08 nibble 0 raw readback: 0030
407909.528: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
408009.528: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
408109.528: AgesaHwWlPhase1: training nibble 1
408209.528: DIMM 1 RttNom: 3
408309.528: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
408409.528: DIMM 1 RttWr: 2
408509.528: DIMM 1 RttWr: 2
408609.528: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
408709.528: DIMM 1 RttWr: 2
408809.528: DIMM 1 RttNom: 3
408909.528: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
409009.528: DIMM 1 RttNom: 3
409109.528: DIMM 1 RttWr: 2
409209.528: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
409309.528: DIMM 1 RttWr: 2
409409.528: DIMM 0 RttNom: 3
409509.528: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
409609.528: DIMM 1 RttNom: 3
409709.528: DIMM 0 RttWr: 2
409809.528: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
409909.528: DIMM 1 RttWr: 2
410009.528: DIMM 0 RttNom: 3
410109.528: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
410209.528: DIMM 1 RttNom: 3
410309.528: DIMM 0 RttWr: 2
410409.528: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
410509.528: DIMM 1 RttWr: 2
410609.528: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
410709.528: <09>Lane 00 initial seed: 0041
410809.528: <09>Lane 01 initial seed: 0041
410909.528: <09>Lane 02 initial seed: 0041
411009.528: <09>Lane 03 initial seed: 0041
411109.528: <09>Lane 04 initial seed: 0041
411209.528: <09>Lane 05 initial seed: 0041
411309.528: <09>Lane 06 initial seed: 0041
411409.528: <09>Lane 07 initial seed: 0041
411509.528: <09>Lane 08 initial seed: 0041
411609.528: <09>Lane 00 nibble 1 raw readback: 003f
411709.529: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
411809.529: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
411909.529: <09>Lane 01 nibble 1 raw readback: 003b
412009.529: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003b
412109.529: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
412209.529: <09>Lane 02 nibble 1 raw readback: 003a
412309.529: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003a
412409.529: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
412509.529: <09>Lane 03 nibble 1 raw readback: 0037
412609.529: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
412709.529: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
412809.529: <09>Lane 04 nibble 1 raw readback: 002e
412909.529: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
413009.529: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
413109.529: <09>Lane 05 nibble 1 raw readback: 0031
413209.529: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
413309.529: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
413409.529: <09>Lane 06 nibble 1 raw readback: 0033
413509.529: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
413609.529: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
413709.529: <09>Lane 07 nibble 1 raw readback: 0037
413809.529: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0037
413909.529: <09>Lane 07 nibble 1 adjusted value (post nibble): 003c
414009.529: <09>Lane 08 nibble 1 raw readback: 002f
414109.529: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
414209.529: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
414309.529: <09>original critical gross delay: 0
414409.529: <09>new critical gross delay: 0
414509.529: DIMM 1 RttNom: 3
414609.529: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
414709.529: DIMM 1 RttNom: 3
414809.529: DIMM 1 RttWr: 2
414909.529: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
415009.529: DIMM 1 RttWr: 2
415109.529: DIMM 1 RttNom: 3
415209.529: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
415309.529: DIMM 1 RttNom: 3
415409.529: DIMM 1 RttWr: 2
415509.529: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
415609.529: DIMM 1 RttWr: 2
415709.529: DIMM 0 RttNom: 3
415809.529: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
415909.529: DIMM 1 RttNom: 3
416009.529: DIMM 0 RttWr: 2
416109.529: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
416209.529: DIMM 1 RttWr: 2
416309.529: DIMM 0 RttNom: 3
416409.529: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
416509.529: DIMM 1 RttNom: 3
416609.529: DIMM 0 RttWr: 2
416709.529: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
416809.529: DIMM 1 RttWr: 2
416909.529: AgesaHwWlPhase1: training nibble 0
417009.529: DIMM 0 RttNom: 3
417109.529: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
417209.529: DIMM 0 RttWr: 2
417309.529: DIMM 0 RttWr: 2
417409.529: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
417509.529: DIMM 0 RttWr: 2
417609.529: DIMM 0 RttNom: 3
417709.529: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
417809.529: DIMM 0 RttNom: 3
417909.529: DIMM 0 RttWr: 2
418009.529: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
418109.529: DIMM 0 RttWr: 2
418209.529: DIMM 1 RttNom: 3
418309.530: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
418409.530: DIMM 0 RttNom: 3
418509.530: DIMM 1 RttWr: 2
418609.530: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
418709.530: DIMM 0 RttWr: 2
418809.530: DIMM 1 RttNom: 3
418909.530: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
419009.530: DIMM 0 RttNom: 3
419109.530: DIMM 1 RttWr: 2
419209.530: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
419309.530: DIMM 0 RttWr: 2
419409.530: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
419509.530: <09>Lane 00 initial seed: 0041
419609.530: <09>Lane 01 initial seed: 0041
419709.530: <09>Lane 02 initial seed: 0041
419809.530: <09>Lane 03 initial seed: 0041
419909.530: <09>Lane 04 initial seed: 0041
420009.530: <09>Lane 05 initial seed: 0041
420109.530: <09>Lane 06 initial seed: 0041
420209.530: <09>Lane 07 initial seed: 0041
420309.530: <09>Lane 08 initial seed: 0041
420409.530: <09>Lane 00 nibble 0 raw readback: 004a
420509.530: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004a
420609.530: <09>Lane 00 nibble 0 adjusted value (post nibble): 004a
420709.530: <09>Lane 01 nibble 0 raw readback: 0047
420809.530: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
420909.530: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
421009.530: <09>Lane 02 nibble 0 raw readback: 0044
421109.530: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0044
421209.530: <09>Lane 02 nibble 0 adjusted value (post nibble): 0044
421309.530: <09>Lane 03 nibble 0 raw readback: 0041
421409.530: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0041
421509.530: <09>Lane 03 nibble 0 adjusted value (post nibble): 0041
421609.530: <09>Lane 04 nibble 0 raw readback: 0039
421709.530: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
421809.530: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
421909.530: <09>Lane 05 nibble 0 raw readback: 003c
422009.530: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
422109.530: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
422209.530: <09>Lane 06 nibble 0 raw readback: 003f
422309.530: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
422409.530: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
422509.530: <09>Lane 07 nibble 0 raw readback: 0041
422609.530: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
422709.530: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
422809.530: <09>Lane 08 nibble 0 raw readback: 003b
422909.530: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
423009.530: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
423109.530: AgesaHwWlPhase1: training nibble 1
423209.530: DIMM 0 RttNom: 3
423309.530: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
423409.530: DIMM 0 RttWr: 2
423509.530: DIMM 0 RttWr: 2
423609.530: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
423709.530: DIMM 0 RttWr: 2
423809.530: DIMM 0 RttNom: 3
423909.530: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
424009.530: DIMM 0 RttNom: 3
424109.530: DIMM 0 RttWr: 2
424209.530: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
424309.530: DIMM 0 RttWr: 2
424409.530: DIMM 1 RttNom: 3
424509.530: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
424609.530: DIMM 0 RttNom: 3
424709.530: DIMM 1 RttWr: 2
424809.530: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
424909.530: DIMM 0 RttWr: 2
425009.530: DIMM 1 RttNom: 3
425109.530: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
425209.531: DIMM 0 RttNom: 3
425309.531: DIMM 1 RttWr: 2
425409.531: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
425509.531: DIMM 0 RttWr: 2
425609.531: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
425709.531: <09>Lane 00 initial seed: 0041
425809.531: <09>Lane 01 initial seed: 0041
425909.531: <09>Lane 02 initial seed: 0041
426009.531: <09>Lane 03 initial seed: 0041
426109.531: <09>Lane 04 initial seed: 0041
426209.531: <09>Lane 05 initial seed: 0041
426309.531: <09>Lane 06 initial seed: 0041
426409.531: <09>Lane 07 initial seed: 0041
426509.531: <09>Lane 08 initial seed: 0041
426609.531: <09>Lane 00 nibble 1 raw readback: 004a
426709.531: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
426809.531: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
426909.531: <09>Lane 01 nibble 1 raw readback: 0047
427009.531: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
427109.531: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
427209.531: <09>Lane 02 nibble 1 raw readback: 0044
427309.531: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
427409.531: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
427509.531: <09>Lane 03 nibble 1 raw readback: 0042
427609.531: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0042
427709.531: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
427809.531: <09>Lane 04 nibble 1 raw readback: 0039
427909.531: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
428009.531: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
428109.531: <09>Lane 05 nibble 1 raw readback: 003c
428209.531: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
428309.531: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
428409.531: <09>Lane 06 nibble 1 raw readback: 003f
428509.531: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
428609.531: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
428709.531: <09>Lane 07 nibble 1 raw readback: 0041
428809.531: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
428909.531: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
429009.531: <09>Lane 08 nibble 1 raw readback: 003b
429109.531: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
429209.531: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
429309.531: <09>original critical gross delay: 0
429409.531: <09>new critical gross delay: 0
429509.531: DIMM 0 RttNom: 3
429609.531: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
429709.531: DIMM 0 RttNom: 3
429809.531: DIMM 0 RttWr: 2
429909.531: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
430009.531: DIMM 0 RttWr: 2
430109.531: DIMM 0 RttNom: 3
430209.531: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
430309.531: DIMM 0 RttNom: 3
430409.531: DIMM 0 RttWr: 2
430509.531: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
430609.531: DIMM 0 RttWr: 2
430709.531: DIMM 1 RttNom: 3
430809.531: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
430909.531: DIMM 0 RttNom: 3
431009.531: DIMM 1 RttWr: 2
431109.531: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
431209.531: DIMM 0 RttWr: 2
431309.531: DIMM 1 RttNom: 3
431409.531: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
431509.531: DIMM 0 RttNom: 3
431609.531: DIMM 1 RttWr: 2
431709.531: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
431809.531: DIMM 0 RttWr: 2
431909.532: AgesaHwWlPhase1: training nibble 0
432009.532: DIMM 1 RttNom: 3
432109.532: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
432209.532: DIMM 1 RttWr: 2
432309.532: DIMM 1 RttWr: 2
432409.532: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
432509.532: DIMM 1 RttWr: 2
432609.532: DIMM 1 RttNom: 3
432709.532: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
432809.532: DIMM 1 RttNom: 3
432909.532: DIMM 1 RttWr: 2
433009.532: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
433109.532: DIMM 1 RttWr: 2
433209.532: DIMM 0 RttNom: 3
433309.532: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
433409.532: DIMM 1 RttNom: 3
433509.532: DIMM 0 RttWr: 2
433609.532: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
433709.532: DIMM 1 RttWr: 2
433809.532: DIMM 0 RttNom: 3
433909.532: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
434009.532: DIMM 1 RttNom: 3
434109.532: DIMM 0 RttWr: 2
434209.532: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
434309.532: DIMM 1 RttWr: 2
434409.532: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
434509.532: <09>Lane 00 initial seed: 0041
434609.532: <09>Lane 01 initial seed: 0041
434709.532: <09>Lane 02 initial seed: 0041
434809.532: <09>Lane 03 initial seed: 0041
434909.532: <09>Lane 04 initial seed: 0041
435009.532: <09>Lane 05 initial seed: 0041
435109.532: <09>Lane 06 initial seed: 0041
435209.532: <09>Lane 07 initial seed: 0041
435309.532: <09>Lane 08 initial seed: 0041
435409.532: <09>Lane 00 nibble 0 raw readback: 003f
435509.532: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
435609.532: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
435709.532: <09>Lane 01 nibble 0 raw readback: 003c
435809.532: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
435909.532: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
436009.532: <09>Lane 02 nibble 0 raw readback: 0038
436109.532: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
436209.532: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
436309.532: <09>Lane 03 nibble 0 raw readback: 0035
436409.532: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0035
436509.532: <09>Lane 03 nibble 0 adjusted value (post nibble): 0035
436609.532: <09>Lane 04 nibble 0 raw readback: 002d
436709.532: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002d
436809.532: <09>Lane 04 nibble 0 adjusted value (post nibble): 002d
436909.532: <09>Lane 05 nibble 0 raw readback: 0030
437009.532: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0030
437109.532: <09>Lane 05 nibble 0 adjusted value (post nibble): 0030
437209.532: <09>Lane 06 nibble 0 raw readback: 0033
437309.532: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
437409.532: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
437509.532: <09>Lane 07 nibble 0 raw readback: 0036
437609.532: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
437709.532: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
437809.532: <09>Lane 08 nibble 0 raw readback: 0030
437909.532: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
438009.532: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
438109.532: AgesaHwWlPhase1: training nibble 1
438209.532: DIMM 1 RttNom: 3
438309.532: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
438409.532: DIMM 1 RttWr: 2
438509.532: DIMM 1 RttWr: 2
438609.532: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
438709.532: DIMM 1 RttWr: 2
438809.533: DIMM 1 RttNom: 3
438909.533: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
439009.533: DIMM 1 RttNom: 3
439109.533: DIMM 1 RttWr: 2
439209.533: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
439309.533: DIMM 1 RttWr: 2
439409.533: DIMM 0 RttNom: 3
439509.533: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
439609.533: DIMM 1 RttNom: 3
439709.533: DIMM 0 RttWr: 2
439809.533: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
439909.533: DIMM 1 RttWr: 2
440009.533: DIMM 0 RttNom: 3
440109.533: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
440209.533: DIMM 1 RttNom: 3
440309.533: DIMM 0 RttWr: 2
440409.533: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
440509.533: DIMM 1 RttWr: 2
440609.533: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
440709.533: <09>Lane 00 initial seed: 0041
440809.533: <09>Lane 01 initial seed: 0041
440909.533: <09>Lane 02 initial seed: 0041
441009.533: <09>Lane 03 initial seed: 0041
441109.533: <09>Lane 04 initial seed: 0041
441209.533: <09>Lane 05 initial seed: 0041
441309.533: <09>Lane 06 initial seed: 0041
441409.533: <09>Lane 07 initial seed: 0041
441509.533: <09>Lane 08 initial seed: 0041
441609.533: <09>Lane 00 nibble 1 raw readback: 003d
441709.533: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003d
441809.533: <09>Lane 00 nibble 1 adjusted value (post nibble): 003f
441909.533: <09>Lane 01 nibble 1 raw readback: 003c
442009.533: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
442109.533: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
442209.533: <09>Lane 02 nibble 1 raw readback: 0038
442309.533: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0038
442409.533: <09>Lane 02 nibble 1 adjusted value (post nibble): 003c
442509.533: <09>Lane 03 nibble 1 raw readback: 0036
442609.533: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
442709.533: <09>Lane 03 nibble 1 adjusted value (post nibble): 003b
442809.533: <09>Lane 04 nibble 1 raw readback: 002e
442909.533: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
443009.533: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
443109.533: <09>Lane 05 nibble 1 raw readback: 0030
443209.533: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0030
443309.533: <09>Lane 05 nibble 1 adjusted value (post nibble): 0038
443409.533: <09>Lane 06 nibble 1 raw readback: 0034
443509.533: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0034
443609.533: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
443709.533: <09>Lane 07 nibble 1 raw readback: 0036
443809.533: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
443909.533: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
444009.533: <09>Lane 08 nibble 1 raw readback: 002f
444109.533: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
444209.533: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
444309.533: <09>original critical gross delay: 0
444409.533: <09>new critical gross delay: 0
444509.533: DIMM 1 RttNom: 3
444609.533: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
444709.533: DIMM 1 RttNom: 3
444809.533: DIMM 1 RttWr: 2
444909.533: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
445009.533: DIMM 1 RttWr: 2
445109.533: DIMM 1 RttNom: 3
445209.534: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
445309.533: DIMM 1 RttNom: 3
445409.534: DIMM 1 RttWr: 2
445509.534: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
445609.534: DIMM 1 RttWr: 2
445709.534: DIMM 0 RttNom: 3
445809.534: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
445909.534: DIMM 1 RttNom: 3
446009.534: DIMM 0 RttWr: 2
446109.534: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
446209.534: DIMM 1 RttWr: 2
446309.534: DIMM 0 RttNom: 3
446409.534: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
446509.534: DIMM 1 RttNom: 3
446609.534: DIMM 0 RttWr: 2
446709.534: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
446809.534: DIMM 1 RttWr: 2
446909.534: activate_spd_rom() for node 03
447009.534: enable_spd_node3()
447109.534: AgesaHwWlPhase1: training nibble 0
447209.534: DIMM 0 RttNom: 3
447309.534: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
447409.534: DIMM 0 RttWr: 2
447509.534: DIMM 0 RttWr: 2
447609.534: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
447709.534: DIMM 0 RttWr: 2
447809.534: DIMM 0 RttNom: 3
447909.534: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
448009.534: DIMM 0 RttNom: 3
448109.534: DIMM 0 RttWr: 2
448209.534: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
448309.534: DIMM 0 RttWr: 2
448409.534: DIMM 1 RttNom: 3
448509.534: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
448609.534: DIMM 0 RttNom: 3
448709.534: DIMM 1 RttWr: 2
448809.534: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
448909.534: DIMM 0 RttWr: 2
449009.534: DIMM 1 RttNom: 3
449109.534: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
449209.534: DIMM 0 RttNom: 3
449309.534: DIMM 1 RttWr: 2
449409.534: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
449509.534: DIMM 0 RttWr: 2
449609.534: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
449709.534: <09>Lane 00 initial seed: 0041
449809.534: <09>Lane 01 initial seed: 0041
449909.534: <09>Lane 02 initial seed: 0041
450009.534: <09>Lane 03 initial seed: 0041
450109.534: <09>Lane 04 initial seed: 0041
450209.535: <09>Lane 05 initial seed: 0041
450309.535: <09>Lane 06 initial seed: 0041
450409.535: <09>Lane 07 initial seed: 0041
450509.535: <09>Lane 08 initial seed: 0041
450609.535: <09>Lane 00 nibble 0 raw readback: 0043
450709.535: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
450809.535: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
450909.535: <09>Lane 01 nibble 0 raw readback: 003d
451009.535: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003d
451109.535: <09>Lane 01 nibble 0 adjusted value (post nibble): 003d
451209.535: <09>Lane 02 nibble 0 raw readback: 003b
451309.535: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
451409.535: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
451509.535: <09>Lane 03 nibble 0 raw readback: 003b
451609.535: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
451709.535: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
451809.535: <09>Lane 04 nibble 0 raw readback: 003a
451909.535: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
452009.535: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
452109.535: <09>Lane 05 nibble 0 raw readback: 003c
452209.535: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
452309.535: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
452409.535: <09>Lane 06 nibble 0 raw readback: 003e
452509.535: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
452609.535: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
452709.535: <09>Lane 07 nibble 0 raw readback: 0040
452809.535: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
452909.535: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
453009.535: <09>Lane 08 nibble 0 raw readback: 0036
453109.535: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
453209.535: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
453309.535: AgesaHwWlPhase1: training nibble 1
453409.535: DIMM 0 RttNom: 3
453509.535: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
453609.535: DIMM 0 RttWr: 2
453709.535: DIMM 0 RttWr: 2
453809.535: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
453909.535: DIMM 0 RttWr: 2
454009.535: DIMM 0 RttNom: 3
454109.535: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
454209.535: DIMM 0 RttNom: 3
454309.535: DIMM 0 RttWr: 2
454409.535: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
454509.535: DIMM 0 RttWr: 2
454609.535: DIMM 1 RttNom: 3
454709.535: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
454809.535: DIMM 0 RttNom: 3
454909.535: DIMM 1 RttWr: 2
455009.535: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
455109.535: DIMM 0 RttWr: 2
455209.535: DIMM 1 RttNom: 3
455309.535: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
455409.535: DIMM 0 RttNom: 3
455509.535: DIMM 1 RttWr: 2
455609.535: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
455709.535: DIMM 0 RttWr: 2
455809.535: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
455909.535: <09>Lane 00 initial seed: 0041
456009.535: <09>Lane 01 initial seed: 0041
456109.535: <09>Lane 02 initial seed: 0041
456209.535: <09>Lane 03 initial seed: 0041
456309.535: <09>Lane 04 initial seed: 0041
456409.535: <09>Lane 05 initial seed: 0041
456509.535: <09>Lane 06 initial seed: 0041
456609.535: <09>Lane 07 initial seed: 0041
456709.535: <09>Lane 08 initial seed: 0041
456809.536: <09>Lane 00 nibble 1 raw readback: 0043
456909.536: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
457009.536: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
457109.536: <09>Lane 01 nibble 1 raw readback: 0040
457209.536: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
457309.536: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
457409.536: <09>Lane 02 nibble 1 raw readback: 003d
457509.536: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
457609.536: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
457709.536: <09>Lane 03 nibble 1 raw readback: 003a
457809.536: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
457909.536: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
458009.536: <09>Lane 04 nibble 1 raw readback: 0039
458109.536: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
458209.536: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
458309.536: <09>Lane 05 nibble 1 raw readback: 003b
458409.536: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
458509.536: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
458609.536: <09>Lane 06 nibble 1 raw readback: 003e
458709.536: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
458809.536: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
458909.536: <09>Lane 07 nibble 1 raw readback: 0042
459009.536: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
459109.536: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
459209.536: <09>Lane 08 nibble 1 raw readback: 0037
459309.536: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
459409.536: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
459509.536: <09>original critical gross delay: 0
459609.536: <09>new critical gross delay: 0
459709.536: DIMM 0 RttNom: 3
459809.536: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
459909.536: DIMM 0 RttNom: 3
460009.536: DIMM 0 RttWr: 2
460109.536: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
460209.536: DIMM 0 RttWr: 2
460309.536: DIMM 0 RttNom: 3
460409.536: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
460509.536: DIMM 0 RttNom: 3
460609.536: DIMM 0 RttWr: 2
460709.536: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
460809.536: DIMM 0 RttWr: 2
460909.536: DIMM 1 RttNom: 3
461009.536: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
461109.536: DIMM 0 RttNom: 3
461209.536: DIMM 1 RttWr: 2
461309.536: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
461409.536: DIMM 0 RttWr: 2
461509.536: DIMM 1 RttNom: 3
461609.536: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
461709.536: DIMM 0 RttNom: 3
461809.536: DIMM 1 RttWr: 2
461909.536: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
462009.536: DIMM 0 RttWr: 2
462109.536: AgesaHwWlPhase1: training nibble 0
462209.536: DIMM 1 RttNom: 3
462309.536: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
462409.536: DIMM 1 RttWr: 2
462509.536: DIMM 1 RttWr: 2
462609.536: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
462709.536: DIMM 1 RttWr: 2
462809.536: DIMM 1 RttNom: 3
462909.536: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
463009.536: DIMM 1 RttNom: 3
463109.536: DIMM 1 RttWr: 2
463209.537: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
463309.537: DIMM 1 RttWr: 2
463409.537: DIMM 0 RttNom: 3
463509.537: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
463609.537: DIMM 1 RttNom: 3
463709.537: DIMM 0 RttWr: 2
463809.537: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
463909.537: DIMM 1 RttWr: 2
464009.537: DIMM 0 RttNom: 3
464109.537: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
464209.537: DIMM 1 RttNom: 3
464309.537: DIMM 0 RttWr: 2
464409.537: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
464509.537: DIMM 1 RttWr: 2
464609.537: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
464709.537: <09>Lane 00 initial seed: 0041
464809.537: <09>Lane 01 initial seed: 0041
464909.537: <09>Lane 02 initial seed: 0041
465009.537: <09>Lane 03 initial seed: 0041
465109.537: <09>Lane 04 initial seed: 0041
465209.537: <09>Lane 05 initial seed: 0041
465309.537: <09>Lane 06 initial seed: 0041
465409.537: <09>Lane 07 initial seed: 0041
465509.537: <09>Lane 08 initial seed: 0041
465609.537: <09>Lane 00 nibble 0 raw readback: 0043
465709.537: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
465809.537: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
465909.537: <09>Lane 01 nibble 0 raw readback: 003e
466009.537: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
466109.537: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
466209.537: <09>Lane 02 nibble 0 raw readback: 003b
466309.537: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
466409.537: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
466509.537: <09>Lane 03 nibble 0 raw readback: 003a
466609.537: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
466709.537: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
466809.537: <09>Lane 04 nibble 0 raw readback: 0038
466909.537: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
467009.537: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
467109.537: <09>Lane 05 nibble 0 raw readback: 003b
467209.537: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
467309.537: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
467409.537: <09>Lane 06 nibble 0 raw readback: 003c
467509.537: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003c
467609.537: <09>Lane 06 nibble 0 adjusted value (post nibble): 003c
467709.537: <09>Lane 07 nibble 0 raw readback: 0040
467809.537: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
467909.537: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
468009.537: <09>Lane 08 nibble 0 raw readback: 0036
468109.537: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
468209.537: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
468309.537: AgesaHwWlPhase1: training nibble 1
468409.537: DIMM 1 RttNom: 3
468509.537: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
468609.537: DIMM 1 RttWr: 2
468709.537: DIMM 1 RttWr: 2
468809.537: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
468909.537: DIMM 1 RttWr: 2
469009.537: DIMM 1 RttNom: 3
469109.537: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
469209.537: DIMM 1 RttNom: 3
469309.537: DIMM 1 RttWr: 2
469409.537: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
469509.537: DIMM 1 RttWr: 2
469609.537: DIMM 0 RttNom: 3
469709.537: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
469809.537: DIMM 1 RttNom: 3
469909.537: DIMM 0 RttWr: 2
470009.537: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
470109.537: DIMM 1 RttWr: 2
470209.537: DIMM 0 RttNom: 3
470309.537: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
470409.538: DIMM 1 RttNom: 3
470509.538: DIMM 0 RttWr: 2
470609.538: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
470709.538: DIMM 1 RttWr: 2
470809.538: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
470909.538: <09>Lane 00 initial seed: 0041
471009.538: <09>Lane 01 initial seed: 0041
471109.538: <09>Lane 02 initial seed: 0041
471209.538: <09>Lane 03 initial seed: 0041
471309.538: <09>Lane 04 initial seed: 0041
471409.538: <09>Lane 05 initial seed: 0041
471509.538: <09>Lane 06 initial seed: 0041
471609.538: <09>Lane 07 initial seed: 0041
471709.538: <09>Lane 08 initial seed: 0041
471809.538: <09>Lane 00 nibble 1 raw readback: 0042
471909.538: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0042
472009.538: <09>Lane 00 nibble 1 adjusted value (post nibble): 0041
472109.538: <09>Lane 01 nibble 1 raw readback: 003f
472209.538: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
472309.538: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
472409.538: <09>Lane 02 nibble 1 raw readback: 003b
472509.538: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003b
472609.538: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
472709.538: <09>Lane 03 nibble 1 raw readback: 003a
472809.538: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
472909.538: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
473009.538: <09>Lane 04 nibble 1 raw readback: 0038
473109.538: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
473209.538: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
473309.538: <09>Lane 05 nibble 1 raw readback: 003a
473409.538: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
473509.538: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
473609.538: <09>Lane 06 nibble 1 raw readback: 003b
473709.538: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003b
473809.538: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
473909.538: <09>Lane 07 nibble 1 raw readback: 0040
474009.538: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
474109.538: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
474209.538: <09>Lane 08 nibble 1 raw readback: 0035
474309.538: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0035
474409.538: <09>Lane 08 nibble 1 adjusted value (post nibble): 003b
474509.538: <09>original critical gross delay: 0
474609.538: <09>new critical gross delay: 0
474709.538: DIMM 1 RttNom: 3
474809.538: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
474909.538: DIMM 1 RttNom: 3
475009.538: DIMM 1 RttWr: 2
475109.538: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
475209.538: DIMM 1 RttWr: 2
475309.538: DIMM 1 RttNom: 3
475409.538: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
475509.538: DIMM 1 RttNom: 3
475609.538: DIMM 1 RttWr: 2
475709.538: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
475809.538: DIMM 1 RttWr: 2
475909.538: DIMM 0 RttNom: 3
476009.538: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
476109.538: DIMM 1 RttNom: 3
476209.538: DIMM 0 RttWr: 2
476309.538: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
476409.538: DIMM 1 RttWr: 2
476509.538: DIMM 0 RttNom: 3
476609.538: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
476709.538: DIMM 1 RttNom: 3
476809.539: DIMM 0 RttWr: 2
476909.539: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
477009.539: DIMM 1 RttWr: 2
477109.539: AgesaHwWlPhase1: training nibble 0
477209.539: DIMM 0 RttNom: 3
477309.539: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
477409.539: DIMM 0 RttWr: 2
477509.539: DIMM 0 RttWr: 2
477609.539: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
477709.539: DIMM 0 RttWr: 2
477809.539: DIMM 0 RttNom: 3
477909.539: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
478009.539: DIMM 0 RttNom: 3
478109.539: DIMM 0 RttWr: 2
478209.539: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
478309.539: DIMM 0 RttWr: 2
478409.539: DIMM 1 RttNom: 3
478509.539: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
478609.539: DIMM 0 RttNom: 3
478709.539: DIMM 1 RttWr: 2
478809.539: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
478909.539: DIMM 0 RttWr: 2
479009.539: DIMM 1 RttNom: 3
479109.539: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
479209.539: DIMM 0 RttNom: 3
479309.539: DIMM 1 RttWr: 2
479409.539: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
479509.539: DIMM 0 RttWr: 2
479609.539: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
479709.539: <09>Lane 00 initial seed: 0041
479809.539: <09>Lane 01 initial seed: 0041
479909.539: <09>Lane 02 initial seed: 0041
480009.539: <09>Lane 03 initial seed: 0041
480109.539: <09>Lane 04 initial seed: 0041
480209.539: <09>Lane 05 initial seed: 0041
480309.539: <09>Lane 06 initial seed: 0041
480409.539: <09>Lane 07 initial seed: 0041
480509.539: <09>Lane 08 initial seed: 0041
480609.539: <09>Lane 00 nibble 0 raw readback: 0044
480709.539: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
480809.539: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
480909.539: <09>Lane 01 nibble 0 raw readback: 0040
481009.539: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
481109.539: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
481209.539: <09>Lane 02 nibble 0 raw readback: 003c
481309.539: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
481409.539: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
481509.539: <09>Lane 03 nibble 0 raw readback: 003a
481609.539: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
481709.539: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
481809.539: <09>Lane 04 nibble 0 raw readback: 003a
481909.539: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
482009.539: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
482109.539: <09>Lane 05 nibble 0 raw readback: 003d
482209.539: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
482309.539: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
482409.539: <09>Lane 06 nibble 0 raw readback: 0040
482509.539: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
482609.539: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
482709.539: <09>Lane 07 nibble 0 raw readback: 0043
482809.539: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
482909.539: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
483009.539: <09>Lane 08 nibble 0 raw readback: 0038
483109.539: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
483209.539: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
483309.539: AgesaHwWlPhase1: training nibble 1
483409.539: DIMM 0 RttNom: 3
483509.539: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
483609.540: DIMM 0 RttWr: 2
483709.540: DIMM 0 RttWr: 2
483809.540: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
483909.539: DIMM 0 RttWr: 2
484009.540: DIMM 0 RttNom: 3
484109.540: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
484209.540: DIMM 0 RttNom: 3
484309.540: DIMM 0 RttWr: 2
484409.540: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
484509.540: DIMM 0 RttWr: 2
484609.540: DIMM 1 RttNom: 3
484709.540: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
484809.540: DIMM 0 RttNom: 3
484909.540: DIMM 1 RttWr: 2
485009.540: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
485109.540: DIMM 0 RttWr: 2
485209.540: DIMM 1 RttNom: 3
485309.540: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
485409.540: DIMM 0 RttNom: 3
485509.540: DIMM 1 RttWr: 2
485609.540: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
485709.540: DIMM 0 RttWr: 2
485809.540: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
485909.540: <09>Lane 00 initial seed: 0041
486009.540: <09>Lane 01 initial seed: 0041
486109.540: <09>Lane 02 initial seed: 0041
486209.540: <09>Lane 03 initial seed: 0041
486309.540: <09>Lane 04 initial seed: 0041
486409.540: <09>Lane 05 initial seed: 0041
486509.540: <09>Lane 06 initial seed: 0041
486609.540: <09>Lane 07 initial seed: 0041
486709.540: <09>Lane 08 initial seed: 0041
486809.540: <09>Lane 00 nibble 1 raw readback: 0044
486909.540: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
487009.540: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
487109.540: <09>Lane 01 nibble 1 raw readback: 0041
487209.540: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
487309.540: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
487409.540: <09>Lane 02 nibble 1 raw readback: 003d
487509.540: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
487609.540: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
487709.540: <09>Lane 03 nibble 1 raw readback: 003b
487809.540: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
487909.540: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
488009.540: <09>Lane 04 nibble 1 raw readback: 0039
488109.540: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
488209.540: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
488309.540: <09>Lane 05 nibble 1 raw readback: 003c
488409.540: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
488509.540: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
488609.540: <09>Lane 06 nibble 1 raw readback: 003f
488709.540: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
488809.540: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
488909.540: <09>Lane 07 nibble 1 raw readback: 0042
489009.540: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
489109.540: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
489209.540: <09>Lane 08 nibble 1 raw readback: 0038
489309.540: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
489409.540: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
489509.540: <09>original critical gross delay: 0
489609.540: <09>new critical gross delay: 0
489709.540: DIMM 0 RttNom: 3
489809.540: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
489909.540: DIMM 0 RttNom: 3
490009.541: DIMM 0 RttWr: 2
490109.540: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
490209.540: DIMM 0 RttWr: 2
490309.540: DIMM 0 RttNom: 3
490409.541: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
490509.541: DIMM 0 RttNom: 3
490609.541: DIMM 0 RttWr: 2
490709.541: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
490809.541: DIMM 0 RttWr: 2
490909.541: DIMM 1 RttNom: 3
491009.541: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
491109.541: DIMM 0 RttNom: 3
491209.541: DIMM 1 RttWr: 2
491309.541: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
491409.541: DIMM 0 RttWr: 2
491509.541: DIMM 1 RttNom: 3
491609.541: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
491709.541: DIMM 0 RttNom: 3
491809.541: DIMM 1 RttWr: 2
491909.541: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
492009.541: DIMM 0 RttWr: 2
492109.541: AgesaHwWlPhase1: training nibble 0
492209.541: DIMM 1 RttNom: 3
492309.541: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
492409.541: DIMM 1 RttWr: 2
492509.541: DIMM 1 RttWr: 2
492609.541: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
492709.541: DIMM 1 RttWr: 2
492809.541: DIMM 1 RttNom: 3
492909.541: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
493009.541: DIMM 1 RttNom: 3
493109.541: DIMM 1 RttWr: 2
493209.541: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
493309.541: DIMM 1 RttWr: 2
493409.541: DIMM 0 RttNom: 3
493509.541: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
493609.541: DIMM 1 RttNom: 3
493709.541: DIMM 0 RttWr: 2
493809.541: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
493909.541: DIMM 1 RttWr: 2
494009.541: DIMM 0 RttNom: 3
494109.541: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
494209.541: DIMM 1 RttNom: 3
494309.541: DIMM 0 RttWr: 2
494409.541: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
494509.541: DIMM 1 RttWr: 2
494609.541: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
494709.541: <09>Lane 00 initial seed: 0041
494809.541: <09>Lane 01 initial seed: 0041
494909.541: <09>Lane 02 initial seed: 0041
495009.541: <09>Lane 03 initial seed: 0041
495109.541: <09>Lane 04 initial seed: 0041
495209.541: <09>Lane 05 initial seed: 0041
495309.541: <09>Lane 06 initial seed: 0041
495409.541: <09>Lane 07 initial seed: 0041
495509.541: <09>Lane 08 initial seed: 0041
495609.541: <09>Lane 00 nibble 0 raw readback: 0044
495709.541: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
495809.541: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
495909.541: <09>Lane 01 nibble 0 raw readback: 0040
496009.541: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
496109.541: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
496209.541: <09>Lane 02 nibble 0 raw readback: 003c
496309.541: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
496409.541: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
496509.541: <09>Lane 03 nibble 0 raw readback: 003a
496609.541: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
496709.541: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
496809.541: <09>Lane 04 nibble 0 raw readback: 0039
496909.541: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
497009.541: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
497109.541: <09>Lane 05 nibble 0 raw readback: 003d
497209.542: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
497309.542: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
497409.542: <09>Lane 06 nibble 0 raw readback: 0040
497509.542: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
497609.542: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
497709.542: <09>Lane 07 nibble 0 raw readback: 0043
497809.542: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
497909.542: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
498009.542: <09>Lane 08 nibble 0 raw readback: 0038
498109.542: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
498209.542: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
498309.542: AgesaHwWlPhase1: training nibble 1
498409.542: DIMM 1 RttNom: 3
498509.542: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
498609.542: DIMM 1 RttWr: 2
498709.542: DIMM 1 RttWr: 2
498809.542: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
498909.542: DIMM 1 RttWr: 2
499009.542: DIMM 1 RttNom: 3
499109.542: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
499209.542: DIMM 1 RttNom: 3
499309.542: DIMM 1 RttWr: 2
499409.542: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
499509.542: DIMM 1 RttWr: 2
499609.542: DIMM 0 RttNom: 3
499709.542: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
499809.542: DIMM 1 RttNom: 3
499909.542: DIMM 0 RttWr: 2
500009.542: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
500109.542: DIMM 1 RttWr: 2
500209.542: DIMM 0 RttNom: 3
500309.542: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
500409.542: DIMM 1 RttNom: 3
500509.542: DIMM 0 RttWr: 2
500609.542: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
500709.542: DIMM 1 RttWr: 2
500809.542: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
500909.542: <09>Lane 00 initial seed: 0041
501009.542: <09>Lane 01 initial seed: 0041
501109.542: <09>Lane 02 initial seed: 0041
501209.542: <09>Lane 03 initial seed: 0041
501309.542: <09>Lane 04 initial seed: 0041
501409.542: <09>Lane 05 initial seed: 0041
501509.542: <09>Lane 06 initial seed: 0041
501609.542: <09>Lane 07 initial seed: 0041
501709.542: <09>Lane 08 initial seed: 0041
501809.542: <09>Lane 00 nibble 1 raw readback: 0044
501909.542: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
502009.542: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
502109.542: <09>Lane 01 nibble 1 raw readback: 0041
502209.542: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
502309.542: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
502409.542: <09>Lane 02 nibble 1 raw readback: 003d
502509.542: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
502609.542: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
502709.542: <09>Lane 03 nibble 1 raw readback: 003b
502809.542: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
502909.542: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
503009.542: <09>Lane 04 nibble 1 raw readback: 0038
503109.542: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
503209.542: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
503309.542: <09>Lane 05 nibble 1 raw readback: 003c
503409.542: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
503509.542: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
503609.542: <09>Lane 06 nibble 1 raw readback: 003f
503709.542: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
503809.542: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
503909.542: <09>Lane 07 nibble 1 raw readback: 0042
504009.542: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
504109.542: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
504209.542: <09>Lane 08 nibble 1 raw readback: 0037
504309.542: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
504409.542: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
504509.543: <09>original critical gross delay: 0
504609.542: <09>new critical gross delay: 0
504709.543: DIMM 1 RttNom: 3
504809.543: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
504909.543: DIMM 1 RttNom: 3
505009.543: DIMM 1 RttWr: 2
505109.543: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
505209.543: DIMM 1 RttWr: 2
505309.543: DIMM 1 RttNom: 3
505409.543: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
505509.543: DIMM 1 RttNom: 3
505609.543: DIMM 1 RttWr: 2
505709.543: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
505809.543: DIMM 1 RttWr: 2
505909.543: DIMM 0 RttNom: 3
506009.543: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
506109.543: DIMM 1 RttNom: 3
506209.543: DIMM 0 RttWr: 2
506309.543: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
506409.543: DIMM 1 RttWr: 2
506509.543: DIMM 0 RttNom: 3
506609.543: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
506709.543: DIMM 1 RttNom: 3
506809.543: DIMM 0 RttWr: 2
506909.543: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
507009.543: DIMM 1 RttWr: 2
507109.545: fam15_receiver_enable_training_seed: using seed: 0054
507209.546: fam15_receiver_enable_training_seed: using seed: 0054
507309.546: fam15_receiver_enable_training_seed: using seed: 0054
507409.546: fam15_receiver_enable_training_seed: using seed: 0054
507509.547: fam15_receiver_enable_training_seed: using seed: 0054
507609.547: fam15_receiver_enable_training_seed: using seed: 0054
507709.547: fam15_receiver_enable_training_seed: using seed: 0054
507809.547: fam15_receiver_enable_training_seed: using seed: 0054
507909.547: fam15_receiver_enable_training_seed: using seed: 004d
508009.547: fam15_receiver_enable_training_seed: using seed: 004d
508109.547: fam15_receiver_enable_training_seed: using seed: 004d
508209.547: fam15_receiver_enable_training_seed: using seed: 004d
508309.547: fam15_receiver_enable_training_seed: using seed: 004d
508409.547: fam15_receiver_enable_training_seed: using seed: 004d
508509.547: fam15_receiver_enable_training_seed: using seed: 004d
508609.547: fam15_receiver_enable_training_seed: using seed: 004d
508709.548: TrainRcvrEn: Status 2205
508809.548: TrainRcvrEn: ErrStatus 0
508909.548: TrainRcvrEn: ErrCode 0
509009.548: TrainRcvrEn: Done
509109.548:
509209.548: fam15_receiver_enable_training_seed: using seed: 0045
509309.548: fam15_receiver_enable_training_seed: using seed: 0045
509409.549: fam15_receiver_enable_training_seed: using seed: 0045
509509.549: fam15_receiver_enable_training_seed: using seed: 0045
509609.549: fam15_receiver_enable_training_seed: using seed: 0045
509709.549: fam15_receiver_enable_training_seed: using seed: 0045
509809.549: fam15_receiver_enable_training_seed: using seed: 0045
509909.549: fam15_receiver_enable_training_seed: using seed: 0045
510009.549: fam15_receiver_enable_training_seed: using seed: 0040
510109.549: fam15_receiver_enable_training_seed: using seed: 0040
510209.549: fam15_receiver_enable_training_seed: using seed: 0040
510309.549: fam15_receiver_enable_training_seed: using seed: 0040
510409.549: fam15_receiver_enable_training_seed: using seed: 0040
510509.549: fam15_receiver_enable_training_seed: using seed: 0040
510609.550: fam15_receiver_enable_training_seed: using seed: 0040
510709.550: fam15_receiver_enable_training_seed: using seed: 0040
510809.550: TrainRcvrEn: Status 2005
510909.550: TrainRcvrEn: ErrStatus 0
511009.550: TrainRcvrEn: ErrCode 0
511109.550: TrainRcvrEn: Done
511209.550:
511309.550: fam15_receiver_enable_training_seed: using seed: 0054
511409.550: fam15_receiver_enable_training_seed: using seed: 0054
511509.550: fam15_receiver_enable_training_seed: using seed: 0054
511609.550: fam15_receiver_enable_training_seed: using seed: 0054
511709.550: fam15_receiver_enable_training_seed: using seed: 0054
511809.550: fam15_receiver_enable_training_seed: using seed: 0054
511909.551: fam15_receiver_enable_training_seed: using seed: 0054
512009.551: fam15_receiver_enable_training_seed: using seed: 0054
512109.551: fam15_receiver_enable_training_seed: using seed: 004d
512209.551: fam15_receiver_enable_training_seed: using seed: 004d
512309.551: fam15_receiver_enable_training_seed: using seed: 004d
512409.551: fam15_receiver_enable_training_seed: using seed: 004d
512509.551: fam15_receiver_enable_training_seed: using seed: 004d
512609.551: fam15_receiver_enable_training_seed: using seed: 004d
512709.551: fam15_receiver_enable_training_seed: using seed: 004d
512809.551: fam15_receiver_enable_training_seed: using seed: 004d
512909.552: TrainRcvrEn: Status 2005
513009.552: TrainRcvrEn: ErrStatus 0
513109.552: TrainRcvrEn: ErrCode 0
513209.552: TrainRcvrEn: Done
513309.552:
513409.552: fam15_receiver_enable_training_seed: using seed: 0045
513509.552: fam15_receiver_enable_training_seed: using seed: 0045
513609.552: fam15_receiver_enable_training_seed: using seed: 0045
513709.552: fam15_receiver_enable_training_seed: using seed: 0045
513809.552: fam15_receiver_enable_training_seed: using seed: 0045
513909.552: fam15_receiver_enable_training_seed: using seed: 0045
514009.552: fam15_receiver_enable_training_seed: using seed: 0045
514109.552: fam15_receiver_enable_training_seed: using seed: 0045
514209.552: fam15_receiver_enable_training_seed: using seed: 0040
514309.553: fam15_receiver_enable_training_seed: using seed: 0040
514409.553: fam15_receiver_enable_training_seed: using seed: 0040
514509.553: fam15_receiver_enable_training_seed: using seed: 0040
514609.553: fam15_receiver_enable_training_seed: using seed: 0040
514709.553: fam15_receiver_enable_training_seed: using seed: 0040
514809.553: fam15_receiver_enable_training_seed: using seed: 0040
514909.553: fam15_receiver_enable_training_seed: using seed: 0040
515009.553: TrainRcvrEn: Status 2005
515109.553: TrainRcvrEn: ErrStatus 0
515209.553: TrainRcvrEn: ErrCode 0
515309.553: TrainRcvrEn: Done
515409.553:
515509.553: activate_spd_rom() for node 00
515609.553: enable_spd_node0()
515709.554: SetTargetFreq: Start
515809.554: SetTargetFreq: Node 0: New frequency code: 0006
515909.554: ChangeMemClk: Start
516009.554: set_2t_configuration: Start
516109.554: set_2t_configuration: Done
516209.554: mct_BeforePlatformSpec: Start
516309.554: mct_BeforePlatformSpec: Done
516409.554: mct_PlatformSpec: Start
516509.554: Programmed DCT 0 timing/termination pattern 00000000 20222222
516609.554: mct_PlatformSpec: Done
516709.554: set_2t_configuration: Start
516809.554: set_2t_configuration: Done
516909.555: mct_BeforePlatformSpec: Start
517009.555: mct_BeforePlatformSpec: Done
517109.555: mct_PlatformSpec: Start
517209.555: Programmed DCT 1 timing/termination pattern 00000000 20222222
517309.555: mct_PlatformSpec: Done
517409.555: ChangeMemClk: Done
517509.555: phyAssistedMemFnceTraining: Start
517609.555: phyAssistedMemFnceTraining: training node 0 DCT 0
517709.555: phyAssistedMemFnceTraining: done training node 0 DCT 0
517809.555: phyAssistedMemFnceTraining: training node 0 DCT 1
517909.555: phyAssistedMemFnceTraining: done training node 0 DCT 1
518009.555: phyAssistedMemFnceTraining: Done
518109.555: InitPhyCompensation: DCT 0: Start
518209.555: Waiting for predriver calibration to be applied...done!
518309.555: InitPhyCompensation: DCT 0: Done
518409.555: phyAssistedMemFnceTraining: Start
518509.555: phyAssistedMemFnceTraining: training node 0 DCT 0
518609.555: phyAssistedMemFnceTraining: done training node 0 DCT 0
518709.555: phyAssistedMemFnceTraining: training node 0 DCT 1
518809.556: phyAssistedMemFnceTraining: done training node 0 DCT 1
518909.556: phyAssistedMemFnceTraining: Done
519009.556: InitPhyCompensation: DCT 1: Start
519109.556: Waiting for predriver calibration to be applied...done!
519209.556: InitPhyCompensation: DCT 1: Done
519309.556: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
519409.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
519509.556: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
519609.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
519709.556: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
519809.556: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
519909.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
520009.556: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
520109.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
520209.556: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
520309.556: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
520409.556: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
520509.556: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
520609.557: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
520709.557: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
520809.557: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
520909.557: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
521009.557: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
521109.557: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
521209.557: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
521309.557: SetTargetFreq: Done
521409.557: SPD2ndTiming: Start
521509.557: SPD2ndTiming: Done
521609.557: mct_BeforeDramInit_Prod_D: Start
521709.557: mct_ProgramODT_D: Start
521809.557: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
521909.557: mct_ProgramODT_D: Done
522009.557: mct_BeforeDramInit_Prod_D: Done
522109.557: mct_DramInit_Sw_D: Start
522209.557: DIMM 0 RttWr: 2
522309.558: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
522409.558: mct_SendMrsCmd: Start
522509.558: mct_SendMrsCmd: Done
522609.558: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
522709.558: mct_SendMrsCmd: Start
522809.558: mct_SendMrsCmd: Done
522909.558: DIMM 0 RttNom: 3
523009.558: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
523109.558: mct_SendMrsCmd: Start
523209.558: mct_SendMrsCmd: Done
523309.558: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
523409.558: mct_SendMrsCmd: Start
523509.558: mct_SendMrsCmd: Done
523609.558: DIMM 0 RttWr: 2
523709.558: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
523809.558: mct_SendMrsCmd: Start
523909.558: mct_SendMrsCmd: Done
524009.558: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
524109.558: mct_SendMrsCmd: Start
524209.558: mct_SendMrsCmd: Done
524309.558: DIMM 0 RttNom: 3
524409.558: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
524509.558: mct_SendMrsCmd: Start
524609.558: mct_SendMrsCmd: Done
524709.558: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
524809.558: mct_SendMrsCmd: Start
524909.558: mct_SendMrsCmd: Done
525009.558: DIMM 1 RttWr: 2
525109.558: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
525209.558: mct_SendMrsCmd: Start
525309.558: mct_SendMrsCmd: Done
525409.558: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
525509.558: mct_SendMrsCmd: Start
525609.558: mct_SendMrsCmd: Done
525709.558: DIMM 1 RttNom: 3
525809.558: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
525909.558: mct_SendMrsCmd: Start
526009.558: mct_SendMrsCmd: Done
526109.558: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
526209.558: mct_SendMrsCmd: Start
526309.558: mct_SendMrsCmd: Done
526409.558: DIMM 1 RttWr: 2
526509.558: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
526609.558: mct_SendMrsCmd: Start
526709.558: mct_SendMrsCmd: Done
526809.558: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
526909.558: mct_SendMrsCmd: Start
527009.558: mct_SendMrsCmd: Done
527109.558: DIMM 1 RttNom: 3
527209.558: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
527309.558: mct_SendMrsCmd: Start
527409.558: mct_SendMrsCmd: Done
527509.558: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
527609.558: mct_SendMrsCmd: Start
527709.558: mct_SendMrsCmd: Done
527809.558: mct_DramInit_Sw_D: Done
527909.559: AgesaHwWlPhase1: training nibble 0
528009.559: DIMM 0 RttNom: 3
528109.559: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
528209.559: DIMM 0 RttWr: 2
528309.559: DIMM 0 RttWr: 2
528409.559: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
528509.559: DIMM 0 RttWr: 2
528609.559: DIMM 0 RttNom: 3
528709.559: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
528809.559: DIMM 0 RttNom: 3
528909.559: DIMM 0 RttWr: 2
529009.559: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
529109.559: DIMM 0 RttWr: 2
529209.559: DIMM 1 RttNom: 3
529309.559: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
529409.559: DIMM 0 RttNom: 3
529509.559: DIMM 1 RttWr: 2
529609.559: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
529709.559: DIMM 0 RttWr: 2
529809.559: DIMM 1 RttNom: 3
529909.559: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
530009.559: DIMM 0 RttNom: 3
530109.559: DIMM 1 RttWr: 2
530209.559: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
530309.559: DIMM 0 RttWr: 2
530409.559: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
530509.559: <09>Lane 00 scaled delay: 0047
530609.559: <09>Lane 00 new seed: 0047
530709.559: <09>Lane 01 scaled delay: 0047
530809.559: <09>Lane 01 new seed: 0047
530909.559: <09>Lane 02 scaled delay: 0047
531009.559: <09>Lane 02 new seed: 0047
531109.559: <09>Lane 03 scaled delay: 0047
531209.560: <09>Lane 03 new seed: 0047
531309.560: <09>Lane 04 scaled delay: 0047
531409.560: <09>Lane 04 new seed: 0047
531509.560: <09>Lane 05 scaled delay: 0047
531609.560: <09>Lane 05 new seed: 0047
531709.560: <09>Lane 06 scaled delay: 0047
531809.560: <09>Lane 06 new seed: 0047
531909.560: <09>Lane 07 scaled delay: 0047
532009.560: <09>Lane 07 new seed: 0047
532109.560: <09>Lane 08 scaled delay: 0047
532209.560: <09>Lane 08 new seed: 0047
532309.560: <09>Lane 00 nibble 0 raw readback: 0050
532409.560: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
532509.560: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
532609.560: <09>Lane 01 nibble 0 raw readback: 004a
532709.560: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
532809.560: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
532909.560: <09>Lane 02 nibble 0 raw readback: 0047
533009.560: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
533109.560: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
533209.560: <09>Lane 03 nibble 0 raw readback: 0044
533309.560: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
533409.560: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
533509.560: <09>Lane 04 nibble 0 raw readback: 003a
533609.560: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
533709.560: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
533809.560: <09>Lane 05 nibble 0 raw readback: 003e
533909.560: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
534009.560: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
534109.560: <09>Lane 06 nibble 0 raw readback: 0041
534209.560: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
534309.560: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
534409.560: <09>Lane 07 nibble 0 raw readback: 0042
534509.560: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
534609.560: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
534709.560: <09>Lane 08 nibble 0 raw readback: 003c
534809.560: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
534909.560: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
535009.560: AgesaHwWlPhase1: training nibble 1
535109.560: DIMM 0 RttNom: 3
535209.560: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
535309.560: DIMM 0 RttWr: 2
535409.560: DIMM 0 RttWr: 2
535509.560: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
535609.560: DIMM 0 RttWr: 2
535709.560: DIMM 0 RttNom: 3
535809.560: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
535909.560: DIMM 0 RttNom: 3
536009.560: DIMM 0 RttWr: 2
536109.560: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
536209.560: DIMM 0 RttWr: 2
536309.560: DIMM 1 RttNom: 3
536409.560: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
536509.560: DIMM 0 RttNom: 3
536609.560: DIMM 1 RttWr: 2
536709.560: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
536809.560: DIMM 0 RttWr: 2
536909.560: DIMM 1 RttNom: 3
537009.560: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
537109.560: DIMM 0 RttNom: 3
537209.560: DIMM 1 RttWr: 2
537309.561: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
537409.561: DIMM 0 RttWr: 2
537509.561: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
537609.561: <09>Lane 00 new seed: 0047
537709.561: <09>Lane 01 new seed: 0047
537809.561: <09>Lane 02 new seed: 0047
537909.561: <09>Lane 03 new seed: 0047
538009.561: <09>Lane 04 new seed: 0047
538109.561: <09>Lane 05 new seed: 0047
538209.561: <09>Lane 06 new seed: 0047
538309.561: <09>Lane 07 new seed: 0047
538409.561: <09>Lane 08 new seed: 0047
538509.561: <09>Lane 00 nibble 1 raw readback: 004f
538609.561: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
538709.561: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
538809.561: <09>Lane 01 nibble 1 raw readback: 004a
538909.561: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
539009.561: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
539109.561: <09>Lane 02 nibble 1 raw readback: 0048
539209.561: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0048
539309.561: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
539409.561: <09>Lane 03 nibble 1 raw readback: 0045
539509.561: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
539609.561: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
539709.561: <09>Lane 04 nibble 1 raw readback: 003a
539809.561: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
539909.561: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
540009.561: <09>Lane 05 nibble 1 raw readback: 003e
540109.561: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
540209.561: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
540309.561: <09>Lane 06 nibble 1 raw readback: 0041
540409.561: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
540509.561: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
540609.561: <09>Lane 07 nibble 1 raw readback: 0042
540709.561: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
540809.561: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
540909.561: <09>Lane 08 nibble 1 raw readback: 003c
541009.561: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
541109.561: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
541209.561: <09>original critical gross delay: 0
541309.561: <09>new critical gross delay: 0
541409.561: DIMM 0 RttNom: 3
541509.561: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
541609.561: DIMM 0 RttNom: 3
541709.561: DIMM 0 RttWr: 2
541809.561: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
541909.561: DIMM 0 RttWr: 2
542009.561: DIMM 0 RttNom: 3
542109.561: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
542209.561: DIMM 0 RttNom: 3
542309.561: DIMM 0 RttWr: 2
542409.561: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
542509.561: DIMM 0 RttWr: 2
542609.561: DIMM 1 RttNom: 3
542709.561: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
542809.561: DIMM 0 RttNom: 3
542909.561: DIMM 1 RttWr: 2
543009.561: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
543109.561: DIMM 0 RttWr: 2
543209.561: DIMM 1 RttNom: 3
543309.562: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
543409.562: DIMM 0 RttNom: 3
543509.562: DIMM 1 RttWr: 2
543609.562: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
543709.562: DIMM 0 RttWr: 2
543809.562: AgesaHwWlPhase1: training nibble 0
543909.562: DIMM 1 RttNom: 3
544009.562: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
544109.562: DIMM 1 RttWr: 2
544209.562: DIMM 1 RttWr: 2
544309.562: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
544409.562: DIMM 1 RttWr: 2
544509.562: DIMM 1 RttNom: 3
544609.562: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
544709.562: DIMM 1 RttNom: 3
544809.562: DIMM 1 RttWr: 2
544909.562: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
545009.562: DIMM 1 RttWr: 2
545109.562: DIMM 0 RttNom: 3
545209.562: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
545309.562: DIMM 1 RttNom: 3
545409.562: DIMM 0 RttWr: 2
545509.562: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
545609.562: DIMM 1 RttWr: 2
545709.562: DIMM 0 RttNom: 3
545809.562: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
545909.562: DIMM 1 RttNom: 3
546009.562: DIMM 0 RttWr: 2
546109.562: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
546209.562: DIMM 1 RttWr: 2
546309.562: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
546409.562: <09>Lane 00 scaled delay: 0047
546509.562: <09>Lane 00 new seed: 0047
546609.562: <09>Lane 01 scaled delay: 0047
546709.562: <09>Lane 01 new seed: 0047
546809.562: <09>Lane 02 scaled delay: 0047
546909.562: <09>Lane 02 new seed: 0047
547009.562: <09>Lane 03 scaled delay: 0047
547109.562: <09>Lane 03 new seed: 0047
547209.562: <09>Lane 04 scaled delay: 0047
547309.562: <09>Lane 04 new seed: 0047
547409.562: <09>Lane 05 scaled delay: 0047
547509.562: <09>Lane 05 new seed: 0047
547609.562: <09>Lane 06 scaled delay: 0047
547709.562: <09>Lane 06 new seed: 0047
547809.562: <09>Lane 07 scaled delay: 0047
547909.562: <09>Lane 07 new seed: 0047
548009.562: <09>Lane 08 scaled delay: 0047
548109.562: <09>Lane 08 new seed: 0047
548209.562: <09>Lane 00 nibble 0 raw readback: 0046
548309.562: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
548409.562: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
548509.562: <09>Lane 01 nibble 0 raw readback: 003f
548609.562: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
548709.562: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
548809.562: <09>Lane 02 nibble 0 raw readback: 003e
548909.562: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
549009.562: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
549109.562: <09>Lane 03 nibble 0 raw readback: 003b
549209.562: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
549309.562: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
549409.562: <09>Lane 04 nibble 0 raw readback: 0030
549509.562: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
549609.562: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
549709.562: <09>Lane 05 nibble 0 raw readback: 0035
549809.562: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
549909.562: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
550009.562: <09>Lane 06 nibble 0 raw readback: 0037
550109.562: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
550209.562: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
550309.563: <09>Lane 07 nibble 0 raw readback: 003a
550409.563: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
550509.563: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
550609.563: <09>Lane 08 nibble 0 raw readback: 0033
550709.563: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
550809.563: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
550909.563: AgesaHwWlPhase1: training nibble 1
551009.563: DIMM 1 RttNom: 3
551109.563: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
551209.563: DIMM 1 RttWr: 2
551309.563: DIMM 1 RttWr: 2
551409.563: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
551509.563: DIMM 1 RttWr: 2
551609.563: DIMM 1 RttNom: 3
551709.563: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
551809.563: DIMM 1 RttNom: 3
551909.563: DIMM 1 RttWr: 2
552009.563: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
552109.563: DIMM 1 RttWr: 2
552209.563: DIMM 0 RttNom: 3
552309.563: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
552409.563: DIMM 1 RttNom: 3
552509.563: DIMM 0 RttWr: 2
552609.563: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
552709.563: DIMM 1 RttWr: 2
552809.563: DIMM 0 RttNom: 3
552909.563: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
553009.563: DIMM 1 RttNom: 3
553109.563: DIMM 0 RttWr: 2
553209.563: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
553309.563: DIMM 1 RttWr: 2
553409.563: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
553509.563: <09>Lane 00 new seed: 0047
553609.563: <09>Lane 01 new seed: 0047
553709.563: <09>Lane 02 new seed: 0047
553809.563: <09>Lane 03 new seed: 0047
553909.563: <09>Lane 04 new seed: 0047
554009.563: <09>Lane 05 new seed: 0047
554109.563: <09>Lane 06 new seed: 0047
554209.563: <09>Lane 07 new seed: 0047
554309.563: <09>Lane 08 new seed: 0047
554409.563: <09>Lane 00 nibble 1 raw readback: 0046
554509.563: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
554609.563: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
554709.563: <09>Lane 01 nibble 1 raw readback: 0040
554809.563: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
554909.563: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
555009.563: <09>Lane 02 nibble 1 raw readback: 003f
555109.563: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
555209.563: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
555309.563: <09>Lane 03 nibble 1 raw readback: 003b
555409.563: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
555509.563: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
555609.563: <09>Lane 04 nibble 1 raw readback: 0030
555709.563: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
555809.563: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
555909.563: <09>Lane 05 nibble 1 raw readback: 0035
556009.563: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
556109.563: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
556209.563: <09>Lane 06 nibble 1 raw readback: 0037
556309.563: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
556409.563: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
556509.563: <09>Lane 07 nibble 1 raw readback: 003a
556609.563: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
556709.563: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
556809.563: <09>Lane 08 nibble 1 raw readback: 0032
556909.563: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
557009.563: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
557109.563: <09>original critical gross delay: 0
557209.563: <09>new critical gross delay: 0
557309.563: DIMM 1 RttNom: 3
557409.563: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
557509.564: DIMM 1 RttNom: 3
557609.564: DIMM 1 RttWr: 2
557709.564: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
557809.564: DIMM 1 RttWr: 2
557909.564: DIMM 1 RttNom: 3
558009.564: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
558109.564: DIMM 1 RttNom: 3
558209.564: DIMM 1 RttWr: 2
558309.564: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
558409.564: DIMM 1 RttWr: 2
558509.564: DIMM 0 RttNom: 3
558609.564: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
558709.564: DIMM 1 RttNom: 3
558809.564: DIMM 0 RttWr: 2
558909.564: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
559009.564: DIMM 1 RttWr: 2
559109.564: DIMM 0 RttNom: 3
559209.564: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
559309.564: DIMM 1 RttNom: 3
559409.564: DIMM 0 RttWr: 2
559509.564: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
559609.564: DIMM 1 RttWr: 2
559709.564: SPD2ndTiming: Start
559809.564: SPD2ndTiming: Done
559909.564: mct_BeforeDramInit_Prod_D: Start
560009.564: mct_ProgramODT_D: Start
560109.564: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
560209.564: mct_ProgramODT_D: Done
560309.565: mct_BeforeDramInit_Prod_D: Done
560409.565: mct_DramInit_Sw_D: Start
560509.565: DIMM 0 RttWr: 2
560609.565: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
560709.565: mct_SendMrsCmd: Start
560809.565: mct_SendMrsCmd: Done
560909.565: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
561009.565: mct_SendMrsCmd: Start
561109.565: mct_SendMrsCmd: Done
561209.565: DIMM 0 RttNom: 3
561309.565: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
561409.565: mct_SendMrsCmd: Start
561509.565: mct_SendMrsCmd: Done
561609.565: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
561709.565: mct_SendMrsCmd: Start
561809.565: mct_SendMrsCmd: Done
561909.565: DIMM 0 RttWr: 2
562009.565: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
562109.565: mct_SendMrsCmd: Start
562209.565: mct_SendMrsCmd: Done
562309.565: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
562409.565: mct_SendMrsCmd: Start
562509.565: mct_SendMrsCmd: Done
562609.565: DIMM 0 RttNom: 3
562709.565: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
562809.565: mct_SendMrsCmd: Start
562909.565: mct_SendMrsCmd: Done
563009.565: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
563109.565: mct_SendMrsCmd: Start
563209.565: mct_SendMrsCmd: Done
563309.565: DIMM 1 RttWr: 2
563409.565: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
563509.565: mct_SendMrsCmd: Start
563609.565: mct_SendMrsCmd: Done
563709.565: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
563809.565: mct_SendMrsCmd: Start
563909.565: mct_SendMrsCmd: Done
564009.565: DIMM 1 RttNom: 3
564109.565: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
564209.565: mct_SendMrsCmd: Start
564309.565: mct_SendMrsCmd: Done
564409.565: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
564509.565: mct_SendMrsCmd: Start
564609.565: mct_SendMrsCmd: Done
564709.565: DIMM 1 RttWr: 2
564809.565: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
564909.565: mct_SendMrsCmd: Start
565009.565: mct_SendMrsCmd: Done
565109.565: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
565209.565: mct_SendMrsCmd: Start
565309.565: mct_SendMrsCmd: Done
565409.565: DIMM 1 RttNom: 3
565509.565: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
565609.565: mct_SendMrsCmd: Start
565709.565: mct_SendMrsCmd: Done
565809.565: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
565909.565: mct_SendMrsCmd: Start
566009.565: mct_SendMrsCmd: Done
566109.565: mct_DramInit_Sw_D: Done
566209.565: AgesaHwWlPhase1: training nibble 0
566309.565: DIMM 0 RttNom: 3
566409.565: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
566509.565: DIMM 0 RttWr: 2
566609.565: DIMM 0 RttWr: 2
566709.565: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
566809.565: DIMM 0 RttWr: 2
566909.565: DIMM 0 RttNom: 3
567009.565: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
567109.565: DIMM 0 RttNom: 3
567209.566: DIMM 0 RttWr: 2
567309.566: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
567409.566: DIMM 0 RttWr: 2
567509.566: DIMM 1 RttNom: 3
567609.566: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
567709.566: DIMM 0 RttNom: 3
567809.566: DIMM 1 RttWr: 2
567909.566: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
568009.566: DIMM 0 RttWr: 2
568109.566: DIMM 1 RttNom: 3
568209.566: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
568309.566: DIMM 0 RttNom: 3
568409.566: DIMM 1 RttWr: 2
568509.566: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
568609.566: DIMM 0 RttWr: 2
568709.566: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
568809.566: <09>Lane 00 scaled delay: 0047
568909.566: <09>Lane 00 new seed: 0047
569009.566: <09>Lane 01 scaled delay: 0047
569109.566: <09>Lane 01 new seed: 0047
569209.566: <09>Lane 02 scaled delay: 0047
569309.566: <09>Lane 02 new seed: 0047
569409.566: <09>Lane 03 scaled delay: 0047
569509.566: <09>Lane 03 new seed: 0047
569609.566: <09>Lane 04 scaled delay: 0047
569709.566: <09>Lane 04 new seed: 0047
569809.566: <09>Lane 05 scaled delay: 0047
569909.566: <09>Lane 05 new seed: 0047
570009.566: <09>Lane 06 scaled delay: 0047
570109.566: <09>Lane 06 new seed: 0047
570209.566: <09>Lane 07 scaled delay: 0047
570309.566: <09>Lane 07 new seed: 0047
570409.566: <09>Lane 08 scaled delay: 0047
570509.566: <09>Lane 08 new seed: 0047
570609.566: <09>Lane 00 nibble 0 raw readback: 004c
570709.566: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
570809.566: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
570909.566: <09>Lane 01 nibble 0 raw readback: 0049
571009.566: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
571109.566: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
571209.566: <09>Lane 02 nibble 0 raw readback: 0045
571309.566: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
571409.566: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
571509.566: <09>Lane 03 nibble 0 raw readback: 0042
571609.566: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
571709.566: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
571809.566: <09>Lane 04 nibble 0 raw readback: 0039
571909.566: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
572009.566: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
572109.566: <09>Lane 05 nibble 0 raw readback: 003b
572209.566: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
572309.566: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
572409.566: <09>Lane 06 nibble 0 raw readback: 003d
572509.566: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
572609.566: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
572709.566: <09>Lane 07 nibble 0 raw readback: 003f
572809.566: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
572909.566: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
573009.566: <09>Lane 08 nibble 0 raw readback: 003a
573109.566: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
573209.566: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
573309.566: AgesaHwWlPhase1: training nibble 1
573409.566: DIMM 0 RttNom: 3
573509.566: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
573609.567: DIMM 0 RttWr: 2
573709.567: DIMM 0 RttWr: 2
573809.567: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
573909.567: DIMM 0 RttWr: 2
574009.567: DIMM 0 RttNom: 3
574109.567: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
574209.567: DIMM 0 RttNom: 3
574309.567: DIMM 0 RttWr: 2
574409.567: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
574509.567: DIMM 0 RttWr: 2
574609.567: DIMM 1 RttNom: 3
574709.567: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
574809.567: DIMM 0 RttNom: 3
574909.567: DIMM 1 RttWr: 2
575009.567: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
575109.567: DIMM 0 RttWr: 2
575209.567: DIMM 1 RttNom: 3
575309.567: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
575409.567: DIMM 0 RttNom: 3
575509.567: DIMM 1 RttWr: 2
575609.567: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
575709.567: DIMM 0 RttWr: 2
575809.567: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
575909.567: <09>Lane 00 new seed: 0047
576009.567: <09>Lane 01 new seed: 0047
576109.567: <09>Lane 02 new seed: 0047
576209.567: <09>Lane 03 new seed: 0047
576309.567: <09>Lane 04 new seed: 0047
576409.567: <09>Lane 05 new seed: 0047
576509.567: <09>Lane 06 new seed: 0047
576609.567: <09>Lane 07 new seed: 0047
576709.567: <09>Lane 08 new seed: 0047
576809.567: <09>Lane 00 nibble 1 raw readback: 004c
576909.567: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004c
577009.567: <09>Lane 00 nibble 1 adjusted value (post nibble): 0049
577109.567: <09>Lane 01 nibble 1 raw readback: 0048
577209.567: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0048
577309.567: <09>Lane 01 nibble 1 adjusted value (post nibble): 0047
577409.567: <09>Lane 02 nibble 1 raw readback: 0046
577509.567: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
577609.567: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
577709.567: <09>Lane 03 nibble 1 raw readback: 0043
577809.567: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
577909.567: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
578009.567: <09>Lane 04 nibble 1 raw readback: 0038
578109.567: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
578209.567: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
578309.567: <09>Lane 05 nibble 1 raw readback: 003b
578409.567: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
578509.567: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
578609.567: <09>Lane 06 nibble 1 raw readback: 003e
578709.567: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
578809.567: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
578909.567: <09>Lane 07 nibble 1 raw readback: 0041
579009.567: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
579109.567: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
579209.567: <09>Lane 08 nibble 1 raw readback: 003a
579309.567: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
579409.567: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
579509.567: <09>original critical gross delay: 0
579609.567: <09>new critical gross delay: 0
579709.567: DIMM 0 RttNom: 3
579809.567: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
579909.567: DIMM 0 RttNom: 3
580009.567: DIMM 0 RttWr: 2
580109.568: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
580209.568: DIMM 0 RttWr: 2
580309.568: DIMM 0 RttNom: 3
580409.568: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
580509.568: DIMM 0 RttNom: 3
580609.568: DIMM 0 RttWr: 2
580709.568: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
580809.568: DIMM 0 RttWr: 2
580909.568: DIMM 1 RttNom: 3
581009.568: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
581109.568: DIMM 0 RttNom: 3
581209.568: DIMM 1 RttWr: 2
581309.568: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
581409.568: DIMM 0 RttWr: 2
581509.568: DIMM 1 RttNom: 3
581609.568: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
581709.568: DIMM 0 RttNom: 3
581809.568: DIMM 1 RttWr: 2
581909.568: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
582009.568: DIMM 0 RttWr: 2
582109.568: AgesaHwWlPhase1: training nibble 0
582209.568: DIMM 1 RttNom: 3
582309.568: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
582409.568: DIMM 1 RttWr: 2
582509.568: DIMM 1 RttWr: 2
582609.568: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
582709.568: DIMM 1 RttWr: 2
582809.568: DIMM 1 RttNom: 3
582909.568: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
583009.568: DIMM 1 RttNom: 3
583109.568: DIMM 1 RttWr: 2
583209.568: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
583309.568: DIMM 1 RttWr: 2
583409.568: DIMM 0 RttNom: 3
583509.568: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
583609.568: DIMM 1 RttNom: 3
583709.568: DIMM 0 RttWr: 2
583809.568: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
583909.568: DIMM 1 RttWr: 2
584009.568: DIMM 0 RttNom: 3
584109.568: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
584209.568: DIMM 1 RttNom: 3
584309.568: DIMM 0 RttWr: 2
584409.568: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
584509.568: DIMM 1 RttWr: 2
584609.568: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
584709.568: <09>Lane 00 scaled delay: 0047
584809.568: <09>Lane 00 new seed: 0047
584909.568: <09>Lane 01 scaled delay: 0047
585009.568: <09>Lane 01 new seed: 0047
585109.568: <09>Lane 02 scaled delay: 0047
585209.568: <09>Lane 02 new seed: 0047
585309.568: <09>Lane 03 scaled delay: 0047
585409.568: <09>Lane 03 new seed: 0047
585509.568: <09>Lane 04 scaled delay: 0047
585609.568: <09>Lane 04 new seed: 0047
585709.568: <09>Lane 05 scaled delay: 0047
585809.568: <09>Lane 05 new seed: 0047
585909.568: <09>Lane 06 scaled delay: 0047
586009.568: <09>Lane 06 new seed: 0047
586109.568: <09>Lane 07 scaled delay: 0047
586209.568: <09>Lane 07 new seed: 0047
586309.568: <09>Lane 08 scaled delay: 0047
586409.569: <09>Lane 08 new seed: 0047
586509.569: <09>Lane 00 nibble 0 raw readback: 0045
586609.569: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
586709.569: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
586809.569: <09>Lane 01 nibble 0 raw readback: 0042
586909.569: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
587009.569: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
587109.569: <09>Lane 02 nibble 0 raw readback: 003e
587209.569: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
587309.569: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
587409.569: <09>Lane 03 nibble 0 raw readback: 003c
587509.569: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003c
587609.569: <09>Lane 03 nibble 0 adjusted value (post nibble): 003c
587709.569: <09>Lane 04 nibble 0 raw readback: 0031
587809.569: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0031
587909.569: <09>Lane 04 nibble 0 adjusted value (post nibble): 0031
588009.569: <09>Lane 05 nibble 0 raw readback: 0033
588109.569: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0033
588209.569: <09>Lane 05 nibble 0 adjusted value (post nibble): 0033
588309.569: <09>Lane 06 nibble 0 raw readback: 0037
588409.569: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
588509.569: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
588609.569: <09>Lane 07 nibble 0 raw readback: 003a
588709.569: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
588809.569: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
588909.569: <09>Lane 08 nibble 0 raw readback: 0033
589009.569: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
589109.569: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
589209.569: AgesaHwWlPhase1: training nibble 1
589309.569: DIMM 1 RttNom: 3
589409.569: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
589509.569: DIMM 1 RttWr: 2
589609.569: DIMM 1 RttWr: 2
589709.569: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
589809.569: DIMM 1 RttWr: 2
589909.569: DIMM 1 RttNom: 3
590009.569: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
590109.569: DIMM 1 RttNom: 3
590209.569: DIMM 1 RttWr: 2
590309.569: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
590409.569: DIMM 1 RttWr: 2
590509.569: DIMM 0 RttNom: 3
590609.569: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
590709.569: DIMM 1 RttNom: 3
590809.569: DIMM 0 RttWr: 2
590909.569: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
591009.569: DIMM 1 RttWr: 2
591109.569: DIMM 0 RttNom: 3
591209.569: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
591309.569: DIMM 1 RttNom: 3
591409.569: DIMM 0 RttWr: 2
591509.569: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
591609.569: DIMM 1 RttWr: 2
591709.569: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
591809.569: <09>Lane 00 new seed: 0047
591909.569: <09>Lane 01 new seed: 0047
592009.569: <09>Lane 02 new seed: 0047
592109.569: <09>Lane 03 new seed: 0047
592209.569: <09>Lane 04 new seed: 0047
592309.569: <09>Lane 05 new seed: 0047
592409.569: <09>Lane 06 new seed: 0047
592509.569: <09>Lane 07 new seed: 0047
592609.569: <09>Lane 08 new seed: 0047
592709.569: <09>Lane 00 nibble 1 raw readback: 0045
592809.569: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
592909.569: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
593009.569: <09>Lane 01 nibble 1 raw readback: 0042
593109.569: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
593209.569: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
593309.569: <09>Lane 02 nibble 1 raw readback: 003e
593409.569: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
593509.569: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
593609.569: <09>Lane 03 nibble 1 raw readback: 003d
593709.569: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003d
593809.569: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
593909.569: <09>Lane 04 nibble 1 raw readback: 0031
594009.569: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
594109.569: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
594209.569: <09>Lane 05 nibble 1 raw readback: 0035
594309.569: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
594409.569: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
594509.570: <09>Lane 06 nibble 1 raw readback: 0037
594609.570: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
594709.570: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
594809.570: <09>Lane 07 nibble 1 raw readback: 0039
594909.570: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
595009.570: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
595109.570: <09>Lane 08 nibble 1 raw readback: 0035
595209.570: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0035
595309.570: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
595409.570: <09>original critical gross delay: 0
595509.570: <09>new critical gross delay: 0
595609.570: DIMM 1 RttNom: 3
595709.570: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
595809.570: DIMM 1 RttNom: 3
595909.570: DIMM 1 RttWr: 2
596009.570: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
596109.570: DIMM 1 RttWr: 2
596209.570: DIMM 1 RttNom: 3
596309.570: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
596409.570: DIMM 1 RttNom: 3
596509.570: DIMM 1 RttWr: 2
596609.570: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
596709.570: DIMM 1 RttWr: 2
596809.570: DIMM 0 RttNom: 3
596909.570: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
597009.570: DIMM 1 RttNom: 3
597109.570: DIMM 0 RttWr: 2
597209.570: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
597309.570: DIMM 1 RttWr: 2
597409.570: DIMM 0 RttNom: 3
597509.570: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
597609.570: DIMM 1 RttNom: 3
597709.570: DIMM 0 RttWr: 2
597809.570: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
597909.570: DIMM 1 RttWr: 2
598009.570: SetTargetFreq: Start
598109.570: SetTargetFreq: Node 0: New frequency code: 000a
598209.570: ChangeMemClk: Start
598309.570: set_2t_configuration: Start
598409.570: set_2t_configuration: Done
598509.570: mct_BeforePlatformSpec: Start
598609.570: mct_BeforePlatformSpec: Done
598709.571: mct_PlatformSpec: Start
598809.571: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
598909.571: mct_PlatformSpec: Done
599009.571: set_2t_configuration: Start
599109.571: set_2t_configuration: Done
599209.571: mct_BeforePlatformSpec: Start
599309.571: mct_BeforePlatformSpec: Done
599409.571: mct_PlatformSpec: Start
599509.571: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
599609.571: mct_PlatformSpec: Done
599709.571: ChangeMemClk: Done
599809.571: phyAssistedMemFnceTraining: Start
599909.571: phyAssistedMemFnceTraining: training node 0 DCT 0
600009.571: phyAssistedMemFnceTraining: done training node 0 DCT 0
600109.571: phyAssistedMemFnceTraining: training node 0 DCT 1
600209.571: phyAssistedMemFnceTraining: done training node 0 DCT 1
600309.571: phyAssistedMemFnceTraining: Done
600409.571: InitPhyCompensation: DCT 0: Start
600509.571: Waiting for predriver calibration to be applied...done!
600609.571: InitPhyCompensation: DCT 0: Done
600709.571: phyAssistedMemFnceTraining: Start
600809.571: phyAssistedMemFnceTraining: training node 0 DCT 0
600909.571: phyAssistedMemFnceTraining: done training node 0 DCT 0
601009.571: phyAssistedMemFnceTraining: training node 0 DCT 1
601109.572: phyAssistedMemFnceTraining: done training node 0 DCT 1
601209.572: phyAssistedMemFnceTraining: Done
601309.572: InitPhyCompensation: DCT 1: Start
601409.572: Waiting for predriver calibration to be applied...done!
601509.572: InitPhyCompensation: DCT 1: Done
601609.572: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
601709.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
601809.572: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
601909.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
602009.572: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
602109.572: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
602209.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
602309.572: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
602409.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
602509.572: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
602609.572: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
602709.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
602809.572: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
602909.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
603009.572: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
603109.572: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
603209.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
603309.572: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
603409.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
603509.572: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
603609.572: SetTargetFreq: Done
603709.572: SPD2ndTiming: Start
603809.573: SPD2ndTiming: Done
603909.573: mct_BeforeDramInit_Prod_D: Start
604009.573: mct_ProgramODT_D: Start
604109.573: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
604209.573: mct_ProgramODT_D: Done
604309.573: mct_BeforeDramInit_Prod_D: Done
604409.573: mct_DramInit_Sw_D: Start
604509.573: DIMM 0 RttWr: 1
604609.573: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
604709.573: mct_SendMrsCmd: Start
604809.573: mct_SendMrsCmd: Done
604909.573: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
605009.573: mct_SendMrsCmd: Start
605109.573: mct_SendMrsCmd: Done
605209.573: DIMM 0 RttNom: 3
605309.573: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
605409.573: mct_SendMrsCmd: Start
605509.573: mct_SendMrsCmd: Done
605609.573: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
605709.573: mct_SendMrsCmd: Start
605809.573: mct_SendMrsCmd: Done
605909.573: DIMM 0 RttWr: 1
606009.573: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
606109.573: mct_SendMrsCmd: Start
606209.573: mct_SendMrsCmd: Done
606309.573: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
606409.573: mct_SendMrsCmd: Start
606509.573: mct_SendMrsCmd: Done
606609.573: DIMM 0 RttNom: 3
606709.573: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
606809.573: mct_SendMrsCmd: Start
606909.573: mct_SendMrsCmd: Done
607009.573: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
607109.573: mct_SendMrsCmd: Start
607209.573: mct_SendMrsCmd: Done
607309.573: DIMM 1 RttWr: 1
607409.573: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
607509.573: mct_SendMrsCmd: Start
607609.573: mct_SendMrsCmd: Done
607709.573: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
607809.573: mct_SendMrsCmd: Start
607909.573: mct_SendMrsCmd: Done
608009.573: DIMM 1 RttNom: 3
608109.573: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
608209.573: mct_SendMrsCmd: Start
608309.573: mct_SendMrsCmd: Done
608409.573: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
608509.573: mct_SendMrsCmd: Start
608609.573: mct_SendMrsCmd: Done
608709.573: DIMM 1 RttWr: 1
608809.573: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
608909.573: mct_SendMrsCmd: Start
609009.573: mct_SendMrsCmd: Done
609109.573: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
609209.573: mct_SendMrsCmd: Start
609309.573: mct_SendMrsCmd: Done
609409.573: DIMM 1 RttNom: 3
609509.573: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
609609.573: mct_SendMrsCmd: Start
609709.574: mct_SendMrsCmd: Done
609809.574: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
609909.574: mct_SendMrsCmd: Start
610009.574: mct_SendMrsCmd: Done
610109.574: mct_DramInit_Sw_D: Done
610209.574: AgesaHwWlPhase1: training nibble 0
610309.574: DIMM 0 RttNom: 3
610409.574: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
610509.574: DIMM 0 RttWr: 1
610609.574: DIMM 0 RttWr: 1
610709.574: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
610809.574: DIMM 0 RttWr: 1
610909.574: DIMM 0 RttNom: 3
611009.574: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
611109.574: DIMM 0 RttNom: 3
611209.574: DIMM 0 RttWr: 1
611309.574: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
611409.574: DIMM 0 RttWr: 1
611509.574: DIMM 1 RttNom: 3
611609.574: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
611709.574: DIMM 0 RttNom: 3
611809.574: DIMM 1 RttWr: 1
611909.574: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
612009.574: DIMM 0 RttWr: 1
612109.574: DIMM 1 RttNom: 3
612209.574: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
612309.574: DIMM 0 RttNom: 3
612409.574: DIMM 1 RttWr: 1
612509.574: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
612609.574: DIMM 0 RttWr: 1
612709.574: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
612809.574: <09>Lane 00 scaled delay: 0059
612909.574: <09>Lane 00 new seed: 0059
613009.574: <09>Lane 01 scaled delay: 0055
613109.574: <09>Lane 01 new seed: 0055
613209.574: <09>Lane 02 scaled delay: 0053
613309.574: <09>Lane 02 new seed: 0053
613409.574: <09>Lane 03 scaled delay: 0052
613509.574: <09>Lane 03 new seed: 0052
613609.574: <09>Lane 04 scaled delay: 004a
613709.575: <09>Lane 04 new seed: 004a
613809.575: <09>Lane 05 scaled delay: 004d
613909.575: <09>Lane 05 new seed: 004d
614009.575: <09>Lane 06 scaled delay: 004f
614109.575: <09>Lane 06 new seed: 004f
614209.575: <09>Lane 07 scaled delay: 004f
614309.575: <09>Lane 07 new seed: 004f
614409.575: <09>Lane 08 scaled delay: 004b
614509.575: <09>Lane 08 new seed: 004b
614609.575: <09>Lane 00 nibble 0 raw readback: 0060
614709.575: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
614809.575: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
614909.575: <09>Lane 01 nibble 0 raw readback: 0058
615009.575: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
615109.575: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
615209.575: <09>Lane 02 nibble 0 raw readback: 0055
615309.575: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
615409.575: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
615509.575: <09>Lane 03 nibble 0 raw readback: 004f
615609.575: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
615709.575: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
615809.575: <09>Lane 04 nibble 0 raw readback: 0042
615909.575: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
616009.575: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
616109.575: <09>Lane 05 nibble 0 raw readback: 0048
616209.575: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
616309.575: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
616409.575: <09>Lane 06 nibble 0 raw readback: 004d
616509.575: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
616609.575: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
616709.575: <09>Lane 07 nibble 0 raw readback: 004f
616809.575: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004f
616909.575: <09>Lane 07 nibble 0 adjusted value (post nibble): 004f
617009.575: <09>Lane 08 nibble 0 raw readback: 0045
617109.575: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
617209.575: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
617309.575: AgesaHwWlPhase1: training nibble 1
617409.575: DIMM 0 RttNom: 3
617509.575: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
617609.575: DIMM 0 RttWr: 1
617709.575: DIMM 0 RttWr: 1
617809.575: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
617909.575: DIMM 0 RttWr: 1
618009.575: DIMM 0 RttNom: 3
618109.575: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
618209.575: DIMM 0 RttNom: 3
618309.575: DIMM 0 RttWr: 1
618409.575: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
618509.575: DIMM 0 RttWr: 1
618609.575: DIMM 1 RttNom: 3
618709.575: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
618809.575: DIMM 0 RttNom: 3
618909.575: DIMM 1 RttWr: 1
619009.575: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
619109.575: DIMM 0 RttWr: 1
619209.575: DIMM 1 RttNom: 3
619309.575: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
619409.575: DIMM 0 RttNom: 3
619509.575: DIMM 1 RttWr: 1
619609.575: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
619709.575: DIMM 0 RttWr: 1
619809.575: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
619909.575: <09>Lane 00 new seed: 0059
620009.575: <09>Lane 01 new seed: 0055
620109.575: <09>Lane 02 new seed: 0053
620209.575: <09>Lane 03 new seed: 0052
620309.576: <09>Lane 04 new seed: 004a
620409.576: <09>Lane 05 new seed: 004d
620509.576: <09>Lane 06 new seed: 004f
620609.576: <09>Lane 07 new seed: 004f
620709.576: <09>Lane 08 new seed: 004b
620809.576: <09>Lane 00 nibble 1 raw readback: 0060
620909.576: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
621009.576: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
621109.576: <09>Lane 01 nibble 1 raw readback: 0058
621209.576: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
621309.576: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
621409.576: <09>Lane 02 nibble 1 raw readback: 0056
621509.576: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
621609.576: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
621709.576: <09>Lane 03 nibble 1 raw readback: 0052
621809.576: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
621909.576: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
622009.576: <09>Lane 04 nibble 1 raw readback: 0042
622109.576: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
622209.576: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
622309.576: <09>Lane 05 nibble 1 raw readback: 0049
622409.576: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0049
622509.576: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
622609.576: <09>Lane 06 nibble 1 raw readback: 004d
622709.576: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
622809.576: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
622909.576: <09>Lane 07 nibble 1 raw readback: 0050
623009.576: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
623109.576: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
623209.576: <09>Lane 08 nibble 1 raw readback: 0046
623309.576: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0046
623409.576: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
623509.576: <09>original critical gross delay: 0
623609.576: <09>new critical gross delay: 0
623709.576: DIMM 0 RttNom: 3
623809.576: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
623909.576: DIMM 0 RttNom: 3
624009.576: DIMM 0 RttWr: 1
624109.576: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
624209.576: DIMM 0 RttWr: 1
624309.576: DIMM 0 RttNom: 3
624409.576: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
624509.576: DIMM 0 RttNom: 3
624609.576: DIMM 0 RttWr: 1
624709.576: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
624809.576: DIMM 0 RttWr: 1
624909.576: DIMM 1 RttNom: 3
625009.576: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
625109.576: DIMM 0 RttNom: 3
625209.576: DIMM 1 RttWr: 1
625309.576: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
625409.576: DIMM 0 RttWr: 1
625509.576: DIMM 1 RttNom: 3
625609.576: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
625709.576: DIMM 0 RttNom: 3
625809.576: DIMM 1 RttWr: 1
625909.576: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
626009.576: DIMM 0 RttWr: 1
626109.576: AgesaHwWlPhase1: training nibble 0
626209.576: DIMM 1 RttNom: 3
626309.576: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
626409.576: DIMM 1 RttWr: 1
626509.576: DIMM 1 RttWr: 1
626609.576: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
626709.576: DIMM 1 RttWr: 1
626809.577: DIMM 1 RttNom: 3
626909.577: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
627009.577: DIMM 1 RttNom: 3
627109.577: DIMM 1 RttWr: 1
627209.577: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
627309.577: DIMM 1 RttWr: 1
627409.577: DIMM 0 RttNom: 3
627509.577: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
627609.577: DIMM 1 RttNom: 3
627709.577: DIMM 0 RttWr: 1
627809.577: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
627909.577: DIMM 1 RttWr: 1
628009.577: DIMM 0 RttNom: 3
628109.577: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
628209.577: DIMM 1 RttNom: 3
628309.577: DIMM 0 RttWr: 1
628409.577: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
628509.577: DIMM 1 RttWr: 1
628609.577: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
628709.577: <09>Lane 00 scaled delay: 0052
628809.577: <09>Lane 00 new seed: 0052
628909.577: <09>Lane 01 scaled delay: 004e
629009.577: <09>Lane 01 new seed: 004e
629109.577: <09>Lane 02 scaled delay: 004e
629209.577: <09>Lane 02 new seed: 004e
629309.577: <09>Lane 03 scaled delay: 004b
629409.577: <09>Lane 03 new seed: 004b
629509.577: <09>Lane 04 scaled delay: 0043
629609.577: <09>Lane 04 new seed: 0043
629709.577: <09>Lane 05 scaled delay: 0047
629809.577: <09>Lane 05 new seed: 0047
629909.577: <09>Lane 06 scaled delay: 0049
630009.577: <09>Lane 06 new seed: 0049
630109.577: <09>Lane 07 scaled delay: 004a
630209.577: <09>Lane 07 new seed: 004a
630309.577: <09>Lane 08 scaled delay: 0045
630409.577: <09>Lane 08 new seed: 0045
630509.577: <09>Lane 00 nibble 0 raw readback: 0052
630609.577: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
630709.577: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
630809.577: <09>Lane 01 nibble 0 raw readback: 004b
630909.577: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
631009.577: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
631109.577: <09>Lane 02 nibble 0 raw readback: 0048
631209.577: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
631309.577: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
631409.577: <09>Lane 03 nibble 0 raw readback: 0044
631509.577: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
631609.577: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
631709.577: <09>Lane 04 nibble 0 raw readback: 0037
631809.577: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0037
631909.577: <09>Lane 04 nibble 0 adjusted value (post nibble): 0037
632009.577: <09>Lane 05 nibble 0 raw readback: 003d
632109.577: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
632209.577: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
632309.577: <09>Lane 06 nibble 0 raw readback: 003f
632409.577: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
632509.577: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
632609.577: <09>Lane 07 nibble 0 raw readback: 0044
632709.577: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
632809.577: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
632909.577: <09>Lane 08 nibble 0 raw readback: 0039
633009.577: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
633109.577: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
633209.577: AgesaHwWlPhase1: training nibble 1
633309.577: DIMM 1 RttNom: 3
633409.577: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
633509.577: DIMM 1 RttWr: 1
633609.577: DIMM 1 RttWr: 1
633709.577: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
633809.577: DIMM 1 RttWr: 1
633909.577: DIMM 1 RttNom: 3
634009.577: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
634109.577: DIMM 1 RttNom: 3
634209.578: DIMM 1 RttWr: 1
634309.577: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
634409.578: DIMM 1 RttWr: 1
634509.578: DIMM 0 RttNom: 3
634609.578: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
634709.578: DIMM 1 RttNom: 3
634809.578: DIMM 0 RttWr: 1
634909.578: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
635009.578: DIMM 1 RttWr: 1
635109.578: DIMM 0 RttNom: 3
635209.578: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
635309.578: DIMM 1 RttNom: 3
635409.578: DIMM 0 RttWr: 1
635509.578: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
635609.578: DIMM 1 RttWr: 1
635709.578: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
635809.578: <09>Lane 00 new seed: 0052
635909.578: <09>Lane 01 new seed: 004e
636009.578: <09>Lane 02 new seed: 004e
636109.578: <09>Lane 03 new seed: 004b
636209.578: <09>Lane 04 new seed: 0043
636309.578: <09>Lane 05 new seed: 0047
636409.578: <09>Lane 06 new seed: 0049
636509.578: <09>Lane 07 new seed: 004a
636609.578: <09>Lane 08 new seed: 0045
636709.578: <09>Lane 00 nibble 1 raw readback: 0053
636809.578: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
636909.578: <09>Lane 00 nibble 1 adjusted value (post nibble): 0052
637009.578: <09>Lane 01 nibble 1 raw readback: 004c
637109.578: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004c
637209.578: <09>Lane 01 nibble 1 adjusted value (post nibble): 004d
637309.578: <09>Lane 02 nibble 1 raw readback: 004a
637409.578: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
637509.578: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
637609.578: <09>Lane 03 nibble 1 raw readback: 0045
637709.578: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
637809.578: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
637909.578: <09>Lane 04 nibble 1 raw readback: 0036
638009.578: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
638109.578: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
638209.578: <09>Lane 05 nibble 1 raw readback: 003d
638309.578: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
638409.578: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
638509.578: <09>Lane 06 nibble 1 raw readback: 0040
638609.578: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
638709.578: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
638809.578: <09>Lane 07 nibble 1 raw readback: 0045
638909.578: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
639009.578: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
639109.578: <09>Lane 08 nibble 1 raw readback: 0038
639209.578: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
639309.578: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
639409.578: <09>original critical gross delay: 0
639509.578: <09>new critical gross delay: 0
639609.578: DIMM 1 RttNom: 3
639709.578: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
639809.578: DIMM 1 RttNom: 3
639909.578: DIMM 1 RttWr: 1
640009.578: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
640109.578: DIMM 1 RttWr: 1
640209.578: DIMM 1 RttNom: 3
640309.578: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
640409.578: DIMM 1 RttNom: 3
640509.578: DIMM 1 RttWr: 1
640609.578: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
640709.578: DIMM 1 RttWr: 1
640809.578: DIMM 0 RttNom: 3
640909.578: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
641009.578: DIMM 1 RttNom: 3
641109.579: DIMM 0 RttWr: 1
641209.578: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
641309.578: DIMM 1 RttWr: 1
641409.579: DIMM 0 RttNom: 3
641509.579: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
641609.579: DIMM 1 RttNom: 3
641709.579: DIMM 0 RttWr: 1
641809.579: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
641909.579: DIMM 1 RttWr: 1
642009.579: SPD2ndTiming: Start
642109.579: SPD2ndTiming: Done
642209.579: mct_BeforeDramInit_Prod_D: Start
642309.579: mct_ProgramODT_D: Start
642409.579: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
642509.579: mct_ProgramODT_D: Done
642609.579: mct_BeforeDramInit_Prod_D: Done
642709.579: mct_DramInit_Sw_D: Start
642809.579: DIMM 0 RttWr: 1
642909.579: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
643009.579: mct_SendMrsCmd: Start
643109.579: mct_SendMrsCmd: Done
643209.579: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
643309.579: mct_SendMrsCmd: Start
643409.579: mct_SendMrsCmd: Done
643509.579: DIMM 0 RttNom: 3
643609.579: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
643709.579: mct_SendMrsCmd: Start
643809.579: mct_SendMrsCmd: Done
643909.579: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
644009.579: mct_SendMrsCmd: Start
644109.579: mct_SendMrsCmd: Done
644209.579: DIMM 0 RttWr: 1
644309.579: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
644409.579: mct_SendMrsCmd: Start
644509.579: mct_SendMrsCmd: Done
644609.580: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
644709.579: mct_SendMrsCmd: Start
644809.579: mct_SendMrsCmd: Done
644909.580: DIMM 0 RttNom: 3
645009.580: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
645109.580: mct_SendMrsCmd: Start
645209.580: mct_SendMrsCmd: Done
645309.580: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
645409.580: mct_SendMrsCmd: Start
645509.580: mct_SendMrsCmd: Done
645609.580: DIMM 1 RttWr: 1
645709.580: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
645809.580: mct_SendMrsCmd: Start
645909.580: mct_SendMrsCmd: Done
646009.580: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
646109.580: mct_SendMrsCmd: Start
646209.580: mct_SendMrsCmd: Done
646309.580: DIMM 1 RttNom: 3
646409.580: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
646509.580: mct_SendMrsCmd: Start
646609.580: mct_SendMrsCmd: Done
646709.580: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
646809.580: mct_SendMrsCmd: Start
646909.580: mct_SendMrsCmd: Done
647009.580: DIMM 1 RttWr: 1
647109.580: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
647209.580: mct_SendMrsCmd: Start
647309.580: mct_SendMrsCmd: Done
647409.580: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
647509.580: mct_SendMrsCmd: Start
647609.580: mct_SendMrsCmd: Done
647709.580: DIMM 1 RttNom: 3
647809.580: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
647909.580: mct_SendMrsCmd: Start
648009.580: mct_SendMrsCmd: Done
648109.580: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
648209.580: mct_SendMrsCmd: Start
648309.580: mct_SendMrsCmd: Done
648409.580: mct_DramInit_Sw_D: Done
648509.580: AgesaHwWlPhase1: training nibble 0
648609.580: DIMM 0 RttNom: 3
648709.580: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
648809.580: DIMM 0 RttWr: 1
648909.580: DIMM 0 RttWr: 1
649009.580: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
649109.580: DIMM 0 RttWr: 1
649209.580: DIMM 0 RttNom: 3
649309.580: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
649409.580: DIMM 0 RttNom: 3
649509.580: DIMM 0 RttWr: 1
649609.580: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
649709.580: DIMM 0 RttWr: 1
649809.580: DIMM 1 RttNom: 3
649909.580: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
650009.580: DIMM 0 RttNom: 3
650109.580: DIMM 1 RttWr: 1
650209.580: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
650309.580: DIMM 0 RttWr: 1
650409.580: DIMM 1 RttNom: 3
650509.580: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
650609.580: DIMM 0 RttNom: 3
650709.580: DIMM 1 RttWr: 1
650809.580: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
650909.580: DIMM 0 RttWr: 1
651009.580: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
651109.581: <09>Lane 00 scaled delay: 0056
651209.580: <09>Lane 00 new seed: 0056
651309.580: <09>Lane 01 scaled delay: 0053
651409.580: <09>Lane 01 new seed: 0053
651509.581: <09>Lane 02 scaled delay: 0052
651609.581: <09>Lane 02 new seed: 0052
651709.581: <09>Lane 03 scaled delay: 0051
651809.581: <09>Lane 03 new seed: 0051
651909.581: <09>Lane 04 scaled delay: 0049
652009.581: <09>Lane 04 new seed: 0049
652109.581: <09>Lane 05 scaled delay: 004b
652209.581: <09>Lane 05 new seed: 004b
652309.581: <09>Lane 06 scaled delay: 004d
652409.581: <09>Lane 06 new seed: 004d
652509.581: <09>Lane 07 scaled delay: 004f
652609.581: <09>Lane 07 new seed: 004f
652709.581: <09>Lane 08 scaled delay: 004a
652809.581: <09>Lane 08 new seed: 004a
652909.581: <09>Lane 00 nibble 0 raw readback: 005c
653009.581: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
653109.581: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
653209.581: <09>Lane 01 nibble 0 raw readback: 0059
653309.581: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
653409.581: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
653509.581: <09>Lane 02 nibble 0 raw readback: 0054
653609.581: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
653709.581: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
653809.581: <09>Lane 03 nibble 0 raw readback: 0050
653909.581: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
654009.581: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
654109.581: <09>Lane 04 nibble 0 raw readback: 0043
654209.581: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
654309.581: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
654409.581: <09>Lane 05 nibble 0 raw readback: 0046
654509.581: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
654609.581: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
654709.581: <09>Lane 06 nibble 0 raw readback: 0048
654809.581: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
654909.581: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
655009.581: <09>Lane 07 nibble 0 raw readback: 004d
655109.581: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
655209.581: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
655309.581: <09>Lane 08 nibble 0 raw readback: 0045
655409.581: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
655509.581: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
655609.581: AgesaHwWlPhase1: training nibble 1
655709.581: DIMM 0 RttNom: 3
655809.581: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
655909.581: DIMM 0 RttWr: 1
656009.581: DIMM 0 RttWr: 1
656109.581: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
656209.581: DIMM 0 RttWr: 1
656309.581: DIMM 0 RttNom: 3
656409.581: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
656509.581: DIMM 0 RttNom: 3
656609.581: DIMM 0 RttWr: 1
656709.581: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
656809.581: DIMM 0 RttWr: 1
656909.581: DIMM 1 RttNom: 3
657009.581: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
657109.581: DIMM 0 RttNom: 3
657209.581: DIMM 1 RttWr: 1
657309.581: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
657409.581: DIMM 0 RttWr: 1
657509.581: DIMM 1 RttNom: 3
657609.581: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
657709.581: DIMM 0 RttNom: 3
657809.581: DIMM 1 RttWr: 1
657909.581: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
658009.581: DIMM 0 RttWr: 1
658109.581: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
658209.582: <09>Lane 00 new seed: 0056
658309.582: <09>Lane 01 new seed: 0053
658409.582: <09>Lane 02 new seed: 0052
658509.582: <09>Lane 03 new seed: 0051
658609.582: <09>Lane 04 new seed: 0049
658709.582: <09>Lane 05 new seed: 004b
658809.582: <09>Lane 06 new seed: 004d
658909.582: <09>Lane 07 new seed: 004f
659009.582: <09>Lane 08 new seed: 004a
659109.582: <09>Lane 00 nibble 1 raw readback: 005c
659209.582: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005c
659309.582: <09>Lane 00 nibble 1 adjusted value (post nibble): 0059
659409.582: <09>Lane 01 nibble 1 raw readback: 0056
659509.582: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
659609.582: <09>Lane 01 nibble 1 adjusted value (post nibble): 0054
659709.582: <09>Lane 02 nibble 1 raw readback: 0054
659809.582: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
659909.582: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
660009.582: <09>Lane 03 nibble 1 raw readback: 0050
660109.582: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
660209.582: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
660309.582: <09>Lane 04 nibble 1 raw readback: 0041
660409.582: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
660509.582: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
660609.582: <09>Lane 05 nibble 1 raw readback: 0045
660709.582: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
660809.582: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
660909.582: <09>Lane 06 nibble 1 raw readback: 004a
661009.582: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
661109.582: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
661209.582: <09>Lane 07 nibble 1 raw readback: 004c
661309.582: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
661409.582: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
661509.582: <09>Lane 08 nibble 1 raw readback: 0044
661609.582: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0044
661709.582: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
661809.582: <09>original critical gross delay: 0
661909.582: <09>new critical gross delay: 0
662009.582: DIMM 0 RttNom: 3
662109.582: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
662209.582: DIMM 0 RttNom: 3
662309.582: DIMM 0 RttWr: 1
662409.582: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
662509.582: DIMM 0 RttWr: 1
662609.582: DIMM 0 RttNom: 3
662709.582: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
662809.582: DIMM 0 RttNom: 3
662909.582: DIMM 0 RttWr: 1
663009.582: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
663109.582: DIMM 0 RttWr: 1
663209.582: DIMM 1 RttNom: 3
663309.582: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
663409.582: DIMM 0 RttNom: 3
663509.582: DIMM 1 RttWr: 1
663609.582: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
663709.582: DIMM 0 RttWr: 1
663809.582: DIMM 1 RttNom: 3
663909.582: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
664009.582: DIMM 0 RttNom: 3
664109.582: DIMM 1 RttWr: 1
664209.582: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
664309.582: DIMM 0 RttWr: 1
664409.582: AgesaHwWlPhase1: training nibble 0
664509.582: DIMM 1 RttNom: 3
664609.582: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
664709.582: DIMM 1 RttWr: 1
664809.583: DIMM 1 RttWr: 1
664909.582: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
665009.583: DIMM 1 RttWr: 1
665109.583: DIMM 1 RttNom: 3
665209.583: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
665309.583: DIMM 1 RttNom: 3
665409.583: DIMM 1 RttWr: 1
665509.583: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
665609.583: DIMM 1 RttWr: 1
665709.583: DIMM 0 RttNom: 3
665809.583: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
665909.583: DIMM 1 RttNom: 3
666009.583: DIMM 0 RttWr: 1
666109.583: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
666209.583: DIMM 1 RttWr: 1
666309.583: DIMM 0 RttNom: 3
666409.583: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
666509.583: DIMM 1 RttNom: 3
666609.583: DIMM 0 RttWr: 1
666709.583: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
666809.583: DIMM 1 RttWr: 1
666909.583: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
667009.583: <09>Lane 00 scaled delay: 0052
667109.583: <09>Lane 00 new seed: 0052
667209.583: <09>Lane 01 scaled delay: 004f
667309.583: <09>Lane 01 new seed: 004f
667409.583: <09>Lane 02 scaled delay: 004d
667509.583: <09>Lane 02 new seed: 004d
667609.583: <09>Lane 03 scaled delay: 004d
667709.583: <09>Lane 03 new seed: 004d
667809.583: <09>Lane 04 scaled delay: 0045
667909.583: <09>Lane 04 new seed: 0045
668009.583: <09>Lane 05 scaled delay: 0047
668109.583: <09>Lane 05 new seed: 0047
668209.583: <09>Lane 06 scaled delay: 0049
668309.583: <09>Lane 06 new seed: 0049
668409.583: <09>Lane 07 scaled delay: 004a
668509.583: <09>Lane 07 new seed: 004a
668609.583: <09>Lane 08 scaled delay: 0047
668709.583: <09>Lane 08 new seed: 0047
668809.583: <09>Lane 00 nibble 0 raw readback: 0052
668909.583: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
669009.583: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
669109.583: <09>Lane 01 nibble 0 raw readback: 004f
669209.583: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
669309.583: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
669409.583: <09>Lane 02 nibble 0 raw readback: 0049
669509.583: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
669609.583: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
669709.583: <09>Lane 03 nibble 0 raw readback: 0045
669809.583: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
669909.583: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
670009.583: <09>Lane 04 nibble 0 raw readback: 0038
670109.583: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
670209.583: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
670309.583: <09>Lane 05 nibble 0 raw readback: 003b
670409.583: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
670509.583: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
670609.583: <09>Lane 06 nibble 0 raw readback: 0040
670709.583: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
670809.583: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
670909.583: <09>Lane 07 nibble 0 raw readback: 0044
671009.583: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
671109.583: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
671209.583: <09>Lane 08 nibble 0 raw readback: 003c
671309.583: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
671409.583: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
671509.583: AgesaHwWlPhase1: training nibble 1
671609.583: DIMM 1 RttNom: 3
671709.583: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
671809.583: DIMM 1 RttWr: 1
671909.583: DIMM 1 RttWr: 1
672009.583: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
672109.583: DIMM 1 RttWr: 1
672209.583: DIMM 1 RttNom: 3
672309.583: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
672409.584: DIMM 1 RttNom: 3
672509.584: DIMM 1 RttWr: 1
672609.584: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
672709.584: DIMM 1 RttWr: 1
672809.584: DIMM 0 RttNom: 3
672909.584: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
673009.584: DIMM 1 RttNom: 3
673109.584: DIMM 0 RttWr: 1
673209.584: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
673309.584: DIMM 1 RttWr: 1
673409.584: DIMM 0 RttNom: 3
673509.584: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
673609.584: DIMM 1 RttNom: 3
673709.584: DIMM 0 RttWr: 1
673809.584: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
673909.584: DIMM 1 RttWr: 1
674009.584: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
674109.584: <09>Lane 00 new seed: 0052
674209.584: <09>Lane 01 new seed: 004f
674309.584: <09>Lane 02 new seed: 004d
674409.584: <09>Lane 03 new seed: 004d
674509.584: <09>Lane 04 new seed: 0045
674609.584: <09>Lane 05 new seed: 0047
674709.584: <09>Lane 06 new seed: 0049
674809.584: <09>Lane 07 new seed: 004a
674909.584: <09>Lane 08 new seed: 0047
675009.584: <09>Lane 00 nibble 1 raw readback: 0051
675109.584: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
675209.584: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
675309.584: <09>Lane 01 nibble 1 raw readback: 004d
675409.584: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004d
675509.584: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
675609.584: <09>Lane 02 nibble 1 raw readback: 0049
675709.584: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
675809.584: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
675909.584: <09>Lane 03 nibble 1 raw readback: 0046
676009.584: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
676109.584: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
676209.584: <09>Lane 04 nibble 1 raw readback: 0037
676309.584: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
676409.584: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
676509.584: <09>Lane 05 nibble 1 raw readback: 003c
676609.584: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
676709.584: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
676809.584: <09>Lane 06 nibble 1 raw readback: 003f
676909.584: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
677009.584: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
677109.584: <09>Lane 07 nibble 1 raw readback: 0042
677209.584: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
677309.584: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
677409.584: <09>Lane 08 nibble 1 raw readback: 003c
677509.584: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
677609.584: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
677709.584: <09>original critical gross delay: 0
677809.584: <09>new critical gross delay: 0
677909.584: DIMM 1 RttNom: 3
678009.584: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
678109.584: DIMM 1 RttNom: 3
678209.584: DIMM 1 RttWr: 1
678309.584: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
678409.584: DIMM 1 RttWr: 1
678509.584: DIMM 1 RttNom: 3
678609.584: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
678709.584: DIMM 1 RttNom: 3
678809.584: DIMM 1 RttWr: 1
678909.584: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
679009.584: DIMM 1 RttWr: 1
679109.584: DIMM 0 RttNom: 3
679209.584: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
679309.584: DIMM 1 RttNom: 3
679409.585: DIMM 0 RttWr: 1
679509.585: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
679609.585: DIMM 1 RttWr: 1
679709.585: DIMM 0 RttNom: 3
679809.585: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
679909.585: DIMM 1 RttNom: 3
680009.585: DIMM 0 RttWr: 1
680109.585: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
680209.585: DIMM 1 RttWr: 1
680309.585: SetTargetFreq: Start
680409.585: SetTargetFreq: Node 0: New frequency code: 000e
680509.585: ChangeMemClk: Start
680609.585: set_2t_configuration: Start
680709.585: set_2t_configuration: Done
680809.585: mct_BeforePlatformSpec: Start
680909.585: mct_BeforePlatformSpec: Done
681009.585: mct_PlatformSpec: Start
681109.585: Programmed DCT 0 timing/termination pattern 00383a38 30222222
681209.585: mct_PlatformSpec: Done
681309.585: set_2t_configuration: Start
681409.585: set_2t_configuration: Done
681509.585: mct_BeforePlatformSpec: Start
681609.585: mct_BeforePlatformSpec: Done
681709.585: mct_PlatformSpec: Start
681809.585: Programmed DCT 1 timing/termination pattern 00383a38 30222222
681909.585: mct_PlatformSpec: Done
682009.585: ChangeMemClk: Done
682109.585: phyAssistedMemFnceTraining: Start
682209.585: phyAssistedMemFnceTraining: training node 0 DCT 0
682309.585: phyAssistedMemFnceTraining: done training node 0 DCT 0
682409.585: phyAssistedMemFnceTraining: training node 0 DCT 1
682509.586: phyAssistedMemFnceTraining: done training node 0 DCT 1
682609.586: phyAssistedMemFnceTraining: Done
682709.586: InitPhyCompensation: DCT 0: Start
682809.586: Waiting for predriver calibration to be applied...done!
682909.586: InitPhyCompensation: DCT 0: Done
683009.586: phyAssistedMemFnceTraining: Start
683109.586: phyAssistedMemFnceTraining: training node 0 DCT 0
683209.586: phyAssistedMemFnceTraining: done training node 0 DCT 0
683309.586: phyAssistedMemFnceTraining: training node 0 DCT 1
683409.586: phyAssistedMemFnceTraining: done training node 0 DCT 1
683509.586: phyAssistedMemFnceTraining: Done
683609.586: InitPhyCompensation: DCT 1: Start
683709.586: Waiting for predriver calibration to be applied...done!
683809.586: InitPhyCompensation: DCT 1: Done
683909.586: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
684009.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
684109.586: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
684209.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
684309.586: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
684409.586: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
684509.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
684609.586: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
684709.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
684809.586: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
684909.586: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
685009.586: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
685109.587: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
685209.587: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
685309.587: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
685409.587: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
685509.587: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
685609.587: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
685709.587: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
685809.587: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
685909.587: SetTargetFreq: Done
686009.587: SPD2ndTiming: Start
686109.587: SPD2ndTiming: Done
686209.587: mct_BeforeDramInit_Prod_D: Start
686309.587: mct_ProgramODT_D: Start
686409.587: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
686509.587: mct_ProgramODT_D: Done
686609.587: mct_BeforeDramInit_Prod_D: Done
686709.587: mct_DramInit_Sw_D: Start
686809.587: DIMM 0 RttWr: 2
686909.587: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
687009.587: mct_SendMrsCmd: Start
687109.587: mct_SendMrsCmd: Done
687209.587: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
687309.587: mct_SendMrsCmd: Start
687409.587: mct_SendMrsCmd: Done
687509.587: DIMM 0 RttNom: 5
687609.587: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
687709.587: mct_SendMrsCmd: Start
687809.587: mct_SendMrsCmd: Done
687909.587: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
688009.587: mct_SendMrsCmd: Start
688109.587: mct_SendMrsCmd: Done
688209.587: DIMM 0 RttWr: 2
688309.587: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
688409.587: mct_SendMrsCmd: Start
688509.587: mct_SendMrsCmd: Done
688609.587: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
688709.587: mct_SendMrsCmd: Start
688809.587: mct_SendMrsCmd: Done
688909.587: DIMM 0 RttNom: 5
689009.588: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
689109.587: mct_SendMrsCmd: Start
689209.587: mct_SendMrsCmd: Done
689309.588: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
689409.588: mct_SendMrsCmd: Start
689509.588: mct_SendMrsCmd: Done
689609.588: DIMM 1 RttWr: 2
689709.588: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
689809.588: mct_SendMrsCmd: Start
689909.588: mct_SendMrsCmd: Done
690009.588: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
690109.588: mct_SendMrsCmd: Start
690209.588: mct_SendMrsCmd: Done
690309.588: DIMM 1 RttNom: 5
690409.588: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
690509.588: mct_SendMrsCmd: Start
690609.588: mct_SendMrsCmd: Done
690709.588: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
690809.588: mct_SendMrsCmd: Start
690909.588: mct_SendMrsCmd: Done
691009.588: DIMM 1 RttWr: 2
691109.588: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
691209.588: mct_SendMrsCmd: Start
691309.588: mct_SendMrsCmd: Done
691409.588: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
691509.588: mct_SendMrsCmd: Start
691609.588: mct_SendMrsCmd: Done
691709.588: DIMM 1 RttNom: 5
691809.588: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
691909.588: mct_SendMrsCmd: Start
692009.588: mct_SendMrsCmd: Done
692109.588: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
692209.588: mct_SendMrsCmd: Start
692309.588: mct_SendMrsCmd: Done
692409.588: mct_DramInit_Sw_D: Done
692509.588: AgesaHwWlPhase1: training nibble 0
692609.588: DIMM 0 RttNom: 5
692709.588: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
692809.588: DIMM 0 RttWr: 2
692909.588: DIMM 0 RttWr: 2
693009.588: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
693109.588: DIMM 0 RttWr: 2
693209.588: DIMM 0 RttNom: 5
693309.588: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
693409.588: DIMM 0 RttNom: 5
693509.588: DIMM 0 RttWr: 2
693609.588: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
693709.588: DIMM 0 RttWr: 2
693809.588: DIMM 1 RttNom: 5
693909.588: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
694009.588: DIMM 0 RttNom: 5
694109.588: DIMM 1 RttWr: 2
694209.588: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
694309.588: DIMM 0 RttWr: 2
694409.588: DIMM 1 RttNom: 5
694509.588: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
694609.588: DIMM 0 RttNom: 5
694709.588: DIMM 1 RttWr: 2
694809.588: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
694909.588: DIMM 0 RttWr: 2
695009.588: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
695109.589: <09>Lane 00 scaled delay: 006b
695209.589: <09>Lane 00 new seed: 006b
695309.589: <09>Lane 01 scaled delay: 0063
695409.589: <09>Lane 01 new seed: 0063
695509.589: <09>Lane 02 scaled delay: 0061
695609.589: <09>Lane 02 new seed: 0061
695709.589: <09>Lane 03 scaled delay: 005e
695809.589: <09>Lane 03 new seed: 005e
695909.589: <09>Lane 04 scaled delay: 004f
696009.589: <09>Lane 04 new seed: 004f
696109.589: <09>Lane 05 scaled delay: 0055
696209.589: <09>Lane 05 new seed: 0055
696309.589: <09>Lane 06 scaled delay: 0059
696409.589: <09>Lane 06 new seed: 0059
696509.589: <09>Lane 07 scaled delay: 005a
696609.589: <09>Lane 07 new seed: 005a
696709.589: <09>Lane 08 scaled delay: 0052
696809.589: <09>Lane 08 new seed: 0052
696909.589: <09>Lane 00 nibble 0 raw readback: 0030
697009.589: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
697109.589: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
697209.589: <09>Lane 01 nibble 0 raw readback: 0026
697309.589: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
697409.589: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
697509.589: <09>Lane 02 nibble 0 raw readback: 0021
697609.589: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
697709.589: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
697809.589: <09>Lane 03 nibble 0 raw readback: 005c
697909.589: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
698009.589: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
698109.589: <09>Lane 04 nibble 0 raw readback: 004a
698209.589: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
698309.589: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
698409.589: <09>Lane 05 nibble 0 raw readback: 0053
698509.589: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
698609.589: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
698709.589: <09>Lane 06 nibble 0 raw readback: 0057
698809.589: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
698909.589: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
699009.589: <09>Lane 07 nibble 0 raw readback: 005b
699109.589: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
699209.589: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
699309.589: <09>Lane 08 nibble 0 raw readback: 004e
699409.589: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
699509.589: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
699609.589: AgesaHwWlPhase1: training nibble 1
699709.589: DIMM 0 RttNom: 5
699809.589: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
699909.589: DIMM 0 RttWr: 2
700009.589: DIMM 0 RttWr: 2
700109.589: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
700209.589: DIMM 0 RttWr: 2
700309.589: DIMM 0 RttNom: 5
700409.589: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
700509.589: DIMM 0 RttNom: 5
700609.590: DIMM 0 RttWr: 2
700709.590: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
700809.590: DIMM 0 RttWr: 2
700909.590: DIMM 1 RttNom: 5
701009.590: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
701109.590: DIMM 0 RttNom: 5
701209.590: DIMM 1 RttWr: 2
701309.590: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
701409.590: DIMM 0 RttWr: 2
701509.590: DIMM 1 RttNom: 5
701609.590: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
701709.590: DIMM 0 RttNom: 5
701809.590: DIMM 1 RttWr: 2
701909.590: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
702009.590: DIMM 0 RttWr: 2
702109.590: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
702209.590: <09>Lane 00 new seed: 006b
702309.590: <09>Lane 01 new seed: 0063
702409.590: <09>Lane 02 new seed: 0061
702509.590: <09>Lane 03 new seed: 005e
702609.590: <09>Lane 04 new seed: 004f
702709.590: <09>Lane 05 new seed: 0055
702809.590: <09>Lane 06 new seed: 0059
702909.590: <09>Lane 07 new seed: 005a
703009.590: <09>Lane 08 new seed: 0052
703109.590: <09>Lane 00 nibble 1 raw readback: 002e
703209.590: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
703309.590: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
703409.590: <09>Lane 01 nibble 1 raw readback: 0025
703509.590: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
703609.590: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
703709.590: <09>Lane 02 nibble 1 raw readback: 0022
703809.590: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
703909.590: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
704009.590: <09>Lane 03 nibble 1 raw readback: 005d
704109.590: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
704209.590: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
704309.590: <09>Lane 04 nibble 1 raw readback: 004a
704409.590: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
704509.590: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
704609.590: <09>Lane 05 nibble 1 raw readback: 0052
704709.590: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
704809.590: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
704909.590: <09>Lane 06 nibble 1 raw readback: 0058
705009.590: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
705109.590: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
705209.590: <09>Lane 07 nibble 1 raw readback: 005a
705309.590: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005a
705409.590: <09>Lane 07 nibble 1 adjusted value (post nibble): 005a
705509.590: <09>Lane 08 nibble 1 raw readback: 004e
705609.590: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
705709.590: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
705809.590: <09>original critical gross delay: 0
705909.590: <09>new critical gross delay: 0
706009.590: DIMM 0 RttNom: 5
706109.590: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
706209.590: DIMM 0 RttNom: 5
706309.590: DIMM 0 RttWr: 2
706409.590: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
706509.590: DIMM 0 RttWr: 2
706609.590: DIMM 0 RttNom: 5
706709.590: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
706809.590: DIMM 0 RttNom: 5
706909.590: DIMM 0 RttWr: 2
707009.590: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
707109.590: DIMM 0 RttWr: 2
707209.590: DIMM 1 RttNom: 5
707309.590: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
707409.590: DIMM 0 RttNom: 5
707509.591: DIMM 1 RttWr: 2
707609.591: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
707709.591: DIMM 0 RttWr: 2
707809.591: DIMM 1 RttNom: 5
707909.591: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
708009.591: DIMM 0 RttNom: 5
708109.591: DIMM 1 RttWr: 2
708209.591: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
708309.591: DIMM 0 RttWr: 2
708409.591: AgesaHwWlPhase1: training nibble 0
708509.591: DIMM 1 RttNom: 5
708609.591: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
708709.591: DIMM 1 RttWr: 2
708809.591: DIMM 1 RttWr: 2
708909.591: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
709009.591: DIMM 1 RttWr: 2
709109.591: DIMM 1 RttNom: 5
709209.591: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
709309.591: DIMM 1 RttNom: 5
709409.591: DIMM 1 RttWr: 2
709509.591: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
709609.591: DIMM 1 RttWr: 2
709709.591: DIMM 0 RttNom: 5
709809.591: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
709909.591: DIMM 1 RttNom: 5
710009.591: DIMM 0 RttWr: 2
710109.591: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
710209.591: DIMM 1 RttWr: 2
710309.591: DIMM 0 RttNom: 5
710409.591: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
710509.591: DIMM 1 RttNom: 5
710609.591: DIMM 0 RttWr: 2
710709.591: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
710809.591: DIMM 1 RttWr: 2
710909.591: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
711009.591: <09>Lane 00 scaled delay: 005e
711109.591: <09>Lane 00 new seed: 005e
711209.591: <09>Lane 01 scaled delay: 0058
711309.591: <09>Lane 01 new seed: 0058
711409.591: <09>Lane 02 scaled delay: 0057
711509.591: <09>Lane 02 new seed: 0057
711609.591: <09>Lane 03 scaled delay: 0052
711709.591: <09>Lane 03 new seed: 0052
711809.591: <09>Lane 04 scaled delay: 0043
711909.591: <09>Lane 04 new seed: 0043
712009.591: <09>Lane 05 scaled delay: 004a
712109.591: <09>Lane 05 new seed: 004a
712209.591: <09>Lane 06 scaled delay: 004d
712309.591: <09>Lane 06 new seed: 004d
712409.591: <09>Lane 07 scaled delay: 0050
712509.591: <09>Lane 07 new seed: 0050
712609.591: <09>Lane 08 scaled delay: 0045
712709.591: <09>Lane 08 new seed: 0045
712809.591: <09>Lane 00 nibble 0 raw readback: 005f
712909.591: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
713009.591: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
713109.591: <09>Lane 01 nibble 0 raw readback: 0056
713209.591: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
713309.591: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
713409.591: <09>Lane 02 nibble 0 raw readback: 0052
713509.591: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0052
713609.591: <09>Lane 02 nibble 0 adjusted value (post nibble): 0052
713709.591: <09>Lane 03 nibble 0 raw readback: 004c
713809.591: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004c
713909.591: <09>Lane 03 nibble 0 adjusted value (post nibble): 004c
714009.591: <09>Lane 04 nibble 0 raw readback: 003d
714109.591: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003d
714209.591: <09>Lane 04 nibble 0 adjusted value (post nibble): 003d
714309.591: <09>Lane 05 nibble 0 raw readback: 0046
714409.591: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
714509.591: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
714609.592: <09>Lane 06 nibble 0 raw readback: 0048
714709.592: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
714809.592: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
714909.592: <09>Lane 07 nibble 0 raw readback: 004c
715009.592: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004c
715109.592: <09>Lane 07 nibble 0 adjusted value (post nibble): 004c
715209.592: <09>Lane 08 nibble 0 raw readback: 003e
715309.592: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
715409.592: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
715509.592: AgesaHwWlPhase1: training nibble 1
715609.592: DIMM 1 RttNom: 5
715709.592: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
715809.592: DIMM 1 RttWr: 2
715909.592: DIMM 1 RttWr: 2
716009.592: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
716109.592: DIMM 1 RttWr: 2
716209.592: DIMM 1 RttNom: 5
716309.592: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
716409.592: DIMM 1 RttNom: 5
716509.592: DIMM 1 RttWr: 2
716609.592: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
716709.592: DIMM 1 RttWr: 2
716809.592: DIMM 0 RttNom: 5
716909.592: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
717009.592: DIMM 1 RttNom: 5
717109.592: DIMM 0 RttWr: 2
717209.592: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
717309.592: DIMM 1 RttWr: 2
717409.592: DIMM 0 RttNom: 5
717509.592: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
717609.592: DIMM 1 RttNom: 5
717709.592: DIMM 0 RttWr: 2
717809.592: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
717909.592: DIMM 1 RttWr: 2
718009.592: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
718109.592: <09>Lane 00 new seed: 005e
718209.592: <09>Lane 01 new seed: 0058
718309.592: <09>Lane 02 new seed: 0057
718409.592: <09>Lane 03 new seed: 0052
718509.592: <09>Lane 04 new seed: 0043
718609.592: <09>Lane 05 new seed: 004a
718709.592: <09>Lane 06 new seed: 004d
718809.592: <09>Lane 07 new seed: 0050
718909.592: <09>Lane 08 new seed: 0045
719009.592: <09>Lane 00 nibble 1 raw readback: 0060
719109.592: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
719209.592: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
719309.592: <09>Lane 01 nibble 1 raw readback: 0057
719409.592: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0057
719509.592: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
719609.592: <09>Lane 02 nibble 1 raw readback: 0054
719709.592: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
719809.592: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
719909.592: <09>Lane 03 nibble 1 raw readback: 004e
720009.592: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
720109.592: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
720209.592: <09>Lane 04 nibble 1 raw readback: 003c
720309.592: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003c
720409.592: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
720509.592: <09>Lane 05 nibble 1 raw readback: 0045
720609.592: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
720709.592: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
720809.592: <09>Lane 06 nibble 1 raw readback: 0048
720909.592: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0048
721009.592: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
721109.592: <09>Lane 07 nibble 1 raw readback: 004e
721209.592: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
721309.592: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
721409.592: <09>Lane 08 nibble 1 raw readback: 003f
721509.592: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
721609.592: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
721709.592: <09>original critical gross delay: 0
721809.592: <09>new critical gross delay: 0
721909.593: DIMM 1 RttNom: 5
722009.593: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
722109.593: DIMM 1 RttNom: 5
722209.593: DIMM 1 RttWr: 2
722309.593: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
722409.593: DIMM 1 RttWr: 2
722509.593: DIMM 1 RttNom: 5
722609.593: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
722709.593: DIMM 1 RttNom: 5
722809.593: DIMM 1 RttWr: 2
722909.593: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
723009.593: DIMM 1 RttWr: 2
723109.593: DIMM 0 RttNom: 5
723209.593: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
723309.593: DIMM 1 RttNom: 5
723409.593: DIMM 0 RttWr: 2
723509.593: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
723609.593: DIMM 1 RttWr: 2
723709.593: DIMM 0 RttNom: 5
723809.593: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
723909.593: DIMM 1 RttNom: 5
724009.593: DIMM 0 RttWr: 2
724109.593: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
724209.593: DIMM 1 RttWr: 2
724309.593: SPD2ndTiming: Start
724409.593: SPD2ndTiming: Done
724509.593: mct_BeforeDramInit_Prod_D: Start
724609.593: mct_ProgramODT_D: Start
724709.593: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
724809.593: mct_ProgramODT_D: Done
724909.593: mct_BeforeDramInit_Prod_D: Done
725009.593: mct_DramInit_Sw_D: Start
725109.594: DIMM 0 RttWr: 2
725209.594: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
725309.594: mct_SendMrsCmd: Start
725409.594: mct_SendMrsCmd: Done
725509.594: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
725609.594: mct_SendMrsCmd: Start
725709.594: mct_SendMrsCmd: Done
725809.594: DIMM 0 RttNom: 5
725909.594: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
726009.594: mct_SendMrsCmd: Start
726109.594: mct_SendMrsCmd: Done
726209.594: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
726309.594: mct_SendMrsCmd: Start
726409.594: mct_SendMrsCmd: Done
726509.594: DIMM 0 RttWr: 2
726609.594: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
726709.594: mct_SendMrsCmd: Start
726809.594: mct_SendMrsCmd: Done
726909.594: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
727009.594: mct_SendMrsCmd: Start
727109.594: mct_SendMrsCmd: Done
727209.594: DIMM 0 RttNom: 5
727309.594: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
727409.594: mct_SendMrsCmd: Start
727509.594: mct_SendMrsCmd: Done
727609.594: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
727709.594: mct_SendMrsCmd: Start
727809.594: mct_SendMrsCmd: Done
727909.594: DIMM 1 RttWr: 2
728009.594: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
728109.594: mct_SendMrsCmd: Start
728209.594: mct_SendMrsCmd: Done
728309.594: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
728409.594: mct_SendMrsCmd: Start
728509.594: mct_SendMrsCmd: Done
728609.594: DIMM 1 RttNom: 5
728709.594: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
728809.594: mct_SendMrsCmd: Start
728909.594: mct_SendMrsCmd: Done
729009.594: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
729109.594: mct_SendMrsCmd: Start
729209.594: mct_SendMrsCmd: Done
729309.594: DIMM 1 RttWr: 2
729409.594: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
729509.594: mct_SendMrsCmd: Start
729609.594: mct_SendMrsCmd: Done
729709.594: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
729809.594: mct_SendMrsCmd: Start
729909.594: mct_SendMrsCmd: Done
730009.594: DIMM 1 RttNom: 5
730109.594: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
730209.594: mct_SendMrsCmd: Start
730309.594: mct_SendMrsCmd: Done
730409.594: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
730509.594: mct_SendMrsCmd: Start
730609.594: mct_SendMrsCmd: Done
730709.594: mct_DramInit_Sw_D: Done
730809.594: AgesaHwWlPhase1: training nibble 0
730909.594: DIMM 0 RttNom: 5
731009.594: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
731109.594: DIMM 0 RttWr: 2
731209.594: DIMM 0 RttWr: 2
731309.594: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
731409.594: DIMM 0 RttWr: 2
731509.594: DIMM 0 RttNom: 5
731609.594: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
731709.594: DIMM 0 RttNom: 5
731809.594: DIMM 0 RttWr: 2
731909.594: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
732009.594: DIMM 0 RttWr: 2
732109.595: DIMM 1 RttNom: 5
732209.595: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
732309.595: DIMM 0 RttNom: 5
732409.595: DIMM 1 RttWr: 2
732509.595: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
732609.595: DIMM 0 RttWr: 2
732709.595: DIMM 1 RttNom: 5
732809.595: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
732909.595: DIMM 0 RttNom: 5
733009.595: DIMM 1 RttWr: 2
733109.595: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
733209.595: DIMM 0 RttWr: 2
733309.595: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
733409.595: <09>Lane 00 scaled delay: 0067
733509.595: <09>Lane 00 new seed: 0067
733609.595: <09>Lane 01 scaled delay: 0061
733709.595: <09>Lane 01 new seed: 0061
733809.595: <09>Lane 02 scaled delay: 005f
733909.595: <09>Lane 02 new seed: 005f
734009.595: <09>Lane 03 scaled delay: 005c
734109.595: <09>Lane 03 new seed: 005c
734209.595: <09>Lane 04 scaled delay: 004e
734309.595: <09>Lane 04 new seed: 004e
734409.595: <09>Lane 05 scaled delay: 0052
734509.595: <09>Lane 05 new seed: 0052
734609.595: <09>Lane 06 scaled delay: 0055
734709.595: <09>Lane 06 new seed: 0055
734809.595: <09>Lane 07 scaled delay: 0058
734909.595: <09>Lane 07 new seed: 0058
735009.595: <09>Lane 08 scaled delay: 0050
735109.595: <09>Lane 08 new seed: 0050
735209.595: <09>Lane 00 nibble 0 raw readback: 002b
735309.595: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006b
735409.595: <09>Lane 00 nibble 0 adjusted value (post nibble): 006b
735509.595: <09>Lane 01 nibble 0 raw readback: 0026
735609.595: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
735709.595: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
735809.595: <09>Lane 02 nibble 0 raw readback: 0060
735909.595: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
736009.595: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
736109.595: <09>Lane 03 nibble 0 raw readback: 005b
736209.595: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
736309.595: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
736409.595: <09>Lane 04 nibble 0 raw readback: 004a
736509.595: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
736609.595: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
736709.595: <09>Lane 05 nibble 0 raw readback: 0050
736809.595: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0050
736909.595: <09>Lane 05 nibble 0 adjusted value (post nibble): 0050
737009.595: <09>Lane 06 nibble 0 raw readback: 0053
737109.595: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0053
737209.595: <09>Lane 06 nibble 0 adjusted value (post nibble): 0053
737309.595: <09>Lane 07 nibble 0 raw readback: 0059
737409.595: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
737509.595: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
737609.595: <09>Lane 08 nibble 0 raw readback: 004e
737709.595: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
737809.595: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
737909.595: AgesaHwWlPhase1: training nibble 1
738009.595: DIMM 0 RttNom: 5
738109.595: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
738209.595: DIMM 0 RttWr: 2
738309.595: DIMM 0 RttWr: 2
738409.596: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
738509.596: DIMM 0 RttWr: 2
738609.596: DIMM 0 RttNom: 5
738709.596: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
738809.596: DIMM 0 RttNom: 5
738909.596: DIMM 0 RttWr: 2
739009.596: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
739109.596: DIMM 0 RttWr: 2
739209.596: DIMM 1 RttNom: 5
739309.596: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
739409.596: DIMM 0 RttNom: 5
739509.596: DIMM 1 RttWr: 2
739609.596: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
739709.596: DIMM 0 RttWr: 2
739809.596: DIMM 1 RttNom: 5
739909.596: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
740009.596: DIMM 0 RttNom: 5
740109.596: DIMM 1 RttWr: 2
740209.596: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
740309.596: DIMM 0 RttWr: 2
740409.596: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
740509.596: <09>Lane 00 new seed: 0067
740609.596: <09>Lane 01 new seed: 0061
740709.596: <09>Lane 02 new seed: 005f
740809.596: <09>Lane 03 new seed: 005c
740909.596: <09>Lane 04 new seed: 004e
741009.596: <09>Lane 05 new seed: 0052
741109.596: <09>Lane 06 new seed: 0055
741209.596: <09>Lane 07 new seed: 0058
741309.596: <09>Lane 08 new seed: 0050
741409.596: <09>Lane 00 nibble 1 raw readback: 002b
741509.596: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006b
741609.596: <09>Lane 00 nibble 1 adjusted value (post nibble): 0069
741709.596: <09>Lane 01 nibble 1 raw readback: 0025
741809.596: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
741909.596: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
742009.596: <09>Lane 02 nibble 1 raw readback: 0061
742109.596: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
742209.596: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
742309.596: <09>Lane 03 nibble 1 raw readback: 005c
742409.596: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
742509.596: <09>Lane 03 nibble 1 adjusted value (post nibble): 005c
742609.596: <09>Lane 04 nibble 1 raw readback: 004a
742709.596: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
742809.596: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
742909.596: <09>Lane 05 nibble 1 raw readback: 004f
743009.596: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
743109.596: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
743209.596: <09>Lane 06 nibble 1 raw readback: 0055
743309.596: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
743409.596: <09>Lane 06 nibble 1 adjusted value (post nibble): 0055
743509.596: <09>Lane 07 nibble 1 raw readback: 0059
743609.596: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0059
743709.596: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
743809.596: <09>Lane 08 nibble 1 raw readback: 004e
743909.596: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
744009.596: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
744109.596: <09>original critical gross delay: 0
744209.596: <09>new critical gross delay: 0
744309.596: DIMM 0 RttNom: 5
744409.596: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
744509.596: DIMM 0 RttNom: 5
744609.596: DIMM 0 RttWr: 2
744709.596: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
744809.596: DIMM 0 RttWr: 2
744909.597: DIMM 0 RttNom: 5
745009.597: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
745109.597: DIMM 0 RttNom: 5
745209.597: DIMM 0 RttWr: 2
745309.597: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
745409.597: DIMM 0 RttWr: 2
745509.597: DIMM 1 RttNom: 5
745609.597: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
745709.597: DIMM 0 RttNom: 5
745809.597: DIMM 1 RttWr: 2
745909.597: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
746009.597: DIMM 0 RttWr: 2
746109.597: DIMM 1 RttNom: 5
746209.597: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
746309.597: DIMM 0 RttNom: 5
746409.597: DIMM 1 RttWr: 2
746509.597: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
746609.597: DIMM 0 RttWr: 2
746709.597: AgesaHwWlPhase1: training nibble 0
746809.597: DIMM 1 RttNom: 5
746909.597: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
747009.597: DIMM 1 RttWr: 2
747109.597: DIMM 1 RttWr: 2
747209.597: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
747309.597: DIMM 1 RttWr: 2
747409.597: DIMM 1 RttNom: 5
747509.597: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
747609.597: DIMM 1 RttNom: 5
747709.597: DIMM 1 RttWr: 2
747809.597: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
747909.597: DIMM 1 RttWr: 2
748009.597: DIMM 0 RttNom: 5
748109.597: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
748209.597: DIMM 1 RttNom: 5
748309.597: DIMM 0 RttWr: 2
748409.597: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
748509.597: DIMM 1 RttWr: 2
748609.597: DIMM 0 RttNom: 5
748709.597: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
748809.597: DIMM 1 RttNom: 5
748909.597: DIMM 0 RttWr: 2
749009.597: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
749109.597: DIMM 1 RttWr: 2
749209.597: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
749309.597: <09>Lane 00 scaled delay: 005d
749409.597: <09>Lane 00 new seed: 005d
749509.597: <09>Lane 01 scaled delay: 0059
749609.597: <09>Lane 01 new seed: 0059
749709.597: <09>Lane 02 scaled delay: 0055
749809.597: <09>Lane 02 new seed: 0055
749909.597: <09>Lane 03 scaled delay: 0053
750009.597: <09>Lane 03 new seed: 0053
750109.597: <09>Lane 04 scaled delay: 0045
750209.597: <09>Lane 04 new seed: 0045
750309.597: <09>Lane 05 scaled delay: 0049
750409.597: <09>Lane 05 new seed: 0049
750509.597: <09>Lane 06 scaled delay: 004d
750609.597: <09>Lane 06 new seed: 004d
750709.597: <09>Lane 07 scaled delay: 004f
750809.597: <09>Lane 07 new seed: 004f
750909.597: <09>Lane 08 scaled delay: 0049
751009.597: <09>Lane 08 new seed: 0049
751109.597: <09>Lane 00 nibble 0 raw readback: 005f
751209.597: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
751309.597: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
751409.597: <09>Lane 01 nibble 0 raw readback: 005a
751509.597: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005a
751609.598: <09>Lane 01 nibble 0 adjusted value (post nibble): 005a
751709.597: <09>Lane 02 nibble 0 raw readback: 0052
751809.597: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0052
751909.597: <09>Lane 02 nibble 0 adjusted value (post nibble): 0052
752009.597: <09>Lane 03 nibble 0 raw readback: 004e
752109.598: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
752209.598: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
752309.598: <09>Lane 04 nibble 0 raw readback: 003e
752409.598: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003e
752509.598: <09>Lane 04 nibble 0 adjusted value (post nibble): 003e
752609.598: <09>Lane 05 nibble 0 raw readback: 0042
752709.598: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0042
752809.598: <09>Lane 05 nibble 0 adjusted value (post nibble): 0042
752909.598: <09>Lane 06 nibble 0 raw readback: 0049
753009.598: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
753109.598: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
753209.598: <09>Lane 07 nibble 0 raw readback: 004d
753309.598: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
753409.598: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
753509.598: <09>Lane 08 nibble 0 raw readback: 0041
753609.598: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
753709.598: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
753809.598: AgesaHwWlPhase1: training nibble 1
753909.598: DIMM 1 RttNom: 5
754009.598: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
754109.598: DIMM 1 RttWr: 2
754209.598: DIMM 1 RttWr: 2
754309.598: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
754409.598: DIMM 1 RttWr: 2
754509.598: DIMM 1 RttNom: 5
754609.598: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
754709.598: DIMM 1 RttNom: 5
754809.598: DIMM 1 RttWr: 2
754909.598: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
755009.598: DIMM 1 RttWr: 2
755109.598: DIMM 0 RttNom: 5
755209.598: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
755309.598: DIMM 1 RttNom: 5
755409.598: DIMM 0 RttWr: 2
755509.598: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
755609.598: DIMM 1 RttWr: 2
755709.598: DIMM 0 RttNom: 5
755809.598: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
755909.598: DIMM 1 RttNom: 5
756009.598: DIMM 0 RttWr: 2
756109.598: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
756209.598: DIMM 1 RttWr: 2
756309.598: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
756409.598: <09>Lane 00 new seed: 005d
756509.598: <09>Lane 01 new seed: 0059
756609.598: <09>Lane 02 new seed: 0055
756709.598: <09>Lane 03 new seed: 0053
756809.598: <09>Lane 04 new seed: 0045
756909.598: <09>Lane 05 new seed: 0049
757009.598: <09>Lane 06 new seed: 004d
757109.598: <09>Lane 07 new seed: 004f
757209.598: <09>Lane 08 new seed: 0049
757309.598: <09>Lane 00 nibble 1 raw readback: 005d
757409.598: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
757509.598: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
757609.598: <09>Lane 01 nibble 1 raw readback: 0058
757709.598: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
757809.598: <09>Lane 01 nibble 1 adjusted value (post nibble): 0058
757909.598: <09>Lane 02 nibble 1 raw readback: 0051
758009.598: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
758109.598: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
758209.598: <09>Lane 03 nibble 1 raw readback: 004f
758309.598: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
758409.598: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
758509.598: <09>Lane 04 nibble 1 raw readback: 003c
758609.598: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003c
758709.598: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
758809.598: <09>Lane 05 nibble 1 raw readback: 0043
758909.598: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0043
759009.598: <09>Lane 05 nibble 1 adjusted value (post nibble): 0046
759109.598: <09>Lane 06 nibble 1 raw readback: 0048
759209.598: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0048
759309.598: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
759409.598: <09>Lane 07 nibble 1 raw readback: 004c
759509.598: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
759609.598: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
759709.598: <09>Lane 08 nibble 1 raw readback: 0041
759809.598: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
759909.598: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
760009.598: <09>original critical gross delay: 0
760109.598: <09>new critical gross delay: 0
760209.599: DIMM 1 RttNom: 5
760309.599: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
760409.599: DIMM 1 RttNom: 5
760509.599: DIMM 1 RttWr: 2
760609.599: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
760709.599: DIMM 1 RttWr: 2
760809.599: DIMM 1 RttNom: 5
760909.599: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
761009.599: DIMM 1 RttNom: 5
761109.599: DIMM 1 RttWr: 2
761209.599: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
761309.599: DIMM 1 RttWr: 2
761409.599: DIMM 0 RttNom: 5
761509.599: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
761609.599: DIMM 1 RttNom: 5
761709.599: DIMM 0 RttWr: 2
761809.599: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
761909.599: DIMM 1 RttWr: 2
762009.599: DIMM 0 RttNom: 5
762109.599: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
762209.599: DIMM 1 RttNom: 5
762309.599: DIMM 0 RttWr: 2
762409.599: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
762509.599: DIMM 1 RttWr: 2
762609.599: SetTargetFreq: Start
762709.599: SetTargetFreq: Node 0: New frequency code: 0012
762809.599: ChangeMemClk: Start
762909.599: set_2t_configuration: Start
763009.599: set_2t_configuration: Done
763109.599: mct_BeforePlatformSpec: Start
763209.599: mct_BeforePlatformSpec: Done
763309.599: mct_PlatformSpec: Start
763409.599: Programmed DCT 0 timing/termination pattern 00353935 30222222
763509.599: mct_PlatformSpec: Done
763609.599: set_2t_configuration: Start
763709.600: set_2t_configuration: Done
763809.599: mct_BeforePlatformSpec: Start
763909.600: mct_BeforePlatformSpec: Done
764009.600: mct_PlatformSpec: Start
764109.600: Programmed DCT 1 timing/termination pattern 00353935 30222222
764209.600: mct_PlatformSpec: Done
764309.600: ChangeMemClk: Done
764409.600: phyAssistedMemFnceTraining: Start
764509.600: phyAssistedMemFnceTraining: training node 0 DCT 0
764609.600: phyAssistedMemFnceTraining: done training node 0 DCT 0
764709.600: phyAssistedMemFnceTraining: training node 0 DCT 1
764809.600: phyAssistedMemFnceTraining: done training node 0 DCT 1
764909.600: phyAssistedMemFnceTraining: Done
765009.600: InitPhyCompensation: DCT 0: Start
765109.600: Waiting for predriver calibration to be applied...done!
765209.600: InitPhyCompensation: DCT 0: Done
765309.600: phyAssistedMemFnceTraining: Start
765409.600: phyAssistedMemFnceTraining: training node 0 DCT 0
765509.600: phyAssistedMemFnceTraining: done training node 0 DCT 0
765609.600: phyAssistedMemFnceTraining: training node 0 DCT 1
765709.600: phyAssistedMemFnceTraining: done training node 0 DCT 1
765809.600: phyAssistedMemFnceTraining: Done
765909.600: InitPhyCompensation: DCT 1: Start
766009.600: Waiting for predriver calibration to be applied...done!
766109.600: InitPhyCompensation: DCT 1: Done
766209.600: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
766309.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
766409.601: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
766509.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
766609.601: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
766709.601: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
766809.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
766909.601: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
767009.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
767109.601: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
767209.601: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
767309.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
767409.601: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
767509.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
767609.601: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
767709.601: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
767809.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
767909.601: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
768009.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
768109.601: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
768209.601: SetTargetFreq: Done
768309.601: SPD2ndTiming: Start
768409.601: SPD2ndTiming: Done
768509.601: mct_BeforeDramInit_Prod_D: Start
768609.601: mct_ProgramODT_D: Start
768709.601: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
768809.601: mct_ProgramODT_D: Done
768909.601: mct_BeforeDramInit_Prod_D: Done
769009.601: mct_DramInit_Sw_D: Start
769109.601: DIMM 0 RttWr: 1
769209.601: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
769309.602: mct_SendMrsCmd: Start
769409.601: mct_SendMrsCmd: Done
769509.601: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
769609.601: mct_SendMrsCmd: Start
769709.601: mct_SendMrsCmd: Done
769809.602: DIMM 0 RttNom: 4
769909.602: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
770009.602: mct_SendMrsCmd: Start
770109.602: mct_SendMrsCmd: Done
770209.602: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
770309.602: mct_SendMrsCmd: Start
770409.602: mct_SendMrsCmd: Done
770509.602: DIMM 0 RttWr: 1
770609.602: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
770709.602: mct_SendMrsCmd: Start
770809.602: mct_SendMrsCmd: Done
770909.602: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
771009.602: mct_SendMrsCmd: Start
771109.602: mct_SendMrsCmd: Done
771209.602: DIMM 0 RttNom: 4
771309.602: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
771409.602: mct_SendMrsCmd: Start
771509.602: mct_SendMrsCmd: Done
771609.602: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
771709.602: mct_SendMrsCmd: Start
771809.602: mct_SendMrsCmd: Done
771909.602: DIMM 1 RttWr: 1
772009.602: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
772109.602: mct_SendMrsCmd: Start
772209.602: mct_SendMrsCmd: Done
772309.602: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
772409.602: mct_SendMrsCmd: Start
772509.602: mct_SendMrsCmd: Done
772609.602: DIMM 1 RttNom: 4
772709.602: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
772809.602: mct_SendMrsCmd: Start
772909.602: mct_SendMrsCmd: Done
773009.602: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
773109.602: mct_SendMrsCmd: Start
773209.602: mct_SendMrsCmd: Done
773309.602: DIMM 1 RttWr: 1
773409.602: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
773509.602: mct_SendMrsCmd: Start
773609.602: mct_SendMrsCmd: Done
773709.602: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
773809.602: mct_SendMrsCmd: Start
773909.602: mct_SendMrsCmd: Done
774009.602: DIMM 1 RttNom: 4
774109.602: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
774209.602: mct_SendMrsCmd: Start
774309.602: mct_SendMrsCmd: Done
774409.602: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
774509.602: mct_SendMrsCmd: Start
774609.602: mct_SendMrsCmd: Done
774709.602: mct_DramInit_Sw_D: Done
774809.603: AgesaHwWlPhase1: training nibble 0
774909.603: DIMM 0 RttNom: 4
775009.603: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
775109.603: DIMM 0 RttWr: 1
775209.603: DIMM 0 RttWr: 1
775309.603: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
775409.603: DIMM 0 RttWr: 1
775509.603: DIMM 0 RttNom: 4
775609.603: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
775709.603: DIMM 0 RttNom: 4
775809.603: DIMM 0 RttWr: 1
775909.603: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
776009.603: DIMM 0 RttWr: 1
776109.603: DIMM 1 RttNom: 4
776209.603: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
776309.603: DIMM 0 RttNom: 4
776409.603: DIMM 1 RttWr: 1
776509.603: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
776609.603: DIMM 0 RttWr: 1
776709.603: DIMM 1 RttNom: 4
776809.603: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
776909.603: DIMM 0 RttNom: 4
777009.603: DIMM 1 RttWr: 1
777109.603: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
777209.603: DIMM 0 RttWr: 1
777309.603: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
777409.603: <09>Lane 00 scaled delay: 007b
777509.603: <09>Lane 00 new seed: 007b
777609.603: <09>Lane 01 scaled delay: 0071
777709.603: <09>Lane 01 new seed: 0071
777809.603: <09>Lane 02 scaled delay: 006d
777909.603: <09>Lane 02 new seed: 006d
778009.603: <09>Lane 03 scaled delay: 0069
778109.603: <09>Lane 03 new seed: 0069
778209.603: <09>Lane 04 scaled delay: 0054
778309.603: <09>Lane 04 new seed: 0054
778409.603: <09>Lane 05 scaled delay: 005d
778509.603: <09>Lane 05 new seed: 005d
778609.603: <09>Lane 06 scaled delay: 0063
778709.603: <09>Lane 06 new seed: 0063
778809.603: <09>Lane 07 scaled delay: 0065
778909.603: <09>Lane 07 new seed: 0065
779009.603: <09>Lane 08 scaled delay: 0059
779109.603: <09>Lane 08 new seed: 0059
779209.603: <09>Lane 00 nibble 0 raw readback: 0042
779309.604: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0082
779409.604: <09>Lane 00 nibble 0 adjusted value (post nibble): 0082
779509.604: <09>Lane 01 nibble 0 raw readback: 0036
779609.604: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0076
779709.604: <09>Lane 01 nibble 0 adjusted value (post nibble): 0076
779809.604: <09>Lane 02 nibble 0 raw readback: 0031
779909.604: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0071
780009.604: <09>Lane 02 nibble 0 adjusted value (post nibble): 0071
780109.604: <09>Lane 03 nibble 0 raw readback: 002a
780209.604: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
780309.604: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
780409.604: <09>Lane 04 nibble 0 raw readback: 0056
780509.604: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
780609.604: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
780709.604: <09>Lane 05 nibble 0 raw readback: 005f
780809.604: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005f
780909.604: <09>Lane 05 nibble 0 adjusted value (post nibble): 005f
781009.604: <09>Lane 06 nibble 0 raw readback: 0025
781109.604: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
781209.604: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
781309.604: <09>Lane 07 nibble 0 raw readback: 0029
781409.604: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
781509.604: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
781609.604: <09>Lane 08 nibble 0 raw readback: 005b
781709.604: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005b
781809.604: <09>Lane 08 nibble 0 adjusted value (post nibble): 005b
781909.604: AgesaHwWlPhase1: training nibble 1
782009.604: DIMM 0 RttNom: 4
782109.604: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
782209.604: DIMM 0 RttWr: 1
782309.604: DIMM 0 RttWr: 1
782409.604: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
782509.604: DIMM 0 RttWr: 1
782609.604: DIMM 0 RttNom: 4
782709.604: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
782809.604: DIMM 0 RttNom: 4
782909.604: DIMM 0 RttWr: 1
783009.604: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
783109.604: DIMM 0 RttWr: 1
783209.604: DIMM 1 RttNom: 4
783309.604: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
783409.604: DIMM 0 RttNom: 4
783509.604: DIMM 1 RttWr: 1
783609.604: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
783709.604: DIMM 0 RttWr: 1
783809.604: DIMM 1 RttNom: 4
783909.604: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
784009.604: DIMM 0 RttNom: 4
784109.604: DIMM 1 RttWr: 1
784209.604: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
784309.604: DIMM 0 RttWr: 1
784409.604: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
784509.604: <09>Lane 00 new seed: 007b
784609.604: <09>Lane 01 new seed: 0071
784709.604: <09>Lane 02 new seed: 006d
784809.604: <09>Lane 03 new seed: 0069
784909.604: <09>Lane 04 new seed: 0054
785009.604: <09>Lane 05 new seed: 005d
785109.604: <09>Lane 06 new seed: 0063
785209.604: <09>Lane 07 new seed: 0065
785309.604: <09>Lane 08 new seed: 0059
785409.604: <09>Lane 00 nibble 1 raw readback: 0040
785509.604: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0080
785609.604: <09>Lane 00 nibble 1 adjusted value (post nibble): 007d
785709.604: <09>Lane 01 nibble 1 raw readback: 0036
785809.604: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0076
785909.604: <09>Lane 01 nibble 1 adjusted value (post nibble): 0073
786009.604: <09>Lane 02 nibble 1 raw readback: 0032
786109.604: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
786209.605: <09>Lane 02 nibble 1 adjusted value (post nibble): 006f
786309.605: <09>Lane 03 nibble 1 raw readback: 002c
786409.605: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
786509.605: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
786609.605: <09>Lane 04 nibble 1 raw readback: 0056
786709.605: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
786809.605: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
786909.605: <09>Lane 05 nibble 1 raw readback: 0060
787009.605: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0060
787109.605: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
787209.605: <09>Lane 06 nibble 1 raw readback: 0025
787309.605: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0065
787409.605: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
787509.605: <09>Lane 07 nibble 1 raw readback: 0028
787609.605: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
787709.605: <09>Lane 07 nibble 1 adjusted value (post nibble): 0066
787809.605: <09>Lane 08 nibble 1 raw readback: 005c
787909.605: <09>Lane 08 nibble 1 adjusted value (pre nibble): 005c
788009.605: <09>Lane 08 nibble 1 adjusted value (post nibble): 005a
788109.605: <09>original critical gross delay: 0
788209.605: <09>new critical gross delay: 0
788309.605: DIMM 0 RttNom: 4
788409.605: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
788509.605: DIMM 0 RttNom: 4
788609.605: DIMM 0 RttWr: 1
788709.605: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
788809.605: DIMM 0 RttWr: 1
788909.605: DIMM 0 RttNom: 4
789009.605: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
789109.605: DIMM 0 RttNom: 4
789209.605: DIMM 0 RttWr: 1
789309.605: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
789409.605: DIMM 0 RttWr: 1
789509.605: DIMM 1 RttNom: 4
789609.605: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
789709.605: DIMM 0 RttNom: 4
789809.605: DIMM 1 RttWr: 1
789909.605: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
790009.605: DIMM 0 RttWr: 1
790109.605: DIMM 1 RttNom: 4
790209.605: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
790309.605: DIMM 0 RttNom: 4
790409.605: DIMM 1 RttWr: 1
790509.605: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
790609.605: DIMM 0 RttWr: 1
790709.605: AgesaHwWlPhase1: training nibble 0
790809.605: DIMM 1 RttNom: 4
790909.605: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
791009.605: DIMM 1 RttWr: 1
791109.605: DIMM 1 RttWr: 1
791209.605: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
791309.605: DIMM 1 RttWr: 1
791409.605: DIMM 1 RttNom: 4
791509.605: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
791609.605: DIMM 1 RttNom: 4
791709.605: DIMM 1 RttWr: 1
791809.605: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
791909.605: DIMM 1 RttWr: 1
792009.605: DIMM 0 RttNom: 4
792109.605: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
792209.605: DIMM 1 RttNom: 4
792309.605: DIMM 0 RttWr: 1
792409.605: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
792509.605: DIMM 1 RttWr: 1
792609.606: DIMM 0 RttNom: 4
792709.606: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
792809.606: DIMM 1 RttNom: 4
792909.606: DIMM 0 RttWr: 1
793009.606: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
793109.606: DIMM 1 RttWr: 1
793209.606: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
793309.606: <09>Lane 00 scaled delay: 006b
793409.606: <09>Lane 00 new seed: 006b
793509.606: <09>Lane 01 scaled delay: 0061
793609.606: <09>Lane 01 new seed: 0061
793709.606: <09>Lane 02 scaled delay: 005f
793809.606: <09>Lane 02 new seed: 005f
793909.606: <09>Lane 03 scaled delay: 0059
794009.606: <09>Lane 03 new seed: 0059
794109.606: <09>Lane 04 scaled delay: 0045
794209.606: <09>Lane 04 new seed: 0045
794309.606: <09>Lane 05 scaled delay: 004e
794409.606: <09>Lane 05 new seed: 004e
794509.606: <09>Lane 06 scaled delay: 0052
794609.606: <09>Lane 06 new seed: 0052
794709.606: <09>Lane 07 scaled delay: 0058
794809.606: <09>Lane 07 new seed: 0058
794909.606: <09>Lane 08 scaled delay: 0048
795009.606: <09>Lane 08 new seed: 0048
795109.606: <09>Lane 00 nibble 0 raw readback: 0031
795209.606: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0071
795309.606: <09>Lane 00 nibble 0 adjusted value (post nibble): 0071
795409.606: <09>Lane 01 nibble 0 raw readback: 0026
795509.606: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
795609.606: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
795709.606: <09>Lane 02 nibble 0 raw readback: 0061
795809.606: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
795909.606: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
796009.606: <09>Lane 03 nibble 0 raw readback: 005b
796109.606: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
796209.606: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
796309.606: <09>Lane 04 nibble 0 raw readback: 0048
796409.606: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0048
796509.606: <09>Lane 04 nibble 0 adjusted value (post nibble): 0048
796609.606: <09>Lane 05 nibble 0 raw readback: 0051
796709.606: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
796809.606: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
796909.606: <09>Lane 06 nibble 0 raw readback: 0055
797009.606: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
797109.606: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
797209.606: <09>Lane 07 nibble 0 raw readback: 005a
797309.606: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
797409.606: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
797509.606: <09>Lane 08 nibble 0 raw readback: 004b
797609.606: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
797709.606: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
797809.606: AgesaHwWlPhase1: training nibble 1
797909.606: DIMM 1 RttNom: 4
798009.606: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
798109.606: DIMM 1 RttWr: 1
798209.606: DIMM 1 RttWr: 1
798309.606: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
798409.606: DIMM 1 RttWr: 1
798509.606: DIMM 1 RttNom: 4
798609.606: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
798709.606: DIMM 1 RttNom: 4
798809.606: DIMM 1 RttWr: 1
798909.606: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
799009.606: DIMM 1 RttWr: 1
799109.606: DIMM 0 RttNom: 4
799209.606: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
799309.606: DIMM 1 RttNom: 4
799409.606: DIMM 0 RttWr: 1
799509.606: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
799609.606: DIMM 1 RttWr: 1
799709.606: DIMM 0 RttNom: 4
799809.606: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
799909.606: DIMM 1 RttNom: 4
800009.606: DIMM 0 RttWr: 1
800109.606: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
800209.606: DIMM 1 RttWr: 1
800309.606: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
800409.606: <09>Lane 00 new seed: 006b
800509.606: <09>Lane 01 new seed: 0061
800609.607: <09>Lane 02 new seed: 005f
800709.607: <09>Lane 03 new seed: 0059
800809.607: <09>Lane 04 new seed: 0045
800909.607: <09>Lane 05 new seed: 004e
801009.607: <09>Lane 06 new seed: 0052
801109.607: <09>Lane 07 new seed: 0058
801209.607: <09>Lane 08 new seed: 0048
801309.607: <09>Lane 00 nibble 1 raw readback: 0031
801409.607: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0071
801509.607: <09>Lane 00 nibble 1 adjusted value (post nibble): 006e
801609.607: <09>Lane 01 nibble 1 raw readback: 0027
801709.607: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
801809.607: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
801909.607: <09>Lane 02 nibble 1 raw readback: 0063
802009.607: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0063
802109.607: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
802209.607: <09>Lane 03 nibble 1 raw readback: 005c
802309.607: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
802409.607: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
802509.607: <09>Lane 04 nibble 1 raw readback: 0047
802609.607: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0047
802709.607: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
802809.607: <09>Lane 05 nibble 1 raw readback: 0050
802909.607: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
803009.607: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
803109.607: <09>Lane 06 nibble 1 raw readback: 0055
803209.607: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
803309.607: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
803409.607: <09>Lane 07 nibble 1 raw readback: 005b
803509.607: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
803609.607: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
803709.607: <09>Lane 08 nibble 1 raw readback: 004a
803809.607: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
803909.607: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
804009.607: <09>original critical gross delay: 0
804109.607: <09>new critical gross delay: 0
804209.607: DIMM 1 RttNom: 4
804309.607: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
804409.607: DIMM 1 RttNom: 4
804509.607: DIMM 1 RttWr: 1
804609.607: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
804709.607: DIMM 1 RttWr: 1
804809.607: DIMM 1 RttNom: 4
804909.607: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
805009.607: DIMM 1 RttNom: 4
805109.607: DIMM 1 RttWr: 1
805209.607: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
805309.607: DIMM 1 RttWr: 1
805409.607: DIMM 0 RttNom: 4
805509.607: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
805609.607: DIMM 1 RttNom: 4
805709.607: DIMM 0 RttWr: 1
805809.607: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
805909.607: DIMM 1 RttWr: 1
806009.607: DIMM 0 RttNom: 4
806109.607: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
806209.607: DIMM 1 RttNom: 4
806309.607: DIMM 0 RttWr: 1
806409.607: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
806509.607: DIMM 1 RttWr: 1
806609.607: SPD2ndTiming: Start
806709.608: SPD2ndTiming: Done
806809.608: mct_BeforeDramInit_Prod_D: Start
806909.608: mct_ProgramODT_D: Start
807009.608: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
807109.608: mct_ProgramODT_D: Done
807209.608: mct_BeforeDramInit_Prod_D: Done
807309.608: mct_DramInit_Sw_D: Start
807409.608: DIMM 0 RttWr: 1
807509.608: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
807609.608: mct_SendMrsCmd: Start
807709.608: mct_SendMrsCmd: Done
807809.608: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
807909.608: mct_SendMrsCmd: Start
808009.608: mct_SendMrsCmd: Done
808109.608: DIMM 0 RttNom: 4
808209.608: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
808309.608: mct_SendMrsCmd: Start
808409.608: mct_SendMrsCmd: Done
808509.608: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
808609.608: mct_SendMrsCmd: Start
808709.608: mct_SendMrsCmd: Done
808809.608: DIMM 0 RttWr: 1
808909.608: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
809009.608: mct_SendMrsCmd: Start
809109.608: mct_SendMrsCmd: Done
809209.608: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
809309.608: mct_SendMrsCmd: Start
809409.608: mct_SendMrsCmd: Done
809509.608: DIMM 0 RttNom: 4
809609.608: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
809709.608: mct_SendMrsCmd: Start
809809.608: mct_SendMrsCmd: Done
809909.608: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
810009.608: mct_SendMrsCmd: Start
810109.608: mct_SendMrsCmd: Done
810209.608: DIMM 1 RttWr: 1
810309.608: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
810409.608: mct_SendMrsCmd: Start
810509.608: mct_SendMrsCmd: Done
810609.608: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
810709.608: mct_SendMrsCmd: Start
810809.608: mct_SendMrsCmd: Done
810909.609: DIMM 1 RttNom: 4
811009.609: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
811109.609: mct_SendMrsCmd: Start
811209.609: mct_SendMrsCmd: Done
811309.609: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
811409.609: mct_SendMrsCmd: Start
811509.609: mct_SendMrsCmd: Done
811609.609: DIMM 1 RttWr: 1
811709.609: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
811809.609: mct_SendMrsCmd: Start
811909.609: mct_SendMrsCmd: Done
812009.609: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
812109.609: mct_SendMrsCmd: Start
812209.609: mct_SendMrsCmd: Done
812309.609: DIMM 1 RttNom: 4
812409.609: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
812509.609: mct_SendMrsCmd: Start
812609.609: mct_SendMrsCmd: Done
812709.609: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
812809.609: mct_SendMrsCmd: Start
812909.609: mct_SendMrsCmd: Done
813009.609: mct_DramInit_Sw_D: Done
813109.609: AgesaHwWlPhase1: training nibble 0
813209.609: DIMM 0 RttNom: 4
813309.609: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
813409.609: DIMM 0 RttWr: 1
813509.609: DIMM 0 RttWr: 1
813609.609: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
813709.609: DIMM 0 RttWr: 1
813809.609: DIMM 0 RttNom: 4
813909.609: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
814009.609: DIMM 0 RttNom: 4
814109.609: DIMM 0 RttWr: 1
814209.609: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
814309.609: DIMM 0 RttWr: 1
814409.609: DIMM 1 RttNom: 4
814509.609: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
814609.609: DIMM 0 RttNom: 4
814709.609: DIMM 1 RttWr: 1
814809.609: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
814909.609: DIMM 0 RttWr: 1
815009.609: DIMM 1 RttNom: 4
815109.609: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
815209.609: DIMM 0 RttNom: 4
815309.609: DIMM 1 RttWr: 1
815409.609: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
815509.609: DIMM 0 RttWr: 1
815609.609: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
815709.609: <09>Lane 00 scaled delay: 0077
815809.609: <09>Lane 00 new seed: 0077
815909.609: <09>Lane 01 scaled delay: 0070
816009.609: <09>Lane 01 new seed: 0070
816109.609: <09>Lane 02 scaled delay: 006c
816209.609: <09>Lane 02 new seed: 006c
816309.610: <09>Lane 03 scaled delay: 0067
816409.609: <09>Lane 03 new seed: 0067
816509.609: <09>Lane 04 scaled delay: 0054
816609.609: <09>Lane 04 new seed: 0054
816709.609: <09>Lane 05 scaled delay: 0059
816809.610: <09>Lane 05 new seed: 0059
816909.610: <09>Lane 06 scaled delay: 005f
817009.610: <09>Lane 06 new seed: 005f
817109.610: <09>Lane 07 scaled delay: 0063
817209.610: <09>Lane 07 new seed: 0063
817309.610: <09>Lane 08 scaled delay: 0058
817409.610: <09>Lane 08 new seed: 0058
817509.610: <09>Lane 00 nibble 0 raw readback: 003d
817609.610: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007d
817709.610: <09>Lane 00 nibble 0 adjusted value (post nibble): 007d
817809.610: <09>Lane 01 nibble 0 raw readback: 0037
817909.610: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0077
818009.610: <09>Lane 01 nibble 0 adjusted value (post nibble): 0077
818109.610: <09>Lane 02 nibble 0 raw readback: 002e
818209.610: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006e
818309.610: <09>Lane 02 nibble 0 adjusted value (post nibble): 006e
818409.610: <09>Lane 03 nibble 0 raw readback: 0029
818509.610: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0069
818609.610: <09>Lane 03 nibble 0 adjusted value (post nibble): 0069
818709.610: <09>Lane 04 nibble 0 raw readback: 0056
818809.610: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
818909.610: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
819009.610: <09>Lane 05 nibble 0 raw readback: 005d
819109.610: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
819209.610: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
819309.610: <09>Lane 06 nibble 0 raw readback: 0060
819409.610: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0060
819509.610: <09>Lane 06 nibble 0 adjusted value (post nibble): 0060
819609.610: <09>Lane 07 nibble 0 raw readback: 0025
819709.610: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0065
819809.610: <09>Lane 07 nibble 0 adjusted value (post nibble): 0065
819909.610: <09>Lane 08 nibble 0 raw readback: 0059
820009.610: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0059
820109.610: <09>Lane 08 nibble 0 adjusted value (post nibble): 0059
820209.610: AgesaHwWlPhase1: training nibble 1
820309.610: DIMM 0 RttNom: 4
820409.610: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
820509.610: DIMM 0 RttWr: 1
820609.610: DIMM 0 RttWr: 1
820709.610: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
820809.610: DIMM 0 RttWr: 1
820909.610: DIMM 0 RttNom: 4
821009.610: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
821109.610: DIMM 0 RttNom: 4
821209.610: DIMM 0 RttWr: 1
821309.610: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
821409.610: DIMM 0 RttWr: 1
821509.610: DIMM 1 RttNom: 4
821609.610: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
821709.610: DIMM 0 RttNom: 4
821809.610: DIMM 1 RttWr: 1
821909.610: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
822009.610: DIMM 0 RttWr: 1
822109.610: DIMM 1 RttNom: 4
822209.610: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
822309.610: DIMM 0 RttNom: 4
822409.610: DIMM 1 RttWr: 1
822509.610: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
822609.610: DIMM 0 RttWr: 1
822709.610: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
822809.610: <09>Lane 00 new seed: 0077
822909.610: <09>Lane 01 new seed: 0070
823009.610: <09>Lane 02 new seed: 006c
823109.611: <09>Lane 03 new seed: 0067
823209.611: <09>Lane 04 new seed: 0054
823309.611: <09>Lane 05 new seed: 0059
823409.611: <09>Lane 06 new seed: 005f
823509.611: <09>Lane 07 new seed: 0063
823609.611: <09>Lane 08 new seed: 0058
823709.611: <09>Lane 00 nibble 1 raw readback: 003d
823809.611: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007d
823909.611: <09>Lane 00 nibble 1 adjusted value (post nibble): 007a
824009.611: <09>Lane 01 nibble 1 raw readback: 0035
824109.611: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0075
824209.611: <09>Lane 01 nibble 1 adjusted value (post nibble): 0072
824309.611: <09>Lane 02 nibble 1 raw readback: 0030
824409.611: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0070
824509.611: <09>Lane 02 nibble 1 adjusted value (post nibble): 006e
824609.611: <09>Lane 03 nibble 1 raw readback: 0029
824709.611: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0069
824809.611: <09>Lane 03 nibble 1 adjusted value (post nibble): 0068
824909.611: <09>Lane 04 nibble 1 raw readback: 0054
825009.611: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
825109.611: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
825209.611: <09>Lane 05 nibble 1 raw readback: 005b
825309.611: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005b
825409.611: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
825509.611: <09>Lane 06 nibble 1 raw readback: 0062
825609.611: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0062
825709.611: <09>Lane 06 nibble 1 adjusted value (post nibble): 0060
825809.611: <09>Lane 07 nibble 1 raw readback: 0026
825909.611: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
826009.611: <09>Lane 07 nibble 1 adjusted value (post nibble): 0064
826109.611: <09>Lane 08 nibble 1 raw readback: 0059
826209.611: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
826309.611: <09>Lane 08 nibble 1 adjusted value (post nibble): 0058
826409.611: <09>original critical gross delay: 0
826509.611: <09>new critical gross delay: 0
826609.611: DIMM 0 RttNom: 4
826709.611: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
826809.611: DIMM 0 RttNom: 4
826909.611: DIMM 0 RttWr: 1
827009.611: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
827109.611: DIMM 0 RttWr: 1
827209.611: DIMM 0 RttNom: 4
827309.611: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
827409.611: DIMM 0 RttNom: 4
827509.611: DIMM 0 RttWr: 1
827609.611: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
827709.611: DIMM 0 RttWr: 1
827809.611: DIMM 1 RttNom: 4
827909.611: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
828009.611: DIMM 0 RttNom: 4
828109.611: DIMM 1 RttWr: 1
828209.611: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
828309.611: DIMM 0 RttWr: 1
828409.611: DIMM 1 RttNom: 4
828509.611: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
828609.611: DIMM 0 RttNom: 4
828709.611: DIMM 1 RttWr: 1
828809.611: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
828909.611: DIMM 0 RttWr: 1
829009.611: AgesaHwWlPhase1: training nibble 0
829109.611: DIMM 1 RttNom: 4
829209.611: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
829309.611: DIMM 1 RttWr: 1
829409.611: DIMM 1 RttWr: 1
829509.611: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
829609.611: DIMM 1 RttWr: 1
829709.611: DIMM 1 RttNom: 4
829809.611: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
829909.611: DIMM 1 RttNom: 4
830009.611: DIMM 1 RttWr: 1
830109.612: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
830209.612: DIMM 1 RttWr: 1
830309.612: DIMM 0 RttNom: 4
830409.612: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
830509.612: DIMM 1 RttNom: 4
830609.612: DIMM 0 RttWr: 1
830709.612: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
830809.612: DIMM 1 RttWr: 1
830909.612: DIMM 0 RttNom: 4
831009.612: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
831109.612: DIMM 1 RttNom: 4
831209.612: DIMM 0 RttWr: 1
831309.612: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
831409.612: DIMM 1 RttWr: 1
831509.612: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
831609.612: <09>Lane 00 scaled delay: 0069
831709.612: <09>Lane 00 new seed: 0069
831809.612: <09>Lane 01 scaled delay: 0063
831909.612: <09>Lane 01 new seed: 0063
832009.612: <09>Lane 02 scaled delay: 005d
832109.612: <09>Lane 02 new seed: 005d
832209.612: <09>Lane 03 scaled delay: 005a
832309.612: <09>Lane 03 new seed: 005a
832409.612: <09>Lane 04 scaled delay: 0046
832509.612: <09>Lane 04 new seed: 0046
832609.612: <09>Lane 05 scaled delay: 004d
832709.612: <09>Lane 05 new seed: 004d
832809.612: <09>Lane 06 scaled delay: 0052
832909.612: <09>Lane 06 new seed: 0052
833009.612: <09>Lane 07 scaled delay: 0055
833109.612: <09>Lane 07 new seed: 0055
833209.612: <09>Lane 08 scaled delay: 004c
833309.612: <09>Lane 08 new seed: 004c
833409.612: <09>Lane 00 nibble 0 raw readback: 002e
833509.612: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
833609.612: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
833709.612: <09>Lane 01 nibble 0 raw readback: 0029
833809.612: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0069
833909.612: <09>Lane 01 nibble 0 adjusted value (post nibble): 0069
834009.612: <09>Lane 02 nibble 0 raw readback: 005f
834109.612: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
834209.612: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
834309.612: <09>Lane 03 nibble 0 raw readback: 005a
834409.612: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005a
834509.612: <09>Lane 03 nibble 0 adjusted value (post nibble): 005a
834609.612: <09>Lane 04 nibble 0 raw readback: 0047
834709.612: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0047
834809.612: <09>Lane 04 nibble 0 adjusted value (post nibble): 0047
834909.612: <09>Lane 05 nibble 0 raw readback: 004c
835009.612: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004c
835109.612: <09>Lane 05 nibble 0 adjusted value (post nibble): 004c
835209.612: <09>Lane 06 nibble 0 raw readback: 0053
835309.612: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0053
835409.612: <09>Lane 06 nibble 0 adjusted value (post nibble): 0053
835509.612: <09>Lane 07 nibble 0 raw readback: 0058
835609.612: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
835709.612: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
835809.612: <09>Lane 08 nibble 0 raw readback: 004a
835909.612: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
836009.612: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
836109.612: AgesaHwWlPhase1: training nibble 1
836209.612: DIMM 1 RttNom: 4
836309.612: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
836409.612: DIMM 1 RttWr: 1
836509.612: DIMM 1 RttWr: 1
836609.612: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
836709.612: DIMM 1 RttWr: 1
836809.612: DIMM 1 RttNom: 4
836909.612: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
837009.613: DIMM 1 RttNom: 4
837109.612: DIMM 1 RttWr: 1
837209.612: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
837309.612: DIMM 1 RttWr: 1
837409.612: DIMM 0 RttNom: 4
837509.612: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
837609.612: DIMM 1 RttNom: 4
837709.613: DIMM 0 RttWr: 1
837809.613: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
837909.613: DIMM 1 RttWr: 1
838009.613: DIMM 0 RttNom: 4
838109.613: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
838209.613: DIMM 1 RttNom: 4
838309.613: DIMM 0 RttWr: 1
838409.613: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
838509.613: DIMM 1 RttWr: 1
838609.613: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
838709.613: <09>Lane 00 new seed: 0069
838809.613: <09>Lane 01 new seed: 0063
838909.613: <09>Lane 02 new seed: 005d
839009.613: <09>Lane 03 new seed: 005a
839109.613: <09>Lane 04 new seed: 0046
839209.613: <09>Lane 05 new seed: 004d
839309.613: <09>Lane 06 new seed: 0052
839409.613: <09>Lane 07 new seed: 0055
839509.613: <09>Lane 08 new seed: 004c
839609.613: <09>Lane 00 nibble 1 raw readback: 002e
839709.613: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
839809.613: <09>Lane 00 nibble 1 adjusted value (post nibble): 006b
839909.613: <09>Lane 01 nibble 1 raw readback: 0027
840009.613: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
840109.613: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
840209.613: <09>Lane 02 nibble 1 raw readback: 0060
840309.613: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0060
840409.613: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
840509.613: <09>Lane 03 nibble 1 raw readback: 005c
840609.613: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
840709.613: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
840809.613: <09>Lane 04 nibble 1 raw readback: 0046
840909.613: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
841009.613: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
841109.613: <09>Lane 05 nibble 1 raw readback: 004f
841209.613: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
841309.613: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
841409.613: <09>Lane 06 nibble 1 raw readback: 0053
841509.613: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0053
841609.613: <09>Lane 06 nibble 1 adjusted value (post nibble): 0052
841709.613: <09>Lane 07 nibble 1 raw readback: 0057
841809.613: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
841909.613: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
842009.613: <09>Lane 08 nibble 1 raw readback: 004d
842109.613: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004d
842209.613: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
842309.613: <09>original critical gross delay: 0
842409.613: <09>new critical gross delay: 0
842509.613: DIMM 1 RttNom: 4
842609.613: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
842709.613: DIMM 1 RttNom: 4
842809.613: DIMM 1 RttWr: 1
842909.613: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
843009.613: DIMM 1 RttWr: 1
843109.613: DIMM 1 RttNom: 4
843209.613: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
843309.613: DIMM 1 RttNom: 4
843409.613: DIMM 1 RttWr: 1
843509.613: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
843609.613: DIMM 1 RttWr: 1
843709.613: DIMM 0 RttNom: 4
843809.613: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
843909.613: DIMM 1 RttNom: 4
844009.613: DIMM 0 RttWr: 1
844109.613: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
844209.613: DIMM 1 RttWr: 1
844309.613: DIMM 0 RttNom: 4
844409.613: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
844509.613: DIMM 1 RttNom: 4
844609.614: DIMM 0 RttWr: 1
844709.614: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
844809.614: DIMM 1 RttWr: 1
844909.614: activate_spd_rom() for node 01
845009.614: enable_spd_node1()
845109.614: SetTargetFreq: Start
845209.614: SetTargetFreq: Node 1: New frequency code: 0006
845309.614: ChangeMemClk: Start
845409.614: set_2t_configuration: Start
845509.614: set_2t_configuration: Done
845609.614: mct_BeforePlatformSpec: Start
845709.614: mct_BeforePlatformSpec: Done
845809.614: mct_PlatformSpec: Start
845909.614: Programmed DCT 0 timing/termination pattern 00000000 20222222
846009.614: mct_PlatformSpec: Done
846109.614: set_2t_configuration: Start
846209.615: set_2t_configuration: Done
846309.615: mct_BeforePlatformSpec: Start
846409.615: mct_BeforePlatformSpec: Done
846509.615: mct_PlatformSpec: Start
846609.615: Programmed DCT 1 timing/termination pattern 00000000 20222222
846709.615: mct_PlatformSpec: Done
846809.615: ChangeMemClk: Done
846909.615: phyAssistedMemFnceTraining: Start
847009.615: phyAssistedMemFnceTraining: training node 1 DCT 0
847109.615: phyAssistedMemFnceTraining: done training node 1 DCT 0
847209.615: phyAssistedMemFnceTraining: training node 1 DCT 1
847309.615: phyAssistedMemFnceTraining: done training node 1 DCT 1
847409.615: phyAssistedMemFnceTraining: Done
847509.615: InitPhyCompensation: DCT 0: Start
847609.615: Waiting for predriver calibration to be applied...done!
847709.615: InitPhyCompensation: DCT 0: Done
847809.615: phyAssistedMemFnceTraining: Start
847909.615: phyAssistedMemFnceTraining: training node 1 DCT 0
848009.615: phyAssistedMemFnceTraining: done training node 1 DCT 0
848109.615: phyAssistedMemFnceTraining: training node 1 DCT 1
848209.615: phyAssistedMemFnceTraining: done training node 1 DCT 1
848309.615: phyAssistedMemFnceTraining: Done
848409.615: InitPhyCompensation: DCT 1: Start
848509.615: Waiting for predriver calibration to be applied...done!
848609.615: InitPhyCompensation: DCT 1: Done
848709.616: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
848809.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
848909.616: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
849009.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
849109.616: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
849209.616: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
849309.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
849409.616: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
849509.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
849609.616: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
849709.616: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
849809.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
849909.616: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
850009.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
850109.616: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
850209.616: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
850309.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
850409.616: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
850509.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
850609.616: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
850709.616: SetTargetFreq: Done
850809.616: SPD2ndTiming: Start
850909.617: SPD2ndTiming: Done
851009.617: mct_BeforeDramInit_Prod_D: Start
851109.617: mct_ProgramODT_D: Start
851209.617: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
851309.617: mct_ProgramODT_D: Done
851409.617: mct_BeforeDramInit_Prod_D: Done
851509.617: mct_DramInit_Sw_D: Start
851609.617: DIMM 0 RttWr: 2
851709.617: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
851809.617: mct_SendMrsCmd: Start
851909.617: mct_SendMrsCmd: Done
852009.617: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
852109.617: mct_SendMrsCmd: Start
852209.617: mct_SendMrsCmd: Done
852309.617: DIMM 0 RttNom: 3
852409.617: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
852509.617: mct_SendMrsCmd: Start
852609.617: mct_SendMrsCmd: Done
852709.617: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
852809.617: mct_SendMrsCmd: Start
852909.617: mct_SendMrsCmd: Done
853009.617: DIMM 0 RttWr: 2
853109.617: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
853209.617: mct_SendMrsCmd: Start
853309.617: mct_SendMrsCmd: Done
853409.617: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
853509.617: mct_SendMrsCmd: Start
853609.617: mct_SendMrsCmd: Done
853709.617: DIMM 0 RttNom: 3
853809.617: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
853909.617: mct_SendMrsCmd: Start
854009.617: mct_SendMrsCmd: Done
854109.617: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
854209.617: mct_SendMrsCmd: Start
854309.617: mct_SendMrsCmd: Done
854409.617: DIMM 1 RttWr: 2
854509.617: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
854609.617: mct_SendMrsCmd: Start
854709.617: mct_SendMrsCmd: Done
854809.617: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
854909.617: mct_SendMrsCmd: Start
855009.617: mct_SendMrsCmd: Done
855109.617: DIMM 1 RttNom: 3
855209.617: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
855309.617: mct_SendMrsCmd: Start
855409.617: mct_SendMrsCmd: Done
855509.617: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
855609.617: mct_SendMrsCmd: Start
855709.617: mct_SendMrsCmd: Done
855809.617: DIMM 1 RttWr: 2
855909.617: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
856009.617: mct_SendMrsCmd: Start
856109.617: mct_SendMrsCmd: Done
856209.617: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
856309.617: mct_SendMrsCmd: Start
856409.617: mct_SendMrsCmd: Done
856509.617: DIMM 1 RttNom: 3
856609.617: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
856709.617: mct_SendMrsCmd: Start
856809.617: mct_SendMrsCmd: Done
856909.617: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
857009.617: mct_SendMrsCmd: Start
857109.617: mct_SendMrsCmd: Done
857209.617: mct_DramInit_Sw_D: Done
857309.618: AgesaHwWlPhase1: training nibble 0
857409.618: DIMM 0 RttNom: 3
857509.618: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
857609.618: DIMM 0 RttWr: 2
857709.618: DIMM 0 RttWr: 2
857809.618: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
857909.618: DIMM 0 RttWr: 2
858009.618: DIMM 0 RttNom: 3
858109.618: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
858209.618: DIMM 0 RttNom: 3
858309.618: DIMM 0 RttWr: 2
858409.618: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
858509.618: DIMM 0 RttWr: 2
858609.618: DIMM 1 RttNom: 3
858709.618: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
858809.618: DIMM 0 RttNom: 3
858909.618: DIMM 1 RttWr: 2
859009.618: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
859109.618: DIMM 0 RttWr: 2
859209.618: DIMM 1 RttNom: 3
859309.618: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
859409.618: DIMM 0 RttNom: 3
859509.618: DIMM 1 RttWr: 2
859609.618: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
859709.618: DIMM 0 RttWr: 2
859809.618: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
859909.618: <09>Lane 00 scaled delay: 0047
860009.618: <09>Lane 00 new seed: 0047
860109.618: <09>Lane 01 scaled delay: 0047
860209.618: <09>Lane 01 new seed: 0047
860309.618: <09>Lane 02 scaled delay: 0047
860409.618: <09>Lane 02 new seed: 0047
860509.618: <09>Lane 03 scaled delay: 0047
860609.618: <09>Lane 03 new seed: 0047
860709.618: <09>Lane 04 scaled delay: 0047
860809.618: <09>Lane 04 new seed: 0047
860909.618: <09>Lane 05 scaled delay: 0047
861009.618: <09>Lane 05 new seed: 0047
861109.618: <09>Lane 06 scaled delay: 0047
861209.618: <09>Lane 06 new seed: 0047
861309.618: <09>Lane 07 scaled delay: 0047
861409.619: <09>Lane 07 new seed: 0047
861509.619: <09>Lane 08 scaled delay: 0047
861609.619: <09>Lane 08 new seed: 0047
861709.619: <09>Lane 00 nibble 0 raw readback: 003f
861809.619: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
861909.619: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
862009.619: <09>Lane 01 nibble 0 raw readback: 003c
862109.619: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
862209.619: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
862309.619: <09>Lane 02 nibble 0 raw readback: 0038
862409.619: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
862509.619: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
862609.619: <09>Lane 03 nibble 0 raw readback: 0036
862709.619: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
862809.619: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
862909.619: <09>Lane 04 nibble 0 raw readback: 0034
863009.619: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0034
863109.619: <09>Lane 04 nibble 0 adjusted value (post nibble): 0034
863209.619: <09>Lane 05 nibble 0 raw readback: 0036
863309.619: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0036
863409.619: <09>Lane 05 nibble 0 adjusted value (post nibble): 0036
863509.619: <09>Lane 06 nibble 0 raw readback: 0039
863609.619: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0039
863709.619: <09>Lane 06 nibble 0 adjusted value (post nibble): 0039
863809.619: <09>Lane 07 nibble 0 raw readback: 003d
863909.619: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003d
864009.619: <09>Lane 07 nibble 0 adjusted value (post nibble): 003d
864109.619: <09>Lane 08 nibble 0 raw readback: 0031
864209.619: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0031
864309.619: <09>Lane 08 nibble 0 adjusted value (post nibble): 0031
864409.619: AgesaHwWlPhase1: training nibble 1
864509.619: DIMM 0 RttNom: 3
864609.619: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
864709.619: DIMM 0 RttWr: 2
864809.619: DIMM 0 RttWr: 2
864909.619: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
865009.619: DIMM 0 RttWr: 2
865109.619: DIMM 0 RttNom: 3
865209.619: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
865309.619: DIMM 0 RttNom: 3
865409.619: DIMM 0 RttWr: 2
865509.619: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
865609.619: DIMM 0 RttWr: 2
865709.619: DIMM 1 RttNom: 3
865809.619: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
865909.619: DIMM 0 RttNom: 3
866009.619: DIMM 1 RttWr: 2
866109.619: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
866209.619: DIMM 0 RttWr: 2
866309.619: DIMM 1 RttNom: 3
866409.619: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
866509.619: DIMM 0 RttNom: 3
866609.619: DIMM 1 RttWr: 2
866709.619: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
866809.619: DIMM 0 RttWr: 2
866909.619: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
867009.619: <09>Lane 00 new seed: 0047
867109.620: <09>Lane 01 new seed: 0047
867209.620: <09>Lane 02 new seed: 0047
867309.620: <09>Lane 03 new seed: 0047
867409.620: <09>Lane 04 new seed: 0047
867509.620: <09>Lane 05 new seed: 0047
867609.620: <09>Lane 06 new seed: 0047
867709.620: <09>Lane 07 new seed: 0047
867809.620: <09>Lane 08 new seed: 0047
867909.620: <09>Lane 00 nibble 1 raw readback: 003f
868009.620: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
868109.620: <09>Lane 00 nibble 1 adjusted value (post nibble): 0043
868209.620: <09>Lane 01 nibble 1 raw readback: 003c
868309.620: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
868409.620: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
868509.620: <09>Lane 02 nibble 1 raw readback: 0038
868609.620: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0038
868709.620: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
868809.620: <09>Lane 03 nibble 1 raw readback: 0037
868909.620: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
869009.620: <09>Lane 03 nibble 1 adjusted value (post nibble): 003f
869109.620: <09>Lane 04 nibble 1 raw readback: 0032
869209.620: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0032
869309.620: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
869409.620: <09>Lane 05 nibble 1 raw readback: 0036
869509.620: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0036
869609.620: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
869709.620: <09>Lane 06 nibble 1 raw readback: 0039
869809.620: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0039
869909.620: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
870009.620: <09>Lane 07 nibble 1 raw readback: 003d
870109.620: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003d
870209.620: <09>Lane 07 nibble 1 adjusted value (post nibble): 0042
870309.620: <09>Lane 08 nibble 1 raw readback: 0031
870409.620: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
870509.620: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
870609.620: <09>original critical gross delay: 0
870709.620: <09>new critical gross delay: 0
870809.620: DIMM 0 RttNom: 3
870909.620: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
871009.620: DIMM 0 RttNom: 3
871109.620: DIMM 0 RttWr: 2
871209.620: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
871309.620: DIMM 0 RttWr: 2
871409.620: DIMM 0 RttNom: 3
871509.620: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
871609.620: DIMM 0 RttNom: 3
871709.620: DIMM 0 RttWr: 2
871809.620: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
871909.620: DIMM 0 RttWr: 2
872009.620: DIMM 1 RttNom: 3
872109.620: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
872209.620: DIMM 0 RttNom: 3
872309.620: DIMM 1 RttWr: 2
872409.620: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
872509.620: DIMM 0 RttWr: 2
872609.620: DIMM 1 RttNom: 3
872709.620: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
872809.620: DIMM 0 RttNom: 3
872909.620: DIMM 1 RttWr: 2
873009.620: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
873109.620: DIMM 0 RttWr: 2
873209.621: AgesaHwWlPhase1: training nibble 0
873309.621: DIMM 1 RttNom: 3
873409.621: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
873509.621: DIMM 1 RttWr: 2
873609.621: DIMM 1 RttWr: 2
873709.621: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
873809.621: DIMM 1 RttWr: 2
873909.621: DIMM 1 RttNom: 3
874009.621: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
874109.621: DIMM 1 RttNom: 3
874209.621: DIMM 1 RttWr: 2
874309.621: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
874409.621: DIMM 1 RttWr: 2
874509.621: DIMM 0 RttNom: 3
874609.621: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
874709.621: DIMM 1 RttNom: 3
874809.621: DIMM 0 RttWr: 2
874909.621: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
875009.621: DIMM 1 RttWr: 2
875109.621: DIMM 0 RttNom: 3
875209.621: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
875309.621: DIMM 1 RttNom: 3
875409.621: DIMM 0 RttWr: 2
875509.621: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
875609.621: DIMM 1 RttWr: 2
875709.621: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
875809.621: <09>Lane 00 scaled delay: 0047
875909.621: <09>Lane 00 new seed: 0047
876009.621: <09>Lane 01 scaled delay: 0047
876109.621: <09>Lane 01 new seed: 0047
876209.621: <09>Lane 02 scaled delay: 0047
876309.621: <09>Lane 02 new seed: 0047
876409.621: <09>Lane 03 scaled delay: 0047
876509.621: <09>Lane 03 new seed: 0047
876609.621: <09>Lane 04 scaled delay: 0047
876709.621: <09>Lane 04 new seed: 0047
876809.621: <09>Lane 05 scaled delay: 0047
876909.621: <09>Lane 05 new seed: 0047
877009.621: <09>Lane 06 scaled delay: 0047
877109.621: <09>Lane 06 new seed: 0047
877209.621: <09>Lane 07 scaled delay: 0047
877309.621: <09>Lane 07 new seed: 0047
877409.621: <09>Lane 08 scaled delay: 0047
877509.621: <09>Lane 08 new seed: 0047
877609.621: <09>Lane 00 nibble 0 raw readback: 0045
877709.621: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
877809.621: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
877909.621: <09>Lane 01 nibble 0 raw readback: 0040
878009.621: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
878109.621: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
878209.621: <09>Lane 02 nibble 0 raw readback: 003b
878309.621: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
878409.621: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
878509.621: <09>Lane 03 nibble 0 raw readback: 003b
878609.621: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
878709.621: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
878809.621: <09>Lane 04 nibble 0 raw readback: 0039
878909.621: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
879009.621: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
879109.621: <09>Lane 05 nibble 0 raw readback: 003d
879209.621: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
879309.621: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
879409.621: <09>Lane 06 nibble 0 raw readback: 003d
879509.621: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
879609.621: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
879709.621: <09>Lane 07 nibble 0 raw readback: 0042
879809.621: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
879909.621: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
880009.621: <09>Lane 08 nibble 0 raw readback: 0036
880109.621: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
880209.621: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
880309.621: AgesaHwWlPhase1: training nibble 1
880409.622: DIMM 1 RttNom: 3
880509.622: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
880609.622: DIMM 1 RttWr: 2
880709.622: DIMM 1 RttWr: 2
880809.622: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
880909.622: DIMM 1 RttWr: 2
881009.622: DIMM 1 RttNom: 3
881109.622: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
881209.622: DIMM 1 RttNom: 3
881309.622: DIMM 1 RttWr: 2
881409.622: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
881509.622: DIMM 1 RttWr: 2
881609.622: DIMM 0 RttNom: 3
881709.622: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
881809.622: DIMM 1 RttNom: 3
881909.622: DIMM 0 RttWr: 2
882009.622: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
882109.622: DIMM 1 RttWr: 2
882209.622: DIMM 0 RttNom: 3
882309.622: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
882409.622: DIMM 1 RttNom: 3
882509.622: DIMM 0 RttWr: 2
882609.622: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
882709.622: DIMM 1 RttWr: 2
882809.622: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
882909.622: <09>Lane 00 new seed: 0047
883009.622: <09>Lane 01 new seed: 0047
883109.622: <09>Lane 02 new seed: 0047
883209.622: <09>Lane 03 new seed: 0047
883309.622: <09>Lane 04 new seed: 0047
883409.622: <09>Lane 05 new seed: 0047
883509.622: <09>Lane 06 new seed: 0047
883609.622: <09>Lane 07 new seed: 0047
883709.622: <09>Lane 08 new seed: 0047
883809.622: <09>Lane 00 nibble 1 raw readback: 0045
883909.622: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
884009.622: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
884109.622: <09>Lane 01 nibble 1 raw readback: 003f
884209.622: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
884309.622: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
884409.622: <09>Lane 02 nibble 1 raw readback: 003c
884509.622: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
884609.622: <09>Lane 02 nibble 1 adjusted value (post nibble): 0041
884709.622: <09>Lane 03 nibble 1 raw readback: 003b
884809.622: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
884909.622: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
885009.622: <09>Lane 04 nibble 1 raw readback: 0037
885109.622: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
885209.622: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
885309.622: <09>Lane 05 nibble 1 raw readback: 003b
885409.622: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
885509.622: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
885609.622: <09>Lane 06 nibble 1 raw readback: 003e
885709.622: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
885809.622: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
885909.622: <09>Lane 07 nibble 1 raw readback: 0041
886009.622: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
886109.622: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
886209.622: <09>Lane 08 nibble 1 raw readback: 0037
886309.622: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
886409.622: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
886509.622: <09>original critical gross delay: 0
886609.622: <09>new critical gross delay: 0
886709.623: DIMM 1 RttNom: 3
886809.623: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
886909.623: DIMM 1 RttNom: 3
887009.623: DIMM 1 RttWr: 2
887109.623: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
887209.623: DIMM 1 RttWr: 2
887309.623: DIMM 1 RttNom: 3
887409.623: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
887509.623: DIMM 1 RttNom: 3
887609.623: DIMM 1 RttWr: 2
887709.623: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
887809.623: DIMM 1 RttWr: 2
887909.623: DIMM 0 RttNom: 3
888009.623: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
888109.623: DIMM 1 RttNom: 3
888209.623: DIMM 0 RttWr: 2
888309.623: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
888409.623: DIMM 1 RttWr: 2
888509.623: DIMM 0 RttNom: 3
888609.623: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
888709.623: DIMM 1 RttNom: 3
888809.623: DIMM 0 RttWr: 2
888909.623: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
889009.623: DIMM 1 RttWr: 2
889109.623: SPD2ndTiming: Start
889209.623: SPD2ndTiming: Done
889309.623: mct_BeforeDramInit_Prod_D: Start
889409.623: mct_ProgramODT_D: Start
889509.623: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
889609.623: mct_ProgramODT_D: Done
889709.623: mct_BeforeDramInit_Prod_D: Done
889809.623: mct_DramInit_Sw_D: Start
889909.624: DIMM 0 RttWr: 2
890009.624: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
890109.624: mct_SendMrsCmd: Start
890209.624: mct_SendMrsCmd: Done
890309.624: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
890409.624: mct_SendMrsCmd: Start
890509.624: mct_SendMrsCmd: Done
890609.624: DIMM 0 RttNom: 3
890709.624: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
890809.624: mct_SendMrsCmd: Start
890909.624: mct_SendMrsCmd: Done
891009.624: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
891109.624: mct_SendMrsCmd: Start
891209.624: mct_SendMrsCmd: Done
891309.624: DIMM 0 RttWr: 2
891409.624: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
891509.624: mct_SendMrsCmd: Start
891609.624: mct_SendMrsCmd: Done
891709.624: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
891809.624: mct_SendMrsCmd: Start
891909.624: mct_SendMrsCmd: Done
892009.624: DIMM 0 RttNom: 3
892109.624: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
892209.624: mct_SendMrsCmd: Start
892309.624: mct_SendMrsCmd: Done
892409.624: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
892509.624: mct_SendMrsCmd: Start
892609.624: mct_SendMrsCmd: Done
892709.624: DIMM 1 RttWr: 2
892809.624: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
892909.624: mct_SendMrsCmd: Start
893009.624: mct_SendMrsCmd: Done
893109.624: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
893209.624: mct_SendMrsCmd: Start
893309.624: mct_SendMrsCmd: Done
893409.624: DIMM 1 RttNom: 3
893509.624: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
893609.624: mct_SendMrsCmd: Start
893709.624: mct_SendMrsCmd: Done
893809.624: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
893909.624: mct_SendMrsCmd: Start
894009.624: mct_SendMrsCmd: Done
894109.624: DIMM 1 RttWr: 2
894209.624: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
894309.624: mct_SendMrsCmd: Start
894409.624: mct_SendMrsCmd: Done
894509.624: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
894609.624: mct_SendMrsCmd: Start
894709.624: mct_SendMrsCmd: Done
894809.624: DIMM 1 RttNom: 3
894909.624: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
895009.624: mct_SendMrsCmd: Start
895109.624: mct_SendMrsCmd: Done
895209.624: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
895309.624: mct_SendMrsCmd: Start
895409.624: mct_SendMrsCmd: Done
895509.624: mct_DramInit_Sw_D: Done
895609.624: AgesaHwWlPhase1: training nibble 0
895709.624: DIMM 0 RttNom: 3
895809.624: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
895909.624: DIMM 0 RttWr: 2
896009.624: DIMM 0 RttWr: 2
896109.624: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
896209.624: DIMM 0 RttWr: 2
896309.624: DIMM 0 RttNom: 3
896409.624: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
896509.624: DIMM 0 RttNom: 3
896609.624: DIMM 0 RttWr: 2
896709.624: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
896809.624: DIMM 0 RttWr: 2
896909.625: DIMM 1 RttNom: 3
897009.625: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
897109.625: DIMM 0 RttNom: 3
897209.625: DIMM 1 RttWr: 2
897309.625: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
897409.625: DIMM 0 RttWr: 2
897509.625: DIMM 1 RttNom: 3
897609.625: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
897709.625: DIMM 0 RttNom: 3
897809.625: DIMM 1 RttWr: 2
897909.625: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
898009.625: DIMM 0 RttWr: 2
898109.625: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
898209.625: <09>Lane 00 scaled delay: 0047
898309.625: <09>Lane 00 new seed: 0047
898409.625: <09>Lane 01 scaled delay: 0047
898509.625: <09>Lane 01 new seed: 0047
898609.625: <09>Lane 02 scaled delay: 0047
898709.625: <09>Lane 02 new seed: 0047
898809.625: <09>Lane 03 scaled delay: 0047
898909.625: <09>Lane 03 new seed: 0047
899009.625: <09>Lane 04 scaled delay: 0047
899109.625: <09>Lane 04 new seed: 0047
899209.625: <09>Lane 05 scaled delay: 0047
899309.625: <09>Lane 05 new seed: 0047
899409.625: <09>Lane 06 scaled delay: 0047
899509.625: <09>Lane 06 new seed: 0047
899609.625: <09>Lane 07 scaled delay: 0047
899709.625: <09>Lane 07 new seed: 0047
899809.625: <09>Lane 08 scaled delay: 0047
899909.625: <09>Lane 08 new seed: 0047
900009.625: <09>Lane 00 nibble 0 raw readback: 0041
900109.625: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0041
900209.625: <09>Lane 00 nibble 0 adjusted value (post nibble): 0041
900309.625: <09>Lane 01 nibble 0 raw readback: 003d
900409.625: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003d
900509.625: <09>Lane 01 nibble 0 adjusted value (post nibble): 003d
900609.625: <09>Lane 02 nibble 0 raw readback: 0039
900709.625: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
900809.625: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
900909.625: <09>Lane 03 nibble 0 raw readback: 0036
901009.625: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
901109.625: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
901209.625: <09>Lane 04 nibble 0 raw readback: 0034
901309.625: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0034
901409.625: <09>Lane 04 nibble 0 adjusted value (post nibble): 0034
901509.625: <09>Lane 05 nibble 0 raw readback: 0038
901609.625: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0038
901709.625: <09>Lane 05 nibble 0 adjusted value (post nibble): 0038
901809.625: <09>Lane 06 nibble 0 raw readback: 003a
901909.625: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003a
902009.625: <09>Lane 06 nibble 0 adjusted value (post nibble): 003a
902109.625: <09>Lane 07 nibble 0 raw readback: 003f
902209.625: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
902309.625: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
902409.625: <09>Lane 08 nibble 0 raw readback: 0032
902509.625: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
902609.625: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
902709.625: AgesaHwWlPhase1: training nibble 1
902809.625: DIMM 0 RttNom: 3
902909.625: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
903009.625: DIMM 0 RttWr: 2
903109.626: DIMM 0 RttWr: 2
903209.626: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
903309.626: DIMM 0 RttWr: 2
903409.626: DIMM 0 RttNom: 3
903509.626: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
903609.626: DIMM 0 RttNom: 3
903709.626: DIMM 0 RttWr: 2
903809.626: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
903909.626: DIMM 0 RttWr: 2
904009.626: DIMM 1 RttNom: 3
904109.626: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
904209.626: DIMM 0 RttNom: 3
904309.626: DIMM 1 RttWr: 2
904409.626: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
904509.626: DIMM 0 RttWr: 2
904609.626: DIMM 1 RttNom: 3
904709.626: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
904809.626: DIMM 0 RttNom: 3
904909.626: DIMM 1 RttWr: 2
905009.626: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
905109.626: DIMM 0 RttWr: 2
905209.626: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
905309.626: <09>Lane 00 new seed: 0047
905409.626: <09>Lane 01 new seed: 0047
905509.626: <09>Lane 02 new seed: 0047
905609.626: <09>Lane 03 new seed: 0047
905709.626: <09>Lane 04 new seed: 0047
905809.626: <09>Lane 05 new seed: 0047
905909.626: <09>Lane 06 new seed: 0047
906009.626: <09>Lane 07 new seed: 0047
906109.626: <09>Lane 08 new seed: 0047
906209.626: <09>Lane 00 nibble 1 raw readback: 0041
906309.626: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0041
906409.626: <09>Lane 00 nibble 1 adjusted value (post nibble): 0044
906509.626: <09>Lane 01 nibble 1 raw readback: 003d
906609.626: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003d
906709.626: <09>Lane 01 nibble 1 adjusted value (post nibble): 0042
906809.626: <09>Lane 02 nibble 1 raw readback: 0039
906909.626: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
907009.626: <09>Lane 02 nibble 1 adjusted value (post nibble): 0040
907109.626: <09>Lane 03 nibble 1 raw readback: 0036
907209.626: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
907309.626: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
907409.626: <09>Lane 04 nibble 1 raw readback: 0033
907509.626: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0033
907609.626: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
907709.626: <09>Lane 05 nibble 1 raw readback: 0038
907809.626: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0038
907909.626: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
908009.626: <09>Lane 06 nibble 1 raw readback: 003b
908109.626: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003b
908209.626: <09>Lane 06 nibble 1 adjusted value (post nibble): 0041
908309.626: <09>Lane 07 nibble 1 raw readback: 003f
908409.626: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
908509.626: <09>Lane 07 nibble 1 adjusted value (post nibble): 0043
908609.626: <09>Lane 08 nibble 1 raw readback: 0031
908709.626: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
908809.626: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
908909.626: <09>original critical gross delay: 0
909009.626: <09>new critical gross delay: 0
909109.626: DIMM 0 RttNom: 3
909209.627: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
909309.627: DIMM 0 RttNom: 3
909409.627: DIMM 0 RttWr: 2
909509.627: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
909609.627: DIMM 0 RttWr: 2
909709.627: DIMM 0 RttNom: 3
909809.627: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
909909.627: DIMM 0 RttNom: 3
910009.627: DIMM 0 RttWr: 2
910109.627: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
910209.627: DIMM 0 RttWr: 2
910309.627: DIMM 1 RttNom: 3
910409.627: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
910509.627: DIMM 0 RttNom: 3
910609.627: DIMM 1 RttWr: 2
910709.627: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
910809.627: DIMM 0 RttWr: 2
910909.627: DIMM 1 RttNom: 3
911009.627: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
911109.627: DIMM 0 RttNom: 3
911209.627: DIMM 1 RttWr: 2
911309.627: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
911409.627: DIMM 0 RttWr: 2
911509.627: AgesaHwWlPhase1: training nibble 0
911609.627: DIMM 1 RttNom: 3
911709.627: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
911809.627: DIMM 1 RttWr: 2
911909.627: DIMM 1 RttWr: 2
912009.627: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
912109.627: DIMM 1 RttWr: 2
912209.627: DIMM 1 RttNom: 3
912309.627: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
912409.627: DIMM 1 RttNom: 3
912509.627: DIMM 1 RttWr: 2
912609.627: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
912709.627: DIMM 1 RttWr: 2
912809.627: DIMM 0 RttNom: 3
912909.627: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
913009.627: DIMM 1 RttNom: 3
913109.627: DIMM 0 RttWr: 2
913209.627: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
913309.627: DIMM 1 RttWr: 2
913409.627: DIMM 0 RttNom: 3
913509.627: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
913609.627: DIMM 1 RttNom: 3
913709.627: DIMM 0 RttWr: 2
913809.627: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
913909.627: DIMM 1 RttWr: 2
914009.627: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
914109.627: <09>Lane 00 scaled delay: 0047
914209.627: <09>Lane 00 new seed: 0047
914309.627: <09>Lane 01 scaled delay: 0047
914409.627: <09>Lane 01 new seed: 0047
914509.627: <09>Lane 02 scaled delay: 0047
914609.627: <09>Lane 02 new seed: 0047
914709.627: <09>Lane 03 scaled delay: 0047
914809.627: <09>Lane 03 new seed: 0047
914909.627: <09>Lane 04 scaled delay: 0047
915009.627: <09>Lane 04 new seed: 0047
915109.627: <09>Lane 05 scaled delay: 0047
915209.627: <09>Lane 05 new seed: 0047
915309.627: <09>Lane 06 scaled delay: 0047
915409.627: <09>Lane 06 new seed: 0047
915509.627: <09>Lane 07 scaled delay: 0047
915609.627: <09>Lane 07 new seed: 0047
915709.628: <09>Lane 08 scaled delay: 0047
915809.628: <09>Lane 08 new seed: 0047
915909.628: <09>Lane 00 nibble 0 raw readback: 0044
916009.628: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
916109.628: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
916209.628: <09>Lane 01 nibble 0 raw readback: 0042
916309.628: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
916409.628: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
916509.628: <09>Lane 02 nibble 0 raw readback: 003e
916609.628: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
916709.628: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
916809.628: <09>Lane 03 nibble 0 raw readback: 003a
916909.628: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
917009.628: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
917109.628: <09>Lane 04 nibble 0 raw readback: 0039
917209.628: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
917309.628: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
917409.628: <09>Lane 05 nibble 0 raw readback: 003c
917509.628: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
917609.628: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
917709.628: <09>Lane 06 nibble 0 raw readback: 0040
917809.628: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
917909.628: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
918009.628: <09>Lane 07 nibble 0 raw readback: 0043
918109.628: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
918209.628: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
918309.628: <09>Lane 08 nibble 0 raw readback: 0036
918409.628: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
918509.628: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
918609.628: AgesaHwWlPhase1: training nibble 1
918709.628: DIMM 1 RttNom: 3
918809.628: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
918909.628: DIMM 1 RttWr: 2
919009.628: DIMM 1 RttWr: 2
919109.628: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
919209.628: DIMM 1 RttWr: 2
919309.628: DIMM 1 RttNom: 3
919409.628: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
919509.628: DIMM 1 RttNom: 3
919609.628: DIMM 1 RttWr: 2
919709.628: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
919809.628: DIMM 1 RttWr: 2
919909.628: DIMM 0 RttNom: 3
920009.628: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
920109.628: DIMM 1 RttNom: 3
920209.628: DIMM 0 RttWr: 2
920309.628: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
920409.628: DIMM 1 RttWr: 2
920509.628: DIMM 0 RttNom: 3
920609.628: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
920709.628: DIMM 1 RttNom: 3
920809.628: DIMM 0 RttWr: 2
920909.628: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
921009.628: DIMM 1 RttWr: 2
921109.628: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
921209.628: <09>Lane 00 new seed: 0047
921309.628: <09>Lane 01 new seed: 0047
921409.628: <09>Lane 02 new seed: 0047
921509.628: <09>Lane 03 new seed: 0047
921609.628: <09>Lane 04 new seed: 0047
921709.628: <09>Lane 05 new seed: 0047
921809.628: <09>Lane 06 new seed: 0047
921909.628: <09>Lane 07 new seed: 0047
922009.628: <09>Lane 08 new seed: 0047
922109.628: <09>Lane 00 nibble 1 raw readback: 0047
922209.628: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
922309.628: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
922409.628: <09>Lane 01 nibble 1 raw readback: 0042
922509.628: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
922609.628: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
922709.628: <09>Lane 02 nibble 1 raw readback: 003e
922809.628: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
922909.628: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
923009.629: <09>Lane 03 nibble 1 raw readback: 003b
923109.629: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
923209.629: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
923309.629: <09>Lane 04 nibble 1 raw readback: 0038
923409.629: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
923509.629: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
923609.629: <09>Lane 05 nibble 1 raw readback: 003b
923709.629: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
923809.629: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
923909.629: <09>Lane 06 nibble 1 raw readback: 003f
924009.629: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
924109.629: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
924209.629: <09>Lane 07 nibble 1 raw readback: 0045
924309.629: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
924409.629: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
924509.629: <09>Lane 08 nibble 1 raw readback: 0037
924609.629: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
924709.629: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
924809.629: <09>original critical gross delay: 0
924909.629: <09>new critical gross delay: 0
925009.629: DIMM 1 RttNom: 3
925109.629: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
925209.629: DIMM 1 RttNom: 3
925309.629: DIMM 1 RttWr: 2
925409.629: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
925509.629: DIMM 1 RttWr: 2
925609.629: DIMM 1 RttNom: 3
925709.629: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
925809.629: DIMM 1 RttNom: 3
925909.629: DIMM 1 RttWr: 2
926009.629: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
926109.629: DIMM 1 RttWr: 2
926209.629: DIMM 0 RttNom: 3
926309.629: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
926409.629: DIMM 1 RttNom: 3
926509.629: DIMM 0 RttWr: 2
926609.629: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
926709.629: DIMM 1 RttWr: 2
926809.629: DIMM 0 RttNom: 3
926909.629: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
927009.629: DIMM 1 RttNom: 3
927109.629: DIMM 0 RttWr: 2
927209.629: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
927309.629: DIMM 1 RttWr: 2
927409.629: SetTargetFreq: Start
927509.629: SetTargetFreq: Node 1: New frequency code: 000a
927609.629: ChangeMemClk: Start
927709.630: set_2t_configuration: Start
927809.630: set_2t_configuration: Done
927909.630: mct_BeforePlatformSpec: Start
928009.630: mct_BeforePlatformSpec: Done
928109.630: mct_PlatformSpec: Start
928209.630: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
928309.630: mct_PlatformSpec: Done
928409.630: set_2t_configuration: Start
928509.630: set_2t_configuration: Done
928609.630: mct_BeforePlatformSpec: Start
928709.630: mct_BeforePlatformSpec: Done
928809.630: mct_PlatformSpec: Start
928909.630: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
929009.630: mct_PlatformSpec: Done
929109.630: ChangeMemClk: Done
929209.630: phyAssistedMemFnceTraining: Start
929309.630: phyAssistedMemFnceTraining: training node 1 DCT 0
929409.630: phyAssistedMemFnceTraining: done training node 1 DCT 0
929509.630: phyAssistedMemFnceTraining: training node 1 DCT 1
929609.630: phyAssistedMemFnceTraining: done training node 1 DCT 1
929709.630: phyAssistedMemFnceTraining: Done
929809.630: InitPhyCompensation: DCT 0: Start
929909.630: Waiting for predriver calibration to be applied...done!
930009.630: InitPhyCompensation: DCT 0: Done
930109.630: phyAssistedMemFnceTraining: Start
930209.630: phyAssistedMemFnceTraining: training node 1 DCT 0
930309.630: phyAssistedMemFnceTraining: done training node 1 DCT 0
930409.630: phyAssistedMemFnceTraining: training node 1 DCT 1
930509.631: phyAssistedMemFnceTraining: done training node 1 DCT 1
930609.631: phyAssistedMemFnceTraining: Done
930709.631: InitPhyCompensation: DCT 1: Start
930809.631: Waiting for predriver calibration to be applied...done!
930909.631: InitPhyCompensation: DCT 1: Done
931009.631: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
931109.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
931209.631: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
931309.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
931409.631: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
931509.631: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
931609.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
931709.631: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
931809.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
931909.631: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
932009.631: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
932109.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
932209.631: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
932309.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
932409.631: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
932509.631: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
932609.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
932709.631: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
932809.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
932909.631: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
933009.631: SetTargetFreq: Done
933109.631: SPD2ndTiming: Start
933209.632: SPD2ndTiming: Done
933309.632: mct_BeforeDramInit_Prod_D: Start
933409.632: mct_ProgramODT_D: Start
933509.632: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
933609.632: mct_ProgramODT_D: Done
933709.632: mct_BeforeDramInit_Prod_D: Done
933809.632: mct_DramInit_Sw_D: Start
933909.632: DIMM 0 RttWr: 1
934009.632: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
934109.632: mct_SendMrsCmd: Start
934209.632: mct_SendMrsCmd: Done
934309.632: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
934409.632: mct_SendMrsCmd: Start
934509.632: mct_SendMrsCmd: Done
934609.632: DIMM 0 RttNom: 3
934709.632: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
934809.632: mct_SendMrsCmd: Start
934909.632: mct_SendMrsCmd: Done
935009.632: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
935109.632: mct_SendMrsCmd: Start
935209.632: mct_SendMrsCmd: Done
935309.632: DIMM 0 RttWr: 1
935409.632: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
935509.632: mct_SendMrsCmd: Start
935609.632: mct_SendMrsCmd: Done
935709.632: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
935809.632: mct_SendMrsCmd: Start
935909.632: mct_SendMrsCmd: Done
936009.632: DIMM 0 RttNom: 3
936109.632: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
936209.632: mct_SendMrsCmd: Start
936309.632: mct_SendMrsCmd: Done
936409.632: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
936509.632: mct_SendMrsCmd: Start
936609.632: mct_SendMrsCmd: Done
936709.632: DIMM 1 RttWr: 1
936809.632: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
936909.632: mct_SendMrsCmd: Start
937009.632: mct_SendMrsCmd: Done
937109.632: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
937209.632: mct_SendMrsCmd: Start
937309.632: mct_SendMrsCmd: Done
937409.632: DIMM 1 RttNom: 3
937509.632: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
937609.632: mct_SendMrsCmd: Start
937709.632: mct_SendMrsCmd: Done
937809.632: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
937909.632: mct_SendMrsCmd: Start
938009.632: mct_SendMrsCmd: Done
938109.632: DIMM 1 RttWr: 1
938209.632: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
938309.633: mct_SendMrsCmd: Start
938409.632: mct_SendMrsCmd: Done
938509.632: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
938609.632: mct_SendMrsCmd: Start
938709.633: mct_SendMrsCmd: Done
938809.633: DIMM 1 RttNom: 3
938909.633: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
939009.633: mct_SendMrsCmd: Start
939109.633: mct_SendMrsCmd: Done
939209.633: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
939309.633: mct_SendMrsCmd: Start
939409.633: mct_SendMrsCmd: Done
939509.633: mct_DramInit_Sw_D: Done
939609.633: AgesaHwWlPhase1: training nibble 0
939709.633: DIMM 0 RttNom: 3
939809.633: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
939909.633: DIMM 0 RttWr: 1
940009.633: DIMM 0 RttWr: 1
940109.633: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
940209.633: DIMM 0 RttWr: 1
940309.633: DIMM 0 RttNom: 3
940409.633: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
940509.633: DIMM 0 RttNom: 3
940609.633: DIMM 0 RttWr: 1
940709.633: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
940809.633: DIMM 0 RttWr: 1
940909.633: DIMM 1 RttNom: 3
941009.633: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
941109.633: DIMM 0 RttNom: 3
941209.633: DIMM 1 RttWr: 1
941309.633: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
941409.633: DIMM 0 RttWr: 1
941509.633: DIMM 1 RttNom: 3
941609.633: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
941709.633: DIMM 0 RttNom: 3
941809.633: DIMM 1 RttWr: 1
941909.633: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
942009.633: DIMM 0 RttWr: 1
942109.633: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
942209.633: <09>Lane 00 scaled delay: 004e
942309.633: <09>Lane 00 new seed: 004e
942409.633: <09>Lane 01 scaled delay: 004b
942509.633: <09>Lane 01 new seed: 004b
942609.633: <09>Lane 02 scaled delay: 0049
942709.633: <09>Lane 02 new seed: 0049
942809.634: <09>Lane 03 scaled delay: 0049
942909.634: <09>Lane 03 new seed: 0049
943009.634: <09>Lane 04 scaled delay: 0045
943109.634: <09>Lane 04 new seed: 0045
943209.634: <09>Lane 05 scaled delay: 0047
943309.634: <09>Lane 05 new seed: 0047
943409.634: <09>Lane 06 scaled delay: 004a
943509.634: <09>Lane 06 new seed: 004a
943609.634: <09>Lane 07 scaled delay: 004d
943709.634: <09>Lane 07 new seed: 004d
943809.634: <09>Lane 08 scaled delay: 0045
943909.634: <09>Lane 08 new seed: 0045
944009.634: <09>Lane 00 nibble 0 raw readback: 0049
944109.634: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0049
944209.634: <09>Lane 00 nibble 0 adjusted value (post nibble): 0049
944309.634: <09>Lane 01 nibble 0 raw readback: 0043
944409.634: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0043
944509.634: <09>Lane 01 nibble 0 adjusted value (post nibble): 0043
944609.634: <09>Lane 02 nibble 0 raw readback: 0040
944709.634: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0040
944809.634: <09>Lane 02 nibble 0 adjusted value (post nibble): 0040
944909.634: <09>Lane 03 nibble 0 raw readback: 003d
945009.634: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003d
945109.634: <09>Lane 03 nibble 0 adjusted value (post nibble): 003d
945209.634: <09>Lane 04 nibble 0 raw readback: 003a
945309.634: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
945409.634: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
945509.634: <09>Lane 05 nibble 0 raw readback: 003e
945609.634: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
945709.634: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
945809.634: <09>Lane 06 nibble 0 raw readback: 0041
945909.634: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
946009.634: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
946109.634: <09>Lane 07 nibble 0 raw readback: 0046
946209.634: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0046
946309.634: <09>Lane 07 nibble 0 adjusted value (post nibble): 0046
946409.634: <09>Lane 08 nibble 0 raw readback: 0037
946509.634: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
946609.634: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
946709.634: AgesaHwWlPhase1: training nibble 1
946809.634: DIMM 0 RttNom: 3
946909.634: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
947009.634: DIMM 0 RttWr: 1
947109.634: DIMM 0 RttWr: 1
947209.634: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
947309.634: DIMM 0 RttWr: 1
947409.634: DIMM 0 RttNom: 3
947509.634: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
947609.634: DIMM 0 RttNom: 3
947709.634: DIMM 0 RttWr: 1
947809.634: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
947909.634: DIMM 0 RttWr: 1
948009.634: DIMM 1 RttNom: 3
948109.634: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
948209.634: DIMM 0 RttNom: 3
948309.634: DIMM 1 RttWr: 1
948409.634: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
948509.634: DIMM 0 RttWr: 1
948609.634: DIMM 1 RttNom: 3
948709.634: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
948809.634: DIMM 0 RttNom: 3
948909.634: DIMM 1 RttWr: 1
949009.634: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
949109.634: DIMM 0 RttWr: 1
949209.635: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
949309.635: <09>Lane 00 new seed: 004e
949409.635: <09>Lane 01 new seed: 004b
949509.635: <09>Lane 02 new seed: 0049
949609.635: <09>Lane 03 new seed: 0049
949709.635: <09>Lane 04 new seed: 0045
949809.635: <09>Lane 05 new seed: 0047
949909.635: <09>Lane 06 new seed: 004a
950009.635: <09>Lane 07 new seed: 004d
950109.635: <09>Lane 08 new seed: 0045
950209.635: <09>Lane 00 nibble 1 raw readback: 0049
950309.635: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0049
950409.635: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
950509.635: <09>Lane 01 nibble 1 raw readback: 0044
950609.635: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
950709.635: <09>Lane 01 nibble 1 adjusted value (post nibble): 0047
950809.635: <09>Lane 02 nibble 1 raw readback: 0040
950909.635: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
951009.635: <09>Lane 02 nibble 1 adjusted value (post nibble): 0044
951109.635: <09>Lane 03 nibble 1 raw readback: 003f
951209.635: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003f
951309.635: <09>Lane 03 nibble 1 adjusted value (post nibble): 0044
951409.635: <09>Lane 04 nibble 1 raw readback: 0039
951509.635: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
951609.635: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
951709.635: <09>Lane 05 nibble 1 raw readback: 003f
951809.635: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003f
951909.635: <09>Lane 05 nibble 1 adjusted value (post nibble): 0043
952009.635: <09>Lane 06 nibble 1 raw readback: 0041
952109.635: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
952209.635: <09>Lane 06 nibble 1 adjusted value (post nibble): 0045
952309.635: <09>Lane 07 nibble 1 raw readback: 0046
952409.635: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
952509.635: <09>Lane 07 nibble 1 adjusted value (post nibble): 0049
952609.635: <09>Lane 08 nibble 1 raw readback: 0037
952709.635: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
952809.635: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
952909.635: <09>original critical gross delay: 0
953009.635: <09>new critical gross delay: 0
953109.635: DIMM 0 RttNom: 3
953209.635: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
953309.635: DIMM 0 RttNom: 3
953409.635: DIMM 0 RttWr: 1
953509.635: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
953609.635: DIMM 0 RttWr: 1
953709.635: DIMM 0 RttNom: 3
953809.635: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
953909.635: DIMM 0 RttNom: 3
954009.635: DIMM 0 RttWr: 1
954109.635: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
954209.635: DIMM 0 RttWr: 1
954309.635: DIMM 1 RttNom: 3
954409.635: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
954509.635: DIMM 0 RttNom: 3
954609.635: DIMM 1 RttWr: 1
954709.635: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
954809.635: DIMM 0 RttWr: 1
954909.635: DIMM 1 RttNom: 3
955009.635: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
955109.635: DIMM 0 RttNom: 3
955209.635: DIMM 1 RttWr: 1
955309.635: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
955409.635: DIMM 0 RttWr: 1
955509.636: AgesaHwWlPhase1: training nibble 0
955609.636: DIMM 1 RttNom: 3
955709.636: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
955809.636: DIMM 1 RttWr: 1
955909.636: DIMM 1 RttWr: 1
956009.636: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
956109.636: DIMM 1 RttWr: 1
956209.636: DIMM 1 RttNom: 3
956309.636: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
956409.636: DIMM 1 RttNom: 3
956509.636: DIMM 1 RttWr: 1
956609.636: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
956709.636: DIMM 1 RttWr: 1
956809.636: DIMM 0 RttNom: 3
956909.636: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
957009.636: DIMM 1 RttNom: 3
957109.636: DIMM 0 RttWr: 1
957209.636: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
957309.636: DIMM 1 RttWr: 1
957409.636: DIMM 0 RttNom: 3
957509.636: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
957609.636: DIMM 1 RttNom: 3
957709.636: DIMM 0 RttWr: 1
957809.636: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
957909.636: DIMM 1 RttWr: 1
958009.636: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
958109.636: <09>Lane 00 scaled delay: 0052
958209.636: <09>Lane 00 new seed: 0052
958309.636: <09>Lane 01 scaled delay: 004e
958409.636: <09>Lane 01 new seed: 004e
958509.636: <09>Lane 02 scaled delay: 004b
958609.636: <09>Lane 02 new seed: 004b
958709.636: <09>Lane 03 scaled delay: 004b
958809.636: <09>Lane 03 new seed: 004b
958909.636: <09>Lane 04 scaled delay: 0049
959009.636: <09>Lane 04 new seed: 0049
959109.636: <09>Lane 05 scaled delay: 004b
959209.636: <09>Lane 05 new seed: 004b
959309.636: <09>Lane 06 scaled delay: 004d
959409.636: <09>Lane 06 new seed: 004d
959509.636: <09>Lane 07 scaled delay: 004f
959609.636: <09>Lane 07 new seed: 004f
959709.636: <09>Lane 08 scaled delay: 0049
959809.636: <09>Lane 08 new seed: 0049
959909.636: <09>Lane 00 nibble 0 raw readback: 0051
960009.636: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0051
960109.636: <09>Lane 00 nibble 0 adjusted value (post nibble): 0051
960209.636: <09>Lane 01 nibble 0 raw readback: 004a
960309.636: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
960409.636: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
960509.636: <09>Lane 02 nibble 0 raw readback: 0046
960609.636: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
960709.636: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
960809.636: <09>Lane 03 nibble 0 raw readback: 0045
960909.636: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
961009.636: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
961109.636: <09>Lane 04 nibble 0 raw readback: 0042
961209.636: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
961309.636: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
961409.636: <09>Lane 05 nibble 0 raw readback: 0047
961509.636: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
961609.636: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
961709.636: <09>Lane 06 nibble 0 raw readback: 0048
961809.636: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
961909.636: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
962009.636: <09>Lane 07 nibble 0 raw readback: 004e
962109.636: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
962209.636: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
962309.636: <09>Lane 08 nibble 0 raw readback: 003e
962409.636: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
962509.636: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
962609.636: AgesaHwWlPhase1: training nibble 1
962709.637: DIMM 1 RttNom: 3
962809.637: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
962909.637: DIMM 1 RttWr: 1
963009.637: DIMM 1 RttWr: 1
963109.637: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
963209.637: DIMM 1 RttWr: 1
963309.637: DIMM 1 RttNom: 3
963409.637: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
963509.637: DIMM 1 RttNom: 3
963609.637: DIMM 1 RttWr: 1
963709.637: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
963809.637: DIMM 1 RttWr: 1
963909.637: DIMM 0 RttNom: 3
964009.637: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
964109.637: DIMM 1 RttNom: 3
964209.637: DIMM 0 RttWr: 1
964309.637: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
964409.637: DIMM 1 RttWr: 1
964509.637: DIMM 0 RttNom: 3
964609.637: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
964709.637: DIMM 1 RttNom: 3
964809.637: DIMM 0 RttWr: 1
964909.637: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
965009.637: DIMM 1 RttWr: 1
965109.637: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
965209.637: <09>Lane 00 new seed: 0052
965309.637: <09>Lane 01 new seed: 004e
965409.637: <09>Lane 02 new seed: 004b
965509.637: <09>Lane 03 new seed: 004b
965609.637: <09>Lane 04 new seed: 0049
965709.637: <09>Lane 05 new seed: 004b
965809.637: <09>Lane 06 new seed: 004d
965909.637: <09>Lane 07 new seed: 004f
966009.637: <09>Lane 08 new seed: 0049
966109.637: <09>Lane 00 nibble 1 raw readback: 0051
966209.637: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
966309.637: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
966409.637: <09>Lane 01 nibble 1 raw readback: 004b
966509.637: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004b
966609.637: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
966709.637: <09>Lane 02 nibble 1 raw readback: 0047
966809.637: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
966909.637: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
967009.637: <09>Lane 03 nibble 1 raw readback: 0045
967109.637: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
967209.637: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
967309.637: <09>Lane 04 nibble 1 raw readback: 0040
967409.637: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
967509.637: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
967609.637: <09>Lane 05 nibble 1 raw readback: 0046
967709.637: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0046
967809.637: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
967909.637: <09>Lane 06 nibble 1 raw readback: 0049
968009.637: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
968109.637: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
968209.637: <09>Lane 07 nibble 1 raw readback: 004e
968309.637: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
968409.637: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
968509.637: <09>Lane 08 nibble 1 raw readback: 0040
968609.637: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
968709.637: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
968809.637: <09>original critical gross delay: 0
968909.637: <09>new critical gross delay: 0
969009.637: DIMM 1 RttNom: 3
969109.638: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
969209.638: DIMM 1 RttNom: 3
969309.638: DIMM 1 RttWr: 1
969409.638: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
969509.638: DIMM 1 RttWr: 1
969609.638: DIMM 1 RttNom: 3
969709.638: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
969809.638: DIMM 1 RttNom: 3
969909.638: DIMM 1 RttWr: 1
970009.638: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
970109.638: DIMM 1 RttWr: 1
970209.638: DIMM 0 RttNom: 3
970309.638: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
970409.638: DIMM 1 RttNom: 3
970509.638: DIMM 0 RttWr: 1
970609.638: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
970709.638: DIMM 1 RttWr: 1
970809.638: DIMM 0 RttNom: 3
970909.638: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
971009.638: DIMM 1 RttNom: 3
971109.638: DIMM 0 RttWr: 1
971209.638: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
971309.638: DIMM 1 RttWr: 1
971409.638: SPD2ndTiming: Start
971509.638: SPD2ndTiming: Done
971609.638: mct_BeforeDramInit_Prod_D: Start
971709.638: mct_ProgramODT_D: Start
971809.638: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
971909.638: mct_ProgramODT_D: Done
972009.638: mct_BeforeDramInit_Prod_D: Done
972109.638: mct_DramInit_Sw_D: Start
972209.638: DIMM 0 RttWr: 1
972309.638: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
972409.639: mct_SendMrsCmd: Start
972509.639: mct_SendMrsCmd: Done
972609.639: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
972709.639: mct_SendMrsCmd: Start
972809.639: mct_SendMrsCmd: Done
972909.639: DIMM 0 RttNom: 3
973009.639: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
973109.639: mct_SendMrsCmd: Start
973209.639: mct_SendMrsCmd: Done
973309.639: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
973409.639: mct_SendMrsCmd: Start
973509.639: mct_SendMrsCmd: Done
973609.639: DIMM 0 RttWr: 1
973709.639: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
973809.639: mct_SendMrsCmd: Start
973909.639: mct_SendMrsCmd: Done
974009.639: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
974109.639: mct_SendMrsCmd: Start
974209.639: mct_SendMrsCmd: Done
974309.639: DIMM 0 RttNom: 3
974409.639: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
974509.639: mct_SendMrsCmd: Start
974609.639: mct_SendMrsCmd: Done
974709.639: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
974809.639: mct_SendMrsCmd: Start
974909.639: mct_SendMrsCmd: Done
975009.639: DIMM 1 RttWr: 1
975109.639: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
975209.639: mct_SendMrsCmd: Start
975309.639: mct_SendMrsCmd: Done
975409.639: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
975509.639: mct_SendMrsCmd: Start
975609.639: mct_SendMrsCmd: Done
975709.639: DIMM 1 RttNom: 3
975809.639: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
975909.639: mct_SendMrsCmd: Start
976009.639: mct_SendMrsCmd: Done
976109.639: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
976209.639: mct_SendMrsCmd: Start
976309.639: mct_SendMrsCmd: Done
976409.639: DIMM 1 RttWr: 1
976509.639: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
976609.639: mct_SendMrsCmd: Start
976709.639: mct_SendMrsCmd: Done
976809.639: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
976909.639: mct_SendMrsCmd: Start
977009.639: mct_SendMrsCmd: Done
977109.639: DIMM 1 RttNom: 3
977209.639: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
977309.639: mct_SendMrsCmd: Start
977409.639: mct_SendMrsCmd: Done
977509.639: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
977609.639: mct_SendMrsCmd: Start
977709.639: mct_SendMrsCmd: Done
977809.639: mct_DramInit_Sw_D: Done
977909.639: AgesaHwWlPhase1: training nibble 0
978009.639: DIMM 0 RttNom: 3
978109.639: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
978209.639: DIMM 0 RttWr: 1
978309.639: DIMM 0 RttWr: 1
978409.639: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
978509.639: DIMM 0 RttWr: 1
978609.639: DIMM 0 RttNom: 3
978709.639: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
978809.639: DIMM 0 RttNom: 3
978909.639: DIMM 0 RttWr: 1
979009.639: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
979109.639: DIMM 0 RttWr: 1
979209.639: DIMM 1 RttNom: 3
979309.640: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
979409.639: DIMM 0 RttNom: 3
979509.639: DIMM 1 RttWr: 1
979609.639: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
979709.640: DIMM 0 RttWr: 1
979809.640: DIMM 1 RttNom: 3
979909.640: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
980009.640: DIMM 0 RttNom: 3
980109.640: DIMM 1 RttWr: 1
980209.640: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
980309.640: DIMM 0 RttWr: 1
980409.640: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
980509.640: <09>Lane 00 scaled delay: 004f
980609.640: <09>Lane 00 new seed: 004f
980709.640: <09>Lane 01 scaled delay: 004d
980809.640: <09>Lane 01 new seed: 004d
980909.640: <09>Lane 02 scaled delay: 004a
981009.640: <09>Lane 02 new seed: 004a
981109.640: <09>Lane 03 scaled delay: 0047
981209.640: <09>Lane 03 new seed: 0047
981309.640: <09>Lane 04 scaled delay: 0046
981409.640: <09>Lane 04 new seed: 0046
981509.640: <09>Lane 05 scaled delay: 0049
981609.640: <09>Lane 05 new seed: 0049
981709.640: <09>Lane 06 scaled delay: 004b
981809.640: <09>Lane 06 new seed: 004b
981909.640: <09>Lane 07 scaled delay: 004e
982009.640: <09>Lane 07 new seed: 004e
982109.640: <09>Lane 08 scaled delay: 0045
982209.640: <09>Lane 08 new seed: 0045
982309.640: <09>Lane 00 nibble 0 raw readback: 004d
982409.640: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
982509.640: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
982609.640: <09>Lane 01 nibble 0 raw readback: 0047
982709.640: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
982809.640: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
982909.640: <09>Lane 02 nibble 0 raw readback: 0043
983009.640: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
983109.640: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
983209.640: <09>Lane 03 nibble 0 raw readback: 003e
983309.640: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003e
983409.640: <09>Lane 03 nibble 0 adjusted value (post nibble): 003e
983509.640: <09>Lane 04 nibble 0 raw readback: 003b
983609.640: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
983709.640: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
983809.640: <09>Lane 05 nibble 0 raw readback: 0041
983909.640: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
984009.640: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
984109.640: <09>Lane 06 nibble 0 raw readback: 0045
984209.640: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0045
984309.640: <09>Lane 06 nibble 0 adjusted value (post nibble): 0045
984409.640: <09>Lane 07 nibble 0 raw readback: 004a
984509.640: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004a
984609.640: <09>Lane 07 nibble 0 adjusted value (post nibble): 004a
984709.640: <09>Lane 08 nibble 0 raw readback: 003a
984809.640: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
984909.640: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
985009.640: AgesaHwWlPhase1: training nibble 1
985109.640: DIMM 0 RttNom: 3
985209.640: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
985309.640: DIMM 0 RttWr: 1
985409.640: DIMM 0 RttWr: 1
985509.640: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
985609.640: DIMM 0 RttWr: 1
985709.641: DIMM 0 RttNom: 3
985809.641: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
985909.641: DIMM 0 RttNom: 3
986009.641: DIMM 0 RttWr: 1
986109.641: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
986209.641: DIMM 0 RttWr: 1
986309.641: DIMM 1 RttNom: 3
986409.641: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
986509.641: DIMM 0 RttNom: 3
986609.641: DIMM 1 RttWr: 1
986709.641: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
986809.641: DIMM 0 RttWr: 1
986909.641: DIMM 1 RttNom: 3
987009.641: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
987109.641: DIMM 0 RttNom: 3
987209.641: DIMM 1 RttWr: 1
987309.641: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
987409.641: DIMM 0 RttWr: 1
987509.641: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
987609.641: <09>Lane 00 new seed: 004f
987709.641: <09>Lane 01 new seed: 004d
987809.641: <09>Lane 02 new seed: 004a
987909.641: <09>Lane 03 new seed: 0047
988009.641: <09>Lane 04 new seed: 0046
988109.641: <09>Lane 05 new seed: 0049
988209.641: <09>Lane 06 new seed: 004b
988309.641: <09>Lane 07 new seed: 004e
988409.641: <09>Lane 08 new seed: 0045
988509.641: <09>Lane 00 nibble 1 raw readback: 004d
988609.641: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004d
988709.641: <09>Lane 00 nibble 1 adjusted value (post nibble): 004e
988809.641: <09>Lane 01 nibble 1 raw readback: 0047
988909.641: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
989009.641: <09>Lane 01 nibble 1 adjusted value (post nibble): 004a
989109.641: <09>Lane 02 nibble 1 raw readback: 0042
989209.641: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0042
989309.641: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
989409.641: <09>Lane 03 nibble 1 raw readback: 003f
989509.641: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003f
989609.641: <09>Lane 03 nibble 1 adjusted value (post nibble): 0043
989709.641: <09>Lane 04 nibble 1 raw readback: 003a
989809.641: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
989909.641: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
990009.641: <09>Lane 05 nibble 1 raw readback: 0040
990109.641: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0040
990209.641: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
990309.641: <09>Lane 06 nibble 1 raw readback: 0045
990409.641: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0045
990509.641: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
990609.641: <09>Lane 07 nibble 1 raw readback: 004b
990709.641: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
990809.641: <09>Lane 07 nibble 1 adjusted value (post nibble): 004c
990909.641: <09>Lane 08 nibble 1 raw readback: 0038
991009.641: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
991109.641: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
991209.641: <09>original critical gross delay: 0
991309.641: <09>new critical gross delay: 0
991409.641: DIMM 0 RttNom: 3
991509.641: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
991609.641: DIMM 0 RttNom: 3
991709.641: DIMM 0 RttWr: 1
991809.641: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
991909.641: DIMM 0 RttWr: 1
992009.642: DIMM 0 RttNom: 3
992109.642: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
992209.642: DIMM 0 RttNom: 3
992309.642: DIMM 0 RttWr: 1
992409.642: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
992509.642: DIMM 0 RttWr: 1
992609.642: DIMM 1 RttNom: 3
992709.642: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
992809.642: DIMM 0 RttNom: 3
992909.642: DIMM 1 RttWr: 1
993009.642: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
993109.642: DIMM 0 RttWr: 1
993209.642: DIMM 1 RttNom: 3
993309.642: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
993409.642: DIMM 0 RttNom: 3
993509.642: DIMM 1 RttWr: 1
993609.642: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
993709.642: DIMM 0 RttWr: 1
993809.642: AgesaHwWlPhase1: training nibble 0
993909.642: DIMM 1 RttNom: 3
994009.642: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
994109.642: DIMM 1 RttWr: 1
994209.642: DIMM 1 RttWr: 1
994309.642: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
994409.642: DIMM 1 RttWr: 1
994509.642: DIMM 1 RttNom: 3
994609.642: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
994709.642: DIMM 1 RttNom: 3
994809.642: DIMM 1 RttWr: 1
994909.642: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
995009.642: DIMM 1 RttWr: 1
995109.642: DIMM 0 RttNom: 3
995209.642: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
995309.642: DIMM 1 RttNom: 3
995409.642: DIMM 0 RttWr: 1
995509.642: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
995609.642: DIMM 1 RttWr: 1
995709.642: DIMM 0 RttNom: 3
995809.642: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
995909.642: DIMM 1 RttNom: 3
996009.642: DIMM 0 RttWr: 1
996109.642: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
996209.642: DIMM 1 RttWr: 1
996309.642: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
996409.642: <09>Lane 00 scaled delay: 0053
996509.642: <09>Lane 00 new seed: 0053
996609.642: <09>Lane 01 scaled delay: 004f
996709.642: <09>Lane 01 new seed: 004f
996809.642: <09>Lane 02 scaled delay: 004d
996909.642: <09>Lane 02 new seed: 004d
997009.642: <09>Lane 03 scaled delay: 004b
997109.642: <09>Lane 03 new seed: 004b
997209.642: <09>Lane 04 scaled delay: 0049
997309.642: <09>Lane 04 new seed: 0049
997409.642: <09>Lane 05 scaled delay: 004b
997509.642: <09>Lane 05 new seed: 004b
997609.642: <09>Lane 06 scaled delay: 004e
997709.642: <09>Lane 06 new seed: 004e
997809.642: <09>Lane 07 scaled delay: 0052
997909.642: <09>Lane 07 new seed: 0052
998009.642: <09>Lane 08 scaled delay: 0049
998109.642: <09>Lane 08 new seed: 0049
998209.642: <09>Lane 00 nibble 0 raw readback: 0050
998309.642: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
998409.642: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
998509.642: <09>Lane 01 nibble 0 raw readback: 004f
998609.643: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
998709.642: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
998809.643: <09>Lane 02 nibble 0 raw readback: 0049
998909.643: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
999009.643: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
999109.643: <09>Lane 03 nibble 0 raw readback: 0044
999209.643: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
999309.643: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
999409.643: <09>Lane 04 nibble 0 raw readback: 0041
999509.643: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
999609.643: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
999709.643: <09>Lane 05 nibble 0 raw readback: 0047
999809.643: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
999909.643: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
1000009.643: <09>Lane 06 nibble 0 raw readback: 004c
1000109.643: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004c
1000209.643: <09>Lane 06 nibble 0 adjusted value (post nibble): 004c
1000309.643: <09>Lane 07 nibble 0 raw readback: 0050
1000409.643: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
1000509.643: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
1000609.643: <09>Lane 08 nibble 0 raw readback: 003e
1000709.643: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
1000809.643: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
1000909.643: AgesaHwWlPhase1: training nibble 1
1001009.643: DIMM 1 RttNom: 3
1001109.643: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1001209.643: DIMM 1 RttWr: 1
1001309.643: DIMM 1 RttWr: 1
1001409.643: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1001509.643: DIMM 1 RttWr: 1
1001609.643: DIMM 1 RttNom: 3
1001709.643: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1001809.643: DIMM 1 RttNom: 3
1001909.643: DIMM 1 RttWr: 1
1002009.643: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1002109.643: DIMM 1 RttWr: 1
1002209.643: DIMM 0 RttNom: 3
1002309.643: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1002409.643: DIMM 1 RttNom: 3
1002509.643: DIMM 0 RttWr: 1
1002609.643: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1002709.643: DIMM 1 RttWr: 1
1002809.643: DIMM 0 RttNom: 3
1002909.643: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1003009.643: DIMM 1 RttNom: 3
1003109.643: DIMM 0 RttWr: 1
1003209.643: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1003309.643: DIMM 1 RttWr: 1
1003409.643: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1003509.643: <09>Lane 00 new seed: 0053
1003609.643: <09>Lane 01 new seed: 004f
1003709.643: <09>Lane 02 new seed: 004d
1003809.643: <09>Lane 03 new seed: 004b
1003909.643: <09>Lane 04 new seed: 0049
1004009.643: <09>Lane 05 new seed: 004b
1004109.643: <09>Lane 06 new seed: 004e
1004209.643: <09>Lane 07 new seed: 0052
1004309.643: <09>Lane 08 new seed: 0049
1004409.643: <09>Lane 00 nibble 1 raw readback: 0053
1004509.643: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
1004609.643: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
1004709.643: <09>Lane 01 nibble 1 raw readback: 004e
1004809.643: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
1004909.643: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
1005009.643: <09>Lane 02 nibble 1 raw readback: 0049
1005109.643: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
1005209.643: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
1005309.643: <09>Lane 03 nibble 1 raw readback: 0045
1005409.643: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
1005509.643: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1005609.643: <09>Lane 04 nibble 1 raw readback: 0040
1005709.643: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
1005809.643: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
1005909.643: <09>Lane 05 nibble 1 raw readback: 0045
1006009.643: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
1006109.643: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
1006209.644: <09>Lane 06 nibble 1 raw readback: 004b
1006309.644: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004b
1006409.644: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
1006509.644: <09>Lane 07 nibble 1 raw readback: 0050
1006609.644: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
1006709.644: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
1006809.644: <09>Lane 08 nibble 1 raw readback: 0040
1006909.644: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
1007009.644: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
1007109.644: <09>original critical gross delay: 0
1007209.644: <09>new critical gross delay: 0
1007309.644: DIMM 1 RttNom: 3
1007409.644: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1007509.644: DIMM 1 RttNom: 3
1007609.644: DIMM 1 RttWr: 1
1007709.644: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1007809.644: DIMM 1 RttWr: 1
1007909.644: DIMM 1 RttNom: 3
1008009.644: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1008109.644: DIMM 1 RttNom: 3
1008209.644: DIMM 1 RttWr: 1
1008309.644: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1008409.644: DIMM 1 RttWr: 1
1008509.644: DIMM 0 RttNom: 3
1008609.644: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1008709.644: DIMM 1 RttNom: 3
1008809.644: DIMM 0 RttWr: 1
1008909.644: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1009009.644: DIMM 1 RttWr: 1
1009109.644: DIMM 0 RttNom: 3
1009209.644: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1009309.644: DIMM 1 RttNom: 3
1009409.644: DIMM 0 RttWr: 1
1009509.644: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1009609.644: DIMM 1 RttWr: 1
1009709.644: SetTargetFreq: Start
1009809.644: SetTargetFreq: Node 1: New frequency code: 000e
1009909.644: ChangeMemClk: Start
1010009.644: set_2t_configuration: Start
1010109.644: set_2t_configuration: Done
1010209.644: mct_BeforePlatformSpec: Start
1010309.644: mct_BeforePlatformSpec: Done
1010409.645: mct_PlatformSpec: Start
1010509.645: Programmed DCT 0 timing/termination pattern 00383a38 30222222
1010609.645: mct_PlatformSpec: Done
1010709.645: set_2t_configuration: Start
1010809.645: set_2t_configuration: Done
1010909.645: mct_BeforePlatformSpec: Start
1011009.645: mct_BeforePlatformSpec: Done
1011109.645: mct_PlatformSpec: Start
1011209.645: Programmed DCT 1 timing/termination pattern 00383a38 30222222
1011309.645: mct_PlatformSpec: Done
1011409.645: ChangeMemClk: Done
1011509.645: phyAssistedMemFnceTraining: Start
1011609.645: phyAssistedMemFnceTraining: training node 1 DCT 0
1011709.645: phyAssistedMemFnceTraining: done training node 1 DCT 0
1011809.645: phyAssistedMemFnceTraining: training node 1 DCT 1
1011909.645: phyAssistedMemFnceTraining: done training node 1 DCT 1
1012009.645: phyAssistedMemFnceTraining: Done
1012109.645: InitPhyCompensation: DCT 0: Start
1012209.645: Waiting for predriver calibration to be applied...done!
1012309.645: InitPhyCompensation: DCT 0: Done
1012409.645: phyAssistedMemFnceTraining: Start
1012509.645: phyAssistedMemFnceTraining: training node 1 DCT 0
1012609.645: phyAssistedMemFnceTraining: done training node 1 DCT 0
1012709.645: phyAssistedMemFnceTraining: training node 1 DCT 1
1012809.645: phyAssistedMemFnceTraining: done training node 1 DCT 1
1012909.645: phyAssistedMemFnceTraining: Done
1013009.645: InitPhyCompensation: DCT 1: Start
1013109.646: Waiting for predriver calibration to be applied...done!
1013209.646: InitPhyCompensation: DCT 1: Done
1013309.646: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
1013409.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1013509.646: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1013609.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1013709.646: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1013809.646: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
1013909.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1014009.646: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1014109.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1014209.646: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1014309.646: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
1014409.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1014509.646: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1014609.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1014709.646: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1014809.646: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
1014909.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1015009.646: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1015109.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1015209.646: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1015309.646: SetTargetFreq: Done
1015409.646: SPD2ndTiming: Start
1015509.647: SPD2ndTiming: Done
1015609.647: mct_BeforeDramInit_Prod_D: Start
1015709.647: mct_ProgramODT_D: Start
1015809.647: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1015909.647: mct_ProgramODT_D: Done
1016009.647: mct_BeforeDramInit_Prod_D: Done
1016109.647: mct_DramInit_Sw_D: Start
1016209.647: DIMM 0 RttWr: 2
1016309.647: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1016409.647: mct_SendMrsCmd: Start
1016509.647: mct_SendMrsCmd: Done
1016609.647: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1016709.647: mct_SendMrsCmd: Start
1016809.647: mct_SendMrsCmd: Done
1016909.647: DIMM 0 RttNom: 5
1017009.647: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1017109.647: mct_SendMrsCmd: Start
1017209.647: mct_SendMrsCmd: Done
1017309.647: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
1017409.647: mct_SendMrsCmd: Start
1017509.647: mct_SendMrsCmd: Done
1017609.647: DIMM 0 RttWr: 2
1017709.647: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1017809.647: mct_SendMrsCmd: Start
1017909.647: mct_SendMrsCmd: Done
1018009.647: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1018109.647: mct_SendMrsCmd: Start
1018209.647: mct_SendMrsCmd: Done
1018309.647: DIMM 0 RttNom: 5
1018409.647: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1018509.647: mct_SendMrsCmd: Start
1018609.647: mct_SendMrsCmd: Done
1018709.647: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
1018809.647: mct_SendMrsCmd: Start
1018909.647: mct_SendMrsCmd: Done
1019009.647: DIMM 1 RttWr: 2
1019109.647: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1019209.647: mct_SendMrsCmd: Start
1019309.647: mct_SendMrsCmd: Done
1019409.647: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1019509.647: mct_SendMrsCmd: Start
1019609.647: mct_SendMrsCmd: Done
1019709.647: DIMM 1 RttNom: 5
1019809.647: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1019909.647: mct_SendMrsCmd: Start
1020009.647: mct_SendMrsCmd: Done
1020109.647: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
1020209.647: mct_SendMrsCmd: Start
1020309.647: mct_SendMrsCmd: Done
1020409.647: DIMM 1 RttWr: 2
1020509.647: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1020609.647: mct_SendMrsCmd: Start
1020709.647: mct_SendMrsCmd: Done
1020809.647: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1020909.647: mct_SendMrsCmd: Start
1021009.647: mct_SendMrsCmd: Done
1021109.647: DIMM 1 RttNom: 5
1021209.647: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1021309.647: mct_SendMrsCmd: Start
1021409.647: mct_SendMrsCmd: Done
1021509.647: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
1021609.647: mct_SendMrsCmd: Start
1021709.647: mct_SendMrsCmd: Done
1021809.647: mct_DramInit_Sw_D: Done
1021909.648: AgesaHwWlPhase1: training nibble 0
1022009.648: DIMM 0 RttNom: 5
1022109.648: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1022209.648: DIMM 0 RttWr: 2
1022309.648: DIMM 0 RttWr: 2
1022409.648: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1022509.648: DIMM 0 RttWr: 2
1022609.648: DIMM 0 RttNom: 5
1022709.648: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1022809.648: DIMM 0 RttNom: 5
1022909.648: DIMM 0 RttWr: 2
1023009.648: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1023109.648: DIMM 0 RttWr: 2
1023209.648: DIMM 1 RttNom: 5
1023309.648: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1023409.648: DIMM 0 RttNom: 5
1023509.648: DIMM 1 RttWr: 2
1023609.648: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1023709.648: DIMM 0 RttWr: 2
1023809.648: DIMM 1 RttNom: 5
1023909.648: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1024009.648: DIMM 0 RttNom: 5
1024109.648: DIMM 1 RttWr: 2
1024209.648: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1024309.648: DIMM 0 RttWr: 2
1024409.648: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1024509.648: <09>Lane 00 scaled delay: 0055
1024609.648: <09>Lane 00 new seed: 0055
1024709.648: <09>Lane 01 scaled delay: 0050
1024809.648: <09>Lane 01 new seed: 0050
1024909.648: <09>Lane 02 scaled delay: 004d
1025009.648: <09>Lane 02 new seed: 004d
1025109.648: <09>Lane 03 scaled delay: 004d
1025209.648: <09>Lane 03 new seed: 004d
1025309.648: <09>Lane 04 scaled delay: 0046
1025409.648: <09>Lane 04 new seed: 0046
1025509.648: <09>Lane 05 scaled delay: 004b
1025609.648: <09>Lane 05 new seed: 004b
1025709.648: <09>Lane 06 scaled delay: 004e
1025809.648: <09>Lane 06 new seed: 004e
1025909.648: <09>Lane 07 scaled delay: 0053
1026009.649: <09>Lane 07 new seed: 0053
1026109.648: <09>Lane 08 scaled delay: 0045
1026209.649: <09>Lane 08 new seed: 0045
1026309.649: <09>Lane 00 nibble 0 raw readback: 0055
1026409.649: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0055
1026509.649: <09>Lane 00 nibble 0 adjusted value (post nibble): 0055
1026609.649: <09>Lane 01 nibble 0 raw readback: 004e
1026709.649: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
1026809.649: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
1026909.649: <09>Lane 02 nibble 0 raw readback: 0049
1027009.649: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
1027109.649: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
1027209.649: <09>Lane 03 nibble 0 raw readback: 0046
1027309.649: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0046
1027409.649: <09>Lane 03 nibble 0 adjusted value (post nibble): 0046
1027509.649: <09>Lane 04 nibble 0 raw readback: 0042
1027609.649: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
1027709.649: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
1027809.649: <09>Lane 05 nibble 0 raw readback: 0048
1027909.649: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
1028009.649: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
1028109.649: <09>Lane 06 nibble 0 raw readback: 004b
1028209.649: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
1028309.649: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
1028409.649: <09>Lane 07 nibble 0 raw readback: 0050
1028509.649: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
1028609.649: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
1028709.649: <09>Lane 08 nibble 0 raw readback: 003e
1028809.649: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
1028909.649: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
1029009.649: AgesaHwWlPhase1: training nibble 1
1029109.649: DIMM 0 RttNom: 5
1029209.649: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1029309.649: DIMM 0 RttWr: 2
1029409.649: DIMM 0 RttWr: 2
1029509.649: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1029609.649: DIMM 0 RttWr: 2
1029709.649: DIMM 0 RttNom: 5
1029809.649: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1029909.649: DIMM 0 RttNom: 5
1030009.649: DIMM 0 RttWr: 2
1030109.649: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1030209.649: DIMM 0 RttWr: 2
1030309.649: DIMM 1 RttNom: 5
1030409.649: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1030509.649: DIMM 0 RttNom: 5
1030609.649: DIMM 1 RttWr: 2
1030709.649: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1030809.649: DIMM 0 RttWr: 2
1030909.649: DIMM 1 RttNom: 5
1031009.649: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1031109.649: DIMM 0 RttNom: 5
1031209.649: DIMM 1 RttWr: 2
1031309.649: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1031409.649: DIMM 0 RttWr: 2
1031509.649: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1031609.649: <09>Lane 00 new seed: 0055
1031709.649: <09>Lane 01 new seed: 0050
1031809.649: <09>Lane 02 new seed: 004d
1031909.649: <09>Lane 03 new seed: 004d
1032009.649: <09>Lane 04 new seed: 0046
1032109.650: <09>Lane 05 new seed: 004b
1032209.649: <09>Lane 06 new seed: 004e
1032309.649: <09>Lane 07 new seed: 0053
1032409.650: <09>Lane 08 new seed: 0045
1032509.650: <09>Lane 00 nibble 1 raw readback: 0055
1032609.650: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0055
1032709.650: <09>Lane 00 nibble 1 adjusted value (post nibble): 0055
1032809.650: <09>Lane 01 nibble 1 raw readback: 004f
1032909.650: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004f
1033009.650: <09>Lane 01 nibble 1 adjusted value (post nibble): 004f
1033109.650: <09>Lane 02 nibble 1 raw readback: 0049
1033209.650: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
1033309.650: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
1033409.650: <09>Lane 03 nibble 1 raw readback: 0047
1033509.650: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
1033609.650: <09>Lane 03 nibble 1 adjusted value (post nibble): 004a
1033709.650: <09>Lane 04 nibble 1 raw readback: 0040
1033809.650: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
1033909.650: <09>Lane 04 nibble 1 adjusted value (post nibble): 0043
1034009.650: <09>Lane 05 nibble 1 raw readback: 0047
1034109.650: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
1034209.650: <09>Lane 05 nibble 1 adjusted value (post nibble): 0049
1034309.650: <09>Lane 06 nibble 1 raw readback: 004b
1034409.650: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004b
1034509.650: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
1034609.650: <09>Lane 07 nibble 1 raw readback: 0050
1034709.650: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
1034809.650: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
1034909.650: <09>Lane 08 nibble 1 raw readback: 003d
1035009.650: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
1035109.650: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
1035209.650: <09>original critical gross delay: 0
1035309.650: <09>new critical gross delay: 0
1035409.650: DIMM 0 RttNom: 5
1035509.650: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1035609.650: DIMM 0 RttNom: 5
1035709.650: DIMM 0 RttWr: 2
1035809.650: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1035909.650: DIMM 0 RttWr: 2
1036009.650: DIMM 0 RttNom: 5
1036109.650: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1036209.650: DIMM 0 RttNom: 5
1036309.650: DIMM 0 RttWr: 2
1036409.650: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1036509.650: DIMM 0 RttWr: 2
1036609.650: DIMM 1 RttNom: 5
1036709.650: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1036809.650: DIMM 0 RttNom: 5
1036909.650: DIMM 1 RttWr: 2
1037009.650: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1037109.650: DIMM 0 RttWr: 2
1037209.650: DIMM 1 RttNom: 5
1037309.650: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1037409.650: DIMM 0 RttNom: 5
1037509.650: DIMM 1 RttWr: 2
1037609.650: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1037709.650: DIMM 0 RttWr: 2
1037809.650: AgesaHwWlPhase1: training nibble 0
1037909.650: DIMM 1 RttNom: 5
1038009.650: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1038109.650: DIMM 1 RttWr: 2
1038209.650: DIMM 1 RttWr: 2
1038309.650: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1038409.650: DIMM 1 RttWr: 2
1038509.651: DIMM 1 RttNom: 5
1038609.650: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1038709.651: DIMM 1 RttNom: 5
1038809.651: DIMM 1 RttWr: 2
1038909.651: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1039009.651: DIMM 1 RttWr: 2
1039109.651: DIMM 0 RttNom: 5
1039209.651: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1039309.651: DIMM 1 RttNom: 5
1039409.651: DIMM 0 RttWr: 2
1039509.651: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1039609.651: DIMM 1 RttWr: 2
1039709.651: DIMM 0 RttNom: 5
1039809.651: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1039909.651: DIMM 1 RttNom: 5
1040009.651: DIMM 0 RttWr: 2
1040109.651: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1040209.651: DIMM 1 RttWr: 2
1040309.651: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1040409.651: <09>Lane 00 scaled delay: 005d
1040509.651: <09>Lane 00 new seed: 005d
1040609.651: <09>Lane 01 scaled delay: 0057
1040709.651: <09>Lane 01 new seed: 0057
1040809.651: <09>Lane 02 scaled delay: 0053
1040909.651: <09>Lane 02 new seed: 0053
1041009.651: <09>Lane 03 scaled delay: 0052
1041109.651: <09>Lane 03 new seed: 0052
1041209.651: <09>Lane 04 scaled delay: 004d
1041309.651: <09>Lane 04 new seed: 004d
1041409.651: <09>Lane 05 scaled delay: 0052
1041509.651: <09>Lane 05 new seed: 0052
1041609.651: <09>Lane 06 scaled delay: 0055
1041709.651: <09>Lane 06 new seed: 0055
1041809.651: <09>Lane 07 scaled delay: 0059
1041909.651: <09>Lane 07 new seed: 0059
1042009.651: <09>Lane 08 scaled delay: 004d
1042109.651: <09>Lane 08 new seed: 004d
1042209.651: <09>Lane 00 nibble 0 raw readback: 005f
1042309.651: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
1042409.651: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
1042509.651: <09>Lane 01 nibble 0 raw readback: 0055
1042609.651: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0055
1042709.651: <09>Lane 01 nibble 0 adjusted value (post nibble): 0055
1042809.651: <09>Lane 02 nibble 0 raw readback: 004f
1042909.651: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
1043009.651: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
1043109.651: <09>Lane 03 nibble 0 raw readback: 004e
1043209.651: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
1043309.651: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
1043409.651: <09>Lane 04 nibble 0 raw readback: 0049
1043509.651: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
1043609.651: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
1043709.651: <09>Lane 05 nibble 0 raw readback: 0051
1043809.651: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
1043909.651: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
1044009.651: <09>Lane 06 nibble 0 raw readback: 0051
1044109.651: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
1044209.651: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
1044309.651: <09>Lane 07 nibble 0 raw readback: 0058
1044409.651: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
1044509.651: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
1044609.651: <09>Lane 08 nibble 0 raw readback: 0046
1044709.651: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0046
1044809.651: <09>Lane 08 nibble 0 adjusted value (post nibble): 0046
1044909.651: AgesaHwWlPhase1: training nibble 1
1045009.651: DIMM 1 RttNom: 5
1045109.651: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1045209.651: DIMM 1 RttWr: 2
1045309.651: DIMM 1 RttWr: 2
1045409.651: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1045509.651: DIMM 1 RttWr: 2
1045609.651: DIMM 1 RttNom: 5
1045709.652: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1045809.651: DIMM 1 RttNom: 5
1045909.651: DIMM 1 RttWr: 2
1046009.652: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1046109.652: DIMM 1 RttWr: 2
1046209.652: DIMM 0 RttNom: 5
1046309.652: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1046409.652: DIMM 1 RttNom: 5
1046509.652: DIMM 0 RttWr: 2
1046609.652: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1046709.652: DIMM 1 RttWr: 2
1046809.652: DIMM 0 RttNom: 5
1046909.652: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1047009.652: DIMM 1 RttNom: 5
1047109.652: DIMM 0 RttWr: 2
1047209.652: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1047309.652: DIMM 1 RttWr: 2
1047409.652: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1047509.652: <09>Lane 00 new seed: 005d
1047609.652: <09>Lane 01 new seed: 0057
1047709.652: <09>Lane 02 new seed: 0053
1047809.652: <09>Lane 03 new seed: 0052
1047909.652: <09>Lane 04 new seed: 004d
1048009.652: <09>Lane 05 new seed: 0052
1048109.652: <09>Lane 06 new seed: 0055
1048209.652: <09>Lane 07 new seed: 0059
1048309.652: <09>Lane 08 new seed: 004d
1048409.652: <09>Lane 00 nibble 1 raw readback: 005e
1048509.652: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005e
1048609.652: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
1048709.652: <09>Lane 01 nibble 1 raw readback: 0055
1048809.652: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
1048909.652: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
1049009.652: <09>Lane 02 nibble 1 raw readback: 004f
1049109.652: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004f
1049209.652: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
1049309.652: <09>Lane 03 nibble 1 raw readback: 004d
1049409.652: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
1049509.652: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
1049609.652: <09>Lane 04 nibble 1 raw readback: 0047
1049709.652: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0047
1049809.652: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
1049909.652: <09>Lane 05 nibble 1 raw readback: 004e
1050009.652: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004e
1050109.652: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
1050209.652: <09>Lane 06 nibble 1 raw readback: 0051
1050309.652: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0051
1050409.652: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
1050509.652: <09>Lane 07 nibble 1 raw readback: 0057
1050609.652: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
1050709.652: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
1050809.652: <09>Lane 08 nibble 1 raw readback: 0046
1050909.652: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0046
1051009.652: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
1051109.652: <09>original critical gross delay: 0
1051209.652: <09>new critical gross delay: 0
1051309.652: DIMM 1 RttNom: 5
1051409.652: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1051509.652: DIMM 1 RttNom: 5
1051609.652: DIMM 1 RttWr: 2
1051709.652: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1051809.652: DIMM 1 RttWr: 2
1051909.652: DIMM 1 RttNom: 5
1052009.652: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1052109.652: DIMM 1 RttNom: 5
1052209.652: DIMM 1 RttWr: 2
1052309.652: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1052409.653: DIMM 1 RttWr: 2
1052509.653: DIMM 0 RttNom: 5
1052609.653: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1052709.653: DIMM 1 RttNom: 5
1052809.653: DIMM 0 RttWr: 2
1052909.653: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1053009.653: DIMM 1 RttWr: 2
1053109.653: DIMM 0 RttNom: 5
1053209.653: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1053309.653: DIMM 1 RttNom: 5
1053409.653: DIMM 0 RttWr: 2
1053509.653: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1053609.653: DIMM 1 RttWr: 2
1053709.653: SPD2ndTiming: Start
1053809.653: SPD2ndTiming: Done
1053909.653: mct_BeforeDramInit_Prod_D: Start
1054009.653: mct_ProgramODT_D: Start
1054109.653: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1054209.653: mct_ProgramODT_D: Done
1054309.653: mct_BeforeDramInit_Prod_D: Done
1054409.653: mct_DramInit_Sw_D: Start
1054509.653: DIMM 0 RttWr: 2
1054609.653: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1054709.653: mct_SendMrsCmd: Start
1054809.653: mct_SendMrsCmd: Done
1054909.653: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1055009.653: mct_SendMrsCmd: Start
1055109.653: mct_SendMrsCmd: Done
1055209.653: DIMM 0 RttNom: 5
1055309.653: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1055409.653: mct_SendMrsCmd: Start
1055509.653: mct_SendMrsCmd: Done
1055609.653: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
1055709.653: mct_SendMrsCmd: Start
1055809.653: mct_SendMrsCmd: Done
1055909.653: DIMM 0 RttWr: 2
1056009.653: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1056109.654: mct_SendMrsCmd: Start
1056209.654: mct_SendMrsCmd: Done
1056309.654: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1056409.654: mct_SendMrsCmd: Start
1056509.654: mct_SendMrsCmd: Done
1056609.654: DIMM 0 RttNom: 5
1056709.654: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1056809.654: mct_SendMrsCmd: Start
1056909.654: mct_SendMrsCmd: Done
1057009.654: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
1057109.654: mct_SendMrsCmd: Start
1057209.654: mct_SendMrsCmd: Done
1057309.654: DIMM 1 RttWr: 2
1057409.654: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1057509.654: mct_SendMrsCmd: Start
1057609.654: mct_SendMrsCmd: Done
1057709.654: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1057809.654: mct_SendMrsCmd: Start
1057909.654: mct_SendMrsCmd: Done
1058009.654: DIMM 1 RttNom: 5
1058109.654: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1058209.654: mct_SendMrsCmd: Start
1058309.654: mct_SendMrsCmd: Done
1058409.654: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
1058509.654: mct_SendMrsCmd: Start
1058609.654: mct_SendMrsCmd: Done
1058709.654: DIMM 1 RttWr: 2
1058809.654: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1058909.654: mct_SendMrsCmd: Start
1059009.654: mct_SendMrsCmd: Done
1059109.654: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1059209.654: mct_SendMrsCmd: Start
1059309.654: mct_SendMrsCmd: Done
1059409.654: DIMM 1 RttNom: 5
1059509.654: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1059609.654: mct_SendMrsCmd: Start
1059709.654: mct_SendMrsCmd: Done
1059809.654: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
1059909.654: mct_SendMrsCmd: Start
1060009.654: mct_SendMrsCmd: Done
1060109.654: mct_DramInit_Sw_D: Done
1060209.654: AgesaHwWlPhase1: training nibble 0
1060309.654: DIMM 0 RttNom: 5
1060409.654: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1060509.654: DIMM 0 RttWr: 2
1060609.654: DIMM 0 RttWr: 2
1060709.654: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1060809.654: DIMM 0 RttWr: 2
1060909.654: DIMM 0 RttNom: 5
1061009.654: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1061109.654: DIMM 0 RttNom: 5
1061209.654: DIMM 0 RttWr: 2
1061309.654: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1061409.654: DIMM 0 RttWr: 2
1061509.654: DIMM 1 RttNom: 5
1061609.654: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1061709.654: DIMM 0 RttNom: 5
1061809.654: DIMM 1 RttWr: 2
1061909.654: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1062009.654: DIMM 0 RttWr: 2
1062109.654: DIMM 1 RttNom: 5
1062209.654: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1062309.654: DIMM 0 RttNom: 5
1062409.654: DIMM 1 RttWr: 2
1062509.654: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1062609.654: DIMM 0 RttWr: 2
1062709.654: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1062809.655: <09>Lane 00 scaled delay: 0059
1062909.655: <09>Lane 00 new seed: 0059
1063009.655: <09>Lane 01 scaled delay: 0054
1063109.655: <09>Lane 01 new seed: 0054
1063209.655: <09>Lane 02 scaled delay: 004f
1063309.655: <09>Lane 02 new seed: 004f
1063409.655: <09>Lane 03 scaled delay: 004b
1063509.655: <09>Lane 03 new seed: 004b
1063609.655: <09>Lane 04 scaled delay: 0048
1063709.655: <09>Lane 04 new seed: 0048
1063809.655: <09>Lane 05 scaled delay: 004d
1063909.655: <09>Lane 05 new seed: 004d
1064009.655: <09>Lane 06 scaled delay: 0052
1064109.655: <09>Lane 06 new seed: 0052
1064209.655: <09>Lane 07 scaled delay: 0057
1064309.655: <09>Lane 07 new seed: 0057
1064409.655: <09>Lane 08 scaled delay: 0045
1064509.655: <09>Lane 08 new seed: 0045
1064609.655: <09>Lane 00 nibble 0 raw readback: 0059
1064709.655: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0059
1064809.655: <09>Lane 00 nibble 0 adjusted value (post nibble): 0059
1064909.655: <09>Lane 01 nibble 0 raw readback: 0050
1065009.655: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0050
1065109.655: <09>Lane 01 nibble 0 adjusted value (post nibble): 0050
1065209.655: <09>Lane 02 nibble 0 raw readback: 004d
1065309.655: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004d
1065409.655: <09>Lane 02 nibble 0 adjusted value (post nibble): 004d
1065509.655: <09>Lane 03 nibble 0 raw readback: 0047
1065609.655: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
1065709.655: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
1065809.655: <09>Lane 04 nibble 0 raw readback: 0044
1065909.655: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
1066009.655: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
1066109.655: <09>Lane 05 nibble 0 raw readback: 004b
1066209.655: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004b
1066309.655: <09>Lane 05 nibble 0 adjusted value (post nibble): 004b
1066409.655: <09>Lane 06 nibble 0 raw readback: 004e
1066509.655: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
1066609.655: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
1066709.655: <09>Lane 07 nibble 0 raw readback: 0055
1066809.655: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0055
1066909.655: <09>Lane 07 nibble 0 adjusted value (post nibble): 0055
1067009.655: <09>Lane 08 nibble 0 raw readback: 0042
1067109.655: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0042
1067209.655: <09>Lane 08 nibble 0 adjusted value (post nibble): 0042
1067309.655: AgesaHwWlPhase1: training nibble 1
1067409.655: DIMM 0 RttNom: 5
1067509.655: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1067609.655: DIMM 0 RttWr: 2
1067709.655: DIMM 0 RttWr: 2
1067809.655: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1067909.655: DIMM 0 RttWr: 2
1068009.655: DIMM 0 RttNom: 5
1068109.655: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1068209.655: DIMM 0 RttNom: 5
1068309.655: DIMM 0 RttWr: 2
1068409.655: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1068509.655: DIMM 0 RttWr: 2
1068609.655: DIMM 1 RttNom: 5
1068709.655: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1068809.655: DIMM 0 RttNom: 5
1068909.655: DIMM 1 RttWr: 2
1069009.655: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1069109.655: DIMM 0 RttWr: 2
1069209.656: DIMM 1 RttNom: 5
1069309.656: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1069409.656: DIMM 0 RttNom: 5
1069509.656: DIMM 1 RttWr: 2
1069609.656: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1069709.656: DIMM 0 RttWr: 2
1069809.656: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1069909.656: <09>Lane 00 new seed: 0059
1070009.656: <09>Lane 01 new seed: 0054
1070109.656: <09>Lane 02 new seed: 004f
1070209.656: <09>Lane 03 new seed: 004b
1070309.656: <09>Lane 04 new seed: 0048
1070409.656: <09>Lane 05 new seed: 004d
1070509.656: <09>Lane 06 new seed: 0052
1070609.656: <09>Lane 07 new seed: 0057
1070709.656: <09>Lane 08 new seed: 0045
1070809.656: <09>Lane 00 nibble 1 raw readback: 0058
1070909.656: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0058
1071009.656: <09>Lane 00 nibble 1 adjusted value (post nibble): 0058
1071109.656: <09>Lane 01 nibble 1 raw readback: 0051
1071209.656: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0051
1071309.656: <09>Lane 01 nibble 1 adjusted value (post nibble): 0052
1071409.656: <09>Lane 02 nibble 1 raw readback: 004b
1071509.656: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004b
1071609.656: <09>Lane 02 nibble 1 adjusted value (post nibble): 004d
1071709.656: <09>Lane 03 nibble 1 raw readback: 0047
1071809.656: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
1071909.656: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
1072009.656: <09>Lane 04 nibble 1 raw readback: 0042
1072109.656: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
1072209.656: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
1072309.656: <09>Lane 05 nibble 1 raw readback: 004a
1072409.656: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004a
1072509.656: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
1072609.656: <09>Lane 06 nibble 1 raw readback: 004f
1072709.656: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
1072809.656: <09>Lane 06 nibble 1 adjusted value (post nibble): 0050
1072909.656: <09>Lane 07 nibble 1 raw readback: 0057
1073009.656: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
1073109.656: <09>Lane 07 nibble 1 adjusted value (post nibble): 0057
1073209.656: <09>Lane 08 nibble 1 raw readback: 0040
1073309.656: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
1073409.656: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
1073509.656: <09>original critical gross delay: 0
1073609.656: <09>new critical gross delay: 0
1073709.656: DIMM 0 RttNom: 5
1073809.656: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1073909.656: DIMM 0 RttNom: 5
1074009.656: DIMM 0 RttWr: 2
1074109.656: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1074209.656: DIMM 0 RttWr: 2
1074309.656: DIMM 0 RttNom: 5
1074409.656: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1074509.656: DIMM 0 RttNom: 5
1074609.656: DIMM 0 RttWr: 2
1074709.656: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1074809.656: DIMM 0 RttWr: 2
1074909.656: DIMM 1 RttNom: 5
1075009.656: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1075109.657: DIMM 0 RttNom: 5
1075209.656: DIMM 1 RttWr: 2
1075309.657: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1075409.657: DIMM 0 RttWr: 2
1075509.657: DIMM 1 RttNom: 5
1075609.657: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1075709.657: DIMM 0 RttNom: 5
1075809.657: DIMM 1 RttWr: 2
1075909.657: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1076009.657: DIMM 0 RttWr: 2
1076109.657: AgesaHwWlPhase1: training nibble 0
1076209.657: DIMM 1 RttNom: 5
1076309.657: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1076409.657: DIMM 1 RttWr: 2
1076509.657: DIMM 1 RttWr: 2
1076609.657: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1076709.657: DIMM 1 RttWr: 2
1076809.657: DIMM 1 RttNom: 5
1076909.657: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1077009.657: DIMM 1 RttNom: 5
1077109.657: DIMM 1 RttWr: 2
1077209.657: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1077309.657: DIMM 1 RttWr: 2
1077409.657: DIMM 0 RttNom: 5
1077509.657: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1077609.657: DIMM 1 RttNom: 5
1077709.657: DIMM 0 RttWr: 2
1077809.657: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1077909.657: DIMM 1 RttWr: 2
1078009.657: DIMM 0 RttNom: 5
1078109.657: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1078209.657: DIMM 1 RttNom: 5
1078309.657: DIMM 0 RttWr: 2
1078409.657: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1078509.657: DIMM 1 RttWr: 2
1078609.657: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1078709.657: <09>Lane 00 scaled delay: 005f
1078809.657: <09>Lane 00 new seed: 005f
1078909.657: <09>Lane 01 scaled delay: 0059
1079009.657: <09>Lane 01 new seed: 0059
1079109.657: <09>Lane 02 scaled delay: 0055
1079209.657: <09>Lane 02 new seed: 0055
1079309.657: <09>Lane 03 scaled delay: 0052
1079409.657: <09>Lane 03 new seed: 0052
1079509.657: <09>Lane 04 scaled delay: 004d
1079609.657: <09>Lane 04 new seed: 004d
1079709.657: <09>Lane 05 scaled delay: 0052
1079809.657: <09>Lane 05 new seed: 0052
1079909.657: <09>Lane 06 scaled delay: 0057
1080009.657: <09>Lane 06 new seed: 0057
1080109.657: <09>Lane 07 scaled delay: 005d
1080209.657: <09>Lane 07 new seed: 005d
1080309.657: <09>Lane 08 scaled delay: 004d
1080409.657: <09>Lane 08 new seed: 004d
1080509.657: <09>Lane 00 nibble 0 raw readback: 005c
1080609.657: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
1080709.657: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
1080809.657: <09>Lane 01 nibble 0 raw readback: 005a
1080909.657: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005a
1081009.657: <09>Lane 01 nibble 0 adjusted value (post nibble): 005a
1081109.657: <09>Lane 02 nibble 0 raw readback: 0053
1081209.657: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
1081309.657: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
1081409.657: <09>Lane 03 nibble 0 raw readback: 004d
1081509.657: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
1081609.657: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
1081709.657: <09>Lane 04 nibble 0 raw readback: 004a
1081809.657: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
1081909.657: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
1082009.657: <09>Lane 05 nibble 0 raw readback: 0051
1082109.657: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
1082209.658: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
1082309.658: <09>Lane 06 nibble 0 raw readback: 0058
1082409.658: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
1082509.658: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
1082609.658: <09>Lane 07 nibble 0 raw readback: 005b
1082709.658: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
1082809.658: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
1082909.658: <09>Lane 08 nibble 0 raw readback: 0047
1083009.658: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
1083109.658: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
1083209.658: AgesaHwWlPhase1: training nibble 1
1083309.658: DIMM 1 RttNom: 5
1083409.658: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1083509.658: DIMM 1 RttWr: 2
1083609.658: DIMM 1 RttWr: 2
1083709.658: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1083809.658: DIMM 1 RttWr: 2
1083909.658: DIMM 1 RttNom: 5
1084009.658: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1084109.658: DIMM 1 RttNom: 5
1084209.658: DIMM 1 RttWr: 2
1084309.658: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1084409.658: DIMM 1 RttWr: 2
1084509.658: DIMM 0 RttNom: 5
1084609.658: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1084709.658: DIMM 1 RttNom: 5
1084809.658: DIMM 0 RttWr: 2
1084909.658: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1085009.658: DIMM 1 RttWr: 2
1085109.658: DIMM 0 RttNom: 5
1085209.658: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1085309.658: DIMM 1 RttNom: 5
1085409.658: DIMM 0 RttWr: 2
1085509.658: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1085609.658: DIMM 1 RttWr: 2
1085709.658: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1085809.658: <09>Lane 00 new seed: 005f
1085909.658: <09>Lane 01 new seed: 0059
1086009.658: <09>Lane 02 new seed: 0055
1086109.658: <09>Lane 03 new seed: 0052
1086209.658: <09>Lane 04 new seed: 004d
1086309.658: <09>Lane 05 new seed: 0052
1086409.658: <09>Lane 06 new seed: 0057
1086509.658: <09>Lane 07 new seed: 005d
1086609.658: <09>Lane 08 new seed: 004d
1086709.658: <09>Lane 00 nibble 1 raw readback: 0060
1086809.658: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
1086909.658: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
1087009.658: <09>Lane 01 nibble 1 raw readback: 0059
1087109.658: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
1087209.658: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
1087309.658: <09>Lane 02 nibble 1 raw readback: 0053
1087409.658: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0053
1087509.658: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
1087609.658: <09>Lane 03 nibble 1 raw readback: 004e
1087709.658: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
1087809.658: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1087909.658: <09>Lane 04 nibble 1 raw readback: 0049
1088009.658: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
1088109.658: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
1088209.658: <09>Lane 05 nibble 1 raw readback: 004f
1088309.658: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
1088409.658: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
1088509.658: <09>Lane 06 nibble 1 raw readback: 0056
1088609.658: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
1088709.658: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
1088809.658: <09>Lane 07 nibble 1 raw readback: 005d
1088909.658: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
1089009.658: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
1089109.658: <09>Lane 08 nibble 1 raw readback: 0048
1089209.658: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
1089309.658: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
1089409.658: <09>original critical gross delay: 0
1089509.658: <09>new critical gross delay: 0
1089609.659: DIMM 1 RttNom: 5
1089709.659: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1089809.659: DIMM 1 RttNom: 5
1089909.659: DIMM 1 RttWr: 2
1090009.659: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1090109.659: DIMM 1 RttWr: 2
1090209.659: DIMM 1 RttNom: 5
1090309.659: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1090409.659: DIMM 1 RttNom: 5
1090509.659: DIMM 1 RttWr: 2
1090609.659: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1090709.659: DIMM 1 RttWr: 2
1090809.659: DIMM 0 RttNom: 5
1090909.659: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1091009.659: DIMM 1 RttNom: 5
1091109.659: DIMM 0 RttWr: 2
1091209.659: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1091309.659: DIMM 1 RttWr: 2
1091409.659: DIMM 0 RttNom: 5
1091509.659: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1091609.659: DIMM 1 RttNom: 5
1091709.659: DIMM 0 RttWr: 2
1091809.659: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1091909.659: DIMM 1 RttWr: 2
1092009.659: SetTargetFreq: Start
1092109.659: SetTargetFreq: Node 1: New frequency code: 0012
1092209.659: ChangeMemClk: Start
1092309.659: set_2t_configuration: Start
1092409.659: set_2t_configuration: Done
1092509.659: mct_BeforePlatformSpec: Start
1092609.659: mct_BeforePlatformSpec: Done
1092709.659: mct_PlatformSpec: Start
1092809.659: Programmed DCT 0 timing/termination pattern 00353935 30222222
1092909.659: mct_PlatformSpec: Done
1093009.659: set_2t_configuration: Start
1093109.659: set_2t_configuration: Done
1093209.659: mct_BeforePlatformSpec: Start
1093309.659: mct_BeforePlatformSpec: Done
1093409.659: mct_PlatformSpec: Start
1093509.659: Programmed DCT 1 timing/termination pattern 00353935 30222222
1093609.659: mct_PlatformSpec: Done
1093709.660: ChangeMemClk: Done
1093809.660: phyAssistedMemFnceTraining: Start
1093909.660: phyAssistedMemFnceTraining: training node 1 DCT 0
1094009.660: phyAssistedMemFnceTraining: done training node 1 DCT 0
1094109.660: phyAssistedMemFnceTraining: training node 1 DCT 1
1094209.660: phyAssistedMemFnceTraining: done training node 1 DCT 1
1094309.660: phyAssistedMemFnceTraining: Done
1094409.660: InitPhyCompensation: DCT 0: Start
1094509.660: Waiting for predriver calibration to be applied...done!
1094609.660: InitPhyCompensation: DCT 0: Done
1094709.660: phyAssistedMemFnceTraining: Start
1094809.660: phyAssistedMemFnceTraining: training node 1 DCT 0
1094909.660: phyAssistedMemFnceTraining: done training node 1 DCT 0
1095009.660: phyAssistedMemFnceTraining: training node 1 DCT 1
1095109.660: phyAssistedMemFnceTraining: done training node 1 DCT 1
1095209.660: phyAssistedMemFnceTraining: Done
1095309.660: InitPhyCompensation: DCT 1: Start
1095409.660: Waiting for predriver calibration to be applied...done!
1095509.660: InitPhyCompensation: DCT 1: Done
1095609.660: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
1095709.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1095809.661: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1095909.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1096009.661: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1096109.661: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
1096209.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1096309.661: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1096409.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1096509.661: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1096609.661: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
1096709.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1096809.661: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1096909.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1097009.661: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1097109.661: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
1097209.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1097309.661: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1097409.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1097509.661: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1097609.661: SetTargetFreq: Done
1097709.661: SPD2ndTiming: Start
1097809.661: SPD2ndTiming: Done
1097909.661: mct_BeforeDramInit_Prod_D: Start
1098009.661: mct_ProgramODT_D: Start
1098109.661: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1098209.661: mct_ProgramODT_D: Done
1098309.661: mct_BeforeDramInit_Prod_D: Done
1098409.661: mct_DramInit_Sw_D: Start
1098509.661: DIMM 0 RttWr: 1
1098609.661: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1098709.661: mct_SendMrsCmd: Start
1098809.661: mct_SendMrsCmd: Done
1098909.661: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1099009.661: mct_SendMrsCmd: Start
1099109.661: mct_SendMrsCmd: Done
1099209.662: DIMM 0 RttNom: 4
1099309.662: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1099409.662: mct_SendMrsCmd: Start
1099509.662: mct_SendMrsCmd: Done
1099609.662: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
1099709.662: mct_SendMrsCmd: Start
1099809.662: mct_SendMrsCmd: Done
1099909.662: DIMM 0 RttWr: 1
1100009.662: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1100109.662: mct_SendMrsCmd: Start
1100209.662: mct_SendMrsCmd: Done
1100309.662: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1100409.662: mct_SendMrsCmd: Start
1100509.662: mct_SendMrsCmd: Done
1100609.662: DIMM 0 RttNom: 4
1100709.662: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1100809.662: mct_SendMrsCmd: Start
1100909.662: mct_SendMrsCmd: Done
1101009.662: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
1101109.662: mct_SendMrsCmd: Start
1101209.662: mct_SendMrsCmd: Done
1101309.662: DIMM 1 RttWr: 1
1101409.662: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1101509.662: mct_SendMrsCmd: Start
1101609.662: mct_SendMrsCmd: Done
1101709.662: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1101809.662: mct_SendMrsCmd: Start
1101909.662: mct_SendMrsCmd: Done
1102009.662: DIMM 1 RttNom: 4
1102109.662: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1102209.662: mct_SendMrsCmd: Start
1102309.662: mct_SendMrsCmd: Done
1102409.662: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
1102509.662: mct_SendMrsCmd: Start
1102609.662: mct_SendMrsCmd: Done
1102709.662: DIMM 1 RttWr: 1
1102809.662: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1102909.662: mct_SendMrsCmd: Start
1103009.662: mct_SendMrsCmd: Done
1103109.662: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1103209.662: mct_SendMrsCmd: Start
1103309.662: mct_SendMrsCmd: Done
1103409.662: DIMM 1 RttNom: 4
1103509.662: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1103609.662: mct_SendMrsCmd: Start
1103709.662: mct_SendMrsCmd: Done
1103809.662: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
1103909.662: mct_SendMrsCmd: Start
1104009.662: mct_SendMrsCmd: Done
1104109.662: mct_DramInit_Sw_D: Done
1104209.662: AgesaHwWlPhase1: training nibble 0
1104309.662: DIMM 0 RttNom: 4
1104409.662: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1104509.663: DIMM 0 RttWr: 1
1104609.663: DIMM 0 RttWr: 1
1104709.663: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1104809.663: DIMM 0 RttWr: 1
1104909.663: DIMM 0 RttNom: 4
1105009.663: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1105109.663: DIMM 0 RttNom: 4
1105209.663: DIMM 0 RttWr: 1
1105309.663: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1105409.663: DIMM 0 RttWr: 1
1105509.663: DIMM 1 RttNom: 4
1105609.663: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1105709.663: DIMM 0 RttNom: 4
1105809.663: DIMM 1 RttWr: 1
1105909.663: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1106009.663: DIMM 0 RttWr: 1
1106109.663: DIMM 1 RttNom: 4
1106209.663: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1106309.663: DIMM 0 RttNom: 4
1106409.663: DIMM 1 RttWr: 1
1106509.663: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1106609.663: DIMM 0 RttWr: 1
1106709.663: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1106809.663: <09>Lane 00 scaled delay: 005f
1106909.663: <09>Lane 00 new seed: 005f
1107009.663: <09>Lane 01 scaled delay: 0058
1107109.663: <09>Lane 01 new seed: 0058
1107209.663: <09>Lane 02 scaled delay: 0053
1107309.663: <09>Lane 02 new seed: 0053
1107409.663: <09>Lane 03 scaled delay: 0052
1107509.663: <09>Lane 03 new seed: 0052
1107609.663: <09>Lane 04 scaled delay: 0049
1107709.663: <09>Lane 04 new seed: 0049
1107809.663: <09>Lane 05 scaled delay: 0051
1107909.663: <09>Lane 05 new seed: 0051
1108009.663: <09>Lane 06 scaled delay: 0054
1108109.663: <09>Lane 06 new seed: 0054
1108209.663: <09>Lane 07 scaled delay: 005a
1108309.663: <09>Lane 07 new seed: 005a
1108409.663: <09>Lane 08 scaled delay: 0047
1108509.663: <09>Lane 08 new seed: 0047
1108609.663: <09>Lane 00 nibble 0 raw readback: 0065
1108709.663: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0065
1108809.663: <09>Lane 00 nibble 0 adjusted value (post nibble): 0065
1108909.663: <09>Lane 01 nibble 0 raw readback: 005c
1109009.663: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005c
1109109.663: <09>Lane 01 nibble 0 adjusted value (post nibble): 005c
1109209.663: <09>Lane 02 nibble 0 raw readback: 0055
1109309.663: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
1109409.663: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
1109509.664: <09>Lane 03 nibble 0 raw readback: 0051
1109609.664: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
1109709.664: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
1109809.664: <09>Lane 04 nibble 0 raw readback: 004c
1109909.664: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
1110009.664: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
1110109.664: <09>Lane 05 nibble 0 raw readback: 0053
1110209.664: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
1110309.664: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
1110409.664: <09>Lane 06 nibble 0 raw readback: 0057
1110509.664: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
1110609.664: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
1110709.664: <09>Lane 07 nibble 0 raw readback: 005e
1110809.664: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005e
1110909.664: <09>Lane 07 nibble 0 adjusted value (post nibble): 005e
1111009.664: <09>Lane 08 nibble 0 raw readback: 0048
1111109.664: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0048
1111209.664: <09>Lane 08 nibble 0 adjusted value (post nibble): 0048
1111309.664: AgesaHwWlPhase1: training nibble 1
1111409.664: DIMM 0 RttNom: 4
1111509.664: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1111609.664: DIMM 0 RttWr: 1
1111709.664: DIMM 0 RttWr: 1
1111809.664: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1111909.664: DIMM 0 RttWr: 1
1112009.664: DIMM 0 RttNom: 4
1112109.664: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1112209.664: DIMM 0 RttNom: 4
1112309.664: DIMM 0 RttWr: 1
1112409.664: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1112509.664: DIMM 0 RttWr: 1
1112609.664: DIMM 1 RttNom: 4
1112709.664: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1112809.664: DIMM 0 RttNom: 4
1112909.664: DIMM 1 RttWr: 1
1113009.664: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1113109.664: DIMM 0 RttWr: 1
1113209.664: DIMM 1 RttNom: 4
1113309.664: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1113409.664: DIMM 0 RttNom: 4
1113509.664: DIMM 1 RttWr: 1
1113609.664: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1113709.664: DIMM 0 RttWr: 1
1113809.664: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1113909.664: <09>Lane 00 new seed: 005f
1114009.664: <09>Lane 01 new seed: 0058
1114109.664: <09>Lane 02 new seed: 0053
1114209.664: <09>Lane 03 new seed: 0052
1114309.664: <09>Lane 04 new seed: 0049
1114409.664: <09>Lane 05 new seed: 0051
1114509.664: <09>Lane 06 new seed: 0054
1114609.664: <09>Lane 07 new seed: 005a
1114709.664: <09>Lane 08 new seed: 0047
1114809.664: <09>Lane 00 nibble 1 raw readback: 0064
1114909.664: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0064
1115009.664: <09>Lane 00 nibble 1 adjusted value (post nibble): 0061
1115109.664: <09>Lane 01 nibble 1 raw readback: 005c
1115209.664: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005c
1115309.664: <09>Lane 01 nibble 1 adjusted value (post nibble): 005a
1115409.664: <09>Lane 02 nibble 1 raw readback: 0056
1115509.664: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
1115609.664: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
1115709.664: <09>Lane 03 nibble 1 raw readback: 0051
1115809.664: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
1115909.664: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
1116009.664: <09>Lane 04 nibble 1 raw readback: 004b
1116109.664: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
1116209.664: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
1116309.665: <09>Lane 05 nibble 1 raw readback: 0052
1116409.664: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
1116509.665: <09>Lane 05 nibble 1 adjusted value (post nibble): 0051
1116609.665: <09>Lane 06 nibble 1 raw readback: 0058
1116709.665: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
1116809.665: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
1116909.665: <09>Lane 07 nibble 1 raw readback: 005e
1117009.665: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005e
1117109.665: <09>Lane 07 nibble 1 adjusted value (post nibble): 005c
1117209.665: <09>Lane 08 nibble 1 raw readback: 0048
1117309.665: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
1117409.665: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
1117509.665: <09>original critical gross delay: 0
1117609.665: <09>new critical gross delay: 0
1117709.665: DIMM 0 RttNom: 4
1117809.665: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1117909.665: DIMM 0 RttNom: 4
1118009.665: DIMM 0 RttWr: 1
1118109.665: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1118209.665: DIMM 0 RttWr: 1
1118309.665: DIMM 0 RttNom: 4
1118409.665: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1118509.665: DIMM 0 RttNom: 4
1118609.665: DIMM 0 RttWr: 1
1118709.665: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1118809.665: DIMM 0 RttWr: 1
1118909.665: DIMM 1 RttNom: 4
1119009.665: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1119109.665: DIMM 0 RttNom: 4
1119209.665: DIMM 1 RttWr: 1
1119309.665: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1119409.665: DIMM 0 RttWr: 1
1119509.665: DIMM 1 RttNom: 4
1119609.665: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1119709.665: DIMM 0 RttNom: 4
1119809.665: DIMM 1 RttWr: 1
1119909.665: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1120009.665: DIMM 0 RttWr: 1
1120109.665: AgesaHwWlPhase1: training nibble 0
1120209.665: DIMM 1 RttNom: 4
1120309.665: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1120409.665: DIMM 1 RttWr: 1
1120509.665: DIMM 1 RttWr: 1
1120609.665: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1120709.665: DIMM 1 RttWr: 1
1120809.665: DIMM 1 RttNom: 4
1120909.665: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1121009.665: DIMM 1 RttNom: 4
1121109.665: DIMM 1 RttWr: 1
1121209.665: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1121309.665: DIMM 1 RttWr: 1
1121409.665: DIMM 0 RttNom: 4
1121509.665: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1121609.665: DIMM 1 RttNom: 4
1121709.665: DIMM 0 RttWr: 1
1121809.665: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1121909.665: DIMM 1 RttWr: 1
1122009.665: DIMM 0 RttNom: 4
1122109.665: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1122209.665: DIMM 1 RttNom: 4
1122309.666: DIMM 0 RttWr: 1
1122409.666: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1122509.666: DIMM 1 RttWr: 1
1122609.666: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1122709.666: <09>Lane 00 scaled delay: 0069
1122809.666: <09>Lane 00 new seed: 0069
1122909.666: <09>Lane 01 scaled delay: 0060
1123009.666: <09>Lane 01 new seed: 0060
1123109.666: <09>Lane 02 scaled delay: 005a
1123209.666: <09>Lane 02 new seed: 005a
1123309.666: <09>Lane 03 scaled delay: 0058
1123409.666: <09>Lane 03 new seed: 0058
1123509.666: <09>Lane 04 scaled delay: 0052
1123609.666: <09>Lane 04 new seed: 0052
1123709.666: <09>Lane 05 scaled delay: 0059
1123809.666: <09>Lane 05 new seed: 0059
1123909.666: <09>Lane 06 scaled delay: 005d
1124009.666: <09>Lane 06 new seed: 005d
1124109.666: <09>Lane 07 scaled delay: 0063
1124209.666: <09>Lane 07 new seed: 0063
1124309.666: <09>Lane 08 scaled delay: 0051
1124409.666: <09>Lane 08 new seed: 0051
1124509.666: <09>Lane 00 nibble 0 raw readback: 0030
1124609.666: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
1124709.666: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
1124809.666: <09>Lane 01 nibble 0 raw readback: 0026
1124909.666: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
1125009.666: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
1125109.666: <09>Lane 02 nibble 0 raw readback: 005d
1125209.666: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
1125309.666: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
1125409.666: <09>Lane 03 nibble 0 raw readback: 005c
1125509.666: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
1125609.666: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
1125709.666: <09>Lane 04 nibble 0 raw readback: 0057
1125809.666: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
1125909.666: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
1126009.666: <09>Lane 05 nibble 0 raw readback: 005f
1126109.666: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005f
1126209.666: <09>Lane 05 nibble 0 adjusted value (post nibble): 005f
1126309.666: <09>Lane 06 nibble 0 raw readback: 0060
1126409.666: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0060
1126509.666: <09>Lane 06 nibble 0 adjusted value (post nibble): 0060
1126609.666: <09>Lane 07 nibble 0 raw readback: 0029
1126709.666: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
1126809.666: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
1126909.666: <09>Lane 08 nibble 0 raw readback: 0052
1127009.666: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0052
1127109.666: <09>Lane 08 nibble 0 adjusted value (post nibble): 0052
1127209.666: AgesaHwWlPhase1: training nibble 1
1127309.666: DIMM 1 RttNom: 4
1127409.666: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1127509.666: DIMM 1 RttWr: 1
1127609.666: DIMM 1 RttWr: 1
1127709.666: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1127809.666: DIMM 1 RttWr: 1
1127909.666: DIMM 1 RttNom: 4
1128009.666: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1128109.666: DIMM 1 RttNom: 4
1128209.666: DIMM 1 RttWr: 1
1128309.666: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1128409.666: DIMM 1 RttWr: 1
1128509.666: DIMM 0 RttNom: 4
1128609.666: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1128709.666: DIMM 1 RttNom: 4
1128809.666: DIMM 0 RttWr: 1
1128909.666: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1129009.666: DIMM 1 RttWr: 1
1129109.666: DIMM 0 RttNom: 4
1129209.666: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1129309.666: DIMM 1 RttNom: 4
1129409.666: DIMM 0 RttWr: 1
1129509.666: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1129609.667: DIMM 1 RttWr: 1
1129709.667: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1129809.667: <09>Lane 00 new seed: 0069
1129909.667: <09>Lane 01 new seed: 0060
1130009.667: <09>Lane 02 new seed: 005a
1130109.667: <09>Lane 03 new seed: 0058
1130209.667: <09>Lane 04 new seed: 0052
1130309.667: <09>Lane 05 new seed: 0059
1130409.667: <09>Lane 06 new seed: 005d
1130509.667: <09>Lane 07 new seed: 0063
1130609.667: <09>Lane 08 new seed: 0051
1130709.667: <09>Lane 00 nibble 1 raw readback: 0030
1130809.667: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
1130909.667: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
1131009.667: <09>Lane 01 nibble 1 raw readback: 0025
1131109.667: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
1131209.667: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
1131309.667: <09>Lane 02 nibble 1 raw readback: 005d
1131409.667: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005d
1131509.667: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
1131609.667: <09>Lane 03 nibble 1 raw readback: 005b
1131709.667: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
1131809.667: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
1131909.667: <09>Lane 04 nibble 1 raw readback: 0054
1132009.667: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
1132109.667: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
1132209.667: <09>Lane 05 nibble 1 raw readback: 005c
1132309.667: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
1132409.667: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
1132509.667: <09>Lane 06 nibble 1 raw readback: 0061
1132609.667: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0061
1132709.667: <09>Lane 06 nibble 1 adjusted value (post nibble): 005f
1132809.667: <09>Lane 07 nibble 1 raw readback: 0028
1132909.667: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
1133009.667: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
1133109.667: <09>Lane 08 nibble 1 raw readback: 0054
1133209.667: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0054
1133309.667: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
1133409.667: <09>original critical gross delay: 0
1133509.667: <09>new critical gross delay: 0
1133609.667: DIMM 1 RttNom: 4
1133709.667: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1133809.667: DIMM 1 RttNom: 4
1133909.667: DIMM 1 RttWr: 1
1134009.667: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1134109.667: DIMM 1 RttWr: 1
1134209.667: DIMM 1 RttNom: 4
1134309.667: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1134409.667: DIMM 1 RttNom: 4
1134509.667: DIMM 1 RttWr: 1
1134609.667: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1134709.667: DIMM 1 RttWr: 1
1134809.667: DIMM 0 RttNom: 4
1134909.667: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1135009.667: DIMM 1 RttNom: 4
1135109.667: DIMM 0 RttWr: 1
1135209.667: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1135309.667: DIMM 1 RttWr: 1
1135409.667: DIMM 0 RttNom: 4
1135509.667: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1135609.667: DIMM 1 RttNom: 4
1135709.668: DIMM 0 RttWr: 1
1135809.667: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1135909.667: DIMM 1 RttWr: 1
1136009.668: SPD2ndTiming: Start
1136109.668: SPD2ndTiming: Done
1136209.668: mct_BeforeDramInit_Prod_D: Start
1136309.668: mct_ProgramODT_D: Start
1136409.668: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1136509.668: mct_ProgramODT_D: Done
1136609.668: mct_BeforeDramInit_Prod_D: Done
1136709.668: mct_DramInit_Sw_D: Start
1136809.668: DIMM 0 RttWr: 1
1136909.668: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1137009.668: mct_SendMrsCmd: Start
1137109.668: mct_SendMrsCmd: Done
1137209.668: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1137309.668: mct_SendMrsCmd: Start
1137409.668: mct_SendMrsCmd: Done
1137509.668: DIMM 0 RttNom: 4
1137609.668: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1137709.668: mct_SendMrsCmd: Start
1137809.668: mct_SendMrsCmd: Done
1137909.668: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
1138009.668: mct_SendMrsCmd: Start
1138109.668: mct_SendMrsCmd: Done
1138209.668: DIMM 0 RttWr: 1
1138309.668: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1138409.668: mct_SendMrsCmd: Start
1138509.668: mct_SendMrsCmd: Done
1138609.668: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1138709.668: mct_SendMrsCmd: Start
1138809.668: mct_SendMrsCmd: Done
1138909.668: DIMM 0 RttNom: 4
1139009.668: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1139109.668: mct_SendMrsCmd: Start
1139209.668: mct_SendMrsCmd: Done
1139309.668: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
1139409.668: mct_SendMrsCmd: Start
1139509.668: mct_SendMrsCmd: Done
1139609.668: DIMM 1 RttWr: 1
1139709.669: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1139809.668: mct_SendMrsCmd: Start
1139909.669: mct_SendMrsCmd: Done
1140009.669: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1140109.669: mct_SendMrsCmd: Start
1140209.669: mct_SendMrsCmd: Done
1140309.669: DIMM 1 RttNom: 4
1140409.669: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1140509.669: mct_SendMrsCmd: Start
1140609.669: mct_SendMrsCmd: Done
1140709.669: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
1140809.669: mct_SendMrsCmd: Start
1140909.669: mct_SendMrsCmd: Done
1141009.669: DIMM 1 RttWr: 1
1141109.669: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1141209.669: mct_SendMrsCmd: Start
1141309.669: mct_SendMrsCmd: Done
1141409.669: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1141509.669: mct_SendMrsCmd: Start
1141609.669: mct_SendMrsCmd: Done
1141709.669: DIMM 1 RttNom: 4
1141809.669: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1141909.669: mct_SendMrsCmd: Start
1142009.669: mct_SendMrsCmd: Done
1142109.669: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
1142209.669: mct_SendMrsCmd: Start
1142309.669: mct_SendMrsCmd: Done
1142409.669: mct_DramInit_Sw_D: Done
1142509.669: AgesaHwWlPhase1: training nibble 0
1142609.669: DIMM 0 RttNom: 4
1142709.669: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1142809.669: DIMM 0 RttWr: 1
1142909.669: DIMM 0 RttWr: 1
1143009.669: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1143109.669: DIMM 0 RttWr: 1
1143209.669: DIMM 0 RttNom: 4
1143309.669: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1143409.669: DIMM 0 RttNom: 4
1143509.669: DIMM 0 RttWr: 1
1143609.669: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1143709.669: DIMM 0 RttWr: 1
1143809.669: DIMM 1 RttNom: 4
1143909.669: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1144009.669: DIMM 0 RttNom: 4
1144109.669: DIMM 1 RttWr: 1
1144209.669: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1144309.669: DIMM 0 RttWr: 1
1144409.669: DIMM 1 RttNom: 4
1144509.669: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1144609.669: DIMM 0 RttNom: 4
1144709.669: DIMM 1 RttWr: 1
1144809.669: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1144909.669: DIMM 0 RttWr: 1
1145009.669: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1145109.669: <09>Lane 00 scaled delay: 0063
1145209.669: <09>Lane 00 new seed: 0063
1145309.669: <09>Lane 01 scaled delay: 005b
1145409.669: <09>Lane 01 new seed: 005b
1145509.669: <09>Lane 02 scaled delay: 0055
1145609.669: <09>Lane 02 new seed: 0055
1145709.669: <09>Lane 03 scaled delay: 0051
1145809.670: <09>Lane 03 new seed: 0051
1145909.670: <09>Lane 04 scaled delay: 004c
1146009.670: <09>Lane 04 new seed: 004c
1146109.670: <09>Lane 05 scaled delay: 0053
1146209.670: <09>Lane 05 new seed: 0053
1146309.670: <09>Lane 06 scaled delay: 0059
1146409.670: <09>Lane 06 new seed: 0059
1146509.670: <09>Lane 07 scaled delay: 0061
1146609.670: <09>Lane 07 new seed: 0061
1146709.670: <09>Lane 08 scaled delay: 0048
1146809.670: <09>Lane 08 new seed: 0048
1146909.670: <09>Lane 00 nibble 0 raw readback: 0027
1147009.670: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0067
1147109.670: <09>Lane 00 nibble 0 adjusted value (post nibble): 0067
1147209.670: <09>Lane 01 nibble 0 raw readback: 005d
1147309.670: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005d
1147409.670: <09>Lane 01 nibble 0 adjusted value (post nibble): 005d
1147509.670: <09>Lane 02 nibble 0 raw readback: 0056
1147609.670: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0056
1147709.670: <09>Lane 02 nibble 0 adjusted value (post nibble): 0056
1147809.670: <09>Lane 03 nibble 0 raw readback: 004f
1147909.670: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
1148009.670: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
1148109.670: <09>Lane 04 nibble 0 raw readback: 004c
1148209.670: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
1148309.670: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
1148409.670: <09>Lane 05 nibble 0 raw readback: 0056
1148509.670: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0056
1148609.670: <09>Lane 05 nibble 0 adjusted value (post nibble): 0056
1148709.670: <09>Lane 06 nibble 0 raw readback: 005a
1148809.670: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005a
1148909.670: <09>Lane 06 nibble 0 adjusted value (post nibble): 005a
1149009.670: <09>Lane 07 nibble 0 raw readback: 0021
1149109.670: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0061
1149209.670: <09>Lane 07 nibble 0 adjusted value (post nibble): 0061
1149309.670: <09>Lane 08 nibble 0 raw readback: 004a
1149409.670: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
1149509.670: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
1149609.670: AgesaHwWlPhase1: training nibble 1
1149709.670: DIMM 0 RttNom: 4
1149809.670: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1149909.670: DIMM 0 RttWr: 1
1150009.670: DIMM 0 RttWr: 1
1150109.670: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1150209.670: DIMM 0 RttWr: 1
1150309.670: DIMM 0 RttNom: 4
1150409.670: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1150509.670: DIMM 0 RttNom: 4
1150609.670: DIMM 0 RttWr: 1
1150709.670: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1150809.670: DIMM 0 RttWr: 1
1150909.670: DIMM 1 RttNom: 4
1151009.670: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1151109.670: DIMM 0 RttNom: 4
1151209.670: DIMM 1 RttWr: 1
1151309.670: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1151409.670: DIMM 0 RttWr: 1
1151509.670: DIMM 1 RttNom: 4
1151609.670: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1151709.670: DIMM 0 RttNom: 4
1151809.670: DIMM 1 RttWr: 1
1151909.670: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1152009.670: DIMM 0 RttWr: 1
1152109.670: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1152209.671: <09>Lane 00 new seed: 0063
1152309.671: <09>Lane 01 new seed: 005b
1152409.671: <09>Lane 02 new seed: 0055
1152509.671: <09>Lane 03 new seed: 0051
1152609.671: <09>Lane 04 new seed: 004c
1152709.671: <09>Lane 05 new seed: 0053
1152809.671: <09>Lane 06 new seed: 0059
1152909.671: <09>Lane 07 new seed: 0061
1153009.671: <09>Lane 08 new seed: 0048
1153109.671: <09>Lane 00 nibble 1 raw readback: 0026
1153209.671: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0066
1153309.671: <09>Lane 00 nibble 1 adjusted value (post nibble): 0064
1153409.671: <09>Lane 01 nibble 1 raw readback: 005e
1153509.671: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005e
1153609.671: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
1153709.671: <09>Lane 02 nibble 1 raw readback: 0056
1153809.671: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
1153909.671: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
1154009.671: <09>Lane 03 nibble 1 raw readback: 0050
1154109.671: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
1154209.671: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1154309.671: <09>Lane 04 nibble 1 raw readback: 004c
1154409.671: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
1154509.671: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
1154609.671: <09>Lane 05 nibble 1 raw readback: 0054
1154709.671: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0054
1154809.671: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
1154909.671: <09>Lane 06 nibble 1 raw readback: 005b
1155009.671: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005b
1155109.671: <09>Lane 06 nibble 1 adjusted value (post nibble): 005a
1155209.671: <09>Lane 07 nibble 1 raw readback: 0024
1155309.671: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0064
1155409.671: <09>Lane 07 nibble 1 adjusted value (post nibble): 0062
1155509.671: <09>Lane 08 nibble 1 raw readback: 0049
1155609.671: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0049
1155709.671: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
1155809.671: <09>original critical gross delay: 0
1155909.671: <09>new critical gross delay: 0
1156009.671: DIMM 0 RttNom: 4
1156109.671: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1156209.671: DIMM 0 RttNom: 4
1156309.671: DIMM 0 RttWr: 1
1156409.671: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1156509.671: DIMM 0 RttWr: 1
1156609.671: DIMM 0 RttNom: 4
1156709.671: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1156809.671: DIMM 0 RttNom: 4
1156909.671: DIMM 0 RttWr: 1
1157009.671: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1157109.671: DIMM 0 RttWr: 1
1157209.671: DIMM 1 RttNom: 4
1157309.671: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1157409.671: DIMM 0 RttNom: 4
1157509.671: DIMM 1 RttWr: 1
1157609.671: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1157709.671: DIMM 0 RttWr: 1
1157809.671: DIMM 1 RttNom: 4
1157909.671: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1158009.671: DIMM 0 RttNom: 4
1158109.671: DIMM 1 RttWr: 1
1158209.671: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1158309.671: DIMM 0 RttWr: 1
1158409.671: AgesaHwWlPhase1: training nibble 0
1158509.672: DIMM 1 RttNom: 4
1158609.672: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1158709.672: DIMM 1 RttWr: 1
1158809.672: DIMM 1 RttWr: 1
1158909.672: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1159009.672: DIMM 1 RttWr: 1
1159109.672: DIMM 1 RttNom: 4
1159209.672: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1159309.672: DIMM 1 RttNom: 4
1159409.672: DIMM 1 RttWr: 1
1159509.672: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1159609.672: DIMM 1 RttWr: 1
1159709.672: DIMM 0 RttNom: 4
1159809.672: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1159909.672: DIMM 1 RttNom: 4
1160009.672: DIMM 0 RttWr: 1
1160109.672: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1160209.672: DIMM 1 RttWr: 1
1160309.672: DIMM 0 RttNom: 4
1160409.672: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1160509.672: DIMM 1 RttNom: 4
1160609.672: DIMM 0 RttWr: 1
1160709.672: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1160809.672: DIMM 1 RttWr: 1
1160909.672: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1161009.672: <09>Lane 00 scaled delay: 006b
1161109.672: <09>Lane 00 new seed: 006b
1161209.672: <09>Lane 01 scaled delay: 0064
1161309.672: <09>Lane 01 new seed: 0064
1161409.672: <09>Lane 02 scaled delay: 005e
1161509.672: <09>Lane 02 new seed: 005e
1161609.672: <09>Lane 03 scaled delay: 0059
1161709.672: <09>Lane 03 new seed: 0059
1161809.672: <09>Lane 04 scaled delay: 0053
1161909.672: <09>Lane 04 new seed: 0053
1162009.672: <09>Lane 05 scaled delay: 0059
1162109.672: <09>Lane 05 new seed: 0059
1162209.672: <09>Lane 06 scaled delay: 0060
1162309.672: <09>Lane 06 new seed: 0060
1162409.672: <09>Lane 07 scaled delay: 0069
1162509.672: <09>Lane 07 new seed: 0069
1162609.672: <09>Lane 08 scaled delay: 0052
1162709.672: <09>Lane 08 new seed: 0052
1162809.672: <09>Lane 00 nibble 0 raw readback: 0029
1162909.672: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0069
1163009.672: <09>Lane 00 nibble 0 adjusted value (post nibble): 0069
1163109.672: <09>Lane 01 nibble 0 raw readback: 0027
1163209.672: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
1163309.672: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
1163409.672: <09>Lane 02 nibble 0 raw readback: 005e
1163509.672: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005e
1163609.672: <09>Lane 02 nibble 0 adjusted value (post nibble): 005e
1163709.672: <09>Lane 03 nibble 0 raw readback: 0057
1163809.672: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0057
1163909.672: <09>Lane 03 nibble 0 adjusted value (post nibble): 0057
1164009.672: <09>Lane 04 nibble 0 raw readback: 0055
1164109.672: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
1164209.672: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
1164309.672: <09>Lane 05 nibble 0 raw readback: 005d
1164409.672: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
1164509.672: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
1164609.672: <09>Lane 06 nibble 0 raw readback: 0024
1164709.672: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
1164809.672: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
1164909.672: <09>Lane 07 nibble 0 raw readback: 0028
1165009.672: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0068
1165109.672: <09>Lane 07 nibble 0 adjusted value (post nibble): 0068
1165209.672: <09>Lane 08 nibble 0 raw readback: 0050
1165309.672: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0050
1165409.672: <09>Lane 08 nibble 0 adjusted value (post nibble): 0050
1165509.672: AgesaHwWlPhase1: training nibble 1
1165609.672: DIMM 1 RttNom: 4
1165709.673: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1165809.673: DIMM 1 RttWr: 1
1165909.673: DIMM 1 RttWr: 1
1166009.673: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1166109.673: DIMM 1 RttWr: 1
1166209.673: DIMM 1 RttNom: 4
1166309.673: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1166409.673: DIMM 1 RttNom: 4
1166509.673: DIMM 1 RttWr: 1
1166609.673: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1166709.673: DIMM 1 RttWr: 1
1166809.673: DIMM 0 RttNom: 4
1166909.673: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1167009.673: DIMM 1 RttNom: 4
1167109.673: DIMM 0 RttWr: 1
1167209.673: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1167309.673: DIMM 1 RttWr: 1
1167409.673: DIMM 0 RttNom: 4
1167509.673: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1167609.673: DIMM 1 RttNom: 4
1167709.673: DIMM 0 RttWr: 1
1167809.673: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1167909.673: DIMM 1 RttWr: 1
1168009.673: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1168109.673: <09>Lane 00 new seed: 006b
1168209.673: <09>Lane 01 new seed: 0064
1168309.673: <09>Lane 02 new seed: 005e
1168409.673: <09>Lane 03 new seed: 0059
1168509.673: <09>Lane 04 new seed: 0053
1168609.673: <09>Lane 05 new seed: 0059
1168709.673: <09>Lane 06 new seed: 0060
1168809.673: <09>Lane 07 new seed: 0069
1168909.673: <09>Lane 08 new seed: 0052
1169009.673: <09>Lane 00 nibble 1 raw readback: 002f
1169109.673: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
1169209.673: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
1169309.673: <09>Lane 01 nibble 1 raw readback: 0027
1169409.673: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
1169509.673: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
1169609.673: <09>Lane 02 nibble 1 raw readback: 005e
1169709.673: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
1169809.673: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
1169909.673: <09>Lane 03 nibble 1 raw readback: 0059
1170009.673: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
1170109.673: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
1170209.673: <09>Lane 04 nibble 1 raw readback: 0053
1170309.673: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0053
1170409.673: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
1170509.673: <09>Lane 05 nibble 1 raw readback: 005a
1170609.673: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005a
1170709.673: <09>Lane 05 nibble 1 adjusted value (post nibble): 0059
1170809.673: <09>Lane 06 nibble 1 raw readback: 0022
1170909.673: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0062
1171009.673: <09>Lane 06 nibble 1 adjusted value (post nibble): 0061
1171109.673: <09>Lane 07 nibble 1 raw readback: 002b
1171209.673: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
1171309.673: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
1171409.673: <09>Lane 08 nibble 1 raw readback: 0052
1171509.673: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0052
1171609.673: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
1171709.673: <09>original critical gross delay: 0
1171809.673: <09>new critical gross delay: 0
1171909.674: DIMM 1 RttNom: 4
1172009.673: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1172109.673: DIMM 1 RttNom: 4
1172209.674: DIMM 1 RttWr: 1
1172309.673: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1172409.674: DIMM 1 RttWr: 1
1172509.674: DIMM 1 RttNom: 4
1172609.674: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1172709.674: DIMM 1 RttNom: 4
1172809.674: DIMM 1 RttWr: 1
1172909.674: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1173009.674: DIMM 1 RttWr: 1
1173109.674: DIMM 0 RttNom: 4
1173209.674: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1173309.674: DIMM 1 RttNom: 4
1173409.674: DIMM 0 RttWr: 1
1173509.674: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1173609.674: DIMM 1 RttWr: 1
1173709.674: DIMM 0 RttNom: 4
1173809.674: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1173909.674: DIMM 1 RttNom: 4
1174009.674: DIMM 0 RttWr: 1
1174109.674: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1174209.674: DIMM 1 RttWr: 1
1174309.674: activate_spd_rom() for node 02
1174409.674: enable_spd_node2()
1174509.674: SetTargetFreq: Start
1174609.674: SetTargetFreq: Node 2: New frequency code: 0006
1174709.674: ChangeMemClk: Start
1174809.674: set_2t_configuration: Start
1174909.674: set_2t_configuration: Done
1175009.675: mct_BeforePlatformSpec: Start
1175109.675: mct_BeforePlatformSpec: Done
1175209.675: mct_PlatformSpec: Start
1175309.675: Programmed DCT 0 timing/termination pattern 00000000 20222222
1175409.675: mct_PlatformSpec: Done
1175509.675: set_2t_configuration: Start
1175609.675: set_2t_configuration: Done
1175709.675: mct_BeforePlatformSpec: Start
1175809.675: mct_BeforePlatformSpec: Done
1175909.675: mct_PlatformSpec: Start
1176009.675: Programmed DCT 1 timing/termination pattern 00000000 20222222
1176109.675: mct_PlatformSpec: Done
1176209.675: ChangeMemClk: Done
1176309.675: phyAssistedMemFnceTraining: Start
1176409.675: phyAssistedMemFnceTraining: training node 2 DCT 0
1176509.675: phyAssistedMemFnceTraining: done training node 2 DCT 0
1176609.675: phyAssistedMemFnceTraining: training node 2 DCT 1
1176709.675: phyAssistedMemFnceTraining: done training node 2 DCT 1
1176809.675: phyAssistedMemFnceTraining: Done
1176909.675: InitPhyCompensation: DCT 0: Start
1177009.675: Waiting for predriver calibration to be applied...done!
1177109.675: InitPhyCompensation: DCT 0: Done
1177209.675: phyAssistedMemFnceTraining: Start
1177309.675: phyAssistedMemFnceTraining: training node 2 DCT 0
1177409.676: phyAssistedMemFnceTraining: done training node 2 DCT 0
1177509.676: phyAssistedMemFnceTraining: training node 2 DCT 1
1177609.676: phyAssistedMemFnceTraining: done training node 2 DCT 1
1177709.676: phyAssistedMemFnceTraining: Done
1177809.676: InitPhyCompensation: DCT 1: Start
1177909.676: Waiting for predriver calibration to be applied...done!
1178009.676: InitPhyCompensation: DCT 1: Done
1178109.676: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
1178209.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1178309.676: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1178409.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1178509.676: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1178609.676: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
1178709.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1178809.676: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1178909.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1179009.676: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1179109.676: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
1179209.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1179309.676: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1179409.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1179509.676: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1179609.676: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
1179709.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1179809.676: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1179909.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1180009.676: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1180109.676: SetTargetFreq: Done
1180209.676: SPD2ndTiming: Start
1180309.677: SPD2ndTiming: Done
1180409.677: mct_BeforeDramInit_Prod_D: Start
1180509.677: mct_ProgramODT_D: Start
1180609.677: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1180709.677: mct_ProgramODT_D: Done
1180809.677: mct_BeforeDramInit_Prod_D: Done
1180909.677: mct_DramInit_Sw_D: Start
1181009.677: DIMM 0 RttWr: 2
1181109.677: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1181209.677: mct_SendMrsCmd: Start
1181309.677: mct_SendMrsCmd: Done
1181409.677: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1181509.677: mct_SendMrsCmd: Start
1181609.677: mct_SendMrsCmd: Done
1181709.677: DIMM 0 RttNom: 3
1181809.677: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1181909.677: mct_SendMrsCmd: Start
1182009.677: mct_SendMrsCmd: Done
1182109.677: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
1182209.677: mct_SendMrsCmd: Start
1182309.677: mct_SendMrsCmd: Done
1182409.677: DIMM 0 RttWr: 2
1182509.677: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1182609.677: mct_SendMrsCmd: Start
1182709.677: mct_SendMrsCmd: Done
1182809.677: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1182909.677: mct_SendMrsCmd: Start
1183009.677: mct_SendMrsCmd: Done
1183109.677: DIMM 0 RttNom: 3
1183209.677: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1183309.677: mct_SendMrsCmd: Start
1183409.677: mct_SendMrsCmd: Done
1183509.677: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
1183609.677: mct_SendMrsCmd: Start
1183709.677: mct_SendMrsCmd: Done
1183809.677: DIMM 1 RttWr: 2
1183909.677: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1184009.677: mct_SendMrsCmd: Start
1184109.677: mct_SendMrsCmd: Done
1184209.677: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1184309.677: mct_SendMrsCmd: Start
1184409.677: mct_SendMrsCmd: Done
1184509.677: DIMM 1 RttNom: 3
1184609.677: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1184709.677: mct_SendMrsCmd: Start
1184809.678: mct_SendMrsCmd: Done
1184909.678: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
1185009.678: mct_SendMrsCmd: Start
1185109.678: mct_SendMrsCmd: Done
1185209.678: DIMM 1 RttWr: 2
1185309.678: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1185409.678: mct_SendMrsCmd: Start
1185509.678: mct_SendMrsCmd: Done
1185609.678: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1185709.678: mct_SendMrsCmd: Start
1185809.678: mct_SendMrsCmd: Done
1185909.678: DIMM 1 RttNom: 3
1186009.678: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1186109.678: mct_SendMrsCmd: Start
1186209.678: mct_SendMrsCmd: Done
1186309.678: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
1186409.678: mct_SendMrsCmd: Start
1186509.678: mct_SendMrsCmd: Done
1186609.678: mct_DramInit_Sw_D: Done
1186709.678: AgesaHwWlPhase1: training nibble 0
1186809.678: DIMM 0 RttNom: 3
1186909.678: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1187009.678: DIMM 0 RttWr: 2
1187109.678: DIMM 0 RttWr: 2
1187209.678: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1187309.678: DIMM 0 RttWr: 2
1187409.678: DIMM 0 RttNom: 3
1187509.678: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1187609.678: DIMM 0 RttNom: 3
1187709.678: DIMM 0 RttWr: 2
1187809.678: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1187909.678: DIMM 0 RttWr: 2
1188009.678: DIMM 1 RttNom: 3
1188109.678: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1188209.678: DIMM 0 RttNom: 3
1188309.678: DIMM 1 RttWr: 2
1188409.678: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1188509.678: DIMM 0 RttWr: 2
1188609.678: DIMM 1 RttNom: 3
1188709.678: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1188809.678: DIMM 0 RttNom: 3
1188909.678: DIMM 1 RttWr: 2
1189009.678: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1189109.678: DIMM 0 RttWr: 2
1189209.678: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1189309.678: <09>Lane 00 scaled delay: 0047
1189409.679: <09>Lane 00 new seed: 0047
1189509.679: <09>Lane 01 scaled delay: 0047
1189609.679: <09>Lane 01 new seed: 0047
1189709.679: <09>Lane 02 scaled delay: 0047
1189809.679: <09>Lane 02 new seed: 0047
1189909.679: <09>Lane 03 scaled delay: 0047
1190009.679: <09>Lane 03 new seed: 0047
1190109.679: <09>Lane 04 scaled delay: 0047
1190209.679: <09>Lane 04 new seed: 0047
1190309.679: <09>Lane 05 scaled delay: 0047
1190409.679: <09>Lane 05 new seed: 0047
1190509.679: <09>Lane 06 scaled delay: 0047
1190609.679: <09>Lane 06 new seed: 0047
1190709.679: <09>Lane 07 scaled delay: 0047
1190809.679: <09>Lane 07 new seed: 0047
1190909.679: <09>Lane 08 scaled delay: 0047
1191009.679: <09>Lane 08 new seed: 0047
1191109.679: <09>Lane 00 nibble 0 raw readback: 004f
1191209.679: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004f
1191309.679: <09>Lane 00 nibble 0 adjusted value (post nibble): 004f
1191409.679: <09>Lane 01 nibble 0 raw readback: 0048
1191509.679: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0048
1191609.679: <09>Lane 01 nibble 0 adjusted value (post nibble): 0048
1191709.679: <09>Lane 02 nibble 0 raw readback: 0047
1191809.679: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
1191909.679: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
1192009.679: <09>Lane 03 nibble 0 raw readback: 0044
1192109.679: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
1192209.679: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
1192309.679: <09>Lane 04 nibble 0 raw readback: 003b
1192409.679: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
1192509.679: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
1192609.679: <09>Lane 05 nibble 0 raw readback: 003e
1192709.679: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
1192809.679: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
1192909.679: <09>Lane 06 nibble 0 raw readback: 0040
1193009.679: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
1193109.679: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
1193209.679: <09>Lane 07 nibble 0 raw readback: 0043
1193309.679: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
1193409.679: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
1193509.679: <09>Lane 08 nibble 0 raw readback: 003c
1193609.679: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
1193709.679: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
1193809.679: AgesaHwWlPhase1: training nibble 1
1193909.679: DIMM 0 RttNom: 3
1194009.679: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1194109.679: DIMM 0 RttWr: 2
1194209.679: DIMM 0 RttWr: 2
1194309.679: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1194409.679: DIMM 0 RttWr: 2
1194509.679: DIMM 0 RttNom: 3
1194609.679: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1194709.679: DIMM 0 RttNom: 3
1194809.679: DIMM 0 RttWr: 2
1194909.679: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1195009.679: DIMM 0 RttWr: 2
1195109.679: DIMM 1 RttNom: 3
1195209.679: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1195309.679: DIMM 0 RttNom: 3
1195409.680: DIMM 1 RttWr: 2
1195509.680: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1195609.680: DIMM 0 RttWr: 2
1195709.680: DIMM 1 RttNom: 3
1195809.680: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1195909.680: DIMM 0 RttNom: 3
1196009.680: DIMM 1 RttWr: 2
1196109.680: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1196209.680: DIMM 0 RttWr: 2
1196309.680: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1196409.680: <09>Lane 00 new seed: 0047
1196509.680: <09>Lane 01 new seed: 0047
1196609.680: <09>Lane 02 new seed: 0047
1196709.680: <09>Lane 03 new seed: 0047
1196809.680: <09>Lane 04 new seed: 0047
1196909.680: <09>Lane 05 new seed: 0047
1197009.680: <09>Lane 06 new seed: 0047
1197109.680: <09>Lane 07 new seed: 0047
1197209.680: <09>Lane 08 new seed: 0047
1197309.680: <09>Lane 00 nibble 1 raw readback: 004f
1197409.680: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
1197509.680: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
1197609.680: <09>Lane 01 nibble 1 raw readback: 004a
1197709.680: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
1197809.680: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
1197909.680: <09>Lane 02 nibble 1 raw readback: 0048
1198009.680: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0048
1198109.680: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
1198209.680: <09>Lane 03 nibble 1 raw readback: 0045
1198309.680: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
1198409.680: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
1198509.680: <09>Lane 04 nibble 1 raw readback: 0039
1198609.680: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
1198709.680: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
1198809.680: <09>Lane 05 nibble 1 raw readback: 003e
1198909.680: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
1199009.680: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
1199109.680: <09>Lane 06 nibble 1 raw readback: 0041
1199209.680: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
1199309.680: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
1199409.680: <09>Lane 07 nibble 1 raw readback: 0043
1199509.680: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0043
1199609.680: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
1199709.680: <09>Lane 08 nibble 1 raw readback: 003b
1199809.680: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
1199909.680: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
1200009.680: <09>original critical gross delay: 0
1200109.680: <09>new critical gross delay: 0
1200209.680: DIMM 0 RttNom: 3
1200309.680: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1200409.680: DIMM 0 RttNom: 3
1200509.680: DIMM 0 RttWr: 2
1200609.680: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1200709.680: DIMM 0 RttWr: 2
1200809.680: DIMM 0 RttNom: 3
1200909.680: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1201009.680: DIMM 0 RttNom: 3
1201109.680: DIMM 0 RttWr: 2
1201209.680: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1201309.680: DIMM 0 RttWr: 2
1201409.680: DIMM 1 RttNom: 3
1201509.681: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1201609.680: DIMM 0 RttNom: 3
1201709.681: DIMM 1 RttWr: 2
1201809.681: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1201909.681: DIMM 0 RttWr: 2
1202009.681: DIMM 1 RttNom: 3
1202109.681: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1202209.681: DIMM 0 RttNom: 3
1202309.681: DIMM 1 RttWr: 2
1202409.681: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1202509.681: DIMM 0 RttWr: 2
1202609.681: AgesaHwWlPhase1: training nibble 0
1202709.681: DIMM 1 RttNom: 3
1202809.681: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1202909.681: DIMM 1 RttWr: 2
1203009.681: DIMM 1 RttWr: 2
1203109.681: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1203209.681: DIMM 1 RttWr: 2
1203309.681: DIMM 1 RttNom: 3
1203409.681: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1203509.681: DIMM 1 RttNom: 3
1203609.681: DIMM 1 RttWr: 2
1203709.681: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1203809.681: DIMM 1 RttWr: 2
1203909.681: DIMM 0 RttNom: 3
1204009.681: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1204109.681: DIMM 1 RttNom: 3
1204209.681: DIMM 0 RttWr: 2
1204309.681: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1204409.681: DIMM 1 RttWr: 2
1204509.681: DIMM 0 RttNom: 3
1204609.681: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1204709.681: DIMM 1 RttNom: 3
1204809.681: DIMM 0 RttWr: 2
1204909.681: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1205009.681: DIMM 1 RttWr: 2
1205109.681: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1205209.681: <09>Lane 00 scaled delay: 0047
1205309.681: <09>Lane 00 new seed: 0047
1205409.681: <09>Lane 01 scaled delay: 0047
1205509.681: <09>Lane 01 new seed: 0047
1205609.681: <09>Lane 02 scaled delay: 0047
1205709.681: <09>Lane 02 new seed: 0047
1205809.681: <09>Lane 03 scaled delay: 0047
1205909.681: <09>Lane 03 new seed: 0047
1206009.681: <09>Lane 04 scaled delay: 0047
1206109.681: <09>Lane 04 new seed: 0047
1206209.681: <09>Lane 05 scaled delay: 0047
1206309.681: <09>Lane 05 new seed: 0047
1206409.681: <09>Lane 06 scaled delay: 0047
1206509.681: <09>Lane 06 new seed: 0047
1206609.681: <09>Lane 07 scaled delay: 0047
1206709.681: <09>Lane 07 new seed: 0047
1206809.681: <09>Lane 08 scaled delay: 0047
1206909.681: <09>Lane 08 new seed: 0047
1207009.681: <09>Lane 00 nibble 0 raw readback: 0046
1207109.681: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
1207209.681: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
1207309.681: <09>Lane 01 nibble 0 raw readback: 003f
1207409.681: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
1207509.681: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
1207609.681: <09>Lane 02 nibble 0 raw readback: 003e
1207709.681: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
1207809.681: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
1207909.681: <09>Lane 03 nibble 0 raw readback: 003b
1208009.681: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
1208109.681: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
1208209.681: <09>Lane 04 nibble 0 raw readback: 002f
1208309.681: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
1208409.682: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
1208509.682: <09>Lane 05 nibble 0 raw readback: 0035
1208609.682: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
1208709.682: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
1208809.682: <09>Lane 06 nibble 0 raw readback: 0038
1208909.682: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0038
1209009.682: <09>Lane 06 nibble 0 adjusted value (post nibble): 0038
1209109.682: <09>Lane 07 nibble 0 raw readback: 003a
1209209.682: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
1209309.682: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
1209409.682: <09>Lane 08 nibble 0 raw readback: 0034
1209509.682: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0034
1209609.682: <09>Lane 08 nibble 0 adjusted value (post nibble): 0034
1209709.682: AgesaHwWlPhase1: training nibble 1
1209809.682: DIMM 1 RttNom: 3
1209909.682: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1210009.682: DIMM 1 RttWr: 2
1210109.682: DIMM 1 RttWr: 2
1210209.682: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1210309.682: DIMM 1 RttWr: 2
1210409.682: DIMM 1 RttNom: 3
1210509.682: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1210609.682: DIMM 1 RttNom: 3
1210709.682: DIMM 1 RttWr: 2
1210809.682: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1210909.682: DIMM 1 RttWr: 2
1211009.682: DIMM 0 RttNom: 3
1211109.682: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1211209.682: DIMM 1 RttNom: 3
1211309.682: DIMM 0 RttWr: 2
1211409.682: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1211509.682: DIMM 1 RttWr: 2
1211609.682: DIMM 0 RttNom: 3
1211709.682: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1211809.682: DIMM 1 RttNom: 3
1211909.682: DIMM 0 RttWr: 2
1212009.682: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1212109.682: DIMM 1 RttWr: 2
1212209.682: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1212309.682: <09>Lane 00 new seed: 0047
1212409.682: <09>Lane 01 new seed: 0047
1212509.682: <09>Lane 02 new seed: 0047
1212609.682: <09>Lane 03 new seed: 0047
1212709.682: <09>Lane 04 new seed: 0047
1212809.682: <09>Lane 05 new seed: 0047
1212909.682: <09>Lane 06 new seed: 0047
1213009.682: <09>Lane 07 new seed: 0047
1213109.682: <09>Lane 08 new seed: 0047
1213209.682: <09>Lane 00 nibble 1 raw readback: 0045
1213309.682: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
1213409.682: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
1213509.682: <09>Lane 01 nibble 1 raw readback: 003f
1213609.682: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
1213709.682: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
1213809.682: <09>Lane 02 nibble 1 raw readback: 003f
1213909.682: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
1214009.682: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
1214109.682: <09>Lane 03 nibble 1 raw readback: 003c
1214209.682: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
1214309.682: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
1214409.682: <09>Lane 04 nibble 1 raw readback: 0031
1214509.682: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
1214609.682: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
1214709.682: <09>Lane 05 nibble 1 raw readback: 0035
1214809.682: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
1214909.682: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
1215009.682: <09>Lane 06 nibble 1 raw readback: 0038
1215109.682: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0038
1215209.682: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
1215309.682: <09>Lane 07 nibble 1 raw readback: 003a
1215409.682: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
1215509.682: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
1215609.682: <09>Lane 08 nibble 1 raw readback: 0033
1215709.682: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0033
1215809.682: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
1215909.682: <09>original critical gross delay: 0
1216009.683: <09>new critical gross delay: 0
1216109.683: DIMM 1 RttNom: 3
1216209.683: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1216309.683: DIMM 1 RttNom: 3
1216409.683: DIMM 1 RttWr: 2
1216509.683: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1216609.683: DIMM 1 RttWr: 2
1216709.683: DIMM 1 RttNom: 3
1216809.683: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1216909.683: DIMM 1 RttNom: 3
1217009.683: DIMM 1 RttWr: 2
1217109.683: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1217209.683: DIMM 1 RttWr: 2
1217309.683: DIMM 0 RttNom: 3
1217409.683: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1217509.683: DIMM 1 RttNom: 3
1217609.683: DIMM 0 RttWr: 2
1217709.683: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1217809.683: DIMM 1 RttWr: 2
1217909.683: DIMM 0 RttNom: 3
1218009.683: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1218109.683: DIMM 1 RttNom: 3
1218209.683: DIMM 0 RttWr: 2
1218309.683: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1218409.683: DIMM 1 RttWr: 2
1218509.683: SPD2ndTiming: Start
1218609.684: SPD2ndTiming: Done
1218709.684: mct_BeforeDramInit_Prod_D: Start
1218809.684: mct_ProgramODT_D: Start
1218909.684: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1219009.684: mct_ProgramODT_D: Done
1219109.684: mct_BeforeDramInit_Prod_D: Done
1219209.684: mct_DramInit_Sw_D: Start
1219309.684: DIMM 0 RttWr: 2
1219409.684: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1219509.684: mct_SendMrsCmd: Start
1219609.684: mct_SendMrsCmd: Done
1219709.684: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1219809.684: mct_SendMrsCmd: Start
1219909.684: mct_SendMrsCmd: Done
1220009.684: DIMM 0 RttNom: 3
1220109.684: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1220209.684: mct_SendMrsCmd: Start
1220309.684: mct_SendMrsCmd: Done
1220409.684: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
1220509.684: mct_SendMrsCmd: Start
1220609.684: mct_SendMrsCmd: Done
1220709.684: DIMM 0 RttWr: 2
1220809.684: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1220909.684: mct_SendMrsCmd: Start
1221009.684: mct_SendMrsCmd: Done
1221109.684: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1221209.684: mct_SendMrsCmd: Start
1221309.684: mct_SendMrsCmd: Done
1221409.684: DIMM 0 RttNom: 3
1221509.684: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1221609.684: mct_SendMrsCmd: Start
1221709.684: mct_SendMrsCmd: Done
1221809.684: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
1221909.684: mct_SendMrsCmd: Start
1222009.684: mct_SendMrsCmd: Done
1222109.684: DIMM 1 RttWr: 2
1222209.684: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1222309.684: mct_SendMrsCmd: Start
1222409.684: mct_SendMrsCmd: Done
1222509.684: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1222609.684: mct_SendMrsCmd: Start
1222709.684: mct_SendMrsCmd: Done
1222809.684: DIMM 1 RttNom: 3
1222909.684: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1223009.684: mct_SendMrsCmd: Start
1223109.684: mct_SendMrsCmd: Done
1223209.684: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
1223309.684: mct_SendMrsCmd: Start
1223409.684: mct_SendMrsCmd: Done
1223509.684: DIMM 1 RttWr: 2
1223609.684: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1223709.684: mct_SendMrsCmd: Start
1223809.684: mct_SendMrsCmd: Done
1223909.684: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1224009.684: mct_SendMrsCmd: Start
1224109.684: mct_SendMrsCmd: Done
1224209.684: DIMM 1 RttNom: 3
1224309.684: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1224409.684: mct_SendMrsCmd: Start
1224509.684: mct_SendMrsCmd: Done
1224609.684: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
1224709.684: mct_SendMrsCmd: Start
1224809.684: mct_SendMrsCmd: Done
1224909.684: mct_DramInit_Sw_D: Done
1225009.684: AgesaHwWlPhase1: training nibble 0
1225109.684: DIMM 0 RttNom: 3
1225209.684: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1225309.684: DIMM 0 RttWr: 2
1225409.685: DIMM 0 RttWr: 2
1225509.685: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1225609.685: DIMM 0 RttWr: 2
1225709.685: DIMM 0 RttNom: 3
1225809.685: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1225909.685: DIMM 0 RttNom: 3
1226009.685: DIMM 0 RttWr: 2
1226109.685: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1226209.685: DIMM 0 RttWr: 2
1226309.685: DIMM 1 RttNom: 3
1226409.685: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1226509.685: DIMM 0 RttNom: 3
1226609.685: DIMM 1 RttWr: 2
1226709.685: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1226809.685: DIMM 0 RttWr: 2
1226909.685: DIMM 1 RttNom: 3
1227009.685: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1227109.685: DIMM 0 RttNom: 3
1227209.685: DIMM 1 RttWr: 2
1227309.685: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1227409.685: DIMM 0 RttWr: 2
1227509.685: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1227609.685: <09>Lane 00 scaled delay: 0047
1227709.685: <09>Lane 00 new seed: 0047
1227809.685: <09>Lane 01 scaled delay: 0047
1227909.685: <09>Lane 01 new seed: 0047
1228009.685: <09>Lane 02 scaled delay: 0047
1228109.685: <09>Lane 02 new seed: 0047
1228209.685: <09>Lane 03 scaled delay: 0047
1228309.685: <09>Lane 03 new seed: 0047
1228409.685: <09>Lane 04 scaled delay: 0047
1228509.685: <09>Lane 04 new seed: 0047
1228609.685: <09>Lane 05 scaled delay: 0047
1228709.685: <09>Lane 05 new seed: 0047
1228809.685: <09>Lane 06 scaled delay: 0047
1228909.685: <09>Lane 06 new seed: 0047
1229009.685: <09>Lane 07 scaled delay: 0047
1229109.685: <09>Lane 07 new seed: 0047
1229209.685: <09>Lane 08 scaled delay: 0047
1229309.685: <09>Lane 08 new seed: 0047
1229409.685: <09>Lane 00 nibble 0 raw readback: 004e
1229509.685: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004e
1229609.685: <09>Lane 00 nibble 0 adjusted value (post nibble): 004e
1229709.685: <09>Lane 01 nibble 0 raw readback: 004a
1229809.685: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
1229909.685: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
1230009.685: <09>Lane 02 nibble 0 raw readback: 0046
1230109.685: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
1230209.685: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
1230309.685: <09>Lane 03 nibble 0 raw readback: 0044
1230409.685: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
1230509.685: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
1230609.685: <09>Lane 04 nibble 0 raw readback: 0039
1230709.686: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
1230809.686: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
1230909.686: <09>Lane 05 nibble 0 raw readback: 003d
1231009.686: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
1231109.686: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
1231209.686: <09>Lane 06 nibble 0 raw readback: 0040
1231309.686: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
1231409.686: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
1231509.686: <09>Lane 07 nibble 0 raw readback: 0042
1231609.686: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
1231709.686: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
1231809.686: <09>Lane 08 nibble 0 raw readback: 003b
1231909.686: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
1232009.686: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
1232109.686: AgesaHwWlPhase1: training nibble 1
1232209.686: DIMM 0 RttNom: 3
1232309.686: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1232409.686: DIMM 0 RttWr: 2
1232509.686: DIMM 0 RttWr: 2
1232609.686: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1232709.686: DIMM 0 RttWr: 2
1232809.686: DIMM 0 RttNom: 3
1232909.686: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1233009.686: DIMM 0 RttNom: 3
1233109.686: DIMM 0 RttWr: 2
1233209.686: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1233309.686: DIMM 0 RttWr: 2
1233409.686: DIMM 1 RttNom: 3
1233509.686: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1233609.686: DIMM 0 RttNom: 3
1233709.686: DIMM 1 RttWr: 2
1233809.686: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1233909.686: DIMM 0 RttWr: 2
1234009.686: DIMM 1 RttNom: 3
1234109.686: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1234209.686: DIMM 0 RttNom: 3
1234309.686: DIMM 1 RttWr: 2
1234409.686: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1234509.686: DIMM 0 RttWr: 2
1234609.686: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1234709.686: <09>Lane 00 new seed: 0047
1234809.686: <09>Lane 01 new seed: 0047
1234909.686: <09>Lane 02 new seed: 0047
1235009.686: <09>Lane 03 new seed: 0047
1235109.686: <09>Lane 04 new seed: 0047
1235209.686: <09>Lane 05 new seed: 0047
1235309.686: <09>Lane 06 new seed: 0047
1235409.686: <09>Lane 07 new seed: 0047
1235509.686: <09>Lane 08 new seed: 0047
1235609.686: <09>Lane 00 nibble 1 raw readback: 004e
1235709.686: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004e
1235809.686: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
1235909.686: <09>Lane 01 nibble 1 raw readback: 004a
1236009.686: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
1236109.686: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
1236209.686: <09>Lane 02 nibble 1 raw readback: 0047
1236309.686: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
1236409.686: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
1236509.686: <09>Lane 03 nibble 1 raw readback: 0044
1236609.686: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
1236709.686: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
1236809.686: <09>Lane 04 nibble 1 raw readback: 0039
1236909.686: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
1237009.686: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
1237109.686: <09>Lane 05 nibble 1 raw readback: 003e
1237209.686: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
1237309.686: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
1237409.686: <09>Lane 06 nibble 1 raw readback: 0040
1237509.686: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
1237609.686: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
1237709.686: <09>Lane 07 nibble 1 raw readback: 0041
1237809.687: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
1237909.687: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
1238009.687: <09>Lane 08 nibble 1 raw readback: 003c
1238109.687: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
1238209.687: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
1238309.687: <09>original critical gross delay: 0
1238409.687: <09>new critical gross delay: 0
1238509.687: DIMM 0 RttNom: 3
1238609.687: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1238709.687: DIMM 0 RttNom: 3
1238809.687: DIMM 0 RttWr: 2
1238909.687: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1239009.687: DIMM 0 RttWr: 2
1239109.687: DIMM 0 RttNom: 3
1239209.687: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1239309.687: DIMM 0 RttNom: 3
1239409.687: DIMM 0 RttWr: 2
1239509.687: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1239609.687: DIMM 0 RttWr: 2
1239709.687: DIMM 1 RttNom: 3
1239809.687: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1239909.687: DIMM 0 RttNom: 3
1240009.687: DIMM 1 RttWr: 2
1240109.687: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1240209.687: DIMM 0 RttWr: 2
1240309.687: DIMM 1 RttNom: 3
1240409.687: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1240509.687: DIMM 0 RttNom: 3
1240609.687: DIMM 1 RttWr: 2
1240709.687: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1240809.687: DIMM 0 RttWr: 2
1240909.687: AgesaHwWlPhase1: training nibble 0
1241009.687: DIMM 1 RttNom: 3
1241109.687: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1241209.687: DIMM 1 RttWr: 2
1241309.687: DIMM 1 RttWr: 2
1241409.687: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1241509.687: DIMM 1 RttWr: 2
1241609.687: DIMM 1 RttNom: 3
1241709.687: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1241809.687: DIMM 1 RttNom: 3
1241909.687: DIMM 1 RttWr: 2
1242009.687: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1242109.687: DIMM 1 RttWr: 2
1242209.687: DIMM 0 RttNom: 3
1242309.687: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1242409.687: DIMM 1 RttNom: 3
1242509.687: DIMM 0 RttWr: 2
1242609.687: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1242709.687: DIMM 1 RttWr: 2
1242809.687: DIMM 0 RttNom: 3
1242909.687: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1243009.687: DIMM 1 RttNom: 3
1243109.687: DIMM 0 RttWr: 2
1243209.687: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1243309.687: DIMM 1 RttWr: 2
1243409.687: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1243509.688: <09>Lane 00 scaled delay: 0047
1243609.688: <09>Lane 00 new seed: 0047
1243709.688: <09>Lane 01 scaled delay: 0047
1243809.688: <09>Lane 01 new seed: 0047
1243909.688: <09>Lane 02 scaled delay: 0047
1244009.688: <09>Lane 02 new seed: 0047
1244109.688: <09>Lane 03 scaled delay: 0047
1244209.688: <09>Lane 03 new seed: 0047
1244309.688: <09>Lane 04 scaled delay: 0047
1244409.688: <09>Lane 04 new seed: 0047
1244509.688: <09>Lane 05 scaled delay: 0047
1244609.688: <09>Lane 05 new seed: 0047
1244709.688: <09>Lane 06 scaled delay: 0047
1244809.688: <09>Lane 06 new seed: 0047
1244909.688: <09>Lane 07 scaled delay: 0047
1245009.688: <09>Lane 07 new seed: 0047
1245109.688: <09>Lane 08 scaled delay: 0047
1245209.688: <09>Lane 08 new seed: 0047
1245309.688: <09>Lane 00 nibble 0 raw readback: 0044
1245409.688: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
1245509.688: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
1245609.688: <09>Lane 01 nibble 0 raw readback: 003f
1245709.688: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
1245809.688: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
1245909.688: <09>Lane 02 nibble 0 raw readback: 003c
1246009.688: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
1246109.688: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
1246209.688: <09>Lane 03 nibble 0 raw readback: 003a
1246309.688: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
1246409.688: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
1246509.688: <09>Lane 04 nibble 0 raw readback: 002f
1246609.688: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
1246709.688: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
1246809.688: <09>Lane 05 nibble 0 raw readback: 0033
1246909.688: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0033
1247009.688: <09>Lane 05 nibble 0 adjusted value (post nibble): 0033
1247109.688: <09>Lane 06 nibble 0 raw readback: 0035
1247209.688: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0035
1247309.688: <09>Lane 06 nibble 0 adjusted value (post nibble): 0035
1247409.688: <09>Lane 07 nibble 0 raw readback: 0039
1247509.688: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
1247609.688: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
1247709.688: <09>Lane 08 nibble 0 raw readback: 0032
1247809.688: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
1247909.688: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
1248009.688: AgesaHwWlPhase1: training nibble 1
1248109.688: DIMM 1 RttNom: 3
1248209.688: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1248309.688: DIMM 1 RttWr: 2
1248409.688: DIMM 1 RttWr: 2
1248509.688: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1248609.688: DIMM 1 RttWr: 2
1248709.688: DIMM 1 RttNom: 3
1248809.688: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1248909.688: DIMM 1 RttNom: 3
1249009.688: DIMM 1 RttWr: 2
1249109.688: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1249209.688: DIMM 1 RttWr: 2
1249309.688: DIMM 0 RttNom: 3
1249409.688: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1249509.688: DIMM 1 RttNom: 3
1249609.688: DIMM 0 RttWr: 2
1249709.688: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1249809.688: DIMM 1 RttWr: 2
1249909.688: DIMM 0 RttNom: 3
1250009.688: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1250109.688: DIMM 1 RttNom: 3
1250209.688: DIMM 0 RttWr: 2
1250309.688: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1250409.688: DIMM 1 RttWr: 2
1250509.689: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1250609.689: <09>Lane 00 new seed: 0047
1250709.689: <09>Lane 01 new seed: 0047
1250809.689: <09>Lane 02 new seed: 0047
1250909.689: <09>Lane 03 new seed: 0047
1251009.689: <09>Lane 04 new seed: 0047
1251109.689: <09>Lane 05 new seed: 0047
1251209.689: <09>Lane 06 new seed: 0047
1251309.689: <09>Lane 07 new seed: 0047
1251409.689: <09>Lane 08 new seed: 0047
1251509.689: <09>Lane 00 nibble 1 raw readback: 0043
1251609.689: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
1251709.689: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
1251809.689: <09>Lane 01 nibble 1 raw readback: 003f
1251909.689: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
1252009.689: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
1252109.689: <09>Lane 02 nibble 1 raw readback: 003c
1252209.689: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
1252309.689: <09>Lane 02 nibble 1 adjusted value (post nibble): 0041
1252409.689: <09>Lane 03 nibble 1 raw readback: 003b
1252509.689: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
1252609.689: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
1252709.689: <09>Lane 04 nibble 1 raw readback: 0030
1252809.689: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
1252909.689: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
1253009.689: <09>Lane 05 nibble 1 raw readback: 0033
1253109.689: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0033
1253209.689: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
1253309.689: <09>Lane 06 nibble 1 raw readback: 0036
1253409.689: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0036
1253509.689: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
1253609.689: <09>Lane 07 nibble 1 raw readback: 0039
1253709.689: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
1253809.689: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
1253909.689: <09>Lane 08 nibble 1 raw readback: 0032
1254009.689: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
1254109.689: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
1254209.689: <09>original critical gross delay: 0
1254309.689: <09>new critical gross delay: 0
1254409.689: DIMM 1 RttNom: 3
1254509.689: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1254609.689: DIMM 1 RttNom: 3
1254709.689: DIMM 1 RttWr: 2
1254809.689: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1254909.689: DIMM 1 RttWr: 2
1255009.689: DIMM 1 RttNom: 3
1255109.689: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1255209.689: DIMM 1 RttNom: 3
1255309.689: DIMM 1 RttWr: 2
1255409.689: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1255509.689: DIMM 1 RttWr: 2
1255609.689: DIMM 0 RttNom: 3
1255709.689: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1255809.689: DIMM 1 RttNom: 3
1255909.689: DIMM 0 RttWr: 2
1256009.689: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1256109.689: DIMM 1 RttWr: 2
1256209.689: DIMM 0 RttNom: 3
1256309.689: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1256409.689: DIMM 1 RttNom: 3
1256509.689: DIMM 0 RttWr: 2
1256609.689: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1256709.689: DIMM 1 RttWr: 2
1256809.690: SetTargetFreq: Start
1256909.690: SetTargetFreq: Node 2: New frequency code: 000a
1257009.690: ChangeMemClk: Start
1257109.690: set_2t_configuration: Start
1257209.690: set_2t_configuration: Done
1257309.690: mct_BeforePlatformSpec: Start
1257409.690: mct_BeforePlatformSpec: Done
1257509.690: mct_PlatformSpec: Start
1257609.690: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
1257709.690: mct_PlatformSpec: Done
1257809.690: set_2t_configuration: Start
1257909.690: set_2t_configuration: Done
1258009.690: mct_BeforePlatformSpec: Start
1258109.690: mct_BeforePlatformSpec: Done
1258209.690: mct_PlatformSpec: Start
1258309.690: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
1258409.690: mct_PlatformSpec: Done
1258509.690: ChangeMemClk: Done
1258609.690: phyAssistedMemFnceTraining: Start
1258709.690: phyAssistedMemFnceTraining: training node 2 DCT 0
1258809.690: phyAssistedMemFnceTraining: done training node 2 DCT 0
1258909.690: phyAssistedMemFnceTraining: training node 2 DCT 1
1259009.690: phyAssistedMemFnceTraining: done training node 2 DCT 1
1259109.690: phyAssistedMemFnceTraining: Done
1259209.690: InitPhyCompensation: DCT 0: Start
1259309.690: Waiting for predriver calibration to be applied...done!
1259409.691: InitPhyCompensation: DCT 0: Done
1259509.691: phyAssistedMemFnceTraining: Start
1259609.691: phyAssistedMemFnceTraining: training node 2 DCT 0
1259709.691: phyAssistedMemFnceTraining: done training node 2 DCT 0
1259809.691: phyAssistedMemFnceTraining: training node 2 DCT 1
1259909.691: phyAssistedMemFnceTraining: done training node 2 DCT 1
1260009.691: phyAssistedMemFnceTraining: Done
1260109.691: InitPhyCompensation: DCT 1: Start
1260209.691: Waiting for predriver calibration to be applied...done!
1260309.691: InitPhyCompensation: DCT 1: Done
1260409.691: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
1260509.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1260609.691: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1260709.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1260809.691: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1260909.691: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
1261009.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1261109.691: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1261209.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1261309.691: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1261409.691: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
1261509.691: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1261609.691: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1261709.691: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1261809.691: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1261909.691: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
1262009.691: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1262109.692: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1262209.692: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1262309.692: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1262409.692: SetTargetFreq: Done
1262509.692: SPD2ndTiming: Start
1262609.692: SPD2ndTiming: Done
1262709.692: mct_BeforeDramInit_Prod_D: Start
1262809.692: mct_ProgramODT_D: Start
1262909.692: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1263009.692: mct_ProgramODT_D: Done
1263109.692: mct_BeforeDramInit_Prod_D: Done
1263209.692: mct_DramInit_Sw_D: Start
1263309.692: DIMM 0 RttWr: 1
1263409.692: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1263509.692: mct_SendMrsCmd: Start
1263609.692: mct_SendMrsCmd: Done
1263709.692: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1263809.692: mct_SendMrsCmd: Start
1263909.692: mct_SendMrsCmd: Done
1264009.692: DIMM 0 RttNom: 3
1264109.692: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1264209.692: mct_SendMrsCmd: Start
1264309.692: mct_SendMrsCmd: Done
1264409.692: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
1264509.692: mct_SendMrsCmd: Start
1264609.692: mct_SendMrsCmd: Done
1264709.692: DIMM 0 RttWr: 1
1264809.692: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1264909.692: mct_SendMrsCmd: Start
1265009.692: mct_SendMrsCmd: Done
1265109.692: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1265209.692: mct_SendMrsCmd: Start
1265309.692: mct_SendMrsCmd: Done
1265409.692: DIMM 0 RttNom: 3
1265509.692: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1265609.692: mct_SendMrsCmd: Start
1265709.692: mct_SendMrsCmd: Done
1265809.692: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
1265909.692: mct_SendMrsCmd: Start
1266009.692: mct_SendMrsCmd: Done
1266109.692: DIMM 1 RttWr: 1
1266209.692: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1266309.692: mct_SendMrsCmd: Start
1266409.692: mct_SendMrsCmd: Done
1266509.693: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1266609.693: mct_SendMrsCmd: Start
1266709.693: mct_SendMrsCmd: Done
1266809.693: DIMM 1 RttNom: 3
1266909.693: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1267009.693: mct_SendMrsCmd: Start
1267109.693: mct_SendMrsCmd: Done
1267209.693: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
1267309.693: mct_SendMrsCmd: Start
1267409.693: mct_SendMrsCmd: Done
1267509.693: DIMM 1 RttWr: 1
1267609.693: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1267709.693: mct_SendMrsCmd: Start
1267809.693: mct_SendMrsCmd: Done
1267909.693: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1268009.693: mct_SendMrsCmd: Start
1268109.693: mct_SendMrsCmd: Done
1268209.693: DIMM 1 RttNom: 3
1268309.693: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1268409.693: mct_SendMrsCmd: Start
1268509.693: mct_SendMrsCmd: Done
1268609.693: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
1268709.693: mct_SendMrsCmd: Start
1268809.693: mct_SendMrsCmd: Done
1268909.693: mct_DramInit_Sw_D: Done
1269009.693: AgesaHwWlPhase1: training nibble 0
1269109.693: DIMM 0 RttNom: 3
1269209.693: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1269309.693: DIMM 0 RttWr: 1
1269409.693: DIMM 0 RttWr: 1
1269509.693: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1269609.693: DIMM 0 RttWr: 1
1269709.693: DIMM 0 RttNom: 3
1269809.693: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1269909.693: DIMM 0 RttNom: 3
1270009.693: DIMM 0 RttWr: 1
1270109.693: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1270209.693: DIMM 0 RttWr: 1
1270309.693: DIMM 1 RttNom: 3
1270409.693: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1270509.693: DIMM 0 RttNom: 3
1270609.693: DIMM 1 RttWr: 1
1270709.693: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1270809.693: DIMM 0 RttWr: 1
1270909.693: DIMM 1 RttNom: 3
1271009.693: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1271109.693: DIMM 0 RttNom: 3
1271209.693: DIMM 1 RttWr: 1
1271309.693: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1271409.693: DIMM 0 RttWr: 1
1271509.693: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1271609.694: <09>Lane 00 scaled delay: 0059
1271709.694: <09>Lane 00 new seed: 0059
1271809.694: <09>Lane 01 scaled delay: 0055
1271909.694: <09>Lane 01 new seed: 0055
1272009.694: <09>Lane 02 scaled delay: 0053
1272109.694: <09>Lane 02 new seed: 0053
1272209.694: <09>Lane 03 scaled delay: 0052
1272309.694: <09>Lane 03 new seed: 0052
1272409.694: <09>Lane 04 scaled delay: 004a
1272509.694: <09>Lane 04 new seed: 004a
1272609.694: <09>Lane 05 scaled delay: 004d
1272709.694: <09>Lane 05 new seed: 004d
1272809.694: <09>Lane 06 scaled delay: 004f
1272909.694: <09>Lane 06 new seed: 004f
1273009.694: <09>Lane 07 scaled delay: 0051
1273109.694: <09>Lane 07 new seed: 0051
1273209.694: <09>Lane 08 scaled delay: 004b
1273309.694: <09>Lane 08 new seed: 004b
1273409.694: <09>Lane 00 nibble 0 raw readback: 0060
1273509.694: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
1273609.694: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
1273709.694: <09>Lane 01 nibble 0 raw readback: 0057
1273809.694: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0057
1273909.694: <09>Lane 01 nibble 0 adjusted value (post nibble): 0057
1274009.694: <09>Lane 02 nibble 0 raw readback: 0055
1274109.694: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
1274209.694: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
1274309.694: <09>Lane 03 nibble 0 raw readback: 0052
1274409.694: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0052
1274509.694: <09>Lane 03 nibble 0 adjusted value (post nibble): 0052
1274609.694: <09>Lane 04 nibble 0 raw readback: 0044
1274709.694: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
1274809.694: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
1274909.694: <09>Lane 05 nibble 0 raw readback: 004a
1275009.694: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004a
1275109.694: <09>Lane 05 nibble 0 adjusted value (post nibble): 004a
1275209.694: <09>Lane 06 nibble 0 raw readback: 004e
1275309.694: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
1275409.694: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
1275509.694: <09>Lane 07 nibble 0 raw readback: 0051
1275609.694: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0051
1275709.694: <09>Lane 07 nibble 0 adjusted value (post nibble): 0051
1275809.694: <09>Lane 08 nibble 0 raw readback: 0047
1275909.694: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
1276009.694: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
1276109.694: AgesaHwWlPhase1: training nibble 1
1276209.694: DIMM 0 RttNom: 3
1276309.694: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1276409.694: DIMM 0 RttWr: 1
1276509.694: DIMM 0 RttWr: 1
1276609.694: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1276709.694: DIMM 0 RttWr: 1
1276809.694: DIMM 0 RttNom: 3
1276909.694: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1277009.694: DIMM 0 RttNom: 3
1277109.694: DIMM 0 RttWr: 1
1277209.694: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1277309.694: DIMM 0 RttWr: 1
1277409.694: DIMM 1 RttNom: 3
1277509.695: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1277609.695: DIMM 0 RttNom: 3
1277709.695: DIMM 1 RttWr: 1
1277809.695: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1277909.695: DIMM 0 RttWr: 1
1278009.695: DIMM 1 RttNom: 3
1278109.695: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1278209.695: DIMM 0 RttNom: 3
1278309.695: DIMM 1 RttWr: 1
1278409.695: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1278509.695: DIMM 0 RttWr: 1
1278609.695: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1278709.695: <09>Lane 00 new seed: 0059
1278809.695: <09>Lane 01 new seed: 0055
1278909.695: <09>Lane 02 new seed: 0053
1279009.695: <09>Lane 03 new seed: 0052
1279109.695: <09>Lane 04 new seed: 004a
1279209.695: <09>Lane 05 new seed: 004d
1279309.695: <09>Lane 06 new seed: 004f
1279409.695: <09>Lane 07 new seed: 0051
1279509.695: <09>Lane 08 new seed: 004b
1279609.695: <09>Lane 00 nibble 1 raw readback: 005f
1279709.695: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
1279809.695: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
1279909.695: <09>Lane 01 nibble 1 raw readback: 0059
1280009.695: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
1280109.695: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
1280209.695: <09>Lane 02 nibble 1 raw readback: 0056
1280309.695: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
1280409.695: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
1280509.695: <09>Lane 03 nibble 1 raw readback: 0052
1280609.695: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
1280709.695: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
1280809.695: <09>Lane 04 nibble 1 raw readback: 0043
1280909.695: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
1281009.695: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
1281109.695: <09>Lane 05 nibble 1 raw readback: 0048
1281209.695: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
1281309.695: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
1281409.695: <09>Lane 06 nibble 1 raw readback: 004e
1281509.695: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
1281609.695: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
1281709.695: <09>Lane 07 nibble 1 raw readback: 0050
1281809.695: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
1281909.695: <09>Lane 07 nibble 1 adjusted value (post nibble): 0050
1282009.695: <09>Lane 08 nibble 1 raw readback: 0045
1282109.695: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
1282209.695: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
1282309.695: <09>original critical gross delay: 0
1282409.695: <09>new critical gross delay: 0
1282509.695: DIMM 0 RttNom: 3
1282609.695: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1282709.695: DIMM 0 RttNom: 3
1282809.695: DIMM 0 RttWr: 1
1282909.695: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1283009.695: DIMM 0 RttWr: 1
1283109.695: DIMM 0 RttNom: 3
1283209.695: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1283309.695: DIMM 0 RttNom: 3
1283409.695: DIMM 0 RttWr: 1
1283509.695: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1283609.695: DIMM 0 RttWr: 1
1283709.696: DIMM 1 RttNom: 3
1283809.696: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1283909.696: DIMM 0 RttNom: 3
1284009.696: DIMM 1 RttWr: 1
1284109.696: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1284209.696: DIMM 0 RttWr: 1
1284309.696: DIMM 1 RttNom: 3
1284409.696: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1284509.696: DIMM 0 RttNom: 3
1284609.696: DIMM 1 RttWr: 1
1284709.696: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1284809.696: DIMM 0 RttWr: 1
1284909.696: AgesaHwWlPhase1: training nibble 0
1285009.696: DIMM 1 RttNom: 3
1285109.696: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1285209.696: DIMM 1 RttWr: 1
1285309.696: DIMM 1 RttWr: 1
1285409.696: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1285509.696: DIMM 1 RttWr: 1
1285609.696: DIMM 1 RttNom: 3
1285709.696: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1285809.696: DIMM 1 RttNom: 3
1285909.696: DIMM 1 RttWr: 1
1286009.696: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1286109.696: DIMM 1 RttWr: 1
1286209.696: DIMM 0 RttNom: 3
1286309.696: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1286409.696: DIMM 1 RttNom: 3
1286509.696: DIMM 0 RttWr: 1
1286609.696: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1286709.696: DIMM 1 RttWr: 1
1286809.696: DIMM 0 RttNom: 3
1286909.696: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1287009.696: DIMM 1 RttNom: 3
1287109.696: DIMM 0 RttWr: 1
1287209.696: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1287309.696: DIMM 1 RttWr: 1
1287409.696: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1287509.696: <09>Lane 00 scaled delay: 0052
1287609.696: <09>Lane 00 new seed: 0052
1287709.696: <09>Lane 01 scaled delay: 004e
1287809.696: <09>Lane 01 new seed: 004e
1287909.696: <09>Lane 02 scaled delay: 004e
1288009.696: <09>Lane 02 new seed: 004e
1288109.696: <09>Lane 03 scaled delay: 004b
1288209.696: <09>Lane 03 new seed: 004b
1288309.696: <09>Lane 04 scaled delay: 0045
1288409.696: <09>Lane 04 new seed: 0045
1288509.696: <09>Lane 05 scaled delay: 0047
1288609.696: <09>Lane 05 new seed: 0047
1288709.696: <09>Lane 06 scaled delay: 0049
1288809.696: <09>Lane 06 new seed: 0049
1288909.696: <09>Lane 07 scaled delay: 004a
1289009.696: <09>Lane 07 new seed: 004a
1289109.696: <09>Lane 08 scaled delay: 0046
1289209.696: <09>Lane 08 new seed: 0046
1289309.696: <09>Lane 00 nibble 0 raw readback: 0053
1289409.696: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0053
1289509.696: <09>Lane 00 nibble 0 adjusted value (post nibble): 0053
1289609.696: <09>Lane 01 nibble 0 raw readback: 004a
1289709.696: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
1289809.696: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
1289909.696: <09>Lane 02 nibble 0 raw readback: 0048
1290009.696: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
1290109.697: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
1290209.697: <09>Lane 03 nibble 0 raw readback: 0043
1290309.697: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0043
1290409.697: <09>Lane 03 nibble 0 adjusted value (post nibble): 0043
1290509.697: <09>Lane 04 nibble 0 raw readback: 0036
1290609.697: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0036
1290709.697: <09>Lane 04 nibble 0 adjusted value (post nibble): 0036
1290809.697: <09>Lane 05 nibble 0 raw readback: 003c
1290909.697: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
1291009.697: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
1291109.697: <09>Lane 06 nibble 0 raw readback: 0040
1291209.697: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
1291309.697: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
1291409.697: <09>Lane 07 nibble 0 raw readback: 0044
1291509.697: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
1291609.697: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
1291709.697: <09>Lane 08 nibble 0 raw readback: 0039
1291809.697: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
1291909.697: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
1292009.697: AgesaHwWlPhase1: training nibble 1
1292109.697: DIMM 1 RttNom: 3
1292209.697: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1292309.697: DIMM 1 RttWr: 1
1292409.697: DIMM 1 RttWr: 1
1292509.697: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1292609.697: DIMM 1 RttWr: 1
1292709.697: DIMM 1 RttNom: 3
1292809.697: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1292909.697: DIMM 1 RttNom: 3
1293009.697: DIMM 1 RttWr: 1
1293109.697: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1293209.697: DIMM 1 RttWr: 1
1293309.697: DIMM 0 RttNom: 3
1293409.697: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1293509.697: DIMM 1 RttNom: 3
1293609.697: DIMM 0 RttWr: 1
1293709.697: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1293809.697: DIMM 1 RttWr: 1
1293909.697: DIMM 0 RttNom: 3
1294009.697: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1294109.697: DIMM 1 RttNom: 3
1294209.697: DIMM 0 RttWr: 1
1294309.697: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1294409.697: DIMM 1 RttWr: 1
1294509.697: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1294609.697: <09>Lane 00 new seed: 0052
1294709.697: <09>Lane 01 new seed: 004e
1294809.697: <09>Lane 02 new seed: 004e
1294909.697: <09>Lane 03 new seed: 004b
1295009.697: <09>Lane 04 new seed: 0045
1295109.697: <09>Lane 05 new seed: 0047
1295209.697: <09>Lane 06 new seed: 0049
1295309.697: <09>Lane 07 new seed: 004a
1295409.697: <09>Lane 08 new seed: 0046
1295509.697: <09>Lane 00 nibble 1 raw readback: 0051
1295609.697: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
1295709.697: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
1295809.697: <09>Lane 01 nibble 1 raw readback: 004a
1295909.697: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
1296009.697: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
1296109.697: <09>Lane 02 nibble 1 raw readback: 004a
1296209.697: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
1296309.697: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
1296409.697: <09>Lane 03 nibble 1 raw readback: 0045
1296509.697: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
1296609.697: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1296709.697: <09>Lane 04 nibble 1 raw readback: 0037
1296809.697: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
1296909.697: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
1297009.697: <09>Lane 05 nibble 1 raw readback: 003c
1297109.697: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
1297209.697: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
1297309.697: <09>Lane 06 nibble 1 raw readback: 0040
1297409.697: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
1297509.697: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
1297609.697: <09>Lane 07 nibble 1 raw readback: 0045
1297709.698: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
1297809.698: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
1297909.698: <09>Lane 08 nibble 1 raw readback: 0039
1298009.698: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
1298109.698: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
1298209.698: <09>original critical gross delay: 0
1298309.698: <09>new critical gross delay: 0
1298409.698: DIMM 1 RttNom: 3
1298509.698: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1298609.698: DIMM 1 RttNom: 3
1298709.698: DIMM 1 RttWr: 1
1298809.698: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1298909.698: DIMM 1 RttWr: 1
1299009.698: DIMM 1 RttNom: 3
1299109.698: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1299209.698: DIMM 1 RttNom: 3
1299309.698: DIMM 1 RttWr: 1
1299409.698: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1299509.698: DIMM 1 RttWr: 1
1299609.698: DIMM 0 RttNom: 3
1299709.698: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1299809.698: DIMM 1 RttNom: 3
1299909.698: DIMM 0 RttWr: 1
1300009.698: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1300109.698: DIMM 1 RttWr: 1
1300209.698: DIMM 0 RttNom: 3
1300309.698: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1300409.698: DIMM 1 RttNom: 3
1300509.698: DIMM 0 RttWr: 1
1300609.698: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1300709.698: DIMM 1 RttWr: 1
1300809.698: SPD2ndTiming: Start
1300909.699: SPD2ndTiming: Done
1301009.699: mct_BeforeDramInit_Prod_D: Start
1301109.699: mct_ProgramODT_D: Start
1301209.699: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1301309.699: mct_ProgramODT_D: Done
1301409.699: mct_BeforeDramInit_Prod_D: Done
1301509.699: mct_DramInit_Sw_D: Start
1301609.699: DIMM 0 RttWr: 1
1301709.699: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1301809.699: mct_SendMrsCmd: Start
1301909.699: mct_SendMrsCmd: Done
1302009.699: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1302109.699: mct_SendMrsCmd: Start
1302209.699: mct_SendMrsCmd: Done
1302309.699: DIMM 0 RttNom: 3
1302409.699: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1302509.699: mct_SendMrsCmd: Start
1302609.699: mct_SendMrsCmd: Done
1302709.699: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
1302809.699: mct_SendMrsCmd: Start
1302909.699: mct_SendMrsCmd: Done
1303009.699: DIMM 0 RttWr: 1
1303109.699: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1303209.699: mct_SendMrsCmd: Start
1303309.699: mct_SendMrsCmd: Done
1303409.699: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1303509.699: mct_SendMrsCmd: Start
1303609.699: mct_SendMrsCmd: Done
1303709.699: DIMM 0 RttNom: 3
1303809.699: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1303909.699: mct_SendMrsCmd: Start
1304009.699: mct_SendMrsCmd: Done
1304109.699: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
1304209.699: mct_SendMrsCmd: Start
1304309.699: mct_SendMrsCmd: Done
1304409.699: DIMM 1 RttWr: 1
1304509.699: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1304609.699: mct_SendMrsCmd: Start
1304709.699: mct_SendMrsCmd: Done
1304809.699: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1304909.699: mct_SendMrsCmd: Start
1305009.699: mct_SendMrsCmd: Done
1305109.699: DIMM 1 RttNom: 3
1305209.699: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1305309.699: mct_SendMrsCmd: Start
1305409.699: mct_SendMrsCmd: Done
1305509.699: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
1305609.699: mct_SendMrsCmd: Start
1305709.699: mct_SendMrsCmd: Done
1305809.699: DIMM 1 RttWr: 1
1305909.699: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1306009.699: mct_SendMrsCmd: Start
1306109.699: mct_SendMrsCmd: Done
1306209.699: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1306309.699: mct_SendMrsCmd: Start
1306409.699: mct_SendMrsCmd: Done
1306509.699: DIMM 1 RttNom: 3
1306609.699: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1306709.699: mct_SendMrsCmd: Start
1306809.699: mct_SendMrsCmd: Done
1306909.699: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
1307009.699: mct_SendMrsCmd: Start
1307109.699: mct_SendMrsCmd: Done
1307209.699: mct_DramInit_Sw_D: Done
1307309.699: AgesaHwWlPhase1: training nibble 0
1307409.700: DIMM 0 RttNom: 3
1307509.699: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1307609.699: DIMM 0 RttWr: 1
1307709.700: DIMM 0 RttWr: 1
1307809.700: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1307909.700: DIMM 0 RttWr: 1
1308009.700: DIMM 0 RttNom: 3
1308109.700: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1308209.700: DIMM 0 RttNom: 3
1308309.700: DIMM 0 RttWr: 1
1308409.700: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1308509.700: DIMM 0 RttWr: 1
1308609.700: DIMM 1 RttNom: 3
1308709.700: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1308809.700: DIMM 0 RttNom: 3
1308909.700: DIMM 1 RttWr: 1
1309009.700: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1309109.700: DIMM 0 RttWr: 1
1309209.700: DIMM 1 RttNom: 3
1309309.700: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1309409.700: DIMM 0 RttNom: 3
1309509.700: DIMM 1 RttWr: 1
1309609.700: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1309709.700: DIMM 0 RttWr: 1
1309809.700: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1309909.700: <09>Lane 00 scaled delay: 0057
1310009.700: <09>Lane 00 new seed: 0057
1310109.700: <09>Lane 01 scaled delay: 0055
1310209.700: <09>Lane 01 new seed: 0055
1310309.700: <09>Lane 02 scaled delay: 0053
1310409.700: <09>Lane 02 new seed: 0053
1310509.700: <09>Lane 03 scaled delay: 0051
1310609.700: <09>Lane 03 new seed: 0051
1310709.700: <09>Lane 04 scaled delay: 004a
1310809.700: <09>Lane 04 new seed: 004a
1310909.700: <09>Lane 05 scaled delay: 004d
1311009.700: <09>Lane 05 new seed: 004d
1311109.700: <09>Lane 06 scaled delay: 004e
1311209.700: <09>Lane 06 new seed: 004e
1311309.700: <09>Lane 07 scaled delay: 004f
1311409.700: <09>Lane 07 new seed: 004f
1311509.700: <09>Lane 08 scaled delay: 004b
1311609.700: <09>Lane 08 new seed: 004b
1311709.700: <09>Lane 00 nibble 0 raw readback: 005d
1311809.700: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005d
1311909.700: <09>Lane 00 nibble 0 adjusted value (post nibble): 005d
1312009.700: <09>Lane 01 nibble 0 raw readback: 0059
1312109.700: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
1312209.700: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
1312309.700: <09>Lane 02 nibble 0 raw readback: 0054
1312409.700: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
1312509.700: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
1312609.700: <09>Lane 03 nibble 0 raw readback: 0050
1312709.700: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
1312809.700: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
1312909.700: <09>Lane 04 nibble 0 raw readback: 0042
1313009.700: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
1313109.700: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
1313209.700: <09>Lane 05 nibble 0 raw readback: 0047
1313309.700: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
1313409.700: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
1313509.701: <09>Lane 06 nibble 0 raw readback: 004b
1313609.701: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
1313709.701: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
1313809.701: <09>Lane 07 nibble 0 raw readback: 004e
1313909.701: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
1314009.701: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
1314109.701: <09>Lane 08 nibble 0 raw readback: 0045
1314209.701: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
1314309.701: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
1314409.701: AgesaHwWlPhase1: training nibble 1
1314509.701: DIMM 0 RttNom: 3
1314609.701: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1314709.701: DIMM 0 RttWr: 1
1314809.701: DIMM 0 RttWr: 1
1314909.701: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1315009.701: DIMM 0 RttWr: 1
1315109.701: DIMM 0 RttNom: 3
1315209.701: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1315309.701: DIMM 0 RttNom: 3
1315409.701: DIMM 0 RttWr: 1
1315509.701: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1315609.701: DIMM 0 RttWr: 1
1315709.701: DIMM 1 RttNom: 3
1315809.701: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1315909.701: DIMM 0 RttNom: 3
1316009.701: DIMM 1 RttWr: 1
1316109.701: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1316209.701: DIMM 0 RttWr: 1
1316309.701: DIMM 1 RttNom: 3
1316409.701: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1316509.701: DIMM 0 RttNom: 3
1316609.701: DIMM 1 RttWr: 1
1316709.701: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1316809.701: DIMM 0 RttWr: 1
1316909.701: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1317009.701: <09>Lane 00 new seed: 0057
1317109.701: <09>Lane 01 new seed: 0055
1317209.701: <09>Lane 02 new seed: 0053
1317309.701: <09>Lane 03 new seed: 0051
1317409.701: <09>Lane 04 new seed: 004a
1317509.701: <09>Lane 05 new seed: 004d
1317609.701: <09>Lane 06 new seed: 004e
1317709.701: <09>Lane 07 new seed: 004f
1317809.701: <09>Lane 08 new seed: 004b
1317909.701: <09>Lane 00 nibble 1 raw readback: 005d
1318009.701: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
1318109.701: <09>Lane 00 nibble 1 adjusted value (post nibble): 005a
1318209.701: <09>Lane 01 nibble 1 raw readback: 0058
1318309.701: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
1318409.701: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
1318509.701: <09>Lane 02 nibble 1 raw readback: 0055
1318609.701: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
1318709.701: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
1318809.701: <09>Lane 03 nibble 1 raw readback: 0051
1318909.701: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
1319009.701: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
1319109.701: <09>Lane 04 nibble 1 raw readback: 0041
1319209.701: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
1319309.701: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
1319409.701: <09>Lane 05 nibble 1 raw readback: 0047
1319509.701: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
1319609.701: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
1319709.701: <09>Lane 06 nibble 1 raw readback: 004a
1319809.701: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
1319909.701: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
1320009.701: <09>Lane 07 nibble 1 raw readback: 004d
1320109.701: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
1320209.701: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
1320309.701: <09>Lane 08 nibble 1 raw readback: 0045
1320409.701: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
1320509.701: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
1320609.701: <09>original critical gross delay: 0
1320709.702: <09>new critical gross delay: 0
1320809.702: DIMM 0 RttNom: 3
1320909.702: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1321009.702: DIMM 0 RttNom: 3
1321109.702: DIMM 0 RttWr: 1
1321209.702: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1321309.702: DIMM 0 RttWr: 1
1321409.702: DIMM 0 RttNom: 3
1321509.702: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1321609.702: DIMM 0 RttNom: 3
1321709.702: DIMM 0 RttWr: 1
1321809.702: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1321909.702: DIMM 0 RttWr: 1
1322009.702: DIMM 1 RttNom: 3
1322109.702: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1322209.702: DIMM 0 RttNom: 3
1322309.702: DIMM 1 RttWr: 1
1322409.702: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1322509.702: DIMM 0 RttWr: 1
1322609.702: DIMM 1 RttNom: 3
1322709.702: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1322809.702: DIMM 0 RttNom: 3
1322909.702: DIMM 1 RttWr: 1
1323009.702: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1323109.702: DIMM 0 RttWr: 1
1323209.702: AgesaHwWlPhase1: training nibble 0
1323309.702: DIMM 1 RttNom: 3
1323409.702: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1323509.702: DIMM 1 RttWr: 1
1323609.702: DIMM 1 RttWr: 1
1323709.702: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1323809.702: DIMM 1 RttWr: 1
1323909.702: DIMM 1 RttNom: 3
1324009.702: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1324109.702: DIMM 1 RttNom: 3
1324209.702: DIMM 1 RttWr: 1
1324309.702: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1324409.702: DIMM 1 RttWr: 1
1324509.702: DIMM 0 RttNom: 3
1324609.702: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1324709.702: DIMM 1 RttNom: 3
1324809.702: DIMM 0 RttWr: 1
1324909.702: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1325009.702: DIMM 1 RttWr: 1
1325109.702: DIMM 0 RttNom: 3
1325209.702: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1325309.702: DIMM 1 RttNom: 3
1325409.702: DIMM 0 RttWr: 1
1325509.702: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1325609.702: DIMM 1 RttWr: 1
1325709.702: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1325809.702: <09>Lane 00 scaled delay: 0051
1325909.702: <09>Lane 00 new seed: 0051
1326009.702: <09>Lane 01 scaled delay: 004e
1326109.702: <09>Lane 01 new seed: 004e
1326209.702: <09>Lane 02 scaled delay: 004b
1326309.703: <09>Lane 02 new seed: 004b
1326409.703: <09>Lane 03 scaled delay: 004b
1326509.703: <09>Lane 03 new seed: 004b
1326609.703: <09>Lane 04 scaled delay: 0043
1326709.703: <09>Lane 04 new seed: 0043
1326809.703: <09>Lane 05 scaled delay: 0046
1326909.703: <09>Lane 05 new seed: 0046
1327009.703: <09>Lane 06 scaled delay: 0047
1327109.703: <09>Lane 06 new seed: 0047
1327209.703: <09>Lane 07 scaled delay: 004a
1327309.703: <09>Lane 07 new seed: 004a
1327409.703: <09>Lane 08 scaled delay: 0045
1327509.703: <09>Lane 08 new seed: 0045
1327609.703: <09>Lane 00 nibble 0 raw readback: 0050
1327709.703: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
1327809.703: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
1327909.703: <09>Lane 01 nibble 0 raw readback: 004b
1328009.703: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
1328109.703: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
1328209.703: <09>Lane 02 nibble 0 raw readback: 0048
1328309.703: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
1328409.703: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
1328509.703: <09>Lane 03 nibble 0 raw readback: 0044
1328609.703: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
1328709.703: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
1328809.703: <09>Lane 04 nibble 0 raw readback: 0035
1328909.703: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0035
1329009.703: <09>Lane 04 nibble 0 adjusted value (post nibble): 0035
1329109.703: <09>Lane 05 nibble 0 raw readback: 003a
1329209.703: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003a
1329309.703: <09>Lane 05 nibble 0 adjusted value (post nibble): 003a
1329409.703: <09>Lane 06 nibble 0 raw readback: 003d
1329509.703: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
1329609.703: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
1329709.703: <09>Lane 07 nibble 0 raw readback: 0042
1329809.703: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
1329909.703: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
1330009.703: <09>Lane 08 nibble 0 raw readback: 0039
1330109.703: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
1330209.703: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
1330309.703: AgesaHwWlPhase1: training nibble 1
1330409.703: DIMM 1 RttNom: 3
1330509.703: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1330609.703: DIMM 1 RttWr: 1
1330709.703: DIMM 1 RttWr: 1
1330809.703: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1330909.703: DIMM 1 RttWr: 1
1331009.703: DIMM 1 RttNom: 3
1331109.703: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1331209.703: DIMM 1 RttNom: 3
1331309.703: DIMM 1 RttWr: 1
1331409.703: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1331509.703: DIMM 1 RttWr: 1
1331609.703: DIMM 0 RttNom: 3
1331709.703: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1331809.703: DIMM 1 RttNom: 3
1331909.703: DIMM 0 RttWr: 1
1332009.703: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1332109.703: DIMM 1 RttWr: 1
1332209.703: DIMM 0 RttNom: 3
1332309.703: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1332409.703: DIMM 1 RttNom: 3
1332509.703: DIMM 0 RttWr: 1
1332609.703: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1332709.703: DIMM 1 RttWr: 1
1332809.704: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1332909.703: <09>Lane 00 new seed: 0051
1333009.703: <09>Lane 01 new seed: 004e
1333109.703: <09>Lane 02 new seed: 004b
1333209.703: <09>Lane 03 new seed: 004b
1333309.703: <09>Lane 04 new seed: 0043
1333409.703: <09>Lane 05 new seed: 0046
1333509.703: <09>Lane 06 new seed: 0047
1333609.704: <09>Lane 07 new seed: 004a
1333709.703: <09>Lane 08 new seed: 0045
1333809.704: <09>Lane 00 nibble 1 raw readback: 004f
1333909.704: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
1334009.704: <09>Lane 00 nibble 1 adjusted value (post nibble): 0050
1334109.704: <09>Lane 01 nibble 1 raw readback: 004a
1334209.704: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
1334309.704: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
1334409.704: <09>Lane 02 nibble 1 raw readback: 0047
1334509.704: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
1334609.704: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
1334709.704: <09>Lane 03 nibble 1 raw readback: 0045
1334809.704: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
1334909.704: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1335009.704: <09>Lane 04 nibble 1 raw readback: 0035
1335109.704: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0035
1335209.704: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
1335309.704: <09>Lane 05 nibble 1 raw readback: 003a
1335409.704: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
1335509.704: <09>Lane 05 nibble 1 adjusted value (post nibble): 0040
1335609.704: <09>Lane 06 nibble 1 raw readback: 003d
1335709.704: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
1335809.704: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
1335909.704: <09>Lane 07 nibble 1 raw readback: 0041
1336009.704: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
1336109.704: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
1336209.704: <09>Lane 08 nibble 1 raw readback: 003a
1336309.704: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
1336409.704: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
1336509.704: <09>original critical gross delay: 0
1336609.704: <09>new critical gross delay: 0
1336709.704: DIMM 1 RttNom: 3
1336809.704: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1336909.704: DIMM 1 RttNom: 3
1337009.704: DIMM 1 RttWr: 1
1337109.704: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1337209.704: DIMM 1 RttWr: 1
1337309.704: DIMM 1 RttNom: 3
1337409.704: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1337509.704: DIMM 1 RttNom: 3
1337609.704: DIMM 1 RttWr: 1
1337709.704: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1337809.704: DIMM 1 RttWr: 1
1337909.704: DIMM 0 RttNom: 3
1338009.704: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1338109.704: DIMM 1 RttNom: 3
1338209.704: DIMM 0 RttWr: 1
1338309.704: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1338409.704: DIMM 1 RttWr: 1
1338509.704: DIMM 0 RttNom: 3
1338609.704: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1338709.704: DIMM 1 RttNom: 3
1338809.704: DIMM 0 RttWr: 1
1338909.704: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1339009.704: DIMM 1 RttWr: 1
1339109.704: SetTargetFreq: Start
1339209.704: SetTargetFreq: Node 2: New frequency code: 000e
1339309.705: ChangeMemClk: Start
1339409.705: set_2t_configuration: Start
1339509.705: set_2t_configuration: Done
1339609.705: mct_BeforePlatformSpec: Start
1339709.705: mct_BeforePlatformSpec: Done
1339809.705: mct_PlatformSpec: Start
1339909.705: Programmed DCT 0 timing/termination pattern 00383a38 30222222
1340009.705: mct_PlatformSpec: Done
1340109.705: set_2t_configuration: Start
1340209.705: set_2t_configuration: Done
1340309.705: mct_BeforePlatformSpec: Start
1340409.705: mct_BeforePlatformSpec: Done
1340509.705: mct_PlatformSpec: Start
1340609.705: Programmed DCT 1 timing/termination pattern 00383a38 30222222
1340709.705: mct_PlatformSpec: Done
1340809.705: ChangeMemClk: Done
1340909.705: phyAssistedMemFnceTraining: Start
1341009.705: phyAssistedMemFnceTraining: training node 2 DCT 0
1341109.705: phyAssistedMemFnceTraining: done training node 2 DCT 0
1341209.705: phyAssistedMemFnceTraining: training node 2 DCT 1
1341309.705: phyAssistedMemFnceTraining: done training node 2 DCT 1
1341409.705: phyAssistedMemFnceTraining: Done
1341509.705: InitPhyCompensation: DCT 0: Start
1341609.705: Waiting for predriver calibration to be applied...done!
1341709.705: InitPhyCompensation: DCT 0: Done
1341809.706: phyAssistedMemFnceTraining: Start
1341909.706: phyAssistedMemFnceTraining: training node 2 DCT 0
1342009.706: phyAssistedMemFnceTraining: done training node 2 DCT 0
1342109.706: phyAssistedMemFnceTraining: training node 2 DCT 1
1342209.706: phyAssistedMemFnceTraining: done training node 2 DCT 1
1342309.706: phyAssistedMemFnceTraining: Done
1342409.706: InitPhyCompensation: DCT 1: Start
1342509.706: Waiting for predriver calibration to be applied...done!
1342609.706: InitPhyCompensation: DCT 1: Done
1342709.706: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
1342809.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1342909.706: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1343009.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1343109.706: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1343209.706: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
1343309.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1343409.706: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1343509.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1343609.706: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1343709.706: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
1343809.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1343909.706: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1344009.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1344109.706: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1344209.706: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
1344309.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1344409.706: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1344509.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1344609.706: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1344709.706: SetTargetFreq: Done
1344809.707: SPD2ndTiming: Start
1344909.707: SPD2ndTiming: Done
1345009.707: mct_BeforeDramInit_Prod_D: Start
1345109.707: mct_ProgramODT_D: Start
1345209.707: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1345309.707: mct_ProgramODT_D: Done
1345409.707: mct_BeforeDramInit_Prod_D: Done
1345509.707: mct_DramInit_Sw_D: Start
1345609.707: DIMM 0 RttWr: 2
1345709.707: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1345809.707: mct_SendMrsCmd: Start
1345909.707: mct_SendMrsCmd: Done
1346009.707: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1346109.707: mct_SendMrsCmd: Start
1346209.707: mct_SendMrsCmd: Done
1346309.707: DIMM 0 RttNom: 5
1346409.707: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1346509.707: mct_SendMrsCmd: Start
1346609.707: mct_SendMrsCmd: Done
1346709.707: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
1346809.707: mct_SendMrsCmd: Start
1346909.707: mct_SendMrsCmd: Done
1347009.707: DIMM 0 RttWr: 2
1347109.707: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1347209.707: mct_SendMrsCmd: Start
1347309.707: mct_SendMrsCmd: Done
1347409.707: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1347509.707: mct_SendMrsCmd: Start
1347609.707: mct_SendMrsCmd: Done
1347709.707: DIMM 0 RttNom: 5
1347809.707: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1347909.707: mct_SendMrsCmd: Start
1348009.707: mct_SendMrsCmd: Done
1348109.707: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
1348209.707: mct_SendMrsCmd: Start
1348309.707: mct_SendMrsCmd: Done
1348409.707: DIMM 1 RttWr: 2
1348509.707: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1348609.707: mct_SendMrsCmd: Start
1348709.707: mct_SendMrsCmd: Done
1348809.707: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1348909.707: mct_SendMrsCmd: Start
1349009.707: mct_SendMrsCmd: Done
1349109.707: DIMM 1 RttNom: 5
1349209.708: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1349309.708: mct_SendMrsCmd: Start
1349409.708: mct_SendMrsCmd: Done
1349509.708: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
1349609.708: mct_SendMrsCmd: Start
1349709.708: mct_SendMrsCmd: Done
1349809.708: DIMM 1 RttWr: 2
1349909.708: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1350009.708: mct_SendMrsCmd: Start
1350109.708: mct_SendMrsCmd: Done
1350209.708: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1350309.708: mct_SendMrsCmd: Start
1350409.708: mct_SendMrsCmd: Done
1350509.708: DIMM 1 RttNom: 5
1350609.708: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1350709.708: mct_SendMrsCmd: Start
1350809.708: mct_SendMrsCmd: Done
1350909.708: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
1351009.708: mct_SendMrsCmd: Start
1351109.708: mct_SendMrsCmd: Done
1351209.708: mct_DramInit_Sw_D: Done
1351309.708: AgesaHwWlPhase1: training nibble 0
1351409.708: DIMM 0 RttNom: 5
1351509.708: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1351609.708: DIMM 0 RttWr: 2
1351709.708: DIMM 0 RttWr: 2
1351809.708: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1351909.708: DIMM 0 RttWr: 2
1352009.708: DIMM 0 RttNom: 5
1352109.708: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1352209.708: DIMM 0 RttNom: 5
1352309.708: DIMM 0 RttWr: 2
1352409.708: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1352509.708: DIMM 0 RttWr: 2
1352609.708: DIMM 1 RttNom: 5
1352709.708: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1352809.708: DIMM 0 RttNom: 5
1352909.708: DIMM 1 RttWr: 2
1353009.708: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1353109.708: DIMM 0 RttWr: 2
1353209.708: DIMM 1 RttNom: 5
1353309.708: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1353409.708: DIMM 0 RttNom: 5
1353509.708: DIMM 1 RttWr: 2
1353609.708: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1353709.708: DIMM 0 RttWr: 2
1353809.708: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1353909.709: <09>Lane 00 scaled delay: 006b
1354009.709: <09>Lane 00 new seed: 006b
1354109.709: <09>Lane 01 scaled delay: 0064
1354209.709: <09>Lane 01 new seed: 0064
1354309.709: <09>Lane 02 scaled delay: 0061
1354409.709: <09>Lane 02 new seed: 0061
1354509.709: <09>Lane 03 scaled delay: 005e
1354609.709: <09>Lane 03 new seed: 005e
1354709.709: <09>Lane 04 scaled delay: 004f
1354809.709: <09>Lane 04 new seed: 004f
1354909.709: <09>Lane 05 scaled delay: 0054
1355009.709: <09>Lane 05 new seed: 0054
1355109.709: <09>Lane 06 scaled delay: 0059
1355209.709: <09>Lane 06 new seed: 0059
1355309.709: <09>Lane 07 scaled delay: 005c
1355409.709: <09>Lane 07 new seed: 005c
1355509.709: <09>Lane 08 scaled delay: 0052
1355609.709: <09>Lane 08 new seed: 0052
1355709.709: <09>Lane 00 nibble 0 raw readback: 0030
1355809.709: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
1355909.709: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
1356009.709: <09>Lane 01 nibble 0 raw readback: 0025
1356109.709: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
1356209.709: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
1356309.709: <09>Lane 02 nibble 0 raw readback: 0022
1356409.709: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0062
1356509.709: <09>Lane 02 nibble 0 adjusted value (post nibble): 0062
1356609.709: <09>Lane 03 nibble 0 raw readback: 005c
1356709.709: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
1356809.709: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
1356909.709: <09>Lane 04 nibble 0 raw readback: 004c
1357009.709: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
1357109.709: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
1357209.709: <09>Lane 05 nibble 0 raw readback: 0054
1357309.709: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
1357409.709: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
1357509.709: <09>Lane 06 nibble 0 raw readback: 0059
1357609.709: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0059
1357709.709: <09>Lane 06 nibble 0 adjusted value (post nibble): 0059
1357809.709: <09>Lane 07 nibble 0 raw readback: 005d
1357909.709: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005d
1358009.709: <09>Lane 07 nibble 0 adjusted value (post nibble): 005d
1358109.709: <09>Lane 08 nibble 0 raw readback: 004f
1358209.709: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004f
1358309.709: <09>Lane 08 nibble 0 adjusted value (post nibble): 004f
1358409.709: AgesaHwWlPhase1: training nibble 1
1358509.709: DIMM 0 RttNom: 5
1358609.709: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1358709.709: DIMM 0 RttWr: 2
1358809.709: DIMM 0 RttWr: 2
1358909.709: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1359009.709: DIMM 0 RttWr: 2
1359109.709: DIMM 0 RttNom: 5
1359209.709: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1359309.709: DIMM 0 RttNom: 5
1359409.709: DIMM 0 RttWr: 2
1359509.709: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1359609.709: DIMM 0 RttWr: 2
1359709.710: DIMM 1 RttNom: 5
1359809.710: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1359909.710: DIMM 0 RttNom: 5
1360009.710: DIMM 1 RttWr: 2
1360109.710: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1360209.710: DIMM 0 RttWr: 2
1360309.710: DIMM 1 RttNom: 5
1360409.710: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1360509.710: DIMM 0 RttNom: 5
1360609.710: DIMM 1 RttWr: 2
1360709.710: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1360809.710: DIMM 0 RttWr: 2
1360909.710: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1361009.710: <09>Lane 00 new seed: 006b
1361109.710: <09>Lane 01 new seed: 0064
1361209.710: <09>Lane 02 new seed: 0061
1361309.710: <09>Lane 03 new seed: 005e
1361409.710: <09>Lane 04 new seed: 004f
1361509.710: <09>Lane 05 new seed: 0054
1361609.710: <09>Lane 06 new seed: 0059
1361709.710: <09>Lane 07 new seed: 005c
1361809.710: <09>Lane 08 new seed: 0052
1361909.710: <09>Lane 00 nibble 1 raw readback: 002f
1362009.710: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
1362109.710: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
1362209.710: <09>Lane 01 nibble 1 raw readback: 0027
1362309.710: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
1362409.710: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
1362509.710: <09>Lane 02 nibble 1 raw readback: 0023
1362609.710: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0063
1362709.710: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
1362809.710: <09>Lane 03 nibble 1 raw readback: 005e
1362909.710: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005e
1363009.710: <09>Lane 03 nibble 1 adjusted value (post nibble): 005e
1363109.710: <09>Lane 04 nibble 1 raw readback: 004b
1363209.710: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
1363309.710: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
1363409.710: <09>Lane 05 nibble 1 raw readback: 0052
1363509.710: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
1363609.710: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
1363709.710: <09>Lane 06 nibble 1 raw readback: 0058
1363809.710: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
1363909.710: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
1364009.710: <09>Lane 07 nibble 1 raw readback: 005b
1364109.710: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
1364209.710: <09>Lane 07 nibble 1 adjusted value (post nibble): 005b
1364309.710: <09>Lane 08 nibble 1 raw readback: 004c
1364409.710: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004c
1364509.710: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
1364609.710: <09>original critical gross delay: 0
1364709.710: <09>new critical gross delay: 0
1364809.710: DIMM 0 RttNom: 5
1364909.710: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1365009.710: DIMM 0 RttNom: 5
1365109.710: DIMM 0 RttWr: 2
1365209.710: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1365309.710: DIMM 0 RttWr: 2
1365409.710: DIMM 0 RttNom: 5
1365509.710: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1365609.710: DIMM 0 RttNom: 5
1365709.710: DIMM 0 RttWr: 2
1365809.710: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1365909.711: DIMM 0 RttWr: 2
1366009.711: DIMM 1 RttNom: 5
1366109.711: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1366209.711: DIMM 0 RttNom: 5
1366309.711: DIMM 1 RttWr: 2
1366409.711: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1366509.711: DIMM 0 RttWr: 2
1366609.711: DIMM 1 RttNom: 5
1366709.711: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1366809.711: DIMM 0 RttNom: 5
1366909.711: DIMM 1 RttWr: 2
1367009.711: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1367109.711: DIMM 0 RttWr: 2
1367209.711: AgesaHwWlPhase1: training nibble 0
1367309.711: DIMM 1 RttNom: 5
1367409.711: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1367509.711: DIMM 1 RttWr: 2
1367609.711: DIMM 1 RttWr: 2
1367709.711: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1367809.711: DIMM 1 RttWr: 2
1367909.711: DIMM 1 RttNom: 5
1368009.711: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1368109.711: DIMM 1 RttNom: 5
1368209.711: DIMM 1 RttWr: 2
1368309.711: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1368409.711: DIMM 1 RttWr: 2
1368509.711: DIMM 0 RttNom: 5
1368609.711: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1368709.711: DIMM 1 RttNom: 5
1368809.711: DIMM 0 RttWr: 2
1368909.711: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1369009.711: DIMM 1 RttWr: 2
1369109.711: DIMM 0 RttNom: 5
1369209.711: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1369309.711: DIMM 1 RttNom: 5
1369409.711: DIMM 0 RttWr: 2
1369509.711: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1369609.711: DIMM 1 RttWr: 2
1369709.711: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1369809.711: <09>Lane 00 scaled delay: 005d
1369909.711: <09>Lane 00 new seed: 005d
1370009.711: <09>Lane 01 scaled delay: 0057
1370109.711: <09>Lane 01 new seed: 0057
1370209.711: <09>Lane 02 scaled delay: 0057
1370309.711: <09>Lane 02 new seed: 0057
1370409.711: <09>Lane 03 scaled delay: 0052
1370509.711: <09>Lane 03 new seed: 0052
1370609.711: <09>Lane 04 scaled delay: 0045
1370709.711: <09>Lane 04 new seed: 0045
1370809.711: <09>Lane 05 scaled delay: 0049
1370909.711: <09>Lane 05 new seed: 0049
1371009.711: <09>Lane 06 scaled delay: 004d
1371109.711: <09>Lane 06 new seed: 004d
1371209.711: <09>Lane 07 scaled delay: 0050
1371309.711: <09>Lane 07 new seed: 0050
1371409.711: <09>Lane 08 scaled delay: 0046
1371509.711: <09>Lane 08 new seed: 0046
1371609.711: <09>Lane 00 nibble 0 raw readback: 0061
1371709.711: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0061
1371809.711: <09>Lane 00 nibble 0 adjusted value (post nibble): 0061
1371909.711: <09>Lane 01 nibble 0 raw readback: 0056
1372009.711: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
1372109.711: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
1372209.712: <09>Lane 02 nibble 0 raw readback: 0053
1372309.711: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
1372409.712: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
1372509.712: <09>Lane 03 nibble 0 raw readback: 004d
1372609.712: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
1372709.712: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
1372809.712: <09>Lane 04 nibble 0 raw readback: 003b
1372909.712: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
1373009.712: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
1373109.712: <09>Lane 05 nibble 0 raw readback: 0044
1373209.712: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0044
1373309.712: <09>Lane 05 nibble 0 adjusted value (post nibble): 0044
1373409.712: <09>Lane 06 nibble 0 raw readback: 0049
1373509.712: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
1373609.712: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
1373709.712: <09>Lane 07 nibble 0 raw readback: 004d
1373809.712: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
1373909.712: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
1374009.712: <09>Lane 08 nibble 0 raw readback: 0040
1374109.712: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0040
1374209.712: <09>Lane 08 nibble 0 adjusted value (post nibble): 0040
1374309.712: AgesaHwWlPhase1: training nibble 1
1374409.712: DIMM 1 RttNom: 5
1374509.712: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1374609.712: DIMM 1 RttWr: 2
1374709.712: DIMM 1 RttWr: 2
1374809.712: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1374909.712: DIMM 1 RttWr: 2
1375009.712: DIMM 1 RttNom: 5
1375109.712: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1375209.712: DIMM 1 RttNom: 5
1375309.712: DIMM 1 RttWr: 2
1375409.712: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1375509.712: DIMM 1 RttWr: 2
1375609.712: DIMM 0 RttNom: 5
1375709.712: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1375809.712: DIMM 1 RttNom: 5
1375909.712: DIMM 0 RttWr: 2
1376009.712: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1376109.712: DIMM 1 RttWr: 2
1376209.712: DIMM 0 RttNom: 5
1376309.712: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1376409.712: DIMM 1 RttNom: 5
1376509.712: DIMM 0 RttWr: 2
1376609.712: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1376709.712: DIMM 1 RttWr: 2
1376809.712: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1376909.712: <09>Lane 00 new seed: 005d
1377009.712: <09>Lane 01 new seed: 0057
1377109.712: <09>Lane 02 new seed: 0057
1377209.712: <09>Lane 03 new seed: 0052
1377309.712: <09>Lane 04 new seed: 0045
1377409.712: <09>Lane 05 new seed: 0049
1377509.712: <09>Lane 06 new seed: 004d
1377609.712: <09>Lane 07 new seed: 0050
1377709.712: <09>Lane 08 new seed: 0046
1377809.712: <09>Lane 00 nibble 1 raw readback: 005f
1377909.712: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
1378009.712: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
1378109.712: <09>Lane 01 nibble 1 raw readback: 0055
1378209.712: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
1378309.712: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
1378409.712: <09>Lane 02 nibble 1 raw readback: 0056
1378509.712: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
1378609.712: <09>Lane 02 nibble 1 adjusted value (post nibble): 0056
1378709.712: <09>Lane 03 nibble 1 raw readback: 004f
1378809.712: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
1378909.712: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1379009.712: <09>Lane 04 nibble 1 raw readback: 003d
1379109.712: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003d
1379209.712: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
1379309.712: <09>Lane 05 nibble 1 raw readback: 0045
1379409.712: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
1379509.712: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
1379609.712: <09>Lane 06 nibble 1 raw readback: 0049
1379709.712: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
1379809.712: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
1379909.712: <09>Lane 07 nibble 1 raw readback: 004e
1380009.713: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
1380109.712: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
1380209.713: <09>Lane 08 nibble 1 raw readback: 0040
1380309.713: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
1380409.713: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
1380509.713: <09>original critical gross delay: 0
1380609.713: <09>new critical gross delay: 0
1380709.713: DIMM 1 RttNom: 5
1380809.713: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1380909.713: DIMM 1 RttNom: 5
1381009.713: DIMM 1 RttWr: 2
1381109.713: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1381209.713: DIMM 1 RttWr: 2
1381309.713: DIMM 1 RttNom: 5
1381409.713: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1381509.713: DIMM 1 RttNom: 5
1381609.713: DIMM 1 RttWr: 2
1381709.713: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1381809.713: DIMM 1 RttWr: 2
1381909.713: DIMM 0 RttNom: 5
1382009.713: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1382109.713: DIMM 1 RttNom: 5
1382209.713: DIMM 0 RttWr: 2
1382309.713: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1382409.713: DIMM 1 RttWr: 2
1382509.713: DIMM 0 RttNom: 5
1382609.713: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1382709.713: DIMM 1 RttNom: 5
1382809.713: DIMM 0 RttWr: 2
1382909.713: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1383009.713: DIMM 1 RttWr: 2
1383109.713: SPD2ndTiming: Start
1383209.714: SPD2ndTiming: Done
1383309.714: mct_BeforeDramInit_Prod_D: Start
1383409.714: mct_ProgramODT_D: Start
1383509.714: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1383609.714: mct_ProgramODT_D: Done
1383709.714: mct_BeforeDramInit_Prod_D: Done
1383809.714: mct_DramInit_Sw_D: Start
1383909.714: DIMM 0 RttWr: 2
1384009.714: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1384109.714: mct_SendMrsCmd: Start
1384209.714: mct_SendMrsCmd: Done
1384309.714: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1384409.714: mct_SendMrsCmd: Start
1384509.714: mct_SendMrsCmd: Done
1384609.714: DIMM 0 RttNom: 5
1384709.714: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1384809.714: mct_SendMrsCmd: Start
1384909.714: mct_SendMrsCmd: Done
1385009.714: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
1385109.714: mct_SendMrsCmd: Start
1385209.714: mct_SendMrsCmd: Done
1385309.714: DIMM 0 RttWr: 2
1385409.714: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1385509.714: mct_SendMrsCmd: Start
1385609.714: mct_SendMrsCmd: Done
1385709.714: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1385809.714: mct_SendMrsCmd: Start
1385909.714: mct_SendMrsCmd: Done
1386009.714: DIMM 0 RttNom: 5
1386109.714: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1386209.714: mct_SendMrsCmd: Start
1386309.714: mct_SendMrsCmd: Done
1386409.714: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
1386509.714: mct_SendMrsCmd: Start
1386609.714: mct_SendMrsCmd: Done
1386709.714: DIMM 1 RttWr: 2
1386809.714: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1386909.714: mct_SendMrsCmd: Start
1387009.714: mct_SendMrsCmd: Done
1387109.714: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1387209.714: mct_SendMrsCmd: Start
1387309.714: mct_SendMrsCmd: Done
1387409.714: DIMM 1 RttNom: 5
1387509.714: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1387609.714: mct_SendMrsCmd: Start
1387709.714: mct_SendMrsCmd: Done
1387809.714: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
1387909.714: mct_SendMrsCmd: Start
1388009.714: mct_SendMrsCmd: Done
1388109.714: DIMM 1 RttWr: 2
1388209.714: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1388309.714: mct_SendMrsCmd: Start
1388409.714: mct_SendMrsCmd: Done
1388509.714: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1388609.714: mct_SendMrsCmd: Start
1388709.714: mct_SendMrsCmd: Done
1388809.714: DIMM 1 RttNom: 5
1388909.714: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1389009.714: mct_SendMrsCmd: Start
1389109.714: mct_SendMrsCmd: Done
1389209.714: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
1389309.714: mct_SendMrsCmd: Start
1389409.714: mct_SendMrsCmd: Done
1389509.714: mct_DramInit_Sw_D: Done
1389609.714: AgesaHwWlPhase1: training nibble 0
1389709.714: DIMM 0 RttNom: 5
1389809.714: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1389909.714: DIMM 0 RttWr: 2
1390009.715: DIMM 0 RttWr: 2
1390109.715: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1390209.715: DIMM 0 RttWr: 2
1390309.715: DIMM 0 RttNom: 5
1390409.715: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1390509.715: DIMM 0 RttNom: 5
1390609.715: DIMM 0 RttWr: 2
1390709.715: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1390809.715: DIMM 0 RttWr: 2
1390909.715: DIMM 1 RttNom: 5
1391009.715: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1391109.715: DIMM 0 RttNom: 5
1391209.715: DIMM 1 RttWr: 2
1391309.715: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1391409.715: DIMM 0 RttWr: 2
1391509.715: DIMM 1 RttNom: 5
1391609.715: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1391709.715: DIMM 0 RttNom: 5
1391809.715: DIMM 1 RttWr: 2
1391909.715: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1392009.715: DIMM 0 RttWr: 2
1392109.715: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1392209.715: <09>Lane 00 scaled delay: 0068
1392309.715: <09>Lane 00 new seed: 0068
1392409.715: <09>Lane 01 scaled delay: 0063
1392509.715: <09>Lane 01 new seed: 0063
1392609.715: <09>Lane 02 scaled delay: 0061
1392709.715: <09>Lane 02 new seed: 0061
1392809.715: <09>Lane 03 scaled delay: 005d
1392909.715: <09>Lane 03 new seed: 005d
1393009.715: <09>Lane 04 scaled delay: 004e
1393109.715: <09>Lane 04 new seed: 004e
1393209.715: <09>Lane 05 scaled delay: 0054
1393309.715: <09>Lane 05 new seed: 0054
1393409.715: <09>Lane 06 scaled delay: 0057
1393509.715: <09>Lane 06 new seed: 0057
1393609.715: <09>Lane 07 scaled delay: 0059
1393709.715: <09>Lane 07 new seed: 0059
1393809.715: <09>Lane 08 scaled delay: 0052
1393909.715: <09>Lane 08 new seed: 0052
1394009.715: <09>Lane 00 nibble 0 raw readback: 002c
1394109.715: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006c
1394209.715: <09>Lane 00 nibble 0 adjusted value (post nibble): 006c
1394309.715: <09>Lane 01 nibble 0 raw readback: 0028
1394409.715: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0068
1394509.715: <09>Lane 01 nibble 0 adjusted value (post nibble): 0068
1394609.715: <09>Lane 02 nibble 0 raw readback: 0021
1394709.715: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
1394809.715: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
1394909.715: <09>Lane 03 nibble 0 raw readback: 005c
1395009.715: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
1395109.715: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
1395209.715: <09>Lane 04 nibble 0 raw readback: 004a
1395309.715: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
1395409.715: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
1395509.716: <09>Lane 05 nibble 0 raw readback: 0051
1395609.716: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
1395709.716: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
1395809.716: <09>Lane 06 nibble 0 raw readback: 0057
1395909.716: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
1396009.716: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
1396109.716: <09>Lane 07 nibble 0 raw readback: 005b
1396209.716: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
1396309.716: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
1396409.716: <09>Lane 08 nibble 0 raw readback: 004e
1396509.716: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
1396609.716: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
1396709.716: AgesaHwWlPhase1: training nibble 1
1396809.716: DIMM 0 RttNom: 5
1396909.716: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1397009.716: DIMM 0 RttWr: 2
1397109.716: DIMM 0 RttWr: 2
1397209.716: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1397309.716: DIMM 0 RttWr: 2
1397409.716: DIMM 0 RttNom: 5
1397509.716: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1397609.716: DIMM 0 RttNom: 5
1397709.716: DIMM 0 RttWr: 2
1397809.716: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1397909.716: DIMM 0 RttWr: 2
1398009.716: DIMM 1 RttNom: 5
1398109.716: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1398209.716: DIMM 0 RttNom: 5
1398309.716: DIMM 1 RttWr: 2
1398409.716: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1398509.716: DIMM 0 RttWr: 2
1398609.716: DIMM 1 RttNom: 5
1398709.716: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1398809.716: DIMM 0 RttNom: 5
1398909.716: DIMM 1 RttWr: 2
1399009.716: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1399109.716: DIMM 0 RttWr: 2
1399209.716: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1399309.716: <09>Lane 00 new seed: 0068
1399409.716: <09>Lane 01 new seed: 0063
1399509.716: <09>Lane 02 new seed: 0061
1399609.716: <09>Lane 03 new seed: 005d
1399709.716: <09>Lane 04 new seed: 004e
1399809.716: <09>Lane 05 new seed: 0054
1399909.716: <09>Lane 06 new seed: 0057
1400009.716: <09>Lane 07 new seed: 0059
1400109.716: <09>Lane 08 new seed: 0052
1400209.716: <09>Lane 00 nibble 1 raw readback: 002c
1400309.716: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
1400409.716: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
1400509.716: <09>Lane 01 nibble 1 raw readback: 0026
1400609.716: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
1400709.716: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
1400809.716: <09>Lane 02 nibble 1 raw readback: 0021
1400909.716: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
1401009.716: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
1401109.716: <09>Lane 03 nibble 1 raw readback: 005d
1401209.716: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
1401309.716: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
1401409.716: <09>Lane 04 nibble 1 raw readback: 0049
1401509.716: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
1401609.716: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
1401709.716: <09>Lane 05 nibble 1 raw readback: 0051
1401809.716: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0051
1401909.716: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
1402009.716: <09>Lane 06 nibble 1 raw readback: 0056
1402109.716: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
1402209.716: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
1402309.716: <09>Lane 07 nibble 1 raw readback: 0059
1402409.716: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0059
1402509.717: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
1402609.717: <09>Lane 08 nibble 1 raw readback: 004e
1402709.717: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
1402809.717: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
1402909.717: <09>original critical gross delay: 0
1403009.717: <09>new critical gross delay: 0
1403109.717: DIMM 0 RttNom: 5
1403209.717: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1403309.717: DIMM 0 RttNom: 5
1403409.717: DIMM 0 RttWr: 2
1403509.717: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1403609.717: DIMM 0 RttWr: 2
1403709.717: DIMM 0 RttNom: 5
1403809.717: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1403909.717: DIMM 0 RttNom: 5
1404009.717: DIMM 0 RttWr: 2
1404109.717: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1404209.717: DIMM 0 RttWr: 2
1404309.717: DIMM 1 RttNom: 5
1404409.717: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1404509.717: DIMM 0 RttNom: 5
1404609.717: DIMM 1 RttWr: 2
1404709.717: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1404809.717: DIMM 0 RttWr: 2
1404909.717: DIMM 1 RttNom: 5
1405009.717: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1405109.717: DIMM 0 RttNom: 5
1405209.717: DIMM 1 RttWr: 2
1405309.717: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1405409.717: DIMM 0 RttWr: 2
1405509.717: AgesaHwWlPhase1: training nibble 0
1405609.717: DIMM 1 RttNom: 5
1405709.717: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1405809.717: DIMM 1 RttWr: 2
1405909.717: DIMM 1 RttWr: 2
1406009.717: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1406109.717: DIMM 1 RttWr: 2
1406209.717: DIMM 1 RttNom: 5
1406309.717: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1406409.717: DIMM 1 RttNom: 5
1406509.717: DIMM 1 RttWr: 2
1406609.717: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1406709.717: DIMM 1 RttWr: 2
1406809.717: DIMM 0 RttNom: 5
1406909.717: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1407009.717: DIMM 1 RttNom: 5
1407109.717: DIMM 0 RttWr: 2
1407209.717: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1407309.717: DIMM 1 RttWr: 2
1407409.717: DIMM 0 RttNom: 5
1407509.717: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1407609.717: DIMM 1 RttNom: 5
1407709.717: DIMM 0 RttWr: 2
1407809.717: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1407909.717: DIMM 1 RttWr: 2
1408009.717: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1408109.717: <09>Lane 00 scaled delay: 005c
1408209.718: <09>Lane 00 new seed: 005c
1408309.718: <09>Lane 01 scaled delay: 0057
1408409.718: <09>Lane 01 new seed: 0057
1408509.718: <09>Lane 02 scaled delay: 0053
1408609.718: <09>Lane 02 new seed: 0053
1408709.718: <09>Lane 03 scaled delay: 0052
1408809.718: <09>Lane 03 new seed: 0052
1408909.718: <09>Lane 04 scaled delay: 0043
1409009.718: <09>Lane 04 new seed: 0043
1409109.718: <09>Lane 05 scaled delay: 0048
1409209.718: <09>Lane 05 new seed: 0048
1409309.718: <09>Lane 06 scaled delay: 004a
1409409.718: <09>Lane 06 new seed: 004a
1409509.718: <09>Lane 07 scaled delay: 004e
1409609.718: <09>Lane 07 new seed: 004e
1409709.718: <09>Lane 08 scaled delay: 0046
1409809.718: <09>Lane 08 new seed: 0046
1409909.718: <09>Lane 00 nibble 0 raw readback: 005c
1410009.718: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
1410109.718: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
1410209.718: <09>Lane 01 nibble 0 raw readback: 0056
1410309.718: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
1410409.718: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
1410509.718: <09>Lane 02 nibble 0 raw readback: 0050
1410609.718: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
1410709.718: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
1410809.718: <09>Lane 03 nibble 0 raw readback: 004b
1410909.718: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004b
1411009.718: <09>Lane 03 nibble 0 adjusted value (post nibble): 004b
1411109.718: <09>Lane 04 nibble 0 raw readback: 0039
1411209.718: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
1411309.718: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
1411409.718: <09>Lane 05 nibble 0 raw readback: 0041
1411509.718: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
1411609.718: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
1411709.718: <09>Lane 06 nibble 0 raw readback: 0045
1411809.718: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0045
1411909.718: <09>Lane 06 nibble 0 adjusted value (post nibble): 0045
1412009.718: <09>Lane 07 nibble 0 raw readback: 004b
1412109.718: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004b
1412209.718: <09>Lane 07 nibble 0 adjusted value (post nibble): 004b
1412309.718: <09>Lane 08 nibble 0 raw readback: 003e
1412409.718: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
1412509.718: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
1412609.718: AgesaHwWlPhase1: training nibble 1
1412709.718: DIMM 1 RttNom: 5
1412809.718: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1412909.718: DIMM 1 RttWr: 2
1413009.718: DIMM 1 RttWr: 2
1413109.718: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1413209.718: DIMM 1 RttWr: 2
1413309.718: DIMM 1 RttNom: 5
1413409.718: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1413509.718: DIMM 1 RttNom: 5
1413609.718: DIMM 1 RttWr: 2
1413709.718: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1413809.718: DIMM 1 RttWr: 2
1413909.718: DIMM 0 RttNom: 5
1414009.718: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1414109.718: DIMM 1 RttNom: 5
1414209.718: DIMM 0 RttWr: 2
1414309.718: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1414409.718: DIMM 1 RttWr: 2
1414509.718: DIMM 0 RttNom: 5
1414609.718: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1414709.718: DIMM 1 RttNom: 5
1414809.718: DIMM 0 RttWr: 2
1414909.718: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1415009.718: DIMM 1 RttWr: 2
1415109.719: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1415209.718: <09>Lane 00 new seed: 005c
1415309.718: <09>Lane 01 new seed: 0057
1415409.718: <09>Lane 02 new seed: 0053
1415509.718: <09>Lane 03 new seed: 0052
1415609.719: <09>Lane 04 new seed: 0043
1415709.719: <09>Lane 05 new seed: 0048
1415809.719: <09>Lane 06 new seed: 004a
1415909.719: <09>Lane 07 new seed: 004e
1416009.719: <09>Lane 08 new seed: 0046
1416109.719: <09>Lane 00 nibble 1 raw readback: 005b
1416209.719: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005b
1416309.719: <09>Lane 00 nibble 1 adjusted value (post nibble): 005b
1416409.719: <09>Lane 01 nibble 1 raw readback: 0055
1416509.719: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
1416609.719: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
1416709.719: <09>Lane 02 nibble 1 raw readback: 0050
1416809.719: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0050
1416909.719: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
1417009.719: <09>Lane 03 nibble 1 raw readback: 004d
1417109.719: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
1417209.719: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
1417309.719: <09>Lane 04 nibble 1 raw readback: 003a
1417409.719: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
1417509.719: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
1417609.719: <09>Lane 05 nibble 1 raw readback: 0041
1417709.719: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0041
1417809.719: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
1417909.719: <09>Lane 06 nibble 1 raw readback: 0046
1418009.719: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
1418109.719: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
1418209.719: <09>Lane 07 nibble 1 raw readback: 004b
1418309.719: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
1418409.719: <09>Lane 07 nibble 1 adjusted value (post nibble): 004c
1418509.719: <09>Lane 08 nibble 1 raw readback: 003f
1418609.719: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
1418709.719: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
1418809.719: <09>original critical gross delay: 0
1418909.719: <09>new critical gross delay: 0
1419009.719: DIMM 1 RttNom: 5
1419109.719: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1419209.719: DIMM 1 RttNom: 5
1419309.719: DIMM 1 RttWr: 2
1419409.719: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1419509.719: DIMM 1 RttWr: 2
1419609.719: DIMM 1 RttNom: 5
1419709.719: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1419809.719: DIMM 1 RttNom: 5
1419909.719: DIMM 1 RttWr: 2
1420009.719: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1420109.719: DIMM 1 RttWr: 2
1420209.719: DIMM 0 RttNom: 5
1420309.719: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1420409.719: DIMM 1 RttNom: 5
1420509.719: DIMM 0 RttWr: 2
1420609.719: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1420709.719: DIMM 1 RttWr: 2
1420809.719: DIMM 0 RttNom: 5
1420909.719: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1421009.719: DIMM 1 RttNom: 5
1421109.719: DIMM 0 RttWr: 2
1421209.719: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1421309.719: DIMM 1 RttWr: 2
1421409.720: SetTargetFreq: Start
1421509.720: SetTargetFreq: Node 2: New frequency code: 0012
1421609.720: ChangeMemClk: Start
1421709.720: set_2t_configuration: Start
1421809.720: set_2t_configuration: Done
1421909.720: mct_BeforePlatformSpec: Start
1422009.720: mct_BeforePlatformSpec: Done
1422109.720: mct_PlatformSpec: Start
1422209.720: Programmed DCT 0 timing/termination pattern 00353935 30222222
1422309.720: mct_PlatformSpec: Done
1422409.720: set_2t_configuration: Start
1422509.720: set_2t_configuration: Done
1422609.720: mct_BeforePlatformSpec: Start
1422709.720: mct_BeforePlatformSpec: Done
1422809.720: mct_PlatformSpec: Start
1422909.720: Programmed DCT 1 timing/termination pattern 00353935 30222222
1423009.720: mct_PlatformSpec: Done
1423109.720: ChangeMemClk: Done
1423209.720: phyAssistedMemFnceTraining: Start
1423309.720: phyAssistedMemFnceTraining: training node 2 DCT 0
1423409.720: phyAssistedMemFnceTraining: done training node 2 DCT 0
1423509.720: phyAssistedMemFnceTraining: training node 2 DCT 1
1423609.720: phyAssistedMemFnceTraining: done training node 2 DCT 1
1423709.720: phyAssistedMemFnceTraining: Done
1423809.720: InitPhyCompensation: DCT 0: Start
1423909.720: Waiting for predriver calibration to be applied...done!
1424009.721: InitPhyCompensation: DCT 0: Done
1424109.721: phyAssistedMemFnceTraining: Start
1424209.721: phyAssistedMemFnceTraining: training node 2 DCT 0
1424309.721: phyAssistedMemFnceTraining: done training node 2 DCT 0
1424409.721: phyAssistedMemFnceTraining: training node 2 DCT 1
1424509.721: phyAssistedMemFnceTraining: done training node 2 DCT 1
1424609.721: phyAssistedMemFnceTraining: Done
1424709.721: InitPhyCompensation: DCT 1: Start
1424809.721: Waiting for predriver calibration to be applied...done!
1424909.721: InitPhyCompensation: DCT 1: Done
1425009.721: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
1425109.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1425209.721: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1425309.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1425409.721: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1425509.721: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
1425609.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1425709.721: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1425809.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1425909.721: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1426009.721: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
1426109.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1426209.721: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1426309.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1426409.721: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1426509.722: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
1426609.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1426709.721: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1426809.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1426909.722: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1427009.722: SetTargetFreq: Done
1427109.722: SPD2ndTiming: Start
1427209.722: SPD2ndTiming: Done
1427309.722: mct_BeforeDramInit_Prod_D: Start
1427409.722: mct_ProgramODT_D: Start
1427509.722: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1427609.722: mct_ProgramODT_D: Done
1427709.722: mct_BeforeDramInit_Prod_D: Done
1427809.722: mct_DramInit_Sw_D: Start
1427909.722: DIMM 0 RttWr: 1
1428009.722: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1428109.722: mct_SendMrsCmd: Start
1428209.722: mct_SendMrsCmd: Done
1428309.722: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1428409.722: mct_SendMrsCmd: Start
1428509.722: mct_SendMrsCmd: Done
1428609.722: DIMM 0 RttNom: 4
1428709.722: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1428809.722: mct_SendMrsCmd: Start
1428909.722: mct_SendMrsCmd: Done
1429009.722: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
1429109.722: mct_SendMrsCmd: Start
1429209.722: mct_SendMrsCmd: Done
1429309.722: DIMM 0 RttWr: 1
1429409.722: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1429509.722: mct_SendMrsCmd: Start
1429609.722: mct_SendMrsCmd: Done
1429709.722: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1429809.722: mct_SendMrsCmd: Start
1429909.722: mct_SendMrsCmd: Done
1430009.722: DIMM 0 RttNom: 4
1430109.722: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1430209.722: mct_SendMrsCmd: Start
1430309.722: mct_SendMrsCmd: Done
1430409.722: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
1430509.722: mct_SendMrsCmd: Start
1430609.722: mct_SendMrsCmd: Done
1430709.722: DIMM 1 RttWr: 1
1430809.722: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1430909.722: mct_SendMrsCmd: Start
1431009.722: mct_SendMrsCmd: Done
1431109.722: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1431209.722: mct_SendMrsCmd: Start
1431309.723: mct_SendMrsCmd: Done
1431409.723: DIMM 1 RttNom: 4
1431509.723: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1431609.723: mct_SendMrsCmd: Start
1431709.723: mct_SendMrsCmd: Done
1431809.723: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
1431909.723: mct_SendMrsCmd: Start
1432009.723: mct_SendMrsCmd: Done
1432109.723: DIMM 1 RttWr: 1
1432209.723: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1432309.723: mct_SendMrsCmd: Start
1432409.723: mct_SendMrsCmd: Done
1432509.723: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1432609.723: mct_SendMrsCmd: Start
1432709.723: mct_SendMrsCmd: Done
1432809.723: DIMM 1 RttNom: 4
1432909.723: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1433009.723: mct_SendMrsCmd: Start
1433109.723: mct_SendMrsCmd: Done
1433209.723: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
1433309.723: mct_SendMrsCmd: Start
1433409.723: mct_SendMrsCmd: Done
1433509.723: mct_DramInit_Sw_D: Done
1433609.723: AgesaHwWlPhase1: training nibble 0
1433709.723: DIMM 0 RttNom: 4
1433809.723: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1433909.723: DIMM 0 RttWr: 1
1434009.723: DIMM 0 RttWr: 1
1434109.723: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1434209.723: DIMM 0 RttWr: 1
1434309.723: DIMM 0 RttNom: 4
1434409.723: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1434509.723: DIMM 0 RttNom: 4
1434609.723: DIMM 0 RttWr: 1
1434709.723: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1434809.723: DIMM 0 RttWr: 1
1434909.723: DIMM 1 RttNom: 4
1435009.723: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1435109.723: DIMM 0 RttNom: 4
1435209.723: DIMM 1 RttWr: 1
1435309.723: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1435409.723: DIMM 0 RttWr: 1
1435509.723: DIMM 1 RttNom: 4
1435609.723: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1435709.723: DIMM 0 RttNom: 4
1435809.723: DIMM 1 RttWr: 1
1435909.723: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1436009.723: DIMM 0 RttWr: 1
1436109.723: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1436209.724: <09>Lane 00 scaled delay: 007c
1436309.724: <09>Lane 00 new seed: 007c
1436409.724: <09>Lane 01 scaled delay: 0072
1436509.724: <09>Lane 01 new seed: 0072
1436609.724: <09>Lane 02 scaled delay: 006f
1436709.724: <09>Lane 02 new seed: 006f
1436809.724: <09>Lane 03 scaled delay: 006a
1436909.724: <09>Lane 03 new seed: 006a
1437009.724: <09>Lane 04 scaled delay: 0055
1437109.724: <09>Lane 04 new seed: 0055
1437209.724: <09>Lane 05 scaled delay: 005d
1437309.724: <09>Lane 05 new seed: 005d
1437409.724: <09>Lane 06 scaled delay: 0063
1437509.724: <09>Lane 06 new seed: 0063
1437609.724: <09>Lane 07 scaled delay: 0066
1437709.724: <09>Lane 07 new seed: 0066
1437809.724: <09>Lane 08 scaled delay: 0058
1437909.724: <09>Lane 08 new seed: 0058
1438009.724: <09>Lane 00 nibble 0 raw readback: 0042
1438109.724: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0082
1438209.724: <09>Lane 00 nibble 0 adjusted value (post nibble): 0082
1438309.724: <09>Lane 01 nibble 0 raw readback: 0034
1438409.724: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0074
1438509.724: <09>Lane 01 nibble 0 adjusted value (post nibble): 0074
1438609.724: <09>Lane 02 nibble 0 raw readback: 0032
1438709.724: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0072
1438809.724: <09>Lane 02 nibble 0 adjusted value (post nibble): 0072
1438909.724: <09>Lane 03 nibble 0 raw readback: 002c
1439009.724: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006c
1439109.724: <09>Lane 03 nibble 0 adjusted value (post nibble): 006c
1439209.724: <09>Lane 04 nibble 0 raw readback: 0059
1439309.724: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0059
1439409.724: <09>Lane 04 nibble 0 adjusted value (post nibble): 0059
1439509.724: <09>Lane 05 nibble 0 raw readback: 0060
1439609.724: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0060
1439709.724: <09>Lane 05 nibble 0 adjusted value (post nibble): 0060
1439809.724: <09>Lane 06 nibble 0 raw readback: 0026
1439909.724: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0066
1440009.724: <09>Lane 06 nibble 0 adjusted value (post nibble): 0066
1440109.724: <09>Lane 07 nibble 0 raw readback: 002b
1440209.724: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
1440309.724: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
1440409.724: <09>Lane 08 nibble 0 raw readback: 005c
1440509.724: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005c
1440609.724: <09>Lane 08 nibble 0 adjusted value (post nibble): 005c
1440709.724: AgesaHwWlPhase1: training nibble 1
1440809.724: DIMM 0 RttNom: 4
1440909.724: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1441009.724: DIMM 0 RttWr: 1
1441109.724: DIMM 0 RttWr: 1
1441209.724: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1441309.724: DIMM 0 RttWr: 1
1441409.724: DIMM 0 RttNom: 4
1441509.724: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1441609.724: DIMM 0 RttNom: 4
1441709.725: DIMM 0 RttWr: 1
1441809.725: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1441909.725: DIMM 0 RttWr: 1
1442009.725: DIMM 1 RttNom: 4
1442109.725: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1442209.725: DIMM 0 RttNom: 4
1442309.725: DIMM 1 RttWr: 1
1442409.725: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1442509.725: DIMM 0 RttWr: 1
1442609.725: DIMM 1 RttNom: 4
1442709.725: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1442809.725: DIMM 0 RttNom: 4
1442909.725: DIMM 1 RttWr: 1
1443009.725: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1443109.725: DIMM 0 RttWr: 1
1443209.725: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1443309.725: <09>Lane 00 new seed: 007c
1443409.725: <09>Lane 01 new seed: 0072
1443509.725: <09>Lane 02 new seed: 006f
1443609.725: <09>Lane 03 new seed: 006a
1443709.725: <09>Lane 04 new seed: 0055
1443809.725: <09>Lane 05 new seed: 005d
1443909.725: <09>Lane 06 new seed: 0063
1444009.725: <09>Lane 07 new seed: 0066
1444109.725: <09>Lane 08 new seed: 0058
1444209.725: <09>Lane 00 nibble 1 raw readback: 0041
1444309.725: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0081
1444409.725: <09>Lane 00 nibble 1 adjusted value (post nibble): 007e
1444509.725: <09>Lane 01 nibble 1 raw readback: 0038
1444609.725: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0078
1444709.725: <09>Lane 01 nibble 1 adjusted value (post nibble): 0075
1444809.725: <09>Lane 02 nibble 1 raw readback: 0032
1444909.725: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
1445009.725: <09>Lane 02 nibble 1 adjusted value (post nibble): 0070
1445109.725: <09>Lane 03 nibble 1 raw readback: 002c
1445209.725: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
1445309.725: <09>Lane 03 nibble 1 adjusted value (post nibble): 006b
1445409.725: <09>Lane 04 nibble 1 raw readback: 0057
1445509.725: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0057
1445609.725: <09>Lane 04 nibble 1 adjusted value (post nibble): 0056
1445709.725: <09>Lane 05 nibble 1 raw readback: 0060
1445809.725: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0060
1445909.725: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
1446009.725: <09>Lane 06 nibble 1 raw readback: 0026
1446109.725: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
1446209.725: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
1446309.725: <09>Lane 07 nibble 1 raw readback: 002a
1446409.725: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006a
1446509.725: <09>Lane 07 nibble 1 adjusted value (post nibble): 0068
1446609.725: <09>Lane 08 nibble 1 raw readback: 0059
1446709.725: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
1446809.725: <09>Lane 08 nibble 1 adjusted value (post nibble): 0058
1446909.725: <09>original critical gross delay: 0
1447009.725: <09>new critical gross delay: 0
1447109.725: DIMM 0 RttNom: 4
1447209.725: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1447309.725: DIMM 0 RttNom: 4
1447409.725: DIMM 0 RttWr: 1
1447509.725: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1447609.725: DIMM 0 RttWr: 1
1447709.725: DIMM 0 RttNom: 4
1447809.725: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1447909.725: DIMM 0 RttNom: 4
1448009.726: DIMM 0 RttWr: 1
1448109.726: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1448209.726: DIMM 0 RttWr: 1
1448309.726: DIMM 1 RttNom: 4
1448409.726: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1448509.726: DIMM 0 RttNom: 4
1448609.726: DIMM 1 RttWr: 1
1448709.726: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1448809.726: DIMM 0 RttWr: 1
1448909.726: DIMM 1 RttNom: 4
1449009.726: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1449109.726: DIMM 0 RttNom: 4
1449209.726: DIMM 1 RttWr: 1
1449309.726: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1449409.726: DIMM 0 RttWr: 1
1449509.726: AgesaHwWlPhase1: training nibble 0
1449609.726: DIMM 1 RttNom: 4
1449709.726: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1449809.726: DIMM 1 RttWr: 1
1449909.726: DIMM 1 RttWr: 1
1450009.726: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1450109.726: DIMM 1 RttWr: 1
1450209.726: DIMM 1 RttNom: 4
1450309.726: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1450409.726: DIMM 1 RttNom: 4
1450509.726: DIMM 1 RttWr: 1
1450609.726: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1450709.726: DIMM 1 RttWr: 1
1450809.726: DIMM 0 RttNom: 4
1450909.726: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1451009.726: DIMM 1 RttNom: 4
1451109.726: DIMM 0 RttWr: 1
1451209.726: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1451309.726: DIMM 1 RttWr: 1
1451409.726: DIMM 0 RttNom: 4
1451509.726: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1451609.726: DIMM 1 RttNom: 4
1451709.726: DIMM 0 RttWr: 1
1451809.726: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1451909.726: DIMM 1 RttWr: 1
1452009.726: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1452109.726: <09>Lane 00 scaled delay: 006a
1452209.726: <09>Lane 00 new seed: 006a
1452309.726: <09>Lane 01 scaled delay: 0060
1452409.726: <09>Lane 01 new seed: 0060
1452509.726: <09>Lane 02 scaled delay: 0060
1452609.726: <09>Lane 02 new seed: 0060
1452709.726: <09>Lane 03 scaled delay: 0059
1452809.726: <09>Lane 03 new seed: 0059
1452909.726: <09>Lane 04 scaled delay: 0047
1453009.726: <09>Lane 04 new seed: 0047
1453109.726: <09>Lane 05 scaled delay: 004e
1453209.726: <09>Lane 05 new seed: 004e
1453309.726: <09>Lane 06 scaled delay: 0053
1453409.726: <09>Lane 06 new seed: 0053
1453509.726: <09>Lane 07 scaled delay: 0058
1453609.726: <09>Lane 07 new seed: 0058
1453709.726: <09>Lane 08 scaled delay: 0049
1453809.726: <09>Lane 08 new seed: 0049
1453909.726: <09>Lane 00 nibble 0 raw readback: 0031
1454009.726: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0071
1454109.726: <09>Lane 00 nibble 0 adjusted value (post nibble): 0071
1454209.726: <09>Lane 01 nibble 0 raw readback: 0024
1454309.727: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
1454409.727: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
1454509.727: <09>Lane 02 nibble 0 raw readback: 0021
1454609.727: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
1454709.727: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
1454809.727: <09>Lane 03 nibble 0 raw readback: 0059
1454909.727: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
1455009.727: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
1455109.727: <09>Lane 04 nibble 0 raw readback: 0045
1455209.727: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0045
1455309.727: <09>Lane 04 nibble 0 adjusted value (post nibble): 0045
1455409.727: <09>Lane 05 nibble 0 raw readback: 004f
1455509.727: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
1455609.727: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
1455709.727: <09>Lane 06 nibble 0 raw readback: 0055
1455809.727: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
1455909.727: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
1456009.727: <09>Lane 07 nibble 0 raw readback: 005a
1456109.727: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
1456209.727: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
1456309.727: <09>Lane 08 nibble 0 raw readback: 004b
1456409.727: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
1456509.727: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
1456609.727: AgesaHwWlPhase1: training nibble 1
1456709.727: DIMM 1 RttNom: 4
1456809.727: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1456909.727: DIMM 1 RttWr: 1
1457009.727: DIMM 1 RttWr: 1
1457109.727: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1457209.727: DIMM 1 RttWr: 1
1457309.727: DIMM 1 RttNom: 4
1457409.727: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1457509.727: DIMM 1 RttNom: 4
1457609.727: DIMM 1 RttWr: 1
1457709.727: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1457809.727: DIMM 1 RttWr: 1
1457909.727: DIMM 0 RttNom: 4
1458009.727: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1458109.727: DIMM 1 RttNom: 4
1458209.727: DIMM 0 RttWr: 1
1458309.727: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1458409.727: DIMM 1 RttWr: 1
1458509.727: DIMM 0 RttNom: 4
1458609.727: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1458709.727: DIMM 1 RttNom: 4
1458809.727: DIMM 0 RttWr: 1
1458909.727: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1459009.727: DIMM 1 RttWr: 1
1459109.727: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1459209.727: <09>Lane 00 new seed: 006a
1459309.727: <09>Lane 01 new seed: 0060
1459409.727: <09>Lane 02 new seed: 0060
1459509.727: <09>Lane 03 new seed: 0059
1459609.727: <09>Lane 04 new seed: 0047
1459709.727: <09>Lane 05 new seed: 004e
1459809.727: <09>Lane 06 new seed: 0053
1459909.727: <09>Lane 07 new seed: 0058
1460009.727: <09>Lane 08 new seed: 0049
1460109.727: <09>Lane 00 nibble 1 raw readback: 0030
1460209.727: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
1460309.727: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
1460409.727: <09>Lane 01 nibble 1 raw readback: 0025
1460509.727: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
1460609.727: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
1460709.727: <09>Lane 02 nibble 1 raw readback: 0025
1460809.727: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0065
1460909.727: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
1461009.727: <09>Lane 03 nibble 1 raw readback: 005d
1461109.727: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
1461209.727: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
1461309.727: <09>Lane 04 nibble 1 raw readback: 0048
1461409.727: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
1461509.727: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
1461609.727: <09>Lane 05 nibble 1 raw readback: 004f
1461709.727: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
1461809.727: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
1461909.727: <09>Lane 06 nibble 1 raw readback: 0055
1462009.727: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
1462109.728: <09>Lane 06 nibble 1 adjusted value (post nibble): 0054
1462209.728: <09>Lane 07 nibble 1 raw readback: 005c
1462309.728: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
1462409.728: <09>Lane 07 nibble 1 adjusted value (post nibble): 005a
1462509.728: <09>Lane 08 nibble 1 raw readback: 004b
1462609.728: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004b
1462709.728: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
1462809.728: <09>original critical gross delay: 0
1462909.728: <09>new critical gross delay: 0
1463009.728: DIMM 1 RttNom: 4
1463109.728: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1463209.728: DIMM 1 RttNom: 4
1463309.728: DIMM 1 RttWr: 1
1463409.728: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1463509.728: DIMM 1 RttWr: 1
1463609.728: DIMM 1 RttNom: 4
1463709.728: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1463809.728: DIMM 1 RttNom: 4
1463909.728: DIMM 1 RttWr: 1
1464009.728: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1464109.728: DIMM 1 RttWr: 1
1464209.728: DIMM 0 RttNom: 4
1464309.728: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1464409.728: DIMM 1 RttNom: 4
1464509.728: DIMM 0 RttWr: 1
1464609.728: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1464709.728: DIMM 1 RttWr: 1
1464809.728: DIMM 0 RttNom: 4
1464909.728: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1465009.728: DIMM 1 RttNom: 4
1465109.728: DIMM 0 RttWr: 1
1465209.728: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1465309.728: DIMM 1 RttWr: 1
1465409.728: SPD2ndTiming: Start
1465509.729: SPD2ndTiming: Done
1465609.729: mct_BeforeDramInit_Prod_D: Start
1465709.729: mct_ProgramODT_D: Start
1465809.729: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1465909.729: mct_ProgramODT_D: Done
1466009.729: mct_BeforeDramInit_Prod_D: Done
1466109.729: mct_DramInit_Sw_D: Start
1466209.729: DIMM 0 RttWr: 1
1466309.729: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1466409.729: mct_SendMrsCmd: Start
1466509.729: mct_SendMrsCmd: Done
1466609.729: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1466709.729: mct_SendMrsCmd: Start
1466809.729: mct_SendMrsCmd: Done
1466909.729: DIMM 0 RttNom: 4
1467009.729: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1467109.729: mct_SendMrsCmd: Start
1467209.729: mct_SendMrsCmd: Done
1467309.729: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
1467409.729: mct_SendMrsCmd: Start
1467509.729: mct_SendMrsCmd: Done
1467609.729: DIMM 0 RttWr: 1
1467709.729: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1467809.729: mct_SendMrsCmd: Start
1467909.729: mct_SendMrsCmd: Done
1468009.729: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1468109.729: mct_SendMrsCmd: Start
1468209.729: mct_SendMrsCmd: Done
1468309.729: DIMM 0 RttNom: 4
1468409.729: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1468509.729: mct_SendMrsCmd: Start
1468609.729: mct_SendMrsCmd: Done
1468709.729: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
1468809.729: mct_SendMrsCmd: Start
1468909.729: mct_SendMrsCmd: Done
1469009.729: DIMM 1 RttWr: 1
1469109.729: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1469209.729: mct_SendMrsCmd: Start
1469309.729: mct_SendMrsCmd: Done
1469409.729: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1469509.729: mct_SendMrsCmd: Start
1469609.729: mct_SendMrsCmd: Done
1469709.729: DIMM 1 RttNom: 4
1469809.729: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1469909.729: mct_SendMrsCmd: Start
1470009.729: mct_SendMrsCmd: Done
1470109.729: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
1470209.729: mct_SendMrsCmd: Start
1470309.729: mct_SendMrsCmd: Done
1470409.729: DIMM 1 RttWr: 1
1470509.729: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1470609.729: mct_SendMrsCmd: Start
1470709.729: mct_SendMrsCmd: Done
1470809.729: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1470909.729: mct_SendMrsCmd: Start
1471009.729: mct_SendMrsCmd: Done
1471109.729: DIMM 1 RttNom: 4
1471209.729: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1471309.729: mct_SendMrsCmd: Start
1471409.729: mct_SendMrsCmd: Done
1471509.729: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
1471609.729: mct_SendMrsCmd: Start
1471709.729: mct_SendMrsCmd: Done
1471809.729: mct_DramInit_Sw_D: Done
1471909.729: AgesaHwWlPhase1: training nibble 0
1472009.730: DIMM 0 RttNom: 4
1472109.730: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1472209.730: DIMM 0 RttWr: 1
1472309.730: DIMM 0 RttWr: 1
1472409.730: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1472509.730: DIMM 0 RttWr: 1
1472609.730: DIMM 0 RttNom: 4
1472709.730: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1472809.730: DIMM 0 RttNom: 4
1472909.730: DIMM 0 RttWr: 1
1473009.730: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1473109.730: DIMM 0 RttWr: 1
1473209.730: DIMM 1 RttNom: 4
1473309.730: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1473409.730: DIMM 0 RttNom: 4
1473509.730: DIMM 1 RttWr: 1
1473609.730: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1473709.730: DIMM 0 RttWr: 1
1473809.730: DIMM 1 RttNom: 4
1473909.730: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1474009.730: DIMM 0 RttNom: 4
1474109.730: DIMM 1 RttWr: 1
1474209.730: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1474309.730: DIMM 0 RttWr: 1
1474409.730: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1474509.730: <09>Lane 00 scaled delay: 0078
1474609.730: <09>Lane 00 new seed: 0078
1474709.730: <09>Lane 01 scaled delay: 0071
1474809.730: <09>Lane 01 new seed: 0071
1474909.730: <09>Lane 02 scaled delay: 006d
1475009.730: <09>Lane 02 new seed: 006d
1475109.730: <09>Lane 03 scaled delay: 0069
1475209.730: <09>Lane 03 new seed: 0069
1475309.730: <09>Lane 04 scaled delay: 0053
1475409.730: <09>Lane 04 new seed: 0053
1475509.730: <09>Lane 05 scaled delay: 005b
1475609.730: <09>Lane 05 new seed: 005b
1475709.730: <09>Lane 06 scaled delay: 0060
1475809.730: <09>Lane 06 new seed: 0060
1475909.730: <09>Lane 07 scaled delay: 0064
1476009.730: <09>Lane 07 new seed: 0064
1476109.730: <09>Lane 08 scaled delay: 0059
1476209.730: <09>Lane 08 new seed: 0059
1476309.730: <09>Lane 00 nibble 0 raw readback: 003e
1476409.730: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007e
1476509.730: <09>Lane 00 nibble 0 adjusted value (post nibble): 007e
1476609.730: <09>Lane 01 nibble 0 raw readback: 0038
1476709.730: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0078
1476809.730: <09>Lane 01 nibble 0 adjusted value (post nibble): 0078
1476909.730: <09>Lane 02 nibble 0 raw readback: 002f
1477009.730: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006f
1477109.730: <09>Lane 02 nibble 0 adjusted value (post nibble): 006f
1477209.730: <09>Lane 03 nibble 0 raw readback: 002a
1477309.731: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
1477409.731: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
1477509.731: <09>Lane 04 nibble 0 raw readback: 0055
1477609.731: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
1477709.731: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
1477809.731: <09>Lane 05 nibble 0 raw readback: 005e
1477909.731: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
1478009.731: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
1478109.731: <09>Lane 06 nibble 0 raw readback: 0024
1478209.731: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
1478309.731: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
1478409.731: <09>Lane 07 nibble 0 raw readback: 0026
1478509.731: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0066
1478609.731: <09>Lane 07 nibble 0 adjusted value (post nibble): 0066
1478709.731: <09>Lane 08 nibble 0 raw readback: 005a
1478809.731: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005a
1478909.731: <09>Lane 08 nibble 0 adjusted value (post nibble): 005a
1479009.731: AgesaHwWlPhase1: training nibble 1
1479109.731: DIMM 0 RttNom: 4
1479209.731: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1479309.731: DIMM 0 RttWr: 1
1479409.731: DIMM 0 RttWr: 1
1479509.731: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1479609.731: DIMM 0 RttWr: 1
1479709.731: DIMM 0 RttNom: 4
1479809.731: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1479909.731: DIMM 0 RttNom: 4
1480009.731: DIMM 0 RttWr: 1
1480109.731: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1480209.731: DIMM 0 RttWr: 1
1480309.731: DIMM 1 RttNom: 4
1480409.731: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1480509.731: DIMM 0 RttNom: 4
1480609.731: DIMM 1 RttWr: 1
1480709.731: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1480809.731: DIMM 0 RttWr: 1
1480909.731: DIMM 1 RttNom: 4
1481009.731: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1481109.731: DIMM 0 RttNom: 4
1481209.731: DIMM 1 RttWr: 1
1481309.731: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1481409.731: DIMM 0 RttWr: 1
1481509.731: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1481609.731: <09>Lane 00 new seed: 0078
1481709.731: <09>Lane 01 new seed: 0071
1481809.731: <09>Lane 02 new seed: 006d
1481909.731: <09>Lane 03 new seed: 0069
1482009.731: <09>Lane 04 new seed: 0053
1482109.731: <09>Lane 05 new seed: 005b
1482209.731: <09>Lane 06 new seed: 0060
1482309.731: <09>Lane 07 new seed: 0064
1482409.731: <09>Lane 08 new seed: 0059
1482509.731: <09>Lane 00 nibble 1 raw readback: 003d
1482609.731: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007d
1482709.731: <09>Lane 00 nibble 1 adjusted value (post nibble): 007a
1482809.731: <09>Lane 01 nibble 1 raw readback: 0037
1482909.731: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0077
1483009.731: <09>Lane 01 nibble 1 adjusted value (post nibble): 0074
1483109.731: <09>Lane 02 nibble 1 raw readback: 002f
1483209.731: <09>Lane 02 nibble 1 adjusted value (pre nibble): 006f
1483309.731: <09>Lane 02 nibble 1 adjusted value (post nibble): 006e
1483409.731: <09>Lane 03 nibble 1 raw readback: 002b
1483509.731: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006b
1483609.731: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
1483709.731: <09>Lane 04 nibble 1 raw readback: 0055
1483809.731: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0055
1483909.732: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
1484009.731: <09>Lane 05 nibble 1 raw readback: 005e
1484109.732: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005e
1484209.732: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
1484309.732: <09>Lane 06 nibble 1 raw readback: 0023
1484409.732: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0063
1484509.732: <09>Lane 06 nibble 1 adjusted value (post nibble): 0061
1484609.732: <09>Lane 07 nibble 1 raw readback: 0026
1484709.732: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
1484809.732: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
1484909.732: <09>Lane 08 nibble 1 raw readback: 0059
1485009.732: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
1485109.732: <09>Lane 08 nibble 1 adjusted value (post nibble): 0059
1485209.732: <09>original critical gross delay: 0
1485309.732: <09>new critical gross delay: 0
1485409.732: DIMM 0 RttNom: 4
1485509.732: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1485609.732: DIMM 0 RttNom: 4
1485709.732: DIMM 0 RttWr: 1
1485809.732: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1485909.732: DIMM 0 RttWr: 1
1486009.732: DIMM 0 RttNom: 4
1486109.732: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1486209.732: DIMM 0 RttNom: 4
1486309.732: DIMM 0 RttWr: 1
1486409.732: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1486509.732: DIMM 0 RttWr: 1
1486609.732: DIMM 1 RttNom: 4
1486709.732: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1486809.732: DIMM 0 RttNom: 4
1486909.732: DIMM 1 RttWr: 1
1487009.732: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1487109.732: DIMM 0 RttWr: 1
1487209.732: DIMM 1 RttNom: 4
1487309.732: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1487409.732: DIMM 0 RttNom: 4
1487509.732: DIMM 1 RttWr: 1
1487609.732: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1487709.732: DIMM 0 RttWr: 1
1487809.732: AgesaHwWlPhase1: training nibble 0
1487909.732: DIMM 1 RttNom: 4
1488009.732: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1488109.732: DIMM 1 RttWr: 1
1488209.732: DIMM 1 RttWr: 1
1488309.732: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1488409.732: DIMM 1 RttWr: 1
1488509.732: DIMM 1 RttNom: 4
1488609.732: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1488709.732: DIMM 1 RttNom: 4
1488809.732: DIMM 1 RttWr: 1
1488909.732: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1489009.732: DIMM 1 RttWr: 1
1489109.732: DIMM 0 RttNom: 4
1489209.732: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1489309.732: DIMM 1 RttNom: 4
1489409.732: DIMM 0 RttWr: 1
1489509.732: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1489609.732: DIMM 1 RttWr: 1
1489709.732: DIMM 0 RttNom: 4
1489809.732: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1489909.732: DIMM 1 RttNom: 4
1490009.732: DIMM 0 RttWr: 1
1490109.733: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1490209.733: DIMM 1 RttWr: 1
1490309.733: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1490409.733: <09>Lane 00 scaled delay: 0066
1490509.733: <09>Lane 00 new seed: 0066
1490609.733: <09>Lane 01 scaled delay: 0060
1490709.733: <09>Lane 01 new seed: 0060
1490809.733: <09>Lane 02 scaled delay: 005a
1490909.733: <09>Lane 02 new seed: 005a
1491009.733: <09>Lane 03 scaled delay: 0058
1491109.733: <09>Lane 03 new seed: 0058
1491209.733: <09>Lane 04 scaled delay: 0043
1491309.733: <09>Lane 04 new seed: 0043
1491409.733: <09>Lane 05 scaled delay: 004b
1491509.733: <09>Lane 05 new seed: 004b
1491609.733: <09>Lane 06 scaled delay: 004f
1491709.733: <09>Lane 06 new seed: 004f
1491809.733: <09>Lane 07 scaled delay: 0054
1491909.733: <09>Lane 07 new seed: 0054
1492009.733: <09>Lane 08 scaled delay: 0048
1492109.733: <09>Lane 08 new seed: 0048
1492209.733: <09>Lane 00 nibble 0 raw readback: 002e
1492309.733: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
1492409.733: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
1492509.733: <09>Lane 01 nibble 0 raw readback: 0026
1492609.733: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
1492709.733: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
1492809.733: <09>Lane 02 nibble 0 raw readback: 005f
1492909.733: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
1493009.733: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
1493109.733: <09>Lane 03 nibble 0 raw readback: 0059
1493209.733: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
1493309.733: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
1493409.733: <09>Lane 04 nibble 0 raw readback: 0044
1493509.733: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
1493609.733: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
1493709.733: <09>Lane 05 nibble 0 raw readback: 004d
1493809.733: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004d
1493909.733: <09>Lane 05 nibble 0 adjusted value (post nibble): 004d
1494009.733: <09>Lane 06 nibble 0 raw readback: 0051
1494109.733: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
1494209.733: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
1494309.733: <09>Lane 07 nibble 0 raw readback: 0058
1494409.733: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
1494509.733: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
1494609.733: <09>Lane 08 nibble 0 raw readback: 004a
1494709.733: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
1494809.733: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
1494909.733: AgesaHwWlPhase1: training nibble 1
1495009.733: DIMM 1 RttNom: 4
1495109.733: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1495209.733: DIMM 1 RttWr: 1
1495309.733: DIMM 1 RttWr: 1
1495409.733: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1495509.733: DIMM 1 RttWr: 1
1495609.733: DIMM 1 RttNom: 4
1495709.733: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1495809.733: DIMM 1 RttNom: 4
1495909.733: DIMM 1 RttWr: 1
1496009.733: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1496109.733: DIMM 1 RttWr: 1
1496209.733: DIMM 0 RttNom: 4
1496309.733: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1496409.733: DIMM 1 RttNom: 4
1496509.733: DIMM 0 RttWr: 1
1496609.733: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1496709.733: DIMM 1 RttWr: 1
1496809.733: DIMM 0 RttNom: 4
1496909.733: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1497009.733: DIMM 1 RttNom: 4
1497109.733: DIMM 0 RttWr: 1
1497209.733: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1497309.734: DIMM 1 RttWr: 1
1497409.734: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1497509.734: <09>Lane 00 new seed: 0066
1497609.734: <09>Lane 01 new seed: 0060
1497709.734: <09>Lane 02 new seed: 005a
1497809.734: <09>Lane 03 new seed: 0058
1497909.734: <09>Lane 04 new seed: 0043
1498009.734: <09>Lane 05 new seed: 004b
1498109.734: <09>Lane 06 new seed: 004f
1498209.734: <09>Lane 07 new seed: 0054
1498309.734: <09>Lane 08 new seed: 0048
1498409.734: <09>Lane 00 nibble 1 raw readback: 002c
1498509.734: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
1498609.734: <09>Lane 00 nibble 1 adjusted value (post nibble): 0069
1498709.734: <09>Lane 01 nibble 1 raw readback: 0025
1498809.734: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
1498909.734: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
1499009.734: <09>Lane 02 nibble 1 raw readback: 005e
1499109.734: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
1499209.734: <09>Lane 02 nibble 1 adjusted value (post nibble): 005c
1499309.734: <09>Lane 03 nibble 1 raw readback: 005a
1499409.734: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005a
1499509.734: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
1499609.734: <09>Lane 04 nibble 1 raw readback: 0046
1499709.734: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
1499809.734: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
1499909.734: <09>Lane 05 nibble 1 raw readback: 004d
1500009.734: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004d
1500109.734: <09>Lane 05 nibble 1 adjusted value (post nibble): 004c
1500209.734: <09>Lane 06 nibble 1 raw readback: 0052
1500309.734: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0052
1500409.734: <09>Lane 06 nibble 1 adjusted value (post nibble): 0050
1500509.734: <09>Lane 07 nibble 1 raw readback: 0057
1500609.734: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
1500709.734: <09>Lane 07 nibble 1 adjusted value (post nibble): 0055
1500809.734: <09>Lane 08 nibble 1 raw readback: 004a
1500909.734: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
1501009.734: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
1501109.734: <09>original critical gross delay: 0
1501209.734: <09>new critical gross delay: 0
1501309.734: DIMM 1 RttNom: 4
1501409.734: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1501509.734: DIMM 1 RttNom: 4
1501609.734: DIMM 1 RttWr: 1
1501709.734: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1501809.734: DIMM 1 RttWr: 1
1501909.734: DIMM 1 RttNom: 4
1502009.734: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1502109.734: DIMM 1 RttNom: 4
1502209.734: DIMM 1 RttWr: 1
1502309.734: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1502409.734: DIMM 1 RttWr: 1
1502509.734: DIMM 0 RttNom: 4
1502609.734: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1502709.734: DIMM 1 RttNom: 4
1502809.734: DIMM 0 RttWr: 1
1502909.734: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1503009.734: DIMM 1 RttWr: 1
1503109.734: DIMM 0 RttNom: 4
1503209.734: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1503309.734: DIMM 1 RttNom: 4
1503409.734: DIMM 0 RttWr: 1
1503509.734: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1503609.734: DIMM 1 RttWr: 1
1503709.735: activate_spd_rom() for node 03
1503809.735: enable_spd_node3()
1503909.735: SetTargetFreq: Start
1504009.735: SetTargetFreq: Node 3: New frequency code: 0006
1504109.735: ChangeMemClk: Start
1504209.735: set_2t_configuration: Start
1504309.735: set_2t_configuration: Done
1504409.735: mct_BeforePlatformSpec: Start
1504509.735: mct_BeforePlatformSpec: Done
1504609.735: mct_PlatformSpec: Start
1504709.735: Programmed DCT 0 timing/termination pattern 00000000 20222222
1504809.735: mct_PlatformSpec: Done
1504909.735: set_2t_configuration: Start
1505009.735: set_2t_configuration: Done
1505109.735: mct_BeforePlatformSpec: Start
1505209.735: mct_BeforePlatformSpec: Done
1505309.735: mct_PlatformSpec: Start
1505409.735: Programmed DCT 1 timing/termination pattern 00000000 20222222
1505509.735: mct_PlatformSpec: Done
1505609.735: ChangeMemClk: Done
1505709.735: phyAssistedMemFnceTraining: Start
1505809.735: phyAssistedMemFnceTraining: training node 3 DCT 0
1505909.736: phyAssistedMemFnceTraining: done training node 3 DCT 0
1506009.736: phyAssistedMemFnceTraining: training node 3 DCT 1
1506109.736: phyAssistedMemFnceTraining: done training node 3 DCT 1
1506209.736: phyAssistedMemFnceTraining: Done
1506309.736: InitPhyCompensation: DCT 0: Start
1506409.736: Waiting for predriver calibration to be applied...done!
1506509.736: InitPhyCompensation: DCT 0: Done
1506609.736: phyAssistedMemFnceTraining: Start
1506709.736: phyAssistedMemFnceTraining: training node 3 DCT 0
1506809.736: phyAssistedMemFnceTraining: done training node 3 DCT 0
1506909.736: phyAssistedMemFnceTraining: training node 3 DCT 1
1507009.736: phyAssistedMemFnceTraining: done training node 3 DCT 1
1507109.736: phyAssistedMemFnceTraining: Done
1507209.736: InitPhyCompensation: DCT 1: Start
1507309.736: Waiting for predriver calibration to be applied...done!
1507409.736: InitPhyCompensation: DCT 1: Done
1507509.736: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
1507609.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1507709.737: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1507809.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1507909.737: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1508009.737: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
1508109.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1508209.737: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1508309.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1508409.737: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1508509.737: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
1508609.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1508709.737: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1508809.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1508909.737: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1509009.737: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
1509109.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1509209.737: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1509309.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1509409.737: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1509509.737: SetTargetFreq: Done
1509609.737: SPD2ndTiming: Start
1509709.737: SPD2ndTiming: Done
1509809.737: mct_BeforeDramInit_Prod_D: Start
1509909.737: mct_ProgramODT_D: Start
1510009.737: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1510109.737: mct_ProgramODT_D: Done
1510209.738: mct_BeforeDramInit_Prod_D: Done
1510309.738: mct_DramInit_Sw_D: Start
1510409.738: DIMM 0 RttWr: 2
1510509.738: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1510609.738: mct_SendMrsCmd: Start
1510709.738: mct_SendMrsCmd: Done
1510809.738: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1510909.738: mct_SendMrsCmd: Start
1511009.738: mct_SendMrsCmd: Done
1511109.738: DIMM 0 RttNom: 3
1511209.738: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1511309.738: mct_SendMrsCmd: Start
1511409.738: mct_SendMrsCmd: Done
1511509.738: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
1511609.738: mct_SendMrsCmd: Start
1511709.738: mct_SendMrsCmd: Done
1511809.738: DIMM 0 RttWr: 2
1511909.738: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1512009.738: mct_SendMrsCmd: Start
1512109.738: mct_SendMrsCmd: Done
1512209.738: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1512309.738: mct_SendMrsCmd: Start
1512409.738: mct_SendMrsCmd: Done
1512509.738: DIMM 0 RttNom: 3
1512609.738: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1512709.738: mct_SendMrsCmd: Start
1512809.738: mct_SendMrsCmd: Done
1512909.738: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
1513009.738: mct_SendMrsCmd: Start
1513109.738: mct_SendMrsCmd: Done
1513209.738: DIMM 1 RttWr: 2
1513309.738: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1513409.738: mct_SendMrsCmd: Start
1513509.738: mct_SendMrsCmd: Done
1513609.738: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1513709.738: mct_SendMrsCmd: Start
1513809.738: mct_SendMrsCmd: Done
1513909.738: DIMM 1 RttNom: 3
1514009.738: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1514109.738: mct_SendMrsCmd: Start
1514209.738: mct_SendMrsCmd: Done
1514309.738: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
1514409.738: mct_SendMrsCmd: Start
1514509.738: mct_SendMrsCmd: Done
1514609.738: DIMM 1 RttWr: 2
1514709.738: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1514809.738: mct_SendMrsCmd: Start
1514909.738: mct_SendMrsCmd: Done
1515009.738: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1515109.738: mct_SendMrsCmd: Start
1515209.738: mct_SendMrsCmd: Done
1515309.738: DIMM 1 RttNom: 3
1515409.738: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1515509.738: mct_SendMrsCmd: Start
1515609.738: mct_SendMrsCmd: Done
1515709.738: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
1515809.738: mct_SendMrsCmd: Start
1515909.738: mct_SendMrsCmd: Done
1516009.738: mct_DramInit_Sw_D: Done
1516109.739: AgesaHwWlPhase1: training nibble 0
1516209.739: DIMM 0 RttNom: 3
1516309.739: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1516409.739: DIMM 0 RttWr: 2
1516509.739: DIMM 0 RttWr: 2
1516609.739: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1516709.739: DIMM 0 RttWr: 2
1516809.739: DIMM 0 RttNom: 3
1516909.739: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1517009.739: DIMM 0 RttNom: 3
1517109.739: DIMM 0 RttWr: 2
1517209.739: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1517309.739: DIMM 0 RttWr: 2
1517409.739: DIMM 1 RttNom: 3
1517509.739: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1517609.739: DIMM 0 RttNom: 3
1517709.739: DIMM 1 RttWr: 2
1517809.739: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1517909.739: DIMM 0 RttWr: 2
1518009.739: DIMM 1 RttNom: 3
1518109.739: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1518209.739: DIMM 0 RttNom: 3
1518309.739: DIMM 1 RttWr: 2
1518409.739: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1518509.739: DIMM 0 RttWr: 2
1518609.739: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1518709.739: <09>Lane 00 scaled delay: 0047
1518809.739: <09>Lane 00 new seed: 0047
1518909.739: <09>Lane 01 scaled delay: 0047
1519009.739: <09>Lane 01 new seed: 0047
1519109.739: <09>Lane 02 scaled delay: 0047
1519209.739: <09>Lane 02 new seed: 0047
1519309.739: <09>Lane 03 scaled delay: 0047
1519409.739: <09>Lane 03 new seed: 0047
1519509.739: <09>Lane 04 scaled delay: 0047
1519609.739: <09>Lane 04 new seed: 0047
1519709.739: <09>Lane 05 scaled delay: 0047
1519809.739: <09>Lane 05 new seed: 0047
1519909.739: <09>Lane 06 scaled delay: 0047
1520009.739: <09>Lane 06 new seed: 0047
1520109.739: <09>Lane 07 scaled delay: 0047
1520209.739: <09>Lane 07 new seed: 0047
1520309.739: <09>Lane 08 scaled delay: 0047
1520409.739: <09>Lane 08 new seed: 0047
1520509.740: <09>Lane 00 nibble 0 raw readback: 0046
1520609.740: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
1520709.740: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
1520809.740: <09>Lane 01 nibble 0 raw readback: 003f
1520909.740: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
1521009.740: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
1521109.740: <09>Lane 02 nibble 0 raw readback: 003c
1521209.740: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
1521309.740: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
1521409.740: <09>Lane 03 nibble 0 raw readback: 003e
1521509.740: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003e
1521609.740: <09>Lane 03 nibble 0 adjusted value (post nibble): 003e
1521709.740: <09>Lane 04 nibble 0 raw readback: 003a
1521809.740: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
1521909.740: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
1522009.740: <09>Lane 05 nibble 0 raw readback: 003e
1522109.740: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
1522209.740: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
1522309.740: <09>Lane 06 nibble 0 raw readback: 003f
1522409.740: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
1522509.740: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
1522609.740: <09>Lane 07 nibble 0 raw readback: 0043
1522709.740: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
1522809.740: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
1522909.740: <09>Lane 08 nibble 0 raw readback: 0037
1523009.740: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
1523109.740: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
1523209.740: AgesaHwWlPhase1: training nibble 1
1523309.740: DIMM 0 RttNom: 3
1523409.740: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1523509.740: DIMM 0 RttWr: 2
1523609.740: DIMM 0 RttWr: 2
1523709.740: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1523809.740: DIMM 0 RttWr: 2
1523909.740: DIMM 0 RttNom: 3
1524009.740: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1524109.740: DIMM 0 RttNom: 3
1524209.740: DIMM 0 RttWr: 2
1524309.740: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1524409.740: DIMM 0 RttWr: 2
1524509.740: DIMM 1 RttNom: 3
1524609.740: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1524709.740: DIMM 0 RttNom: 3
1524809.740: DIMM 1 RttWr: 2
1524909.740: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1525009.740: DIMM 0 RttWr: 2
1525109.740: DIMM 1 RttNom: 3
1525209.740: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1525309.740: DIMM 0 RttNom: 3
1525409.740: DIMM 1 RttWr: 2
1525509.740: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1525609.740: DIMM 0 RttWr: 2
1525709.740: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1525809.740: <09>Lane 00 new seed: 0047
1525909.740: <09>Lane 01 new seed: 0047
1526009.740: <09>Lane 02 new seed: 0047
1526109.740: <09>Lane 03 new seed: 0047
1526209.740: <09>Lane 04 new seed: 0047
1526309.740: <09>Lane 05 new seed: 0047
1526409.740: <09>Lane 06 new seed: 0047
1526509.740: <09>Lane 07 new seed: 0047
1526609.740: <09>Lane 08 new seed: 0047
1526709.741: <09>Lane 00 nibble 1 raw readback: 0047
1526809.741: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
1526909.741: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
1527009.741: <09>Lane 01 nibble 1 raw readback: 0042
1527109.741: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
1527209.741: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
1527309.741: <09>Lane 02 nibble 1 raw readback: 003f
1527409.741: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
1527509.741: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
1527609.741: <09>Lane 03 nibble 1 raw readback: 003c
1527709.741: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
1527809.741: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
1527909.741: <09>Lane 04 nibble 1 raw readback: 003a
1528009.741: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
1528109.741: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
1528209.741: <09>Lane 05 nibble 1 raw readback: 003d
1528309.741: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
1528409.741: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
1528509.741: <09>Lane 06 nibble 1 raw readback: 0041
1528609.741: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
1528709.741: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
1528809.741: <09>Lane 07 nibble 1 raw readback: 0045
1528909.741: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
1529009.741: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
1529109.741: <09>Lane 08 nibble 1 raw readback: 0038
1529209.741: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
1529309.741: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
1529409.741: <09>original critical gross delay: 0
1529509.741: <09>new critical gross delay: 0
1529609.741: DIMM 0 RttNom: 3
1529709.741: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1529809.741: DIMM 0 RttNom: 3
1529909.741: DIMM 0 RttWr: 2
1530009.741: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1530109.741: DIMM 0 RttWr: 2
1530209.741: DIMM 0 RttNom: 3
1530309.741: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1530409.741: DIMM 0 RttNom: 3
1530509.741: DIMM 0 RttWr: 2
1530609.741: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1530709.741: DIMM 0 RttWr: 2
1530809.741: DIMM 1 RttNom: 3
1530909.741: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1531009.741: DIMM 0 RttNom: 3
1531109.741: DIMM 1 RttWr: 2
1531209.741: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1531309.741: DIMM 0 RttWr: 2
1531409.741: DIMM 1 RttNom: 3
1531509.741: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1531609.741: DIMM 0 RttNom: 3
1531709.741: DIMM 1 RttWr: 2
1531809.741: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1531909.741: DIMM 0 RttWr: 2
1532009.741: AgesaHwWlPhase1: training nibble 0
1532109.741: DIMM 1 RttNom: 3
1532209.741: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1532309.741: DIMM 1 RttWr: 2
1532409.741: DIMM 1 RttWr: 2
1532509.741: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1532609.741: DIMM 1 RttWr: 2
1532709.741: DIMM 1 RttNom: 3
1532809.741: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1532909.741: DIMM 1 RttNom: 3
1533009.742: DIMM 1 RttWr: 2
1533109.742: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1533209.742: DIMM 1 RttWr: 2
1533309.742: DIMM 0 RttNom: 3
1533409.742: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1533509.742: DIMM 1 RttNom: 3
1533609.742: DIMM 0 RttWr: 2
1533709.742: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1533809.742: DIMM 1 RttWr: 2
1533909.742: DIMM 0 RttNom: 3
1534009.742: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1534109.742: DIMM 1 RttNom: 3
1534209.742: DIMM 0 RttWr: 2
1534309.742: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1534409.742: DIMM 1 RttWr: 2
1534509.742: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1534609.742: <09>Lane 00 scaled delay: 0047
1534709.742: <09>Lane 00 new seed: 0047
1534809.742: <09>Lane 01 scaled delay: 0047
1534909.742: <09>Lane 01 new seed: 0047
1535009.742: <09>Lane 02 scaled delay: 0047
1535109.742: <09>Lane 02 new seed: 0047
1535209.742: <09>Lane 03 scaled delay: 0047
1535309.742: <09>Lane 03 new seed: 0047
1535409.742: <09>Lane 04 scaled delay: 0047
1535509.742: <09>Lane 04 new seed: 0047
1535609.742: <09>Lane 05 scaled delay: 0047
1535709.742: <09>Lane 05 new seed: 0047
1535809.742: <09>Lane 06 scaled delay: 0047
1535909.742: <09>Lane 06 new seed: 0047
1536009.742: <09>Lane 07 scaled delay: 0047
1536109.742: <09>Lane 07 new seed: 0047
1536209.742: <09>Lane 08 scaled delay: 0047
1536309.742: <09>Lane 08 new seed: 0047
1536409.742: <09>Lane 00 nibble 0 raw readback: 0044
1536509.742: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
1536609.742: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
1536709.742: <09>Lane 01 nibble 0 raw readback: 0040
1536809.742: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
1536909.742: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
1537009.742: <09>Lane 02 nibble 0 raw readback: 003c
1537109.742: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
1537209.742: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
1537309.742: <09>Lane 03 nibble 0 raw readback: 003c
1537409.742: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003c
1537509.742: <09>Lane 03 nibble 0 adjusted value (post nibble): 003c
1537609.742: <09>Lane 04 nibble 0 raw readback: 0039
1537709.742: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
1537809.742: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
1537909.742: <09>Lane 05 nibble 0 raw readback: 003c
1538009.742: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
1538109.742: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
1538209.742: <09>Lane 06 nibble 0 raw readback: 003e
1538309.742: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
1538409.742: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
1538509.742: <09>Lane 07 nibble 0 raw readback: 0042
1538609.742: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
1538709.742: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
1538809.742: <09>Lane 08 nibble 0 raw readback: 0036
1538909.742: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
1539009.742: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
1539109.742: AgesaHwWlPhase1: training nibble 1
1539209.742: DIMM 1 RttNom: 3
1539309.742: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1539409.742: DIMM 1 RttWr: 2
1539509.742: DIMM 1 RttWr: 2
1539609.742: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1539709.742: DIMM 1 RttWr: 2
1539809.742: DIMM 1 RttNom: 3
1539909.742: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1540009.742: DIMM 1 RttNom: 3
1540109.742: DIMM 1 RttWr: 2
1540209.742: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1540309.742: DIMM 1 RttWr: 2
1540409.743: DIMM 0 RttNom: 3
1540509.743: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1540609.743: DIMM 1 RttNom: 3
1540709.743: DIMM 0 RttWr: 2
1540809.743: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1540909.743: DIMM 1 RttWr: 2
1541009.743: DIMM 0 RttNom: 3
1541109.743: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1541209.743: DIMM 1 RttNom: 3
1541309.743: DIMM 0 RttWr: 2
1541409.743: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1541509.743: DIMM 1 RttWr: 2
1541609.743: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1541709.743: <09>Lane 00 new seed: 0047
1541809.743: <09>Lane 01 new seed: 0047
1541909.743: <09>Lane 02 new seed: 0047
1542009.743: <09>Lane 03 new seed: 0047
1542109.743: <09>Lane 04 new seed: 0047
1542209.743: <09>Lane 05 new seed: 0047
1542309.743: <09>Lane 06 new seed: 0047
1542409.743: <09>Lane 07 new seed: 0047
1542509.743: <09>Lane 08 new seed: 0047
1542609.743: <09>Lane 00 nibble 1 raw readback: 0045
1542709.743: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
1542809.743: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
1542909.743: <09>Lane 01 nibble 1 raw readback: 0040
1543009.743: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
1543109.743: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
1543209.743: <09>Lane 02 nibble 1 raw readback: 003d
1543309.743: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
1543409.743: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
1543509.743: <09>Lane 03 nibble 1 raw readback: 003c
1543609.743: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
1543709.743: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
1543809.743: <09>Lane 04 nibble 1 raw readback: 0038
1543909.743: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
1544009.743: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
1544109.743: <09>Lane 05 nibble 1 raw readback: 003c
1544209.743: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
1544309.743: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
1544409.743: <09>Lane 06 nibble 1 raw readback: 003d
1544509.743: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
1544609.743: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
1544709.743: <09>Lane 07 nibble 1 raw readback: 0042
1544809.743: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
1544909.743: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
1545009.743: <09>Lane 08 nibble 1 raw readback: 0036
1545109.743: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
1545209.743: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
1545309.743: <09>original critical gross delay: 0
1545409.743: <09>new critical gross delay: 0
1545509.743: DIMM 1 RttNom: 3
1545609.743: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1545709.743: DIMM 1 RttNom: 3
1545809.743: DIMM 1 RttWr: 2
1545909.743: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
1546009.743: DIMM 1 RttWr: 2
1546109.743: DIMM 1 RttNom: 3
1546209.743: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1546309.743: DIMM 1 RttNom: 3
1546409.743: DIMM 1 RttWr: 2
1546509.743: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
1546609.744: DIMM 1 RttWr: 2
1546709.744: DIMM 0 RttNom: 3
1546809.744: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1546909.744: DIMM 1 RttNom: 3
1547009.744: DIMM 0 RttWr: 2
1547109.744: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
1547209.744: DIMM 1 RttWr: 2
1547309.744: DIMM 0 RttNom: 3
1547409.744: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1547509.744: DIMM 1 RttNom: 3
1547609.744: DIMM 0 RttWr: 2
1547709.744: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
1547809.744: DIMM 1 RttWr: 2
1547909.744: SPD2ndTiming: Start
1548009.744: SPD2ndTiming: Done
1548109.744: mct_BeforeDramInit_Prod_D: Start
1548209.744: mct_ProgramODT_D: Start
1548309.744: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1548409.744: mct_ProgramODT_D: Done
1548509.744: mct_BeforeDramInit_Prod_D: Done
1548609.744: mct_DramInit_Sw_D: Start
1548709.744: DIMM 0 RttWr: 2
1548809.744: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1548909.744: mct_SendMrsCmd: Start
1549009.744: mct_SendMrsCmd: Done
1549109.744: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1549209.744: mct_SendMrsCmd: Start
1549309.744: mct_SendMrsCmd: Done
1549409.744: DIMM 0 RttNom: 3
1549509.744: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1549609.744: mct_SendMrsCmd: Start
1549709.745: mct_SendMrsCmd: Done
1549809.745: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
1549909.744: mct_SendMrsCmd: Start
1550009.745: mct_SendMrsCmd: Done
1550109.745: DIMM 0 RttWr: 2
1550209.745: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1550309.745: mct_SendMrsCmd: Start
1550409.745: mct_SendMrsCmd: Done
1550509.745: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1550609.745: mct_SendMrsCmd: Start
1550709.745: mct_SendMrsCmd: Done
1550809.745: DIMM 0 RttNom: 3
1550909.745: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1551009.745: mct_SendMrsCmd: Start
1551109.745: mct_SendMrsCmd: Done
1551209.745: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
1551309.745: mct_SendMrsCmd: Start
1551409.745: mct_SendMrsCmd: Done
1551509.745: DIMM 1 RttWr: 2
1551609.745: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1551709.745: mct_SendMrsCmd: Start
1551809.745: mct_SendMrsCmd: Done
1551909.745: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1552009.745: mct_SendMrsCmd: Start
1552109.745: mct_SendMrsCmd: Done
1552209.745: DIMM 1 RttNom: 3
1552309.745: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1552409.745: mct_SendMrsCmd: Start
1552509.745: mct_SendMrsCmd: Done
1552609.745: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
1552709.745: mct_SendMrsCmd: Start
1552809.745: mct_SendMrsCmd: Done
1552909.745: DIMM 1 RttWr: 2
1553009.745: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1553109.745: mct_SendMrsCmd: Start
1553209.745: mct_SendMrsCmd: Done
1553309.745: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1553409.745: mct_SendMrsCmd: Start
1553509.745: mct_SendMrsCmd: Done
1553609.745: DIMM 1 RttNom: 3
1553709.745: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1553809.745: mct_SendMrsCmd: Start
1553909.745: mct_SendMrsCmd: Done
1554009.745: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
1554109.745: mct_SendMrsCmd: Start
1554209.745: mct_SendMrsCmd: Done
1554309.745: mct_DramInit_Sw_D: Done
1554409.745: AgesaHwWlPhase1: training nibble 0
1554509.745: DIMM 0 RttNom: 3
1554609.745: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1554709.745: DIMM 0 RttWr: 2
1554809.745: DIMM 0 RttWr: 2
1554909.745: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1555009.745: DIMM 0 RttWr: 2
1555109.745: DIMM 0 RttNom: 3
1555209.745: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1555309.745: DIMM 0 RttNom: 3
1555409.745: DIMM 0 RttWr: 2
1555509.745: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1555609.745: DIMM 0 RttWr: 2
1555709.745: DIMM 1 RttNom: 3
1555809.745: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1555909.745: DIMM 0 RttNom: 3
1556009.745: DIMM 1 RttWr: 2
1556109.745: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1556209.745: DIMM 0 RttWr: 2
1556309.745: DIMM 1 RttNom: 3
1556409.745: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1556509.745: DIMM 0 RttNom: 3
1556609.745: DIMM 1 RttWr: 2
1556709.745: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1556809.745: DIMM 0 RttWr: 2
1556909.746: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1557009.746: <09>Lane 00 scaled delay: 0047
1557109.746: <09>Lane 00 new seed: 0047
1557209.746: <09>Lane 01 scaled delay: 0047
1557309.746: <09>Lane 01 new seed: 0047
1557409.746: <09>Lane 02 scaled delay: 0047
1557509.746: <09>Lane 02 new seed: 0047
1557609.746: <09>Lane 03 scaled delay: 0047
1557709.746: <09>Lane 03 new seed: 0047
1557809.746: <09>Lane 04 scaled delay: 0047
1557909.746: <09>Lane 04 new seed: 0047
1558009.746: <09>Lane 05 scaled delay: 0047
1558109.746: <09>Lane 05 new seed: 0047
1558209.746: <09>Lane 06 scaled delay: 0047
1558309.746: <09>Lane 06 new seed: 0047
1558409.746: <09>Lane 07 scaled delay: 0047
1558509.746: <09>Lane 07 new seed: 0047
1558609.746: <09>Lane 08 scaled delay: 0047
1558709.746: <09>Lane 08 new seed: 0047
1558809.746: <09>Lane 00 nibble 0 raw readback: 0046
1558909.746: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
1559009.746: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
1559109.746: <09>Lane 01 nibble 0 raw readback: 0042
1559209.746: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
1559309.746: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
1559409.746: <09>Lane 02 nibble 0 raw readback: 003e
1559509.746: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
1559609.746: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
1559709.746: <09>Lane 03 nibble 0 raw readback: 003b
1559809.746: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
1559909.746: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
1560009.746: <09>Lane 04 nibble 0 raw readback: 003a
1560109.746: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
1560209.746: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
1560309.746: <09>Lane 05 nibble 0 raw readback: 003e
1560409.746: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
1560509.746: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
1560609.746: <09>Lane 06 nibble 0 raw readback: 0041
1560709.746: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
1560809.746: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
1560909.746: <09>Lane 07 nibble 0 raw readback: 0045
1561009.746: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
1561109.746: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
1561209.746: <09>Lane 08 nibble 0 raw readback: 0037
1561309.746: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
1561409.746: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
1561509.746: AgesaHwWlPhase1: training nibble 1
1561609.746: DIMM 0 RttNom: 3
1561709.746: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1561809.746: DIMM 0 RttWr: 2
1561909.746: DIMM 0 RttWr: 2
1562009.746: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1562109.746: DIMM 0 RttWr: 2
1562209.746: DIMM 0 RttNom: 3
1562309.746: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1562409.746: DIMM 0 RttNom: 3
1562509.746: DIMM 0 RttWr: 2
1562609.746: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1562709.746: DIMM 0 RttWr: 2
1562809.746: DIMM 1 RttNom: 3
1562909.746: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1563009.746: DIMM 0 RttNom: 3
1563109.746: DIMM 1 RttWr: 2
1563209.746: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1563309.747: DIMM 0 RttWr: 2
1563409.747: DIMM 1 RttNom: 3
1563509.747: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1563609.747: DIMM 0 RttNom: 3
1563709.747: DIMM 1 RttWr: 2
1563809.747: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1563909.747: DIMM 0 RttWr: 2
1564009.747: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1564109.747: <09>Lane 00 new seed: 0047
1564209.747: <09>Lane 01 new seed: 0047
1564309.747: <09>Lane 02 new seed: 0047
1564409.747: <09>Lane 03 new seed: 0047
1564509.747: <09>Lane 04 new seed: 0047
1564609.747: <09>Lane 05 new seed: 0047
1564709.747: <09>Lane 06 new seed: 0047
1564809.747: <09>Lane 07 new seed: 0047
1564909.747: <09>Lane 08 new seed: 0047
1565009.747: <09>Lane 00 nibble 1 raw readback: 0047
1565109.747: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
1565209.747: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
1565309.747: <09>Lane 01 nibble 1 raw readback: 0044
1565409.747: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
1565509.747: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
1565609.747: <09>Lane 02 nibble 1 raw readback: 0040
1565709.747: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
1565809.747: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
1565909.747: <09>Lane 03 nibble 1 raw readback: 003c
1566009.747: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
1566109.747: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
1566209.747: <09>Lane 04 nibble 1 raw readback: 003a
1566309.747: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
1566409.747: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
1566509.747: <09>Lane 05 nibble 1 raw readback: 003d
1566609.747: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
1566709.747: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
1566809.747: <09>Lane 06 nibble 1 raw readback: 0041
1566909.747: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
1567009.747: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
1567109.747: <09>Lane 07 nibble 1 raw readback: 0046
1567209.747: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
1567309.747: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
1567409.747: <09>Lane 08 nibble 1 raw readback: 0038
1567509.747: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
1567609.747: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
1567709.747: <09>original critical gross delay: 0
1567809.747: <09>new critical gross delay: 0
1567909.747: DIMM 0 RttNom: 3
1568009.747: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1568109.747: DIMM 0 RttNom: 3
1568209.747: DIMM 0 RttWr: 2
1568309.747: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1568409.747: DIMM 0 RttWr: 2
1568509.747: DIMM 0 RttNom: 3
1568609.747: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1568709.747: DIMM 0 RttNom: 3
1568809.747: DIMM 0 RttWr: 2
1568909.747: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1569009.747: DIMM 0 RttWr: 2
1569109.748: DIMM 1 RttNom: 3
1569209.747: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1569309.748: DIMM 0 RttNom: 3
1569409.748: DIMM 1 RttWr: 2
1569509.748: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1569609.748: DIMM 0 RttWr: 2
1569709.748: DIMM 1 RttNom: 3
1569809.748: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1569909.748: DIMM 0 RttNom: 3
1570009.748: DIMM 1 RttWr: 2
1570109.748: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1570209.748: DIMM 0 RttWr: 2
1570309.748: AgesaHwWlPhase1: training nibble 0
1570409.748: DIMM 1 RttNom: 3
1570509.748: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1570609.748: DIMM 1 RttWr: 2
1570709.748: DIMM 1 RttWr: 2
1570809.748: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1570909.748: DIMM 1 RttWr: 2
1571009.748: DIMM 1 RttNom: 3
1571109.748: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1571209.748: DIMM 1 RttNom: 3
1571309.748: DIMM 1 RttWr: 2
1571409.748: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1571509.748: DIMM 1 RttWr: 2
1571609.748: DIMM 0 RttNom: 3
1571709.748: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1571809.748: DIMM 1 RttNom: 3
1571909.748: DIMM 0 RttWr: 2
1572009.748: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1572109.748: DIMM 1 RttWr: 2
1572209.748: DIMM 0 RttNom: 3
1572309.748: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1572409.748: DIMM 1 RttNom: 3
1572509.748: DIMM 0 RttWr: 2
1572609.748: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1572709.748: DIMM 1 RttWr: 2
1572809.748: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1572909.748: <09>Lane 00 scaled delay: 0047
1573009.748: <09>Lane 00 new seed: 0047
1573109.748: <09>Lane 01 scaled delay: 0047
1573209.748: <09>Lane 01 new seed: 0047
1573309.748: <09>Lane 02 scaled delay: 0047
1573409.748: <09>Lane 02 new seed: 0047
1573509.748: <09>Lane 03 scaled delay: 0047
1573609.748: <09>Lane 03 new seed: 0047
1573709.748: <09>Lane 04 scaled delay: 0047
1573809.748: <09>Lane 04 new seed: 0047
1573909.748: <09>Lane 05 scaled delay: 0047
1574009.748: <09>Lane 05 new seed: 0047
1574109.748: <09>Lane 06 scaled delay: 0047
1574209.748: <09>Lane 06 new seed: 0047
1574309.748: <09>Lane 07 scaled delay: 0047
1574409.748: <09>Lane 07 new seed: 0047
1574509.748: <09>Lane 08 scaled delay: 0047
1574609.748: <09>Lane 08 new seed: 0047
1574709.748: <09>Lane 00 nibble 0 raw readback: 0046
1574809.748: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
1574909.748: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
1575009.748: <09>Lane 01 nibble 0 raw readback: 0042
1575109.748: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
1575209.748: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
1575309.748: <09>Lane 02 nibble 0 raw readback: 003d
1575409.748: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
1575509.748: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
1575609.748: <09>Lane 03 nibble 0 raw readback: 003b
1575709.748: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
1575809.748: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
1575909.748: <09>Lane 04 nibble 0 raw readback: 0039
1576009.749: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
1576109.748: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
1576209.749: <09>Lane 05 nibble 0 raw readback: 003e
1576309.749: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
1576409.749: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
1576509.749: <09>Lane 06 nibble 0 raw readback: 0041
1576609.749: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
1576709.749: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
1576809.749: <09>Lane 07 nibble 0 raw readback: 0044
1576909.749: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
1577009.749: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
1577109.749: <09>Lane 08 nibble 0 raw readback: 0038
1577209.749: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
1577309.749: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
1577409.749: AgesaHwWlPhase1: training nibble 1
1577509.749: DIMM 1 RttNom: 3
1577609.749: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1577709.749: DIMM 1 RttWr: 2
1577809.749: DIMM 1 RttWr: 2
1577909.749: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1578009.749: DIMM 1 RttWr: 2
1578109.749: DIMM 1 RttNom: 3
1578209.749: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1578309.749: DIMM 1 RttNom: 3
1578409.749: DIMM 1 RttWr: 2
1578509.749: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1578609.749: DIMM 1 RttWr: 2
1578709.749: DIMM 0 RttNom: 3
1578809.749: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1578909.749: DIMM 1 RttNom: 3
1579009.749: DIMM 0 RttWr: 2
1579109.749: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1579209.749: DIMM 1 RttWr: 2
1579309.749: DIMM 0 RttNom: 3
1579409.749: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1579509.749: DIMM 1 RttNom: 3
1579609.749: DIMM 0 RttWr: 2
1579709.749: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1579809.749: DIMM 1 RttWr: 2
1579909.749: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1580009.749: <09>Lane 00 new seed: 0047
1580109.749: <09>Lane 01 new seed: 0047
1580209.749: <09>Lane 02 new seed: 0047
1580309.749: <09>Lane 03 new seed: 0047
1580409.749: <09>Lane 04 new seed: 0047
1580509.749: <09>Lane 05 new seed: 0047
1580609.749: <09>Lane 06 new seed: 0047
1580709.749: <09>Lane 07 new seed: 0047
1580809.749: <09>Lane 08 new seed: 0047
1580909.749: <09>Lane 00 nibble 1 raw readback: 0047
1581009.749: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
1581109.749: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
1581209.749: <09>Lane 01 nibble 1 raw readback: 0044
1581309.749: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
1581409.749: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
1581509.749: <09>Lane 02 nibble 1 raw readback: 003e
1581609.749: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
1581709.749: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
1581809.749: <09>Lane 03 nibble 1 raw readback: 003c
1581909.749: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
1582009.749: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
1582109.749: <09>Lane 04 nibble 1 raw readback: 003a
1582209.749: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
1582309.749: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
1582409.749: <09>Lane 05 nibble 1 raw readback: 003d
1582509.749: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
1582609.749: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
1582709.749: <09>Lane 06 nibble 1 raw readback: 0042
1582809.749: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0042
1582909.749: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
1583009.749: <09>Lane 07 nibble 1 raw readback: 0046
1583109.749: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
1583209.749: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
1583309.749: <09>Lane 08 nibble 1 raw readback: 0037
1583409.749: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
1583509.749: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
1583609.750: <09>original critical gross delay: 0
1583709.750: <09>new critical gross delay: 0
1583809.750: DIMM 1 RttNom: 3
1583909.750: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1584009.750: DIMM 1 RttNom: 3
1584109.750: DIMM 1 RttWr: 2
1584209.750: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
1584309.750: DIMM 1 RttWr: 2
1584409.750: DIMM 1 RttNom: 3
1584509.750: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1584609.750: DIMM 1 RttNom: 3
1584709.750: DIMM 1 RttWr: 2
1584809.750: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
1584909.750: DIMM 1 RttWr: 2
1585009.750: DIMM 0 RttNom: 3
1585109.750: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1585209.750: DIMM 1 RttNom: 3
1585309.750: DIMM 0 RttWr: 2
1585409.750: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
1585509.750: DIMM 1 RttWr: 2
1585609.750: DIMM 0 RttNom: 3
1585709.750: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1585809.750: DIMM 1 RttNom: 3
1585909.750: DIMM 0 RttWr: 2
1586009.750: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
1586109.750: DIMM 1 RttWr: 2
1586209.750: SetTargetFreq: Start
1586309.750: SetTargetFreq: Node 3: New frequency code: 000a
1586409.750: ChangeMemClk: Start
1586509.750: set_2t_configuration: Start
1586609.750: set_2t_configuration: Done
1586709.750: mct_BeforePlatformSpec: Start
1586809.750: mct_BeforePlatformSpec: Done
1586909.750: mct_PlatformSpec: Start
1587009.751: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
1587109.751: mct_PlatformSpec: Done
1587209.751: set_2t_configuration: Start
1587309.751: set_2t_configuration: Done
1587409.751: mct_BeforePlatformSpec: Start
1587509.751: mct_BeforePlatformSpec: Done
1587609.751: mct_PlatformSpec: Start
1587709.751: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
1587809.751: mct_PlatformSpec: Done
1587909.751: ChangeMemClk: Done
1588009.751: phyAssistedMemFnceTraining: Start
1588109.751: phyAssistedMemFnceTraining: training node 3 DCT 0
1588209.751: phyAssistedMemFnceTraining: done training node 3 DCT 0
1588309.751: phyAssistedMemFnceTraining: training node 3 DCT 1
1588409.751: phyAssistedMemFnceTraining: done training node 3 DCT 1
1588509.751: phyAssistedMemFnceTraining: Done
1588609.751: InitPhyCompensation: DCT 0: Start
1588709.751: Waiting for predriver calibration to be applied...done!
1588809.751: InitPhyCompensation: DCT 0: Done
1588909.751: phyAssistedMemFnceTraining: Start
1589009.751: phyAssistedMemFnceTraining: training node 3 DCT 0
1589109.751: phyAssistedMemFnceTraining: done training node 3 DCT 0
1589209.751: phyAssistedMemFnceTraining: training node 3 DCT 1
1589309.751: phyAssistedMemFnceTraining: done training node 3 DCT 1
1589409.751: phyAssistedMemFnceTraining: Done
1589509.751: InitPhyCompensation: DCT 1: Start
1589609.751: Waiting for predriver calibration to be applied...done!
1589709.751: InitPhyCompensation: DCT 1: Done
1589809.752: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
1589909.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1590009.752: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1590109.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1590209.752: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1590309.752: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
1590409.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1590509.752: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1590609.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1590709.752: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1590809.752: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
1590909.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1591009.752: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1591109.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1591209.752: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1591309.752: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
1591409.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1591509.752: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1591609.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1591709.752: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1591809.752: SetTargetFreq: Done
1591909.752: SPD2ndTiming: Start
1592009.752: SPD2ndTiming: Done
1592109.752: mct_BeforeDramInit_Prod_D: Start
1592209.752: mct_ProgramODT_D: Start
1592309.752: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1592409.752: mct_ProgramODT_D: Done
1592509.752: mct_BeforeDramInit_Prod_D: Done
1592609.753: mct_DramInit_Sw_D: Start
1592709.753: DIMM 0 RttWr: 1
1592809.753: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1592909.753: mct_SendMrsCmd: Start
1593009.753: mct_SendMrsCmd: Done
1593109.753: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1593209.753: mct_SendMrsCmd: Start
1593309.753: mct_SendMrsCmd: Done
1593409.753: DIMM 0 RttNom: 3
1593509.753: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1593609.753: mct_SendMrsCmd: Start
1593709.753: mct_SendMrsCmd: Done
1593809.753: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
1593909.753: mct_SendMrsCmd: Start
1594009.753: mct_SendMrsCmd: Done
1594109.753: DIMM 0 RttWr: 1
1594209.753: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1594309.753: mct_SendMrsCmd: Start
1594409.753: mct_SendMrsCmd: Done
1594509.753: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1594609.753: mct_SendMrsCmd: Start
1594709.753: mct_SendMrsCmd: Done
1594809.753: DIMM 0 RttNom: 3
1594909.753: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1595009.753: mct_SendMrsCmd: Start
1595109.753: mct_SendMrsCmd: Done
1595209.753: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
1595309.753: mct_SendMrsCmd: Start
1595409.753: mct_SendMrsCmd: Done
1595509.753: DIMM 1 RttWr: 1
1595609.753: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1595709.753: mct_SendMrsCmd: Start
1595809.753: mct_SendMrsCmd: Done
1595909.753: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1596009.753: mct_SendMrsCmd: Start
1596109.753: mct_SendMrsCmd: Done
1596209.753: DIMM 1 RttNom: 3
1596309.753: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1596409.753: mct_SendMrsCmd: Start
1596509.753: mct_SendMrsCmd: Done
1596609.753: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
1596709.753: mct_SendMrsCmd: Start
1596809.753: mct_SendMrsCmd: Done
1596909.753: DIMM 1 RttWr: 1
1597009.753: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1597109.753: mct_SendMrsCmd: Start
1597209.753: mct_SendMrsCmd: Done
1597309.753: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1597409.753: mct_SendMrsCmd: Start
1597509.753: mct_SendMrsCmd: Done
1597609.753: DIMM 1 RttNom: 3
1597709.753: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1597809.753: mct_SendMrsCmd: Start
1597909.753: mct_SendMrsCmd: Done
1598009.753: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
1598109.753: mct_SendMrsCmd: Start
1598209.753: mct_SendMrsCmd: Done
1598309.753: mct_DramInit_Sw_D: Done
1598409.754: AgesaHwWlPhase1: training nibble 0
1598509.754: DIMM 0 RttNom: 3
1598609.754: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1598709.754: DIMM 0 RttWr: 1
1598809.754: DIMM 0 RttWr: 1
1598909.754: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1599009.754: DIMM 0 RttWr: 1
1599109.754: DIMM 0 RttNom: 3
1599209.754: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1599309.754: DIMM 0 RttNom: 3
1599409.754: DIMM 0 RttWr: 1
1599509.754: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1599609.754: DIMM 0 RttWr: 1
1599709.754: DIMM 1 RttNom: 3
1599809.754: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1599909.754: DIMM 0 RttNom: 3
1600009.754: DIMM 1 RttWr: 1
1600109.754: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1600209.754: DIMM 0 RttWr: 1
1600309.754: DIMM 1 RttNom: 3
1600409.754: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1600509.754: DIMM 0 RttNom: 3
1600609.754: DIMM 1 RttWr: 1
1600709.754: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1600809.754: DIMM 0 RttWr: 1
1600909.754: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1601009.754: <09>Lane 00 scaled delay: 0053
1601109.754: <09>Lane 00 new seed: 0053
1601209.754: <09>Lane 01 scaled delay: 004f
1601309.754: <09>Lane 01 new seed: 004f
1601409.754: <09>Lane 02 scaled delay: 004e
1601509.754: <09>Lane 02 new seed: 004e
1601609.754: <09>Lane 03 scaled delay: 004b
1601709.754: <09>Lane 03 new seed: 004b
1601809.754: <09>Lane 04 scaled delay: 004a
1601909.754: <09>Lane 04 new seed: 004a
1602009.754: <09>Lane 05 scaled delay: 004d
1602109.754: <09>Lane 05 new seed: 004d
1602209.754: <09>Lane 06 scaled delay: 004f
1602309.754: <09>Lane 06 new seed: 004f
1602409.754: <09>Lane 07 scaled delay: 0052
1602509.754: <09>Lane 07 new seed: 0052
1602609.754: <09>Lane 08 scaled delay: 0049
1602709.754: <09>Lane 08 new seed: 0049
1602809.754: <09>Lane 00 nibble 0 raw readback: 0052
1602909.755: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
1603009.755: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
1603109.755: <09>Lane 01 nibble 0 raw readback: 0049
1603209.755: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
1603309.755: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
1603409.755: <09>Lane 02 nibble 0 raw readback: 0047
1603509.755: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
1603609.755: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
1603709.755: <09>Lane 03 nibble 0 raw readback: 0047
1603809.755: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
1603909.755: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
1604009.755: <09>Lane 04 nibble 0 raw readback: 0044
1604109.755: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
1604209.755: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
1604309.755: <09>Lane 05 nibble 0 raw readback: 0049
1604409.755: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
1604509.755: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
1604609.755: <09>Lane 06 nibble 0 raw readback: 004b
1604709.755: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
1604809.755: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
1604909.755: <09>Lane 07 nibble 0 raw readback: 004e
1605009.755: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
1605109.755: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
1605209.755: <09>Lane 08 nibble 0 raw readback: 003e
1605309.755: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
1605409.755: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
1605509.755: AgesaHwWlPhase1: training nibble 1
1605609.755: DIMM 0 RttNom: 3
1605709.755: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1605809.755: DIMM 0 RttWr: 1
1605909.755: DIMM 0 RttWr: 1
1606009.755: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1606109.755: DIMM 0 RttWr: 1
1606209.755: DIMM 0 RttNom: 3
1606309.755: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1606409.755: DIMM 0 RttNom: 3
1606509.755: DIMM 0 RttWr: 1
1606609.755: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1606709.755: DIMM 0 RttWr: 1
1606809.755: DIMM 1 RttNom: 3
1606909.755: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1607009.755: DIMM 0 RttNom: 3
1607109.755: DIMM 1 RttWr: 1
1607209.755: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1607309.755: DIMM 0 RttWr: 1
1607409.755: DIMM 1 RttNom: 3
1607509.755: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1607609.755: DIMM 0 RttNom: 3
1607709.755: DIMM 1 RttWr: 1
1607809.755: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1607909.755: DIMM 0 RttWr: 1
1608009.755: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1608109.755: <09>Lane 00 new seed: 0053
1608209.755: <09>Lane 01 new seed: 004f
1608309.755: <09>Lane 02 new seed: 004e
1608409.755: <09>Lane 03 new seed: 004b
1608509.755: <09>Lane 04 new seed: 004a
1608609.755: <09>Lane 05 new seed: 004d
1608709.755: <09>Lane 06 new seed: 004f
1608809.755: <09>Lane 07 new seed: 0052
1608909.755: <09>Lane 08 new seed: 0049
1609009.755: <09>Lane 00 nibble 1 raw readback: 0054
1609109.755: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
1609209.755: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
1609309.755: <09>Lane 01 nibble 1 raw readback: 004d
1609409.755: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004d
1609509.755: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
1609609.755: <09>Lane 02 nibble 1 raw readback: 0049
1609709.755: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
1609809.755: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
1609909.755: <09>Lane 03 nibble 1 raw readback: 0046
1610009.755: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
1610109.755: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1610209.756: <09>Lane 04 nibble 1 raw readback: 0043
1610309.756: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
1610409.756: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
1610509.756: <09>Lane 05 nibble 1 raw readback: 0048
1610609.756: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
1610709.756: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
1610809.756: <09>Lane 06 nibble 1 raw readback: 004d
1610909.756: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
1611009.756: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
1611109.756: <09>Lane 07 nibble 1 raw readback: 0050
1611209.756: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
1611309.756: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
1611409.756: <09>Lane 08 nibble 1 raw readback: 0040
1611509.756: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
1611609.756: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
1611709.756: <09>original critical gross delay: 0
1611809.756: <09>new critical gross delay: 0
1611909.756: DIMM 0 RttNom: 3
1612009.756: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1612109.756: DIMM 0 RttNom: 3
1612209.756: DIMM 0 RttWr: 1
1612309.756: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1612409.756: DIMM 0 RttWr: 1
1612509.756: DIMM 0 RttNom: 3
1612609.756: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1612709.756: DIMM 0 RttNom: 3
1612809.756: DIMM 0 RttWr: 1
1612909.756: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1613009.756: DIMM 0 RttWr: 1
1613109.756: DIMM 1 RttNom: 3
1613209.756: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1613309.756: DIMM 0 RttNom: 3
1613409.756: DIMM 1 RttWr: 1
1613509.756: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1613609.756: DIMM 0 RttWr: 1
1613709.756: DIMM 1 RttNom: 3
1613809.756: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1613909.756: DIMM 0 RttNom: 3
1614009.756: DIMM 1 RttWr: 1
1614109.756: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1614209.756: DIMM 0 RttWr: 1
1614309.756: AgesaHwWlPhase1: training nibble 0
1614409.756: DIMM 1 RttNom: 3
1614509.756: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1614609.756: DIMM 1 RttWr: 1
1614709.756: DIMM 1 RttWr: 1
1614809.756: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1614909.756: DIMM 1 RttWr: 1
1615009.756: DIMM 1 RttNom: 3
1615109.756: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1615209.756: DIMM 1 RttNom: 3
1615309.756: DIMM 1 RttWr: 1
1615409.756: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1615509.756: DIMM 1 RttWr: 1
1615609.756: DIMM 0 RttNom: 3
1615709.756: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1615809.756: DIMM 1 RttNom: 3
1615909.756: DIMM 0 RttWr: 1
1616009.756: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1616109.756: DIMM 1 RttWr: 1
1616209.756: DIMM 0 RttNom: 3
1616309.757: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1616409.757: DIMM 1 RttNom: 3
1616509.757: DIMM 0 RttWr: 1
1616609.757: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1616709.757: DIMM 1 RttWr: 1
1616809.757: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1616909.757: <09>Lane 00 scaled delay: 0052
1617009.757: <09>Lane 00 new seed: 0052
1617109.757: <09>Lane 01 scaled delay: 004e
1617209.757: <09>Lane 01 new seed: 004e
1617309.757: <09>Lane 02 scaled delay: 004d
1617409.757: <09>Lane 02 new seed: 004d
1617509.757: <09>Lane 03 scaled delay: 004b
1617609.757: <09>Lane 03 new seed: 004b
1617709.757: <09>Lane 04 scaled delay: 0049
1617809.757: <09>Lane 04 new seed: 0049
1617909.757: <09>Lane 05 scaled delay: 004b
1618009.757: <09>Lane 05 new seed: 004b
1618109.757: <09>Lane 06 scaled delay: 004d
1618209.757: <09>Lane 06 new seed: 004d
1618309.757: <09>Lane 07 scaled delay: 004f
1618409.757: <09>Lane 07 new seed: 004f
1618509.757: <09>Lane 08 scaled delay: 0047
1618609.757: <09>Lane 08 new seed: 0047
1618709.757: <09>Lane 00 nibble 0 raw readback: 004f
1618809.757: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004f
1618909.757: <09>Lane 00 nibble 0 adjusted value (post nibble): 004f
1619009.757: <09>Lane 01 nibble 0 raw readback: 004a
1619109.757: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
1619209.757: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
1619309.757: <09>Lane 02 nibble 0 raw readback: 0046
1619409.757: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
1619509.757: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
1619609.757: <09>Lane 03 nibble 0 raw readback: 0044
1619709.757: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
1619809.757: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
1619909.757: <09>Lane 04 nibble 0 raw readback: 0041
1620009.757: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
1620109.757: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
1620209.757: <09>Lane 05 nibble 0 raw readback: 0045
1620309.757: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0045
1620409.757: <09>Lane 05 nibble 0 adjusted value (post nibble): 0045
1620509.757: <09>Lane 06 nibble 0 raw readback: 0047
1620609.757: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0047
1620709.757: <09>Lane 06 nibble 0 adjusted value (post nibble): 0047
1620809.757: <09>Lane 07 nibble 0 raw readback: 004d
1620909.757: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
1621009.757: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
1621109.757: <09>Lane 08 nibble 0 raw readback: 003d
1621209.757: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003d
1621309.757: <09>Lane 08 nibble 0 adjusted value (post nibble): 003d
1621409.757: AgesaHwWlPhase1: training nibble 1
1621509.757: DIMM 1 RttNom: 3
1621609.757: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1621709.757: DIMM 1 RttWr: 1
1621809.757: DIMM 1 RttWr: 1
1621909.757: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1622009.757: DIMM 1 RttWr: 1
1622109.757: DIMM 1 RttNom: 3
1622209.757: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1622309.757: DIMM 1 RttNom: 3
1622409.757: DIMM 1 RttWr: 1
1622509.757: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1622609.757: DIMM 1 RttWr: 1
1622709.757: DIMM 0 RttNom: 3
1622809.757: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1622909.757: DIMM 1 RttNom: 3
1623009.757: DIMM 0 RttWr: 1
1623109.757: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1623209.757: DIMM 1 RttWr: 1
1623309.757: DIMM 0 RttNom: 3
1623409.758: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1623509.758: DIMM 1 RttNom: 3
1623609.758: DIMM 0 RttWr: 1
1623709.758: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1623809.758: DIMM 1 RttWr: 1
1623909.758: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1624009.758: <09>Lane 00 new seed: 0052
1624109.758: <09>Lane 01 new seed: 004e
1624209.758: <09>Lane 02 new seed: 004d
1624309.758: <09>Lane 03 new seed: 004b
1624409.758: <09>Lane 04 new seed: 0049
1624509.758: <09>Lane 05 new seed: 004b
1624609.758: <09>Lane 06 new seed: 004d
1624709.758: <09>Lane 07 new seed: 004f
1624809.758: <09>Lane 08 new seed: 0047
1624909.758: <09>Lane 00 nibble 1 raw readback: 0050
1625009.758: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0050
1625109.758: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
1625209.758: <09>Lane 01 nibble 1 raw readback: 004a
1625309.758: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
1625409.758: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
1625509.758: <09>Lane 02 nibble 1 raw readback: 0046
1625609.758: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
1625709.758: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
1625809.758: <09>Lane 03 nibble 1 raw readback: 0045
1625909.758: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
1626009.758: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1626109.758: <09>Lane 04 nibble 1 raw readback: 0040
1626209.758: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
1626309.758: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
1626409.758: <09>Lane 05 nibble 1 raw readback: 0045
1626509.758: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
1626609.758: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
1626709.758: <09>Lane 06 nibble 1 raw readback: 0046
1626809.758: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
1626909.758: <09>Lane 06 nibble 1 adjusted value (post nibble): 0049
1627009.758: <09>Lane 07 nibble 1 raw readback: 004d
1627109.758: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
1627209.758: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
1627309.758: <09>Lane 08 nibble 1 raw readback: 003d
1627409.758: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
1627509.758: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
1627609.758: <09>original critical gross delay: 0
1627709.758: <09>new critical gross delay: 0
1627809.758: DIMM 1 RttNom: 3
1627909.758: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
1628009.758: DIMM 1 RttNom: 3
1628109.758: DIMM 1 RttWr: 1
1628209.758: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
1628309.758: DIMM 1 RttWr: 1
1628409.758: DIMM 1 RttNom: 3
1628509.758: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
1628609.758: DIMM 1 RttNom: 3
1628709.758: DIMM 1 RttWr: 1
1628809.758: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
1628909.758: DIMM 1 RttWr: 1
1629009.758: DIMM 0 RttNom: 3
1629109.758: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
1629209.758: DIMM 1 RttNom: 3
1629309.758: DIMM 0 RttWr: 1
1629409.758: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
1629509.758: DIMM 1 RttWr: 1
1629609.758: DIMM 0 RttNom: 3
1629709.758: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
1629809.758: DIMM 1 RttNom: 3
1629909.758: DIMM 0 RttWr: 1
1630009.758: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
1630109.759: DIMM 1 RttWr: 1
1630209.759: SPD2ndTiming: Start
1630309.759: SPD2ndTiming: Done
1630409.759: mct_BeforeDramInit_Prod_D: Start
1630509.759: mct_ProgramODT_D: Start
1630609.759: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1630709.759: mct_ProgramODT_D: Done
1630809.759: mct_BeforeDramInit_Prod_D: Done
1630909.759: mct_DramInit_Sw_D: Start
1631009.759: DIMM 0 RttWr: 1
1631109.759: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1631209.759: mct_SendMrsCmd: Start
1631309.759: mct_SendMrsCmd: Done
1631409.759: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1631509.759: mct_SendMrsCmd: Start
1631609.759: mct_SendMrsCmd: Done
1631709.759: DIMM 0 RttNom: 3
1631809.759: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1631909.759: mct_SendMrsCmd: Start
1632009.759: mct_SendMrsCmd: Done
1632109.759: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
1632209.759: mct_SendMrsCmd: Start
1632309.759: mct_SendMrsCmd: Done
1632409.759: DIMM 0 RttWr: 1
1632509.759: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1632609.759: mct_SendMrsCmd: Start
1632709.759: mct_SendMrsCmd: Done
1632809.759: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1632909.759: mct_SendMrsCmd: Start
1633009.759: mct_SendMrsCmd: Done
1633109.759: DIMM 0 RttNom: 3
1633209.759: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1633309.759: mct_SendMrsCmd: Start
1633409.759: mct_SendMrsCmd: Done
1633509.759: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
1633609.759: mct_SendMrsCmd: Start
1633709.759: mct_SendMrsCmd: Done
1633809.759: DIMM 1 RttWr: 1
1633909.759: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1634009.759: mct_SendMrsCmd: Start
1634109.760: mct_SendMrsCmd: Done
1634209.760: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1634309.760: mct_SendMrsCmd: Start
1634409.760: mct_SendMrsCmd: Done
1634509.760: DIMM 1 RttNom: 3
1634609.760: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1634709.760: mct_SendMrsCmd: Start
1634809.760: mct_SendMrsCmd: Done
1634909.760: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
1635009.760: mct_SendMrsCmd: Start
1635109.760: mct_SendMrsCmd: Done
1635209.760: DIMM 1 RttWr: 1
1635309.760: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1635409.760: mct_SendMrsCmd: Start
1635509.760: mct_SendMrsCmd: Done
1635609.760: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1635709.760: mct_SendMrsCmd: Start
1635809.760: mct_SendMrsCmd: Done
1635909.760: DIMM 1 RttNom: 3
1636009.760: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1636109.760: mct_SendMrsCmd: Start
1636209.760: mct_SendMrsCmd: Done
1636309.760: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
1636409.760: mct_SendMrsCmd: Start
1636509.760: mct_SendMrsCmd: Done
1636609.760: mct_DramInit_Sw_D: Done
1636709.760: AgesaHwWlPhase1: training nibble 0
1636809.760: DIMM 0 RttNom: 3
1636909.760: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1637009.760: DIMM 0 RttWr: 1
1637109.760: DIMM 0 RttWr: 1
1637209.760: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1637309.760: DIMM 0 RttWr: 1
1637409.760: DIMM 0 RttNom: 3
1637509.760: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1637609.760: DIMM 0 RttNom: 3
1637709.760: DIMM 0 RttWr: 1
1637809.760: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1637909.760: DIMM 0 RttWr: 1
1638009.760: DIMM 1 RttNom: 3
1638109.760: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1638209.760: DIMM 0 RttNom: 3
1638309.760: DIMM 1 RttWr: 1
1638409.760: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1638509.760: DIMM 0 RttWr: 1
1638609.760: DIMM 1 RttNom: 3
1638709.760: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1638809.760: DIMM 0 RttNom: 3
1638909.760: DIMM 1 RttWr: 1
1639009.760: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1639109.760: DIMM 0 RttWr: 1
1639209.760: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1639309.760: <09>Lane 00 scaled delay: 0053
1639409.760: <09>Lane 00 new seed: 0053
1639509.760: <09>Lane 01 scaled delay: 0051
1639609.760: <09>Lane 01 new seed: 0051
1639709.760: <09>Lane 02 scaled delay: 004e
1639809.760: <09>Lane 02 new seed: 004e
1639909.760: <09>Lane 03 scaled delay: 004b
1640009.760: <09>Lane 03 new seed: 004b
1640109.761: <09>Lane 04 scaled delay: 004a
1640209.760: <09>Lane 04 new seed: 004a
1640309.761: <09>Lane 05 scaled delay: 004d
1640409.761: <09>Lane 05 new seed: 004d
1640509.761: <09>Lane 06 scaled delay: 004f
1640609.761: <09>Lane 06 new seed: 004f
1640709.761: <09>Lane 07 scaled delay: 0052
1640809.761: <09>Lane 07 new seed: 0052
1640909.761: <09>Lane 08 scaled delay: 0049
1641009.761: <09>Lane 08 new seed: 0049
1641109.761: <09>Lane 00 nibble 0 raw readback: 0054
1641209.761: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0054
1641309.761: <09>Lane 00 nibble 0 adjusted value (post nibble): 0054
1641409.761: <09>Lane 01 nibble 0 raw readback: 004e
1641509.761: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
1641609.761: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
1641709.761: <09>Lane 02 nibble 0 raw readback: 004a
1641809.761: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004a
1641909.761: <09>Lane 02 nibble 0 adjusted value (post nibble): 004a
1642009.761: <09>Lane 03 nibble 0 raw readback: 0045
1642109.761: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
1642209.761: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
1642309.761: <09>Lane 04 nibble 0 raw readback: 0044
1642409.761: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
1642509.761: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
1642609.761: <09>Lane 05 nibble 0 raw readback: 004a
1642709.761: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004a
1642809.761: <09>Lane 05 nibble 0 adjusted value (post nibble): 004a
1642909.761: <09>Lane 06 nibble 0 raw readback: 004e
1643009.761: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
1643109.761: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
1643209.761: <09>Lane 07 nibble 0 raw readback: 0053
1643309.761: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0053
1643409.761: <09>Lane 07 nibble 0 adjusted value (post nibble): 0053
1643509.761: <09>Lane 08 nibble 0 raw readback: 0040
1643609.761: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0040
1643709.761: <09>Lane 08 nibble 0 adjusted value (post nibble): 0040
1643809.761: AgesaHwWlPhase1: training nibble 1
1643909.761: DIMM 0 RttNom: 3
1644009.761: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1644109.761: DIMM 0 RttWr: 1
1644209.761: DIMM 0 RttWr: 1
1644309.761: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1644409.761: DIMM 0 RttWr: 1
1644509.761: DIMM 0 RttNom: 3
1644609.761: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1644709.761: DIMM 0 RttNom: 3
1644809.761: DIMM 0 RttWr: 1
1644909.761: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1645009.761: DIMM 0 RttWr: 1
1645109.761: DIMM 1 RttNom: 3
1645209.761: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1645309.761: DIMM 0 RttNom: 3
1645409.761: DIMM 1 RttWr: 1
1645509.761: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1645609.761: DIMM 0 RttWr: 1
1645709.761: DIMM 1 RttNom: 3
1645809.761: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1645909.761: DIMM 0 RttNom: 3
1646009.761: DIMM 1 RttWr: 1
1646109.761: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1646209.761: DIMM 0 RttWr: 1
1646309.761: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1646409.761: <09>Lane 00 new seed: 0053
1646509.761: <09>Lane 01 new seed: 0051
1646609.762: <09>Lane 02 new seed: 004e
1646709.762: <09>Lane 03 new seed: 004b
1646809.762: <09>Lane 04 new seed: 004a
1646909.762: <09>Lane 05 new seed: 004d
1647009.762: <09>Lane 06 new seed: 004f
1647109.762: <09>Lane 07 new seed: 0052
1647209.762: <09>Lane 08 new seed: 0049
1647309.762: <09>Lane 00 nibble 1 raw readback: 0055
1647409.762: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0055
1647509.762: <09>Lane 00 nibble 1 adjusted value (post nibble): 0054
1647609.762: <09>Lane 01 nibble 1 raw readback: 0050
1647709.762: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0050
1647809.762: <09>Lane 01 nibble 1 adjusted value (post nibble): 0050
1647909.762: <09>Lane 02 nibble 1 raw readback: 004c
1648009.762: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004c
1648109.762: <09>Lane 02 nibble 1 adjusted value (post nibble): 004d
1648209.762: <09>Lane 03 nibble 1 raw readback: 0046
1648309.762: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
1648409.762: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1648509.762: <09>Lane 04 nibble 1 raw readback: 0043
1648609.762: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
1648709.762: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
1648809.762: <09>Lane 05 nibble 1 raw readback: 0049
1648909.762: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0049
1649009.762: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
1649109.762: <09>Lane 06 nibble 1 raw readback: 004e
1649209.762: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
1649309.762: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
1649409.762: <09>Lane 07 nibble 1 raw readback: 0053
1649509.762: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0053
1649609.762: <09>Lane 07 nibble 1 adjusted value (post nibble): 0052
1649709.762: <09>Lane 08 nibble 1 raw readback: 0041
1649809.762: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
1649909.762: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
1650009.762: <09>original critical gross delay: 0
1650109.762: <09>new critical gross delay: 0
1650209.762: DIMM 0 RttNom: 3
1650309.762: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1650409.762: DIMM 0 RttNom: 3
1650509.762: DIMM 0 RttWr: 1
1650609.762: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1650709.762: DIMM 0 RttWr: 1
1650809.762: DIMM 0 RttNom: 3
1650909.762: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1651009.762: DIMM 0 RttNom: 3
1651109.762: DIMM 0 RttWr: 1
1651209.762: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1651309.762: DIMM 0 RttWr: 1
1651409.762: DIMM 1 RttNom: 3
1651509.762: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1651609.762: DIMM 0 RttNom: 3
1651709.762: DIMM 1 RttWr: 1
1651809.762: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1651909.762: DIMM 0 RttWr: 1
1652009.762: DIMM 1 RttNom: 3
1652109.762: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1652209.762: DIMM 0 RttNom: 3
1652309.762: DIMM 1 RttWr: 1
1652409.762: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1652509.762: DIMM 0 RttWr: 1
1652609.762: AgesaHwWlPhase1: training nibble 0
1652709.762: DIMM 1 RttNom: 3
1652809.762: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1652909.763: DIMM 1 RttWr: 1
1653009.763: DIMM 1 RttWr: 1
1653109.763: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1653209.763: DIMM 1 RttWr: 1
1653309.763: DIMM 1 RttNom: 3
1653409.763: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1653509.763: DIMM 1 RttNom: 3
1653609.763: DIMM 1 RttWr: 1
1653709.763: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1653809.763: DIMM 1 RttWr: 1
1653909.763: DIMM 0 RttNom: 3
1654009.763: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1654109.763: DIMM 1 RttNom: 3
1654209.763: DIMM 0 RttWr: 1
1654309.763: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1654409.763: DIMM 1 RttWr: 1
1654509.763: DIMM 0 RttNom: 3
1654609.763: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1654709.763: DIMM 1 RttNom: 3
1654809.763: DIMM 0 RttWr: 1
1654909.763: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1655009.763: DIMM 1 RttWr: 1
1655109.763: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1655209.763: <09>Lane 00 scaled delay: 0053
1655309.763: <09>Lane 00 new seed: 0053
1655409.763: <09>Lane 01 scaled delay: 0051
1655509.763: <09>Lane 01 new seed: 0051
1655609.763: <09>Lane 02 scaled delay: 004d
1655709.763: <09>Lane 02 new seed: 004d
1655809.763: <09>Lane 03 scaled delay: 004b
1655909.763: <09>Lane 03 new seed: 004b
1656009.763: <09>Lane 04 scaled delay: 004a
1656109.763: <09>Lane 04 new seed: 004a
1656209.763: <09>Lane 05 scaled delay: 004d
1656309.763: <09>Lane 05 new seed: 004d
1656409.763: <09>Lane 06 scaled delay: 004f
1656509.763: <09>Lane 06 new seed: 004f
1656609.763: <09>Lane 07 scaled delay: 0052
1656709.763: <09>Lane 07 new seed: 0052
1656809.763: <09>Lane 08 scaled delay: 0049
1656909.763: <09>Lane 08 new seed: 0049
1657009.763: <09>Lane 00 nibble 0 raw readback: 0053
1657109.763: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0053
1657209.763: <09>Lane 00 nibble 0 adjusted value (post nibble): 0053
1657309.763: <09>Lane 01 nibble 0 raw readback: 004d
1657409.763: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004d
1657509.763: <09>Lane 01 nibble 0 adjusted value (post nibble): 004d
1657609.763: <09>Lane 02 nibble 0 raw readback: 0048
1657709.763: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
1657809.763: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
1657909.763: <09>Lane 03 nibble 0 raw readback: 0044
1658009.763: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
1658109.763: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
1658209.763: <09>Lane 04 nibble 0 raw readback: 0041
1658309.763: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
1658409.763: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
1658509.763: <09>Lane 05 nibble 0 raw readback: 0048
1658609.763: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
1658709.763: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
1658809.763: <09>Lane 06 nibble 0 raw readback: 004e
1658909.763: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
1659009.763: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
1659109.763: <09>Lane 07 nibble 0 raw readback: 0052
1659209.763: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0052
1659309.763: <09>Lane 07 nibble 0 adjusted value (post nibble): 0052
1659409.763: <09>Lane 08 nibble 0 raw readback: 0041
1659509.763: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
1659609.763: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
1659709.763: AgesaHwWlPhase1: training nibble 1
1659809.763: DIMM 1 RttNom: 3
1659909.763: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1660009.763: DIMM 1 RttWr: 1
1660109.764: DIMM 1 RttWr: 1
1660209.764: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1660309.764: DIMM 1 RttWr: 1
1660409.764: DIMM 1 RttNom: 3
1660509.764: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1660609.764: DIMM 1 RttNom: 3
1660709.764: DIMM 1 RttWr: 1
1660809.764: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1660909.764: DIMM 1 RttWr: 1
1661009.764: DIMM 0 RttNom: 3
1661109.764: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1661209.764: DIMM 1 RttNom: 3
1661309.764: DIMM 0 RttWr: 1
1661409.764: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1661509.764: DIMM 1 RttWr: 1
1661609.764: DIMM 0 RttNom: 3
1661709.764: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1661809.764: DIMM 1 RttNom: 3
1661909.764: DIMM 0 RttWr: 1
1662009.764: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1662109.764: DIMM 1 RttWr: 1
1662209.764: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1662309.764: <09>Lane 00 new seed: 0053
1662409.764: <09>Lane 01 new seed: 0051
1662509.764: <09>Lane 02 new seed: 004d
1662609.764: <09>Lane 03 new seed: 004b
1662709.764: <09>Lane 04 new seed: 004a
1662809.764: <09>Lane 05 new seed: 004d
1662909.764: <09>Lane 06 new seed: 004f
1663009.764: <09>Lane 07 new seed: 0052
1663109.764: <09>Lane 08 new seed: 0049
1663209.764: <09>Lane 00 nibble 1 raw readback: 0053
1663309.764: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
1663409.764: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
1663509.764: <09>Lane 01 nibble 1 raw readback: 004e
1663609.764: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
1663709.764: <09>Lane 01 nibble 1 adjusted value (post nibble): 004f
1663809.764: <09>Lane 02 nibble 1 raw readback: 0047
1663909.764: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
1664009.764: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
1664109.764: <09>Lane 03 nibble 1 raw readback: 0045
1664209.764: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
1664309.764: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
1664409.764: <09>Lane 04 nibble 1 raw readback: 0040
1664509.764: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
1664609.764: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
1664709.764: <09>Lane 05 nibble 1 raw readback: 0047
1664809.764: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
1664909.764: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
1665009.764: <09>Lane 06 nibble 1 raw readback: 004d
1665109.764: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
1665209.764: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
1665309.764: <09>Lane 07 nibble 1 raw readback: 0051
1665409.764: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
1665509.764: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
1665609.764: <09>Lane 08 nibble 1 raw readback: 003e
1665709.764: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003e
1665809.764: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
1665909.764: <09>original critical gross delay: 0
1666009.764: <09>new critical gross delay: 0
1666109.764: DIMM 1 RttNom: 3
1666209.764: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
1666309.764: DIMM 1 RttNom: 3
1666409.764: DIMM 1 RttWr: 1
1666509.764: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
1666609.765: DIMM 1 RttWr: 1
1666709.765: DIMM 1 RttNom: 3
1666809.765: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
1666909.765: DIMM 1 RttNom: 3
1667009.765: DIMM 1 RttWr: 1
1667109.765: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
1667209.765: DIMM 1 RttWr: 1
1667309.765: DIMM 0 RttNom: 3
1667409.765: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
1667509.765: DIMM 1 RttNom: 3
1667609.765: DIMM 0 RttWr: 1
1667709.765: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
1667809.765: DIMM 1 RttWr: 1
1667909.765: DIMM 0 RttNom: 3
1668009.765: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
1668109.765: DIMM 1 RttNom: 3
1668209.765: DIMM 0 RttWr: 1
1668309.765: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
1668409.765: DIMM 1 RttWr: 1
1668509.765: SetTargetFreq: Start
1668609.765: SetTargetFreq: Node 3: New frequency code: 000e
1668709.765: ChangeMemClk: Start
1668809.765: set_2t_configuration: Start
1668909.765: set_2t_configuration: Done
1669009.765: mct_BeforePlatformSpec: Start
1669109.765: mct_BeforePlatformSpec: Done
1669209.765: mct_PlatformSpec: Start
1669309.765: Programmed DCT 0 timing/termination pattern 00383a38 30222222
1669409.765: mct_PlatformSpec: Done
1669509.765: set_2t_configuration: Start
1669609.765: set_2t_configuration: Done
1669709.765: mct_BeforePlatformSpec: Start
1669809.765: mct_BeforePlatformSpec: Done
1669909.765: mct_PlatformSpec: Start
1670009.765: Programmed DCT 1 timing/termination pattern 00383a38 30222222
1670109.765: mct_PlatformSpec: Done
1670209.765: ChangeMemClk: Done
1670309.765: phyAssistedMemFnceTraining: Start
1670409.765: phyAssistedMemFnceTraining: training node 3 DCT 0
1670509.766: phyAssistedMemFnceTraining: done training node 3 DCT 0
1670609.766: phyAssistedMemFnceTraining: training node 3 DCT 1
1670709.766: phyAssistedMemFnceTraining: done training node 3 DCT 1
1670809.766: phyAssistedMemFnceTraining: Done
1670909.766: InitPhyCompensation: DCT 0: Start
1671009.766: Waiting for predriver calibration to be applied...done!
1671109.766: InitPhyCompensation: DCT 0: Done
1671209.766: phyAssistedMemFnceTraining: Start
1671309.766: phyAssistedMemFnceTraining: training node 3 DCT 0
1671409.766: phyAssistedMemFnceTraining: done training node 3 DCT 0
1671509.766: phyAssistedMemFnceTraining: training node 3 DCT 1
1671609.766: phyAssistedMemFnceTraining: done training node 3 DCT 1
1671709.766: phyAssistedMemFnceTraining: Done
1671809.766: InitPhyCompensation: DCT 1: Start
1671909.766: Waiting for predriver calibration to be applied...done!
1672009.766: InitPhyCompensation: DCT 1: Done
1672109.766: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
1672209.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1672309.767: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1672409.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1672509.767: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1672609.767: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
1672709.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1672809.767: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1672909.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1673009.767: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1673109.767: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
1673209.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1673309.767: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1673409.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1673509.767: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1673609.767: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
1673709.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1673809.767: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1673909.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1674009.767: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1674109.767: SetTargetFreq: Done
1674209.767: SPD2ndTiming: Start
1674309.767: SPD2ndTiming: Done
1674409.767: mct_BeforeDramInit_Prod_D: Start
1674509.767: mct_ProgramODT_D: Start
1674609.767: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1674709.767: mct_ProgramODT_D: Done
1674809.767: mct_BeforeDramInit_Prod_D: Done
1674909.767: mct_DramInit_Sw_D: Start
1675009.767: DIMM 0 RttWr: 2
1675109.767: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1675209.767: mct_SendMrsCmd: Start
1675309.767: mct_SendMrsCmd: Done
1675409.767: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1675509.767: mct_SendMrsCmd: Start
1675609.767: mct_SendMrsCmd: Done
1675709.767: DIMM 0 RttNom: 5
1675809.767: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1675909.767: mct_SendMrsCmd: Start
1676009.767: mct_SendMrsCmd: Done
1676109.768: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
1676209.768: mct_SendMrsCmd: Start
1676309.768: mct_SendMrsCmd: Done
1676409.768: DIMM 0 RttWr: 2
1676509.768: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1676609.768: mct_SendMrsCmd: Start
1676709.768: mct_SendMrsCmd: Done
1676809.768: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1676909.768: mct_SendMrsCmd: Start
1677009.768: mct_SendMrsCmd: Done
1677109.768: DIMM 0 RttNom: 5
1677209.768: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1677309.768: mct_SendMrsCmd: Start
1677409.768: mct_SendMrsCmd: Done
1677509.768: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
1677609.768: mct_SendMrsCmd: Start
1677709.768: mct_SendMrsCmd: Done
1677809.768: DIMM 1 RttWr: 2
1677909.768: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1678009.768: mct_SendMrsCmd: Start
1678109.768: mct_SendMrsCmd: Done
1678209.768: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1678309.768: mct_SendMrsCmd: Start
1678409.768: mct_SendMrsCmd: Done
1678509.768: DIMM 1 RttNom: 5
1678609.768: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1678709.768: mct_SendMrsCmd: Start
1678809.768: mct_SendMrsCmd: Done
1678909.768: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
1679009.768: mct_SendMrsCmd: Start
1679109.768: mct_SendMrsCmd: Done
1679209.768: DIMM 1 RttWr: 2
1679309.768: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1679409.768: mct_SendMrsCmd: Start
1679509.768: mct_SendMrsCmd: Done
1679609.768: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1679709.768: mct_SendMrsCmd: Start
1679809.768: mct_SendMrsCmd: Done
1679909.768: DIMM 1 RttNom: 5
1680009.768: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1680109.768: mct_SendMrsCmd: Start
1680209.768: mct_SendMrsCmd: Done
1680309.768: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
1680409.768: mct_SendMrsCmd: Start
1680509.768: mct_SendMrsCmd: Done
1680609.768: mct_DramInit_Sw_D: Done
1680709.768: AgesaHwWlPhase1: training nibble 0
1680809.768: DIMM 0 RttNom: 5
1680909.768: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1681009.768: DIMM 0 RttWr: 2
1681109.768: DIMM 0 RttWr: 2
1681209.768: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1681309.768: DIMM 0 RttWr: 2
1681409.768: DIMM 0 RttNom: 5
1681509.768: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1681609.768: DIMM 0 RttNom: 5
1681709.768: DIMM 0 RttWr: 2
1681809.769: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1681909.769: DIMM 0 RttWr: 2
1682009.769: DIMM 1 RttNom: 5
1682109.769: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1682209.769: DIMM 0 RttNom: 5
1682309.769: DIMM 1 RttWr: 2
1682409.769: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1682509.769: DIMM 0 RttWr: 2
1682609.769: DIMM 1 RttNom: 5
1682709.769: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1682809.769: DIMM 0 RttNom: 5
1682909.769: DIMM 1 RttWr: 2
1683009.769: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1683109.769: DIMM 0 RttWr: 2
1683209.769: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1683309.769: <09>Lane 00 scaled delay: 005f
1683409.769: <09>Lane 00 new seed: 005f
1683509.769: <09>Lane 01 scaled delay: 0059
1683609.769: <09>Lane 01 new seed: 0059
1683709.769: <09>Lane 02 scaled delay: 0055
1683809.769: <09>Lane 02 new seed: 0055
1683909.769: <09>Lane 03 scaled delay: 0052
1684009.769: <09>Lane 03 new seed: 0052
1684109.769: <09>Lane 04 scaled delay: 004f
1684209.769: <09>Lane 04 new seed: 004f
1684309.769: <09>Lane 05 scaled delay: 0054
1684409.769: <09>Lane 05 new seed: 0054
1684509.769: <09>Lane 06 scaled delay: 0059
1684609.769: <09>Lane 06 new seed: 0059
1684709.769: <09>Lane 07 scaled delay: 005d
1684809.769: <09>Lane 07 new seed: 005d
1684909.769: <09>Lane 08 scaled delay: 004d
1685009.769: <09>Lane 08 new seed: 004d
1685109.769: <09>Lane 00 nibble 0 raw readback: 005f
1685209.769: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
1685309.769: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
1685409.769: <09>Lane 01 nibble 0 raw readback: 0054
1685509.769: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0054
1685609.769: <09>Lane 01 nibble 0 adjusted value (post nibble): 0054
1685709.769: <09>Lane 02 nibble 0 raw readback: 0050
1685809.769: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
1685909.769: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
1686009.769: <09>Lane 03 nibble 0 raw readback: 0051
1686109.769: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
1686209.769: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
1686309.769: <09>Lane 04 nibble 0 raw readback: 004d
1686409.769: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
1686509.769: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
1686609.769: <09>Lane 05 nibble 0 raw readback: 0053
1686709.769: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
1686809.769: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
1686909.769: <09>Lane 06 nibble 0 raw readback: 0054
1687009.769: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0054
1687109.769: <09>Lane 06 nibble 0 adjusted value (post nibble): 0054
1687209.769: <09>Lane 07 nibble 0 raw readback: 0059
1687309.769: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
1687409.770: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
1687509.770: <09>Lane 08 nibble 0 raw readback: 0047
1687609.770: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
1687709.770: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
1687809.770: AgesaHwWlPhase1: training nibble 1
1687909.770: DIMM 0 RttNom: 5
1688009.770: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1688109.770: DIMM 0 RttWr: 2
1688209.770: DIMM 0 RttWr: 2
1688309.770: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1688409.770: DIMM 0 RttWr: 2
1688509.770: DIMM 0 RttNom: 5
1688609.770: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1688709.770: DIMM 0 RttNom: 5
1688809.770: DIMM 0 RttWr: 2
1688909.770: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1689009.770: DIMM 0 RttWr: 2
1689109.770: DIMM 1 RttNom: 5
1689209.770: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1689309.770: DIMM 0 RttNom: 5
1689409.770: DIMM 1 RttWr: 2
1689509.770: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1689609.770: DIMM 0 RttWr: 2
1689709.770: DIMM 1 RttNom: 5
1689809.770: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1689909.770: DIMM 0 RttNom: 5
1690009.770: DIMM 1 RttWr: 2
1690109.770: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1690209.770: DIMM 0 RttWr: 2
1690309.770: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1690409.770: <09>Lane 00 new seed: 005f
1690509.770: <09>Lane 01 new seed: 0059
1690609.770: <09>Lane 02 new seed: 0055
1690709.770: <09>Lane 03 new seed: 0052
1690809.770: <09>Lane 04 new seed: 004f
1690909.770: <09>Lane 05 new seed: 0054
1691009.770: <09>Lane 06 new seed: 0059
1691109.770: <09>Lane 07 new seed: 005d
1691209.770: <09>Lane 08 new seed: 004d
1691309.770: <09>Lane 00 nibble 1 raw readback: 0061
1691409.770: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0061
1691509.770: <09>Lane 00 nibble 1 adjusted value (post nibble): 0060
1691609.770: <09>Lane 01 nibble 1 raw readback: 0059
1691709.770: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
1691809.770: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
1691909.770: <09>Lane 02 nibble 1 raw readback: 0054
1692009.770: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
1692109.770: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
1692209.770: <09>Lane 03 nibble 1 raw readback: 004f
1692309.770: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
1692409.770: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1692509.770: <09>Lane 04 nibble 1 raw readback: 004b
1692609.770: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
1692709.770: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
1692809.770: <09>Lane 05 nibble 1 raw readback: 0050
1692909.770: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
1693009.770: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
1693109.770: <09>Lane 06 nibble 1 raw readback: 0055
1693209.770: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
1693309.770: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
1693409.770: <09>Lane 07 nibble 1 raw readback: 005c
1693509.770: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
1693609.770: <09>Lane 07 nibble 1 adjusted value (post nibble): 005c
1693709.770: <09>Lane 08 nibble 1 raw readback: 0049
1693809.770: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0049
1693909.770: <09>Lane 08 nibble 1 adjusted value (post nibble): 004b
1694009.770: <09>original critical gross delay: 0
1694109.770: <09>new critical gross delay: 0
1694209.771: DIMM 0 RttNom: 5
1694309.771: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1694409.771: DIMM 0 RttNom: 5
1694509.771: DIMM 0 RttWr: 2
1694609.771: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1694709.771: DIMM 0 RttWr: 2
1694809.771: DIMM 0 RttNom: 5
1694909.771: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1695009.771: DIMM 0 RttNom: 5
1695109.771: DIMM 0 RttWr: 2
1695209.771: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1695309.771: DIMM 0 RttWr: 2
1695409.771: DIMM 1 RttNom: 5
1695509.771: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1695609.771: DIMM 0 RttNom: 5
1695709.771: DIMM 1 RttWr: 2
1695809.771: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1695909.771: DIMM 0 RttWr: 2
1696009.771: DIMM 1 RttNom: 5
1696109.771: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1696209.771: DIMM 0 RttNom: 5
1696309.771: DIMM 1 RttWr: 2
1696409.771: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1696509.771: DIMM 0 RttWr: 2
1696609.771: AgesaHwWlPhase1: training nibble 0
1696709.771: DIMM 1 RttNom: 5
1696809.771: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1696909.771: DIMM 1 RttWr: 2
1697009.771: DIMM 1 RttWr: 2
1697109.771: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1697209.771: DIMM 1 RttWr: 2
1697309.771: DIMM 1 RttNom: 5
1697409.771: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1697509.771: DIMM 1 RttNom: 5
1697609.771: DIMM 1 RttWr: 2
1697709.771: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1697809.771: DIMM 1 RttWr: 2
1697909.771: DIMM 0 RttNom: 5
1698009.771: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1698109.771: DIMM 1 RttNom: 5
1698209.771: DIMM 0 RttWr: 2
1698309.771: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1698409.771: DIMM 1 RttWr: 2
1698509.771: DIMM 0 RttNom: 5
1698609.771: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1698709.771: DIMM 1 RttNom: 5
1698809.771: DIMM 0 RttWr: 2
1698909.772: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1699009.771: DIMM 1 RttWr: 2
1699109.771: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1699209.771: <09>Lane 00 scaled delay: 005d
1699309.771: <09>Lane 00 new seed: 005d
1699409.771: <09>Lane 01 scaled delay: 0057
1699509.771: <09>Lane 01 new seed: 0057
1699609.771: <09>Lane 02 scaled delay: 0053
1699709.771: <09>Lane 02 new seed: 0053
1699809.772: <09>Lane 03 scaled delay: 0052
1699909.772: <09>Lane 03 new seed: 0052
1700009.772: <09>Lane 04 scaled delay: 004d
1700109.772: <09>Lane 04 new seed: 004d
1700209.772: <09>Lane 05 scaled delay: 0052
1700309.772: <09>Lane 05 new seed: 0052
1700409.772: <09>Lane 06 scaled delay: 0053
1700509.772: <09>Lane 06 new seed: 0053
1700609.772: <09>Lane 07 scaled delay: 0059
1700709.772: <09>Lane 07 new seed: 0059
1700809.772: <09>Lane 08 scaled delay: 004a
1700909.772: <09>Lane 08 new seed: 004a
1701009.772: <09>Lane 00 nibble 0 raw readback: 005d
1701109.772: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005d
1701209.772: <09>Lane 00 nibble 0 adjusted value (post nibble): 005d
1701309.772: <09>Lane 01 nibble 0 raw readback: 0054
1701409.772: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0054
1701509.772: <09>Lane 01 nibble 0 adjusted value (post nibble): 0054
1701609.772: <09>Lane 02 nibble 0 raw readback: 004f
1701709.772: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
1701809.772: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
1701909.772: <09>Lane 03 nibble 0 raw readback: 004d
1702009.772: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
1702109.772: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
1702209.772: <09>Lane 04 nibble 0 raw readback: 0049
1702309.772: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
1702409.772: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
1702509.772: <09>Lane 05 nibble 0 raw readback: 004f
1702609.772: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
1702709.772: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
1702809.772: <09>Lane 06 nibble 0 raw readback: 004f
1702909.772: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004f
1703009.772: <09>Lane 06 nibble 0 adjusted value (post nibble): 004f
1703109.772: <09>Lane 07 nibble 0 raw readback: 0057
1703209.772: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0057
1703309.772: <09>Lane 07 nibble 0 adjusted value (post nibble): 0057
1703409.772: <09>Lane 08 nibble 0 raw readback: 0045
1703509.772: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
1703609.772: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
1703709.772: AgesaHwWlPhase1: training nibble 1
1703809.772: DIMM 1 RttNom: 5
1703909.772: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1704009.772: DIMM 1 RttWr: 2
1704109.772: DIMM 1 RttWr: 2
1704209.772: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1704309.772: DIMM 1 RttWr: 2
1704409.772: DIMM 1 RttNom: 5
1704509.772: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1704609.772: DIMM 1 RttNom: 5
1704709.772: DIMM 1 RttWr: 2
1704809.772: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1704909.772: DIMM 1 RttWr: 2
1705009.772: DIMM 0 RttNom: 5
1705109.772: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1705209.772: DIMM 1 RttNom: 5
1705309.772: DIMM 0 RttWr: 2
1705409.772: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1705509.772: DIMM 1 RttWr: 2
1705609.772: DIMM 0 RttNom: 5
1705709.772: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1705809.772: DIMM 1 RttNom: 5
1705909.772: DIMM 0 RttWr: 2
1706009.772: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1706109.772: DIMM 1 RttWr: 2
1706209.772: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1706309.772: <09>Lane 00 new seed: 005d
1706409.772: <09>Lane 01 new seed: 0057
1706509.772: <09>Lane 02 new seed: 0053
1706609.772: <09>Lane 03 new seed: 0052
1706709.772: <09>Lane 04 new seed: 004d
1706809.772: <09>Lane 05 new seed: 0052
1706909.772: <09>Lane 06 new seed: 0053
1707009.773: <09>Lane 07 new seed: 0059
1707109.773: <09>Lane 08 new seed: 004a
1707209.773: <09>Lane 00 nibble 1 raw readback: 005d
1707309.773: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
1707409.773: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
1707509.773: <09>Lane 01 nibble 1 raw readback: 0056
1707609.773: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
1707709.773: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
1707809.773: <09>Lane 02 nibble 1 raw readback: 0050
1707909.773: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0050
1708009.773: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
1708109.773: <09>Lane 03 nibble 1 raw readback: 004e
1708209.773: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
1708309.773: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1708409.773: <09>Lane 04 nibble 1 raw readback: 0048
1708509.773: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
1708609.773: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
1708709.773: <09>Lane 05 nibble 1 raw readback: 004e
1708809.773: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004e
1708909.773: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
1709009.773: <09>Lane 06 nibble 1 raw readback: 004f
1709109.773: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
1709209.773: <09>Lane 06 nibble 1 adjusted value (post nibble): 0051
1709309.773: <09>Lane 07 nibble 1 raw readback: 0058
1709409.773: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0058
1709509.773: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
1709609.773: <09>Lane 08 nibble 1 raw readback: 0044
1709709.773: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0044
1709809.773: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
1709909.773: <09>original critical gross delay: 0
1710009.773: <09>new critical gross delay: 0
1710109.773: DIMM 1 RttNom: 5
1710209.773: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
1710309.773: DIMM 1 RttNom: 5
1710409.773: DIMM 1 RttWr: 2
1710509.773: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
1710609.773: DIMM 1 RttWr: 2
1710709.773: DIMM 1 RttNom: 5
1710809.773: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
1710909.773: DIMM 1 RttNom: 5
1711009.773: DIMM 1 RttWr: 2
1711109.773: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
1711209.773: DIMM 1 RttWr: 2
1711309.773: DIMM 0 RttNom: 5
1711409.773: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
1711509.773: DIMM 1 RttNom: 5
1711609.773: DIMM 0 RttWr: 2
1711709.773: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
1711809.773: DIMM 1 RttWr: 2
1711909.773: DIMM 0 RttNom: 5
1712009.773: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
1712109.773: DIMM 1 RttNom: 5
1712209.773: DIMM 0 RttWr: 2
1712309.773: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
1712409.773: DIMM 1 RttWr: 2
1712509.773: SPD2ndTiming: Start
1712609.774: SPD2ndTiming: Done
1712709.774: mct_BeforeDramInit_Prod_D: Start
1712809.774: mct_ProgramODT_D: Start
1712909.774: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1713009.774: mct_ProgramODT_D: Done
1713109.774: mct_BeforeDramInit_Prod_D: Done
1713209.774: mct_DramInit_Sw_D: Start
1713309.774: DIMM 0 RttWr: 2
1713409.774: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1713509.774: mct_SendMrsCmd: Start
1713609.774: mct_SendMrsCmd: Done
1713709.774: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1713809.774: mct_SendMrsCmd: Start
1713909.774: mct_SendMrsCmd: Done
1714009.774: DIMM 0 RttNom: 5
1714109.774: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1714209.774: mct_SendMrsCmd: Start
1714309.774: mct_SendMrsCmd: Done
1714409.774: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
1714509.774: mct_SendMrsCmd: Start
1714609.774: mct_SendMrsCmd: Done
1714709.774: DIMM 0 RttWr: 2
1714809.774: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1714909.774: mct_SendMrsCmd: Start
1715009.774: mct_SendMrsCmd: Done
1715109.774: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1715209.774: mct_SendMrsCmd: Start
1715309.774: mct_SendMrsCmd: Done
1715409.774: DIMM 0 RttNom: 5
1715509.774: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1715609.774: mct_SendMrsCmd: Start
1715709.774: mct_SendMrsCmd: Done
1715809.774: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
1715909.774: mct_SendMrsCmd: Start
1716009.774: mct_SendMrsCmd: Done
1716109.774: DIMM 1 RttWr: 2
1716209.774: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1716309.774: mct_SendMrsCmd: Start
1716409.774: mct_SendMrsCmd: Done
1716509.774: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1716609.774: mct_SendMrsCmd: Start
1716709.774: mct_SendMrsCmd: Done
1716809.774: DIMM 1 RttNom: 5
1716909.774: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1717009.774: mct_SendMrsCmd: Start
1717109.774: mct_SendMrsCmd: Done
1717209.774: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
1717309.774: mct_SendMrsCmd: Start
1717409.774: mct_SendMrsCmd: Done
1717509.775: DIMM 1 RttWr: 2
1717609.775: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1717709.775: mct_SendMrsCmd: Start
1717809.775: mct_SendMrsCmd: Done
1717909.775: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1718009.775: mct_SendMrsCmd: Start
1718109.775: mct_SendMrsCmd: Done
1718209.775: DIMM 1 RttNom: 5
1718309.775: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1718409.775: mct_SendMrsCmd: Start
1718509.775: mct_SendMrsCmd: Done
1718609.775: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
1718709.775: mct_SendMrsCmd: Start
1718809.775: mct_SendMrsCmd: Done
1718909.775: mct_DramInit_Sw_D: Done
1719009.775: AgesaHwWlPhase1: training nibble 0
1719109.775: DIMM 0 RttNom: 5
1719209.775: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1719309.775: DIMM 0 RttWr: 2
1719409.775: DIMM 0 RttWr: 2
1719509.775: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1719609.775: DIMM 0 RttWr: 2
1719709.775: DIMM 0 RttNom: 5
1719809.775: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1719909.775: DIMM 0 RttNom: 5
1720009.775: DIMM 0 RttWr: 2
1720109.775: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1720209.775: DIMM 0 RttWr: 2
1720309.775: DIMM 1 RttNom: 5
1720409.775: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1720509.775: DIMM 0 RttNom: 5
1720609.775: DIMM 1 RttWr: 2
1720709.775: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1720809.775: DIMM 0 RttWr: 2
1720909.775: DIMM 1 RttNom: 5
1721009.775: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1721109.775: DIMM 0 RttNom: 5
1721209.775: DIMM 1 RttWr: 2
1721309.775: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1721409.775: DIMM 0 RttWr: 2
1721509.775: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1721609.775: <09>Lane 00 scaled delay: 0061
1721709.775: <09>Lane 00 new seed: 0061
1721809.775: <09>Lane 01 scaled delay: 005c
1721909.775: <09>Lane 01 new seed: 005c
1722009.775: <09>Lane 02 scaled delay: 0058
1722109.775: <09>Lane 02 new seed: 0058
1722209.775: <09>Lane 03 scaled delay: 0052
1722309.775: <09>Lane 03 new seed: 0052
1722409.775: <09>Lane 04 scaled delay: 004f
1722509.775: <09>Lane 04 new seed: 004f
1722609.775: <09>Lane 05 scaled delay: 0055
1722709.775: <09>Lane 05 new seed: 0055
1722809.775: <09>Lane 06 scaled delay: 0059
1722909.775: <09>Lane 06 new seed: 0059
1723009.775: <09>Lane 07 scaled delay: 005e
1723109.776: <09>Lane 07 new seed: 005e
1723209.775: <09>Lane 08 scaled delay: 004e
1723309.776: <09>Lane 08 new seed: 004e
1723409.776: <09>Lane 00 nibble 0 raw readback: 001f
1723509.776: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
1723609.776: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
1723709.776: <09>Lane 01 nibble 0 raw readback: 0059
1723809.776: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
1723909.776: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
1724009.776: <09>Lane 02 nibble 0 raw readback: 0054
1724109.776: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
1724209.776: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
1724309.776: <09>Lane 03 nibble 0 raw readback: 004e
1724409.776: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
1724509.776: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
1724609.776: <09>Lane 04 nibble 0 raw readback: 004c
1724709.776: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
1724809.776: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
1724909.776: <09>Lane 05 nibble 0 raw readback: 0054
1725009.776: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
1725109.776: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
1725209.776: <09>Lane 06 nibble 0 raw readback: 0059
1725309.776: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0059
1725409.776: <09>Lane 06 nibble 0 adjusted value (post nibble): 0059
1725509.776: <09>Lane 07 nibble 0 raw readback: 0060
1725609.776: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0060
1725709.776: <09>Lane 07 nibble 0 adjusted value (post nibble): 0060
1725809.776: <09>Lane 08 nibble 0 raw readback: 0049
1725909.776: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
1726009.776: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
1726109.776: AgesaHwWlPhase1: training nibble 1
1726209.776: DIMM 0 RttNom: 5
1726309.776: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1726409.776: DIMM 0 RttWr: 2
1726509.776: DIMM 0 RttWr: 2
1726609.776: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1726709.776: DIMM 0 RttWr: 2
1726809.776: DIMM 0 RttNom: 5
1726909.776: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1727009.776: DIMM 0 RttNom: 5
1727109.776: DIMM 0 RttWr: 2
1727209.776: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1727309.776: DIMM 0 RttWr: 2
1727409.776: DIMM 1 RttNom: 5
1727509.776: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1727609.776: DIMM 0 RttNom: 5
1727709.776: DIMM 1 RttWr: 2
1727809.776: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1727909.776: DIMM 0 RttWr: 2
1728009.776: DIMM 1 RttNom: 5
1728109.776: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1728209.776: DIMM 0 RttNom: 5
1728309.776: DIMM 1 RttWr: 2
1728409.776: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1728509.776: DIMM 0 RttWr: 2
1728609.776: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1728709.776: <09>Lane 00 new seed: 0061
1728809.776: <09>Lane 01 new seed: 005c
1728909.776: <09>Lane 02 new seed: 0058
1729009.776: <09>Lane 03 new seed: 0052
1729109.776: <09>Lane 04 new seed: 004f
1729209.776: <09>Lane 05 new seed: 0055
1729309.776: <09>Lane 06 new seed: 0059
1729409.776: <09>Lane 07 new seed: 005e
1729509.776: <09>Lane 08 new seed: 004e
1729609.777: <09>Lane 00 nibble 1 raw readback: 0021
1729709.777: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0061
1729809.777: <09>Lane 00 nibble 1 adjusted value (post nibble): 0061
1729909.777: <09>Lane 01 nibble 1 raw readback: 005c
1730009.777: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005c
1730109.777: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
1730209.777: <09>Lane 02 nibble 1 raw readback: 0056
1730309.777: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
1730409.777: <09>Lane 02 nibble 1 adjusted value (post nibble): 0057
1730509.777: <09>Lane 03 nibble 1 raw readback: 004f
1730609.777: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
1730709.777: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1730809.777: <09>Lane 04 nibble 1 raw readback: 004c
1730909.777: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
1731009.777: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
1731109.777: <09>Lane 05 nibble 1 raw readback: 0053
1731209.777: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0053
1731309.777: <09>Lane 05 nibble 1 adjusted value (post nibble): 0054
1731409.777: <09>Lane 06 nibble 1 raw readback: 005a
1731509.777: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005a
1731609.777: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
1731709.777: <09>Lane 07 nibble 1 raw readback: 005f
1731809.777: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005f
1731909.777: <09>Lane 07 nibble 1 adjusted value (post nibble): 005e
1732009.777: <09>Lane 08 nibble 1 raw readback: 004a
1732109.777: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
1732209.777: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
1732309.777: <09>original critical gross delay: 0
1732409.777: <09>new critical gross delay: 0
1732509.777: DIMM 0 RttNom: 5
1732609.777: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1732709.777: DIMM 0 RttNom: 5
1732809.777: DIMM 0 RttWr: 2
1732909.777: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1733009.777: DIMM 0 RttWr: 2
1733109.777: DIMM 0 RttNom: 5
1733209.777: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1733309.777: DIMM 0 RttNom: 5
1733409.777: DIMM 0 RttWr: 2
1733509.777: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1733609.777: DIMM 0 RttWr: 2
1733709.777: DIMM 1 RttNom: 5
1733809.777: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1733909.777: DIMM 0 RttNom: 5
1734009.777: DIMM 1 RttWr: 2
1734109.777: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1734209.777: DIMM 0 RttWr: 2
1734309.777: DIMM 1 RttNom: 5
1734409.777: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1734509.777: DIMM 0 RttNom: 5
1734609.777: DIMM 1 RttWr: 2
1734709.777: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1734809.777: DIMM 0 RttWr: 2
1734909.777: AgesaHwWlPhase1: training nibble 0
1735009.777: DIMM 1 RttNom: 5
1735109.777: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1735209.777: DIMM 1 RttWr: 2
1735309.777: DIMM 1 RttWr: 2
1735409.777: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1735509.777: DIMM 1 RttWr: 2
1735609.778: DIMM 1 RttNom: 5
1735709.777: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1735809.777: DIMM 1 RttNom: 5
1735909.778: DIMM 1 RttWr: 2
1736009.778: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1736109.778: DIMM 1 RttWr: 2
1736209.778: DIMM 0 RttNom: 5
1736309.778: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1736409.778: DIMM 1 RttNom: 5
1736509.778: DIMM 0 RttWr: 2
1736609.778: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1736709.778: DIMM 1 RttWr: 2
1736809.778: DIMM 0 RttNom: 5
1736909.778: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1737009.778: DIMM 1 RttNom: 5
1737109.778: DIMM 0 RttWr: 2
1737209.778: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1737309.778: DIMM 1 RttWr: 2
1737409.778: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1737509.778: <09>Lane 00 scaled delay: 005f
1737609.778: <09>Lane 00 new seed: 005f
1737709.778: <09>Lane 01 scaled delay: 005a
1737809.778: <09>Lane 01 new seed: 005a
1737909.778: <09>Lane 02 scaled delay: 0054
1738009.778: <09>Lane 02 new seed: 0054
1738109.778: <09>Lane 03 scaled delay: 0052
1738209.778: <09>Lane 03 new seed: 0052
1738309.778: <09>Lane 04 scaled delay: 004e
1738409.778: <09>Lane 04 new seed: 004e
1738509.778: <09>Lane 05 scaled delay: 0054
1738609.778: <09>Lane 05 new seed: 0054
1738709.778: <09>Lane 06 scaled delay: 0059
1738809.778: <09>Lane 06 new seed: 0059
1738909.778: <09>Lane 07 scaled delay: 005d
1739009.778: <09>Lane 07 new seed: 005d
1739109.778: <09>Lane 08 scaled delay: 004b
1739209.778: <09>Lane 08 new seed: 004b
1739309.778: <09>Lane 00 nibble 0 raw readback: 005d
1739409.778: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005d
1739509.778: <09>Lane 00 nibble 0 adjusted value (post nibble): 005d
1739609.778: <09>Lane 01 nibble 0 raw readback: 0058
1739709.778: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
1739809.778: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
1739909.778: <09>Lane 02 nibble 0 raw readback: 0050
1740009.778: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
1740109.778: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
1740209.778: <09>Lane 03 nibble 0 raw readback: 004d
1740309.778: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
1740409.778: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
1740509.778: <09>Lane 04 nibble 0 raw readback: 0049
1740609.778: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
1740709.778: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
1740809.778: <09>Lane 05 nibble 0 raw readback: 0052
1740909.778: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0052
1741009.778: <09>Lane 05 nibble 0 adjusted value (post nibble): 0052
1741109.778: <09>Lane 06 nibble 0 raw readback: 0058
1741209.778: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
1741309.778: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
1741409.778: <09>Lane 07 nibble 0 raw readback: 005d
1741509.778: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005d
1741609.778: <09>Lane 07 nibble 0 adjusted value (post nibble): 005d
1741709.778: <09>Lane 08 nibble 0 raw readback: 0049
1741809.778: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
1741909.778: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
1742009.778: AgesaHwWlPhase1: training nibble 1
1742109.778: DIMM 1 RttNom: 5
1742209.778: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1742309.778: DIMM 1 RttWr: 2
1742409.778: DIMM 1 RttWr: 2
1742509.778: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1742609.778: DIMM 1 RttWr: 2
1742709.778: DIMM 1 RttNom: 5
1742809.778: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1742909.778: DIMM 1 RttNom: 5
1743009.778: DIMM 1 RttWr: 2
1743109.779: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1743209.778: DIMM 1 RttWr: 2
1743309.779: DIMM 0 RttNom: 5
1743409.779: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1743509.779: DIMM 1 RttNom: 5
1743609.779: DIMM 0 RttWr: 2
1743709.779: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1743809.779: DIMM 1 RttWr: 2
1743909.779: DIMM 0 RttNom: 5
1744009.779: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1744109.779: DIMM 1 RttNom: 5
1744209.779: DIMM 0 RttWr: 2
1744309.779: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1744409.779: DIMM 1 RttWr: 2
1744509.779: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1744609.779: <09>Lane 00 new seed: 005f
1744709.779: <09>Lane 01 new seed: 005a
1744809.779: <09>Lane 02 new seed: 0054
1744909.779: <09>Lane 03 new seed: 0052
1745009.779: <09>Lane 04 new seed: 004e
1745109.779: <09>Lane 05 new seed: 0054
1745209.779: <09>Lane 06 new seed: 0059
1745309.779: <09>Lane 07 new seed: 005d
1745409.779: <09>Lane 08 new seed: 004b
1745509.779: <09>Lane 00 nibble 1 raw readback: 005f
1745609.779: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
1745709.779: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
1745809.779: <09>Lane 01 nibble 1 raw readback: 0059
1745909.779: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
1746009.779: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
1746109.779: <09>Lane 02 nibble 1 raw readback: 0051
1746209.779: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
1746309.779: <09>Lane 02 nibble 1 adjusted value (post nibble): 0052
1746409.779: <09>Lane 03 nibble 1 raw readback: 004e
1746509.779: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
1746609.779: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
1746709.779: <09>Lane 04 nibble 1 raw readback: 0049
1746809.779: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
1746909.779: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
1747009.779: <09>Lane 05 nibble 1 raw readback: 0050
1747109.779: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
1747209.779: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
1747309.779: <09>Lane 06 nibble 1 raw readback: 0058
1747409.779: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
1747509.779: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
1747609.779: <09>Lane 07 nibble 1 raw readback: 005d
1747709.779: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
1747809.779: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
1747909.779: <09>Lane 08 nibble 1 raw readback: 0046
1748009.779: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0046
1748109.779: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
1748209.779: <09>original critical gross delay: 0
1748309.779: <09>new critical gross delay: 0
1748409.779: DIMM 1 RttNom: 5
1748509.779: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
1748609.779: DIMM 1 RttNom: 5
1748709.779: DIMM 1 RttWr: 2
1748809.779: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
1748909.779: DIMM 1 RttWr: 2
1749009.779: DIMM 1 RttNom: 5
1749109.779: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
1749209.779: DIMM 1 RttNom: 5
1749309.779: DIMM 1 RttWr: 2
1749409.779: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
1749509.780: DIMM 1 RttWr: 2
1749609.780: DIMM 0 RttNom: 5
1749709.780: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
1749809.780: DIMM 1 RttNom: 5
1749909.780: DIMM 0 RttWr: 2
1750009.780: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
1750109.780: DIMM 1 RttWr: 2
1750209.780: DIMM 0 RttNom: 5
1750309.780: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
1750409.780: DIMM 1 RttNom: 5
1750509.780: DIMM 0 RttWr: 2
1750609.780: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
1750709.780: DIMM 1 RttWr: 2
1750809.780: SetTargetFreq: Start
1750909.780: SetTargetFreq: Node 3: New frequency code: 0012
1751009.780: ChangeMemClk: Start
1751109.780: set_2t_configuration: Start
1751209.780: set_2t_configuration: Done
1751309.780: mct_BeforePlatformSpec: Start
1751409.780: mct_BeforePlatformSpec: Done
1751509.780: mct_PlatformSpec: Start
1751609.780: Programmed DCT 0 timing/termination pattern 00353935 30222222
1751709.780: mct_PlatformSpec: Done
1751809.780: set_2t_configuration: Start
1751909.780: set_2t_configuration: Done
1752009.780: mct_BeforePlatformSpec: Start
1752109.780: mct_BeforePlatformSpec: Done
1752209.780: mct_PlatformSpec: Start
1752309.780: Programmed DCT 1 timing/termination pattern 00353935 30222222
1752409.780: mct_PlatformSpec: Done
1752509.780: ChangeMemClk: Done
1752609.780: phyAssistedMemFnceTraining: Start
1752709.780: phyAssistedMemFnceTraining: training node 3 DCT 0
1752809.781: phyAssistedMemFnceTraining: done training node 3 DCT 0
1752909.781: phyAssistedMemFnceTraining: training node 3 DCT 1
1753009.781: phyAssistedMemFnceTraining: done training node 3 DCT 1
1753109.781: phyAssistedMemFnceTraining: Done
1753209.781: InitPhyCompensation: DCT 0: Start
1753309.781: Waiting for predriver calibration to be applied...done!
1753409.781: InitPhyCompensation: DCT 0: Done
1753509.781: phyAssistedMemFnceTraining: Start
1753609.781: phyAssistedMemFnceTraining: training node 3 DCT 0
1753709.781: phyAssistedMemFnceTraining: done training node 3 DCT 0
1753809.781: phyAssistedMemFnceTraining: training node 3 DCT 1
1753909.781: phyAssistedMemFnceTraining: done training node 3 DCT 1
1754009.781: phyAssistedMemFnceTraining: Done
1754109.781: InitPhyCompensation: DCT 1: Start
1754209.781: Waiting for predriver calibration to be applied...done!
1754309.781: InitPhyCompensation: DCT 1: Done
1754409.781: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
1754509.781: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1754609.781: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
1754709.782: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1754809.782: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
1754909.782: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
1755009.782: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1755109.782: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
1755209.782: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
1755309.782: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
1755409.782: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
1755509.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1755609.782: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
1755709.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1755809.782: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
1755909.782: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
1756009.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1756109.782: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
1756209.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
1756309.782: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
1756409.782: SetTargetFreq: Done
1756509.782: SPD2ndTiming: Start
1756609.782: SPD2ndTiming: Done
1756709.782: mct_BeforeDramInit_Prod_D: Start
1756809.782: mct_ProgramODT_D: Start
1756909.782: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
1757009.782: mct_ProgramODT_D: Done
1757109.782: mct_BeforeDramInit_Prod_D: Done
1757209.782: mct_DramInit_Sw_D: Start
1757309.782: DIMM 0 RttWr: 1
1757409.782: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1757509.782: mct_SendMrsCmd: Start
1757609.782: mct_SendMrsCmd: Done
1757709.782: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
1757809.782: mct_SendMrsCmd: Start
1757909.782: mct_SendMrsCmd: Done
1758009.782: DIMM 0 RttNom: 4
1758109.783: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1758209.783: mct_SendMrsCmd: Start
1758309.783: mct_SendMrsCmd: Done
1758409.783: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
1758509.783: mct_SendMrsCmd: Start
1758609.783: mct_SendMrsCmd: Done
1758709.783: DIMM 0 RttWr: 1
1758809.783: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1758909.783: mct_SendMrsCmd: Start
1759009.783: mct_SendMrsCmd: Done
1759109.783: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
1759209.783: mct_SendMrsCmd: Start
1759309.783: mct_SendMrsCmd: Done
1759409.783: DIMM 0 RttNom: 4
1759509.783: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1759609.783: mct_SendMrsCmd: Start
1759709.783: mct_SendMrsCmd: Done
1759809.783: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
1759909.783: mct_SendMrsCmd: Start
1760009.783: mct_SendMrsCmd: Done
1760109.783: DIMM 1 RttWr: 1
1760209.783: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1760309.783: mct_SendMrsCmd: Start
1760409.783: mct_SendMrsCmd: Done
1760509.783: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
1760609.783: mct_SendMrsCmd: Start
1760709.783: mct_SendMrsCmd: Done
1760809.783: DIMM 1 RttNom: 4
1760909.783: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1761009.783: mct_SendMrsCmd: Start
1761109.783: mct_SendMrsCmd: Done
1761209.783: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
1761309.783: mct_SendMrsCmd: Start
1761409.783: mct_SendMrsCmd: Done
1761509.783: DIMM 1 RttWr: 1
1761609.783: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1761709.783: mct_SendMrsCmd: Start
1761809.783: mct_SendMrsCmd: Done
1761909.783: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
1762009.783: mct_SendMrsCmd: Start
1762109.783: mct_SendMrsCmd: Done
1762209.783: DIMM 1 RttNom: 4
1762309.783: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1762409.783: mct_SendMrsCmd: Start
1762509.783: mct_SendMrsCmd: Done
1762609.783: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
1762709.783: mct_SendMrsCmd: Start
1762809.783: mct_SendMrsCmd: Done
1762909.783: mct_DramInit_Sw_D: Done
1763009.783: AgesaHwWlPhase1: training nibble 0
1763109.783: DIMM 0 RttNom: 4
1763209.783: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1763309.783: DIMM 0 RttWr: 1
1763409.783: DIMM 0 RttWr: 1
1763509.784: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1763609.783: DIMM 0 RttWr: 1
1763709.783: DIMM 0 RttNom: 4
1763809.784: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1763909.784: DIMM 0 RttNom: 4
1764009.784: DIMM 0 RttWr: 1
1764109.784: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1764209.784: DIMM 0 RttWr: 1
1764309.784: DIMM 1 RttNom: 4
1764409.784: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1764509.784: DIMM 0 RttNom: 4
1764609.784: DIMM 1 RttWr: 1
1764709.784: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1764809.784: DIMM 0 RttWr: 1
1764909.784: DIMM 1 RttNom: 4
1765009.784: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1765109.784: DIMM 0 RttNom: 4
1765209.784: DIMM 1 RttWr: 1
1765309.784: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1765409.784: DIMM 0 RttWr: 1
1765509.784: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1765609.784: <09>Lane 00 scaled delay: 006c
1765709.784: <09>Lane 00 new seed: 006c
1765809.784: <09>Lane 01 scaled delay: 0064
1765909.784: <09>Lane 01 new seed: 0064
1766009.784: <09>Lane 02 scaled delay: 005e
1766109.784: <09>Lane 02 new seed: 005e
1766209.784: <09>Lane 03 scaled delay: 0059
1766309.784: <09>Lane 03 new seed: 0059
1766409.784: <09>Lane 04 scaled delay: 0055
1766509.784: <09>Lane 04 new seed: 0055
1766609.784: <09>Lane 05 scaled delay: 005b
1766709.784: <09>Lane 05 new seed: 005b
1766809.784: <09>Lane 06 scaled delay: 0061
1766909.784: <09>Lane 06 new seed: 0061
1767009.784: <09>Lane 07 scaled delay: 0067
1767109.784: <09>Lane 07 new seed: 0067
1767209.784: <09>Lane 08 scaled delay: 0053
1767309.784: <09>Lane 08 new seed: 0053
1767409.784: <09>Lane 00 nibble 0 raw readback: 0030
1767509.784: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
1767609.784: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
1767709.784: <09>Lane 01 nibble 0 raw readback: 0023
1767809.784: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0063
1767909.784: <09>Lane 01 nibble 0 adjusted value (post nibble): 0063
1768009.784: <09>Lane 02 nibble 0 raw readback: 005c
1768109.784: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005c
1768209.784: <09>Lane 02 nibble 0 adjusted value (post nibble): 005c
1768309.784: <09>Lane 03 nibble 0 raw readback: 005e
1768409.784: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005e
1768509.784: <09>Lane 03 nibble 0 adjusted value (post nibble): 005e
1768609.784: <09>Lane 04 nibble 0 raw readback: 005a
1768709.784: <09>Lane 04 nibble 0 adjusted value (pre nibble): 005a
1768809.784: <09>Lane 04 nibble 0 adjusted value (post nibble): 005a
1768909.784: <09>Lane 05 nibble 0 raw readback: 0062
1769009.784: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0062
1769109.785: <09>Lane 05 nibble 0 adjusted value (post nibble): 0062
1769209.785: <09>Lane 06 nibble 0 raw readback: 0024
1769309.785: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
1769409.785: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
1769509.785: <09>Lane 07 nibble 0 raw readback: 0029
1769609.785: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
1769709.785: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
1769809.785: <09>Lane 08 nibble 0 raw readback: 0052
1769909.785: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0052
1770009.785: <09>Lane 08 nibble 0 adjusted value (post nibble): 0052
1770109.785: AgesaHwWlPhase1: training nibble 1
1770209.785: DIMM 0 RttNom: 4
1770309.785: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1770409.785: DIMM 0 RttWr: 1
1770509.785: DIMM 0 RttWr: 1
1770609.785: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1770709.785: DIMM 0 RttWr: 1
1770809.785: DIMM 0 RttNom: 4
1770909.785: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1771009.785: DIMM 0 RttNom: 4
1771109.785: DIMM 0 RttWr: 1
1771209.785: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1771309.785: DIMM 0 RttWr: 1
1771409.785: DIMM 1 RttNom: 4
1771509.785: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1771609.785: DIMM 0 RttNom: 4
1771709.785: DIMM 1 RttWr: 1
1771809.785: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1771909.785: DIMM 0 RttWr: 1
1772009.785: DIMM 1 RttNom: 4
1772109.785: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1772209.785: DIMM 0 RttNom: 4
1772309.785: DIMM 1 RttWr: 1
1772409.785: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1772509.785: DIMM 0 RttWr: 1
1772609.785: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
1772709.785: <09>Lane 00 new seed: 006c
1772809.785: <09>Lane 01 new seed: 0064
1772909.785: <09>Lane 02 new seed: 005e
1773009.785: <09>Lane 03 new seed: 0059
1773109.785: <09>Lane 04 new seed: 0055
1773209.785: <09>Lane 05 new seed: 005b
1773309.785: <09>Lane 06 new seed: 0061
1773409.785: <09>Lane 07 new seed: 0067
1773509.785: <09>Lane 08 new seed: 0053
1773609.785: <09>Lane 00 nibble 1 raw readback: 0033
1773709.785: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0073
1773809.785: <09>Lane 00 nibble 1 adjusted value (post nibble): 006f
1773909.785: <09>Lane 01 nibble 1 raw readback: 0029
1774009.785: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0069
1774109.785: <09>Lane 01 nibble 1 adjusted value (post nibble): 0066
1774209.785: <09>Lane 02 nibble 1 raw readback: 0061
1774309.785: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
1774409.785: <09>Lane 02 nibble 1 adjusted value (post nibble): 005f
1774509.785: <09>Lane 03 nibble 1 raw readback: 005b
1774609.785: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
1774709.785: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
1774809.785: <09>Lane 04 nibble 1 raw readback: 0059
1774909.785: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0059
1775009.785: <09>Lane 04 nibble 1 adjusted value (post nibble): 0057
1775109.785: <09>Lane 05 nibble 1 raw readback: 005e
1775209.785: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005e
1775309.785: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
1775409.785: <09>Lane 06 nibble 1 raw readback: 0027
1775509.785: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0067
1775609.785: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
1775709.785: <09>Lane 07 nibble 1 raw readback: 002e
1775809.785: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006e
1775909.786: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
1776009.786: <09>Lane 08 nibble 1 raw readback: 0055
1776109.786: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
1776209.786: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
1776309.786: <09>original critical gross delay: 0
1776409.786: <09>new critical gross delay: 0
1776509.786: DIMM 0 RttNom: 4
1776609.786: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1776709.786: DIMM 0 RttNom: 4
1776809.786: DIMM 0 RttWr: 1
1776909.786: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1777009.786: DIMM 0 RttWr: 1
1777109.786: DIMM 0 RttNom: 4
1777209.786: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1777309.786: DIMM 0 RttNom: 4
1777409.786: DIMM 0 RttWr: 1
1777509.786: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1777609.786: DIMM 0 RttWr: 1
1777709.786: DIMM 1 RttNom: 4
1777809.786: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1777909.786: DIMM 0 RttNom: 4
1778009.786: DIMM 1 RttWr: 1
1778109.786: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1778209.786: DIMM 0 RttWr: 1
1778309.786: DIMM 1 RttNom: 4
1778409.786: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1778509.786: DIMM 0 RttNom: 4
1778609.786: DIMM 1 RttWr: 1
1778709.786: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1778809.786: DIMM 0 RttWr: 1
1778909.786: AgesaHwWlPhase1: training nibble 0
1779009.786: DIMM 1 RttNom: 4
1779109.786: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1779209.786: DIMM 1 RttWr: 1
1779309.786: DIMM 1 RttWr: 1
1779409.786: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1779509.786: DIMM 1 RttWr: 1
1779609.786: DIMM 1 RttNom: 4
1779709.786: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1779809.786: DIMM 1 RttNom: 4
1779909.786: DIMM 1 RttWr: 1
1780009.786: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1780109.786: DIMM 1 RttWr: 1
1780209.786: DIMM 0 RttNom: 4
1780309.786: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1780409.786: DIMM 1 RttNom: 4
1780509.786: DIMM 0 RttWr: 1
1780609.786: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1780709.786: DIMM 1 RttWr: 1
1780809.786: DIMM 0 RttNom: 4
1780909.786: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1781009.786: DIMM 1 RttNom: 4
1781109.786: DIMM 0 RttWr: 1
1781209.787: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1781309.786: DIMM 1 RttWr: 1
1781409.786: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1781509.787: <09>Lane 00 scaled delay: 0069
1781609.786: <09>Lane 00 new seed: 0069
1781709.787: <09>Lane 01 scaled delay: 0060
1781809.787: <09>Lane 01 new seed: 0060
1781909.787: <09>Lane 02 scaled delay: 005a
1782009.787: <09>Lane 02 new seed: 005a
1782109.787: <09>Lane 03 scaled delay: 0059
1782209.787: <09>Lane 03 new seed: 0059
1782309.787: <09>Lane 04 scaled delay: 0052
1782409.787: <09>Lane 04 new seed: 0052
1782509.787: <09>Lane 05 scaled delay: 0059
1782609.787: <09>Lane 05 new seed: 0059
1782709.787: <09>Lane 06 scaled delay: 005a
1782809.787: <09>Lane 06 new seed: 005a
1782909.787: <09>Lane 07 scaled delay: 0063
1783009.787: <09>Lane 07 new seed: 0063
1783109.787: <09>Lane 08 scaled delay: 004e
1783209.787: <09>Lane 08 new seed: 004e
1783309.787: <09>Lane 00 nibble 0 raw readback: 002e
1783409.787: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
1783509.787: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
1783609.787: <09>Lane 01 nibble 0 raw readback: 0024
1783709.787: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
1783809.787: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
1783909.787: <09>Lane 02 nibble 0 raw readback: 005c
1784009.787: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005c
1784109.787: <09>Lane 02 nibble 0 adjusted value (post nibble): 005c
1784209.787: <09>Lane 03 nibble 0 raw readback: 005c
1784309.787: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
1784409.787: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
1784509.787: <09>Lane 04 nibble 0 raw readback: 0055
1784609.787: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
1784709.787: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
1784809.787: <09>Lane 05 nibble 0 raw readback: 005c
1784909.787: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005c
1785009.787: <09>Lane 05 nibble 0 adjusted value (post nibble): 005c
1785109.787: <09>Lane 06 nibble 0 raw readback: 005f
1785209.787: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005f
1785309.787: <09>Lane 06 nibble 0 adjusted value (post nibble): 005f
1785409.787: <09>Lane 07 nibble 0 raw readback: 0028
1785509.787: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0068
1785609.787: <09>Lane 07 nibble 0 adjusted value (post nibble): 0068
1785709.787: <09>Lane 08 nibble 0 raw readback: 004f
1785809.787: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004f
1785909.787: <09>Lane 08 nibble 0 adjusted value (post nibble): 004f
1786009.787: AgesaHwWlPhase1: training nibble 1
1786109.787: DIMM 1 RttNom: 4
1786209.787: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1786309.787: DIMM 1 RttWr: 1
1786409.787: DIMM 1 RttWr: 1
1786509.787: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1786609.787: DIMM 1 RttWr: 1
1786709.787: DIMM 1 RttNom: 4
1786809.787: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1786909.787: DIMM 1 RttNom: 4
1787009.787: DIMM 1 RttWr: 1
1787109.787: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1787209.787: DIMM 1 RttWr: 1
1787309.787: DIMM 0 RttNom: 4
1787409.787: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1787509.787: DIMM 1 RttNom: 4
1787609.787: DIMM 0 RttWr: 1
1787709.787: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1787809.787: DIMM 1 RttWr: 1
1787909.787: DIMM 0 RttNom: 4
1788009.787: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1788109.787: DIMM 1 RttNom: 4
1788209.787: DIMM 0 RttWr: 1
1788309.787: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1788409.787: DIMM 1 RttWr: 1
1788509.787: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
1788609.787: <09>Lane 00 new seed: 0069
1788709.787: <09>Lane 01 new seed: 0060
1788809.787: <09>Lane 02 new seed: 005a
1788909.788: <09>Lane 03 new seed: 0059
1789009.788: <09>Lane 04 new seed: 0052
1789109.788: <09>Lane 05 new seed: 0059
1789209.788: <09>Lane 06 new seed: 005a
1789309.788: <09>Lane 07 new seed: 0063
1789409.788: <09>Lane 08 new seed: 004e
1789509.788: <09>Lane 00 nibble 1 raw readback: 002e
1789609.788: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
1789709.788: <09>Lane 00 nibble 1 adjusted value (post nibble): 006b
1789809.788: <09>Lane 01 nibble 1 raw readback: 0025
1789909.788: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
1790009.788: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
1790109.788: <09>Lane 02 nibble 1 raw readback: 005d
1790209.788: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005d
1790309.788: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
1790409.788: <09>Lane 03 nibble 1 raw readback: 005b
1790509.788: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
1790609.788: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
1790709.788: <09>Lane 04 nibble 1 raw readback: 0054
1790809.788: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
1790909.788: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
1791009.788: <09>Lane 05 nibble 1 raw readback: 005c
1791109.788: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
1791209.788: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
1791309.788: <09>Lane 06 nibble 1 raw readback: 005d
1791409.788: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005d
1791509.788: <09>Lane 06 nibble 1 adjusted value (post nibble): 005b
1791609.788: <09>Lane 07 nibble 1 raw readback: 0027
1791709.788: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0067
1791809.788: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
1791909.788: <09>Lane 08 nibble 1 raw readback: 0050
1792009.788: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0050
1792109.788: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
1792209.788: <09>original critical gross delay: 0
1792309.788: <09>new critical gross delay: 0
1792409.788: DIMM 1 RttNom: 4
1792509.788: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
1792609.788: DIMM 1 RttNom: 4
1792709.788: DIMM 1 RttWr: 1
1792809.788: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
1792909.788: DIMM 1 RttWr: 1
1793009.788: DIMM 1 RttNom: 4
1793109.788: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
1793209.788: DIMM 1 RttNom: 4
1793309.788: DIMM 1 RttWr: 1
1793409.788: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
1793509.788: DIMM 1 RttWr: 1
1793609.788: DIMM 0 RttNom: 4
1793709.788: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
1793809.788: DIMM 1 RttNom: 4
1793909.788: DIMM 0 RttWr: 1
1794009.788: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
1794109.788: DIMM 1 RttWr: 1
1794209.788: DIMM 0 RttNom: 4
1794309.788: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
1794409.788: DIMM 1 RttNom: 4
1794509.788: DIMM 0 RttWr: 1
1794609.788: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
1794709.788: DIMM 1 RttWr: 1
1794809.788: SPD2ndTiming: Start
1794909.789: SPD2ndTiming: Done
1795009.789: mct_BeforeDramInit_Prod_D: Start
1795109.789: mct_ProgramODT_D: Start
1795209.789: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
1795309.789: mct_ProgramODT_D: Done
1795409.789: mct_BeforeDramInit_Prod_D: Done
1795509.789: mct_DramInit_Sw_D: Start
1795609.789: DIMM 0 RttWr: 1
1795709.789: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1795809.789: mct_SendMrsCmd: Start
1795909.789: mct_SendMrsCmd: Done
1796009.789: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
1796109.789: mct_SendMrsCmd: Start
1796209.789: mct_SendMrsCmd: Done
1796309.789: DIMM 0 RttNom: 4
1796409.789: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1796509.789: mct_SendMrsCmd: Start
1796609.789: mct_SendMrsCmd: Done
1796709.789: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
1796809.789: mct_SendMrsCmd: Start
1796909.789: mct_SendMrsCmd: Done
1797009.789: DIMM 0 RttWr: 1
1797109.789: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1797209.789: mct_SendMrsCmd: Start
1797309.789: mct_SendMrsCmd: Done
1797409.789: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
1797509.789: mct_SendMrsCmd: Start
1797609.789: mct_SendMrsCmd: Done
1797709.789: DIMM 0 RttNom: 4
1797809.789: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1797909.789: mct_SendMrsCmd: Start
1798009.789: mct_SendMrsCmd: Done
1798109.789: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
1798209.789: mct_SendMrsCmd: Start
1798309.789: mct_SendMrsCmd: Done
1798409.789: DIMM 1 RttWr: 1
1798509.789: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1798609.789: mct_SendMrsCmd: Start
1798709.789: mct_SendMrsCmd: Done
1798809.790: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
1798909.789: mct_SendMrsCmd: Start
1799009.790: mct_SendMrsCmd: Done
1799109.790: DIMM 1 RttNom: 4
1799209.790: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1799309.790: mct_SendMrsCmd: Start
1799409.790: mct_SendMrsCmd: Done
1799509.790: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
1799609.790: mct_SendMrsCmd: Start
1799709.790: mct_SendMrsCmd: Done
1799809.790: DIMM 1 RttWr: 1
1799909.790: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1800009.790: mct_SendMrsCmd: Start
1800109.790: mct_SendMrsCmd: Done
1800209.790: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
1800309.790: mct_SendMrsCmd: Start
1800409.790: mct_SendMrsCmd: Done
1800509.790: DIMM 1 RttNom: 4
1800609.790: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1800709.790: mct_SendMrsCmd: Start
1800809.790: mct_SendMrsCmd: Done
1800909.790: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
1801009.790: mct_SendMrsCmd: Start
1801109.790: mct_SendMrsCmd: Done
1801209.790: mct_DramInit_Sw_D: Done
1801309.790: AgesaHwWlPhase1: training nibble 0
1801409.790: DIMM 0 RttNom: 4
1801509.790: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1801609.790: DIMM 0 RttWr: 1
1801709.790: DIMM 0 RttWr: 1
1801809.790: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1801909.790: DIMM 0 RttWr: 1
1802009.790: DIMM 0 RttNom: 4
1802109.790: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1802209.790: DIMM 0 RttNom: 4
1802309.790: DIMM 0 RttWr: 1
1802409.790: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1802509.790: DIMM 0 RttWr: 1
1802609.790: DIMM 1 RttNom: 4
1802709.790: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1802809.790: DIMM 0 RttNom: 4
1802909.790: DIMM 1 RttWr: 1
1803009.790: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1803109.790: DIMM 0 RttWr: 1
1803209.790: DIMM 1 RttNom: 4
1803309.790: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1803409.790: DIMM 0 RttNom: 4
1803509.790: DIMM 1 RttWr: 1
1803609.790: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1803709.790: DIMM 0 RttWr: 1
1803809.790: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1803909.790: <09>Lane 00 scaled delay: 006d
1804009.790: <09>Lane 00 new seed: 006d
1804109.790: <09>Lane 01 scaled delay: 0067
1804209.790: <09>Lane 01 new seed: 0067
1804309.790: <09>Lane 02 scaled delay: 0061
1804409.790: <09>Lane 02 new seed: 0061
1804509.790: <09>Lane 03 scaled delay: 0059
1804609.790: <09>Lane 03 new seed: 0059
1804709.790: <09>Lane 04 scaled delay: 0055
1804809.790: <09>Lane 04 new seed: 0055
1804909.790: <09>Lane 05 scaled delay: 005e
1805009.790: <09>Lane 05 new seed: 005e
1805109.790: <09>Lane 06 scaled delay: 0064
1805209.791: <09>Lane 06 new seed: 0064
1805309.791: <09>Lane 07 scaled delay: 006a
1805409.791: <09>Lane 07 new seed: 006a
1805509.791: <09>Lane 08 scaled delay: 0054
1805609.791: <09>Lane 08 new seed: 0054
1805709.791: <09>Lane 00 nibble 0 raw readback: 002f
1805809.791: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
1805909.791: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
1806009.791: <09>Lane 01 nibble 0 raw readback: 0027
1806109.791: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
1806209.791: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
1806309.791: <09>Lane 02 nibble 0 raw readback: 0020
1806409.791: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
1806509.791: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
1806609.791: <09>Lane 03 nibble 0 raw readback: 0059
1806709.791: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
1806809.791: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
1806909.791: <09>Lane 04 nibble 0 raw readback: 0057
1807009.791: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
1807109.791: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
1807209.791: <09>Lane 05 nibble 0 raw readback: 0061
1807309.791: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0061
1807409.791: <09>Lane 05 nibble 0 adjusted value (post nibble): 0061
1807509.791: <09>Lane 06 nibble 0 raw readback: 0027
1807609.791: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0067
1807709.791: <09>Lane 06 nibble 0 adjusted value (post nibble): 0067
1807809.791: <09>Lane 07 nibble 0 raw readback: 002e
1807909.791: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006e
1808009.791: <09>Lane 07 nibble 0 adjusted value (post nibble): 006e
1808109.791: <09>Lane 08 nibble 0 raw readback: 0053
1808209.791: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
1808309.791: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
1808409.791: AgesaHwWlPhase1: training nibble 1
1808509.791: DIMM 0 RttNom: 4
1808609.791: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1808709.791: DIMM 0 RttWr: 1
1808809.791: DIMM 0 RttWr: 1
1808909.791: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1809009.791: DIMM 0 RttWr: 1
1809109.791: DIMM 0 RttNom: 4
1809209.791: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1809309.791: DIMM 0 RttNom: 4
1809409.791: DIMM 0 RttWr: 1
1809509.791: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1809609.791: DIMM 0 RttWr: 1
1809709.791: DIMM 1 RttNom: 4
1809809.791: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1809909.791: DIMM 0 RttNom: 4
1810009.791: DIMM 1 RttWr: 1
1810109.791: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1810209.791: DIMM 0 RttWr: 1
1810309.791: DIMM 1 RttNom: 4
1810409.791: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1810509.791: DIMM 0 RttNom: 4
1810609.791: DIMM 1 RttWr: 1
1810709.791: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1810809.791: DIMM 0 RttWr: 1
1810909.791: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
1811009.791: <09>Lane 00 new seed: 006d
1811109.792: <09>Lane 01 new seed: 0067
1811209.792: <09>Lane 02 new seed: 0061
1811309.792: <09>Lane 03 new seed: 0059
1811409.792: <09>Lane 04 new seed: 0055
1811509.792: <09>Lane 05 new seed: 005e
1811609.792: <09>Lane 06 new seed: 0064
1811709.792: <09>Lane 07 new seed: 006a
1811809.792: <09>Lane 08 new seed: 0054
1811909.792: <09>Lane 00 nibble 1 raw readback: 0030
1812009.792: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
1812109.792: <09>Lane 00 nibble 1 adjusted value (post nibble): 006e
1812209.792: <09>Lane 01 nibble 1 raw readback: 002a
1812309.792: <09>Lane 01 nibble 1 adjusted value (pre nibble): 006a
1812409.792: <09>Lane 01 nibble 1 adjusted value (post nibble): 0068
1812509.792: <09>Lane 02 nibble 1 raw readback: 0022
1812609.792: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
1812709.792: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
1812809.792: <09>Lane 03 nibble 1 raw readback: 005b
1812909.792: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
1813009.792: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
1813109.792: <09>Lane 04 nibble 1 raw readback: 0056
1813209.792: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
1813309.792: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
1813409.792: <09>Lane 05 nibble 1 raw readback: 005f
1813509.792: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
1813609.792: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
1813709.792: <09>Lane 06 nibble 1 raw readback: 0026
1813809.792: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
1813909.792: <09>Lane 06 nibble 1 adjusted value (post nibble): 0065
1814009.792: <09>Lane 07 nibble 1 raw readback: 002e
1814109.792: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006e
1814209.792: <09>Lane 07 nibble 1 adjusted value (post nibble): 006c
1814309.792: <09>Lane 08 nibble 1 raw readback: 0055
1814409.792: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
1814509.792: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
1814609.792: <09>original critical gross delay: 0
1814709.792: <09>new critical gross delay: 0
1814809.792: DIMM 0 RttNom: 4
1814909.792: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1815009.792: DIMM 0 RttNom: 4
1815109.792: DIMM 0 RttWr: 1
1815209.792: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1815309.792: DIMM 0 RttWr: 1
1815409.792: DIMM 0 RttNom: 4
1815509.792: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1815609.792: DIMM 0 RttNom: 4
1815709.792: DIMM 0 RttWr: 1
1815809.792: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1815909.792: DIMM 0 RttWr: 1
1816009.792: DIMM 1 RttNom: 4
1816109.792: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1816209.792: DIMM 0 RttNom: 4
1816309.792: DIMM 1 RttWr: 1
1816409.792: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1816509.792: DIMM 0 RttWr: 1
1816609.792: DIMM 1 RttNom: 4
1816709.792: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1816809.792: DIMM 0 RttNom: 4
1816909.792: DIMM 1 RttWr: 1
1817009.792: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1817109.792: DIMM 0 RttWr: 1
1817209.792: AgesaHwWlPhase1: training nibble 0
1817309.792: DIMM 1 RttNom: 4
1817409.793: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1817509.793: DIMM 1 RttWr: 1
1817609.793: DIMM 1 RttWr: 1
1817709.793: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1817809.793: DIMM 1 RttWr: 1
1817909.793: DIMM 1 RttNom: 4
1818009.793: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1818109.793: DIMM 1 RttNom: 4
1818209.793: DIMM 1 RttWr: 1
1818309.793: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1818409.793: DIMM 1 RttWr: 1
1818509.793: DIMM 0 RttNom: 4
1818609.793: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1818709.793: DIMM 1 RttNom: 4
1818809.793: DIMM 0 RttWr: 1
1818909.793: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1819009.793: DIMM 1 RttWr: 1
1819109.793: DIMM 0 RttNom: 4
1819209.793: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1819309.793: DIMM 1 RttNom: 4
1819409.793: DIMM 0 RttWr: 1
1819509.793: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1819609.793: DIMM 1 RttWr: 1
1819709.793: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1819809.793: <09>Lane 00 scaled delay: 006b
1819909.793: <09>Lane 00 new seed: 006b
1820009.793: <09>Lane 01 scaled delay: 0064
1820109.793: <09>Lane 01 new seed: 0064
1820209.793: <09>Lane 02 scaled delay: 005b
1820309.793: <09>Lane 02 new seed: 005b
1820409.793: <09>Lane 03 scaled delay: 0059
1820509.793: <09>Lane 03 new seed: 0059
1820609.793: <09>Lane 04 scaled delay: 0053
1820709.793: <09>Lane 04 new seed: 0053
1820809.793: <09>Lane 05 scaled delay: 005b
1820909.793: <09>Lane 05 new seed: 005b
1821009.793: <09>Lane 06 scaled delay: 0063
1821109.793: <09>Lane 06 new seed: 0063
1821209.793: <09>Lane 07 scaled delay: 0069
1821309.793: <09>Lane 07 new seed: 0069
1821409.793: <09>Lane 08 scaled delay: 004f
1821509.793: <09>Lane 08 new seed: 004f
1821609.793: <09>Lane 00 nibble 0 raw readback: 002d
1821709.793: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006d
1821809.793: <09>Lane 00 nibble 0 adjusted value (post nibble): 006d
1821909.793: <09>Lane 01 nibble 0 raw readback: 0025
1822009.793: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
1822109.793: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
1822209.793: <09>Lane 02 nibble 0 raw readback: 005b
1822309.793: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005b
1822409.793: <09>Lane 02 nibble 0 adjusted value (post nibble): 005b
1822509.793: <09>Lane 03 nibble 0 raw readback: 0057
1822609.793: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0057
1822709.793: <09>Lane 03 nibble 0 adjusted value (post nibble): 0057
1822809.793: <09>Lane 04 nibble 0 raw readback: 0054
1822909.793: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0054
1823009.793: <09>Lane 04 nibble 0 adjusted value (post nibble): 0054
1823109.793: <09>Lane 05 nibble 0 raw readback: 005e
1823209.793: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
1823309.793: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
1823409.793: <09>Lane 06 nibble 0 raw readback: 0025
1823509.793: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
1823609.793: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
1823709.793: <09>Lane 07 nibble 0 raw readback: 002b
1823809.793: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
1823909.793: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
1824009.793: <09>Lane 08 nibble 0 raw readback: 0053
1824109.793: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
1824209.793: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
1824309.793: AgesaHwWlPhase1: training nibble 1
1824409.793: DIMM 1 RttNom: 4
1824509.793: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1824609.793: DIMM 1 RttWr: 1
1824709.794: DIMM 1 RttWr: 1
1824809.794: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1824909.794: DIMM 1 RttWr: 1
1825009.794: DIMM 1 RttNom: 4
1825109.794: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1825209.794: DIMM 1 RttNom: 4
1825309.794: DIMM 1 RttWr: 1
1825409.794: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1825509.794: DIMM 1 RttWr: 1
1825609.794: DIMM 0 RttNom: 4
1825709.794: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1825809.794: DIMM 1 RttNom: 4
1825909.794: DIMM 0 RttWr: 1
1826009.794: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1826109.794: DIMM 1 RttWr: 1
1826209.794: DIMM 0 RttNom: 4
1826309.794: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1826409.794: DIMM 1 RttNom: 4
1826509.794: DIMM 0 RttWr: 1
1826609.794: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1826709.794: DIMM 1 RttWr: 1
1826809.794: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
1826909.794: <09>Lane 00 new seed: 006b
1827009.794: <09>Lane 01 new seed: 0064
1827109.794: <09>Lane 02 new seed: 005b
1827209.794: <09>Lane 03 new seed: 0059
1827309.794: <09>Lane 04 new seed: 0053
1827409.794: <09>Lane 05 new seed: 005b
1827509.794: <09>Lane 06 new seed: 0063
1827609.794: <09>Lane 07 new seed: 0069
1827709.794: <09>Lane 08 new seed: 004f
1827809.794: <09>Lane 00 nibble 1 raw readback: 002e
1827909.794: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
1828009.794: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
1828109.794: <09>Lane 01 nibble 1 raw readback: 0028
1828209.794: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0068
1828309.794: <09>Lane 01 nibble 1 adjusted value (post nibble): 0066
1828409.794: <09>Lane 02 nibble 1 raw readback: 005c
1828509.794: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005c
1828609.794: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
1828709.794: <09>Lane 03 nibble 1 raw readback: 0059
1828809.794: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
1828909.794: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
1829009.794: <09>Lane 04 nibble 1 raw readback: 0054
1829109.794: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
1829209.794: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
1829309.794: <09>Lane 05 nibble 1 raw readback: 005d
1829409.794: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005d
1829509.794: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
1829609.794: <09>Lane 06 nibble 1 raw readback: 0026
1829709.794: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
1829809.794: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
1829909.794: <09>Lane 07 nibble 1 raw readback: 002b
1830009.794: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
1830109.794: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
1830209.794: <09>Lane 08 nibble 1 raw readback: 0051
1830309.794: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0051
1830409.794: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
1830509.794: <09>original critical gross delay: 0
1830609.794: <09>new critical gross delay: 0
1830709.794: DIMM 1 RttNom: 4
1830809.794: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
1830909.794: DIMM 1 RttNom: 4
1831009.795: DIMM 1 RttWr: 1
1831109.794: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
1831209.794: DIMM 1 RttWr: 1
1831309.795: DIMM 1 RttNom: 4
1831409.795: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
1831509.795: DIMM 1 RttNom: 4
1831609.795: DIMM 1 RttWr: 1
1831709.795: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
1831809.795: DIMM 1 RttWr: 1
1831909.795: DIMM 0 RttNom: 4
1832009.795: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
1832109.795: DIMM 1 RttNom: 4
1832209.795: DIMM 0 RttWr: 1
1832309.795: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
1832409.795: DIMM 1 RttWr: 1
1832509.795: DIMM 0 RttNom: 4
1832609.795: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
1832709.795: DIMM 1 RttNom: 4
1832809.795: DIMM 0 RttWr: 1
1832909.795: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
1833009.795: DIMM 1 RttWr: 1
1833109.796: fam15_receiver_enable_training_seed: using seed: 0054
1833209.796: fam15_receiver_enable_training_seed: using seed: 0054
1833309.796: fam15_receiver_enable_training_seed: using seed: 0054
1833409.796: fam15_receiver_enable_training_seed: using seed: 0054
1833509.796: fam15_receiver_enable_training_seed: using seed: 0054
1833609.796: fam15_receiver_enable_training_seed: using seed: 0054
1833709.796: fam15_receiver_enable_training_seed: using seed: 0054
1833809.796: fam15_receiver_enable_training_seed: using seed: 0054
1833909.796: fam15_receiver_enable_training_seed: using seed: 004d
1834009.796: fam15_receiver_enable_training_seed: using seed: 004d
1834109.797: fam15_receiver_enable_training_seed: using seed: 004d
1834209.797: fam15_receiver_enable_training_seed: using seed: 004d
1834309.797: fam15_receiver_enable_training_seed: using seed: 004d
1834409.797: fam15_receiver_enable_training_seed: using seed: 004d
1834509.797: fam15_receiver_enable_training_seed: using seed: 004d
1834609.797: fam15_receiver_enable_training_seed: using seed: 004d
1834709.797: TrainRcvrEn: Status 2205
1834809.797: TrainRcvrEn: ErrStatus 0
1834909.797: TrainRcvrEn: ErrCode 0
1835009.797: TrainRcvrEn: Done
1835109.797:
1835209.797: fam15_receiver_enable_training_seed: using seed: 0045
1835309.797: fam15_receiver_enable_training_seed: using seed: 0045
1835409.797: fam15_receiver_enable_training_seed: using seed: 0045
1835509.797: fam15_receiver_enable_training_seed: using seed: 0045
1835609.798: fam15_receiver_enable_training_seed: using seed: 0045
1835709.798: fam15_receiver_enable_training_seed: using seed: 0045
1835809.798: fam15_receiver_enable_training_seed: using seed: 0045
1835909.798: fam15_receiver_enable_training_seed: using seed: 0045
1836009.798: fam15_receiver_enable_training_seed: using seed: 0040
1836109.798: fam15_receiver_enable_training_seed: using seed: 0040
1836209.798: fam15_receiver_enable_training_seed: using seed: 0040
1836309.798: fam15_receiver_enable_training_seed: using seed: 0040
1836409.798: fam15_receiver_enable_training_seed: using seed: 0040
1836509.798: fam15_receiver_enable_training_seed: using seed: 0040
1836609.798: fam15_receiver_enable_training_seed: using seed: 0040
1836709.798: fam15_receiver_enable_training_seed: using seed: 0040
1836809.799: TrainRcvrEn: Status 2005
1836909.799: TrainRcvrEn: ErrStatus 0
1837009.799: TrainRcvrEn: ErrCode 0
1837109.799: TrainRcvrEn: Done
1837209.799:
1837309.799: fam15_receiver_enable_training_seed: using seed: 0054
1837409.799: fam15_receiver_enable_training_seed: using seed: 0054
1837509.799: fam15_receiver_enable_training_seed: using seed: 0054
1837609.799: fam15_receiver_enable_training_seed: using seed: 0054
1837709.799: fam15_receiver_enable_training_seed: using seed: 0054
1837809.799: fam15_receiver_enable_training_seed: using seed: 0054
1837909.799: fam15_receiver_enable_training_seed: using seed: 0054
1838009.799: fam15_receiver_enable_training_seed: using seed: 0054
1838109.800: fam15_receiver_enable_training_seed: using seed: 004d
1838209.800: fam15_receiver_enable_training_seed: using seed: 004d
1838309.800: fam15_receiver_enable_training_seed: using seed: 004d
1838409.800: fam15_receiver_enable_training_seed: using seed: 004d
1838509.800: fam15_receiver_enable_training_seed: using seed: 004d
1838609.800: fam15_receiver_enable_training_seed: using seed: 004d
1838709.800: fam15_receiver_enable_training_seed: using seed: 004d
1838809.800: fam15_receiver_enable_training_seed: using seed: 004d
1838909.800: TrainRcvrEn: Status 2005
1839009.800: TrainRcvrEn: ErrStatus 0
1839109.800: TrainRcvrEn: ErrCode 0
1839209.800: TrainRcvrEn: Done
1839309.800:
1839409.800: fam15_receiver_enable_training_seed: using seed: 0045
1839509.801: fam15_receiver_enable_training_seed: using seed: 0045
1839609.801: fam15_receiver_enable_training_seed: using seed: 0045
1839709.801: fam15_receiver_enable_training_seed: using seed: 0045
1839809.801: fam15_receiver_enable_training_seed: using seed: 0045
1839909.801: fam15_receiver_enable_training_seed: using seed: 0045
1840009.801: fam15_receiver_enable_training_seed: using seed: 0045
1840109.801: fam15_receiver_enable_training_seed: using seed: 0045
1840209.801: fam15_receiver_enable_training_seed: using seed: 0040
1840309.801: fam15_receiver_enable_training_seed: using seed: 0040
1840409.801: fam15_receiver_enable_training_seed: using seed: 0040
1840509.801: fam15_receiver_enable_training_seed: using seed: 0040
1840609.802: fam15_receiver_enable_training_seed: using seed: 0040
1840709.802: fam15_receiver_enable_training_seed: using seed: 0040
1840809.802: fam15_receiver_enable_training_seed: using seed: 0040
1840909.802: fam15_receiver_enable_training_seed: using seed: 0040
1841009.802: TrainRcvrEn: Status 2005
1841109.802: TrainRcvrEn: ErrStatus 0
1841209.802: TrainRcvrEn: ErrCode 0
1841309.802: TrainRcvrEn: Done
1841409.802:
1841519.758: TrainDQSReceiverEnCyc: Status 2205
1841619.758: TrainDQSReceiverEnCyc: TrainErrors 4000
1841719.758: TrainDQSReceiverEnCyc: ErrStatus 4000
1841819.758: TrainDQSReceiverEnCyc: ErrCode 0
1841919.758: TrainDQSReceiverEnCyc: Done
1842019.758:
1842130.849: TrainDQSReceiverEnCyc: Status 2005
1842230.849: TrainDQSReceiverEnCyc: TrainErrors 4000
1842330.849: TrainDQSReceiverEnCyc: ErrStatus 4000
1842430.849: TrainDQSReceiverEnCyc: ErrCode 0
1842530.849: TrainDQSReceiverEnCyc: Done
1842630.849:
1842744.196: TrainDQSReceiverEnCyc: Status 2005
1842844.196: TrainDQSReceiverEnCyc: TrainErrors 4000
1842944.196: TrainDQSReceiverEnCyc: ErrStatus 4000
1843044.196: TrainDQSReceiverEnCyc: ErrCode 0
1843144.196: TrainDQSReceiverEnCyc: Done
1843244.196:
1843356.920: TrainDQSReceiverEnCyc: Status 2005
1843456.920: TrainDQSReceiverEnCyc: TrainErrors 4000
1843556.919: TrainDQSReceiverEnCyc: ErrStatus 4000
1843656.920: TrainDQSReceiverEnCyc: ErrCode 0
1843756.920: TrainDQSReceiverEnCyc: Done
1843856.920:
1843956.920: TrainMaxRdLatency: Status 2205
1844056.921: TrainMaxRdLatency: ErrStatus 4000
1844156.921: TrainMaxRdLatency: ErrCode 0
1844256.921: TrainMaxRdLatency: Done
1844356.921:
1844456.921: TrainMaxRdLatency: Status 2005
1844556.921: TrainMaxRdLatency: ErrStatus 4000
1844656.921: TrainMaxRdLatency: ErrCode 0
1844756.921: TrainMaxRdLatency: Done
1844856.921:
1844956.922: TrainMaxRdLatency: Status 2005
1845056.922: TrainMaxRdLatency: ErrStatus 4000
1845156.922: TrainMaxRdLatency: ErrCode 0
1845256.922: TrainMaxRdLatency: Done
1845356.922:
1845456.923: TrainMaxRdLatency: Status 2005
1845556.923: TrainMaxRdLatency: ErrStatus 4000
1845656.923: TrainMaxRdLatency: ErrCode 0
1845756.923: TrainMaxRdLatency: Done
1845856.923:
1845956.924: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1846056.924: CBFS: Locating 'cmos_layout.bin'
1846156.924: CBFS: Found @ offset 2b0c0 size e88
1846256.925: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1846356.925: CBFS: Locating 'cmos_layout.bin'
1846456.925: CBFS: Found @ offset 2b0c0 size e88
1846556.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1846656.926: CBFS: Locating 'cmos_layout.bin'
1846756.926: CBFS: Found @ offset 2b0c0 size e88
1846856.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1846956.926: CBFS: Locating 'cmos_layout.bin'
1847056.926: CBFS: Found @ offset 2b0c0 size e88
1847156.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1847256.926: CBFS: Locating 'cmos_layout.bin'
1847356.926: CBFS: Found @ offset 2b0c0 size e88
1847456.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1847556.927: CBFS: Locating 'cmos_layout.bin'
1847656.927: CBFS: Found @ offset 2b0c0 size e88
1847756.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1847856.927: CBFS: Locating 'cmos_layout.bin'
1847956.927: CBFS: Found @ offset 2b0c0 size e88
1848056.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1848156.927: CBFS: Locating 'cmos_layout.bin'
1848256.927: CBFS: Found @ offset 2b0c0 size e88
1848356.928: mctAutoInitMCT_D: :OtherTiming
1848456.929: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1848556.929: CBFS: Locating 'cmos_layout.bin'
1848656.929: CBFS: Found @ offset 2b0c0 size e88
1848756.929: InterleaveNodes_D: Status 2205
1848856.929: InterleaveNodes_D: ErrStatus 4000
1848956.929: InterleaveNodes_D: ErrCode 0
1849056.929: InterleaveNodes_D: Done
1849156.929:
1849256.929: InterleaveChannels_D: Node 0
1849356.929: InterleaveChannels_D: Status 2205
1849456.929: InterleaveChannels_D: ErrStatus 4000
1849556.929: InterleaveChannels_D: ErrCode 0
1849656.930: InterleaveChannels_D: Node 1
1849756.930: InterleaveChannels_D: Status 2005
1849856.930: InterleaveChannels_D: ErrStatus 4000
1849956.930: InterleaveChannels_D: ErrCode 0
1850056.930: InterleaveChannels_D: Node 2
1850156.930: InterleaveChannels_D: Status 2005
1850256.930: InterleaveChannels_D: ErrStatus 4000
1850356.930: InterleaveChannels_D: ErrCode 0
1850456.930: InterleaveChannels_D: Node 3
1850556.930: InterleaveChannels_D: Status 2005
1850656.930: InterleaveChannels_D: ErrStatus 4000
1850756.930: InterleaveChannels_D: ErrCode 0
1850856.930: InterleaveChannels_D: Node 4
1850956.930: InterleaveChannels_D: Status 2000
1851056.930: InterleaveChannels_D: ErrStatus 0
1851156.930: InterleaveChannels_D: ErrCode 0
1851256.930: InterleaveChannels_D: Node 5
1851356.930: InterleaveChannels_D: Status 2000
1851456.930: InterleaveChannels_D: ErrStatus 0
1851556.930: InterleaveChannels_D: ErrCode 0
1851656.930: InterleaveChannels_D: Node 6
1851756.930: InterleaveChannels_D: Status 2000
1851856.930: InterleaveChannels_D: ErrStatus 0
1851956.930: InterleaveChannels_D: ErrCode 0
1852056.930: InterleaveChannels_D: Node 7
1852156.930: InterleaveChannels_D: Status 2000
1852256.930: InterleaveChannels_D: ErrStatus 0
1852356.930: InterleaveChannels_D: ErrCode 0
1852456.930: InterleaveChannels_D: Done
1852556.930:
1852656.930: mctAutoInitMCT_D: ECCInit_D
1852756.930: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1852856.930: CBFS: Locating 'cmos_layout.bin'
1852956.930: CBFS: Found @ offset 2b0c0 size e88
1853056.931: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1853156.931: CBFS: Locating 'cmos_layout.bin'
1853256.931: CBFS: Found @ offset 2b0c0 size e88
1853356.931: ECC enabled on node: 00
1853456.931: DCTMemClr_Sync_D: Start
1853556.931: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
1853657.910: .
1853757.910: DCTMemClr_Sync_D: Done
1853857.910: ECC enabled on node: 01
1853957.910: DCTMemClr_Sync_D: Start
1854057.910: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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1854158.889: .
1854258.889: DCTMemClr_Sync_D: Done
1854358.889: ECC enabled on node: 02
1854458.889: DCTMemClr_Sync_D: Start
1854558.889: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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1854659.868: .
1854759.868: DCTMemClr_Sync_D: Done
1854859.868: ECC enabled on node: 03
1854959.868: DCTMemClr_Sync_D: Start
1855059.868: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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1855160.847: .
1855260.847: DCTMemClr_Sync_D: Done
1855360.847: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1855460.847: CBFS: Locating 'cmos_layout.bin'
1855560.847: CBFS: Found @ offset 2b0c0 size e88
1855660.847: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1855760.847: CBFS: Locating 'cmos_layout.bin'
1855860.847: CBFS: Found @ offset 2b0c0 size e88
1855960.848: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1856060.847: CBFS: Locating 'cmos_layout.bin'
1856160.848: CBFS: Found @ offset 2b0c0 size e88
1856260.848: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1856360.848: CBFS: Locating 'cmos_layout.bin'
1856460.848: CBFS: Found @ offset 2b0c0 size e88
1856560.848: ECCInit: Node 00
1856660.848: ECCInit: Status 2205
1856760.848: ECCInit: ErrStatus 4000
1856860.848: ECCInit: ErrCode 0
1856960.848: ECCInit: Done
1857060.848: ECCInit: Node 01
1857160.848: ECCInit: Status 2005
1857260.848: ECCInit: ErrStatus 4000
1857360.848: ECCInit: ErrCode 0
1857460.848: ECCInit: Done
1857560.848: ECCInit: Node 02
1857660.848: ECCInit: Status 2005
1857760.848: ECCInit: ErrStatus 4000
1857860.848: ECCInit: ErrCode 0
1857960.848: ECCInit: Done
1858060.848: ECCInit: Node 03
1858160.848: ECCInit: Status 2005
1858260.848: ECCInit: ErrStatus 4000
1858360.848: ECCInit: ErrCode 0
1858460.848: ECCInit: Done
1858560.848: mctAutoInitMCT_D: CPUMemTyping_D
1858660.849: <09> CPUMemTyping: Cache32bTOP:c00000
1858760.849: <09> CPUMemTyping: Bottom32bIO:c00000
1858860.849: <09> CPUMemTyping: Bottom40bIO:40400000
1858960.849: mctAutoInitMCT_D: UMAMemTyping_D
1859060.849: mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
1859160.849: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1859260.849: CBFS: Locating 'cmos_layout.bin'
1859360.849: CBFS: Found @ offset 2b0c0 size e88
1859460.849: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 0 (interleaved: 0)
1859560.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 103fffffff
1859660.850: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
1859760.850: set_up_cc6_storage_fam15:<09>Target node: 3
1859860.850: set_up_cc6_storage_fam15:<09>Done
1859960.850: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 1 (interleaved: 0)
1860060.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 203fffffff
1860160.850: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
1860260.850: set_up_cc6_storage_fam15:<09>Target node: 3
1860360.850: set_up_cc6_storage_fam15:<09>Done
1860460.850: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 2 (interleaved: 0)
1860560.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 303fffffff
1860660.850: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
1860760.850: set_up_cc6_storage_fam15:<09>Target node: 3
1860860.850: set_up_cc6_storage_fam15:<09>Done
1860960.850: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 3 (interleaved: 0)
1861060.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 403fffffff
1861160.850: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
1861260.850: set_up_cc6_storage_fam15:<09>Target node: 3
1861360.850: set_up_cc6_storage_fam15:<09>Done
1861460.850: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1861560.850: CBFS: Locating 'cmos_layout.bin'
1861660.850: CBFS: Found @ offset 2b0c0 size e88
1861760.851: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1861860.851: CBFS: Locating 'cmos_layout.bin'
1861960.851: CBFS: Found @ offset 2b0c0 size e88
1862060.851: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1862160.851: CBFS: Locating 'cmos_layout.bin'
1862260.851: CBFS: Found @ offset 2b0c0 size e88
1862360.851: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1862460.851: CBFS: Locating 'cmos_layout.bin'
1862560.851: CBFS: Found @ offset 2b0c0 size e88
1862660.851: mctAutoInitMCT_D Done: Global Status: 12
1862760.851: raminit_amdmct end:
1862860.852: CBMEM:
1862960.852: IMD: root @ b7fff000 254 entries.
1863060.852: IMD: root @ b7ffec00 62 entries.
1863160.853: amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
1863260.853: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1863360.853: CBFS: Locating 'cmos_layout.bin'
1863460.854: CBFS: Found @ offset 2b0c0 size e88
1863560.854: disable_spd()
1863660.980: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1863760.981: CBFS: Locating 'fallback/ramstage'
1863860.981: CBFS: Found @ offset 3ff00 size 1544c
1863961.025: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1864061.025: CBFS: Locating 'cmos_layout.bin'
1864161.025: CBFS: Found @ offset 2b0c0 size e88
1864261.025: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1864361.025: CBFS: Locating 'cmos_layout.bin'
1864461.025: CBFS: Found @ offset 2b0c0 size e88
1864561.025:
1864661.025:
1864761.025: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 ramstage starting...
1864861.025: Moving GDT to b7ffe9e0...ok
1864961.025: Normal boot.
1865061.025: BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
1865161.025: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
1865261.025: Enumerating buses...
1865361.025: Show all devs... Before device enumeration.
1865461.025: Root Device: enabled 1
1865561.025: CPU_CLUSTER: 0: enabled 1
1865661.025: APIC: 00: enabled 1
1865761.025: DOMAIN: 0000: enabled 1
1865861.025: PCI: 00:18.0: enabled 1
1865961.025: PCI: 00:00.0: enabled 1
1866061.025: PCI: 00:00.1: enabled 1
1866161.025: PCI: 00:00.2: enabled 1
1866261.025: PCI: 00:02.0: enabled 1
1866361.025: PCI: 00:03.0: enabled 0
1866461.025: PCI: 00:04.0: enabled 1
1866561.025: PCI: 00:05.0: enabled 0
1866661.025: PCI: 00:06.0: enabled 0
1866761.025: PCI: 00:07.0: enabled 0
1866861.025: PCI: 00:08.0: enabled 0
1866961.025: PCI: 00:09.0: enabled 1
1867061.026: PCI: 00:0a.0: enabled 1
1867161.026: PCI: 00:0b.0: enabled 1
1867261.026: PCI: 00:0c.0: enabled 1
1867361.026: PCI: 00:0d.0: enabled 1
1867461.026: PCI: 00:11.0: enabled 1
1867561.026: PCI: 00:12.0: enabled 1
1867661.026: PCI: 00:12.1: enabled 1
1867761.026: PCI: 00:12.2: enabled 1
1867861.026: PCI: 00:13.0: enabled 1
1867961.026: PCI: 00:13.1: enabled 1
1868061.026: PCI: 00:13.2: enabled 1
1868161.026: PCI: 00:14.0: enabled 1
1868261.026: I2C: 00:50: enabled 1
1868361.026: I2C: 00:51: enabled 1
1868461.026: I2C: 00:52: enabled 1
1868561.026: I2C: 00:53: enabled 1
1868661.026: I2C: 00:54: enabled 1
1868761.026: I2C: 00:55: enabled 1
1868861.026: I2C: 00:56: enabled 1
1868961.026: I2C: 00:57: enabled 1
1869061.026: I2C: 00:2f: enabled 1
1869161.026: PCI: 00:14.1: enabled 1
1869261.026: PCI: 00:14.2: enabled 1
1869361.026: PCI: 00:14.3: enabled 1
1869461.026: PNP: 002e.0: enabled 0
1869561.026: PNP: 002e.1: enabled 0
1869661.026: PNP: 002e.2: enabled 1
1869761.026: PNP: 002e.3: enabled 1
1869861.026: PNP: 002e.5: enabled 1
1869961.026: PNP: 002e.106: enabled 0
1870061.026: PNP: 002e.107: enabled 0
1870161.026: PNP: 002e.207: enabled 0
1870261.026: PNP: 002e.307: enabled 0
1870361.026: PNP: 002e.407: enabled 0
1870461.026: PNP: 002e.8: enabled 0
1870561.026: PNP: 002e.108: enabled 0
1870661.026: PNP: 002e.9: enabled 0
1870761.026: PNP: 002e.109: enabled 0
1870861.026: PNP: 002e.209: enabled 0
1870961.026: PNP: 002e.309: enabled 0
1871061.026: PNP: 002e.a: enabled 1
1871161.026: PNP: 002e.b: enabled 1
1871261.026: PNP: 002e.c: enabled 0
1871361.026: PNP: 002e.d: enabled 0
1871461.026: PNP: 002e.f: enabled 0
1871561.026: PNP: 004e.0: enabled 1
1871661.026: PCI: 00:14.4: enabled 1
1871761.026: PCI: 00:01.0: enabled 1
1871861.026: PCI: 00:02.0: enabled 1
1871961.026: PCI: 00:03.0: enabled 1
1872061.026: PCI: 00:14.5: enabled 1
1872161.026: PCI: 00:18.1: enabled 1
1872261.026: PCI: 00:18.2: enabled 1
1872361.026: PCI: 00:18.3: enabled 1
1872461.026: PCI: 00:18.4: enabled 1
1872561.026: PCI: 00:18.5: enabled 1
1872661.026: PCI: 00:19.0: enabled 1
1872761.026: PCI: 00:19.1: enabled 1
1872861.026: PCI: 00:19.2: enabled 1
1872961.026: PCI: 00:19.3: enabled 1
1873061.026: PCI: 00:19.4: enabled 1
1873161.026: PCI: 00:19.5: enabled 1
1873261.026: PCI: 00:1a.0: enabled 1
1873361.026: PCI: 00:1a.1: enabled 1
1873461.026: PCI: 00:1a.2: enabled 1
1873561.026: PCI: 00:1a.3: enabled 1
1873661.026: PCI: 00:1a.4: enabled 1
1873761.026: PCI: 00:1a.5: enabled 1
1873861.026: PCI: 00:1b.0: enabled 1
1873961.026: PCI: 00:1b.1: enabled 1
1874061.027: PCI: 00:1b.2: enabled 1
1874161.026: PCI: 00:1b.3: enabled 1
1874261.027: PCI: 00:1b.4: enabled 1
1874361.027: PCI: 00:1b.5: enabled 1
1874461.027: Compare with tree...
1874561.027: Root Device: enabled 1
1874661.027: CPU_CLUSTER: 0: enabled 1
1874761.027: APIC: 00: enabled 1
1874861.027: DOMAIN: 0000: enabled 1
1874961.027: PCI: 00:18.0: enabled 1
1875061.027: PCI: 00:00.0: enabled 1
1875161.027: PCI: 00:00.1: enabled 1
1875261.027: PCI: 00:00.2: enabled 1
1875361.027: PCI: 00:02.0: enabled 1
1875461.027: PCI: 00:03.0: enabled 0
1875561.027: PCI: 00:04.0: enabled 1
1875661.027: PCI: 00:05.0: enabled 0
1875761.027: PCI: 00:06.0: enabled 0
1875861.027: PCI: 00:07.0: enabled 0
1875961.027: PCI: 00:08.0: enabled 0
1876061.027: PCI: 00:09.0: enabled 1
1876161.027: PCI: 00:0a.0: enabled 1
1876261.027: PCI: 00:0b.0: enabled 1
1876361.027: PCI: 00:0c.0: enabled 1
1876461.027: PCI: 00:0d.0: enabled 1
1876561.027: PCI: 00:11.0: enabled 1
1876661.027: PCI: 00:12.0: enabled 1
1876761.027: PCI: 00:12.1: enabled 1
1876861.027: PCI: 00:12.2: enabled 1
1876961.027: PCI: 00:13.0: enabled 1
1877061.027: PCI: 00:13.1: enabled 1
1877161.027: PCI: 00:13.2: enabled 1
1877261.027: PCI: 00:14.0: enabled 1
1877361.027: I2C: 00:50: enabled 1
1877461.027: I2C: 00:51: enabled 1
1877561.027: I2C: 00:52: enabled 1
1877661.027: I2C: 00:53: enabled 1
1877761.027: I2C: 00:54: enabled 1
1877861.027: I2C: 00:55: enabled 1
1877961.027: I2C: 00:56: enabled 1
1878061.027: I2C: 00:57: enabled 1
1878161.027: I2C: 00:2f: enabled 1
1878261.027: PCI: 00:14.1: enabled 1
1878361.027: PCI: 00:14.2: enabled 1
1878461.027: PCI: 00:14.3: enabled 1
1878561.027: PNP: 002e.0: enabled 0
1878661.027: PNP: 002e.1: enabled 0
1878761.027: PNP: 002e.2: enabled 1
1878861.027: PNP: 002e.3: enabled 1
1878961.027: PNP: 002e.5: enabled 1
1879061.027: PNP: 002e.106: enabled 0
1879161.027: PNP: 002e.107: enabled 0
1879261.027: PNP: 002e.207: enabled 0
1879361.027: PNP: 002e.307: enabled 0
1879461.027: PNP: 002e.407: enabled 0
1879561.027: PNP: 002e.8: enabled 0
1879661.027: PNP: 002e.108: enabled 0
1879761.027: PNP: 002e.9: enabled 0
1879861.027: PNP: 002e.109: enabled 0
1879961.027: PNP: 002e.209: enabled 0
1880061.027: PNP: 002e.309: enabled 0
1880161.027: PNP: 002e.a: enabled 1
1880261.027: PNP: 002e.b: enabled 1
1880361.027: PNP: 002e.c: enabled 0
1880461.027: PNP: 002e.d: enabled 0
1880561.027: PNP: 002e.f: enabled 0
1880661.027: PNP: 004e.0: enabled 1
1880761.027: PCI: 00:14.4: enabled 1
1880861.027: PCI: 00:01.0: enabled 1
1880961.027: PCI: 00:02.0: enabled 1
1881061.027: PCI: 00:03.0: enabled 1
1881161.027: PCI: 00:14.5: enabled 1
1881261.027: PCI: 00:18.1: enabled 1
1881361.028: PCI: 00:18.2: enabled 1
1881461.027: PCI: 00:18.3: enabled 1
1881561.028: PCI: 00:18.4: enabled 1
1881661.028: PCI: 00:18.5: enabled 1
1881761.028: PCI: 00:19.0: enabled 1
1881861.028: PCI: 00:19.1: enabled 1
1881961.028: PCI: 00:19.2: enabled 1
1882061.028: PCI: 00:19.3: enabled 1
1882161.028: PCI: 00:19.4: enabled 1
1882261.028: PCI: 00:19.5: enabled 1
1882361.028: PCI: 00:1a.0: enabled 1
1882461.028: PCI: 00:1a.1: enabled 1
1882561.028: PCI: 00:1a.2: enabled 1
1882661.028: PCI: 00:1a.3: enabled 1
1882761.028: PCI: 00:1a.4: enabled 1
1882861.028: PCI: 00:1a.5: enabled 1
1882961.028: PCI: 00:1b.0: enabled 1
1883061.028: PCI: 00:1b.1: enabled 1
1883161.028: PCI: 00:1b.2: enabled 1
1883261.028: PCI: 00:1b.3: enabled 1
1883361.028: PCI: 00:1b.4: enabled 1
1883461.028: PCI: 00:1b.5: enabled 1
1883561.028: Mainboard KGPE-D16 Enable. dev=0x0012cbe0
1883661.028: mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
1883761.028: mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000040
1883861.028: Root Device scanning...
1883961.028: root_dev_scan_bus for Root Device
1884061.028: setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
1884161.028: setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000040
1884261.028: CPU_CLUSTER: 0 enabled
1884361.028: DOMAIN: 0000 enabled
1884461.028: CPU_CLUSTER: 0 scanning...
1884561.028: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1884661.028: CBFS: Locating 'cmos_layout.bin'
1884761.028: CBFS: Found @ offset 2b0c0 size e88
1884861.028: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1884961.028: CBFS: Locating 'cmos_layout.bin'
1885061.028: CBFS: Found @ offset 2b0c0 size e88
1885161.029: PCI: 00:18.5 siblings=7
1885261.029: CPU: APIC: 00 enabled
1885361.029: CPU: APIC: 01 enabled
1885461.029: CPU: APIC: 02 enabled
1885561.029: CPU: APIC: 03 enabled
1885661.029: CPU: APIC: 04 enabled
1885761.029: CPU: APIC: 05 enabled
1885861.029: CPU: APIC: 06 enabled
1885961.029: CPU: APIC: 07 enabled
1886061.029: PCI: 00:19.5 siblings=7
1886161.029: CPU: APIC: 08 enabled
1886261.029: CPU: APIC: 09 enabled
1886361.029: CPU: APIC: 0a enabled
1886461.029: CPU: APIC: 0b enabled
1886561.029: CPU: APIC: 0c enabled
1886661.029: CPU: APIC: 0d enabled
1886761.029: CPU: APIC: 0e enabled
1886861.029: CPU: APIC: 0f enabled
1886961.029: PCI: 00:1a.5 siblings=7
1887061.029: CPU: APIC: 20 enabled
1887161.029: CPU: APIC: 21 enabled
1887261.029: CPU: APIC: 22 enabled
1887361.029: CPU: APIC: 23 enabled
1887461.029: CPU: APIC: 24 enabled
1887561.029: CPU: APIC: 25 enabled
1887661.029: CPU: APIC: 26 enabled
1887761.029: CPU: APIC: 27 enabled
1887861.029: PCI: 00:1b.5 siblings=7
1887961.029: CPU: APIC: 28 enabled
1888061.029: CPU: APIC: 29 enabled
1888161.029: CPU: APIC: 2a enabled
1888261.029: CPU: APIC: 2b enabled
1888361.029: CPU: APIC: 2c enabled
1888461.029: CPU: APIC: 2d enabled
1888561.029: CPU: APIC: 2e enabled
1888661.029: CPU: APIC: 2f enabled
1888761.029: scan_bus: scanning of bus CPU_CLUSTER: 0 took 72637 usecs
1888861.029: DOMAIN: 0000 scanning...
1888961.029: PCI: pci_scan_bus for bus 00
1889061.029: PCI: 00:18.0 [1022/1600] bus ops
1889161.029: PCI: 00:18.0 [1022/1600] enabled
1889261.029: PCI: 00:18.1 [1022/1601] enabled
1889361.029: PCI: 00:18.2 [1022/1602] enabled
1889461.029: PCI: 00:18.3 [1022/1603] ops
1889561.029: PCI: 00:18.3 [1022/1603] enabled
1889661.029: PCI: 00:18.4 [1022/1604] ops
1889761.030: PCI: 00:18.4 [1022/1604] enabled
1889861.030: PCI: 00:18.5 [1022/1605] ops
1889961.030: PCI: 00:18.5 [1022/1605] enabled
1890061.030: PCI: 00:19.0 [1022/1600] bus ops
1890161.030: PCI: 00:19.0 [1022/1600] enabled
1890261.030: PCI: 00:19.1 [1022/1601] enabled
1890361.030: PCI: 00:19.2 [1022/1602] enabled
1890461.030: PCI: 00:19.3 [1022/1603] ops
1890561.030: PCI: 00:19.3 [1022/1603] enabled
1890661.030: PCI: 00:19.4 [1022/1604] ops
1890761.030: PCI: 00:19.4 [1022/1604] enabled
1890861.030: PCI: 00:19.5 [1022/1605] ops
1890961.030: PCI: 00:19.5 [1022/1605] enabled
1891061.030: PCI: 00:1a.0 [1022/1600] bus ops
1891161.030: PCI: 00:1a.0 [1022/1600] enabled
1891261.030: PCI: 00:1a.1 [1022/1601] enabled
1891361.030: PCI: 00:1a.2 [1022/1602] enabled
1891461.030: PCI: 00:1a.3 [1022/1603] ops
1891561.030: PCI: 00:1a.3 [1022/1603] enabled
1891661.030: PCI: 00:1a.4 [1022/1604] ops
1891761.030: PCI: 00:1a.4 [1022/1604] enabled
1891861.030: PCI: 00:1a.5 [1022/1605] ops
1891961.030: PCI: 00:1a.5 [1022/1605] enabled
1892061.030: PCI: 00:1b.0 [1022/1600] bus ops
1892161.030: PCI: 00:1b.0 [1022/1600] enabled
1892261.030: PCI: 00:1b.1 [1022/1601] enabled
1892361.030: PCI: 00:1b.2 [1022/1602] enabled
1892461.030: PCI: 00:1b.3 [1022/1603] ops
1892561.030: PCI: 00:1b.3 [1022/1603] enabled
1892661.030: PCI: 00:1b.4 [1022/1604] ops
1892761.030: PCI: 00:1b.4 [1022/1604] enabled
1892861.030: PCI: 00:1b.5 [1022/1605] ops
1892961.030: PCI: 00:1b.5 [1022/1605] enabled
1893061.030: PCI: 00:18.0 scanning...
1893161.030: do_hypertransport_scan_chain for bus 00
1893261.030: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
1893361.030: Bus-0, Dev-0, Fun-0.
1893461.030: enable_pcie_bar3
1893561.033: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
1893661.033: PciePowerOffGppPorts() port 8
1893761.033: NB_PCI_REG04 = 2.
1893861.033: NB_PCI_REG84 = 3000010.
1893961.033: NB_PCI_REG4C = 52042.
1894061.033: Sysmem TOM = 0_c0000000
1894161.033: Sysmem TOM2 = 40_40000000
1894261.033: PCI: 00:00.0 [1002/5a10] ops
1894361.033: PCI: 00:00.0 [1002/5a10] enabled
1894461.033: Capability: type 0x08 @ 0xf0
1894561.033: flags: 0xa803
1894661.033: Capability: type 0x08 @ 0xf0
1894761.033: Capability: type 0x08 @ 0xc4
1894861.033: flags: 0x0280
1894961.033: PCI: 00:00.0 count: 0014 static_count: 0015
1895061.033: PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015
1895161.033: PCI: pci_scan_bus for bus 00
1895261.033: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
1895361.033: Bus-0, Dev-0, Fun-0.
1895461.033: enable_pcie_bar3
1895561.036: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
1895661.036: PciePowerOffGppPorts() port 8
1895761.036: NB_PCI_REG04 = 2.
1895861.037: NB_PCI_REG84 = 3000010.
1895961.037: NB_PCI_REG4C = 52042.
1896061.037: Sysmem TOM = 0_c0000000
1896161.037: Sysmem TOM2 = 40_40000000
1896261.037: PCI: 00:00.0 [1002/5a10] enabled
1896361.037: sr5650_enable: dev=0012f460, VID_DID=0xffffffff
1896461.037: Bus-0, Dev-0, Fun-1.
1896561.037: PCI: Static device PCI: 00:00.1 not found, disabling it.
1896661.037: sr5650_enable: dev=0012f3c0, VID_DID=0x5a231002
1896761.037: Bus-0, Dev-0, Fun-2.
1896861.037: PCI: 00:00.2 [1002/5a23] ops
1896961.037: PCI: 00:00.2 [1002/5a23] enabled
1897061.037: sr5650_enable: dev=0012f320, VID_DID=0xffffffff
1897161.037: Bus-0, Dev-2,3, Fun-0. enable=1
1897261.037: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f320, port=0x2
1897361.077: PcieLinkTraining port=2:lc current state=2030400
1897461.078: sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0
1897561.078: PciePowerOffGppPorts() port 2
1897661.078: Capability: type 0x01 @ 0x50
1897761.078: Capability: type 0x10 @ 0x58
1897861.078: Capability: type 0x05 @ 0xa0
1897961.078: Capability: type 0x0d @ 0xb0
1898061.078: Capability: type 0x08 @ 0xb8
1898161.078: Capability: type 0x01 @ 0x50
1898261.078: Capability: type 0x10 @ 0x58
1898361.078: Capability: type 0x05 @ 0xa0
1898461.078: Capability: type 0x0d @ 0xb0
1898561.078: Capability: type 0x08 @ 0xb8
1898661.078: Capability: type 0x01 @ 0x50
1898761.078: Capability: type 0x10 @ 0x58
1898861.078: Capability: type 0x05 @ 0xa0
1898961.078: Capability: type 0x0d @ 0xb0
1899061.078: Capability: type 0x08 @ 0xb8
1899161.078: Capability: type 0x01 @ 0x50
1899261.078: Capability: type 0x10 @ 0x58
1899361.078: PCI: 00:02.0 subordinate bus PCI Express
1899461.078: PCI: 00:02.0 [1002/5a16] enabled
1899561.078: sr5650_enable: dev=0012f280, VID_DID=0xffffffff
1899661.078: Bus-0, Dev-2,3, Fun-0. enable=0
1899761.078: sr5650_enable: dev=0012f1e0, VID_DID=0xffffffff
1899861.078: enable_pcie_bar3
1899961.078: Bus-0, Dev-4,5,6,7, Fun-0. enable=1
1900061.078: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f1e0, port=0x4
1900161.119: PcieLinkTraining port=4:lc current state=2030400
1900261.120: sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
1900361.120: PciePowerOffGppPorts() port 4
1900461.120: Capability: type 0x01 @ 0x50
1900561.120: Capability: type 0x10 @ 0x58
1900661.120: Capability: type 0x05 @ 0xa0
1900761.120: Capability: type 0x0d @ 0xb0
1900861.120: Capability: type 0x08 @ 0xb8
1900961.120: Capability: type 0x01 @ 0x50
1901061.120: Capability: type 0x10 @ 0x58
1901161.120: Capability: type 0x05 @ 0xa0
1901261.120: Capability: type 0x0d @ 0xb0
1901361.120: Capability: type 0x08 @ 0xb8
1901461.120: Capability: type 0x01 @ 0x50
1901561.120: Capability: type 0x10 @ 0x58
1901661.120: Capability: type 0x05 @ 0xa0
1901761.120: Capability: type 0x0d @ 0xb0
1901861.120: Capability: type 0x08 @ 0xb8
1901961.120: Capability: type 0x01 @ 0x50
1902061.120: Capability: type 0x10 @ 0x58
1902161.120: PCI: 00:04.0 subordinate bus PCI Express
1902261.120: PCI: 00:04.0 [1002/5a18] enabled
1902361.120: sr5650_enable: dev=0012f140, VID_DID=0xffffffff
1902461.120: enable_pcie_bar3
1902561.120: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
1902661.120: sr5650_enable: dev=0012f0a0, VID_DID=0xffffffff
1902761.120: enable_pcie_bar3
1902861.120: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
1902961.120: sr5650_enable: dev=0012f000, VID_DID=0xffffffff
1903061.120: enable_pcie_bar3
1903161.120: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
1903261.120: sr5650_enable: dev=0012ef60, VID_DID=0xffffffff
1903361.120: Bus-0, Dev-8, Fun-0. enable=0
1903461.120: disable_pcie_bar3
1903561.120: sr5650_enable: dev=0012eec0, VID_DID=0xffffffff
1903661.120: Bus-0, Dev-9, 10, Fun-0. enable=1
1903761.120: enable_pcie_bar3
1903861.120: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012eec0, port=0x9
1903961.160: PcieLinkTraining port=5:lc current state=a0b0f10
1904061.160: addr=c0000000,bus=0,devfn=48
1904161.160: PcieTrainPort reg=0x10000
1904261.160: sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
1904361.160: Capability: type 0x01 @ 0x50
1904461.160: Capability: type 0x10 @ 0x58
1904561.160: Capability: type 0x05 @ 0xa0
1904661.160: Capability: type 0x0d @ 0xb0
1904761.160: Capability: type 0x08 @ 0xb8
1904861.160: Capability: type 0x01 @ 0x50
1904961.160: Capability: type 0x10 @ 0x58
1905061.160: Capability: type 0x05 @ 0xa0
1905161.160: Capability: type 0x0d @ 0xb0
1905261.160: Capability: type 0x08 @ 0xb8
1905361.160: Capability: type 0x01 @ 0x50
1905461.160: Capability: type 0x10 @ 0x58
1905561.161: Capability: type 0x05 @ 0xa0
1905661.161: Capability: type 0x0d @ 0xb0
1905761.160: Capability: type 0x08 @ 0xb8
1905861.161: Capability: type 0x01 @ 0x50
1905961.161: Capability: type 0x10 @ 0x58
1906061.161: PCI: 00:09.0 subordinate bus PCI Express
1906161.161: PCI: 00:09.0 [1002/5a1c] enabled
1906261.161: sr5650_enable: dev=0012ee20, VID_DID=0xffffffff
1906361.161: Bus-0, Dev-9, 10, Fun-0. enable=1
1906461.161: enable_pcie_bar3
1906561.161: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ee20, port=0xa
1906661.201: PcieLinkTraining port=6:lc current state=a0b0f10
1906761.201: addr=c0000000,bus=0,devfn=50
1906861.201: PcieTrainPort reg=0x10000
1906961.201: sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
1907061.201: Capability: type 0x01 @ 0x50
1907161.201: Capability: type 0x10 @ 0x58
1907261.201: Capability: type 0x05 @ 0xa0
1907361.201: Capability: type 0x0d @ 0xb0
1907461.201: Capability: type 0x08 @ 0xb8
1907561.201: Capability: type 0x01 @ 0x50
1907661.201: Capability: type 0x10 @ 0x58
1907761.201: Capability: type 0x05 @ 0xa0
1907861.201: Capability: type 0x0d @ 0xb0
1907961.201: Capability: type 0x08 @ 0xb8
1908061.201: Capability: type 0x01 @ 0x50
1908161.201: Capability: type 0x10 @ 0x58
1908261.201: Capability: type 0x05 @ 0xa0
1908361.201: Capability: type 0x0d @ 0xb0
1908461.201: Capability: type 0x08 @ 0xb8
1908561.201: Capability: type 0x01 @ 0x50
1908661.201: Capability: type 0x10 @ 0x58
1908761.201: PCI: 00:0a.0 subordinate bus PCI Express
1908861.201: PCI: 00:0a.0 [1002/5a1d] enabled
1908961.201: sr5650_enable: dev=0012ed80, VID_DID=0xffffffff
1909061.201: Bus-0, Dev-11,12, Fun-0. enable=1
1909161.201: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ed80, port=0xb
1909261.241: PcieLinkTraining port=b:lc current state=2030400
1909361.242: sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0
1909461.242: PciePowerOffGppPorts() port 11
1909561.242: Capability: type 0x01 @ 0x50
1909661.242: Capability: type 0x10 @ 0x58
1909761.242: Capability: type 0x05 @ 0xa0
1909861.242: Capability: type 0x0d @ 0xb0
1909961.242: Capability: type 0x08 @ 0xb8
1910061.242: Capability: type 0x01 @ 0x50
1910161.243: Capability: type 0x10 @ 0x58
1910261.243: Capability: type 0x05 @ 0xa0
1910361.243: Capability: type 0x0d @ 0xb0
1910461.243: Capability: type 0x08 @ 0xb8
1910561.243: Capability: type 0x01 @ 0x50
1910661.243: Capability: type 0x10 @ 0x58
1910761.243: Capability: type 0x05 @ 0xa0
1910861.243: Capability: type 0x0d @ 0xb0
1910961.243: Capability: type 0x08 @ 0xb8
1911061.243: Capability: type 0x01 @ 0x50
1911161.243: Capability: type 0x10 @ 0x58
1911261.243: PCI: 00:0b.0 subordinate bus PCI Express
1911361.243: PCI: 00:0b.0 [1002/5a1f] enabled
1911461.243: sr5650_enable: dev=0012ece0, VID_DID=0xffffffff
1911561.243: Bus-0, Dev-11,12, Fun-0. enable=1
1911661.243: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ece0, port=0xc
1911761.283: PcieLinkTraining port=c:lc current state=2030400
1911861.284: sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0
1911961.284: PciePowerOffGppPorts() port 12
1912061.284: Capability: type 0x01 @ 0x50
1912161.284: Capability: type 0x10 @ 0x58
1912261.284: Capability: type 0x05 @ 0xa0
1912361.284: Capability: type 0x0d @ 0xb0
1912461.284: Capability: type 0x08 @ 0xb8
1912561.284: Capability: type 0x01 @ 0x50
1912661.284: Capability: type 0x10 @ 0x58
1912761.284: Capability: type 0x05 @ 0xa0
1912861.284: Capability: type 0x0d @ 0xb0
1912961.284: Capability: type 0x08 @ 0xb8
1913061.284: Capability: type 0x01 @ 0x50
1913161.284: Capability: type 0x10 @ 0x58
1913261.284: Capability: type 0x05 @ 0xa0
1913361.284: Capability: type 0x0d @ 0xb0
1913461.284: Capability: type 0x08 @ 0xb8
1913561.284: Capability: type 0x01 @ 0x50
1913661.284: Capability: type 0x10 @ 0x58
1913761.284: PCI: 00:0c.0 subordinate bus PCI Express
1913861.284: PCI: 00:0c.0 [1002/5a20] enabled
1913961.284: sr5650_enable: dev=0012ec40, VID_DID=0xffffffff
1914061.284: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ec40, port=0xd
1914161.325: PcieLinkTraining port=d:lc current state=20212210
1914261.324: addr=c0000000,bus=0,devfn=68
1914361.324: PcieTrainPort reg=0x10000
1914461.324: sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1
1914562.324: Capability: type 0x01 @ 0x50
1914662.324: Capability: type 0x10 @ 0x58
1914762.324: Capability: type 0x05 @ 0xa0
1914862.324: Capability: type 0x0d @ 0xb0
1914962.324: Capability: type 0x08 @ 0xb8
1915062.324: Capability: type 0x01 @ 0x50
1915162.325: Capability: type 0x10 @ 0x58
1915262.324: Capability: type 0x05 @ 0xa0
1915362.325: Capability: type 0x0d @ 0xb0
1915462.325: Capability: type 0x08 @ 0xb8
1915562.325: Capability: type 0x01 @ 0x50
1915662.325: Capability: type 0x10 @ 0x58
1915762.325: Capability: type 0x05 @ 0xa0
1915862.325: Capability: type 0x0d @ 0xb0
1915962.325: Capability: type 0x08 @ 0xb8
1916062.325: Capability: type 0x01 @ 0x50
1916162.325: Capability: type 0x10 @ 0x58
1916262.325: PCI: 00:0d.0 subordinate bus PCI Express
1916362.325: PCI: 00:0d.0 [1002/5a1e] enabled
1916462.325: sb7xx_51xx_enable()
1916562.325: PCI: 00:11.0 [1002/4394] ops
1916662.325: PCI: 00:11.0 [1002/4394] enabled
1916762.325: sb7xx_51xx_enable()
1916862.325: PCI: 00:12.0 [1002/4397] ops
1916962.325: PCI: 00:12.0 [1002/4397] enabled
1917062.325: sb7xx_51xx_enable()
1917162.325: PCI: 00:12.1 [1002/4398] ops
1917262.325: PCI: 00:12.1 [1002/4398] enabled
1917362.325: sb7xx_51xx_enable()
1917462.325: PCI: 00:12.2 [1002/4396] ops
1917562.325: PCI: 00:12.2 [1002/4396] enabled
1917662.325: sb7xx_51xx_enable()
1917762.325: PCI: 00:13.0 [1002/4397] ops
1917862.325: PCI: 00:13.0 [1002/4397] enabled
1917962.325: sb7xx_51xx_enable()
1918062.325: PCI: 00:13.1 [1002/4398] ops
1918162.325: PCI: 00:13.1 [1002/4398] enabled
1918262.325: sb7xx_51xx_enable()
1918362.325: PCI: 00:13.2 [1002/4396] ops
1918462.325: PCI: 00:13.2 [1002/4396] enabled
1918562.325: sb7xx_51xx_enable()
1918662.325: PCI: 00:14.0 [1002/4385] bus ops
1918762.325: PCI: 00:14.0 [1002/4385] enabled
1918862.325: sb7xx_51xx_enable()
1918962.325: PCI: 00:14.1 [1002/439c] ops
1919062.325: PCI: 00:14.1 [1002/439c] enabled
1919162.325: sb7xx_51xx_enable()
1919262.325: PCI: 00:14.2 [1002/4383] ops
1919362.325: PCI: 00:14.2 [1002/4383] enabled
1919462.325: sb7xx_51xx_enable()
1919562.325: PCI: 00:14.3 [1002/439d] bus ops
1919662.325: PCI: 00:14.3 [1002/439d] enabled
1919762.325: sb7xx_51xx_enable()
1919862.325: PCI: 00:14.4 [1002/4384] bus ops
1919962.325: PCI: 00:14.4 [1002/4384] enabled
1920062.325: sb7xx_51xx_enable()
1920162.325: PCI: 00:14.5 [1002/4399] ops
1920262.325: PCI: 00:14.5 [1002/4399] enabled
1920362.325: PCI: 00:02.0 scanning...
1920462.325: do_pci_scan_bridge for PCI: 00:02.0
1920562.325: PCI: pci_scan_bus for bus 01
1920662.325: scan_bus: scanning of bus PCI: 00:02.0 took 5932 usecs
1920762.325: PCI: 00:04.0 scanning...
1920862.325: do_pci_scan_bridge for PCI: 00:04.0
1920962.325: PCI: pci_scan_bus for bus 02
1921062.325: scan_bus: scanning of bus PCI: 00:04.0 took 5921 usecs
1921162.325: PCI: 00:09.0 scanning...
1921262.325: do_pci_scan_bridge for PCI: 00:09.0
1921362.325: PCI: pci_scan_bus for bus 03
1921462.326: PCI: 03:00.0 [8086/10d3] enabled
1921562.326: Capability: type 0x01 @ 0xc8
1921662.326: Capability: type 0x05 @ 0xd0
1921762.326: Capability: type 0x10 @ 0xe0
1921862.326: Capability: type 0x01 @ 0x50
1921962.326: Capability: type 0x10 @ 0x58
1922062.326: Enabling Common Clock Configuration
1922162.326: PCIE CLK PM is not supported by endpointASPM: Enabled None
1922262.326: scan_bus: scanning of bus PCI: 00:09.0 took 23857 usecs
1922362.326: PCI: 00:0a.0 scanning...
1922462.326: do_pci_scan_bridge for PCI: 00:0a.0
1922562.326: PCI: pci_scan_bus for bus 04
1922662.326: PCI: 04:00.0 [8086/10d3] enabled
1922762.326: Capability: type 0x01 @ 0xc8
1922862.326: Capability: type 0x05 @ 0xd0
1922962.326: Capability: type 0x10 @ 0xe0
1923062.326: Capability: type 0x01 @ 0x50
1923162.326: Capability: type 0x10 @ 0x58
1923262.326: Enabling Common Clock Configuration
1923362.326: PCIE CLK PM is not supported by endpointASPM: Enabled None
1923462.326: scan_bus: scanning of bus PCI: 00:0a.0 took 23825 usecs
1923562.326: PCI: 00:0b.0 scanning...
1923662.326: do_pci_scan_bridge for PCI: 00:0b.0
1923762.326: PCI: pci_scan_bus for bus 05
1923862.326: scan_bus: scanning of bus PCI: 00:0b.0 took 5920 usecs
1923962.326: PCI: 00:0c.0 scanning...
1924062.326: do_pci_scan_bridge for PCI: 00:0c.0
1924162.326: PCI: pci_scan_bus for bus 06
1924262.326: scan_bus: scanning of bus PCI: 00:0c.0 took 5920 usecs
1924362.326: PCI: 00:0d.0 scanning...
1924462.326: do_pci_scan_bridge for PCI: 00:0d.0
1924562.326: PCI: pci_scan_bus for bus 07
1924662.326: PCI: 07:00.0 [8086/10fb] enabled
1924762.326: PCI: 07:00.1 [8086/10fb] enabled
1924862.326: Capability: type 0x01 @ 0x40
1924962.326: Capability: type 0x05 @ 0x50
1925062.326: Capability: type 0x11 @ 0x70
1925162.326: Capability: type 0x10 @ 0xa0
1925262.326: Capability: type 0x01 @ 0x50
1925362.326: Capability: type 0x10 @ 0x58
1925462.326: Enabling Common Clock Configuration
1925562.327: PCIE CLK PM is not supported by endpointASPM: Enabled None
1925662.327: Capability: type 0x01 @ 0x40
1925762.327: Capability: type 0x05 @ 0x50
1925862.327: Capability: type 0x11 @ 0x70
1925962.327: Capability: type 0x10 @ 0xa0
1926062.327: Capability: type 0x01 @ 0x50
1926162.327: Capability: type 0x10 @ 0x58
1926262.327: Enabling Common Clock Configuration
1926362.327: PCIE CLK PM is not supported by endpointASPM: Enabled None
1926462.327: scan_bus: scanning of bus PCI: 00:0d.0 took 45521 usecs
1926562.327: PCI: 00:14.0 scanning...
1926662.327: scan_generic_bus for PCI: 00:14.0
1926762.327: bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
1926862.327: bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
1926962.327: bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
1927062.327: bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
1927162.327: bus: PCI: 00:14.0[0]->I2C: 01:54 enabled
1927262.327: bus: PCI: 00:14.0[0]->I2C: 01:55 enabled
1927362.327: bus: PCI: 00:14.0[0]->I2C: 01:56 enabled
1927462.327: bus: PCI: 00:14.0[0]->I2C: 01:57 enabled
1927562.327: bus: PCI: 00:14.0[0]->I2C: 01:2f enabled
1927662.327: scan_generic_bus for PCI: 00:14.0 done
1927762.327: scan_bus: scanning of bus PCI: 00:14.0 took 30457 usecs
1927862.327: PCI: 00:14.3 scanning...
1927962.327: scan_lpc_bus for PCI: 00:14.3
1928062.327: PNP: 002e.0 disabled
1928162.327: PNP: 002e.1 disabled
1928262.327: PNP: 002e.2 enabled
1928362.327: PNP: 002e.3 enabled
1928462.327: PNP: 002e.5 enabled
1928562.327: PNP: 002e.106 disabled
1928662.327: PNP: 002e.107 disabled
1928762.327: PNP: 002e.207 disabled
1928862.327: PNP: 002e.307 disabled
1928962.327: PNP: 002e.407 disabled
1929062.328: PNP: 002e.8 disabled
1929162.328: PNP: 002e.108 disabled
1929262.328: PNP: 002e.9 disabled
1929362.328: PNP: 002e.109 disabled
1929462.328: PNP: 002e.209 disabled
1929562.328: PNP: 002e.309 disabled
1929662.328: PNP: 002e.a enabled
1929762.328: PNP: 002e.b enabled
1929862.328: PNP: 002e.c disabled
1929962.328: PNP: 002e.d disabled
1930062.328: PNP: 002e.f disabled
1930162.328: PNP: 004e.0 enabled
1930262.328: scan_lpc_bus for PCI: 00:14.3 done
1930362.328: scan_bus: scanning of bus PCI: 00:14.3 took 37768 usecs
1930462.328: PCI: 00:14.4 scanning...
1930562.328: do_pci_scan_bridge for PCI: 00:14.4
1930662.328: PCI: pci_scan_bus for bus 08
1930762.328: sb7xx_51xx_enable()
1930862.328: PCI: 08:01.0 [1a03/2000] ops
1930962.328: PCI: 08:01.0 [1a03/2000] enabled
1931062.328: sb7xx_51xx_enable()
1931162.328: PCI: 08:02.0 [11c1/5811] enabled
1931262.328: sb7xx_51xx_enable()
1931362.328: PCI: Static device PCI: 08:03.0 not found, disabling it.
1931462.328: scan_bus: scanning of bus PCI: 00:14.4 took 19824 usecs
1931562.328: scan_bus: scanning of bus PCI: 00:18.0 took 1755041 usecs
1931662.328: PCI: 00:19.0 scanning...
1931762.328: scan_bus: scanning of bus PCI: 00:19.0 took 1652 usecs
1931862.328: PCI: 00:1a.0 scanning...
1931962.328: scan_bus: scanning of bus PCI: 00:1a.0 took 1652 usecs
1932062.328: PCI: 00:1b.0 scanning...
1932162.328: scan_bus: scanning of bus PCI: 00:1b.0 took 1652 usecs
1932262.328: DOMAIN: 0000 passpw: enabled
1932362.328: DOMAIN: 0000 passpw: enabled
1932462.328: DOMAIN: 0000 passpw: enabled
1932562.328: DOMAIN: 0000 passpw: enabled
1932662.328: scan_bus: scanning of bus DOMAIN: 0000 took 1868798 usecs
1932762.328: root_dev_scan_bus for Root Device done
1932862.328: scan_bus: scanning of bus Root Device took 1966996 usecs
1932962.328: done
1933062.328: BS: BS_DEV_ENUMERATE times (us): entry 0 run 2288289 exit 0
1933162.328: found VGA at PCI: 08:01.0
1933262.328: Setting up VGA for PCI: 08:01.0
1933362.328: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4
1933462.328: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
1933562.328: Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1933662.328: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1933762.328: Allocating resources...
1933862.328: Reading resources...
1933962.328: Root Device read_resources bus 0 link: 0
1934062.328: CPU_CLUSTER: 0 read_resources bus 0 link: 0
1934162.328: CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1934262.328: Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
1934362.329: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1934462.329: CBFS: Locating 'cmos_layout.bin'
1934562.329: CBFS: Found @ offset 2b0c0 size e88
1934662.329: Reserving CC6 save segment base: 4038000000 size: 08000000
1934762.329: DOMAIN: 0000 read_resources bus 0 link: 0
1934862.329: PCI: 00:18.0 read_resources bus 0 link: 2
1934962.329: PCI: 00:18.0 read_resources bus 0 link: 2 done
1935062.329: PCI: 00:18.0 read_resources bus 0 link: 3
1935162.329: PCI: 00:18.0 read_resources bus 0 link: 3 done
1935262.329: PCI: 00:18.0 read_resources bus 0 link: 0
1935362.329: PCI: 00:18.0 read_resources bus 0 link: 0 done
1935462.329: PCI: 00:18.0 read_resources bus 0 link: 1
1935562.329: sr5690_read_resource: PCI: 00:00.0
1935662.329: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1935762.329: CBFS: Locating 'cmos_layout.bin'
1935862.329: CBFS: Found @ offset 2b0c0 size e88
1935962.330: PCI: 00:02.0 read_resources bus 1 link: 0
1936062.330: PCI: 00:02.0 read_resources bus 1 link: 0 done
1936162.330: PCI: 00:04.0 read_resources bus 2 link: 0
1936262.330: PCI: 00:04.0 read_resources bus 2 link: 0 done
1936362.330: PCI: 00:09.0 read_resources bus 3 link: 0
1936462.330: PCI: 00:09.0 read_resources bus 3 link: 0 done
1936562.330: PCI: 00:0a.0 read_resources bus 4 link: 0
1936662.330: PCI: 00:0a.0 read_resources bus 4 link: 0 done
1936762.330: PCI: 00:0b.0 read_resources bus 5 link: 0
1936862.330: PCI: 00:0b.0 read_resources bus 5 link: 0 done
1936962.330: PCI: 00:0c.0 read_resources bus 6 link: 0
1937062.330: PCI: 00:0c.0 read_resources bus 6 link: 0 done
1937162.330: PCI: 00:0d.0 read_resources bus 7 link: 0
1937262.330: PCI: 00:0d.0 read_resources bus 7 link: 0 done
1937362.331: PCI: 00:14.0 read_resources bus 1 link: 0
1937462.331: I2C: 01:50 missing read_resources
1937562.331: I2C: 01:51 missing read_resources
1937662.331: I2C: 01:52 missing read_resources
1937762.331: I2C: 01:53 missing read_resources
1937862.331: I2C: 01:54 missing read_resources
1937962.331: I2C: 01:55 missing read_resources
1938062.331: I2C: 01:56 missing read_resources
1938162.331: I2C: 01:57 missing read_resources
1938262.331: PCI: 00:14.0 read_resources bus 1 link: 0 done
1938362.331: PCI: 00:14.3 read_resources bus 0 link: 0
1938462.331: PNP: 004e.0 missing read_resources
1938562.331: PCI: 00:14.3 read_resources bus 0 link: 0 done
1938662.331: PCI: 00:14.4 read_resources bus 8 link: 0
1938762.331: PCI: 00:14.4 read_resources bus 8 link: 0 done
1938862.331: PCI: 00:18.0 read_resources bus 0 link: 1 done
1938962.331: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1939062.331: CBFS: Locating 'cmos_layout.bin'
1939162.331: CBFS: Found @ offset 2b0c0 size e88
1939262.332: PCI: 00:18.4 read_resources bus 0 link: 0
1939362.332: PCI: 00:18.4 read_resources bus 0 link: 0 done
1939462.332: PCI: 00:18.4 read_resources bus 0 link: 1
1939562.332: PCI: 00:18.4 read_resources bus 0 link: 1 done
1939662.332: PCI: 00:18.4 read_resources bus 0 link: 2
1939762.332: PCI: 00:18.4 read_resources bus 0 link: 2 done
1939862.332: PCI: 00:18.4 read_resources bus 0 link: 3
1939962.332: PCI: 00:18.4 read_resources bus 0 link: 3 done
1940062.332: PCI: 00:19.0 read_resources bus 0 link: 3
1940162.332: PCI: 00:19.0 read_resources bus 0 link: 3 done
1940262.332: PCI: 00:19.0 read_resources bus 0 link: 2
1940362.332: PCI: 00:19.0 read_resources bus 0 link: 2 done
1940462.332: PCI: 00:19.0 read_resources bus 0 link: 0
1940562.332: PCI: 00:19.0 read_resources bus 0 link: 0 done
1940662.332: PCI: 00:19.0 read_resources bus 0 link: 1
1940762.332: PCI: 00:19.0 read_resources bus 0 link: 1 done
1940862.332: PCI: 00:19.4 read_resources bus 0 link: 0
1940962.332: PCI: 00:19.4 read_resources bus 0 link: 0 done
1941062.332: PCI: 00:19.4 read_resources bus 0 link: 1
1941162.332: PCI: 00:19.4 read_resources bus 0 link: 1 done
1941262.332: PCI: 00:19.4 read_resources bus 0 link: 2
1941362.332: PCI: 00:19.4 read_resources bus 0 link: 2 done
1941462.332: PCI: 00:19.4 read_resources bus 0 link: 3
1941562.332: PCI: 00:19.4 read_resources bus 0 link: 3 done
1941662.332: PCI: 00:1a.0 read_resources bus 0 link: 3
1941762.332: PCI: 00:1a.0 read_resources bus 0 link: 3 done
1941862.332: PCI: 00:1a.0 read_resources bus 0 link: 2
1941962.332: PCI: 00:1a.0 read_resources bus 0 link: 2 done
1942062.332: PCI: 00:1a.0 read_resources bus 0 link: 0
1942162.332: PCI: 00:1a.0 read_resources bus 0 link: 0 done
1942262.332: PCI: 00:1a.0 read_resources bus 0 link: 1
1942362.332: PCI: 00:1a.0 read_resources bus 0 link: 1 done
1942462.332: PCI: 00:1a.4 read_resources bus 0 link: 0
1942562.332: PCI: 00:1a.4 read_resources bus 0 link: 0 done
1942662.332: PCI: 00:1a.4 read_resources bus 0 link: 1
1942762.332: PCI: 00:1a.4 read_resources bus 0 link: 1 done
1942862.332: PCI: 00:1a.4 read_resources bus 0 link: 2
1942962.332: PCI: 00:1a.4 read_resources bus 0 link: 2 done
1943062.332: PCI: 00:1a.4 read_resources bus 0 link: 3
1943162.332: PCI: 00:1a.4 read_resources bus 0 link: 3 done
1943262.332: PCI: 00:1b.0 read_resources bus 0 link: 3
1943362.332: PCI: 00:1b.0 read_resources bus 0 link: 3 done
1943462.332: PCI: 00:1b.0 read_resources bus 0 link: 2
1943562.332: PCI: 00:1b.0 read_resources bus 0 link: 2 done
1943662.332: PCI: 00:1b.0 read_resources bus 0 link: 0
1943762.332: PCI: 00:1b.0 read_resources bus 0 link: 0 done
1943862.332: PCI: 00:1b.0 read_resources bus 0 link: 1
1943962.332: PCI: 00:1b.0 read_resources bus 0 link: 1 done
1944062.332: PCI: 00:1b.4 read_resources bus 0 link: 0
1944162.332: PCI: 00:1b.4 read_resources bus 0 link: 0 done
1944262.332: PCI: 00:1b.4 read_resources bus 0 link: 1
1944362.332: PCI: 00:1b.4 read_resources bus 0 link: 1 done
1944462.332: PCI: 00:1b.4 read_resources bus 0 link: 2
1944562.332: PCI: 00:1b.4 read_resources bus 0 link: 2 done
1944662.332: PCI: 00:1b.4 read_resources bus 0 link: 3
1944762.332: PCI: 00:1b.4 read_resources bus 0 link: 3 done
1944862.332: DOMAIN: 0000 read_resources bus 0 link: 0 done
1944962.332: Root Device read_resources bus 0 link: 0 done
1945062.332: Done reading resources.
1945162.333: Show resources in subtree (Root Device)...After reading.
1945262.333: Root Device child on link 0 CPU_CLUSTER: 0
1945362.333: CPU_CLUSTER: 0 child on link 0 APIC: 00
1945462.333: APIC: 00
1945562.333: APIC: 01
1945662.333: APIC: 02
1945762.333: APIC: 03
1945862.333: APIC: 04
1945962.333: APIC: 05
1946062.333: APIC: 06
1946162.333: APIC: 07
1946262.333: APIC: 08
1946362.333: APIC: 09
1946462.333: APIC: 0a
1946562.333: APIC: 0b
1946662.333: APIC: 0c
1946762.333: APIC: 0d
1946862.333: APIC: 0e
1946962.333: APIC: 0f
1947062.333: APIC: 20
1947162.333: APIC: 21
1947262.333: APIC: 22
1947362.333: APIC: 23
1947462.333: APIC: 24
1947562.333: APIC: 25
1947662.333: APIC: 26
1947762.333: APIC: 27
1947862.333: APIC: 28
1947962.333: APIC: 29
1948062.333: APIC: 2a
1948162.334: APIC: 2b
1948262.334: APIC: 2c
1948362.334: APIC: 2d
1948462.334: APIC: 2e
1948562.334: APIC: 2f
1948662.334: DOMAIN: 0000 child on link 0 PCI: 00:18.0
1948762.334: DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1948862.334: DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1948962.334: DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
1949062.334: DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
1949162.334: DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
1949262.334: PCI: 00:18.0
1949362.334: PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0
1949462.334: PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8
1949562.334: PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8
1949662.334: PCI: 00:00.0
1949762.334: PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
1949862.334: PCI: 00:00.1
1949962.334: PCI: 00:00.2
1950062.334: PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
1950162.334: PCI: 00:02.0
1950262.334: PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1950362.334: PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1950462.334: PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1950562.334: PCI: 00:03.0
1950662.334: PCI: 00:04.0
1950762.334: PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1950862.334: PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1950962.334: PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1951062.334: PCI: 00:05.0
1951162.334: PCI: 00:06.0
1951262.334: PCI: 00:07.0
1951362.334: PCI: 00:08.0
1951462.334: PCI: 00:09.0 child on link 0 PCI: 03:00.0
1951562.334: PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1951662.334: PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1951762.334: PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1951862.334: PCI: 03:00.0
1951962.334: PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
1952062.334: PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
1952162.334: PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
1952262.334: PCI: 00:0a.0 child on link 0 PCI: 04:00.0
1952362.334: PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1952462.334: PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1952562.334: PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1952662.334: PCI: 04:00.0
1952762.334: PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
1952862.334: PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
1952962.334: PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
1953062.334: PCI: 00:0b.0
1953162.334: PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1953262.334: PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1953362.334: PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1953462.334: PCI: 00:0c.0
1953562.334: PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1953662.334: PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1953762.334: PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1953862.334: PCI: 00:0d.0 child on link 0 PCI: 07:00.0
1953962.334: PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
1954062.334: PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1954162.334: PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1954262.334: PCI: 07:00.0
1954362.335: PCI: 07:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
1954462.335: PCI: 07:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
1954562.335: PCI: 07:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
1954662.335: PCI: 07:00.1
1954762.335: PCI: 07:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
1954862.335: PCI: 07:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
1954962.335: PCI: 07:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
1955062.335: PCI: 00:11.0
1955162.335: PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
1955262.335: PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
1955362.335: PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1955462.335: PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1955562.335: PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
1955662.335: PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
1955762.335: PCI: 00:12.0
1955862.335: PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1955962.335: PCI: 00:12.1
1956062.335: PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1956162.335: PCI: 00:12.2
1956262.335: PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
1956362.335: PCI: 00:13.0
1956462.335: PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1956562.335: PCI: 00:13.1
1956662.335: PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1956762.335: PCI: 00:13.2
1956862.335: PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
1956962.335: PCI: 00:14.0 child on link 0 I2C: 01:50
1957062.335: PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
1957162.335: PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
1957262.335: PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
1957362.335: PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
1957462.335: PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
1957562.335: I2C: 01:50
1957662.335: I2C: 01:51
1957762.335: I2C: 01:52
1957862.335: I2C: 01:53
1957962.335: I2C: 01:54
1958062.335: I2C: 01:55
1958162.335: I2C: 01:56
1958262.335: I2C: 01:57
1958362.335: I2C: 01:2f
1958462.335: PCI: 00:14.1
1958562.335: PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
1958662.335: PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
1958762.335: PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1958862.335: PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1958962.335: PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
1959062.335: PCI: 00:14.2
1959162.335: PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1959262.335: PCI: 00:14.3 child on link 0 PNP: 002e.0
1959362.335: PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
1959462.335: PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
1959562.335: PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
1959662.335: PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
1959762.335: PNP: 002e.0
1959862.335: PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
1959962.335: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
1960062.335: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
1960162.335: PNP: 002e.1
1960262.335: PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
1960362.335: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
1960462.335: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
1960562.335: PNP: 002e.2
1960662.335: PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
1960762.335: PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
1960862.335: PNP: 002e.3
1960962.336: PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
1961062.336: PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
1961162.336: PNP: 002e.5
1961262.336: PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
1961362.336: PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
1961462.336: PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
1961562.336: PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
1961662.336: PNP: 002e.106
1961762.336: PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
1961862.336: PNP: 002e.107
1961962.336: PNP: 002e.207
1962062.336: PNP: 002e.307
1962162.336: PNP: 002e.407
1962262.336: PNP: 002e.8
1962362.336: PNP: 002e.108
1962462.336: PNP: 002e.9
1962562.336: PNP: 002e.109
1962662.336: PNP: 002e.209
1962762.336: PNP: 002e.309
1962862.336: PNP: 002e.a
1962962.336: PNP: 002e.b
1963062.336: PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
1963162.336: PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
1963262.336: PNP: 002e.c
1963362.336: PNP: 002e.d
1963462.336: PNP: 002e.f
1963562.336: PNP: 004e.0
1963662.336: PCI: 00:14.4 child on link 0 PCI: 08:01.0
1963762.336: PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1963862.336: PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
1963962.336: PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1964062.336: PCI: 08:01.0
1964162.336: PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
1964262.336: PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
1964362.336: PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
1964462.336: PCI: 08:02.0
1964562.336: PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1964662.336: PCI: 08:03.0
1964762.336: PCI: 00:14.5
1964862.336: PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1964962.336: PCI: 00:18.1
1965062.336: PCI: 00:18.2
1965162.336: PCI: 00:18.3
1965262.336: PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
1965362.336: PCI: 00:18.4
1965462.336: PCI: 00:18.5
1965562.337: PCI: 00:19.0
1965662.337: PCI: 00:19.1
1965762.337: PCI: 00:19.2
1965862.337: PCI: 00:19.3
1965962.337: PCI: 00:19.4
1966062.337: PCI: 00:19.5
1966162.337: PCI: 00:1a.0
1966262.337: PCI: 00:1a.1
1966362.337: PCI: 00:1a.2
1966462.337: PCI: 00:1a.3
1966562.337: PCI: 00:1a.4
1966662.337: PCI: 00:1a.5
1966762.337: PCI: 00:1b.0
1966862.337: PCI: 00:1b.1
1966962.337: PCI: 00:1b.2
1967062.337: PCI: 00:1b.3
1967162.337: PCI: 00:1b.4
1967262.337: PCI: 00:1b.5
1967362.337: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1967462.337: PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1967562.337: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1967662.337: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
1967762.337: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1967862.337: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
1967962.337: PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1968062.337: PCI: 03:00.0 18 * [0x0 - 0x1f] io
1968162.337: PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
1968262.337: PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1968362.337: PCI: 04:00.0 18 * [0x0 - 0x1f] io
1968462.337: PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
1968562.337: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1968662.337: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
1968762.337: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1968862.337: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
1968962.337: PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
1969062.337: PCI: 07:00.0 18 * [0x0 - 0x1f] io
1969162.337: PCI: 07:00.1 18 * [0x20 - 0x3f] io
1969262.337: PCI: 00:0d.0 io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done
1969362.337: PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1969462.337: PCI: 08:01.0 18 * [0x0 - 0x7f] io
1969562.337: PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
1969662.337: PCI: 00:09.0 1c * [0x0 - 0xfff] io
1969762.337: PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
1969862.337: PCI: 00:0d.0 1c * [0x2000 - 0x2fff] io
1969962.337: PCI: 00:14.4 1c * [0x3000 - 0x3fff] io
1970062.337: PCI: 00:11.0 20 * [0x4000 - 0x400f] io
1970162.337: PCI: 00:14.1 20 * [0x4010 - 0x401f] io
1970262.337: PCI: 00:11.0 10 * [0x4020 - 0x4027] io
1970362.337: PCI: 00:11.0 18 * [0x4028 - 0x402f] io
1970462.337: PCI: 00:14.1 10 * [0x4030 - 0x4037] io
1970562.337: PCI: 00:14.1 18 * [0x4038 - 0x403f] io
1970662.337: PCI: 00:11.0 14 * [0x4040 - 0x4043] io
1970762.337: PCI: 00:11.0 1c * [0x4044 - 0x4047] io
1970862.337: PCI: 00:14.1 14 * [0x4048 - 0x404b] io
1970962.337: PCI: 00:14.1 1c * [0x404c - 0x404f] io
1971062.337: PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done
1971162.338: PCI: 00:18.0 110d8 * [0x0 - 0x4fff] io
1971262.338: DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
1971362.338: DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1971462.338: PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
1971562.338: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1971662.338: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1971762.338: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1971862.338: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1971962.338: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1972062.338: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1972162.338: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1972262.338: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1972362.338: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1972462.338: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1972562.338: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1972662.338: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1972762.338: PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1972862.338: PCI: 07:00.0 10 * [0x0 - 0x7ffff] prefmem
1972962.338: PCI: 07:00.1 10 * [0x80000 - 0xfffff] prefmem
1973062.338: PCI: 07:00.0 20 * [0x100000 - 0x103fff] prefmem
1973162.338: PCI: 07:00.1 20 * [0x104000 - 0x107fff] prefmem
1973262.338: PCI: 00:0d.0 prefmem: base: 108000 size: 200000 align: 20 gran: 20 limit: ffffffffffffffff done
1973362.338: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1973462.338: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
1973562.338: PCI: 00:0d.0 24 * [0x0 - 0x1fffff] prefmem
1973662.338: PCI: 00:00.0 fc * [0x200000 - 0x2000ff] prefmem
1973762.338: PCI: 00:18.0 prefmem: base: 200100 size: 300000 align: 20 gran: 20 limit: ffffffff done
1973862.338: PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
1973962.338: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1974062.338: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
1974162.338: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1974262.338: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
1974362.338: PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1974462.338: PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem
1974562.338: PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem
1974662.338: PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1974762.338: PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1974862.338: PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem
1974962.338: PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem
1975062.338: PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1975162.338: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1975262.338: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
1975362.338: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1975462.338: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
1975562.338: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1975662.338: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
1975762.338: PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1975862.338: PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem
1975962.338: PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem
1976062.338: PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem
1976162.338: PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done
1976262.338: PCI: 00:14.4 20 * [0x0 - 0x8fffff] mem
1976362.338: PCI: 00:09.0 20 * [0x900000 - 0x9fffff] mem
1976462.338: PCI: 00:0a.0 20 * [0xa00000 - 0xafffff] mem
1976562.338: PCI: 00:00.2 44 * [0xb00000 - 0xb03fff] mem
1976662.338: PCI: 00:14.2 10 * [0xb04000 - 0xb07fff] mem
1976762.338: PCI: 00:12.0 10 * [0xb08000 - 0xb08fff] mem
1976862.338: PCI: 00:12.1 10 * [0xb09000 - 0xb09fff] mem
1976962.338: PCI: 00:13.0 10 * [0xb0a000 - 0xb0afff] mem
1977062.338: PCI: 00:13.1 10 * [0xb0b000 - 0xb0bfff] mem
1977162.338: PCI: 00:14.5 10 * [0xb0c000 - 0xb0cfff] mem
1977262.338: PCI: 00:11.0 24 * [0xb0d000 - 0xb0d3ff] mem
1977362.338: PCI: 00:12.2 10 * [0xb0e000 - 0xb0e0ff] mem
1977462.338: PCI: 00:13.2 10 * [0xb0f000 - 0xb0f0ff] mem
1977562.338: PCI: 00:14.3 a0 * [0xb10000 - 0xb10000] mem
1977662.338: PCI: 00:18.0 mem: base: b10001 size: c00000 align: 23 gran: 20 limit: ffffffff done
1977762.338: PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem
1977862.338: PCI: 00:18.0 110b8 * [0x4000000 - 0x4bfffff] mem
1977962.338: PCI: 00:18.0 110b0 * [0x4c00000 - 0x4efffff] prefmem
1978062.338: DOMAIN: 0000 mem: base: 4f00000 size: 4f00000 align: 26 gran: 0 limit: ffffffff done
1978162.338: avoid_fixed_resources: DOMAIN: 0000
1978262.338: avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1978362.338: avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1978462.338: constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
1978562.338: constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
1978662.338: constrain_resources: DOMAIN: 0000 08 base 4038000000 limit 403fffffff mem (fixed)
1978762.338: constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
1978862.338: constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed)
1978962.338: constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
1979062.338: constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
1979162.338: constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
1979262.338: constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
1979362.338: avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
1979462.338: avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff
1979562.338: Setting resources...
1979662.338: DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
1979762.338: PCI: 00:18.0 110d8 * [0x1000 - 0x5fff] io
1979862.338: DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
1979962.338: PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
1980062.338: PCI: 00:09.0 1c * [0x1000 - 0x1fff] io
1980162.338: PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
1980262.338: PCI: 00:0d.0 1c * [0x3000 - 0x3fff] io
1980362.338: PCI: 00:14.4 1c * [0x4000 - 0x4fff] io
1980462.338: PCI: 00:11.0 20 * [0x5000 - 0x500f] io
1980562.338: PCI: 00:14.1 20 * [0x5010 - 0x501f] io
1980662.338: PCI: 00:11.0 10 * [0x5020 - 0x5027] io
1980762.338: PCI: 00:11.0 18 * [0x5028 - 0x502f] io
1980862.338: PCI: 00:14.1 10 * [0x5030 - 0x5037] io
1980962.338: PCI: 00:14.1 18 * [0x5038 - 0x503f] io
1981062.339: PCI: 00:11.0 14 * [0x5040 - 0x5043] io
1981162.338: PCI: 00:11.0 1c * [0x5044 - 0x5047] io
1981262.338: PCI: 00:14.1 14 * [0x5048 - 0x504b] io
1981362.338: PCI: 00:14.1 1c * [0x504c - 0x504f] io
1981462.339: PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done
1981562.339: PCI: 00:02.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
1981662.339: PCI: 00:02.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
1981762.339: PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
1981862.339: PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
1981962.339: PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
1982062.339: PCI: 03:00.0 18 * [0x1000 - 0x101f] io
1982162.339: PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
1982262.339: PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
1982362.339: PCI: 04:00.0 18 * [0x2000 - 0x201f] io
1982462.339: PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
1982562.339: PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
1982662.339: PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
1982762.339: PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
1982862.339: PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
1982962.339: PCI: 00:0d.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
1983062.339: PCI: 07:00.0 18 * [0x3000 - 0x301f] io
1983162.339: PCI: 07:00.1 18 * [0x3020 - 0x303f] io
1983262.339: PCI: 00:0d.0 io: next_base: 3040 size: 1000 align: 12 gran: 12 done
1983362.339: PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff
1983462.339: PCI: 08:01.0 18 * [0x4000 - 0x407f] io
1983562.339: PCI: 00:14.4 io: next_base: 4080 size: 1000 align: 12 gran: 12 done
1983662.339: DOMAIN: 0000 mem: base:f8000000 size:4f00000 align:26 gran:0 limit:ffffffff
1983762.339: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem
1983862.339: PCI: 00:18.0 110b8 * [0xfc000000 - 0xfcbfffff] mem
1983962.339: PCI: 00:18.0 110b0 * [0xfcc00000 - 0xfcefffff] prefmem
1984062.339: DOMAIN: 0000 mem: next_base: fcf00000 size: 4f00000 align: 26 gran: 0 done
1984162.339: PCI: 00:18.0 prefmem: base:fcc00000 size:300000 align:20 gran:20 limit:fcefffff
1984262.339: PCI: 00:0d.0 24 * [0xfcc00000 - 0xfcdfffff] prefmem
1984362.339: PCI: 00:00.0 fc * [0xfce00000 - 0xfce000ff] prefmem
1984462.339: PCI: 00:18.0 prefmem: next_base: fce00100 size: 300000 align: 20 gran: 20 done
1984562.339: PCI: 00:02.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1984662.339: PCI: 00:02.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1984762.339: PCI: 00:04.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1984862.339: PCI: 00:04.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1984962.339: PCI: 00:09.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1985062.339: PCI: 00:09.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1985162.339: PCI: 00:0a.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1985262.339: PCI: 00:0a.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1985362.339: PCI: 00:0b.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1985462.339: PCI: 00:0b.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1985562.339: PCI: 00:0c.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1985662.339: PCI: 00:0c.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1985762.339: PCI: 00:0d.0 prefmem: base:fcc00000 size:200000 align:20 gran:20 limit:fcdfffff
1985862.339: PCI: 07:00.0 10 * [0xfcc00000 - 0xfcc7ffff] prefmem
1985962.339: PCI: 07:00.1 10 * [0xfcc80000 - 0xfccfffff] prefmem
1986062.339: PCI: 07:00.0 20 * [0xfcd00000 - 0xfcd03fff] prefmem
1986162.339: PCI: 07:00.1 20 * [0xfcd04000 - 0xfcd07fff] prefmem
1986262.339: PCI: 00:0d.0 prefmem: next_base: fcd08000 size: 200000 align: 20 gran: 20 done
1986362.339: PCI: 00:14.4 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
1986462.339: PCI: 00:14.4 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
1986562.339: PCI: 00:18.0 mem: base:fc000000 size:c00000 align:23 gran:20 limit:fcbfffff
1986662.339: PCI: 00:14.4 20 * [0xfc000000 - 0xfc8fffff] mem
1986762.339: PCI: 00:09.0 20 * [0xfc900000 - 0xfc9fffff] mem
1986862.339: PCI: 00:0a.0 20 * [0xfca00000 - 0xfcafffff] mem
1986962.339: PCI: 00:00.2 44 * [0xfcb00000 - 0xfcb03fff] mem
1987062.339: PCI: 00:14.2 10 * [0xfcb04000 - 0xfcb07fff] mem
1987162.339: PCI: 00:12.0 10 * [0xfcb08000 - 0xfcb08fff] mem
1987262.339: PCI: 00:12.1 10 * [0xfcb09000 - 0xfcb09fff] mem
1987362.339: PCI: 00:13.0 10 * [0xfcb0a000 - 0xfcb0afff] mem
1987462.339: PCI: 00:13.1 10 * [0xfcb0b000 - 0xfcb0bfff] mem
1987562.339: PCI: 00:14.5 10 * [0xfcb0c000 - 0xfcb0cfff] mem
1987662.339: PCI: 00:11.0 24 * [0xfcb0d000 - 0xfcb0d3ff] mem
1987762.339: PCI: 00:12.2 10 * [0xfcb0e000 - 0xfcb0e0ff] mem
1987862.339: PCI: 00:13.2 10 * [0xfcb0f000 - 0xfcb0f0ff] mem
1987962.339: PCI: 00:14.3 a0 * [0xfcb10000 - 0xfcb10000] mem
1988062.339: PCI: 00:18.0 mem: next_base: fcb10001 size: c00000 align: 23 gran: 20 done
1988162.339: PCI: 00:02.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
1988262.339: PCI: 00:02.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
1988362.339: PCI: 00:04.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
1988462.339: PCI: 00:04.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
1988562.339: PCI: 00:09.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff
1988662.339: PCI: 03:00.0 10 * [0xfc900000 - 0xfc91ffff] mem
1988762.339: PCI: 03:00.0 1c * [0xfc920000 - 0xfc923fff] mem
1988862.339: PCI: 00:09.0 mem: next_base: fc924000 size: 100000 align: 20 gran: 20 done
1988962.339: PCI: 00:0a.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff
1989062.339: PCI: 04:00.0 10 * [0xfca00000 - 0xfca1ffff] mem
1989162.339: PCI: 04:00.0 1c * [0xfca20000 - 0xfca23fff] mem
1989262.339: PCI: 00:0a.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done
1989362.339: PCI: 00:0b.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
1989462.339: PCI: 00:0b.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
1989562.339: PCI: 00:0c.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
1989662.339: PCI: 00:0c.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
1989762.339: PCI: 00:0d.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
1989862.339: PCI: 00:0d.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
1989962.339: PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff
1990062.339: PCI: 08:01.0 10 * [0xfc000000 - 0xfc7fffff] mem
1990162.339: PCI: 08:01.0 14 * [0xfc800000 - 0xfc81ffff] mem
1990262.339: PCI: 08:02.0 10 * [0xfc820000 - 0xfc820fff] mem
1990362.339: PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done
1990462.339: Root Device assign_resources, bus 0 link: 0
1990562.339: 0: mmio_basek=00300000, basek=00400000, limitk=04100000
1990662.339: 1: mmio_basek=00300000, basek=04100000, limitk=08100000
1990762.339: 2: mmio_basek=00300000, basek=08100000, limitk=0c100000
1990862.339: 3: mmio_basek=00300000, basek=0c100000, limitk=10100000
1990962.339: DOMAIN: 0000 assign_resources, bus 0 link: 0
1991062.339: VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
1991162.339: PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
1991262.339: PCI: 00:18.0 110b0 <- [0x00fcc00000 - 0x00fcefffff] size 0x00300000 gran 0x14 prefmem <node 0 link 1>
1991362.339: PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fcbfffff] size 0x00c00000 gran 0x14 mem <node 0 link 1>
1991462.339: PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1>
1991562.339: PCI: 00:18.0 assign_resources, bus 0 link: 1
1991662.339: PCI: 00:00.0 sr5690_set_resources
1991762.339: sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
1991862.339: PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig>
1991962.339: sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90
1992062.339: PCI: 00:00.0 fc <- [0x00fce00000 - 0x00fce000ff] size 0x00000100 gran 0x08 prefmem
1992162.340: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
1992262.340: CBFS: Locating 'cmos_layout.bin'
1992362.340: CBFS: Found @ offset 2b0c0 size e88
1992462.340: PCI: 00:00.2 44 <- [0x00fcb00000 - 0x00fcb03fff] size 0x00004000 gran 0x0e mem
1992562.340: PCI: 00:02.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 01 io
1992662.340: PCI: 00:02.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1992762.340: PCI: 00:02.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 01 mem
1992862.340: PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
1992962.340: PCI: 00:04.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 02 prefmem
1993062.340: PCI: 00:04.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 02 mem
1993162.340: PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
1993262.340: PCI: 00:09.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 03 prefmem
1993362.340: PCI: 00:09.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 03 mem
1993462.340: PCI: 00:09.0 assign_resources, bus 3 link: 0
1993562.340: PCI: 03:00.0 10 <- [0x00fc900000 - 0x00fc91ffff] size 0x00020000 gran 0x11 mem
1993662.340: PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
1993762.340: PCI: 03:00.0 1c <- [0x00fc920000 - 0x00fc923fff] size 0x00004000 gran 0x0e mem
1993862.340: PCI: 00:09.0 assign_resources, bus 3 link: 0
1993962.340: PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
1994062.340: PCI: 00:0a.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 04 prefmem
1994162.340: PCI: 00:0a.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 04 mem
1994262.340: PCI: 00:0a.0 assign_resources, bus 4 link: 0
1994362.340: PCI: 04:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem
1994462.340: PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
1994562.340: PCI: 04:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem
1994662.340: PCI: 00:0a.0 assign_resources, bus 4 link: 0
1994762.340: PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io
1994862.340: PCI: 00:0b.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 05 prefmem
1994962.340: PCI: 00:0b.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 05 mem
1995062.340: PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io
1995162.340: PCI: 00:0c.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 06 prefmem
1995262.340: PCI: 00:0c.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 06 mem
1995362.340: PCI: 00:0d.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 07 io
1995462.340: PCI: 00:0d.0 24 <- [0x00fcc00000 - 0x00fcdfffff] size 0x00200000 gran 0x14 bus 07 prefmem
1995562.340: PCI: 00:0d.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 07 mem
1995662.340: PCI: 00:0d.0 assign_resources, bus 7 link: 0
1995762.340: PCI: 07:00.0 10 <- [0x00fcc00000 - 0x00fcc7ffff] size 0x00080000 gran 0x13 prefmem64
1995862.340: PCI: 07:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
1995962.340: PCI: 07:00.0 20 <- [0x00fcd00000 - 0x00fcd03fff] size 0x00004000 gran 0x0e prefmem64
1996062.340: PCI: 07:00.1 10 <- [0x00fcc80000 - 0x00fccfffff] size 0x00080000 gran 0x13 prefmem64
1996162.340: PCI: 07:00.1 18 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io
1996262.340: PCI: 07:00.1 20 <- [0x00fcd04000 - 0x00fcd07fff] size 0x00004000 gran 0x0e prefmem64
1996362.340: PCI: 00:0d.0 assign_resources, bus 7 link: 0
1996462.340: PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io
1996562.340: PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io
1996662.340: PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io
1996762.341: PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io
1996862.340: PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io
1996962.340: PCI: 00:11.0 24 <- [0x00fcb0d000 - 0x00fcb0d3ff] size 0x00000400 gran 0x0a mem
1997062.340: PCI: 00:12.0 10 <- [0x00fcb08000 - 0x00fcb08fff] size 0x00001000 gran 0x0c mem
1997162.340: PCI: 00:12.1 10 <- [0x00fcb09000 - 0x00fcb09fff] size 0x00001000 gran 0x0c mem
1997262.341: PCI: 00:12.2 10 <- [0x00fcb0e000 - 0x00fcb0e0ff] size 0x00000100 gran 0x08 mem
1997362.341: PCI: 00:13.0 10 <- [0x00fcb0a000 - 0x00fcb0afff] size 0x00001000 gran 0x0c mem
1997462.341: PCI: 00:13.1 10 <- [0x00fcb0b000 - 0x00fcb0bfff] size 0x00001000 gran 0x0c mem
1997562.341: PCI: 00:13.2 10 <- [0x00fcb0f000 - 0x00fcb0f0ff] size 0x00000100 gran 0x08 mem
1997662.341: PCI: 00:14.0 assign_resources, bus 1 link: 0
1997762.341: PCI: 00:14.0 assign_resources, bus 1 link: 0
1997862.341: PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io
1997962.341: PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io
1998062.341: PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io
1998162.341: PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io
1998262.341: PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io
1998362.341: PCI: 00:14.2 10 <- [0x00fcb04000 - 0x00fcb07fff] size 0x00004000 gran 0x0e mem64
1998462.341: PCI: 00:14.3 a0 <- [0x00fcb10000 - 0x00fcb10000] size 0x00000001 gran 0x00 mem
1998562.341: PCI: 00:14.3 assign_resources, bus 0 link: 0
1998662.341: PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
1998762.341: PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
1998862.341: PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
1998962.341: PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
1999062.341: PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
1999162.341: PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
1999262.341: PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
1999362.341: PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
1999462.341: PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
1999562.341: ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
1999662.341: PCI: 00:14.3 assign_resources, bus 0 link: 0
1999762.341: PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io
1999862.341: PCI: 00:14.4 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 08 prefmem
1999962.341: PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem
2000062.341: PCI: 00:14.4 assign_resources, bus 8 link: 0
2000162.341: PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem
2000262.341: PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem
2000362.341: PCI: 08:01.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io
2000462.341: PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem
2000562.341: PCI: 00:14.4 assign_resources, bus 8 link: 0
2000662.341: PCI: 00:14.5 10 <- [0x00fcb0c000 - 0x00fcb0cfff] size 0x00001000 gran 0x0c mem
2000762.341: PCI: 00:18.0 assign_resources, bus 0 link: 1
2000862.341: PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
2000962.341: PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
2001062.341: PCI: 00:1a.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
2001162.341: PCI: 00:1b.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
2001262.341: DOMAIN: 0000 assign_resources, bus 0 link: 0
2001362.341: Root Device assign_resources, bus 0 link: 0
2001462.341: Done setting resources.
2001562.341: Show resources in subtree (Root Device)...After assigning values.
2001662.341: Root Device child on link 0 CPU_CLUSTER: 0
2001762.341: CPU_CLUSTER: 0 child on link 0 APIC: 00
2001862.341: APIC: 00
2001962.341: APIC: 01
2002062.341: APIC: 02
2002162.341: APIC: 03
2002262.341: APIC: 04
2002362.341: APIC: 05
2002462.341: APIC: 06
2002562.341: APIC: 07
2002662.341: APIC: 08
2002762.341: APIC: 09
2002862.341: APIC: 0a
2002962.341: APIC: 0b
2003062.341: APIC: 0c
2003162.342: APIC: 0d
2003262.342: APIC: 0e
2003362.342: APIC: 0f
2003462.342: APIC: 20
2003562.342: APIC: 21
2003662.342: APIC: 22
2003762.342: APIC: 23
2003862.342: APIC: 24
2003962.342: APIC: 25
2004062.342: APIC: 26
2004162.342: APIC: 27
2004262.342: APIC: 28
2004362.342: APIC: 29
2004462.342: APIC: 2a
2004562.342: APIC: 2b
2004662.342: APIC: 2c
2004762.342: APIC: 2d
2004862.342: APIC: 2e
2004962.342: APIC: 2f
2005062.342: DOMAIN: 0000 child on link 0 PCI: 00:18.0
2005162.342: DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
2005262.342: DOMAIN: 0000 resource base f8000000 size 4f00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100
2005362.342: DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
2005462.342: DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
2005562.342: DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
2005662.342: DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
2005762.342: DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
2005862.342: DOMAIN: 0000 resource base 100000000 size f40000000 align 0 gran 0 limit 0 flags e0004200 index 30
2005962.342: DOMAIN: 0000 resource base 1040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 41
2006062.342: DOMAIN: 0000 resource base 2040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 52
2006162.342: DOMAIN: 0000 resource base 3040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 63
2006262.342: PCI: 00:18.0
2006362.342: PCI: 00:18.0 resource base fcc00000 size 300000 align 20 gran 20 limit fcefffff flags 60081200 index 110b0
2006462.342: PCI: 00:18.0 resource base fc000000 size c00000 align 23 gran 20 limit fcbfffff flags 60080200 index 110b8
2006562.342: PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8
2006662.342: PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8
2006762.342: PCI: 00:00.0
2006862.342: PCI: 00:00.0 resource base fce00000 size 100 align 12 gran 8 limit fce000ff flags 60001200 index fc
2006962.342: PCI: 00:00.1
2007062.342: PCI: 00:00.2
2007162.342: PCI: 00:00.2 resource base fcb00000 size 4000 align 14 gran 14 limit fcb03fff flags 70000200 index 44
2007262.342: PCI: 00:02.0
2007362.342: PCI: 00:02.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
2007462.342: PCI: 00:02.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2007562.342: PCI: 00:02.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
2007662.342: PCI: 00:03.0
2007762.342: PCI: 00:04.0
2007862.342: PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
2007962.342: PCI: 00:04.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2008062.342: PCI: 00:04.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
2008162.342: PCI: 00:05.0
2008262.342: PCI: 00:06.0
2008362.343: PCI: 00:07.0
2008462.343: PCI: 00:08.0
2008562.343: PCI: 00:09.0 child on link 0 PCI: 03:00.0
2008662.343: PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
2008762.343: PCI: 00:09.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2008862.343: PCI: 00:09.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20
2008962.343: PCI: 03:00.0
2009062.343: PCI: 03:00.0 resource base fc900000 size 20000 align 17 gran 17 limit fc91ffff flags 60000200 index 10
2009162.343: PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
2009262.343: PCI: 03:00.0 resource base fc920000 size 4000 align 14 gran 14 limit fc923fff flags 60000200 index 1c
2009362.343: PCI: 00:0a.0 child on link 0 PCI: 04:00.0
2009462.343: PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
2009562.343: PCI: 00:0a.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2009662.343: PCI: 00:0a.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20
2009762.343: PCI: 04:00.0
2009862.343: PCI: 04:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10
2009962.343: PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
2010062.343: PCI: 04:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c
2010162.343: PCI: 00:0b.0
2010262.343: PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
2010362.343: PCI: 00:0b.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2010462.343: PCI: 00:0b.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
2010562.343: PCI: 00:0c.0
2010662.343: PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
2010762.343: PCI: 00:0c.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2010862.343: PCI: 00:0c.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
2010962.343: PCI: 00:0d.0 child on link 0 PCI: 07:00.0
2011062.343: PCI: 00:0d.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
2011162.343: PCI: 00:0d.0 resource base fcc00000 size 200000 align 20 gran 20 limit fcdfffff flags 60081202 index 24
2011262.343: PCI: 00:0d.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
2011362.343: PCI: 07:00.0
2011462.343: PCI: 07:00.0 resource base fcc00000 size 80000 align 19 gran 19 limit fcc7ffff flags 60001201 index 10
2011562.343: PCI: 07:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18
2011662.343: PCI: 07:00.0 resource base fcd00000 size 4000 align 14 gran 14 limit fcd03fff flags 60001201 index 20
2011762.343: PCI: 07:00.1
2011862.343: PCI: 07:00.1 resource base fcc80000 size 80000 align 19 gran 19 limit fccfffff flags 60001201 index 10
2011962.343: PCI: 07:00.1 resource base 3020 size 20 align 5 gran 5 limit 303f flags 60000100 index 18
2012062.343: PCI: 07:00.1 resource base fcd04000 size 4000 align 14 gran 14 limit fcd07fff flags 60001201 index 20
2012162.343: PCI: 00:11.0
2012262.343: PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10
2012362.343: PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14
2012462.343: PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18
2012562.343: PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c
2012662.343: PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20
2012762.343: PCI: 00:11.0 resource base fcb0d000 size 400 align 12 gran 10 limit fcb0d3ff flags 60000200 index 24
2012862.343: PCI: 00:12.0
2012962.343: PCI: 00:12.0 resource base fcb08000 size 1000 align 12 gran 12 limit fcb08fff flags 60000200 index 10
2013062.343: PCI: 00:12.1
2013162.343: PCI: 00:12.1 resource base fcb09000 size 1000 align 12 gran 12 limit fcb09fff flags 60000200 index 10
2013262.343: PCI: 00:12.2
2013362.343: PCI: 00:12.2 resource base fcb0e000 size 100 align 12 gran 8 limit fcb0e0ff flags 60000200 index 10
2013462.343: PCI: 00:13.0
2013562.343: PCI: 00:13.0 resource base fcb0a000 size 1000 align 12 gran 12 limit fcb0afff flags 60000200 index 10
2013662.343: PCI: 00:13.1
2013762.343: PCI: 00:13.1 resource base fcb0b000 size 1000 align 12 gran 12 limit fcb0bfff flags 60000200 index 10
2013862.343: PCI: 00:13.2
2013962.343: PCI: 00:13.2 resource base fcb0f000 size 100 align 12 gran 8 limit fcb0f0ff flags 60000200 index 10
2014062.343: PCI: 00:14.0 child on link 0 I2C: 01:50
2014162.343: PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
2014262.343: PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
2014362.343: PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
2014462.343: PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
2014562.343: PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
2014662.343: I2C: 01:50
2014762.343: I2C: 01:51
2014862.343: I2C: 01:52
2014962.343: I2C: 01:53
2015062.343: I2C: 01:54
2015162.343: I2C: 01:55
2015262.343: I2C: 01:56
2015362.344: I2C: 01:57
2015462.344: I2C: 01:2f
2015562.344: PCI: 00:14.1
2015662.344: PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10
2015762.344: PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14
2015862.344: PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18
2015962.344: PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c
2016062.344: PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20
2016162.344: PCI: 00:14.2
2016262.344: PCI: 00:14.2 resource base fcb04000 size 4000 align 14 gran 14 limit fcb07fff flags 60000201 index 10
2016362.344: PCI: 00:14.3 child on link 0 PNP: 002e.0
2016462.344: PCI: 00:14.3 resource base fcb10000 size 1 align 12 gran 0 limit fcb10000 flags 60000200 index a0
2016562.344: PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
2016662.344: PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
2016762.344: PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
2016862.344: PNP: 002e.0
2016962.344: PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
2017062.344: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
2017162.344: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
2017262.344: PNP: 002e.1
2017362.344: PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
2017462.344: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
2017562.344: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
2017662.344: PNP: 002e.2
2017762.344: PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
2017862.344: PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
2017962.344: PNP: 002e.3
2018062.344: PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
2018162.344: PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
2018262.344: PNP: 002e.5
2018362.344: PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
2018462.344: PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
2018562.344: PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
2018662.344: PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
2018762.344: PNP: 002e.106
2018862.344: PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
2018962.344: PNP: 002e.107
2019062.344: PNP: 002e.207
2019162.344: PNP: 002e.307
2019262.344: PNP: 002e.407
2019362.344: PNP: 002e.8
2019462.344: PNP: 002e.108
2019562.344: PNP: 002e.9
2019662.344: PNP: 002e.109
2019762.344: PNP: 002e.209
2019862.344: PNP: 002e.309
2019962.344: PNP: 002e.a
2020062.344: PNP: 002e.b
2020162.344: PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
2020262.344: PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
2020362.344: PNP: 002e.c
2020462.344: PNP: 002e.d
2020562.344: PNP: 002e.f
2020662.344: PNP: 004e.0
2020762.345: PCI: 00:14.4 child on link 0 PCI: 08:01.0
2020862.345: PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
2020962.345: PCI: 00:14.4 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
2021062.345: PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20
2021162.345: PCI: 08:01.0
2021262.345: PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10
2021362.345: PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14
2021462.345: PCI: 08:01.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18
2021562.345: PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
2021662.345: PCI: 08:02.0
2021762.345: PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10
2021862.345: PCI: 08:03.0
2021962.345: PCI: 00:14.5
2022062.345: PCI: 00:14.5 resource base fcb0c000 size 1000 align 12 gran 12 limit fcb0cfff flags 60000200 index 10
2022162.345: PCI: 00:18.1
2022262.345: PCI: 00:18.2
2022362.345: PCI: 00:18.3
2022462.345: PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94
2022562.345: PCI: 00:18.4
2022662.345: PCI: 00:18.5
2022762.345: PCI: 00:19.0
2022862.345: PCI: 00:19.1
2022962.345: PCI: 00:19.2
2023062.345: PCI: 00:19.3
2023162.345: PCI: 00:19.4
2023262.345: PCI: 00:19.5
2023362.345: PCI: 00:1a.0
2023462.345: PCI: 00:1a.1
2023562.345: PCI: 00:1a.2
2023662.345: PCI: 00:1a.3
2023762.345: PCI: 00:1a.4
2023862.345: PCI: 00:1a.5
2023962.345: PCI: 00:1b.0
2024062.345: PCI: 00:1b.1
2024162.345: PCI: 00:1b.2
2024262.345: PCI: 00:1b.3
2024362.345: PCI: 00:1b.4
2024462.345: PCI: 00:1b.5
2024562.345: Done allocating resources.
2024662.345: BS: BS_DEV_RESOURCES times (us): entry 0 run 3292370 exit 0
2024762.345: Enabling resources...
2024862.345: PCI: 00:18.0 cmd <- 00
2024962.345: PCI: 00:18.1 subsystem <- 1043/8163
2025062.346: PCI: 00:18.1 cmd <- 00
2025162.346: PCI: 00:18.2 subsystem <- 1043/8163
2025262.346: PCI: 00:18.2 cmd <- 00
2025362.346: PCI: 00:18.3 cmd <- 00
2025462.346: PCI: 00:18.4 cmd <- 00
2025562.346: PCI: 00:18.5 cmd <- 00
2025662.346: PCI: 00:19.0 cmd <- 00
2025762.346: PCI: 00:19.1 subsystem <- 1043/8163
2025862.346: PCI: 00:19.1 cmd <- 00
2025962.346: PCI: 00:19.2 subsystem <- 1043/8163
2026062.346: PCI: 00:19.2 cmd <- 00
2026162.346: PCI: 00:19.3 cmd <- 00
2026262.346: PCI: 00:19.4 cmd <- 00
2026362.346: PCI: 00:19.5 cmd <- 00
2026462.346: PCI: 00:1a.0 cmd <- 00
2026562.346: PCI: 00:1a.1 subsystem <- 1043/8163
2026662.346: PCI: 00:1a.1 cmd <- 00
2026762.346: PCI: 00:1a.2 subsystem <- 1043/8163
2026862.346: PCI: 00:1a.2 cmd <- 00
2026962.346: PCI: 00:1a.3 cmd <- 00
2027062.346: PCI: 00:1a.4 cmd <- 00
2027162.346: PCI: 00:1a.5 cmd <- 00
2027262.346: PCI: 00:1b.0 cmd <- 00
2027362.346: PCI: 00:1b.1 subsystem <- 1043/8163
2027462.346: PCI: 00:1b.1 cmd <- 00
2027562.346: PCI: 00:1b.2 subsystem <- 1043/8163
2027662.346: PCI: 00:1b.2 cmd <- 00
2027762.346: PCI: 00:1b.3 cmd <- 00
2027862.346: PCI: 00:1b.4 cmd <- 00
2027962.346: PCI: 00:1b.5 cmd <- 00
2028062.346: PCI: 00:00.0 subsystem <- 1043/8163
2028162.346: PCI: 00:00.0 cmd <- 02
2028262.346: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2028362.346: CBFS: Locating 'cmos_layout.bin'
2028462.346: CBFS: Found @ offset 2b0c0 size e88
2028562.347: Initializing IOMMU
2028662.347: PCI: 00:02.0 bridge ctrl <- 0003
2028762.347: PCI: 00:02.0 cmd <- 00
2028862.347: PCI: 00:04.0 bridge ctrl <- 0003
2028962.347: PCI: 00:04.0 cmd <- 00
2029062.347: PCI: 00:09.0 bridge ctrl <- 0003
2029162.347: PCI: 00:09.0 cmd <- 07
2029262.347: PCI: 00:0a.0 bridge ctrl <- 0003
2029362.347: PCI: 00:0a.0 cmd <- 07
2029462.347: PCI: 00:0b.0 bridge ctrl <- 0003
2029562.347: PCI: 00:0b.0 cmd <- 00
2029662.347: PCI: 00:0c.0 bridge ctrl <- 0003
2029762.347: PCI: 00:0c.0 cmd <- 00
2029862.347: PCI: 00:0d.0 bridge ctrl <- 0003
2029962.347: PCI: 00:0d.0 cmd <- 07
2030062.347: PCI: 00:11.0 subsystem <- 1043/8163
2030162.347: PCI: 00:11.0 cmd <- 03
2030262.347: PCI: 00:12.0 subsystem <- 1043/8163
2030362.347: PCI: 00:12.0 cmd <- 02
2030462.347: PCI: 00:12.1 subsystem <- 1043/8163
2030562.347: PCI: 00:12.1 cmd <- 02
2030662.347: PCI: 00:12.2 subsystem <- 1043/8163
2030762.347: PCI: 00:12.2 cmd <- 02
2030862.347: PCI: 00:13.0 subsystem <- 1043/8163
2030962.347: PCI: 00:13.0 cmd <- 02
2031062.347: PCI: 00:13.1 subsystem <- 1043/8163
2031162.347: PCI: 00:13.1 cmd <- 02
2031262.347: PCI: 00:13.2 subsystem <- 1043/8163
2031362.347: PCI: 00:13.2 cmd <- 02
2031462.347: PCI: 00:14.0 subsystem <- 1043/8163
2031562.347: PCI: 00:14.0 cmd <- 403
2031662.347: PCI: 00:14.1 subsystem <- 1043/8163
2031762.347: PCI: 00:14.1 cmd <- 01
2031862.347: PCI: 00:14.2 subsystem <- 1043/8163
2031962.347: PCI: 00:14.2 cmd <- 02
2032062.347: PCI: 00:14.3 subsystem <- 1043/8163
2032162.347: PCI: 00:14.3 cmd <- 0f
2032262.347: sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
2032362.347: sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
2032462.347: sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
2032562.347: sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
2032662.347: sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
2032762.347: PCI: 00:14.4 bridge ctrl <- 000b
2032862.347: PCI: 00:14.4 cmd <- 07
2032962.347: PCI: 00:14.5 subsystem <- 1043/8163
2033062.347: PCI: 00:14.5 cmd <- 02
2033162.347: PCI: 03:00.0 cmd <- 03
2033262.347: PCI: 04:00.0 cmd <- 03
2033362.347: PCI: 07:00.0 cmd <- 03
2033462.347: PCI: 07:00.1 cmd <- 03
2033562.347: PCI: 08:01.0 cmd <- 03
2033662.347: PCI: 08:02.0 subsystem <- 1043/8163
2033762.347: PCI: 08:02.0 cmd <- 02
2033862.347: done.
2033962.347: BS: BS_DEV_ENABLE times (us): entry 0 run 178661 exit 0
2034062.348: Initializing devices...
2034162.347: Root Device init ...
2034262.347: Root Device init finished in 1398 usecs
2034362.348: CPU_CLUSTER: 0 init ...
2034462.348: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2034562.348: CBFS: Locating 'cmos_layout.bin'
2034662.348: CBFS: Found @ offset 2b0c0 size e88
2034762.348: Enabling probe filter
2034862.353: Enabling ATM mode
2034962.353: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2035062.353: CBFS: Locating 'cmos_layout.bin'
2035162.353: CBFS: Found @ offset 2b0c0 size e88
2035262.354: start_eip=0x00001000, code_size=0x00000031
2035362.354: CPU1: stack_base 00150000, stack_end 00150ff8
2035462.354: Asserting INIT.
2035562.354: Waiting for send to finish...
2035662.354: +Deasserting INIT.
2035762.354: Waiting for send to finish...
2035862.354: +#startup loops: 1.
2035962.354: Sending STARTUP #1 to 1.
2036062.354: After apic_write.
2036162.354: Initializing CPU #1
2036262.354: Startup point 1.
2036362.354: Waiting for send to finish...
2036462.354: +CPU: vendor AMD device 600f12
2036562.354: After Startup.
2036662.354: CPU: family 15, model 01, stepping 02
2036762.354: CPU2: stack_base 0014f000, stack_end 0014fff8
2036862.354: nodeid = 00, coreid = 01
2036962.354: Asserting INIT.
2037062.354: Enabling cache
2037162.354: Waiting for send to finish...
2037262.354: +Deasserting INIT.
2037362.355: Waiting for send to finish...
2037462.355: +#startup loops: 1.
2037562.355: Sending STARTUP #1 to 2.
2037662.355: After apic_write.
2037762.355: Initializing CPU #2
2037862.355: Startup point 1.
2037962.355: Waiting for send to finish...
2038062.355: +CPU: vendor AMD device 600f12
2038162.355: After Startup.
2038262.355: CPU3: stack_base 0014e000, stack_end 0014eff8
2038362.355: CPU: family 15, model 01, stepping 02
2038462.355: Asserting INIT.
2038562.355: Waiting for send to finish...
2038662.355: +nodeid = 00, coreid = 02
2038762.355: Deasserting INIT.
2038862.355: Waiting for send to finish...
2038962.355: +Enabling cache
2039062.355: #startup loops: 1.
2039162.355: Sending STARTUP #1 to 3.
2039262.355: After apic_write.
2039362.355: CPU ID 0x80000001: 600f12
2039462.355: Startup point 1.
2039562.355: Waiting for send to finish...
2039662.355: +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2039762.355: After Startup.
2039862.355: CPU4: stack_base 0014d000, stack_end 0014dff8
2039962.355: Initializing CPU #3
2040062.355: MTRR: Physical address space:
2040162.355: Asserting INIT.
2040262.355: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
2040362.355: Waiting for send to finish...
2040462.355: +CPU: vendor AMD device 600f12
2040562.355: Deasserting INIT.
2040662.355: CPU: family 15, model 01, stepping 02
2040762.355: Waiting for send to finish...
2040862.355: +nodeid = 00, coreid = 03
2040962.355: #startup loops: 1.
2041062.355: Sending STARTUP #1 to 4.
2041162.355: After apic_write.
2041262.355: Enabling cache
2041362.355: 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
2041462.355: 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
2041562.355: Startup point 1.
2041662.355: Waiting for send to finish...
2041762.355: +0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
2041862.356: 0x0000000100000000 - 0x0000004040000000 size 0x3f40000000 type 6
2041962.356: Initializing CPU #4
2042062.356: After Startup.
2042162.356: CPU: vendor AMD device 600f12
2042262.356: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2042362.356: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2042462.356: CPU5: stack_base 0014c000, stack_end 0014cff8
2042562.356: MTRR: Fixed MSR 0x259 0x0000000000000000
2042662.356: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2042762.356: Asserting INIT.
2042862.356: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2042962.356: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2043062.356: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2043162.356: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2043262.356: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2043362.356: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2043462.356: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2043562.356: Waiting for send to finish...
2043662.356: +CPU: family 15, model 01, stepping 02
2043762.356: Deasserting INIT.
2043862.356: MTRR: default type WB/UC MTRR counts: 1/2.
2043962.356: MTRR: WB selected as default type.
2044062.356: Waiting for send to finish...
2044162.356: MTRR: 0 base 0x00000000c0000000 mask 0x0000ffffc0000000 type 0
2044262.356: +nodeid = 00, coreid = 04
2044362.356: #startup loops: 1.
2044462.356:
2044562.356: MTRR check
2044662.356: Sending STARTUP #1 to 5.
2044762.356: After apic_write.
2044862.356: Fixed MTRRs : Enabled
2044962.356: Variable MTRRs: Startup point 1.
2045062.356: Waiting for send to finish...
2045162.356: Enabled
2045262.356:
2045362.356: +Initializing CPU #5
2045462.356: After Startup.
2045562.356: Enabling cache
2045662.356: CPU6: stack_base 0014b000, stack_end 0014bff8
2045762.356: Setting up local APIC...Asserting INIT.
2045862.356: apic_id: 0x02 done.
2045962.356: Waiting for send to finish...
2046062.356: +CPU model: AMD Opteron(tm) Processor 6278
2046162.356: Deasserting INIT.
2046262.356: siblings = 15, Waiting for send to finish...
2046362.356: +Disabling SMM ASeg memory
2046462.356: #startup loops: 1.
2046562.356: Sending STARTUP #1 to 6.
2046662.356: After apic_write.
2046762.356: CPU #2 initialized
2046862.356: Startup point 1.
2046962.356: Waiting for send to finish...
2047062.356: +
2047162.356: MTRR check
2047262.356: Fixed MTRRs : Enabled
2047362.356: Variable MTRRs: Enabled
2047462.357:
2047562.357: After Startup.
2047662.357: CPU7: stack_base 0014a000, stack_end 0014aff8
2047762.357: Setting up local APIC...Asserting INIT.
2047862.357: apic_id: 0x03 done.
2047962.357: Waiting for send to finish...
2048062.357: CPU model: AMD Opteron(tm) Processor 6278
2048162.357: +siblings = 15, Deasserting INIT.
2048262.357: Disabling SMM ASeg memory
2048362.357: Waiting for send to finish...
2048462.357: +CPU #3 initialized
2048562.357: #startup loops: 1.
2048662.357: Sending STARTUP #1 to 7.
2048762.357: CPU: vendor AMD device 600f12
2048862.357: Initializing CPU #6
2048962.357: After apic_write.
2049062.357: CPU: family 15, model 01, stepping 02
2049162.357: Startup point 1.
2049262.357: Waiting for send to finish...
2049362.357: +CPU: vendor AMD device 600f12
2049462.357: After Startup.
2049562.357: CPU8: stack_base 00149000, stack_end 00149ff8
2049662.357: CPU: family 15, model 01, stepping 02
2049762.357: Asserting INIT.
2049862.357: Initializing CPU #7
2049962.357: Waiting for send to finish...
2050062.357: +nodeid = 00, coreid = 06
2050162.357: Deasserting INIT.
2050262.357: nodeid = 00, coreid = 05
2050362.357: CPU ID 0x80000001: 600f12
2050462.357: Waiting for send to finish...
2050562.357: +Enabling cache
2050662.357: #startup loops: 1.
2050762.357: Sending STARTUP #1 to 8.
2050862.357: After apic_write.
2050962.357: CPU: vendor AMD device 600f12
2051062.357: Startup point 1.
2051162.357: Waiting for send to finish...
2051262.357: +Enabling cache
2051362.357: After Startup.
2051462.357: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2051562.357: CPU9: stack_base 00148000, stack_end 00148ff8
2051662.357: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2051762.357: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2051862.357: MTRR: Fixed MSR 0x259 0x0000000000000000
2051962.357: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2052062.357: Asserting INIT.
2052162.357: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2052262.357: Waiting for send to finish...
2052362.357: +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2052462.357: Deasserting INIT.
2052562.357: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2052662.357: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2052762.357: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2052862.357: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2052962.358: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2053062.357: Waiting for send to finish...
2053162.358: +Initializing CPU #8
2053262.358: #startup loops: 1.
2053362.358: Sending STARTUP #1 to 9.
2053462.358:
2053562.358: MTRR check
2053662.358: Fixed MTRRs : Enabled
2053762.358: After apic_write.
2053862.358: Variable MTRRs: Enabled
2053962.358:
2054062.358: Startup point 1.
2054162.358: Waiting for send to finish...
2054262.358: +Setting up local APIC...After Startup.
2054362.358: CPU10: stack_base 00147000, stack_end 00147ff8
2054462.358: apic_id: 0x04 done.
2054562.358: Asserting INIT.
2054662.358: CPU model: AMD Opteron(tm) Processor 6278
2054762.358: Waiting for send to finish...
2054862.358: +siblings = 15, Deasserting INIT.
2054962.358: Disabling SMM ASeg memory
2055062.358: Waiting for send to finish...
2055162.358: +
2055262.358: MTRR check
2055362.358: Fixed MTRRs : Enabled
2055462.358: Variable MTRRs: #startup loops: 1.
2055562.358: CPU #4 initialized
2055662.358: Sending STARTUP #1 to 10.
2055762.358: Enabled
2055862.358:
2055962.358: After apic_write.
2056062.358: CPU: family 15, model 01, stepping 02
2056162.358: Startup point 1.
2056262.358: Setting up local APIC...Waiting for send to finish...
2056362.358: + apic_id: 0x05 done.
2056462.358: After Startup.
2056562.358: CPU11: stack_base 00146000, stack_end 00146ff8
2056662.358: CPU model: AMD Opteron(tm) Processor 6278
2056762.358: Asserting INIT.
2056862.358: siblings = 15, Waiting for send to finish...
2056962.358: +Disabling SMM ASeg memory
2057062.358: Deasserting INIT.
2057162.358: CPU #5 initialized
2057262.358: Waiting for send to finish...
2057362.358: +nodeid = 00, coreid = 07
2057462.358: #startup loops: 1.
2057562.358: Sending STARTUP #1 to 11.
2057662.358: After apic_write.
2057762.358: Enabling cache
2057862.358: Initializing CPU #9
2057962.358: CPU ID 0x80000001: 600f12
2058062.359: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2058162.358: Startup point 1.
2058262.359: Waiting for send to finish...
2058362.359: +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2058462.359: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2058562.359: MTRR: Fixed MSR 0x259 0x0000000000000000
2058662.359: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2058762.359: After Startup.
2058862.359: CPU12: stack_base 00145000, stack_end 00145ff8
2058962.359: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2059062.359: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2059162.359: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2059262.359: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2059362.359: Asserting INIT.
2059462.359: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2059562.359: Waiting for send to finish...
2059662.359: +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2059762.359: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2059862.359: Deasserting INIT.
2059962.359: Waiting for send to finish...
2060062.359: +CPU: vendor AMD device 600f12
2060162.359: #startup loops: 1.
2060262.359:
2060362.359: MTRR check
2060462.359: Fixed MTRRs : Enabled
2060562.359: Variable MTRRs: Enabled
2060662.359:
2060762.359: Sending STARTUP #1 to 12.
2060862.359: After apic_write.
2060962.359: Setting up local APIC...Startup point 1.
2061062.359: Waiting for send to finish...
2061162.359: apic_id: 0x06 done.
2061262.359: +CPU model: AMD Opteron(tm) Processor 6278
2061362.359: After Startup.
2061462.359: CPU13: stack_base 00144000, stack_end 00144ff8
2061562.359: siblings = 15, Asserting INIT.
2061662.359: Disabling SMM ASeg memory
2061762.359: Waiting for send to finish...
2061862.359: +
2061962.359: MTRR check
2062062.359: Deasserting INIT.
2062162.359: Fixed MTRRs : Enabled
2062262.359: Waiting for send to finish...
2062362.359: CPU #6 initialized
2062462.359: +Variable MTRRs: Enabled
2062562.359:
2062662.359: #startup loops: 1.
2062762.359: Sending STARTUP #1 to 13.
2062862.359: Setting up local APIC...After apic_write.
2062962.359: apic_id: 0x07 done.
2063062.359: Startup point 1.
2063162.359: CPU model: AMD Opteron(tm) Processor 6278
2063262.359: Waiting for send to finish...
2063362.359: +siblings = 15, After Startup.
2063462.359: Disabling SMM ASeg memory
2063562.360: CPU14: stack_base 00143000, stack_end 00143ff8
2063662.360: CPU #7 initialized
2063762.360: Asserting INIT.
2063862.360: Waiting for send to finish...
2063962.360: +Initializing CPU #10
2064062.360: Deasserting INIT.
2064162.360: Waiting for send to finish...
2064262.360: +Initializing CPU #11
2064362.360: #startup loops: 1.
2064462.360: Sending STARTUP #1 to 14.
2064562.360: After apic_write.
2064662.360: CPU: family 15, model 01, stepping 02
2064762.360: Startup point 1.
2064862.360: Waiting for send to finish...
2064962.360: +Initializing CPU #14
2065062.360: After Startup.
2065162.360: CPU15: stack_base 00142000, stack_end 00142ff8
2065262.360: CPU: vendor AMD device 600f12
2065362.360: Asserting INIT.
2065462.360: Initializing CPU #12
2065562.360: Waiting for send to finish...
2065662.360: +CPU: vendor AMD device 600f12
2065762.360: Deasserting INIT.
2065862.360: Waiting for send to finish...
2065962.360: +nodeid = 01, coreid = 00
2066062.360: #startup loops: 1.
2066162.360: Sending STARTUP #1 to 15.
2066262.360: After apic_write.
2066362.360: CPU: vendor AMD device 600f12
2066462.360: Startup point 1.
2066562.360: Waiting for send to finish...
2066662.360: +Initializing CPU #15
2066762.360: After Startup.
2066862.360: CPU16: stack_base 00141000, stack_end 00141ff8
2066962.360: CPU: family 15, model 01, stepping 02
2067062.360: Asserting INIT.
2067162.360: CPU: family 15, model 01, stepping 02
2067262.360: Waiting for send to finish...
2067362.360: +CPU: family 15, model 01, stepping 02
2067462.360: Deasserting INIT.
2067562.360: Waiting for send to finish...
2067662.360: +CPU: vendor AMD device 600f12
2067762.360: #startup loops: 1.
2067862.360: Sending STARTUP #1 to 32.
2067962.360: After apic_write.
2068062.360: CPU: family 15, model 01, stepping 02
2068162.361: Startup point 1.
2068262.361: Waiting for send to finish...
2068362.361: +Initializing CPU #16
2068462.361: After Startup.
2068562.361: CPU17: stack_base 00140000, stack_end 00140ff8
2068662.361: CPU: vendor AMD device 600f12
2068762.361: Asserting INIT.
2068862.361: Enabling cache
2068962.361: Waiting for send to finish...
2069062.361: +nodeid = 01, coreid = 02
2069162.361: CPU ID 0x80000001: 600f12
2069262.361: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2069362.361: Deasserting INIT.
2069462.361: CPU: vendor AMD device 600f12
2069562.361: Waiting for send to finish...
2069662.361: +nodeid = 01, coreid = 01
2069762.361: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2069862.361: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2069962.361: MTRR: Fixed MSR 0x259 0x0000000000000000
2070062.361: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2070162.361: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2070262.361: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2070362.361: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2070462.361: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2070562.361: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2070662.361: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2070762.361: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2070862.361: #startup loops: 1.
2070962.361: Sending STARTUP #1 to 33.
2071062.361: After apic_write.
2071162.361: CPU: family 15, model 01, stepping 02
2071262.361: Startup point 1.
2071362.361: Waiting for send to finish...
2071462.361: +Initializing CPU #13
2071562.361:
2071662.361: MTRR check
2071762.361: Fixed MTRRs : Enabled
2071862.361: Variable MTRRs: Enabled
2071962.361:
2072062.361: After Startup.
2072162.361: CPU18: stack_base 0013f000, stack_end 0013fff8
2072262.361: nodeid = 01, coreid = 03
2072362.361: Asserting INIT.
2072462.361: Enabling cache
2072562.361: Setting up local APIC...Waiting for send to finish...
2072662.361: + apic_id: 0x08 done.
2072762.361: Deasserting INIT.
2072862.361: CPU model: AMD Opteron(tm) Processor 6278
2072962.361: Waiting for send to finish...
2073062.361: +siblings = 15, #startup loops: 1.
2073162.361: Disabling SMM ASeg memory
2073262.362: Sending STARTUP #1 to 34.
2073362.362: CPU #8 initialized
2073462.362: After apic_write.
2073562.362:
2073662.362: MTRR check
2073762.362: Fixed MTRRs : Enabled
2073862.362: Variable MTRRs: Enabled
2073962.362:
2074062.362: Startup point 1.
2074162.362: Waiting for send to finish...
2074262.362: +Setting up local APIC...After Startup.
2074362.362: CPU19: stack_base 0013e000, stack_end 0013eff8
2074462.362: apic_id: 0x09 done.
2074562.362: Asserting INIT.
2074662.362: CPU model: AMD Opteron(tm) Processor 6278
2074762.362: Waiting for send to finish...
2074862.362: +siblings = 15, Deasserting INIT.
2074962.362: Disabling SMM ASeg memory
2075062.362: Waiting for send to finish...
2075162.362: +CPU #9 initialized
2075262.362: #startup loops: 1.
2075362.362: Sending STARTUP #1 to 35.
2075462.362: After apic_write.
2075562.362: Initializing CPU #17
2075662.362: Startup point 1.
2075762.362: Waiting for send to finish...
2075862.362: +nodeid = 01, coreid = 07
2075962.362: After Startup.
2076062.362: CPU20: stack_base 0013d000, stack_end 0013dff8
2076162.362: Initializing CPU #19
2076262.362: Asserting INIT.
2076362.362: CPU: vendor AMD device 600f12
2076462.362: Waiting for send to finish...
2076562.362: +CPU: family 15, model 01, stepping 02
2076662.362: Deasserting INIT.
2076762.362: Enabling cache
2076862.362: Waiting for send to finish...
2076962.362: +CPU: family 15, model 01, stepping 02
2077062.362: #startup loops: 1.
2077162.362: Sending STARTUP #1 to 36.
2077262.362: After apic_write.
2077362.362: Initializing CPU #18
2077462.362: Startup point 1.
2077562.362: Waiting for send to finish...
2077662.362: +nodeid = 01, coreid = 06
2077762.362: After Startup.
2077862.362: CPU21: stack_base 0013c000, stack_end 0013cff8
2077962.363: Enabling cache
2078062.363: Asserting INIT.
2078162.363: Waiting for send to finish...
2078262.363: CPU ID 0x80000001: 600f12
2078362.363: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2078462.363: +CPU: vendor AMD device 600f12
2078562.363: Deasserting INIT.
2078662.363: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2078762.363: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2078862.363: MTRR: Fixed MSR 0x259 0x0000000000000000
2078962.363: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2079062.363: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2079162.363: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2079262.363: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2079362.363: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2079462.363: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2079562.363: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2079662.363: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2079762.363: Waiting for send to finish...
2079862.363: +Enabling cache
2079962.363: #startup loops: 1.
2080062.363: Sending STARTUP #1 to 37.
2080162.363: After apic_write.
2080262.363:
2080362.363: MTRR check
2080462.363: Fixed MTRRs : Enabled
2080562.363: Variable MTRRs: Enabled
2080662.363:
2080762.363: Startup point 1.
2080862.363: Waiting for send to finish...
2080962.363: +Setting up local APIC...Enabling cache
2081062.363: After Startup.
2081162.363: CPU22: stack_base 0013b000, stack_end 0013bff8
2081262.363: apic_id: 0x0e done.
2081362.363: CPU ID 0x80000001: 600f12
2081462.363: CPU model: AMD Opteron(tm) Processor 6278
2081562.363: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2081662.363: Asserting INIT.
2081762.363: siblings = 15, Waiting for send to finish...
2081862.363: +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2081962.363: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2082062.363: MTRR: Fixed MSR 0x259 0x0000000000000000
2082162.363: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2082262.363: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2082362.363: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2082462.363: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2082562.363: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2082662.363: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2082762.363: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2082862.363: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2082962.363: Disabling SMM ASeg memory
2083062.363: Deasserting INIT.
2083162.363: CPU #14 initialized
2083262.363: Waiting for send to finish...
2083362.363:
2083462.363: MTRR check
2083562.363: Fixed MTRRs : Enabled
2083662.363: Variable MTRRs: Enabled
2083762.363:
2083862.363:
2083962.363: MTRR check
2084062.363: Fixed MTRRs : Enabled
2084162.364: Variable MTRRs: Enabled
2084262.364:
2084362.364: Setting up local APIC...+ apic_id: 0x0f done.
2084462.364: #startup loops: 1.
2084562.364: Sending STARTUP #1 to 38.
2084662.364: Setting up local APIC...CPU model: AMD Opteron(tm) Processor 6278
2084762.364: apic_id: 0x0a done.
2084862.364: siblings = 15, After apic_write.
2084962.364: CPU model: AMD Opteron(tm) Processor 6278
2085062.364: Disabling SMM ASeg memory
2085162.364: siblings = 15, CPU #15 initialized
2085262.364: CPU: vendor AMD device 600f12
2085362.364: Disabling SMM ASeg memory
2085462.364: Startup point 1.
2085562.364: Waiting for send to finish...
2085662.364: +CPU #10 initialized
2085762.364: After Startup.
2085862.364: CPU23: stack_base 0013a000, stack_end 0013aff8
2085962.364:
2086062.364: MTRR check
2086162.364: Asserting INIT.
2086262.364: Fixed MTRRs : Enabled
2086362.364: Variable MTRRs: Enabled
2086462.364:
2086562.364: Waiting for send to finish...
2086662.364: +Setting up local APIC...Deasserting INIT.
2086762.364: apic_id: 0x0b done.
2086862.364: Waiting for send to finish...
2086962.364: +CPU model: AMD Opteron(tm) Processor 6278
2087062.364: #startup loops: 1.
2087162.364: Sending STARTUP #1 to 39.
2087262.364: siblings = 15, After apic_write.
2087362.364: Disabling SMM ASeg memory
2087462.364: Startup point 1.
2087562.364: Waiting for send to finish...
2087662.364: +CPU #11 initialized
2087762.364: After Startup.
2087862.364: CPU24: stack_base 00139000, stack_end 00139ff8
2087962.364: nodeid = 01, coreid = 04
2088062.364: Asserting INIT.
2088162.364: Initializing CPU #23
2088262.364: Waiting for send to finish...
2088362.364: +Initializing CPU #22
2088462.364: Deasserting INIT.
2088562.364: Waiting for send to finish...
2088662.364: +CPU: family 15, model 01, stepping 02
2088762.365: #startup loops: 1.
2088862.365: Sending STARTUP #1 to 40.
2088962.365: After apic_write.
2089062.365: nodeid = 02, coreid = 00
2089162.365: Startup point 1.
2089262.365: Waiting for send to finish...
2089362.365: +Initializing CPU #20
2089462.365: After Startup.
2089562.365: CPU25: stack_base 00138000, stack_end 00138ff8
2089662.365: CPU: vendor AMD device 600f12
2089762.365: Asserting INIT.
2089862.365: Waiting for send to finish...
2089962.365: +Initializing CPU #24
2090062.365: Deasserting INIT.
2090162.365: Waiting for send to finish...
2090262.365: +CPU: vendor AMD device 600f12
2090362.365: #startup loops: 1.
2090462.365: Sending STARTUP #1 to 41.
2090562.365: After apic_write.
2090662.365: Enabling cache
2090762.365: Startup point 1.
2090862.365: Waiting for send to finish...
2090962.365: +CPU: family 15, model 01, stepping 02
2091062.365: After Startup.
2091162.365: CPU26: stack_base 00137000, stack_end 00137ff8
2091262.365: Enabling cache
2091362.365: Asserting INIT.
2091462.365: nodeid = 01, coreid = 05
2091562.365: CPU ID 0x80000001: 600f12
2091662.365: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2091762.365: Waiting for send to finish...
2091862.365: +Enabling cache
2091962.365: Deasserting INIT.
2092062.365: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2092162.365: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2092262.365: MTRR: Fixed MSR 0x259 0x0000000000000000
2092362.365: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2092462.365: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2092562.365: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2092662.365: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2092762.365: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2092862.365: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2092962.365: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2093062.365: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2093162.365: Waiting for send to finish...
2093262.365: +CPU: family 15, model 01, stepping 02
2093362.365: CPU ID 0x80000001: 600f12
2093462.365: #startup loops: 1.
2093562.365:
2093662.365: MTRR check
2093762.365: Fixed MTRRs : Enabled
2093862.366: Variable MTRRs: Enabled
2093962.366:
2094062.366: Initializing CPU #25
2094162.366: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2094262.366: Setting up local APIC...Sending STARTUP #1 to 42.
2094362.366: After apic_write.
2094462.366: apic_id: 0x0c done.
2094562.366: Startup point 1.
2094662.366: CPU model: AMD Opteron(tm) Processor 6278
2094762.366: Initializing CPU #26
2094862.366: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2094962.366: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2095062.366: MTRR: Fixed MSR 0x259 0x0000000000000000
2095162.366: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2095262.366: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2095362.366: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2095462.366: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2095562.366: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2095662.366: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2095762.366: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2095862.366: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2095962.366: siblings = 15, Waiting for send to finish...
2096062.366: +Disabling SMM ASeg memory
2096162.366: After Startup.
2096262.366: CPU27: stack_base 00136000, stack_end 00136ff8
2096362.366:
2096462.366: MTRR check
2096562.366: Fixed MTRRs : Enabled
2096662.366: Variable MTRRs: Enabled
2096762.366:
2096862.366: Asserting INIT.
2096962.366: CPU: vendor AMD device 600f12
2097062.366:
2097162.366: MTRR check
2097262.366: Fixed MTRRs : Enabled
2097362.366: Variable MTRRs: Enabled
2097462.366:
2097562.366: Waiting for send to finish...
2097662.366: +CPU #12 initialized
2097762.366: Setting up local APIC...Deasserting INIT.
2097862.366: apic_id: 0x0d done.
2097962.366: Waiting for send to finish...
2098062.366: +CPU model: AMD Opteron(tm) Processor 6278
2098162.366: #startup loops: 1.
2098262.366: Sending STARTUP #1 to 43.
2098362.366: After apic_write.
2098462.366: siblings = 15, Startup point 1.
2098562.366: Waiting for send to finish...
2098662.366: +Disabling SMM ASeg memory
2098762.366: After Startup.
2098862.366: CPU28: stack_base 00135000, stack_end 00135ff8
2098962.366: CPU #13 initialized
2099062.366: Asserting INIT.
2099162.367: CPU: vendor AMD device 600f12
2099262.367: Setting up local APIC...Waiting for send to finish...
2099362.367: +CPU: family 15, model 01, stepping 02
2099462.367: apic_id: 0x20 done.
2099562.367: Deasserting INIT.
2099662.367: nodeid = 02, coreid = 01
2099762.367: Waiting for send to finish...
2099862.367: +CPU: vendor AMD device 600f12
2099962.367: CPU model: AMD Opteron(tm) Processor 6278
2100062.367: #startup loops: 1.
2100162.367: Sending STARTUP #1 to 44.
2100262.367: After apic_write.
2100362.367: CPU: family 15, model 01, stepping 02
2100462.367: Startup point 1.
2100562.367: Waiting for send to finish...
2100662.367: +CPU: family 15, model 01, stepping 02
2100762.367: siblings = 15, After Startup.
2100862.367: CPU29: stack_base 00134000, stack_end 00134ff8
2100962.367: Disabling SMM ASeg memory
2101062.367: Asserting INIT.
2101162.367: CPU: vendor AMD device 600f12
2101262.367: Waiting for send to finish...
2101362.367: +Enabling cache
2101462.367: nodeid = 02, coreid = 04
2101562.367: Deasserting INIT.
2101662.367: CPU #16 initialized
2101762.367: Waiting for send to finish...
2101862.367: +
2101962.367: MTRR check
2102062.367: Fixed MTRRs : Enabled
2102162.367: Variable MTRRs: Enabled
2102262.367:
2102362.367: #startup loops: 1.
2102462.367: Sending STARTUP #1 to 45.
2102562.367: After apic_write.
2102662.367: Setting up local APIC...Startup point 1.
2102762.367: Waiting for send to finish...
2102862.367: + apic_id: 0x21 done.
2102962.367: After Startup.
2103062.367: CPU model: AMD Opteron(tm) Processor 6278
2103162.367: CPU30: stack_base 00133000, stack_end 00133ff8
2103262.367: siblings = 15, Asserting INIT.
2103362.368: Disabling SMM ASeg memory
2103462.367: Waiting for send to finish...
2103562.368: +CPU #17 initialized
2103662.368: Deasserting INIT.
2103762.368: Waiting for send to finish...
2103862.368: +CPU: vendor AMD device 600f12
2103962.368: #startup loops: 1.
2104062.368: Sending STARTUP #1 to 46.
2104162.368: After apic_write.
2104262.368: nodeid = 03, coreid = 02
2104362.368: Startup point 1.
2104462.368: Waiting for send to finish...
2104562.368: +CPU: family 15, model 01, stepping 02
2104662.368: After Startup.
2104762.368: CPU31: stack_base 00132000, stack_end 00132ff8
2104862.368: Initializing CPU #28
2104962.368: Asserting INIT.
2105062.368: Waiting for send to finish...
2105162.368: +CPU: vendor AMD device 600f12
2105262.368: Deasserting INIT.
2105362.368: Waiting for send to finish...
2105462.368: +CPU: family 15, model 01, stepping 02
2105562.368: #startup loops: 1.
2105662.368: Sending STARTUP #1 to 47.
2105762.368: After apic_write.
2105862.368: Initializing CPU #30
2105962.368: Startup point 1.
2106062.368: Waiting for send to finish...
2106162.368: +Enabling cache
2106262.368: After Startup.
2106362.368: Initializing CPU #0
2106462.368: Initializing CPU #21
2106562.368: CPU: vendor AMD device 600f12
2106662.368: CPU: family 15, model 01, stepping 02
2106762.368: Enabling cache
2106862.368: CPU ID 0x80000001: 600f12
2106962.368: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2107062.368: nodeid = 00, coreid = 00
2107162.368: Enabling cache
2107262.368: nodeid = 02, coreid = 07
2107362.368: CPU ID 0x80000001: 600f12
2107462.368: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2107562.368: CPU ID 0x80000001: 600f12
2107662.368: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2107762.368: Initializing CPU #27
2107862.368: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2107962.368: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2108062.368: MTRR: Fixed MSR 0x259 0x0000000000000000
2108162.368: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2108262.368: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2108362.368: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2108462.368: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2108562.368: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2108662.368: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2108762.369: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2108862.369: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2108962.369: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2109062.369: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2109162.369: MTRR: Fixed MSR 0x259 0x0000000000000000
2109262.369: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2109362.369: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2109462.369: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2109562.369: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2109662.369: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2109762.369: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2109862.369: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2109962.369: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2110062.369: nodeid = 03, coreid = 00
2110162.369: CPU: vendor AMD device 600f12
2110262.369: CPU: vendor AMD device 600f12
2110362.369:
2110462.369: MTRR check
2110562.369: Fixed MTRRs : Enabled
2110662.369: Variable MTRRs: Enabled
2110762.369:
2110862.369:
2110962.369: MTRR check
2111062.369: Fixed MTRRs : Enabled
2111162.369: Variable MTRRs: Enabled
2111262.369:
2111362.369: Initializing CPU #31
2111462.369: Setting up local APIC...Setting up local APIC...CPU: family 15, model 01, stepping 02
2111562.369: apic_id: 0x00 done.
2111662.369: Enabling cache
2111762.369: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2111862.369: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2111962.369: MTRR: Fixed MSR 0x259 0x0000000000000000
2112062.369: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2112162.369: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2112262.369: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2112362.369: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2112462.369: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2112562.369: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2112662.369: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2112762.369: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2112862.369: CPU model: AMD Opteron(tm) Processor 6278
2112962.369: CPU: vendor AMD device 600f12
2113062.369: siblings = 15, CPU: family 15, model 01, stepping 02
2113162.369:
2113262.369: MTRR check
2113362.369: Fixed MTRRs : Enabled
2113462.369: Variable MTRRs: Enabled
2113562.369:
2113662.369: Disabling SMM ASeg memory
2113762.369: nodeid = 02, coreid = 03
2113862.369:
2113962.369: MTRR check
2114062.369: Fixed MTRRs : Enabled
2114162.369: Variable MTRRs: Enabled
2114262.370:
2114362.370: nodeid = 02, coreid = 05
2114462.370: Setting up local APIC...Setting up local APIC...CPU: family 15, model 01, stepping 02
2114562.370: apic_id: 0x2a done.
2114662.370: apic_id: 0x01 done.
2114762.370: CPU #0 initialized
2114862.370: Waiting for 15 CPUS to stop
2114962.370: CPU model: AMD Opteron(tm) Processor 6278
2115062.370: nodeid = 03, coreid = 03
2115162.370: siblings = 15, CPU: family 15, model 01, stepping 02
2115262.370: apic_id: 0x24 done.
2115362.370: Disabling SMM ASeg memory
2115462.370: CPU: family 15, model 01, stepping 02
2115562.370: CPU model: AMD Opteron(tm) Processor 6278
2115662.370: CPU #1 initialized
2115762.370: nodeid = 02, coreid = 06
2115862.370: siblings = 15, Enabling cache
2115962.370: Waiting for 14 CPUS to stop
2116062.370: CPU ID 0x80000001: 600f12
2116162.370: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2116262.370: Enabling cache
2116362.370: CPU model: AMD Opteron(tm) Processor 6278
2116462.370: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2116562.370: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2116662.370: MTRR: Fixed MSR 0x259 0x0000000000000000
2116762.370: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2116862.370: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2116962.370: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2117062.370: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2117162.370: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2117262.370: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2117362.370: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2117462.370: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2117562.370: siblings = 15, Enabling cache
2117662.370: Disabling SMM ASeg memory
2117762.370: Disabling SMM ASeg memory
2117862.370:
2117962.370: MTRR check
2118062.370: Fixed MTRRs : Enabled
2118162.370: Variable MTRRs: Enabled
2118262.370:
2118362.370: CPU #26 initialized
2118462.370:
2118562.370: MTRR check
2118662.370: Fixed MTRRs : Enabled
2118762.370: Variable MTRRs: Enabled
2118862.370:
2118962.370:
2119062.370: MTRR check
2119162.370: Fixed MTRRs : Enabled
2119262.370: Variable MTRRs: Enabled
2119362.371:
2119462.371: Setting up local APIC...Setting up local APIC...CPU #20 initialized
2119562.371: apic_id: 0x25 done.
2119662.371: Setting up local APIC... apic_id: 0x26 done.
2119762.371: apic_id: 0x2b done.
2119862.371: CPU model: AMD Opteron(tm) Processor 6278
2119962.371: CPU model: AMD Opteron(tm) Processor 6278
2120062.371: CPU model: AMD Opteron(tm) Processor 6278
2120162.371: siblings = 15, Waiting for 13 CPUS to stop
2120262.371: siblings = 15, Disabling SMM ASeg memory
2120362.371: Disabling SMM ASeg memory
2120462.371: siblings = 15, Waiting for 12 CPUS to stop
2120562.371: CPU #27 initialized
2120662.371: CPU #21 initialized
2120762.371: Disabling SMM ASeg memory
2120862.371: Waiting for 11 CPUS to stop
2120962.371: CPU #22 initialized
2121062.371: Waiting for 10 CPUS to stop
2121162.371:
2121262.371: MTRR check
2121362.371: Fixed MTRRs : Enabled
2121462.371: Variable MTRRs: Enabled
2121562.371:
2121662.371: Waiting for 9 CPUS to stop
2121762.371: Setting up local APIC...CPU: vendor AMD device 600f12
2121862.371: apic_id: 0x27 done.
2121962.371: Initializing CPU #29
2122062.371: CPU model: AMD Opteron(tm) Processor 6278
2122162.371: Enabling cache
2122262.371: siblings = 15, CPU: vendor AMD device 600f12
2122362.371: Disabling SMM ASeg memory
2122462.371: CPU #23 initialized
2122562.371: CPU: family 15, model 01, stepping 02
2122662.371: Waiting for 8 CPUS to stop
2122762.371: nodeid = 02, coreid = 02
2122862.371: CPU: vendor AMD device 600f12
2122962.371: Enabling cache
2123062.371: nodeid = 03, coreid = 05
2123162.371: CPU: family 15, model 01, stepping 02
2123262.371: CPU ID 0x80000001: 600f12
2123362.371: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2123462.371: nodeid = 03, coreid = 06
2123562.372: CPU: family 15, model 01, stepping 02
2123662.372: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2123762.372: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2123862.372: MTRR: Fixed MSR 0x259 0x0000000000000000
2123962.372: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2124062.372: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2124162.372: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2124262.372: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2124362.372: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2124462.372: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2124562.372: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2124662.372: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2124762.372: nodeid = 03, coreid = 04
2124862.372: Enabling cache
2124962.372: Enabling cache
2125062.372: nodeid = 03, coreid = 01
2125162.372:
2125262.372: MTRR check
2125362.372: Fixed MTRRs : Enabled
2125462.372: Variable MTRRs: Enabled
2125562.372:
2125662.372: CPU ID 0x80000001: 600f12
2125762.372: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2125862.372: Setting up local APIC...Enabling cache
2125962.372: apic_id: 0x22 done.
2126062.372: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2126162.372: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2126262.372: MTRR: Fixed MSR 0x259 0x0000000000000000
2126362.372: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2126462.372: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2126562.372: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2126662.372: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2126762.372: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2126862.372: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2126962.372: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2127062.372: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2127162.372: CPU model: AMD Opteron(tm) Processor 6278
2127262.372: Enabling cache
2127362.372: siblings = 15, nodeid = 03, coreid = 07
2127462.372:
2127562.372: MTRR check
2127662.372: Fixed MTRRs : Enabled
2127762.372: Variable MTRRs: Enabled
2127862.372:
2127962.372: Disabling SMM ASeg memory
2128062.372: Setting up local APIC...CPU #18 initialized
2128162.372:
2128262.372: MTRR check
2128362.372: Fixed MTRRs : Enabled
2128462.372: Variable MTRRs: Enabled
2128562.372:
2128662.372: apic_id: 0x2c done.
2128762.372: Waiting for 7 CPUS to stop
2128862.372: CPU model: AMD Opteron(tm) Processor 6278
2128962.372: Setting up local APIC...siblings = 15, apic_id: 0x23 done.
2129062.373: Disabling SMM ASeg memory
2129162.373: CPU model: AMD Opteron(tm) Processor 6278
2129262.373: CPU #28 initialized
2129362.373: siblings = 15, Waiting for 6 CPUS to stop
2129462.373:
2129562.373: MTRR check
2129662.373: Fixed MTRRs : Enabled
2129762.373: Variable MTRRs: Enabled
2129862.373:
2129962.373: Disabling SMM ASeg memory
2130062.373: Setting up local APIC...CPU #19 initialized
2130162.373: apic_id: 0x2d done.
2130262.373: Waiting for 5 CPUS to stop
2130362.373: CPU model: AMD Opteron(tm) Processor 6278
2130462.373: Enabling cache
2130562.373: siblings = 15, CPU ID 0x80000001: 600f12
2130662.373: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2130762.373: Disabling SMM ASeg memory
2130862.373: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2130962.373: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2131062.373: MTRR: Fixed MSR 0x259 0x0000000000000000
2131162.373: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2131262.373: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2131362.373: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2131462.373: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2131562.373: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2131662.373: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2131762.373: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2131862.373: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2131962.373: CPU #29 initialized
2132062.373: CPU ID 0x80000001: 600f12
2132162.373: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
2132262.373: Waiting for 4 CPUS to stop
2132362.373:
2132462.373: MTRR check
2132562.373: Fixed MTRRs : Enabled
2132662.373: Variable MTRRs: Enabled
2132762.373:
2132862.373: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
2132962.373: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
2133062.373: MTRR: Fixed MSR 0x259 0x0000000000000000
2133162.373: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
2133262.373: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
2133362.373: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
2133462.373: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
2133562.373: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
2133662.373: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
2133762.373: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
2133862.373: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
2133962.373: Setting up local APIC... apic_id: 0x28 done.
2134062.373: CPU model: AMD Opteron(tm) Processor 6278
2134162.373: Enabling cache
2134262.373: siblings = 15,
2134362.373: MTRR check
2134462.373: Fixed MTRRs : Enabled
2134562.373: Variable MTRRs: Enabled
2134662.373:
2134762.373: Disabling SMM ASeg memory
2134862.373: Setting up local APIC...CPU #24 initialized
2134962.373: apic_id: 0x2e done.
2135062.374:
2135162.374: MTRR check
2135262.374: Fixed MTRRs : Enabled
2135362.374: Variable MTRRs: Enabled
2135462.374:
2135562.374: CPU model: AMD Opteron(tm) Processor 6278
2135662.374: Waiting for 3 CPUS to stop
2135762.374: siblings = 15, Setting up local APIC...Disabling SMM ASeg memory
2135862.374: apic_id: 0x29 done.
2135962.374: CPU #30 initialized
2136062.374: CPU model: AMD Opteron(tm) Processor 6278
2136162.374:
2136262.374: MTRR check
2136362.374: Fixed MTRRs : Enabled
2136462.374: Variable MTRRs: Enabled
2136562.374:
2136662.374: siblings = 15, Waiting for 2 CPUS to stop
2136762.374: Disabling SMM ASeg memory
2136862.374: Setting up local APIC...CPU #25 initialized
2136962.374: apic_id: 0x2f done.
2137062.374: Waiting for 1 CPUS to stop
2137162.374: CPU model: AMD Opteron(tm) Processor 6278
2137262.374: siblings = 15, Disabling SMM ASeg memory
2137362.374: CPU #31 initialized
2137462.374: All AP CPUs stopped (44850 loops)
2137562.374: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
2137662.374: CPU1: stack: 00150000 - 00151000, lowest used address 00150de8, stack used: 536 bytes
2137762.374: CPU2: stack: 0014f000 - 00150000, lowest used address 0014fcac, stack used: 852 bytes
2137862.374: CPU3: stack: 0014e000 - 0014f000, lowest used address 0014ede8, stack used: 536 bytes
2137962.374: CPU4: stack: 0014d000 - 0014e000, lowest used address 0014dd08, stack used: 760 bytes
2138062.374: CPU5: stack: 0014c000 - 0014d000, lowest used address 0014cde8, stack used: 536 bytes
2138162.374: CPU6: stack: 0014b000 - 0014c000, lowest used address 0014bd08, stack used: 760 bytes
2138262.374: CPU7: stack: 0014a000 - 0014b000, lowest used address 0014ade8, stack used: 536 bytes
2138362.374: CPU8: stack: 00149000 - 0014a000, lowest used address 00149d08, stack used: 760 bytes
2138462.374: CPU9: stack: 00148000 - 00149000, lowest used address 00148de8, stack used: 536 bytes
2138562.374: CPU10: stack: 00147000 - 00148000, lowest used address 00147d08, stack used: 760 bytes
2138662.374: CPU11: stack: 00146000 - 00147000, lowest used address 00146de8, stack used: 536 bytes
2138762.374: CPU12: stack: 00145000 - 00146000, lowest used address 00145d08, stack used: 760 bytes
2138862.375: CPU13: stack: 00144000 - 00145000, lowest used address 00144de8, stack used: 536 bytes
2138962.375: CPU14: stack: 00143000 - 00144000, lowest used address 00143d08, stack used: 760 bytes
2139062.375: CPU15: stack: 00142000 - 00143000, lowest used address 00142de8, stack used: 536 bytes
2139162.375: CPU16: stack: 00141000 - 00142000, lowest used address 00141d08, stack used: 760 bytes
2139262.375: CPU17: stack: 00140000 - 00141000, lowest used address 00140de8, stack used: 536 bytes
2139362.375: CPU18: stack: 0013f000 - 00140000, lowest used address 0013fd08, stack used: 760 bytes
2139462.375: CPU19: stack: 0013e000 - 0013f000, lowest used address 0013ede8, stack used: 536 bytes
2139562.375: CPU20: stack: 0013d000 - 0013e000, lowest used address 0013dd08, stack used: 760 bytes
2139662.375: CPU21: stack: 0013c000 - 0013d000, lowest used address 0013cde8, stack used: 536 bytes
2139762.375: CPU22: stack: 0013b000 - 0013c000, lowest used address 0013bd08, stack used: 760 bytes
2139862.375: CPU23: stack: 0013a000 - 0013b000, lowest used address 0013ade8, stack used: 536 bytes
2139962.375: CPU24: stack: 00139000 - 0013a000, lowest used address 00139d08, stack used: 760 bytes
2140062.375: CPU25: stack: 00138000 - 00139000, lowest used address 00138de8, stack used: 536 bytes
2140162.375: CPU26: stack: 00137000 - 00138000, lowest used address 00137d08, stack used: 760 bytes
2140262.375: CPU27: stack: 00136000 - 00137000, lowest used address 00136de8, stack used: 536 bytes
2140362.375: CPU28: stack: 00135000 - 00136000, lowest used address 00135d08, stack used: 760 bytes
2140462.375: CPU29: stack: 00134000 - 00135000, lowest used address 00134de8, stack used: 536 bytes
2140562.375: CPU30: stack: 00133000 - 00134000, lowest used address 00133d08, stack used: 760 bytes
2140662.375: CPU31: stack: 00132000 - 00133000, lowest used address 00132de8, stack used: 536 bytes
2140762.375: CPU_CLUSTER: 0 init finished in 2107935 usecs
2140862.375: PCI: 00:18.0 init ...
2140962.375: PCI: 00:18.0 init finished in 1461 usecs
2141062.375: PCI: 00:18.1 init ...
2141162.375: PCI: 00:18.1 init finished in 1462 usecs
2141262.375: PCI: 00:18.2 init ...
2141362.375: PCI: 00:18.2 init finished in 1462 usecs
2141462.375: PCI: 00:18.3 init ...
2141562.375: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2141662.375: CBFS: Locating 'cmos_layout.bin'
2141762.376: CBFS: Found @ offset 2b0c0 size e88
2141862.376: done.
2141962.376: PCI: 00:18.3 init finished in 12599 usecs
2142062.376: PCI: 00:18.4 init ...
2142162.376: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2142262.376: CBFS: Locating 'cmos_layout.bin'
2142362.376: CBFS: Found @ offset 2b0c0 size e88
2142462.377: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2142562.377: CBFS: Locating 'cmos_layout.bin'
2142662.377: CBFS: Found @ offset 2b0c0 size e88
2142762.377: done.
2142862.377: PCI: 00:18.4 init finished in 21317 usecs
2142962.377: PCI: 00:18.5 init ...
2143062.377: NB: Function 5 Northbridge Control.. done.
2143162.378: PCI: 00:18.5 init finished in 4259 usecs
2143262.378: PCI: 00:19.0 init ...
2143362.378: PCI: 00:19.0 init finished in 1462 usecs
2143462.378: PCI: 00:19.1 init ...
2143562.378: PCI: 00:19.1 init finished in 1462 usecs
2143662.378: PCI: 00:19.2 init ...
2143762.378: PCI: 00:19.2 init finished in 1462 usecs
2143862.378: PCI: 00:19.3 init ...
2143962.378: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2144062.378: CBFS: Locating 'cmos_layout.bin'
2144162.378: CBFS: Found @ offset 2b0c0 size e88
2144262.378: done.
2144362.378: PCI: 00:19.3 init finished in 12593 usecs
2144462.378: PCI: 00:19.4 init ...
2144562.378: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2144662.378: CBFS: Locating 'cmos_layout.bin'
2144762.379: CBFS: Found @ offset 2b0c0 size e88
2144862.379: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2144962.379: CBFS: Locating 'cmos_layout.bin'
2145062.379: CBFS: Found @ offset 2b0c0 size e88
2145162.380: done.
2145262.380: PCI: 00:19.4 init finished in 21329 usecs
2145362.380: PCI: 00:19.5 init ...
2145462.380: NB: Function 5 Northbridge Control.. done.
2145562.380: PCI: 00:19.5 init finished in 4260 usecs
2145662.380: PCI: 00:1a.0 init ...
2145762.380: PCI: 00:1a.0 init finished in 1462 usecs
2145862.380: PCI: 00:1a.1 init ...
2145962.380: PCI: 00:1a.1 init finished in 1461 usecs
2146062.380: PCI: 00:1a.2 init ...
2146162.380: PCI: 00:1a.2 init finished in 1461 usecs
2146262.380: PCI: 00:1a.3 init ...
2146362.380: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2146462.380: CBFS: Locating 'cmos_layout.bin'
2146562.380: CBFS: Found @ offset 2b0c0 size e88
2146662.381: done.
2146762.381: PCI: 00:1a.3 init finished in 12587 usecs
2146862.381: PCI: 00:1a.4 init ...
2146962.381: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2147062.381: CBFS: Locating 'cmos_layout.bin'
2147162.381: CBFS: Found @ offset 2b0c0 size e88
2147262.381: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2147362.381: CBFS: Locating 'cmos_layout.bin'
2147462.381: CBFS: Found @ offset 2b0c0 size e88
2147562.382: done.
2147662.382: PCI: 00:1a.4 init finished in 21324 usecs
2147762.382: PCI: 00:1a.5 init ...
2147862.382: NB: Function 5 Northbridge Control.. done.
2147962.382: PCI: 00:1a.5 init finished in 4260 usecs
2148062.382: PCI: 00:1b.0 init ...
2148162.382: PCI: 00:1b.0 init finished in 1461 usecs
2148262.382: PCI: 00:1b.1 init ...
2148362.382: PCI: 00:1b.1 init finished in 1461 usecs
2148462.382: PCI: 00:1b.2 init ...
2148562.382: PCI: 00:1b.2 init finished in 1462 usecs
2148662.382: PCI: 00:1b.3 init ...
2148762.382: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2148862.382: CBFS: Locating 'cmos_layout.bin'
2148962.382: CBFS: Found @ offset 2b0c0 size e88
2149062.383: done.
2149162.383: PCI: 00:1b.3 init finished in 12587 usecs
2149262.383: PCI: 00:1b.4 init ...
2149362.383: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2149462.383: CBFS: Locating 'cmos_layout.bin'
2149562.383: CBFS: Found @ offset 2b0c0 size e88
2149662.384: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2149762.384: CBFS: Locating 'cmos_layout.bin'
2149862.384: CBFS: Found @ offset 2b0c0 size e88
2149962.384: done.
2150062.384: PCI: 00:1b.4 init finished in 21317 usecs
2150162.384: PCI: 00:1b.5 init ...
2150262.384: NB: Function 5 Northbridge Control.. done.
2150362.384: PCI: 00:1b.5 init finished in 4260 usecs
2150462.384: PCI: 00:00.0 init ...
2150562.384: pcie_init in sr5650_ht.c
2150662.384: IOAPIC: Initializing IOAPIC at 0xfce00000
2150762.384: IOAPIC: Bootstrap Processor Local APIC = 0x00
2150862.384: IOAPIC: ID = 0x01
2150962.384: IOAPIC: Dumping registers
2151062.384: reg 0x0000: 0x01000000
2151162.384: reg 0x0001: 0x001f8021
2151262.384: reg 0x0002: 0x00000000
2151362.384: IOAPIC: 32 interrupts
2151462.384: IOAPIC: Enabling interrupts on FSB
2151562.384: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
2151662.384: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
2151762.384: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
2151862.384: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
2151962.384: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
2152062.384: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
2152162.385: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
2152262.385: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
2152362.385: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
2152462.385: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
2152562.385: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
2152662.385: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
2152762.385: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
2152862.385: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
2152962.385: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
2153062.385: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
2153162.385: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
2153262.385: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
2153362.385: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
2153462.385: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
2153562.385: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
2153662.385: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
2153762.385: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
2153862.385: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
2153962.385: IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
2154062.385: IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
2154162.385: IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
2154262.385: IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
2154362.385: IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
2154462.385: IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
2154562.385: IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
2154662.385: IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
2154762.385: PCI: 00:00.0 init finished in 125721 usecs
2154862.385: PCI: 00:11.0 init ...
2154962.385: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2155062.385: CBFS: Locating 'cmos_layout.bin'
2155162.385: CBFS: Found @ offset 2b0c0 size e88
2155262.385: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2155362.385: CBFS: Locating 'cmos_layout.bin'
2155462.386: CBFS: Found @ offset 2b0c0 size e88
2155562.386: rev_id=15
2155662.386: sata_bar0=5020
2155762.386: sata_bar1=5040
2155862.386: sata_bar2=5028
2155962.386: sata_bar3=5044
2156062.386: sata_bar4=5000
2156162.386: sata_bar5=fcb0d000
2156262.386: ide_bar0=5030
2156362.386: ide_bar1=5048
2156462.386: ide_bar2=5038
2156562.386: ide_bar3=504c
2156662.386: Maximum SATA port count supported by silicon: 6
2156762.398: SATA port 0 status = 23
2156862.398: 0x6=a0, 0x7=80
2156962.398: drive detection not yet completed, waiting...
2157062.408: 0x6=0, 0x7=50
2157162.408: drive no longer selected after 10 ms, retrying init
2157262.408: drive detection done after 0 ms
2157362.408: AHCI device 0 is ready after 2 tries
2157462.408: SATA port 1 status = 23
2157562.408: drive detection done after 0 ms
2157662.408: AHCI device 1 is ready after 1 tries
2157762.408: SATA port 2 status = 0
2157862.408: No AHCI SATA drive on Slot2
2157962.408: SATA port 3 status = 23
2158062.408: drive detection done after 0 ms
2158162.408: AHCI device 3 is ready after 1 tries
2158262.408: SATA port 4 status = 0
2158362.409: No AHCI SATA drive on Slot4
2158462.409: SATA port 5 status = 0
2158562.409: No AHCI SATA drive on Slot5
2158662.409: PCI: 00:11.0 init finished in 85667 usecs
2158762.409: PCI: 00:12.0 init ...
2158862.409: PCI: 00:12.0 init finished in 1484 usecs
2158962.409: PCI: 00:12.1 init ...
2159062.409: PCI: 00:12.1 init finished in 1483 usecs
2159162.409: PCI: 00:12.2 init ...
2159262.409: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2159362.409: CBFS: Locating 'cmos_layout.bin'
2159462.409: CBFS: Found @ offset 2b0c0 size e88
2159562.410: usb2_bar0=0xfcb0e000
2159662.410: rpr 6.23, final dword=849e03c8
2159762.410: PCI: 00:12.2 init finished in 13778 usecs
2159862.410: PCI: 00:13.0 init ...
2159962.410: PCI: 00:13.0 init finished in 1484 usecs
2160062.410: PCI: 00:13.1 init ...
2160162.410: PCI: 00:13.1 init finished in 1484 usecs
2160262.410: PCI: 00:13.2 init ...
2160362.410: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2160462.410: CBFS: Locating 'cmos_layout.bin'
2160562.410: CBFS: Found @ offset 2b0c0 size e88
2160662.411: usb2_bar0=0xfcb0f000
2160762.411: rpr 6.23, final dword=849e03c8
2160862.411: PCI: 00:13.2 init finished in 13778 usecs
2160962.411: PCI: 00:14.0 init ...
2161062.411: sm_init().
2161162.411: IOAPIC: Initializing IOAPIC at 0xfec00000
2161262.411: IOAPIC: Bootstrap Processor Local APIC = 0x00
2161362.411: IOAPIC: Dumping registers
2161462.411: reg 0x0000: 0x00000000
2161562.411: reg 0x0001: 0x00178021
2161662.411: reg 0x0002: 0x00000000
2161762.411: IOAPIC: 24 interrupts
2161862.411: IOAPIC: Enabling interrupts on FSB
2161962.411: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
2162062.411: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
2162162.411: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
2162262.411: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
2162362.411: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
2162462.411: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
2162562.411: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
2162662.411: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
2162762.411: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
2162862.411: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
2162962.411: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
2163062.411: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
2163162.411: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
2163262.411: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
2163362.411: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
2163462.411: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
2163562.411: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
2163662.411: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
2163762.411: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
2163862.411: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
2163962.411: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
2164062.411: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
2164162.411: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
2164262.411: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
2164362.411: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2164462.411: CBFS: Locating 'cmos_layout.bin'
2164562.411: CBFS: Found @ offset 2b0c0 size e88
2164662.412: WARNING: No CMOS option 'enable_legacy_usb'.
2164762.412: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2164862.412: CBFS: Locating 'cmos_layout.bin'
2164962.412: CBFS: Found @ offset 2b0c0 size e88
2165062.412: set power "on" after power fail
2165162.412: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2165262.412: CBFS: Locating 'cmos_layout.bin'
2165362.412: CBFS: Found @ offset 2b0c0 size e88
2165462.413: ++++++++++no set NMI+++++
2165562.413: RTC Init
2165662.413: sm_init() end
2165762.413: PCI: 00:14.0 init finished in 132054 usecs
2165862.413: PCI: 00:14.1 init ...
2165962.413: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2166062.413: CBFS: Locating 'cmos_layout.bin'
2166162.413: CBFS: Found @ offset 2b0c0 size e88
2166262.414: PCI: 00:14.1 init finished in 10194 usecs
2166362.414: PCI: 00:14.2 init ...
2166462.414: base = 0xfcb04000
2166562.418: No codec!
2166662.418: PCI: 00:14.2 init finished in 6297 usecs
2166762.418: PCI: 00:14.3 init ...
2166862.418: lpc_init
2166962.418: PCI: 00:14.3 init finished in 2127 usecs
2167062.418: PCI: 00:14.4 init ...
2167162.418: PCI: 00:14.4 init finished in 1479 usecs
2167262.418: PCI: 00:14.5 init ...
2167362.418: PCI: 00:14.5 init finished in 1484 usecs
2167462.418: PCI: 03:00.0 init ...
2167562.418: PCI: 03:00.0 init finished in 1462 usecs
2167662.418: PCI: 04:00.0 init ...
2167762.418: PCI: 04:00.0 init finished in 1462 usecs
2167862.418: PCI: 07:00.0 init ...
2167962.418: PCI: 07:00.0 init finished in 1462 usecs
2168062.418: PCI: 07:00.1 init ...
2168162.418: PCI: 07:00.1 init finished in 1462 usecs
2168262.418: smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
2168362.418: Set SMBUS controller to channel 1
2168462.423: Found 64 pin W83795G Nuvoton H/W Monitor
2168562.706: W83795G/ADG work in Thermal Cruise Mode
2168662.706: Fan<09>CTFS(celsius)<09>TTTI(celsius)
2168762.709: 1<09>80<09>80
2168862.715: 2<09>80<09>80
2168962.720: 3<09>80<09>80
2169062.726: 4<09>80<09>80
2169162.731: 5<09>80<09>80
2169262.737: 6<09>80<09>80
2169362.742: DTS1 current value: 19
2169462.745: DTS2 current value: 18
2169562.748: DTS3 current value: 0
2169662.751: DTS4 current value: 0
2169762.754: DTS5 current value: 0
2169862.756: DTS6 current value: 0
2169962.759: DTS7 current value: 0
2170062.762: DTS8 current value: 0
2170162.767: Set SMBUS controller to channel 0
2170262.767: I2C: 01:2f init finished in 283804 usecs
2170362.767: PNP: 002e.2 init ...
2170462.767: PNP: 002e.2 init finished in 1399 usecs
2170562.767: PNP: 002e.3 init ...
2170662.767: PNP: 002e.3 init finished in 1399 usecs
2170762.767: PNP: 002e.5 init ...
2170862.767: PNP: 002e.5 init finished in 1415 usecs
2170962.767: PNP: 002e.a init ...
2171062.767: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2171162.767: CBFS: Locating 'cmos_layout.bin'
2171262.767: CBFS: Found @ offset 2b0c0 size e88
2171362.768: set power on after power fail
2171462.768: PNP: 002e.a init finished in 12038 usecs
2171562.768: PNP: 002e.b init ...
2171662.768: PNP: 002e.b init finished in 1399 usecs
2171762.768: PCI: 08:01.0 init ...
2171862.768: ASpeed AST2050: initializing video device
2171962.768: ast_detect_chip: AST 1100 detected
2172062.768: ast_detect_chip: VGA not enabled on entry, requesting chip POST
2172162.768: ast_detect_chip: Analog VGA only
2172262.768: ast_driver_load: dram 800000000 0 16 00800000
2172362.789: ASpeed VGA text mode initialized
2172462.789: PCI: 08:01.0 init finished in 33343 usecs
2172562.789: PCI: 08:02.0 init ...
2172662.789: PCI: 08:02.0 init finished in 1462 usecs
2172762.789: Devices initialized
2172862.789: Show all devs... After init.
2172962.789: Root Device: enabled 1
2173062.789: CPU_CLUSTER: 0: enabled 1
2173162.789: APIC: 00: enabled 1
2173262.789: DOMAIN: 0000: enabled 1
2173362.789: PCI: 00:18.0: enabled 1
2173462.789: PCI: 00:00.0: enabled 1
2173562.789: PCI: 00:00.1: enabled 0
2173662.789: PCI: 00:00.2: enabled 1
2173762.789: PCI: 00:02.0: enabled 1
2173862.789: PCI: 00:03.0: enabled 0
2173962.789: PCI: 00:04.0: enabled 1
2174062.789: PCI: 00:05.0: enabled 0
2174162.789: PCI: 00:06.0: enabled 0
2174262.789: PCI: 00:07.0: enabled 0
2174362.789: PCI: 00:08.0: enabled 0
2174462.789: PCI: 00:09.0: enabled 1
2174562.789: PCI: 00:0a.0: enabled 1
2174662.789: PCI: 00:0b.0: enabled 1
2174762.789: PCI: 00:0c.0: enabled 1
2174862.789: PCI: 00:0d.0: enabled 1
2174962.789: PCI: 00:11.0: enabled 1
2175062.789: PCI: 00:12.0: enabled 1
2175162.790: PCI: 00:12.1: enabled 1
2175262.790: PCI: 00:12.2: enabled 1
2175362.790: PCI: 00:13.0: enabled 1
2175462.790: PCI: 00:13.1: enabled 1
2175562.790: PCI: 00:13.2: enabled 1
2175662.790: PCI: 00:14.0: enabled 1
2175762.790: I2C: 01:50: enabled 1
2175862.790: I2C: 01:51: enabled 1
2175962.790: I2C: 01:52: enabled 1
2176062.790: I2C: 01:53: enabled 1
2176162.790: I2C: 01:54: enabled 1
2176262.790: I2C: 01:55: enabled 1
2176362.790: I2C: 01:56: enabled 1
2176462.790: I2C: 01:57: enabled 1
2176562.790: I2C: 01:2f: enabled 1
2176662.790: PCI: 00:14.1: enabled 1
2176762.790: PCI: 00:14.2: enabled 1
2176862.790: PCI: 00:14.3: enabled 1
2176962.790: PNP: 002e.0: enabled 0
2177062.790: PNP: 002e.1: enabled 0
2177162.790: PNP: 002e.2: enabled 1
2177262.790: PNP: 002e.3: enabled 1
2177362.790: PNP: 002e.5: enabled 1
2177462.790: PNP: 002e.106: enabled 0
2177562.790: PNP: 002e.107: enabled 0
2177662.790: PNP: 002e.207: enabled 0
2177762.790: PNP: 002e.307: enabled 0
2177862.790: PNP: 002e.407: enabled 0
2177962.790: PNP: 002e.8: enabled 0
2178062.790: PNP: 002e.108: enabled 0
2178162.790: PNP: 002e.9: enabled 0
2178262.790: PNP: 002e.109: enabled 0
2178362.790: PNP: 002e.209: enabled 0
2178462.790: PNP: 002e.309: enabled 0
2178562.790: PNP: 002e.a: enabled 1
2178662.790: PNP: 002e.b: enabled 1
2178762.790: PNP: 002e.c: enabled 0
2178862.790: PNP: 002e.d: enabled 0
2178962.790: PNP: 002e.f: enabled 0
2179062.790: PNP: 004e.0: enabled 1
2179162.790: PCI: 00:14.4: enabled 1
2179262.790: PCI: 08:01.0: enabled 1
2179362.790: PCI: 08:02.0: enabled 1
2179462.790: PCI: 08:03.0: enabled 0
2179562.790: PCI: 00:14.5: enabled 1
2179662.790: PCI: 00:18.1: enabled 1
2179762.790: PCI: 00:18.2: enabled 1
2179862.790: PCI: 00:18.3: enabled 1
2179962.790: PCI: 00:18.4: enabled 1
2180062.790: PCI: 00:18.5: enabled 1
2180162.790: PCI: 00:19.0: enabled 1
2180262.790: PCI: 00:19.1: enabled 1
2180362.790: PCI: 00:19.2: enabled 1
2180462.790: PCI: 00:19.3: enabled 1
2180562.790: PCI: 00:19.4: enabled 1
2180662.790: PCI: 00:19.5: enabled 1
2180762.790: PCI: 00:1a.0: enabled 1
2180862.790: PCI: 00:1a.1: enabled 1
2180962.790: PCI: 00:1a.2: enabled 1
2181062.790: PCI: 00:1a.3: enabled 1
2181162.790: PCI: 00:1a.4: enabled 1
2181262.790: PCI: 00:1a.5: enabled 1
2181362.790: PCI: 00:1b.0: enabled 1
2181462.790: PCI: 00:1b.1: enabled 1
2181562.790: PCI: 00:1b.2: enabled 1
2181662.790: PCI: 00:1b.3: enabled 1
2181762.790: PCI: 00:1b.4: enabled 1
2181862.790: PCI: 00:1b.5: enabled 1
2181962.790: APIC: 01: enabled 1
2182062.790: APIC: 02: enabled 1
2182162.790: APIC: 03: enabled 1
2182262.790: APIC: 04: enabled 1
2182362.790: APIC: 05: enabled 1
2182462.791: APIC: 06: enabled 1
2182562.791: APIC: 07: enabled 1
2182662.791: APIC: 08: enabled 1
2182762.791: APIC: 09: enabled 1
2182862.791: APIC: 0a: enabled 1
2182962.791: APIC: 0b: enabled 1
2183062.791: APIC: 0c: enabled 1
2183162.791: APIC: 0d: enabled 1
2183262.791: APIC: 0e: enabled 1
2183362.791: APIC: 0f: enabled 1
2183462.791: APIC: 20: enabled 1
2183562.791: APIC: 21: enabled 1
2183662.791: APIC: 22: enabled 1
2183762.791: APIC: 23: enabled 1
2183862.791: APIC: 24: enabled 1
2183962.791: APIC: 25: enabled 1
2184062.791: APIC: 26: enabled 1
2184162.791: APIC: 27: enabled 1
2184262.791: APIC: 28: enabled 1
2184362.791: APIC: 29: enabled 1
2184462.791: APIC: 2a: enabled 1
2184562.791: APIC: 2b: enabled 1
2184662.791: APIC: 2c: enabled 1
2184762.791: APIC: 2d: enabled 1
2184862.791: APIC: 2e: enabled 1
2184962.791: APIC: 2f: enabled 1
2185062.791: PCI: 03:00.0: enabled 1
2185162.791: PCI: 04:00.0: enabled 1
2185262.791: PCI: 07:00.0: enabled 1
2185362.791: PCI: 07:00.1: enabled 1
2185462.791: BS: BS_DEV_INIT times (us): entry 0 run 3353525 exit 0
2185562.791: Finalize devices...
2185662.791: Devices finalized
2185762.791: BS: BS_POST_DEVICE times (us): entry 0 run 2546 exit 0
2185862.791: BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
2185962.791: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2186062.791: CBFS: Locating 'cmos_layout.bin'
2186162.791: CBFS: Found @ offset 2b0c0 size e88
2186262.792: Writing IRQ routing tables to 0xf0000...done.
2186362.792: Writing IRQ routing tables to 0xb7cbe000...done.
2186462.792: PIRQ table: 48 bytes.
2186562.792: Wrote the mp table end at: 000f0410 - 000f08ac
2186662.792: Wrote the mp table end at: b7cbd010 - b7cbd4ac
2186762.792: MP table: 1196 bytes.
2186862.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2186962.792: CBFS: Locating 'fallback/dsdt.aml'
2187062.792: CBFS: Found @ offset 2bf80 size 2608
2187162.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2187262.792: CBFS: Locating 'fallback/slic'
2187362.792: CBFS: 'fallback/slic' not found.
2187462.792: ACPI: Writing ACPI tables at b7c99000.
2187562.792: ACPI: * FACS
2187662.792: ACPI: * DSDT
2187762.796: ACPI: * FADT
2187862.796: pm_base: 0x0800
2187962.796: ACPI: added table 1/32, length now 40
2188062.796: ACPI: * SSDT
2188162.796: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2188262.796: CBFS: Locating 'cmos_layout.bin'
2188362.796: CBFS: Found @ offset 2b0c0 size e88
2188462.796: processor_brand=AMD Opteron(tm) Processor 6278
2188562.796: Pstates algorithm ...
2188662.796: Pstate_freq[0] = 2400MHz<09>Pstate_power[0] = 6150mw
2188762.796: Pstate_latency[0] = 5us
2188862.796: Pstate_freq[1] = 2100MHz<09>Pstate_power[1] = 5233mw
2188962.796: Pstate_latency[1] = 5us
2189062.796: Pstate_freq[2] = 1900MHz<09>Pstate_power[2] = 4620mw
2189162.796: Pstate_latency[2] = 5us
2189262.796: Pstate_freq[3] = 1600MHz<09>Pstate_power[3] = 3990mw
2189362.796: Pstate_latency[3] = 5us
2189462.797: Pstate_freq[4] = 1400MHz<09>Pstate_power[4] = 3422mw
2189562.797: Pstate_latency[4] = 5us
2189662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2189762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2189862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2189962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2190062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2190162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2190262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2190362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2190462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2190562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2190662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2190762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2190862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2190962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2191062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2191162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2191262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2191362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2191462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2191562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2191662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2191762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2191862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2191962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2192062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2192162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2192262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2192362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2192462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2192562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2192662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2192762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2192862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2192962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2193062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2193162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2193262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2193362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2193462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2193562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2193662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2193762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2193862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2193962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2194062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2194162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2194262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2194362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2194462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2194562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2194662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2194762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2194862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2194962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2195062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2195162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2195262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2195362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2195462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2195562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2195662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2195762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2195862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2195962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2196062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2196162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2196262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2196362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2196462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2196562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2196662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2196762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2196862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2196962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2197062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2197162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2197262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2197362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2197462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2197562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2197662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2197762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2197862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2197962.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2198062.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2198162.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2198262.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2198362.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2198462.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
2198562.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
2198662.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
2198762.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
2198862.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
2198962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2199062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2199162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2199262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2199362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2199462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2199562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2199662.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2199762.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2199862.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2199962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2200062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2200162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2200262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2200362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2200462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2200562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2200662.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2200762.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2200862.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2200962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2201062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2201162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2201262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2201362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2201462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2201562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2201662.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2201762.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2201862.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2201962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2202062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2202162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2202262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2202362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2202462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2202562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2202662.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2202762.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2202862.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2202962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2203062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2203162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2203262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2203362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2203462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2203562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2203662.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2203762.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2203862.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2203962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2204062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2204162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2204262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2204362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2204462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2204562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2204662.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2204762.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2204862.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2204962.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2205062.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2205162.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
2205262.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
2205362.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
2205462.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
2205562.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
2205662.798: ACPI: added table 2/32, length now 44
2205762.798: ACPI: * MCFG
2205862.798: ACPI: added table 3/32, length now 48
2205962.798: ACPI: * TCPA
2206062.798: TCPA log created at b7c89000
2206162.798: ACPI: added table 4/32, length now 52
2206262.798: ACPI: * MADT
2206362.798: ACPI: added table 5/32, length now 56
2206462.798: current = b7c9f410
2206562.798: ACPI: * SRAT at b7c9f410
2206662.798: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
2206762.798: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
2206862.798: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
2206962.798: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
2207062.798: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
2207162.798: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
2207262.798: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
2207362.798: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
2207462.798: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
2207562.798: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
2207662.798: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
2207762.799: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
2207862.799: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
2207962.799: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
2208062.799: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
2208162.799: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
2208262.799: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
2208362.799: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
2208462.799: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
2208562.799: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
2208662.799: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
2208762.799: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
2208862.799: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
2208962.799: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
2209062.799: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
2209162.799: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
2209262.799: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
2209362.799: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
2209462.799: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
2209562.799: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
2209662.799: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
2209762.799: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
2209862.799: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
2209962.799: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
2210062.799: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
2210162.799: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
2210262.799: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
2210362.799: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
2210462.799: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
2210562.799: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
2210662.799: ACPI: added table 6/32, length now 60
2210762.799: ACPI: * SLIT at b7c9f730
2210862.799: ACPI: added table 7/32, length now 64
2210962.799: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2211062.799: CBFS: Locating 'cmos_layout.bin'
2211162.799: CBFS: Found @ offset 2b0c0 size e88
2211262.800: ACPI: * IVRS at b7c9f770
2211362.800: Capability: type 0x01 @ 0xc8
2211462.800: Capability: type 0x05 @ 0xd0
2211562.800: Capability: type 0x10 @ 0xe0
2211662.800: Capability: type 0x01 @ 0xc8
2211762.800: Capability: type 0x05 @ 0xd0
2211862.800: Capability: type 0x10 @ 0xe0
2211962.800: Capability: type 0x01 @ 0x40
2212062.800: Capability: type 0x05 @ 0x50
2212162.800: Capability: type 0x11 @ 0x70
2212262.800: Capability: type 0x10 @ 0xa0
2212362.800: Capability: type 0x01 @ 0x40
2212462.800: Capability: type 0x05 @ 0x50
2212562.800: Capability: type 0x11 @ 0x70
2212662.800: Capability: type 0x10 @ 0xa0
2212762.800: Capability: type 0x01 @ 0x40
2212862.800: Capability: type 0x01 @ 0x44
2212962.800: ACPI: added table 8/32, length now 68
2213062.800: ACPI: * HPET
2213162.800: ACPI: added table 9/32, length now 72
2213262.800: ACPI: * SRAT at b7c9f870
2213362.800: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
2213462.800: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
2213562.800: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
2213662.800: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
2213762.800: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
2213862.800: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
2213962.800: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
2214062.800: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
2214162.800: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
2214262.800: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
2214362.800: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
2214462.800: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
2214562.800: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
2214662.800: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
2214762.800: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
2214862.800: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
2214962.800: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
2215062.800: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
2215162.800: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
2215262.800: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
2215362.800: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
2215462.800: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
2215562.800: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
2215662.800: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
2215762.800: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
2215862.800: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
2215962.800: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
2216062.800: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
2216162.800: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
2216262.800: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
2216362.800: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
2216462.800: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
2216562.800: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
2216662.800: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
2216762.800: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
2216862.800: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
2216962.800: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
2217062.800: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
2217162.800: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
2217262.800: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
2217362.800: ACPI: added table 10/32, length now 76
2217462.800: ACPI: * SLIT at b7c9fb90
2217562.800: ACPI: added table 11/32, length now 80
2217662.800: ACPI: * SRAT at b7c9fbd0
2217762.800: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
2217862.800: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
2217962.800: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
2218062.800: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
2218162.800: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
2218262.800: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
2218362.800: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
2218462.800: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
2218562.800: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
2218662.800: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
2218762.800: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
2218862.800: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
2218962.800: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
2219062.800: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
2219162.800: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
2219262.800: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
2219362.800: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
2219462.800: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
2219562.800: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
2219662.800: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
2219762.800: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
2219862.800: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
2219962.800: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
2220062.800: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
2220162.801: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
2220262.801: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
2220362.801: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
2220462.801: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
2220562.801: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
2220662.801: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
2220762.801: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
2220862.801: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
2220962.801: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
2221062.801: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
2221162.801: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
2221262.801: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
2221362.801: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
2221462.801: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
2221562.801: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
2221662.801: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
2221762.801: ACPI: added table 12/32, length now 84
2221862.801: ACPI: * SLIT at b7c9fef0
2221962.801: ACPI: added table 13/32, length now 88
2222062.801: ACPI: * SRAT at b7c9ff30
2222162.801: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
2222262.801: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
2222362.801: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
2222462.801: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
2222562.801: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
2222662.801: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
2222762.801: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
2222862.801: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
2222962.801: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
2223062.801: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
2223162.801: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
2223262.801: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
2223362.801: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
2223462.801: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
2223562.801: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
2223662.801: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
2223762.801: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
2223862.801: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
2223962.801: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
2224062.801: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
2224162.801: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
2224262.801: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
2224362.801: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
2224462.801: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
2224562.801: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
2224662.801: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
2224762.801: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
2224862.801: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
2224962.801: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
2225062.801: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
2225162.801: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
2225262.801: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
2225362.801: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
2225462.801: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
2225562.801: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
2225662.801: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
2225762.801: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
2225862.801: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
2225962.801: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
2226062.801: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
2226162.801: ACPI: added table 14/32, length now 92
2226262.801: ACPI: * SLIT at b7ca0250
2226362.801: ACPI: added table 15/32, length now 96
2226462.801: ACPI: done.
2226562.801: ACPI tables: 29328 bytes.
2226662.801: smbios_write_tables: b7c88000
2226762.801: Root Device (ASUS KGPE-D16)
2226862.801: CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
2226962.801: APIC: 00 (unknown)
2227062.801: DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
2227162.801: PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
2227262.801: PCI: 00:00.0 (ATI SR5650)
2227362.801: PCI: 00:00.1 (ATI SR5650)
2227462.801: PCI: 00:00.2 (ATI SR5650)
2227562.801: PCI: 00:02.0 (ATI SR5650)
2227662.801: PCI: 00:03.0 (ATI SR5650)
2227762.801: PCI: 00:04.0 (ATI SR5650)
2227862.801: PCI: 00:05.0 (ATI SR5650)
2227962.801: PCI: 00:06.0 (ATI SR5650)
2228062.801: PCI: 00:07.0 (ATI SR5650)
2228162.801: PCI: 00:08.0 (ATI SR5650)
2228262.801: PCI: 00:09.0 (ATI SR5650)
2228362.801: PCI: 00:0a.0 (ATI SR5650)
2228462.801: PCI: 00:0b.0 (ATI SR5650)
2228562.801: PCI: 00:0c.0 (ATI SR5650)
2228662.801: PCI: 00:0d.0 (ATI SR5650)
2228762.801: PCI: 00:11.0 (ATI SP5100)
2228862.801: PCI: 00:12.0 (ATI SP5100)
2228962.801: PCI: 00:12.1 (ATI SP5100)
2229062.801: PCI: 00:12.2 (ATI SP5100)
2229162.801: PCI: 00:13.0 (ATI SP5100)
2229262.801: PCI: 00:13.1 (ATI SP5100)
2229362.801: PCI: 00:13.2 (ATI SP5100)
2229462.802: PCI: 00:14.0 (ATI SP5100)
2229562.802: I2C: 01:50 (unknown)
2229662.802: I2C: 01:51 (unknown)
2229762.802: I2C: 01:52 (unknown)
2229862.802: I2C: 01:53 (unknown)
2229962.802: I2C: 01:54 (unknown)
2230062.802: I2C: 01:55 (unknown)
2230162.802: I2C: 01:56 (unknown)
2230262.802: I2C: 01:57 (unknown)
2230362.802: I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
2230462.802: PCI: 00:14.1 (ATI SP5100)
2230562.802: PCI: 00:14.2 (ATI SP5100)
2230662.802: PCI: 00:14.3 (ATI SP5100)
2230762.802: PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
2230862.802: PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
2230962.802: PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
2231062.802: PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
2231162.802: PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
2231262.802: PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
2231362.802: PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
2231462.802: PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
2231562.802: PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
2231662.802: PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
2231762.802: PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
2231862.802: PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
2231962.802: PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
2232062.802: PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
2232162.802: PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
2232262.802: PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
2232362.802: PNP: 002e.a (WINBOND W83667HG-A Super I/O)
2232462.802: PNP: 002e.b (WINBOND W83667HG-A Super I/O)
2232562.802: PNP: 002e.c (WINBOND W83667HG-A Super I/O)
2232662.802: PNP: 002e.d (WINBOND W83667HG-A Super I/O)
2232762.802: PNP: 002e.f (WINBOND W83667HG-A Super I/O)
2232862.802: PNP: 004e.0 (unknown)
2232962.802: PCI: 00:14.4 (ATI SP5100)
2233062.802: PCI: 08:01.0 (ATI SP5100)
2233162.802: PCI: 08:02.0 (ATI SP5100)
2233262.802: PCI: 08:03.0 (ATI SP5100)
2233362.802: PCI: 00:14.5 (ATI SP5100)
2233462.802: PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
2233562.802: PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
2233662.802: PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
2233762.802: PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
2233862.802: PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
2233962.802: PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
2234062.802: PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
2234162.802: PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
2234262.802: PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
2234362.802: PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
2234462.802: PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
2234562.802: PCI: 00:1a.0 (AMD Family 10h/15h Northbridge)
2234662.802: PCI: 00:1a.1 (AMD Family 10h/15h Northbridge)
2234762.802: PCI: 00:1a.2 (AMD Family 10h/15h Northbridge)
2234862.802: PCI: 00:1a.3 (AMD Family 10h/15h Northbridge)
2234962.802: PCI: 00:1a.4 (AMD Family 10h/15h Northbridge)
2235062.802: PCI: 00:1a.5 (AMD Family 10h/15h Northbridge)
2235162.802: PCI: 00:1b.0 (AMD Family 10h/15h Northbridge)
2235262.802: PCI: 00:1b.1 (AMD Family 10h/15h Northbridge)
2235362.802: PCI: 00:1b.2 (AMD Family 10h/15h Northbridge)
2235462.802: PCI: 00:1b.3 (AMD Family 10h/15h Northbridge)
2235562.802: PCI: 00:1b.4 (AMD Family 10h/15h Northbridge)
2235662.802: PCI: 00:1b.5 (AMD Family 10h/15h Northbridge)
2235762.802: APIC: 01 (unknown)
2235862.802: APIC: 02 (unknown)
2235962.802: APIC: 03 (unknown)
2236062.802: APIC: 04 (unknown)
2236162.802: APIC: 05 (unknown)
2236262.802: APIC: 06 (unknown)
2236362.802: APIC: 07 (unknown)
2236462.802: APIC: 08 (unknown)
2236562.802: APIC: 09 (unknown)
2236662.802: APIC: 0a (unknown)
2236762.802: APIC: 0b (unknown)
2236862.802: APIC: 0c (unknown)
2236962.802: APIC: 0d (unknown)
2237062.802: APIC: 0e (unknown)
2237162.802: APIC: 0f (unknown)
2237262.802: APIC: 20 (unknown)
2237362.802: APIC: 21 (unknown)
2237462.803: APIC: 22 (unknown)
2237562.803: APIC: 23 (unknown)
2237662.803: APIC: 24 (unknown)
2237762.803: APIC: 25 (unknown)
2237862.803: APIC: 26 (unknown)
2237962.803: APIC: 27 (unknown)
2238062.803: APIC: 28 (unknown)
2238162.803: APIC: 29 (unknown)
2238262.803: APIC: 2a (unknown)
2238362.803: APIC: 2b (unknown)
2238462.803: APIC: 2c (unknown)
2238562.803: APIC: 2d (unknown)
2238662.803: APIC: 2e (unknown)
2238762.803: APIC: 2f (unknown)
2238862.803: PCI: 03:00.0 (unknown)
2238962.803: PCI: 04:00.0 (unknown)
2239062.803: PCI: 07:00.0 (unknown)
2239162.803: PCI: 07:00.1 (unknown)
2239262.803: SMBIOS tables: 1819 bytes.
2239362.803: Writing table forward entry at 0x00000500
2239462.803: Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5812
2239562.803: Writing coreboot table at 0xb7cbf000
2239662.803: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2239762.803: CBFS: Locating 'cmos_layout.bin'
2239862.803: CBFS: Found @ offset 2b0c0 size e88
2239962.804: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
2240062.804: 1. 0000000000001000-000000000009ffff: RAM
2240162.804: 2. 00000000000a0000-00000000000bffff: RESERVED
2240262.804: 3. 00000000000c0000-00000000b7c87fff: RAM
2240362.804: 4. 00000000b7c88000-00000000b7ffffff: CONFIGURATION TABLES
2240462.804: 5. 00000000b8000000-00000000bfffffff: RAM
2240562.804: 6. 00000000c0000000-00000000cfffffff: RESERVED
2240662.804: 7. 00000000fcb00000-00000000fcb03fff: RESERVED
2240762.804: 8. 00000000feb00000-00000000feb00fff: RESERVED
2240862.804: 9. 00000000fec00000-00000000fec00fff: RESERVED
2240962.804: 10. 00000000fed00000-00000000fed00fff: RESERVED
2241062.804: 11. 0000000100000000-0000004037ffffff: RAM
2241162.804: 12. 0000004038000000-000000403fffffff: RESERVED
2241262.804: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2241362.804: CBFS: Locating 'cmos_layout.bin'
2241462.804: CBFS: Found @ offset 2b0c0 size e88
2241562.805: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2241662.805: FMAP: Found "FLASH" version 1.1 at 0.
2241762.805: FMAP: base = ff000000 size = 1000000 #areas = 3
2241862.805: Wrote coreboot table at: b7cbf000, 0x1208 bytes, checksum deaf
2241962.805: coreboot table: 4640 bytes.
2242062.805: IMD ROOT 0. b7fff000 00001000
2242162.805: IMD SMALL 1. b7ffe000 00001000
2242262.805: CAR GLOBALS 2. b7ff3000 0000a6c0
2242362.805: CONSOLE 3. b7fd3000 00020000
2242462.805: TIME STAMP 4. b7fd2000 00000400
2242562.805: AMDMEM INFO 5. b7fc8000 000093fc
2242662.805: ACPI RESUME 6. b7cc7000 00301000
2242762.805: COREBOOT 7. b7cbf000 00008000
2242862.805: IRQ TABLE 8. b7cbe000 00001000
2242962.805: SMP TABLE 9. b7cbd000 00001000
2243062.805: ACPI 10. b7c99000 00024000
2243162.805: TCPA LOG 11. b7c89000 00010000
2243262.806: SMBIOS 12. b7c88000 00000800
2243362.806: IMD small region:
2243462.806: IMD ROOT 0. b7ffec00 00000400
2243562.806: ROMSTAGE 1. b7ffebe0 00000004
2243662.806: GDT 2. b7ffe9e0 00000200
2243762.806: Writing AMD DCT configuration to Flash
2243862.808: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2243962.808: CBFS: Locating 'cmos_layout.bin'
2244062.808: CBFS: Found @ offset 2b0c0 size e88
2244162.809: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2244262.809: CBFS: Locating 'cmos_layout.bin'
2244362.809: CBFS: Found @ offset 2b0c0 size e88
2244462.809: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2244562.809: CBFS: Locating 'cmos_layout.bin'
2244662.809: CBFS: Found @ offset 2b0c0 size e88
2244762.810: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2244862.810: CBFS: Locating 'cmos_layout.bin'
2244962.810: CBFS: Found @ offset 2b0c0 size e88
2245062.811: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2245162.811: CBFS: Locating 'cmos_layout.bin'
2245262.811: CBFS: Found @ offset 2b0c0 size e88
2245362.811: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2245462.811: CBFS: Locating 'cmos_layout.bin'
2245562.811: CBFS: Found @ offset 2b0c0 size e88
2245662.812: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2245762.812: CBFS: Locating 'cmos_layout.bin'
2245862.812: CBFS: Found @ offset 2b0c0 size e88
2245962.812: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2246062.812: CBFS: Locating 'cmos_layout.bin'
2246162.812: CBFS: Found @ offset 2b0c0 size e88
2246262.813: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2246362.813: CBFS: Locating 'cmos_layout.bin'
2246462.813: CBFS: Found @ offset 2b0c0 size e88
2246562.813: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2246662.813: CBFS: Locating 'cmos_layout.bin'
2246762.813: CBFS: Found @ offset 2b0c0 size e88
2246862.814: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2246962.814: CBFS: Locating 's3nv'
2247062.814: CBFS: Found @ offset 2fec0 size 10000
2247162.814: Manufacturer: ef
2247262.814: SF: Detected W25Q128 with sector size 0x1000, total 0x1000000
2247362.816: SF: Successfully erased 32768 bytes @ 0x38000
2247463.159: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2247563.159: CBFS: Locating 'cmos_layout.bin'
2247663.159: CBFS: Found @ offset 2b0c0 size e88
2247763.160: BS: BS_WRITE_TABLES times (us): entry 0 run 1989715 exit 0
2247863.160: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
2247963.160: CBFS: Locating 'fallback/payload'
2248063.160: CBFS: Found @ offset 95600 size e920
2248163.160: Loading segment from ROM address 0xff095738
2248263.160: code (compression=1)
2248363.160: New segment dstaddr 0xe4460 memsize 0x1bba0 srcaddr 0xff095770 filesize 0xe8e8
2248463.160: Loading segment from ROM address 0xff095754
2248563.160: Entry Point 0x000ff06e
2248663.160: Bounce Buffer at bfdd1000, 2287584 bytes
2248763.160: Loading Segment: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
2248863.160: lb: [0x0000000000100000, 0x00000000002173f0)
2248963.160: Post relocation: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
2249063.160: using LZMA
2249163.188: [ 0x000e4460, 00100000, 0x00100000) <- ff095770
2249263.188: dest 000e4460, end 00100000, bouncebuffer bfdd1000
2249363.188: Loaded segments
2249463.188: BS: BS_PAYLOAD_LOAD times (us): entry 0 run 68937 exit 0
2249563.188: Jumping to boot code at 000ff06e(b7cbf000)
2249663.188: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
2249763.188: entry = 0x000ff06e
2249863.188: lb_start = 0x00100000
2249963.188: lb_size = 0x001173f0
2250063.189: buffer = 0xbfdd1000
2250163.189: SeaBIOS (version rel-1.10.0-25-g1415d46)
2250263.189: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
2250363.189: Attempting to find coreboot table
2250463.189: Found coreboot table forwarder.
2250563.189: Now attempting to find coreboot memory map
2250663.189: SeaBIOS (version rel-1.10.0-25-g1415d46)
2250763.189: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
2250863.189: Found coreboot cbmem console @ b7fd3000
2250963.189: Found mainboard ASUS KGPE-D16
2251063.189: malloc preinit
2251163.189: Relocating init from 0x000e5980 to 0xbffb4ca0 (size 45728)
2251263.189: malloc init
2251363.189: Found CBFS header at 0xff000138
2251463.189: Add romfile: cbfs master header (size=32)
2251563.189: Add romfile: fallback/romstage (size=174404)
2251663.189: Add romfile: config (size=603)
2251763.189: Add romfile: revision (size=570)
2251863.189: Add romfile: cmos.default (size=256)
2251963.189: Add romfile: cmos_layout.bin (size=3720)
2252063.189: Add romfile: fallback/dsdt.aml (size=9736)
2252163.189: Add romfile: bootorder (size=31)
2252263.190: Add romfile: (size=6168)
2252363.190: Add romfile: s3nv (size=65536)
2252463.190: Add romfile: fallback/ramstage (size=87116)
2252563.190: Add romfile: pci1106,3230.rom (size=27648)
2252663.190: Add romfile: img/coreinfo (size=109556)
2252763.190: Add romfile: img/nvramcui (size=125256)
2252863.190: Add romfile: fallback/payload (size=59680)
2252963.190: Add romfile: img/memtest (size=180268)
2253063.190: Add romfile: microcode_amd.bin (size=12684)
2253163.190: Add romfile: microcode_amd_fam15h.bin (size=7876)
2253263.190: Add romfile: vgaroms/seavgabios.bin (size=27648)
2253363.190: Add romfile: (size=15873240)
2253463.190: Add romfile: bootblock (size=3048)
2253563.190: multiboot: eax=0, ebx=0
2253663.190: init ivt
2253763.190: init bda
2253863.190: Copying romfile 'bootorder' (len 31)
2253963.190: Copying data 31@0xff02e738 to 31@0xbffb3ae0
2254063.190: boot order:
2254163.190: 1: /pci@i0cf8/*@11/drive@3/disk@0
2254263.190: 2:
2254363.190: init bios32
2254463.190: init PMM
2254563.190: init PNPBIOS table
2254663.190: init keyboard
2254763.190: init mouse
2254863.190: init pic
2254963.190: math cp init
2255063.190: PCI probe
2255163.190: PCI device 00:00.0 (vd=1002:5a10 c=0600)
2255263.190: PCI device 00:00.2 (vd=1002:5a23 c=0806)
2255363.190: PCI device 00:02.0 (vd=1002:5a16 c=0604)
2255463.190: PCI device 00:04.0 (vd=1002:5a18 c=0604)
2255563.190: PCI device 00:09.0 (vd=1002:5a1c c=0604)
2255663.190: PCI device 00:0a.0 (vd=1002:5a1d c=0604)
2255763.190: PCI device 00:0b.0 (vd=1002:5a1f c=0604)
2255863.190: PCI device 00:0c.0 (vd=1002:5a20 c=0604)
2255963.190: PCI device 00:0d.0 (vd=1002:5a1e c=0604)
2256063.190: PCI device 00:11.0 (vd=1002:4394 c=0106)
2256163.190: PCI device 00:12.0 (vd=1002:4397 c=0c03)
2256263.190: PCI device 00:12.1 (vd=1002:4398 c=0c03)
2256363.190: PCI device 00:12.2 (vd=1002:4396 c=0c03)
2256463.190: PCI device 00:13.0 (vd=1002:4397 c=0c03)
2256563.190: PCI device 00:13.1 (vd=1002:4398 c=0c03)
2256663.190: PCI device 00:13.2 (vd=1002:4396 c=0c03)
2256763.191: PCI device 00:14.0 (vd=1002:4385 c=0c05)
2256863.191: PCI device 00:14.1 (vd=1002:439c c=0101)
2256963.191: PCI device 00:14.2 (vd=1002:4383 c=0403)
2257063.191: PCI device 00:14.3 (vd=1002:439d c=0601)
2257163.191: PCI device 00:14.4 (vd=1002:4384 c=0604)
2257263.191: PCI device 00:14.5 (vd=1002:4399 c=0c03)
2257363.191: PCI device 00:18.0 (vd=1022:1600 c=0600)
2257463.191: PCI device 00:18.1 (vd=1022:1601 c=0600)
2257563.191: PCI device 00:18.2 (vd=1022:1602 c=0600)
2257663.191: PCI device 00:18.3 (vd=1022:1603 c=0600)
2257763.191: PCI device 00:18.4 (vd=1022:1604 c=0600)
2257863.191: PCI device 00:18.5 (vd=1022:1605 c=0600)
2257963.191: PCI device 00:19.0 (vd=1022:1600 c=0600)
2258063.191: PCI device 00:19.1 (vd=1022:1601 c=0600)
2258163.191: PCI device 00:19.2 (vd=1022:1602 c=0600)
2258263.191: PCI device 00:19.3 (vd=1022:1603 c=0600)
2258363.191: PCI device 00:19.4 (vd=1022:1604 c=0600)
2258463.191: PCI device 00:19.5 (vd=1022:1605 c=0600)
2258563.191: PCI device 00:1a.0 (vd=1022:1600 c=0600)
2258663.191: PCI device 00:1a.1 (vd=1022:1601 c=0600)
2258763.191: PCI device 00:1a.2 (vd=1022:1602 c=0600)
2258863.191: PCI device 00:1a.3 (vd=1022:1603 c=0600)
2258963.191: PCI device 00:1a.4 (vd=1022:1604 c=0600)
2259063.191: PCI device 00:1a.5 (vd=1022:1605 c=0600)
2259163.191: PCI device 00:1b.0 (vd=1022:1600 c=0600)
2259263.191: PCI device 00:1b.1 (vd=1022:1601 c=0600)
2259363.191: PCI device 00:1b.2 (vd=1022:1602 c=0600)
2259463.191: PCI device 00:1b.3 (vd=1022:1603 c=0600)
2259563.191: PCI device 00:1b.4 (vd=1022:1604 c=0600)
2259663.191: PCI device 00:1b.5 (vd=1022:1605 c=0600)
2259763.191: PCI device 03:00.0 (vd=8086:10d3 c=0200)
2259863.191: PCI device 04:00.0 (vd=8086:10d3 c=0200)
2259963.191: PCI device 07:00.0 (vd=8086:10fb c=0200)
2260063.191: PCI device 07:00.1 (vd=8086:10fb c=0200)
2260163.191: PCI device 08:01.0 (vd=1a03:2000 c=0300)
2260263.191: PCI device 08:02.0 (vd=11c1:5811 c=0c00)
2260363.191: Found 52 PCI devices (max PCI bus is 08)
2260463.191: Relocating coreboot bios tables
2260563.191: Copying SMBIOS entry point from 0xb7c88000 to 0x000f0c00
2260663.191: Copying ACPI RSDP from 0xb7c99000 to 0x000f0bd0
2260763.191: Skipping MPTABLE copy due to large size (1196 bytes)
2260863.191: Copying PIR from 0xb7cbe000 to 0x000f0ba0
2260963.193: rsdp=0x000f0bd0
2261063.193: rsdt=0xb7c99030
2261163.193: table(50434146)=0xb7c9b890
2261263.193: pm_tmr_blk=820
2261363.193: Using pmtimer, ioport 0x820
2261463.193: init timer
2261563.193: Scan for VGA option rom
2261663.193: Attempting to init PCI bdf 08:01.0 (vd 1a03:2000)
2261763.193: Copying data 27648@0xff0d5288 to 27648@0x000c0000
2261863.202: Running option rom at c000:0003
2261963.202: Start SeaVGABIOS (version rel-1.10.0-25-g1415d46)
2262063.202: VGABUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
2262163.202: enter vga_post:
2262263.202: a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000
2262363.202: si=00000000 di=00008020 bp=00000000 sp=00006dda cs=f000 ip=cfd0 f=0000
2262463.202: coreboot vga init
2262563.202: Found coreboot table forwarder.
2262663.202: Did not find coreboot framebuffer - assuming EGA text
2262763.202: Attempting to allocate VGA stack via pmm call to f000:d03f
2262863.202: pmm call arg1=0
2262963.202: pmm00: length=20 handle=ffffffff flags=9
2263063.202: VGA stack allocated at ef580
2263163.202: Hooking hardware timer irq (old=f000fea5 new=c0003ed0)
2263263.202: Turning on vga text mode console
2263363.202: set VGA mode 3
2263463.203: SeaBIOS (version rel-1.10.0-25-g1415d46)
2263563.203: init usb
2263663.203: EHCI init on dev 00:12.2 (regs=0xfcb0e020)
2263763.203: /bffb1000\ Start thread
2263863.203: EHCI init on dev 00:13.2 (regs=0xfcb0f020)
2263963.203: /bffb0000\ Start thread
2264063.203: OHCI init on dev 00:12.0 (regs=0xfcb08000)
2264163.203: /bffaf000\ Start thread
2264263.203: OHCI init on dev 00:12.1 (regs=0xfcb09000)
2264363.203: /bffae000\ Start thread
2264463.203: OHCI init on dev 00:13.0 (regs=0xfcb0a000)
2264563.203: /bffad000\ Start thread
2264663.203: /bffac000\ Start thread
2264763.203: \bffac000/ End thread
2264863.203: OHCI init on dev 00:13.1 (regs=0xfcb0b000)
2264963.203: /bffac000\ Start thread
2265063.203: /bffab000\ Start thread
2265163.203: /bffaa000\ Start thread
2265263.203: OHCI init on dev 00:14.5 (regs=0xfcb0c000)
2265363.203: /bffa9000\ Start thread
2265463.203: /bffa8000\ Start thread
2265563.203: /bffa7000\ Start thread
2265663.203: init ps2port
2265763.203: /bffa6000\ Start thread
2265863.207: /bffa5000\ Start thread
2265963.207: /bffa3000\ Start thread
2266063.207: init ahci
2266163.207: AHCI controller at 00:11.0, iobase 0xfcb0d000, irq 0
2266263.207: AHCI: cap 0xf322ff85, ports_impl 0x3f
2266363.207: /bffa2000\ Start thread
2266463.207: |bffa2000| AHCI/0: probing
2266563.207: |bffa2000| AHCI/0: link up
2266663.207: /bffa1000\ Start thread
2266763.207: /bffa0000\ Start thread
2266863.207: /bff9f000\ Start thread
2266963.207: |bff9f000| AHCI/1: probing
2267063.207: |bff9f000| AHCI/1: link up
2267163.207: |bffa2000| AHCI/0: ... finished, status 0x51, ERROR 0x4
2267263.207: /bff9d000\ Start thread
2267363.207: /bff9c000\ Start thread
2267463.207: /bff9b000\ Start thread
2267563.207: /bff9a000\ Start thread
2267663.207: /bff99000\ Start thread
2267763.207: /bff98000\ Start thread
2267863.207: |bff98000| AHCI/2: probing
2267963.207: |bff9f000| AHCI/1: ... finished, status 0x51, ERROR 0x4
2268063.207: |bffa2000| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
2268163.207: |bffa2000| AHCI/0: supported modes: udma 6, multi-dma 2, pio 4
2268263.207: |bffa2000| AHCI/0: Set transfer mode to UDMA-6
2268363.207: /bff97000\ Start thread
2268463.207: /bff96000\ Start thread
2268563.207: /bff95000\ Start thread
2268663.207: /bff94000\ Start thread
2268763.207: |bff9b000| set_address 0xbffb2730
2268863.207: /bff93000\ Start thread
2268963.207: \bff93000/ End thread
2269063.207: \bff9a000/ End thread
2269163.207: \bffa1000/ End thread
2269263.207: \bffa5000/ End thread
2269363.208: \bffa8000/ End thread
2269463.208: \bffab000/ End thread
2269563.208: \bff99000/ End thread
2269663.208: \bffa0000/ End thread
2269763.208: \bffa3000/ End thread
2269863.208: \bffa7000/ End thread
2269963.208: \bffaa000/ End thread
2270063.208: /bffaa000\ Start thread
2270163.208: |bffaa000| AHCI/3: probing
2270263.208: |bffaa000| AHCI/3: link up
2270363.208: |bff98000| AHCI/2: link down
2270463.208: |bff9f000| Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0
2270563.208: |bff9f000| AHCI/1: supported modes: udma 6, multi-dma 2, pio 4
2270663.208: |bff9f000| AHCI/1: Set transfer mode to UDMA-6
2270763.208: /bffa8000\ Start thread
2270863.208: /bffa7000\ Start thread
2270963.208: /bffa5000\ Start thread
2271063.208: \bffa5000/ End thread
2271163.208: \bff96000/ End thread
2271263.208: \bff9d000/ End thread
2271363.208: /bffa5000\ Start thread
2271463.208: \bffa5000/ End thread
2271563.208: \bff95000/ End thread
2271663.208: \bff9c000/ End thread
2271763.208: /bffa5000\ Start thread
2271863.208: \bffa5000/ End thread
2271963.208: \bff94000/ End thread
2272063.208: /bffa5000\ Start thread
2272163.208: |bffa5000| AHCI/4: probing
2272263.208: |bffaa000| AHCI/3: ... finished, status 0x51, ERROR 0x4
2272363.208: \bff98000/ End thread
2272463.208: |bffa2000| AHCI/0: registering: "AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
2272563.208: |bffa2000| Registering bootable: AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0b30)
2272663.208: \bffa2000/ End thread
2272763.208: /bffa3000\ Start thread
2272863.208: /bffa2000\ Start thread
2272963.208: \bffa2000/ End thread
2273063.208: \bffa7000/ End thread
2273163.208: \bff97000/ End thread
2273263.208: /bffa2000\ Start thread
2273363.208: |bffa2000| AHCI/5: probing
2273463.208: |bffa5000| AHCI/4: link down
2273563.208: |bffaa000| Searching bootorder for: /pci@i0cf8/*@11/drive@3/disk@0
2273663.208: |bffaa000| AHCI/3: supported modes: udma 6, multi-dma 2, pio 4
2273763.208: |bffaa000| AHCI/3: Set transfer mode to UDMA-6
2273863.208: |bff9f000| AHCI/1: registering: "AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
2273963.208: |bff9f000| Registering bootable: AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0ae0)
2274063.208: \bff9f000/ End thread
2274163.208: \bffa3000/ End thread
2274263.208: \bffa8000/ End thread
2274363.208: \bffad000/ End thread
2274463.208: \bffae000/ End thread
2274563.208: |bff9b000| config_usb: 0xbffab9b0
2274663.208: \bffb0000/ End thread
2274763.208: \bffb1000/ End thread
2274863.208: init lpt
2274963.208: Found 0 lpt ports
2275063.208: init serial
2275163.208: Found 2 serial ports
2275263.208: Searching bootorder for: /rom@img/memtest
2275363.208: Registering bootable: Payload [memtest] (type:32 prio:9999 data:ff0a4080)
2275463.208: Searching bootorder for: /rom@img/nvramcui
2275563.208: Registering bootable: Payload [nvramcui] (type:32 prio:9999 data:ff076d80)
2275663.208: Searching bootorder for: /rom@img/coreinfo
2275763.208: Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ff05c140)
2275863.209: |bffa2000| AHCI/5: link down
2275963.209: \bffa5000/ End thread
2276063.209: \bffac000/ End thread
2276163.209: |bff9b000| device rev=0110 cls=00 sub=00 proto=00 size=8
2276263.209: \bffa2000/ End thread
2276363.209: |bffaa000| AHCI/3: registering: "AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes)"
2276463.209: |bffaa000| Registering bootable: AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes) (type:2 prio:1 data:f0a90)
2276563.209: \bffaa000/ End thread
2276663.209: \bffa9000/ End thread
2276763.211: |bff9b000| usb_hid_setup 0xbffab9b0
2276863.211: |bff9b000| USB keyboard initialized
2276963.211: \bff9b000/ End thread
2277063.212: \bffaf000/ End thread
2277163.338: |bffa6000| PS2 keyboard initialized
2277263.338: \bffa6000/ End thread
2277363.338: All threads complete.
2277463.338: Scan for option roms
2277563.338: Attempting to init PCI bdf 00:00.0 (vd 1002:5a10)
2277663.338: Attempting to init PCI bdf 00:00.2 (vd 1002:5a23)
2277763.338: Attempting to init PCI bdf 00:02.0 (vd 1002:5a16)
2277863.338: Attempting to init PCI bdf 00:04.0 (vd 1002:5a18)
2277963.338: Attempting to init PCI bdf 00:09.0 (vd 1002:5a1c)
2278063.338: Attempting to init PCI bdf 00:0a.0 (vd 1002:5a1d)
2278163.338: Attempting to init PCI bdf 00:0b.0 (vd 1002:5a1f)
2278263.338: Attempting to init PCI bdf 00:0c.0 (vd 1002:5a20)
2278363.338: Attempting to init PCI bdf 00:0d.0 (vd 1002:5a1e)
2278463.338: Attempting to init PCI bdf 00:14.0 (vd 1002:4385)
2278563.338: Attempting to init PCI bdf 00:14.1 (vd 1002:439c)
2278663.338: Attempting to init PCI bdf 00:14.2 (vd 1002:4383)
2278763.338: Attempting to init PCI bdf 00:14.3 (vd 1002:439d)
2278863.338: Attempting to init PCI bdf 00:14.4 (vd 1002:4384)
2278963.338: Attempting to init PCI bdf 00:18.0 (vd 1022:1600)
2279063.338: Attempting to init PCI bdf 00:18.1 (vd 1022:1601)
2279163.338: Attempting to init PCI bdf 00:18.2 (vd 1022:1602)
2279263.338: Attempting to init PCI bdf 00:18.3 (vd 1022:1603)
2279363.338: Attempting to init PCI bdf 00:18.4 (vd 1022:1604)
2279463.338: Attempting to init PCI bdf 00:18.5 (vd 1022:1605)
2279563.338: Attempting to init PCI bdf 00:19.0 (vd 1022:1600)
2279663.338: Attempting to init PCI bdf 00:19.1 (vd 1022:1601)
2279763.338: Attempting to init PCI bdf 00:19.2 (vd 1022:1602)
2279863.338: Attempting to init PCI bdf 00:19.3 (vd 1022:1603)
2279963.338: Attempting to init PCI bdf 00:19.4 (vd 1022:1604)
2280063.338: Attempting to init PCI bdf 00:19.5 (vd 1022:1605)
2280163.338: Attempting to init PCI bdf 00:1a.0 (vd 1022:1600)
2280263.338: Attempting to init PCI bdf 00:1a.1 (vd 1022:1601)
2280363.338: Attempting to init PCI bdf 00:1a.2 (vd 1022:1602)
2280463.338: Attempting to init PCI bdf 00:1a.3 (vd 1022:1603)
2280563.338: Attempting to init PCI bdf 00:1a.4 (vd 1022:1604)
2280663.338: Attempting to init PCI bdf 00:1a.5 (vd 1022:1605)
2280763.338: Attempting to init PCI bdf 00:1b.0 (vd 1022:1600)
2280863.338: Attempting to init PCI bdf 00:1b.1 (vd 1022:1601)
2280963.338: Attempting to init PCI bdf 00:1b.2 (vd 1022:1602)
2281063.339: Attempting to init PCI bdf 00:1b.3 (vd 1022:1603)
2281163.339: Attempting to init PCI bdf 00:1b.4 (vd 1022:1604)
2281263.338: Attempting to init PCI bdf 00:1b.5 (vd 1022:1605)
2281363.339: Attempting to init PCI bdf 03:00.0 (vd 8086:10d3)
2281463.339: Attempting to init PCI bdf 04:00.0 (vd 8086:10d3)
2281563.339: Attempting to init PCI bdf 07:00.0 (vd 8086:10fb)
2281663.339: Attempting to init PCI bdf 07:00.1 (vd 8086:10fb)
2281763.339: Attempting to init PCI bdf 08:02.0 (vd 11c1:5811)
2281863.339:
2281963.339: Press ESC for boot menu.
2282063.339:
2282163.339: Checking for bootsplash
2282264.210: Select boot device:
2282364.210:
2282464.210: 1. AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiByte
2282564.210: 2. AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
2282664.210: 3. AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
2282764.210: 4. Payload [memtest]
2282864.210: 5. Payload [nvramcui]
2282964.210: 6. Payload [coreinfo]
2283074.346:
2283174.346: Searching bootorder for: HALT
2283274.346: Mapping hd drive 0x000f0a90 to 0
2283374.346: drive 0x000f0a90: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
2283474.346: Mapping hd drive 0x000f0b30 to 1
2283574.346: drive 0x000f0b30: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
2283674.346: Mapping hd drive 0x000f0ae0 to 2
2283774.346: drive 0x000f0ae0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
2283874.346: finalize PMM
2283974.346: malloc finalize
2284074.346: Space available for UMB: c7000-ee800, f0000-f0a90
2284174.346: Returned 245760 bytes of ZoneHigh
2284274.346: e820 map has 13 items:
2284374.346: 0: 0000000000000000 - 000000000009fc00 = 1 RAM
2284474.346: 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2284574.346: 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
2284674.346: 3: 0000000000100000 - 00000000b7c88000 = 1 RAM
2284774.346: 4: 00000000b7c88000 - 00000000b8000000 = 2 RESERVED
2284874.346: 5: 00000000b8000000 - 00000000bfffc000 = 1 RAM
2284974.346: 6: 00000000bfffc000 - 00000000d0000000 = 2 RESERVED
2285074.346: 7: 00000000fcb00000 - 00000000fcb04000 = 2 RESERVED
2285174.346: 8: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
2285274.346: 9: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
2285374.346: 10: 00000000fed00000 - 00000000fed01000 = 2 RESERVED
2285474.346: 11: 0000000100000000 - 0000004038000000 = 1 RAM
2285574.346: 12: 0000004038000000 - 0000004040000000 = 2 RESERVED
2285674.347: Jump to int19
2285774.347: enter handle_19:
2285874.347: NULL
2285974.347: Booting from CBFS...
2286074.348: Run img/memtest
2286174.348: Segment 41544144 180212@0xff0a40e0 -> 180212@0x00010000
2286274.525: Calling addr 0x00010000
2286374.527: <1b>[LINE_SCROLL;24r<1b>[H<1b>[2J<1b>[37m<1b>[44m<1b>[0m<1b>[37m<1b>[44m<1b>[1;1HMemtest86+ 5.01 coreboot 001<1b>[0m<1b>[6;61H| Time: 0:00:00<1b>[2;31HPass %<1b>[3;31HTest %<1b>[4;31HTest #<1b>[5;31HTesting: <1b>[6;31HPattern: <1b>[2;1HCLK: (32b Mode)<1b>[3;1HL1 Cache: Unknown <1b>[4;1HL2 Cache: Unknown <1b>[5;1HL3 Cache: None <1b>[6;1HMemory : <1b>[7;1H------------------------------------------------------------------------------<1b>[8;1HCore#:<1b>[9;1HState:<1b>[10;1HCores: Active / Total (Run: All) | Pass: 0 Errors: 0 <1b>[11;1H------------------------------------------------------------------------------<1b>[8;40H| Chipset : Unknown<1b>[9;40H| Memory Type : Unknown<1b>[1;29H| <1b>[2;29H| <1b>[3;29H| <1b>[4;29H| <1b>[5;29H| <1b>[6;29H| <1b>[25;1H(ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock<1b>[6;12H256<1b>[6;15HG<1b>[1;31HAMD Opteron(tm) Processor 6278<1b>[2;11HMHz<1b>[2;6H2400<1b>[3;11H K <1b>[3;13H64<1b>[3;24HMB/s<1b>[3;18H22430<1b>[4;11H K <1b>[4;11H2048<1b>[4;24HMB/s<1b>[4;18H18045<1b>[5;12H K <1b>[5;13H12<1b>[5;15HM<1b>[5;24HMB/s<1b>[5;19H8000<1b>[19;19H==> Press F1 to enter Fail-Safe Mode <==<1b>[20;16H==> Press F2 to force Multi-Threading (SMP) <==<1b>[19;19H <1b>[20;16H <1b>[8;8H0<1b>[9;8HS<1b>[10;21H1<1b>[8;10H(SMP: Disabled)<1b>[9;10HRunning...<1b>[8;42HRAM: <1b>[8;47H800 <1b>[8;51HMHz (<1b>[8;56HDDR3-<1b>[8;61H1600<1b>[8;65H)<1b>[8;67H- BCLK: <1b>[8;76H88<1b>[9;42HTimings: CAS <1b>[9;55H11<1b>[9;57H-<1b>[9;58H11<1b>[9;60H-<1b>[9;61H11<1b>[9;63H-<1b>[9;64H28<1b>[9;67H@ 128-bit Mode<1b>[24;34HASUS<1b>[24;39HKGPE-D16<1b>[13;1HMemory SPD Informations<1b>[14;1H--------------------------<1b>[9;32H21<1b>[8;27H| CPU Temp<1b>[9;27H| C<1b>[2;17HPAE Mode)<1b>[2;17HX64 Mode)<1b>[6;24HMB/s<1b>[4;37H2 <1b>[4;40H[Address test, own address Parallel] <1b>[9;8HW<1b>[10;9H1<1b>[9;8H-<1b>[6;57HR<1b>[5;43H0<1b>[5;44HK<1b>[5;46H- <1b>[5;50H32<1b>[5;52HM<1b>[5;58H32<1b>[5;60HM<1b>[5;62Hof <1b>[5;66H256<1b>[5;69HG<1b>[6;42Haddress <1b>[3;37H0<1b>[2;37H0<1b>[6;77H1<1b>[9;32H23<1b>[9;8HW<1b>[9;8H-<1b>[6;57H <1b>[5;40H1024<1b>[5;48H2048<1b>[5;56H2047<1b>[6;77H2<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;40H2048<1b>[5;44HM<1b>[5;48H3072<1b>[5;56H1024<1b>[3;37H1<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;40H4096<1b>[5;48H6144<1b>[5;56H2048<1b>[6;77H4<1b>[3;37H2<1b>[9;8HW<1b>[9;8H-<1b>[5;40H6144<1b>[5;48H8192<1b>[6;77H5<1b>[9;33H6<1b>[6;77H6<1b>[9;33H5<1b>[3;37H3<1b>[3;40H#<1b>[9;8HW<1b>[9;8H-<1b>[5;40H8192<1b>[5;48H 10<1b>[5;52HG<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;40H 10<1b>[5;44HG<1b>[5;51H2<1b>[3;37H4<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H5<1b>[6;77H9<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H0<1b>[6;76H1<1b>[3;37H6<1b>[3;41H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H1<1b>[6;77H2<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H20<1b>[3;37H7<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;42H20<1b>[5;51H2<1b>[6;77H4<1b>[3;37H8<1b>[3;42H#<1b>[6;77H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H6<1b>[3;37H9<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H7<1b>[3;36H10<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[9;33H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H30<1b>[3;37H1<1b>[3;43H#<1b>[6;77H9<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H30<1b>[5;51H2<1b>[6;77H0<1b>[6;76H2<1b>[3;37H2<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H2<1b>[3;37H3<1b>[3;44H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H3<1b>[6;77H4<1b>[9;33H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H4<1b>[6;77H5<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H40<1b>[3;37H5<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;42H40<1b>[5;51H2<1b>[3;37H6<1b>[3;45H#<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H8<1b>[9;33H6<1b>[3;37H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H9<1b>[6;77H0<1b>[6;76H3<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H8<1b>[3;46H#<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H50<1b>[6;77H2<1b>[3;37H9<1b>[9;8HW<1b>[9;8H-<1b>[5;42H50<1b>[5;51H2<1b>[6;77H3<1b>[3;36H20<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H5<1b>[3;37H1<1b>[3;47H#<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H2<1b>[6;77H7<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H60<1b>[6;77H8<1b>[3;37H3<1b>[6;77H9<1b>[9;33H6<1b>[9;8HW<1b>[9;8H-<1b>[5;42H60<1b>[5;51H2<1b>[6;77H0<1b>[6;76H4<1b>[9;33H5<1b>[3;37H4<1b>[3;48H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H2<1b>[3;37H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H3<1b>[3;37H6<1b>[3;49H#<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H70<1b>[6;77H5<1b>[6;77H6<1b>[3;37H7<1b>[9;8HW<1b>[9;8H-<1b>[5;42H70<1b>[5;51H2<1b>[6;77H7<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H8<1b>[6;77H9<1b>[6;77H0<1b>[6;76H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H1<1b>[3;37H9<1b>[3;50H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H2<1b>[6;77H3<1b>[3;36H30<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H80<1b>[6;77H4<1b>[6;77H5<1b>[9;33H4<1b>[3;37H1<1b>[3;51H#<1b>[9;8HW<1b>[9;8H-<1b>[5;42H80<1b>[5;51H2<1b>[6;77H6<1b>[9;33H5<1b>[6;77H7<1b>[9;33H4<1b>[6;77H8<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H2<1b>[6;77H9<1b>[9;33H4<1b>[6;77H0<1b>[6;76H0<1b>[6;74H1<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H3<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H2<1b>[9;33H4<1b>[3;37H4<1b>[3;52H#<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H90<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H90<1b>[5;51H2<1b>[3;37H5<1b>[6;77H6<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H6<1b>[3;53H#<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H9<1b>[3;37H7<1b>[6;77H0<1b>[6;76H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H1<1b>[6;77H2<1b>[3;37H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;49H100<1b>[6;77H3<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;41H100<1b>[5;51H2<1b>[3;37H9<1b>[3;54H#<1b>[6;77H5<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;36H40<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H8<1b>[6;77H9<1b>[3;37H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H0<1b>[6;76H2<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H10<1b>[3;37H2<1b>[3;55H#<1b>[6;77H2<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;42H10<1b>[5;51H2<1b>[6;77H4<1b>[3;37H3<1b>[6;77H5<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H4<1b>[3;56H#<1b>[6;77H6<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H7<1b>[6;77H8<1b>[3;37H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H9<1b>[6;77H0<1b>[6;76H3<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H20<1b>[6;77H1<1b>[9;33H5<1b>[3;37H6<1b>[6;77H2<1b>[9;33H4<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H20<1b>[5;51H2<1b>[3;37H7<1b>[3;57H#<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H5<1b>[9;33H4<1b>[3;37H8<1b>[6;77H6<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H7<1b>[9;33H4<1b>[6;77H8<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H9<1b>[3;58H#<1b>[6;77H9<1b>[9;33H4<1b>[6;77H0<1b>[6;76H4<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H30<1b>[3;36H50<1b>[6;77H1<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;42H30<1b>[5;51H2<1b>[6;77H2<1b>[3;37H1<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[3;37H2<1b>[3;59H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H6<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[9;33H5<1b>[3;37H3<1b>[6;77H9<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H40<1b>[6;77H0<1b>[6;76H5<1b>[9;33H5<1b>[3;37H4<1b>[3;60H#<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;42H40<1b>[5;51H2<1b>[6;77H2<1b>[9;33H4<1b>[3;37H5<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[6;77H5<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H6<1b>[6;77H6<1b>[9;33H4<1b>[6;77H7<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[3;37H7<1b>[3;61H#<1b>[6;77H9<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H50<1b>[3;37H8<1b>[6;77H0<1b>[6;76H0<1b>[6;74H2<1b>[6;77H1<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H50<1b>[5;51H2<1b>[6;77H2<1b>[9;33H4<1b>[3;37H9<1b>[3;62H#<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;36H60<1b>[6;77H6<1b>[6;77H7<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[3;37H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H60<1b>[6;77H9<1b>[6;77H0<1b>[6;76H1<1b>[9;33H4<1b>[3;37H2<1b>[3;63H#<1b>[9;8HW<1b>[9;8H-<1b>[5;42H60<1b>[5;51H2<1b>[6;77H1<1b>[9;33H5<1b>[6;77H2<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H3<1b>[6;77H3<1b>[9;33H5<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H4<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H7<1b>[3;37H5<1b>[3;64H#<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H70<1b>[6;77H9<1b>[9;33H5<1b>[6;77H0<1b>[6;76H2<1b>[9;33H4<1b>[3;37H6<1b>[9;8HW<1b>[9;8H-<1b>[5;42H70<1b>[5;51H2<1b>[6;77H1<1b>[9;33H5<1b>[6;77H2<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H3<1b>[9;33H5<1b>[3;37H7<1b>[3;65H#<1b>[6;77H4<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H8<1b>[6;77H5<1b>[6;77H6<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H7<1b>[9;33H4<1b>[3;37H9<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H80<1b>[6;77H9<1b>[6;77H0<1b>[6;76H3<1b>[3;36H70<1b>[3;66H#<1b>[9;8HW<1b>[9;8H-<1b>[5;42H80<1b>[5;51H2<1b>[6;77H1<1b>[6;77H2<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[5;54HHalting...<00>
22864237.422: <00>
22865237.610:
22866237.610:
22867237.610: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
22868237.610: Initial stack pointer: 000dffb8
22869237.612: CPU APICID 00 start flag set
22870237.613: BSP Family_Model: 00600f12
22871237.613: *sysinfo range: [000c2d20,000cd28c]
22872237.613: bsp_apicid = 00
22873237.613: cpu_init_detectedx = 00000000
22874237.613: sb700 reset flags: 0020
22875237.613: WARNING: MC4 Machine Check Exception detected on node 0!
22876237.613: Signature: f256d7df2e1df6cb
22877237.614: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22878237.614: CBFS: Locating 'microcode_amd.bin'
22879237.615: CBFS: Found @ offset d0000 size 318c
22880237.615: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22881237.615: CBFS: Locating 'microcode_amd_fam15h.bin'
22882237.615: CBFS: Found @ offset d3200 size 1ec4
22883237.637: [microcode] patch id to apply = 0x0600063d
22884237.637: [microcode] updated to patch id = 0x0600063d success
22885237.637: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22886237.639: CBFS: Locating 'cmos_layout.bin'
22887237.640: CBFS: Found @ offset 2b0c0 size e88
22888237.641: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22889237.641: CBFS: Locating 'cmos_layout.bin'
22890237.641: CBFS: Found @ offset 2b0c0 size e88
22891237.641: done
22892237.641: Enter amd_ht_init
22893237.645: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
22894237.645: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
22895237.645: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
22896237.648: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22897237.648: CBFS: Locating 'cmos_layout.bin'
22898237.649: CBFS: Found @ offset 2b0c0 size e88
22899237.649: Forcing HT links to isochronous mode due to enabled IOMMU
22900237.649: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22901237.649: CBFS: Locating 'cmos_layout.bin'
22902237.649: CBFS: Found @ offset 2b0c0 size e88
22903237.651: Exit amd_ht_init
22904237.651: amd_ht_fixup
22905237.651: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
22906237.651: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
22907237.651: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
22908237.651: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
22909237.652: cpuSetAMDPCI 00 done
22910237.654: cpuSetAMDPCI 01 done
22911237.655: cpuSetAMDPCI 02 done
22912237.655: cpuSetAMDPCI 03 done
22913237.655: Prep FID/VID Node:00
22914237.656: F3x80: e20be281
22915237.656: F3x84: 01e200e2
22916237.656: F3xD4: c3312f18
22917237.656: F3xD8: 03000016
22918237.656: F3xDC: 05475632
22919237.656: Prep FID/VID Node:01
22920237.656: F3x80: e20be281
22921237.656: F3x84: 01e200e2
22922237.656: F3xD4: c3312f18
22923237.656: F3xD8: 03000016
22924237.656: F3xDC: 05475632
22925237.656: Prep FID/VID Node:02
22926237.656: F3x80: e20be281
22927237.656: F3x84: 01e200e2
22928237.656: F3xD4: c3312f18
22929237.656: F3xD8: 03000016
22930237.656: F3xDC: 05475632
22931237.656: Prep FID/VID Node:03
22932237.656: F3x80: e20be281
22933237.656: F3x84: 01e200e2
22934237.656: F3xD4: c3312f18
22935237.657: F3xD8: 03000016
22936237.657: F3xDC: 05475632
22937237.657: setup_remote_node: 01 done
22938237.657: Start node 01 done.
22939237.657: setup_remote_node: 02 done
22940237.657: Start node 02 done.
22941237.658: setup_remote_node: 03 done
22942237.659: Start node 03 done.
22943237.661: WARNING: MC4 Machine Check Exception detected on node 1!
22944237.666: Signature: f627f6fe561fd7bb
22945237.668: WARNING: MC4 Machine Check Exception detected on node 2!
22946237.671: Signature: fa100aa3ca054c0f
22947237.672: WARNING: MC4 Machine Check Exception detected on node 3!
22948237.674: Signature: f20736f100014e0f
22949237.674: core0 started: 01 02 03
22950237.674: sr5650_early_setup()
22951237.674: get_cpu_rev EAX=0x600f12.
22952237.675: CPU Rev is Fam 15.
22953237.675: NB Revision is A12.
22954237.675: fam10_optimization()
22955237.675: sr5650_por_init
22956237.678: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22957237.678: CBFS: Locating 'cmos_layout.bin'
22958237.679: CBFS: Found @ offset 2b0c0 size e88
22959237.679: Enabling IOMMU
22960237.682: sb700_early_setup()
22961237.682: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22962237.682: CBFS: Locating 'cmos_layout.bin'
22963237.685: CBFS: Found @ offset 2b0c0 size e88
22964237.687: sb700_devices_por_init()
22965237.688: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
22966237.689: SMBus controller enabled, sb revision is A15
22967237.689: sb700_devices_por_init: Disabling ISA DMA support
22968237.689: sb700_devices_por_init(): IDE Device, BDF:0-20-1
22969237.692: sb700_devices_por_init(): LPC Device, BDF:0-20-3
22970237.693: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
22971237.694: sb700_devices_por_init(): SATA Device, BDF:0-17-0
22972237.694: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
22973237.694: CBFS: Locating 'cmos_layout.bin'
22974237.694: CBFS: Found @ offset 2b0c0 size e88
22975237.695: sb700_pmio_por_init()
22976237.695: start_other_cores()
22977237.695: init node: 00 cores: 07 pass 1
22978237.695: Start other core - nodeid: 00 cores: 07
22979237.696: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
22980237.754: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
22981237.778: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
22982237.802: init node: 01 cores: 07 pass 1
22983237.804: Start other core - nodeid: 01 cores: 07
22984237.809: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
22985237.939: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
22986237.964: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
22987237.965: init node: 02 cores: 07 pass 1
22988237.966: Start other core - nodeid: 02 cores: 07
22989237.968: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
22990238.253: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
22991238.255: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
22992238.276: init node: 03 cores: 07 pass 1
22993238.278: Start other core - nodeid: 03 cores: 07
22994238.279: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
22995238.475: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
22996238.501: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
22997238.525: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
22998238.528: * AP 01started
22999238.528: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23000238.532: * AP 02started
23001238.535: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
23002238.536: * AP 03started
23003238.536: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23004238.536: * AP 04started
23005238.536: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
23006238.536: * AP 05started
23007238.537: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23008238.537: * AP 06started
23009238.538: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
23010238.541: * AP 07started
23011238.541: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
23012238.542: * AP 09started
23013238.542: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23014238.542: * AP 0astarted
23015238.542: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
23016238.543: * AP 0bstarted
23017238.543: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23018238.546: * AP 0cstarted
23019238.547: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
23020238.547: * AP 0dstarted
23021238.547: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23022238.548: * AP 0estarted
23023238.548: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
23024238.548: * AP 0fstarted
23025238.548: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
23026238.551: * AP 21started
23027238.551: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23028238.552: * AP 22started
23029238.553: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
23030238.553: * AP 23started
23031238.553: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23032238.553: * AP 24started
23033238.553: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
23034238.555: * AP 25started
23035238.555: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23036238.556: * AP 26started
23037238.556: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
23038238.556: * AP 27started
23039238.556: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
23040238.557: * AP 29started
23041238.557: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23042238.557: * AP 2astarted
23043238.557: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
23044238.557: * AP 2bstarted
23045238.557: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23046238.558: * AP 2cstarted
23047238.558: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
23048238.558: * AP 2dstarted
23049238.558: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23050238.558: * AP 2estarted
23051238.558: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
23052238.558: * AP 2fstarted
23053238.559:
23054238.559:
23055238.559: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c06644c
23056238.559: FIDVID on BSP, APIC_id: 00
23057238.560: BSP fid = 0
23058238.560: get_boot_apic_id: using 0 as APIC ID for node 0, core 0
23059238.560: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
23060238.560: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23061238.560: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
23062238.560: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23063238.561: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
23064238.561: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23065238.561: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
23066238.561: get_boot_apic_id: using 8 as APIC ID for node 1, core 0
23067238.562: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
23068238.562: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23069238.562: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
23070238.562: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23071238.563: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
23072238.563: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23073238.563: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
23074238.563: get_boot_apic_id: using 32 as APIC ID for node 2, core 0
23075238.563: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
23076238.563: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23077238.564: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
23078238.564: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23079238.564: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
23080238.564: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23081238.565: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
23082238.565: get_boot_apic_id: using 40 as APIC ID for node 3, core 0
23083238.565: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
23084238.565: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23085238.565: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
23086238.566: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23087238.566: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
23088238.566: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23089238.566: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
23090238.566: Wait for AP stage 1: ap_apicid = 1
23091238.567: <09>readback = 1000014
23092238.567: <09>common_fid(packed) = 0
23093238.567: Wait for AP stage 1: ap_apicid = 2
23094238.567: <09>readback = 2000014
23095238.567: <09>common_fid(packed) = 0
23096238.567: Wait for AP stage 1: ap_apicid = 3
23097238.567: <09>readback = 3000014
23098238.567: <09>common_fid(packed) = 0
23099238.568: Wait for AP stage 1: ap_apicid = 4
23100238.568: <09>readback = 4000014
23101238.568: <09>common_fid(packed) = 0
23102238.568: Wait for AP stage 1: ap_apicid = 5
23103238.568: <09>readback = 5000014
23104238.568: <09>common_fid(packed) = 0
23105238.568: Wait for AP stage 1: ap_apicid = 6
23106238.568: <09>readback = 6000014
23107238.568: <09>common_fid(packed) = 0
23108238.569: Wait for AP stage 1: ap_apicid = 7
23109238.569: <09>readback = 7000014
23110238.569: <09>common_fid(packed) = 0
23111238.569: Wait for AP stage 1: ap_apicid = 8
23112238.569: <09>readback = 8000014
23113238.569: <09>common_fid(packed) = 0
23114238.569: Wait for AP stage 1: ap_apicid = 9
23115238.569: <09>readback = 9000014
23116238.569: <09>common_fid(packed) = 0
23117238.570: Wait for AP stage 1: ap_apicid = a
23118238.570: <09>readback = a000014
23119238.570: <09>common_fid(packed) = 0
23120238.570: Wait for AP stage 1: ap_apicid = b
23121238.570: <09>readback = b000014
23122238.570: <09>common_fid(packed) = 0
23123238.570: Wait for AP stage 1: ap_apicid = c
23124238.570: <09>readback = c000014
23125238.571: <09>common_fid(packed) = 0
23126238.571: Wait for AP stage 1: ap_apicid = d
23127238.571: <09>readback = d000014
23128238.571: <09>common_fid(packed) = 0
23129238.571: Wait for AP stage 1: ap_apicid = e
23130238.571: <09>readback = e000014
23131238.571: <09>common_fid(packed) = 0
23132238.571: Wait for AP stage 1: ap_apicid = f
23133238.572: <09>readback = f000014
23134238.572: <09>common_fid(packed) = 0
23135238.572: Wait for AP stage 1: ap_apicid = 20
23136238.572: <09>readback = 20000014
23137238.572: <09>common_fid(packed) = 0
23138238.572: Wait for AP stage 1: ap_apicid = 21
23139238.572: <09>readback = 21000014
23140238.572: <09>common_fid(packed) = 0
23141238.573: Wait for AP stage 1: ap_apicid = 22
23142238.573: <09>readback = 22000014
23143238.573: <09>common_fid(packed) = 0
23144238.573: Wait for AP stage 1: ap_apicid = 23
23145238.573: <09>readback = 23000014
23146238.573: <09>common_fid(packed) = 0
23147238.573: Wait for AP stage 1: ap_apicid = 24
23148238.573: <09>readback = 24000014
23149238.573: <09>common_fid(packed) = 0
23150238.573: Wait for AP stage 1: ap_apicid = 25
23151238.574: <09>readback = 25000014
23152238.574: <09>common_fid(packed) = 0
23153238.574: Wait for AP stage 1: ap_apicid = 26
23154238.574: <09>readback = 26000014
23155238.574: <09>common_fid(packed) = 0
23156238.574: Wait for AP stage 1: ap_apicid = 27
23157238.574: <09>readback = 27000014
23158238.574: <09>common_fid(packed) = 0
23159238.574: Wait for AP stage 1: ap_apicid = 28
23160238.575: <09>readback = 28000014
23161238.575: <09>common_fid(packed) = 0
23162238.575: Wait for AP stage 1: ap_apicid = 29
23163238.575: <09>readback = 29000014
23164238.575: <09>common_fid(packed) = 0
23165238.575: Wait for AP stage 1: ap_apicid = 2a
23166238.575: <09>readback = 2a000014
23167238.575: <09>common_fid(packed) = 0
23168238.575: Wait for AP stage 1: ap_apicid = 2b
23169238.575: <09>readback = 2b000014
23170238.576: <09>common_fid(packed) = 0
23171238.576: Wait for AP stage 1: ap_apicid = 2c
23172238.576: <09>readback = 2c000014
23173238.576: <09>common_fid(packed) = 0
23174238.576: Wait for AP stage 1: ap_apicid = 2d
23175238.576: <09>readback = 2d000014
23176238.576: <09>common_fid(packed) = 0
23177238.577: Wait for AP stage 1: ap_apicid = 2e
23178238.577: <09>readback = 2e000014
23179238.577: <09>common_fid(packed) = 0
23180238.577: Wait for AP stage 1: ap_apicid = 2f
23181238.577: <09>readback = 2f000014
23182238.577: <09>common_fid(packed) = 0
23183238.577: common_fid = 0
23184238.577: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c06644c
23185238.578: sr5650_htinit: Node 0 Link 1, HT freq=e.
23186238.578: sr5650_htinit: HT3 mode
23187238.578: ...WARM RESET...
23188238.578:
23189238.578:
23190238.578: <00>
23191238.690:
23192238.690:
23193238.690: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
23194238.690: Initial stack pointer: 000dffb8
23195238.691: CPU APICID 00 start flag set
23196238.692: BSP Family_Model: 00600f12
23197238.692: *sysinfo range: [000c2d20,000cd28c]
23198238.692: bsp_apicid = 00
23199238.692: cpu_init_detectedx = 00000000
23200238.692: sb700 reset flags: 0004
23201238.693: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23202238.693: CBFS: Locating 'microcode_amd.bin'
23203238.694: CBFS: Found @ offset d0000 size 318c
23204238.694: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23205238.694: CBFS: Locating 'microcode_amd_fam15h.bin'
23206238.694: CBFS: Found @ offset d3200 size 1ec4
23207238.716: [microcode] patch id to apply = 0x0600063d
23208238.717: [microcode] updated to patch id = 0x0600063d success
23209238.717: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23210238.719: CBFS: Locating 'cmos_layout.bin'
23211238.719: CBFS: Found @ offset 2b0c0 size e88
23212238.720: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23213238.720: CBFS: Locating 'cmos_layout.bin'
23214238.720: CBFS: Found @ offset 2b0c0 size e88
23215238.720: done
23216238.721: Enter amd_ht_init
23217238.724: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
23218238.724: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
23219238.724: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
23220238.727: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23221238.727: CBFS: Locating 'cmos_layout.bin'
23222238.727: CBFS: Found @ offset 2b0c0 size e88
23223238.727: Forcing HT links to isochronous mode due to enabled IOMMU
23224238.727: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23225238.727: CBFS: Locating 'cmos_layout.bin'
23226238.727: CBFS: Found @ offset 2b0c0 size e88
23227238.729: Exit amd_ht_init
23228238.729: amd_ht_fixup
23229238.729: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
23230238.729: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
23231238.729: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
23232238.729: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
23233238.729: cpuSetAMDPCI 00 done
23234238.732: cpuSetAMDPCI 01 done
23235238.732: cpuSetAMDPCI 02 done
23236238.732: cpuSetAMDPCI 03 done
23237238.732: Prep FID/VID Node:00
23238238.733: F3x80: e20be281
23239238.733: F3x84: 01e200e2
23240238.733: F3xD4: c3312f18
23241238.733: F3xD8: 03000016
23242238.733: F3xDC: 05475632
23243238.733: Prep FID/VID Node:01
23244238.733: F3x80: e20be281
23245238.733: F3x84: 01e200e2
23246238.733: F3xD4: c3312f18
23247238.733: F3xD8: 03000016
23248238.733: F3xDC: 05475632
23249238.733: Prep FID/VID Node:02
23250238.733: F3x80: e20be281
23251238.733: F3x84: 01e200e2
23252238.733: F3xD4: c3312f18
23253238.733: F3xD8: 03000016
23254238.733: F3xDC: 05475632
23255238.733: Prep FID/VID Node:03
23256238.733: F3x80: e20be281
23257238.733: F3x84: 01e200e2
23258238.733: F3xD4: c3312f18
23259238.733: F3xD8: 03000016
23260238.733: F3xDC: 05475632
23261238.733: setup_remote_node: 01 done
23262238.733: Start node 01 done.
23263238.733: setup_remote_node: 02 done
23264238.734: Start node 02 done.
23265238.734: setup_remote_node: 03 done
23266238.735: Start node 03 done.
23267238.739: core0 started: 01 02 03
23268238.741: sr5650_early_setup()
23269238.742: get_cpu_rev EAX=0x600f12.
23270238.743: CPU Rev is Fam 15.
23271238.745: NB Revision is A12.
23272238.746: fam10_optimization()
23273238.747: sr5650_por_init
23274238.748: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23275238.750: CBFS: Locating 'cmos_layout.bin'
23276238.750: CBFS: Found @ offset 2b0c0 size e88
23277238.750: Enabling IOMMU
23278238.751: sb700_early_setup()
23279238.751: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23280238.753: CBFS: Locating 'cmos_layout.bin'
23281238.754: CBFS: Found @ offset 2b0c0 size e88
23282238.754: sb700_devices_por_init()
23283238.756: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
23284238.756: SMBus controller enabled, sb revision is A15
23285238.756: sb700_devices_por_init: Disabling ISA DMA support
23286238.758: sb700_devices_por_init(): IDE Device, BDF:0-20-1
23287238.761: sb700_devices_por_init(): LPC Device, BDF:0-20-3
23288238.762: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
23289238.762: sb700_devices_por_init(): SATA Device, BDF:0-17-0
23290238.763: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23291238.763: CBFS: Locating 'cmos_layout.bin'
23292238.764: CBFS: Found @ offset 2b0c0 size e88
23293238.764: sb700_pmio_por_init()
23294238.766: start_other_cores()
23295238.766: init node: 00 cores: 07 pass 1
23296238.766: Start other core - nodeid: 00 cores: 07
23297238.766: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23298238.817: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23299238.842: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23300238.865: init node: 01 cores: 07 pass 1
23301238.868: Start other core - nodeid: 01 cores: 07
23302238.873: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23303239.085: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23304239.085: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23305239.086: init node: 02 cores: 07 pass 1
23306239.087: Start other core - nodeid: 02 cores: 07
23307239.089: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23308239.297: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23309239.297: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23310239.297: init node: 03 cores: 07 pass 1
23311239.299: Start other core - nodeid: 03 cores: 07
23312239.300: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23313239.506: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23314239.506: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23315239.506: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
23316239.511: * AP 01started
23317239.512: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23318239.514: * AP 02started
23319239.518: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
23320239.519: * AP 03started
23321239.519: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23322239.519: * AP 04started
23323239.519: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
23324239.522: * AP 05started
23325239.522: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23326239.524: * AP 06started
23327239.524: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
23328239.524: * AP 07started
23329239.524: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
23330239.526: * AP 09started
23331239.526: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23332239.528: * AP 0astarted
23333239.528: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
23334239.528: * AP 0bstarted
23335239.528: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23336239.530: * AP 0cstarted
23337239.531: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
23338239.532: * AP 0dstarted
23339239.532: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23340239.532: * AP 0estarted
23341239.532: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
23342239.534: * AP 0fstarted
23343239.534: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
23344239.534: * AP 21started
23345239.534: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23346239.534: * AP 22started
23347239.535: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
23348239.535: * AP 23started
23349239.535: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23350239.535: * AP 24started
23351239.535: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
23352239.535: * AP 25started
23353239.535: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23354239.535: * AP 26started
23355239.535: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
23356239.535: * AP 27started
23357239.535: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
23358239.535: * AP 29started
23359239.535: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23360239.535: * AP 2astarted
23361239.535: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
23362239.535: * AP 2bstarted
23363239.535: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23364239.535: * AP 2cstarted
23365239.535: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
23366239.535: * AP 2dstarted
23367239.535: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23368239.535: * AP 2estarted
23369239.535: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
23370239.535: * AP 2fstarted
23371239.535:
23372239.535:
23373239.535: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
23374239.536: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
23375239.536: sr5650_htinit: Node 0 Link 1, HT freq=e.
23376239.536: sr5650_htinit: HT3 mode
23377239.536: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23378239.536: CBFS: Locating 'cmos_layout.bin'
23379239.536: CBFS: Found @ offset 2b0c0 size e88
23380239.537: ...WARM RESET...
23381239.537:
23382239.537:
23383239.537: <00>
23384239.641:
23385239.641:
23386239.641: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
23387239.641: Initial stack pointer: 000dffb8
23388239.642: CPU APICID 00 start flag set
23389239.643: BSP Family_Model: 00600f12
23390239.643: *sysinfo range: [000c2d20,000cd28c]
23391239.643: bsp_apicid = 00
23392239.643: cpu_init_detectedx = 00000000
23393239.643: sb700 reset flags: 0004
23394239.644: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23395239.644: CBFS: Locating 'microcode_amd.bin'
23396239.644: CBFS: Found @ offset d0000 size 318c
23397239.645: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23398239.645: CBFS: Locating 'microcode_amd_fam15h.bin'
23399239.645: CBFS: Found @ offset d3200 size 1ec4
23400239.659: [microcode] patch id to apply = 0x0600063d
23401239.659: [microcode] updated to patch id = 0x0600063d success
23402239.659: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23403239.661: CBFS: Locating 'cmos_layout.bin'
23404239.661: CBFS: Found @ offset 2b0c0 size e88
23405239.662: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23406239.662: CBFS: Locating 'cmos_layout.bin'
23407239.662: CBFS: Found @ offset 2b0c0 size e88
23408239.663: done
23409239.663: Enter amd_ht_init
23410239.666: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
23411239.666: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
23412239.666: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
23413239.669: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23414239.669: CBFS: Locating 'cmos_layout.bin'
23415239.669: CBFS: Found @ offset 2b0c0 size e88
23416239.669: Forcing HT links to isochronous mode due to enabled IOMMU
23417239.669: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23418239.669: CBFS: Locating 'cmos_layout.bin'
23419239.670: CBFS: Found @ offset 2b0c0 size e88
23420239.670: Exit amd_ht_init
23421239.671: amd_ht_fixup
23422239.671: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
23423239.671: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
23424239.671: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
23425239.671: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
23426239.671: cpuSetAMDPCI 00 done
23427239.674: cpuSetAMDPCI 01 done
23428239.674: cpuSetAMDPCI 02 done
23429239.674: cpuSetAMDPCI 03 done
23430239.674: Prep FID/VID Node:00
23431239.675: F3x80: e20be281
23432239.675: F3x84: 01e200e2
23433239.675: F3xD4: c3312f18
23434239.675: F3xD8: 03000016
23435239.675: F3xDC: 05475632
23436239.675: Prep FID/VID Node:01
23437239.675: F3x80: e20be281
23438239.675: F3x84: 01e200e2
23439239.675: F3xD4: c3312f18
23440239.675: F3xD8: 03000016
23441239.675: F3xDC: 05475632
23442239.675: Prep FID/VID Node:02
23443239.675: F3x80: e20be281
23444239.675: F3x84: 01e200e2
23445239.675: F3xD4: c3312f18
23446239.675: F3xD8: 03000016
23447239.675: F3xDC: 05475632
23448239.675: Prep FID/VID Node:03
23449239.675: F3x80: e20be281
23450239.675: F3x84: 01e200e2
23451239.675: F3xD4: c3312f18
23452239.675: F3xD8: 03000016
23453239.675: F3xDC: 05475632
23454239.675: setup_remote_node: 01 done
23455239.675: Start node 01 done.
23456239.675: setup_remote_node: 02 done
23457239.676: Start node 02 done.
23458239.676: setup_remote_node: 03 done
23459239.677: Start node 03 done.
23460239.680: core0 started: 01 02 03
23461239.683: sr5650_early_setup()
23462239.684: get_cpu_rev EAX=0x600f12.
23463239.685: CPU Rev is Fam 15.
23464239.686: NB Revision is A12.
23465239.687: fam10_optimization()
23466239.689: sr5650_por_init
23467239.690: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23468239.692: CBFS: Locating 'cmos_layout.bin'
23469239.692: CBFS: Found @ offset 2b0c0 size e88
23470239.692: Enabling IOMMU
23471239.698: sb700_early_setup()
23472239.699: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23473239.700: CBFS: Locating 'cmos_layout.bin'
23474239.700: CBFS: Found @ offset 2b0c0 size e88
23475239.700: sb700_devices_por_init()
23476239.700: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
23477239.706: SMBus controller enabled, sb revision is A15
23478239.707: sb700_devices_por_init: Disabling ISA DMA support
23479239.707: sb700_devices_por_init(): IDE Device, BDF:0-20-1
23480239.709: sb700_devices_por_init(): LPC Device, BDF:0-20-3
23481239.710: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
23482239.710: sb700_devices_por_init(): SATA Device, BDF:0-17-0
23483239.710: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23484239.710: CBFS: Locating 'cmos_layout.bin'
23485239.710: CBFS: Found @ offset 2b0c0 size e88
23486239.711: sb700_pmio_por_init()
23487239.711: start_other_cores()
23488239.711: init node: 00 cores: 07 pass 1
23489239.711: Start other core - nodeid: 00 cores: 07
23490239.711: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23491239.778: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23492239.779: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23493239.788: init node: 01 cores: 07 pass 1
23494239.791: Start other core - nodeid: 01 cores: 07
23495239.795: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23496239.920: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23497239.958: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23498239.959: init node: 02 cores: 07 pass 1
23499239.960: Start other core - nodeid: 02 cores: 07
23500239.962: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23501240.109: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23502240.125: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23503240.139: init node: 03 cores: 07 pass 1
23504240.140: Start other core - nodeid: 03 cores: 07
23505240.142: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23506240.284: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23507240.302: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23508240.316: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
23509240.319: * AP 01started
23510240.320: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23511240.325: * AP 02started
23512240.325: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
23513240.326: * AP 03started
23514240.326: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23515240.326: * AP 04started
23516240.326: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
23517240.329: * AP 05started
23518240.330: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23519240.330: * AP 06started
23520240.330: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
23521240.330: * AP 07started
23522240.330: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
23523240.334: * AP 09started
23524240.334: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23525240.334: * AP 0astarted
23526240.335: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
23527240.334: * AP 0bstarted
23528240.336: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23529240.338: * AP 0cstarted
23530240.339: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
23531240.339: * AP 0dstarted
23532240.339: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23533240.339: * AP 0estarted
23534240.341: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
23535240.341: * AP 0fstarted
23536240.341: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
23537240.341: * AP 21started
23538240.341: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23539240.341: * AP 22started
23540240.341: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
23541240.342: * AP 23started
23542240.342: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23543240.342: * AP 24started
23544240.342: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
23545240.342: * AP 25started
23546240.342: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23547240.342: * AP 26started
23548240.342: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
23549240.342: * AP 27started
23550240.342: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
23551240.342: * AP 29started
23552240.342: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23553240.342: * AP 2astarted
23554240.342: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
23555240.342: * AP 2bstarted
23556240.342: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23557240.342: * AP 2cstarted
23558240.342: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
23559240.342: * AP 2dstarted
23560240.342: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23561240.342: * AP 2estarted
23562240.342: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
23563240.342: * AP 2fstarted
23564240.342:
23565240.342:
23566240.342: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
23567240.342: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
23568240.343: sr5650_htinit: Node 0 Link 1, HT freq=e.
23569240.343: sr5650_htinit: HT3 mode
23570240.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23571240.343: CBFS: Locating 'cmos_layout.bin'
23572240.343: CBFS: Found @ offset 2b0c0 size e88
23573240.344: Node 00 DIMM voltage set to index 00
23574240.344: Node 01 DIMM voltage set to index 00
23575240.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23576240.344: CBFS: Locating 'cmos_layout.bin'
23577240.344: CBFS: Found @ offset 2b0c0 size e88
23578240.344: stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
23579240.344: * AP 01stopped
23580240.344: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
23581240.344: * AP 02stopped
23582240.344: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
23583240.344: * AP 03stopped
23584240.344: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
23585240.344: * AP 04stopped
23586240.344: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
23587240.344: * AP 05stopped
23588240.344: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
23589240.344: * AP 06stopped
23590240.344: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
23591240.344: * AP 07stopped
23592240.344: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
23593240.344: * AP 09stopped
23594240.344: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
23595240.344: * AP 0astopped
23596240.344: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
23597240.344: * AP 0bstopped
23598240.344: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
23599240.344: * AP 0cstopped
23600240.344: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
23601240.344: * AP 0dstopped
23602240.344: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
23603240.344: * AP 0estopped
23604240.344: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
23605240.344: * AP 0fstopped
23606240.344: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
23607240.344: * AP 21stopped
23608240.345: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
23609240.345: * AP 22stopped
23610240.345: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
23611240.345: * AP 23stopped
23612240.345: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
23613240.345: * AP 24stopped
23614240.345: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
23615240.345: * AP 25stopped
23616240.345: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
23617240.345: * AP 26stopped
23618240.345: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
23619240.345: * AP 27stopped
23620240.345: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
23621240.345: * AP 29stopped
23622240.345: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
23623240.345: * AP 2astopped
23624240.345: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
23625240.345: * AP 2bstopped
23626240.345: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
23627240.345: * AP 2cstopped
23628240.345: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
23629240.345: * AP 2dstopped
23630240.345: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
23631240.345: * AP 2estopped
23632240.345: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
23633240.345: * AP 2fstopped
23634240.345:
23635240.345: fill_mem_ctrl() detected 4 nodes
23636240.345: raminit_amdmct()
23637240.345: raminit_amdmct begin:
23638240.346: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23639240.346: CBFS: Locating 'cmos_layout.bin'
23640240.346: CBFS: Found @ offset 2b0c0 size e88
23641240.346: mctAutoInitMCT_D: mct_init Node 0
23642240.347: mctAutoInitMCT_D: mct_InitialMCT_D
23643240.347: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
23644240.347: mctAutoInitMCT_D: mctSMBhub_Init
23645240.348: activate_spd_rom() for node 00
23646240.348: enable_spd_node0()
23647240.348: mctAutoInitMCT_D: mct_preInitDCT
23648240.348: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23649240.348: CBFS: Locating 'cmos_layout.bin'
23650240.349: CBFS: Found @ offset 2b0c0 size e88
23651241.957: <09> DIMMPresence: DIMMValid=f
23652241.957: <09> DIMMPresence: DIMMPresent=f
23653241.957: <09> DIMMPresence: RegDIMMPresent=f
23654241.957: <09> DIMMPresence: LRDIMMPresent=0
23655241.957: <09> DIMMPresence: DimmECCPresent=f
23656241.957: <09> DIMMPresence: DimmPARPresent=0
23657241.957: <09> DIMMPresence: Dimmx4Present=f
23658241.957: <09> DIMMPresence: Dimmx8Present=0
23659241.957: <09> DIMMPresence: Dimmx16Present=0
23660241.957: <09> DIMMPresence: DimmPlPresent=0
23661241.957: <09> DIMMPresence: DimmDRPresent=f
23662241.957: <09> DIMMPresence: DimmQRPresent=0
23663241.957: <09> DIMMPresence: DATAload[0]=4
23664241.957: <09> DIMMPresence: MAload[0]=40
23665241.957: <09> DIMMPresence: MAdimms[0]=2
23666241.957: <09> DIMMPresence: DATAload[1]=4
23667241.957: <09> DIMMPresence: MAload[1]=40
23668241.957: <09> DIMMPresence: MAdimms[1]=2
23669241.957: <09> DIMMPresence: Status 2005
23670241.957: <09> DIMMPresence: ErrStatus 0
23671241.958: <09> DIMMPresence: ErrCode 0
23672241.958: <09> DIMMPresence: Done
23673241.958:
23674241.958: <09><09>DCTPreInit_D: mct_DIMMPresence Done
23675241.958: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23676241.958: CBFS: Locating 's3nv'
23677241.958: CBFS: Found @ offset 2fec0 size 10000
23678241.958: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23679241.958: CBFS: Locating 's3nv'
23680241.958: CBFS: Found @ offset 2fec0 size 10000
23681241.959: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23682241.959: CBFS: Locating 'cmos_layout.bin'
23683241.959: CBFS: Found @ offset 2b0c0 size e88
23684241.959: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23685241.959: CBFS: Locating 'cmos_layout.bin'
23686241.959: CBFS: Found @ offset 2b0c0 size e88
23687241.959: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23688241.959: CBFS: Locating 'cmos_layout.bin'
23689241.959: CBFS: Found @ offset 2b0c0 size e88
23690241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23691241.959: CBFS: Locating 'cmos_layout.bin'
23692241.960: CBFS: Found @ offset 2b0c0 size e88
23693241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23694241.960: CBFS: Locating 'cmos_layout.bin'
23695241.960: CBFS: Found @ offset 2b0c0 size e88
23696241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23697241.960: CBFS: Locating 'cmos_layout.bin'
23698241.960: CBFS: Found @ offset 2b0c0 size e88
23699241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23700241.960: CBFS: Locating 'cmos_layout.bin'
23701241.960: CBFS: Found @ offset 2b0c0 size e88
23702241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23703241.960: CBFS: Locating 'cmos_layout.bin'
23704241.960: CBFS: Found @ offset 2b0c0 size e88
23705241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23706241.960: CBFS: Locating 'cmos_layout.bin'
23707241.961: CBFS: Found @ offset 2b0c0 size e88
23708241.961: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23709241.961: CBFS: Locating 'cmos_layout.bin'
23710241.961: CBFS: Found @ offset 2b0c0 size e88
23711241.961: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23712241.961: CBFS: Locating 'cmos_layout.bin'
23713241.961: CBFS: Found @ offset 2b0c0 size e88
23714241.961: mctAutoInitMCT_D: mct_init Node 1
23715241.961: mctAutoInitMCT_D: mct_InitialMCT_D
23716241.961: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
23717241.961: mctAutoInitMCT_D: mctSMBhub_Init
23718241.961: activate_spd_rom() for node 01
23719241.961: enable_spd_node1()
23720241.961: mctAutoInitMCT_D: mct_preInitDCT
23721241.961: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23722241.961: CBFS: Locating 'cmos_layout.bin'
23723241.961: CBFS: Found @ offset 2b0c0 size e88
23724243.570: <09> DIMMPresence: DIMMValid=f
23725243.569: <09> DIMMPresence: DIMMPresent=f
23726243.569: <09> DIMMPresence: RegDIMMPresent=f
23727243.569: <09> DIMMPresence: LRDIMMPresent=0
23728243.569: <09> DIMMPresence: DimmECCPresent=f
23729243.569: <09> DIMMPresence: DimmPARPresent=0
23730243.569: <09> DIMMPresence: Dimmx4Present=f
23731243.569: <09> DIMMPresence: Dimmx8Present=0
23732243.570: <09> DIMMPresence: Dimmx16Present=0
23733243.570: <09> DIMMPresence: DimmPlPresent=0
23734243.570: <09> DIMMPresence: DimmDRPresent=f
23735243.570: <09> DIMMPresence: DimmQRPresent=0
23736243.570: <09> DIMMPresence: DATAload[0]=4
23737243.570: <09> DIMMPresence: MAload[0]=40
23738243.570: <09> DIMMPresence: MAdimms[0]=2
23739243.570: <09> DIMMPresence: DATAload[1]=4
23740243.570: <09> DIMMPresence: MAload[1]=40
23741243.570: <09> DIMMPresence: MAdimms[1]=2
23742243.570: <09> DIMMPresence: Status 2005
23743243.570: <09> DIMMPresence: ErrStatus 0
23744243.570: <09> DIMMPresence: ErrCode 0
23745243.570: <09> DIMMPresence: Done
23746243.570:
23747243.570: <09><09>DCTPreInit_D: mct_DIMMPresence Done
23748243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23749243.570: CBFS: Locating 's3nv'
23750243.570: CBFS: Found @ offset 2fec0 size 10000
23751243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23752243.570: CBFS: Locating 's3nv'
23753243.570: CBFS: Found @ offset 2fec0 size 10000
23754243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23755243.570: CBFS: Locating 'cmos_layout.bin'
23756243.570: CBFS: Found @ offset 2b0c0 size e88
23757243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23758243.570: CBFS: Locating 'cmos_layout.bin'
23759243.570: CBFS: Found @ offset 2b0c0 size e88
23760243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23761243.570: CBFS: Locating 'cmos_layout.bin'
23762243.570: CBFS: Found @ offset 2b0c0 size e88
23763243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23764243.571: CBFS: Locating 'cmos_layout.bin'
23765243.571: CBFS: Found @ offset 2b0c0 size e88
23766243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23767243.571: CBFS: Locating 'cmos_layout.bin'
23768243.571: CBFS: Found @ offset 2b0c0 size e88
23769243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23770243.571: CBFS: Locating 'cmos_layout.bin'
23771243.571: CBFS: Found @ offset 2b0c0 size e88
23772243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23773243.571: CBFS: Locating 'cmos_layout.bin'
23774243.571: CBFS: Found @ offset 2b0c0 size e88
23775243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23776243.571: CBFS: Locating 'cmos_layout.bin'
23777243.571: CBFS: Found @ offset 2b0c0 size e88
23778243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23779243.572: CBFS: Locating 'cmos_layout.bin'
23780243.572: CBFS: Found @ offset 2b0c0 size e88
23781243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23782243.572: CBFS: Locating 'cmos_layout.bin'
23783243.572: CBFS: Found @ offset 2b0c0 size e88
23784243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23785243.572: CBFS: Locating 'cmos_layout.bin'
23786243.572: CBFS: Found @ offset 2b0c0 size e88
23787243.572: mctAutoInitMCT_D: mct_init Node 2
23788243.572: mctAutoInitMCT_D: mct_InitialMCT_D
23789243.572: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
23790243.572: mctAutoInitMCT_D: mctSMBhub_Init
23791243.572: activate_spd_rom() for node 02
23792243.572: enable_spd_node2()
23793243.572: mctAutoInitMCT_D: mct_preInitDCT
23794243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23795243.572: CBFS: Locating 'cmos_layout.bin'
23796243.572: CBFS: Found @ offset 2b0c0 size e88
23797245.180: <09> DIMMPresence: DIMMValid=f
23798245.180: <09> DIMMPresence: DIMMPresent=f
23799245.180: <09> DIMMPresence: RegDIMMPresent=f
23800245.180: <09> DIMMPresence: LRDIMMPresent=0
23801245.180: <09> DIMMPresence: DimmECCPresent=f
23802245.180: <09> DIMMPresence: DimmPARPresent=0
23803245.180: <09> DIMMPresence: Dimmx4Present=f
23804245.180: <09> DIMMPresence: Dimmx8Present=0
23805245.180: <09> DIMMPresence: Dimmx16Present=0
23806245.181: <09> DIMMPresence: DimmPlPresent=0
23807245.181: <09> DIMMPresence: DimmDRPresent=f
23808245.181: <09> DIMMPresence: DimmQRPresent=0
23809245.181: <09> DIMMPresence: DATAload[0]=4
23810245.181: <09> DIMMPresence: MAload[0]=40
23811245.181: <09> DIMMPresence: MAdimms[0]=2
23812245.181: <09> DIMMPresence: DATAload[1]=4
23813245.181: <09> DIMMPresence: MAload[1]=40
23814245.181: <09> DIMMPresence: MAdimms[1]=2
23815245.181: <09> DIMMPresence: Status 2005
23816245.181: <09> DIMMPresence: ErrStatus 0
23817245.181: <09> DIMMPresence: ErrCode 0
23818245.181: <09> DIMMPresence: Done
23819245.181:
23820245.181: <09><09>DCTPreInit_D: mct_DIMMPresence Done
23821245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23822245.181: CBFS: Locating 's3nv'
23823245.181: CBFS: Found @ offset 2fec0 size 10000
23824245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23825245.181: CBFS: Locating 's3nv'
23826245.181: CBFS: Found @ offset 2fec0 size 10000
23827245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23828245.181: CBFS: Locating 'cmos_layout.bin'
23829245.181: CBFS: Found @ offset 2b0c0 size e88
23830245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23831245.181: CBFS: Locating 'cmos_layout.bin'
23832245.181: CBFS: Found @ offset 2b0c0 size e88
23833245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23834245.181: CBFS: Locating 'cmos_layout.bin'
23835245.181: CBFS: Found @ offset 2b0c0 size e88
23836245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23837245.182: CBFS: Locating 'cmos_layout.bin'
23838245.182: CBFS: Found @ offset 2b0c0 size e88
23839245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23840245.182: CBFS: Locating 'cmos_layout.bin'
23841245.182: CBFS: Found @ offset 2b0c0 size e88
23842245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23843245.182: CBFS: Locating 'cmos_layout.bin'
23844245.182: CBFS: Found @ offset 2b0c0 size e88
23845245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23846245.182: CBFS: Locating 'cmos_layout.bin'
23847245.182: CBFS: Found @ offset 2b0c0 size e88
23848245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23849245.182: CBFS: Locating 'cmos_layout.bin'
23850245.182: CBFS: Found @ offset 2b0c0 size e88
23851245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23852245.183: CBFS: Locating 'cmos_layout.bin'
23853245.183: CBFS: Found @ offset 2b0c0 size e88
23854245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23855245.183: CBFS: Locating 'cmos_layout.bin'
23856245.183: CBFS: Found @ offset 2b0c0 size e88
23857245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23858245.183: CBFS: Locating 'cmos_layout.bin'
23859245.183: CBFS: Found @ offset 2b0c0 size e88
23860245.183: mctAutoInitMCT_D: mct_init Node 3
23861245.183: mctAutoInitMCT_D: mct_InitialMCT_D
23862245.183: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
23863245.183: mctAutoInitMCT_D: mctSMBhub_Init
23864245.183: activate_spd_rom() for node 03
23865245.183: enable_spd_node3()
23866245.183: mctAutoInitMCT_D: mct_preInitDCT
23867245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23868245.183: CBFS: Locating 'cmos_layout.bin'
23869245.183: CBFS: Found @ offset 2b0c0 size e88
23870246.791: <09> DIMMPresence: DIMMValid=f
23871246.791: <09> DIMMPresence: DIMMPresent=f
23872246.791: <09> DIMMPresence: RegDIMMPresent=f
23873246.791: <09> DIMMPresence: LRDIMMPresent=0
23874246.791: <09> DIMMPresence: DimmECCPresent=f
23875246.791: <09> DIMMPresence: DimmPARPresent=0
23876246.791: <09> DIMMPresence: Dimmx4Present=f
23877246.791: <09> DIMMPresence: Dimmx8Present=0
23878246.791: <09> DIMMPresence: Dimmx16Present=0
23879246.792: <09> DIMMPresence: DimmPlPresent=0
23880246.792: <09> DIMMPresence: DimmDRPresent=f
23881246.792: <09> DIMMPresence: DimmQRPresent=0
23882246.792: <09> DIMMPresence: DATAload[0]=4
23883246.792: <09> DIMMPresence: MAload[0]=40
23884246.792: <09> DIMMPresence: MAdimms[0]=2
23885246.792: <09> DIMMPresence: DATAload[1]=4
23886246.792: <09> DIMMPresence: MAload[1]=40
23887246.792: <09> DIMMPresence: MAdimms[1]=2
23888246.792: <09> DIMMPresence: Status 2005
23889246.792: <09> DIMMPresence: ErrStatus 0
23890246.792: <09> DIMMPresence: ErrCode 0
23891246.792: <09> DIMMPresence: Done
23892246.792:
23893246.792: <09><09>DCTPreInit_D: mct_DIMMPresence Done
23894246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23895246.792: CBFS: Locating 's3nv'
23896246.792: CBFS: Found @ offset 2fec0 size 10000
23897246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23898246.792: CBFS: Locating 's3nv'
23899246.792: CBFS: Found @ offset 2fec0 size 10000
23900246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23901246.792: CBFS: Locating 'cmos_layout.bin'
23902246.792: CBFS: Found @ offset 2b0c0 size e88
23903246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23904246.792: CBFS: Locating 'cmos_layout.bin'
23905246.792: CBFS: Found @ offset 2b0c0 size e88
23906246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23907246.792: CBFS: Locating 'cmos_layout.bin'
23908246.792: CBFS: Found @ offset 2b0c0 size e88
23909246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23910246.793: CBFS: Locating 'cmos_layout.bin'
23911246.793: CBFS: Found @ offset 2b0c0 size e88
23912246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23913246.793: CBFS: Locating 'cmos_layout.bin'
23914246.793: CBFS: Found @ offset 2b0c0 size e88
23915246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23916246.793: CBFS: Locating 'cmos_layout.bin'
23917246.793: CBFS: Found @ offset 2b0c0 size e88
23918246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23919246.793: CBFS: Locating 'cmos_layout.bin'
23920246.793: CBFS: Found @ offset 2b0c0 size e88
23921246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23922246.793: CBFS: Locating 'cmos_layout.bin'
23923246.793: CBFS: Found @ offset 2b0c0 size e88
23924246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23925246.794: CBFS: Locating 'cmos_layout.bin'
23926246.794: CBFS: Found @ offset 2b0c0 size e88
23927246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23928246.794: CBFS: Locating 'cmos_layout.bin'
23929246.794: CBFS: Found @ offset 2b0c0 size e88
23930246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23931246.794: CBFS: Locating 'cmos_layout.bin'
23932246.794: CBFS: Found @ offset 2b0c0 size e88
23933246.794: mctAutoInitMCT_D: mct_init Node 4
23934246.794: mctAutoInitMCT_D: mct_init Node 5
23935246.794: mctAutoInitMCT_D: mct_init Node 6
23936246.794: mctAutoInitMCT_D: mct_init Node 7
23937246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23938246.795: CBFS: Locating 'cmos_layout.bin'
23939246.795: CBFS: Found @ offset 2b0c0 size e88
23940246.795: mctAutoInitMCT_D: DIMMSetVoltage
23941246.795: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23942246.795: CBFS: Locating 'cmos_layout.bin'
23943246.795: CBFS: Found @ offset 2b0c0 size e88
23944246.796: Node 00 DIMM voltage set to index 00
23945246.796: Node 01 DIMM voltage set to index 00
23946246.896: mctAutoInitMCT_D: mctSMBhub_Init
23947246.896: activate_spd_rom() for node 00
23948246.896: enable_spd_node0()
23949246.896: mctAutoInitMCT_D: mct_initDCT
23950246.896: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23951246.896: CBFS: Locating 'cmos_layout.bin'
23952246.896: CBFS: Found @ offset 2b0c0 size e88
23953246.897: SPDCalcWidth: Status 2005
23954246.897: SPDCalcWidth: ErrStatus 0
23955246.897: SPDCalcWidth: ErrCode 0
23956246.897: SPDCalcWidth: Done
23957246.897: <09><09>DCTInit_D: mct_SPDCalcWidth Done
23958246.897: AutoCycTiming_D: Start
23959246.897: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23960246.897: CBFS: Locating 'cmos_layout.bin'
23961246.897: CBFS: Found @ offset 2b0c0 size e88
23962246.897: GetPresetmaxF_D: Start
23963246.897: GetPresetmaxF_D: Done
23964246.898: SPDGetTCL_D: Start
23965246.898: SPDGetTCL_D: DIMMCASL 5
23966246.898: SPDGetTCL_D: DIMMAutoSpeed 4
23967246.898: SPDGetTCL_D: Status 2005
23968246.898: SPDGetTCL_D: ErrStatus 0
23969246.898: SPDGetTCL_D: ErrCode 0
23970246.898: SPDGetTCL_D: Done
23971246.898:
23972246.898: SPD2ndTiming: Start
23973246.899: SPD2ndTiming: Done
23974246.899: AutoCycTiming: Status 2005
23975246.899: AutoCycTiming: ErrStatus 0
23976246.899: AutoCycTiming: ErrCode 0
23977246.899: AutoCycTiming: Done
23978246.899:
23979246.899: <09><09>DCTInit_D: AutoCycTiming_D Done
23980246.900: SPDSetBanks: CSPresent f
23981246.900: SPDSetBanks: Status 2005
23982246.900: SPDSetBanks: ErrStatus 0
23983246.900: SPDSetBanks: ErrCode 0
23984246.900: SPDSetBanks: Done
23985246.900:
23986246.900: AfterStitch pDCTstat->NodeSysBase = 0
23987246.900: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
23988246.900: StitchMemory: Status 2005
23989246.900: StitchMemory: ErrStatus 0
23990246.900: StitchMemory: ErrCode 0
23991246.900: StitchMemory: Done
23992246.900:
23993246.900: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
23994246.900: CBFS: Locating 'cmos_layout.bin'
23995246.900: CBFS: Found @ offset 2b0c0 size e88
23996246.901: InterleaveBanks_D: Status 2005
23997246.901: InterleaveBanks_D: ErrStatus 0
23998246.901: InterleaveBanks_D: ErrCode 0
23999246.901: InterleaveBanks_D: Done
24000246.901:
24001246.901: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24002246.901: CBFS: Locating 'cmos_layout.bin'
24003246.901: CBFS: Found @ offset 2b0c0 size e88
24004246.902: AutoConfig_D: DramControl: 00002a06
24005246.902: AutoConfig_D: DramTimingLo: 00000000
24006246.902: AutoConfig_D: DramConfigMisc: 00000000
24007246.902: AutoConfig_D: DramConfigMisc2: 00000000
24008246.902: AutoConfig_D: DramConfigLo: 03083000
24009246.902: AutoConfig_D: DramConfigHi: 0f090084
24010246.902: InitDDRPhy: Start
24011246.903: InitDDRPhy: Done
24012246.903: mct_SetDramConfigHi_D: Start
24013246.904: set_2t_configuration: Start
24014246.904: set_2t_configuration: Done
24015246.904: mct_BeforePlatformSpec: Start
24016246.904: mct_BeforePlatformSpec: Done
24017246.904: mct_PlatformSpec: Start
24018246.904: Programmed DCT 0 timing/termination pattern 00000000 10222222
24019246.904: mct_PlatformSpec: Done
24020246.904: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
24021246.904: *
24022246.904: mct_SetDramConfigHi_D: Done
24023246.904: mct_EarlyArbEn_D: Start
24024246.904: mct_EarlyArbEn_D: Done
24025246.904: AutoConfig: Status 2005
24026246.904: AutoConfig: ErrStatus 0
24027246.904: AutoConfig: ErrCode 0
24028246.904: AutoConfig: Done
24029246.904:
24030246.904: <09><09>DCTInit_D: AutoConfig_D Done
24031246.904: <09><09>DCTInit_D: PlatformSpec_D Done
24032246.904: <09><09>DCTFinalInit_D: StartupDCT_D Start
24033246.904: mct_BeforeDramInit_Prod_D: Start
24034246.904: mct_ProgramODT_D: Start
24035246.905: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
24036246.905: mct_ProgramODT_D: Done
24037246.905: mct_BeforeDramInit_Prod_D: Done
24038246.905: mct_DramInit_Sw_D: Start
24039246.905: mct_DCTAccessDone: Start
24040246.905: mct_DCTAccessDone: Done
24041246.906: mct_DramControlReg_Init_D: Start
24042246.907: mct_DramControlReg_Init_D: F2xA8: 00000300
24043246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
24044246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
24045246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24046246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
24047246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
24048246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
24049246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
24050246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
24051246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
24052246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24053246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
24054246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
24055246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
24056246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
24057246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
24058246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
24059246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
24060246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
24061246.907: mct_DramControlReg_Init_D: F2xA8: 00000c00
24062246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
24063246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
24064246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24065246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
24066246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
24067246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
24068246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
24069246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
24070246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
24071246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24072246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
24073246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
24074246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
24075246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
24076246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
24077246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
24078246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
24079246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
24080246.907: mct_DramControlReg_Init_D: Done
24081246.908: DIMM 0 RttWr: 2
24082246.908: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
24083246.908: mct_SendMrsCmd: Start
24084246.908: mct_SendMrsCmd: Done
24085246.908: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
24086246.908: mct_SendMrsCmd: Start
24087246.908: mct_SendMrsCmd: Done
24088246.908: DIMM 0 RttNom: 3
24089246.908: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
24090246.908: mct_SendMrsCmd: Start
24091246.908: mct_SendMrsCmd: Done
24092246.909: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
24093246.909: mct_SendMrsCmd: Start
24094246.909: mct_SendMrsCmd: Done
24095246.909: DIMM 0 RttWr: 2
24096246.909: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
24097246.909: mct_SendMrsCmd: Start
24098246.909: mct_SendMrsCmd: Done
24099246.909: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
24100246.909: mct_SendMrsCmd: Start
24101246.909: mct_SendMrsCmd: Done
24102246.909: DIMM 0 RttNom: 3
24103246.909: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
24104246.909: mct_SendMrsCmd: Start
24105246.909: mct_SendMrsCmd: Done
24106246.909: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
24107246.909: mct_SendMrsCmd: Start
24108246.909: mct_SendMrsCmd: Done
24109246.909: DIMM 1 RttWr: 2
24110246.909: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
24111246.909: mct_SendMrsCmd: Start
24112246.909: mct_SendMrsCmd: Done
24113246.909: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
24114246.909: mct_SendMrsCmd: Start
24115246.909: mct_SendMrsCmd: Done
24116246.909: DIMM 1 RttNom: 3
24117246.909: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
24118246.909: mct_SendMrsCmd: Start
24119246.909: mct_SendMrsCmd: Done
24120246.909: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
24121246.909: mct_SendMrsCmd: Start
24122246.909: mct_SendMrsCmd: Done
24123246.909: DIMM 1 RttWr: 2
24124246.909: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
24125246.909: mct_SendMrsCmd: Start
24126246.909: mct_SendMrsCmd: Done
24127246.909: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
24128246.909: mct_SendMrsCmd: Start
24129246.909: mct_SendMrsCmd: Done
24130246.909: DIMM 1 RttNom: 3
24131246.909: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
24132246.909: mct_SendMrsCmd: Start
24133246.909: mct_SendMrsCmd: Done
24134246.909: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
24135246.909: mct_SendMrsCmd: Start
24136246.909: mct_SendMrsCmd: Done
24137246.909: mct_SendZQCmd: Start
24138246.909: mct_SendZQCmd: Done
24139246.909: mct_SendZQCmd: Start
24140246.909: mct_SendZQCmd: Done
24141246.909: mct_DCTAccessDone: Start
24142246.909: mct_DCTAccessDone: Done
24143246.909: mct_DramInit_Sw_D: Done
24144246.909: <09><09>DCTFinalInit_D: StartupDCT_D Done
24145246.909: SPDCalcWidth: Status 2005
24146246.909: SPDCalcWidth: ErrStatus 0
24147246.909: SPDCalcWidth: ErrCode 0
24148246.909: SPDCalcWidth: Done
24149246.909: <09><09>DCTInit_D: mct_SPDCalcWidth Done
24150246.910: AutoCycTiming_D: Start
24151246.910: SPD2ndTiming: Start
24152246.910: SPD2ndTiming: Done
24153246.910: AutoCycTiming: Status 2005
24154246.910: AutoCycTiming: ErrStatus 0
24155246.910: AutoCycTiming: ErrCode 0
24156246.910: AutoCycTiming: Done
24157246.910:
24158246.910: <09><09>DCTInit_D: AutoCycTiming_D Done
24159246.910: <09><09>DCTInit_D: enabling intra-channel clock skew
24160246.910: SPDSetBanks: CSPresent f
24161246.910: SPDSetBanks: Status 2005
24162246.910: SPDSetBanks: ErrStatus 0
24163246.910: SPDSetBanks: ErrCode 0
24164246.910: SPDSetBanks: Done
24165246.910:
24166246.910: AfterStitch pDCTstat->NodeSysBase = 0
24167246.910: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
24168246.910: StitchMemory: Status 2005
24169246.910: StitchMemory: ErrStatus 0
24170246.910: StitchMemory: ErrCode 0
24171246.910: StitchMemory: Done
24172246.910:
24173246.910: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24174246.910: CBFS: Locating 'cmos_layout.bin'
24175246.910: CBFS: Found @ offset 2b0c0 size e88
24176246.911: InterleaveBanks_D: Status 2005
24177246.911: InterleaveBanks_D: ErrStatus 0
24178246.911: InterleaveBanks_D: ErrCode 0
24179246.911: InterleaveBanks_D: Done
24180246.911:
24181246.911: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24182246.911: CBFS: Locating 'cmos_layout.bin'
24183246.911: CBFS: Found @ offset 2b0c0 size e88
24184246.911: AutoConfig_D: DramControl: 00002a06
24185246.911: AutoConfig_D: DramTimingLo: 00000000
24186246.911: AutoConfig_D: DramConfigMisc: 00000000
24187246.911: AutoConfig_D: DramConfigMisc2: 00000000
24188246.911: AutoConfig_D: DramConfigLo: 03083000
24189246.911: AutoConfig_D: DramConfigHi: 0f090084
24190246.911: InitDDRPhy: Start
24191246.911: InitDDRPhy: Done
24192246.911: mct_SetDramConfigHi_D: Start
24193246.911: set_2t_configuration: Start
24194246.911: set_2t_configuration: Done
24195246.911: mct_BeforePlatformSpec: Start
24196246.911: mct_BeforePlatformSpec: Done
24197246.911: mct_PlatformSpec: Start
24198246.911: Programmed DCT 1 timing/termination pattern 00000000 10222222
24199246.911: mct_PlatformSpec: Done
24200246.911: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
24201246.911: *
24202246.911: mct_SetDramConfigHi_D: Done
24203246.911: mct_EarlyArbEn_D: Start
24204246.911: mct_EarlyArbEn_D: Done
24205246.911: AutoConfig: Status 2005
24206246.911: AutoConfig: ErrStatus 0
24207246.911: AutoConfig: ErrCode 0
24208246.911: AutoConfig: Done
24209246.911:
24210246.911: <09><09>DCTInit_D: AutoConfig_D Done
24211246.912: <09><09>DCTInit_D: PlatformSpec_D Done
24212246.912: <09><09>DCTFinalInit_D: StartupDCT_D Start
24213246.912: mct_BeforeDramInit_Prod_D: Start
24214246.912: mct_ProgramODT_D: Start
24215246.912: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
24216246.912: mct_ProgramODT_D: Done
24217246.912: mct_BeforeDramInit_Prod_D: Done
24218246.912: mct_DramInit_Sw_D: Start
24219246.912: mct_DCTAccessDone: Start
24220246.912: mct_DCTAccessDone: Done
24221246.913: mct_DramControlReg_Init_D: Start
24222246.913: mct_DramControlReg_Init_D: F2xA8: 00000300
24223246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
24224246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
24225246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24226246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
24227246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
24228246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
24229246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
24230246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
24231246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
24232246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24233246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
24234246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
24235246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
24236246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
24237246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
24238246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
24239246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
24240246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
24241246.913: mct_DramControlReg_Init_D: F2xA8: 00000c00
24242246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
24243246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
24244246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24245246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
24246246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
24247246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
24248246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
24249246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
24250246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
24251246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24252246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
24253246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
24254246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
24255246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
24256246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
24257246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
24258246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
24259246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
24260246.913: mct_DramControlReg_Init_D: Done
24261246.913: DIMM 0 RttWr: 2
24262246.913: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
24263246.913: mct_SendMrsCmd: Start
24264246.913: mct_SendMrsCmd: Done
24265246.913: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
24266246.913: mct_SendMrsCmd: Start
24267246.913: mct_SendMrsCmd: Done
24268246.913: DIMM 0 RttNom: 3
24269246.914: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
24270246.914: mct_SendMrsCmd: Start
24271246.914: mct_SendMrsCmd: Done
24272246.914: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
24273246.914: mct_SendMrsCmd: Start
24274246.914: mct_SendMrsCmd: Done
24275246.914: DIMM 0 RttWr: 2
24276246.914: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
24277246.914: mct_SendMrsCmd: Start
24278246.914: mct_SendMrsCmd: Done
24279246.914: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
24280246.914: mct_SendMrsCmd: Start
24281246.914: mct_SendMrsCmd: Done
24282246.914: DIMM 0 RttNom: 3
24283246.914: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
24284246.914: mct_SendMrsCmd: Start
24285246.914: mct_SendMrsCmd: Done
24286246.914: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
24287246.914: mct_SendMrsCmd: Start
24288246.914: mct_SendMrsCmd: Done
24289246.914: DIMM 1 RttWr: 2
24290246.914: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
24291246.914: mct_SendMrsCmd: Start
24292246.914: mct_SendMrsCmd: Done
24293246.914: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
24294246.914: mct_SendMrsCmd: Start
24295246.914: mct_SendMrsCmd: Done
24296246.914: DIMM 1 RttNom: 3
24297246.914: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
24298246.914: mct_SendMrsCmd: Start
24299246.914: mct_SendMrsCmd: Done
24300246.914: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
24301246.914: mct_SendMrsCmd: Start
24302246.914: mct_SendMrsCmd: Done
24303246.914: DIMM 1 RttWr: 2
24304246.914: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
24305246.914: mct_SendMrsCmd: Start
24306246.914: mct_SendMrsCmd: Done
24307246.914: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
24308246.914: mct_SendMrsCmd: Start
24309246.914: mct_SendMrsCmd: Done
24310246.914: DIMM 1 RttNom: 3
24311246.914: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
24312246.914: mct_SendMrsCmd: Start
24313246.914: mct_SendMrsCmd: Done
24314246.914: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
24315246.914: mct_SendMrsCmd: Start
24316246.914: mct_SendMrsCmd: Done
24317246.914: mct_SendZQCmd: Start
24318246.914: mct_SendZQCmd: Done
24319246.914: mct_SendZQCmd: Start
24320246.914: mct_SendZQCmd: Done
24321246.914: mct_DCTAccessDone: Start
24322246.914: mct_DCTAccessDone: Done
24323246.914: mct_DramInit_Sw_D: Done
24324246.914: <09><09>DCTFinalInit_D: StartupDCT_D Done
24325246.914: mctAutoInitMCT_D: mctSMBhub_Init
24326246.914: activate_spd_rom() for node 01
24327246.914: enable_spd_node1()
24328246.914: mctAutoInitMCT_D: mct_initDCT
24329246.915: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24330246.915: CBFS: Locating 'cmos_layout.bin'
24331246.915: CBFS: Found @ offset 2b0c0 size e88
24332246.915: SPDCalcWidth: Status 2005
24333246.915: SPDCalcWidth: ErrStatus 0
24334246.915: SPDCalcWidth: ErrCode 0
24335246.915: SPDCalcWidth: Done
24336246.915: <09><09>DCTInit_D: mct_SPDCalcWidth Done
24337246.915: AutoCycTiming_D: Start
24338246.915: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24339246.915: CBFS: Locating 'cmos_layout.bin'
24340246.915: CBFS: Found @ offset 2b0c0 size e88
24341246.915: GetPresetmaxF_D: Start
24342246.915: GetPresetmaxF_D: Done
24343246.915: SPDGetTCL_D: Start
24344246.915: SPDGetTCL_D: DIMMCASL 5
24345246.915: SPDGetTCL_D: DIMMAutoSpeed 4
24346246.915: SPDGetTCL_D: Status 2005
24347246.915: SPDGetTCL_D: ErrStatus 0
24348246.915: SPDGetTCL_D: ErrCode 0
24349246.915: SPDGetTCL_D: Done
24350246.915:
24351246.915: SPD2ndTiming: Start
24352246.915: SPD2ndTiming: Done
24353246.915: AutoCycTiming: Status 2005
24354246.915: AutoCycTiming: ErrStatus 0
24355246.915: AutoCycTiming: ErrCode 0
24356246.915: AutoCycTiming: Done
24357246.915:
24358246.915: <09><09>DCTInit_D: AutoCycTiming_D Done
24359246.916: SPDSetBanks: CSPresent f
24360246.916: SPDSetBanks: Status 2005
24361246.916: SPDSetBanks: ErrStatus 0
24362246.916: SPDSetBanks: ErrCode 0
24363246.916: SPDSetBanks: Done
24364246.916:
24365246.916: AfterStitch pDCTstat->NodeSysBase = 0
24366246.916: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
24367246.916: StitchMemory: Status 2005
24368246.916: StitchMemory: ErrStatus 0
24369246.916: StitchMemory: ErrCode 0
24370246.916: StitchMemory: Done
24371246.916:
24372246.916: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24373246.916: CBFS: Locating 'cmos_layout.bin'
24374246.916: CBFS: Found @ offset 2b0c0 size e88
24375246.916: InterleaveBanks_D: Status 2005
24376246.916: InterleaveBanks_D: ErrStatus 0
24377246.916: InterleaveBanks_D: ErrCode 0
24378246.916: InterleaveBanks_D: Done
24379246.916:
24380246.917: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24381246.917: CBFS: Locating 'cmos_layout.bin'
24382246.917: CBFS: Found @ offset 2b0c0 size e88
24383246.917: AutoConfig_D: DramControl: 00002a06
24384246.917: AutoConfig_D: DramTimingLo: 00000000
24385246.917: AutoConfig_D: DramConfigMisc: 00000000
24386246.917: AutoConfig_D: DramConfigMisc2: 00000000
24387246.917: AutoConfig_D: DramConfigLo: 03083000
24388246.917: AutoConfig_D: DramConfigHi: 0f090084
24389246.917: InitDDRPhy: Start
24390246.917: InitDDRPhy: Done
24391246.917: mct_SetDramConfigHi_D: Start
24392246.917: set_2t_configuration: Start
24393246.917: set_2t_configuration: Done
24394246.917: mct_BeforePlatformSpec: Start
24395246.917: mct_BeforePlatformSpec: Done
24396246.917: mct_PlatformSpec: Start
24397246.917: Programmed DCT 0 timing/termination pattern 00000000 10222222
24398246.917: mct_PlatformSpec: Done
24399246.917: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
24400246.917: *
24401246.917: mct_SetDramConfigHi_D: Done
24402246.917: mct_EarlyArbEn_D: Start
24403246.917: mct_EarlyArbEn_D: Done
24404246.917: AutoConfig: Status 2005
24405246.917: AutoConfig: ErrStatus 0
24406246.917: AutoConfig: ErrCode 0
24407246.917: AutoConfig: Done
24408246.917:
24409246.917: <09><09>DCTInit_D: AutoConfig_D Done
24410246.917: <09><09>DCTInit_D: PlatformSpec_D Done
24411246.917: <09><09>DCTFinalInit_D: StartupDCT_D Start
24412246.917: mct_BeforeDramInit_Prod_D: Start
24413246.917: mct_ProgramODT_D: Start
24414246.917: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
24415246.917: mct_ProgramODT_D: Done
24416246.917: mct_BeforeDramInit_Prod_D: Done
24417246.918: mct_DramInit_Sw_D: Start
24418246.918: mct_DCTAccessDone: Start
24419246.918: mct_DCTAccessDone: Done
24420246.918: mct_DramControlReg_Init_D: Start
24421246.918: mct_DramControlReg_Init_D: F2xA8: 00000300
24422246.918: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
24423246.918: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
24424246.918: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24425246.918: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
24426246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
24427246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
24428246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
24429246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
24430246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
24431246.919: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24432246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
24433246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
24434246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
24435246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
24436246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
24437246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
24438246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
24439246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
24440246.919: mct_DramControlReg_Init_D: F2xA8: 00000c00
24441246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
24442246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
24443246.919: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24444246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
24445246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
24446246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
24447246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
24448246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
24449246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
24450246.919: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24451246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
24452246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
24453246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
24454246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
24455246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
24456246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
24457246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
24458246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
24459246.919: mct_DramControlReg_Init_D: Done
24460246.919: DIMM 0 RttWr: 2
24461246.919: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
24462246.919: mct_SendMrsCmd: Start
24463246.919: mct_SendMrsCmd: Done
24464246.919: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
24465246.919: mct_SendMrsCmd: Start
24466246.919: mct_SendMrsCmd: Done
24467246.919: DIMM 0 RttNom: 3
24468246.919: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
24469246.919: mct_SendMrsCmd: Start
24470246.919: mct_SendMrsCmd: Done
24471246.920: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
24472246.920: mct_SendMrsCmd: Start
24473246.920: mct_SendMrsCmd: Done
24474246.920: DIMM 0 RttWr: 2
24475246.920: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
24476246.920: mct_SendMrsCmd: Start
24477246.920: mct_SendMrsCmd: Done
24478246.920: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
24479246.920: mct_SendMrsCmd: Start
24480246.920: mct_SendMrsCmd: Done
24481246.920: DIMM 0 RttNom: 3
24482246.920: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
24483246.920: mct_SendMrsCmd: Start
24484246.920: mct_SendMrsCmd: Done
24485246.920: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
24486246.920: mct_SendMrsCmd: Start
24487246.920: mct_SendMrsCmd: Done
24488246.920: DIMM 1 RttWr: 2
24489246.920: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
24490246.920: mct_SendMrsCmd: Start
24491246.920: mct_SendMrsCmd: Done
24492246.920: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
24493246.920: mct_SendMrsCmd: Start
24494246.920: mct_SendMrsCmd: Done
24495246.920: DIMM 1 RttNom: 3
24496246.920: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
24497246.920: mct_SendMrsCmd: Start
24498246.920: mct_SendMrsCmd: Done
24499246.920: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
24500246.920: mct_SendMrsCmd: Start
24501246.920: mct_SendMrsCmd: Done
24502246.920: DIMM 1 RttWr: 2
24503246.920: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
24504246.920: mct_SendMrsCmd: Start
24505246.920: mct_SendMrsCmd: Done
24506246.920: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
24507246.920: mct_SendMrsCmd: Start
24508246.920: mct_SendMrsCmd: Done
24509246.920: DIMM 1 RttNom: 3
24510246.920: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
24511246.920: mct_SendMrsCmd: Start
24512246.920: mct_SendMrsCmd: Done
24513246.920: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
24514246.920: mct_SendMrsCmd: Start
24515246.920: mct_SendMrsCmd: Done
24516246.920: mct_SendZQCmd: Start
24517246.920: mct_SendZQCmd: Done
24518246.920: mct_SendZQCmd: Start
24519246.920: mct_SendZQCmd: Done
24520246.920: mct_DCTAccessDone: Start
24521246.920: mct_DCTAccessDone: Done
24522246.920: mct_DramInit_Sw_D: Done
24523246.920: <09><09>DCTFinalInit_D: StartupDCT_D Done
24524246.920: SPDCalcWidth: Status 2005
24525246.920: SPDCalcWidth: ErrStatus 0
24526246.920: SPDCalcWidth: ErrCode 0
24527246.920: SPDCalcWidth: Done
24528246.920: <09><09>DCTInit_D: mct_SPDCalcWidth Done
24529246.920: AutoCycTiming_D: Start
24530246.920: SPD2ndTiming: Start
24531246.920: SPD2ndTiming: Done
24532246.920: AutoCycTiming: Status 2005
24533246.920: AutoCycTiming: ErrStatus 0
24534246.920: AutoCycTiming: ErrCode 0
24535246.920: AutoCycTiming: Done
24536246.920:
24537246.921: <09><09>DCTInit_D: AutoCycTiming_D Done
24538246.921: <09><09>DCTInit_D: enabling intra-channel clock skew
24539246.921: SPDSetBanks: CSPresent f
24540246.921: SPDSetBanks: Status 2005
24541246.921: SPDSetBanks: ErrStatus 0
24542246.921: SPDSetBanks: ErrCode 0
24543246.921: SPDSetBanks: Done
24544246.921:
24545246.921: AfterStitch pDCTstat->NodeSysBase = 0
24546246.921: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
24547246.921: StitchMemory: Status 2005
24548246.921: StitchMemory: ErrStatus 0
24549246.921: StitchMemory: ErrCode 0
24550246.921: StitchMemory: Done
24551246.921:
24552246.921: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24553246.921: CBFS: Locating 'cmos_layout.bin'
24554246.921: CBFS: Found @ offset 2b0c0 size e88
24555246.922: InterleaveBanks_D: Status 2005
24556246.921: InterleaveBanks_D: ErrStatus 0
24557246.922: InterleaveBanks_D: ErrCode 0
24558246.922: InterleaveBanks_D: Done
24559246.922:
24560246.922: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24561246.922: CBFS: Locating 'cmos_layout.bin'
24562246.922: CBFS: Found @ offset 2b0c0 size e88
24563246.922: AutoConfig_D: DramControl: 00002a06
24564246.922: AutoConfig_D: DramTimingLo: 00000000
24565246.922: AutoConfig_D: DramConfigMisc: 00000000
24566246.922: AutoConfig_D: DramConfigMisc2: 00000000
24567246.922: AutoConfig_D: DramConfigLo: 03083000
24568246.922: AutoConfig_D: DramConfigHi: 0f090084
24569246.922: InitDDRPhy: Start
24570246.922: InitDDRPhy: Done
24571246.922: mct_SetDramConfigHi_D: Start
24572246.922: set_2t_configuration: Start
24573246.922: set_2t_configuration: Done
24574246.922: mct_BeforePlatformSpec: Start
24575246.922: mct_BeforePlatformSpec: Done
24576246.922: mct_PlatformSpec: Start
24577246.922: Programmed DCT 1 timing/termination pattern 00000000 10222222
24578246.922: mct_PlatformSpec: Done
24579246.922: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
24580246.922: *
24581246.922: mct_SetDramConfigHi_D: Done
24582246.922: mct_EarlyArbEn_D: Start
24583246.922: mct_EarlyArbEn_D: Done
24584246.922: AutoConfig: Status 2005
24585246.922: AutoConfig: ErrStatus 0
24586246.922: AutoConfig: ErrCode 0
24587246.922: AutoConfig: Done
24588246.922:
24589246.922: <09><09>DCTInit_D: AutoConfig_D Done
24590246.922: <09><09>DCTInit_D: PlatformSpec_D Done
24591246.922: <09><09>DCTFinalInit_D: StartupDCT_D Start
24592246.922: mct_BeforeDramInit_Prod_D: Start
24593246.923: mct_ProgramODT_D: Start
24594246.922: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
24595246.922: mct_ProgramODT_D: Done
24596246.923: mct_BeforeDramInit_Prod_D: Done
24597246.923: mct_DramInit_Sw_D: Start
24598246.923: mct_DCTAccessDone: Start
24599246.923: mct_DCTAccessDone: Done
24600246.924: mct_DramControlReg_Init_D: Start
24601246.924: mct_DramControlReg_Init_D: F2xA8: 00000300
24602246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
24603246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
24604246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24605246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
24606246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
24607246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
24608246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
24609246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
24610246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
24611246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24612246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
24613246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
24614246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
24615246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
24616246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
24617246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
24618246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
24619246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
24620246.924: mct_DramControlReg_Init_D: F2xA8: 00000c00
24621246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
24622246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
24623246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24624246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
24625246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
24626246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
24627246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
24628246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
24629246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
24630246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24631246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
24632246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
24633246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
24634246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
24635246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
24636246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
24637246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
24638246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
24639246.924: mct_DramControlReg_Init_D: Done
24640246.924: DIMM 0 RttWr: 2
24641246.924: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
24642246.924: mct_SendMrsCmd: Start
24643246.924: mct_SendMrsCmd: Done
24644246.924: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
24645246.924: mct_SendMrsCmd: Start
24646246.924: mct_SendMrsCmd: Done
24647246.924: DIMM 0 RttNom: 3
24648246.924: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
24649246.925: mct_SendMrsCmd: Start
24650246.924: mct_SendMrsCmd: Done
24651246.925: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
24652246.925: mct_SendMrsCmd: Start
24653246.925: mct_SendMrsCmd: Done
24654246.925: DIMM 0 RttWr: 2
24655246.925: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
24656246.925: mct_SendMrsCmd: Start
24657246.925: mct_SendMrsCmd: Done
24658246.925: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
24659246.925: mct_SendMrsCmd: Start
24660246.925: mct_SendMrsCmd: Done
24661246.925: DIMM 0 RttNom: 3
24662246.925: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
24663246.925: mct_SendMrsCmd: Start
24664246.925: mct_SendMrsCmd: Done
24665246.925: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
24666246.925: mct_SendMrsCmd: Start
24667246.925: mct_SendMrsCmd: Done
24668246.925: DIMM 1 RttWr: 2
24669246.925: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
24670246.925: mct_SendMrsCmd: Start
24671246.925: mct_SendMrsCmd: Done
24672246.925: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
24673246.925: mct_SendMrsCmd: Start
24674246.925: mct_SendMrsCmd: Done
24675246.925: DIMM 1 RttNom: 3
24676246.925: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
24677246.925: mct_SendMrsCmd: Start
24678246.925: mct_SendMrsCmd: Done
24679246.925: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
24680246.925: mct_SendMrsCmd: Start
24681246.925: mct_SendMrsCmd: Done
24682246.925: DIMM 1 RttWr: 2
24683246.925: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
24684246.925: mct_SendMrsCmd: Start
24685246.925: mct_SendMrsCmd: Done
24686246.925: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
24687246.925: mct_SendMrsCmd: Start
24688246.925: mct_SendMrsCmd: Done
24689246.925: DIMM 1 RttNom: 3
24690246.925: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
24691246.925: mct_SendMrsCmd: Start
24692246.925: mct_SendMrsCmd: Done
24693246.925: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
24694246.925: mct_SendMrsCmd: Start
24695246.925: mct_SendMrsCmd: Done
24696246.925: mct_SendZQCmd: Start
24697246.925: mct_SendZQCmd: Done
24698246.925: mct_SendZQCmd: Start
24699246.925: mct_SendZQCmd: Done
24700246.925: mct_DCTAccessDone: Start
24701246.925: mct_DCTAccessDone: Done
24702246.925: mct_DramInit_Sw_D: Done
24703246.925: <09><09>DCTFinalInit_D: StartupDCT_D Done
24704246.925: mctAutoInitMCT_D: mctSMBhub_Init
24705246.925: activate_spd_rom() for node 02
24706246.925: enable_spd_node2()
24707246.925: mctAutoInitMCT_D: mct_initDCT
24708246.925: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24709246.925: CBFS: Locating 'cmos_layout.bin'
24710246.925: CBFS: Found @ offset 2b0c0 size e88
24711246.926: SPDCalcWidth: Status 2005
24712246.926: SPDCalcWidth: ErrStatus 0
24713246.926: SPDCalcWidth: ErrCode 0
24714246.926: SPDCalcWidth: Done
24715246.926: <09><09>DCTInit_D: mct_SPDCalcWidth Done
24716246.926: AutoCycTiming_D: Start
24717246.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24718246.926: CBFS: Locating 'cmos_layout.bin'
24719246.926: CBFS: Found @ offset 2b0c0 size e88
24720246.926: GetPresetmaxF_D: Start
24721246.926: GetPresetmaxF_D: Done
24722246.926: SPDGetTCL_D: Start
24723246.926: SPDGetTCL_D: DIMMCASL 5
24724246.926: SPDGetTCL_D: DIMMAutoSpeed 4
24725246.926: SPDGetTCL_D: Status 2005
24726246.926: SPDGetTCL_D: ErrStatus 0
24727246.926: SPDGetTCL_D: ErrCode 0
24728246.926: SPDGetTCL_D: Done
24729246.926:
24730246.926: SPD2ndTiming: Start
24731246.926: SPD2ndTiming: Done
24732246.926: AutoCycTiming: Status 2005
24733246.926: AutoCycTiming: ErrStatus 0
24734246.926: AutoCycTiming: ErrCode 0
24735246.926: AutoCycTiming: Done
24736246.926:
24737246.926: <09><09>DCTInit_D: AutoCycTiming_D Done
24738246.927: SPDSetBanks: CSPresent f
24739246.927: SPDSetBanks: Status 2005
24740246.927: SPDSetBanks: ErrStatus 0
24741246.927: SPDSetBanks: ErrCode 0
24742246.927: SPDSetBanks: Done
24743246.927:
24744246.927: AfterStitch pDCTstat->NodeSysBase = 0
24745246.927: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
24746246.927: StitchMemory: Status 2005
24747246.927: StitchMemory: ErrStatus 0
24748246.927: StitchMemory: ErrCode 0
24749246.927: StitchMemory: Done
24750246.927:
24751246.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24752246.927: CBFS: Locating 'cmos_layout.bin'
24753246.927: CBFS: Found @ offset 2b0c0 size e88
24754246.927: InterleaveBanks_D: Status 2005
24755246.927: InterleaveBanks_D: ErrStatus 0
24756246.927: InterleaveBanks_D: ErrCode 0
24757246.927: InterleaveBanks_D: Done
24758246.927:
24759246.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24760246.927: CBFS: Locating 'cmos_layout.bin'
24761246.927: CBFS: Found @ offset 2b0c0 size e88
24762246.928: AutoConfig_D: DramControl: 00002a06
24763246.928: AutoConfig_D: DramTimingLo: 00000000
24764246.928: AutoConfig_D: DramConfigMisc: 00000000
24765246.928: AutoConfig_D: DramConfigMisc2: 00000000
24766246.928: AutoConfig_D: DramConfigLo: 03083000
24767246.928: AutoConfig_D: DramConfigHi: 0f090084
24768246.928: InitDDRPhy: Start
24769246.928: InitDDRPhy: Done
24770246.928: mct_SetDramConfigHi_D: Start
24771246.928: set_2t_configuration: Start
24772246.928: set_2t_configuration: Done
24773246.928: mct_BeforePlatformSpec: Start
24774246.928: mct_BeforePlatformSpec: Done
24775246.928: mct_PlatformSpec: Start
24776246.928: Programmed DCT 0 timing/termination pattern 00000000 10222222
24777246.928: mct_PlatformSpec: Done
24778246.928: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
24779246.928: *
24780246.928: mct_SetDramConfigHi_D: Done
24781246.928: mct_EarlyArbEn_D: Start
24782246.928: mct_EarlyArbEn_D: Done
24783246.928: AutoConfig: Status 2005
24784246.928: AutoConfig: ErrStatus 0
24785246.928: AutoConfig: ErrCode 0
24786246.928: AutoConfig: Done
24787246.928:
24788246.928: <09><09>DCTInit_D: AutoConfig_D Done
24789246.928: <09><09>DCTInit_D: PlatformSpec_D Done
24790246.928: <09><09>DCTFinalInit_D: StartupDCT_D Start
24791246.928: mct_BeforeDramInit_Prod_D: Start
24792246.928: mct_ProgramODT_D: Start
24793246.928: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
24794246.928: mct_ProgramODT_D: Done
24795246.928: mct_BeforeDramInit_Prod_D: Done
24796246.928: mct_DramInit_Sw_D: Start
24797246.928: mct_DCTAccessDone: Start
24798246.928: mct_DCTAccessDone: Done
24799246.929: mct_DramControlReg_Init_D: Start
24800246.929: mct_DramControlReg_Init_D: F2xA8: 00000300
24801246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
24802246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
24803246.929: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24804246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
24805246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
24806246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
24807246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
24808246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
24809246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
24810246.929: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24811246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
24812246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
24813246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
24814246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
24815246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
24816246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
24817246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
24818246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
24819246.930: mct_DramControlReg_Init_D: F2xA8: 00000c00
24820246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
24821246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
24822246.930: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24823246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
24824246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
24825246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
24826246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
24827246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
24828246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
24829246.930: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
24830246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
24831246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
24832246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
24833246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
24834246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
24835246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
24836246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
24837246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
24838246.930: mct_DramControlReg_Init_D: Done
24839246.930: DIMM 0 RttWr: 2
24840246.930: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
24841246.930: mct_SendMrsCmd: Start
24842246.930: mct_SendMrsCmd: Done
24843246.930: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
24844246.930: mct_SendMrsCmd: Start
24845246.930: mct_SendMrsCmd: Done
24846246.930: DIMM 0 RttNom: 3
24847246.930: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
24848246.930: mct_SendMrsCmd: Start
24849246.930: mct_SendMrsCmd: Done
24850246.930: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
24851246.930: mct_SendMrsCmd: Start
24852246.930: mct_SendMrsCmd: Done
24853246.931: DIMM 0 RttWr: 2
24854246.930: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
24855246.931: mct_SendMrsCmd: Start
24856246.931: mct_SendMrsCmd: Done
24857246.931: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
24858246.931: mct_SendMrsCmd: Start
24859246.931: mct_SendMrsCmd: Done
24860246.931: DIMM 0 RttNom: 3
24861246.931: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
24862246.931: mct_SendMrsCmd: Start
24863246.931: mct_SendMrsCmd: Done
24864246.931: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
24865246.931: mct_SendMrsCmd: Start
24866246.931: mct_SendMrsCmd: Done
24867246.931: DIMM 1 RttWr: 2
24868246.931: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
24869246.931: mct_SendMrsCmd: Start
24870246.931: mct_SendMrsCmd: Done
24871246.931: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
24872246.931: mct_SendMrsCmd: Start
24873246.931: mct_SendMrsCmd: Done
24874246.931: DIMM 1 RttNom: 3
24875246.931: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
24876246.931: mct_SendMrsCmd: Start
24877246.931: mct_SendMrsCmd: Done
24878246.931: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
24879246.931: mct_SendMrsCmd: Start
24880246.931: mct_SendMrsCmd: Done
24881246.931: DIMM 1 RttWr: 2
24882246.931: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
24883246.931: mct_SendMrsCmd: Start
24884246.931: mct_SendMrsCmd: Done
24885246.931: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
24886246.931: mct_SendMrsCmd: Start
24887246.931: mct_SendMrsCmd: Done
24888246.931: DIMM 1 RttNom: 3
24889246.931: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
24890246.931: mct_SendMrsCmd: Start
24891246.931: mct_SendMrsCmd: Done
24892246.931: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
24893246.931: mct_SendMrsCmd: Start
24894246.931: mct_SendMrsCmd: Done
24895246.931: mct_SendZQCmd: Start
24896246.931: mct_SendZQCmd: Done
24897246.931: mct_SendZQCmd: Start
24898246.931: mct_SendZQCmd: Done
24899246.931: mct_DCTAccessDone: Start
24900246.931: mct_DCTAccessDone: Done
24901246.931: mct_DramInit_Sw_D: Done
24902246.931: <09><09>DCTFinalInit_D: StartupDCT_D Done
24903246.931: SPDCalcWidth: Status 2005
24904246.931: SPDCalcWidth: ErrStatus 0
24905246.931: SPDCalcWidth: ErrCode 0
24906246.931: SPDCalcWidth: Done
24907246.931: <09><09>DCTInit_D: mct_SPDCalcWidth Done
24908246.931: AutoCycTiming_D: Start
24909246.931: SPD2ndTiming: Start
24910246.931: SPD2ndTiming: Done
24911246.931: AutoCycTiming: Status 2005
24912246.931: AutoCycTiming: ErrStatus 0
24913246.931: AutoCycTiming: ErrCode 0
24914246.931: AutoCycTiming: Done
24915246.931:
24916246.931: <09><09>DCTInit_D: AutoCycTiming_D Done
24917246.931: <09><09>DCTInit_D: enabling intra-channel clock skew
24918246.932: SPDSetBanks: CSPresent f
24919246.932: SPDSetBanks: Status 2005
24920246.932: SPDSetBanks: ErrStatus 0
24921246.932: SPDSetBanks: ErrCode 0
24922246.932: SPDSetBanks: Done
24923246.932:
24924246.932: AfterStitch pDCTstat->NodeSysBase = 0
24925246.932: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
24926246.932: StitchMemory: Status 2005
24927246.932: StitchMemory: ErrStatus 0
24928246.932: StitchMemory: ErrCode 0
24929246.932: StitchMemory: Done
24930246.932:
24931246.932: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24932246.932: CBFS: Locating 'cmos_layout.bin'
24933246.932: CBFS: Found @ offset 2b0c0 size e88
24934246.932: InterleaveBanks_D: Status 2005
24935246.932: InterleaveBanks_D: ErrStatus 0
24936246.932: InterleaveBanks_D: ErrCode 0
24937246.932: InterleaveBanks_D: Done
24938246.932:
24939246.932: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
24940246.932: CBFS: Locating 'cmos_layout.bin'
24941246.932: CBFS: Found @ offset 2b0c0 size e88
24942246.933: AutoConfig_D: DramControl: 00002a06
24943246.933: AutoConfig_D: DramTimingLo: 00000000
24944246.933: AutoConfig_D: DramConfigMisc: 00000000
24945246.933: AutoConfig_D: DramConfigMisc2: 00000000
24946246.933: AutoConfig_D: DramConfigLo: 03083000
24947246.933: AutoConfig_D: DramConfigHi: 0f090084
24948246.933: InitDDRPhy: Start
24949246.933: InitDDRPhy: Done
24950246.933: mct_SetDramConfigHi_D: Start
24951246.933: set_2t_configuration: Start
24952246.933: set_2t_configuration: Done
24953246.933: mct_BeforePlatformSpec: Start
24954246.933: mct_BeforePlatformSpec: Done
24955246.933: mct_PlatformSpec: Start
24956246.933: Programmed DCT 1 timing/termination pattern 00000000 10222222
24957246.933: mct_PlatformSpec: Done
24958246.933: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
24959246.933: *
24960246.933: mct_SetDramConfigHi_D: Done
24961246.933: mct_EarlyArbEn_D: Start
24962246.933: mct_EarlyArbEn_D: Done
24963246.933: AutoConfig: Status 2005
24964246.933: AutoConfig: ErrStatus 0
24965246.933: AutoConfig: ErrCode 0
24966246.933: AutoConfig: Done
24967246.933:
24968246.933: <09><09>DCTInit_D: AutoConfig_D Done
24969246.933: <09><09>DCTInit_D: PlatformSpec_D Done
24970246.933: <09><09>DCTFinalInit_D: StartupDCT_D Start
24971246.933: mct_BeforeDramInit_Prod_D: Start
24972246.933: mct_ProgramODT_D: Start
24973246.933: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
24974246.933: mct_ProgramODT_D: Done
24975246.933: mct_BeforeDramInit_Prod_D: Done
24976246.933: mct_DramInit_Sw_D: Start
24977246.933: mct_DCTAccessDone: Start
24978246.933: mct_DCTAccessDone: Done
24979246.934: mct_DramControlReg_Init_D: Start
24980246.934: mct_DramControlReg_Init_D: F2xA8: 00000300
24981246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
24982246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
24983246.934: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24984246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
24985246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
24986246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
24987246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
24988246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
24989246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
24990246.934: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
24991246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
24992246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
24993246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
24994246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
24995246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
24996246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
24997246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
24998246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
24999246.934: mct_DramControlReg_Init_D: F2xA8: 00000c00
25000246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
25001246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
25002246.935: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
25003246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
25004246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
25005246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
25006246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
25007246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
25008246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
25009246.935: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
25010246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
25011246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
25012246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
25013246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
25014246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
25015246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
25016246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
25017246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
25018246.935: mct_DramControlReg_Init_D: Done
25019246.935: DIMM 0 RttWr: 2
25020246.935: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
25021246.935: mct_SendMrsCmd: Start
25022246.935: mct_SendMrsCmd: Done
25023246.935: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
25024246.935: mct_SendMrsCmd: Start
25025246.935: mct_SendMrsCmd: Done
25026246.935: DIMM 0 RttNom: 3
25027246.935: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
25028246.935: mct_SendMrsCmd: Start
25029246.935: mct_SendMrsCmd: Done
25030246.935: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
25031246.935: mct_SendMrsCmd: Start
25032246.935: mct_SendMrsCmd: Done
25033246.935: DIMM 0 RttWr: 2
25034246.935: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
25035246.935: mct_SendMrsCmd: Start
25036246.936: mct_SendMrsCmd: Done
25037246.936: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
25038246.936: mct_SendMrsCmd: Start
25039246.936: mct_SendMrsCmd: Done
25040246.936: DIMM 0 RttNom: 3
25041246.936: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
25042246.936: mct_SendMrsCmd: Start
25043246.936: mct_SendMrsCmd: Done
25044246.936: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
25045246.936: mct_SendMrsCmd: Start
25046246.936: mct_SendMrsCmd: Done
25047246.936: DIMM 1 RttWr: 2
25048246.936: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
25049246.936: mct_SendMrsCmd: Start
25050246.936: mct_SendMrsCmd: Done
25051246.936: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
25052246.936: mct_SendMrsCmd: Start
25053246.936: mct_SendMrsCmd: Done
25054246.936: DIMM 1 RttNom: 3
25055246.936: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
25056246.936: mct_SendMrsCmd: Start
25057246.936: mct_SendMrsCmd: Done
25058246.936: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
25059246.936: mct_SendMrsCmd: Start
25060246.936: mct_SendMrsCmd: Done
25061246.936: DIMM 1 RttWr: 2
25062246.936: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
25063246.936: mct_SendMrsCmd: Start
25064246.936: mct_SendMrsCmd: Done
25065246.936: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
25066246.936: mct_SendMrsCmd: Start
25067246.936: mct_SendMrsCmd: Done
25068246.936: DIMM 1 RttNom: 3
25069246.936: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
25070246.936: mct_SendMrsCmd: Start
25071246.936: mct_SendMrsCmd: Done
25072246.936: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
25073246.936: mct_SendMrsCmd: Start
25074246.936: mct_SendMrsCmd: Done
25075246.936: mct_SendZQCmd: Start
25076246.936: mct_SendZQCmd: Done
25077246.936: mct_SendZQCmd: Start
25078246.936: mct_SendZQCmd: Done
25079246.936: mct_DCTAccessDone: Start
25080246.936: mct_DCTAccessDone: Done
25081246.936: mct_DramInit_Sw_D: Done
25082246.936: <09><09>DCTFinalInit_D: StartupDCT_D Done
25083246.936: mctAutoInitMCT_D: mctSMBhub_Init
25084246.936: activate_spd_rom() for node 03
25085246.936: enable_spd_node3()
25086246.936: mctAutoInitMCT_D: mct_initDCT
25087246.936: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
25088246.936: CBFS: Locating 'cmos_layout.bin'
25089246.936: CBFS: Found @ offset 2b0c0 size e88
25090246.937: SPDCalcWidth: Status 2005
25091246.937: SPDCalcWidth: ErrStatus 0
25092246.937: SPDCalcWidth: ErrCode 0
25093246.937: SPDCalcWidth: Done
25094246.937: <09><09>DCTInit_D: mct_SPDCalcWidth Done
25095246.937: AutoCycTiming_D: Start
25096246.937: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
25097246.937: CBFS: Locating 'cmos_layout.bin'
25098246.937: CBFS: Found @ offset 2b0c0 size e88
25099246.937: GetPresetmaxF_D: Start
25100246.937: GetPresetmaxF_D: Done
25101246.937: SPDGetTCL_D: Start
25102246.937: SPDGetTCL_D: DIMMCASL 5
25103246.937: SPDGetTCL_D: DIMMAutoSpeed 4
25104246.937: SPDGetTCL_D: Status 2005
25105246.937: SPDGetTCL_D: ErrStatus 0
25106246.937: SPDGetTCL_D: ErrCode 0
25107246.937: SPDGetTCL_D: Done
25108246.937:
25109246.937: SPD2ndTiming: Start
25110246.937: SPD2ndTiming: Done
25111246.937: AutoCycTiming: Status 2005
25112246.937: AutoCycTiming: ErrStatus 0
25113246.937: AutoCycTiming: ErrCode 0
25114246.937: AutoCycTiming: Done
25115246.937:
25116246.937: <09><09>DCTInit_D: AutoCycTiming_D Done
25117246.937: SPDSetBanks: CSPresent f
25118246.937: SPDSetBanks: Status 2005
25119246.937: SPDSetBanks: ErrStatus 0
25120246.937: SPDSetBanks: ErrCode 0
25121246.937: SPDSetBanks: Done
25122246.937:
25123246.938: AfterStitch pDCTstat->NodeSysBase = 0
25124246.938: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
25125246.938: StitchMemory: Status 2005
25126246.938: StitchMemory: ErrStatus 0
25127246.938: StitchMemory: ErrCode 0
25128246.938: StitchMemory: Done
25129246.938:
25130246.938: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
25131246.938: CBFS: Locating 'cmos_layout.bin'
25132246.938: CBFS: Found @ offset 2b0c0 size e88
25133246.938: InterleaveBanks_D: Status 2005
25134246.938: InterleaveBanks_D: ErrStatus 0
25135246.938: InterleaveBanks_D: ErrCode 0
25136246.938: InterleaveBanks_D: Done
25137246.938:
25138246.938: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
25139246.938: CBFS: Locating 'cmos_layout.bin'
25140246.938: CBFS: Found @ offset 2b0c0 size e88
25141246.939: AutoConfig_D: DramControl: 00002a06
25142246.939: AutoConfig_D: DramTimingLo: 00000000
25143246.939: AutoConfig_D: DramConfigMisc: 00000000
25144246.939: AutoConfig_D: DramConfigMisc2: 00000000
25145246.939: AutoConfig_D: DramConfigLo: 03083000
25146246.939: AutoConfig_D: DramConfigHi: 0f090084
25147246.939: InitDDRPhy: Start
25148246.939: InitDDRPhy: Done
25149246.939: mct_SetDramConfigHi_D: Start
25150246.939: set_2t_configuration: Start
25151246.939: set_2t_configuration: Done
25152246.939: mct_BeforePlatformSpec: Start
25153246.939: mct_BeforePlatformSpec: Done
25154246.939: mct_PlatformSpec: Start
25155246.939: Programmed DCT 0 timing/termination pattern 00000000 10222222
25156246.939: mct_PlatformSpec: Done
25157246.939: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
25158246.939: *
25159246.939: mct_SetDramConfigHi_D: Done
25160246.939: mct_EarlyArbEn_D: Start
25161246.939: mct_EarlyArbEn_D: Done
25162246.939: AutoConfig: Status 2005
25163246.939: AutoConfig: ErrStatus 0
25164246.939: AutoConfig: ErrCode 0
25165246.939: AutoConfig: Done
25166246.939:
25167246.939: <09><09>DCTInit_D: AutoConfig_D Done
25168246.939: <09><09>DCTInit_D: PlatformSpec_D Done
25169246.939: <09><09>DCTFinalInit_D: StartupDCT_D Start
25170246.939: mct_BeforeDramInit_Prod_D: Start
25171246.939: mct_ProgramODT_D: Start
25172246.939: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
25173246.939: mct_ProgramODT_D: Done
25174246.939: mct_BeforeDramInit_Prod_D: Done
25175246.939: mct_DramInit_Sw_D: Start
25176246.939: mct_DCTAccessDone: Start
25177246.939: mct_DCTAccessDone: Done
25178246.940: mct_DramControlReg_Init_D: Start
25179246.940: mct_DramControlReg_Init_D: F2xA8: 00000300
25180246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
25181246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
25182246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
25183246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
25184246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
25185246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
25186246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
25187246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
25188246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
25189246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
25190246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
25191246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
25192246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
25193246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
25194246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
25195246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
25196246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
25197246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
25198246.940: mct_DramControlReg_Init_D: F2xA8: 00000c00
25199246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
25200246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
25201246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
25202246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
25203246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
25204246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
25205246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
25206246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
25207246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
25208246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
25209246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
25210246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
25211246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
25212246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
25213246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
25214246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
25215246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
25216246.941: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
25217246.941: mct_DramControlReg_Init_D: Done
25218246.941: DIMM 0 RttWr: 2
25219246.941: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25220246.941: mct_SendMrsCmd: Start
25221246.941: mct_SendMrsCmd: Done
25222246.941: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
25223246.941: mct_SendMrsCmd: Start
25224246.941: mct_SendMrsCmd: Done
25225246.941: DIMM 0 RttNom: 3
25226246.941: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25227246.941: mct_SendMrsCmd: Start
25228246.941: mct_SendMrsCmd: Done
25229246.941: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
25230246.941: mct_SendMrsCmd: Start
25231246.941: mct_SendMrsCmd: Done
25232246.941: DIMM 0 RttWr: 2
25233246.941: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25234246.941: mct_SendMrsCmd: Start
25235246.941: mct_SendMrsCmd: Done
25236246.941: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
25237246.941: mct_SendMrsCmd: Start
25238246.941: mct_SendMrsCmd: Done
25239246.941: DIMM 0 RttNom: 3
25240246.941: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25241246.941: mct_SendMrsCmd: Start
25242246.941: mct_SendMrsCmd: Done
25243246.941: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
25244246.941: mct_SendMrsCmd: Start
25245246.941: mct_SendMrsCmd: Done
25246246.941: DIMM 1 RttWr: 2
25247246.941: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25248246.941: mct_SendMrsCmd: Start
25249246.942: mct_SendMrsCmd: Done
25250246.942: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
25251246.942: mct_SendMrsCmd: Start
25252246.942: mct_SendMrsCmd: Done
25253246.942: DIMM 1 RttNom: 3
25254246.942: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25255246.942: mct_SendMrsCmd: Start
25256246.942: mct_SendMrsCmd: Done
25257246.942: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
25258246.942: mct_SendMrsCmd: Start
25259246.942: mct_SendMrsCmd: Done
25260246.942: DIMM 1 RttWr: 2
25261246.942: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25262246.942: mct_SendMrsCmd: Start
25263246.942: mct_SendMrsCmd: Done
25264246.942: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
25265246.942: mct_SendMrsCmd: Start
25266246.942: mct_SendMrsCmd: Done
25267246.942: DIMM 1 RttNom: 3
25268246.942: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25269246.942: mct_SendMrsCmd: Start
25270246.942: mct_SendMrsCmd: Done
25271246.942: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
25272246.942: mct_SendMrsCmd: Start
25273246.942: mct_SendMrsCmd: Done
25274246.942: mct_SendZQCmd: Start
25275246.942: mct_SendZQCmd: Done
25276246.942: mct_SendZQCmd: Start
25277246.942: mct_SendZQCmd: Done
25278246.942: mct_DCTAccessDone: Start
25279246.942: mct_DCTAccessDone: Done
25280246.942: mct_DramInit_Sw_D: Done
25281246.942: <09><09>DCTFinalInit_D: StartupDCT_D Done
25282246.942: SPDCalcWidth: Status 2005
25283246.942: SPDCalcWidth: ErrStatus 0
25284246.942: SPDCalcWidth: ErrCode 0
25285246.942: SPDCalcWidth: Done
25286246.942: <09><09>DCTInit_D: mct_SPDCalcWidth Done
25287246.942: AutoCycTiming_D: Start
25288246.942: SPD2ndTiming: Start
25289246.942: SPD2ndTiming: Done
25290246.942: AutoCycTiming: Status 2005
25291246.942: AutoCycTiming: ErrStatus 0
25292246.942: AutoCycTiming: ErrCode 0
25293246.942: AutoCycTiming: Done
25294246.942:
25295246.942: <09><09>DCTInit_D: AutoCycTiming_D Done
25296246.942: <09><09>DCTInit_D: enabling intra-channel clock skew
25297246.942: SPDSetBanks: CSPresent f
25298246.942: SPDSetBanks: Status 2005
25299246.942: SPDSetBanks: ErrStatus 0
25300246.942: SPDSetBanks: ErrCode 0
25301246.942: SPDSetBanks: Done
25302246.942:
25303246.943: AfterStitch pDCTstat->NodeSysBase = 0
25304246.943: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
25305246.943: StitchMemory: Status 2005
25306246.943: StitchMemory: ErrStatus 0
25307246.943: StitchMemory: ErrCode 0
25308246.943: StitchMemory: Done
25309246.943:
25310246.943: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
25311246.943: CBFS: Locating 'cmos_layout.bin'
25312246.943: CBFS: Found @ offset 2b0c0 size e88
25313246.943: InterleaveBanks_D: Status 2005
25314246.943: InterleaveBanks_D: ErrStatus 0
25315246.943: InterleaveBanks_D: ErrCode 0
25316246.943: InterleaveBanks_D: Done
25317246.943:
25318246.944: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
25319246.943: CBFS: Locating 'cmos_layout.bin'
25320246.943: CBFS: Found @ offset 2b0c0 size e88
25321246.944: AutoConfig_D: DramControl: 00002a06
25322246.944: AutoConfig_D: DramTimingLo: 00000000
25323246.944: AutoConfig_D: DramConfigMisc: 00000000
25324246.944: AutoConfig_D: DramConfigMisc2: 00000000
25325246.944: AutoConfig_D: DramConfigLo: 03083000
25326246.944: AutoConfig_D: DramConfigHi: 0f090084
25327246.944: InitDDRPhy: Start
25328246.944: InitDDRPhy: Done
25329246.944: mct_SetDramConfigHi_D: Start
25330246.944: set_2t_configuration: Start
25331246.944: set_2t_configuration: Done
25332246.944: mct_BeforePlatformSpec: Start
25333246.944: mct_BeforePlatformSpec: Done
25334246.944: mct_PlatformSpec: Start
25335246.944: Programmed DCT 1 timing/termination pattern 00000000 10222222
25336246.944: mct_PlatformSpec: Done
25337246.944: mct_SetDramConfigHi_D: DramConfigHi: 0f090084
25338246.944: *
25339246.944: mct_SetDramConfigHi_D: Done
25340246.944: mct_EarlyArbEn_D: Start
25341246.944: mct_EarlyArbEn_D: Done
25342246.944: AutoConfig: Status 2005
25343246.944: AutoConfig: ErrStatus 0
25344246.944: AutoConfig: ErrCode 0
25345246.944: AutoConfig: Done
25346246.944:
25347246.944: <09><09>DCTInit_D: AutoConfig_D Done
25348246.944: <09><09>DCTInit_D: PlatformSpec_D Done
25349246.944: <09><09>DCTFinalInit_D: StartupDCT_D Start
25350246.944: mct_BeforeDramInit_Prod_D: Start
25351246.944: mct_ProgramODT_D: Start
25352246.944: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
25353246.944: mct_ProgramODT_D: Done
25354246.944: mct_BeforeDramInit_Prod_D: Done
25355246.944: mct_DramInit_Sw_D: Start
25356246.944: mct_DCTAccessDone: Start
25357246.944: mct_DCTAccessDone: Done
25358246.945: mct_DramControlReg_Init_D: Start
25359246.945: mct_DramControlReg_Init_D: F2xA8: 00000300
25360246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
25361246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
25362246.945: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
25363246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
25364246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
25365246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
25366246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
25367246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
25368246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
25369246.945: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
25370246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
25371246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
25372246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
25373246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
25374246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
25375246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
25376246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
25377246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
25378246.945: mct_DramControlReg_Init_D: F2xA8: 00000c00
25379246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
25380246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
25381246.946: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
25382246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
25383246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
25384246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
25385246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
25386246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
25387246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
25388246.946: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
25389246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
25390246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
25391246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
25392246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
25393246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
25394246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
25395246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
25396246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
25397246.946: mct_DramControlReg_Init_D: Done
25398246.946: DIMM 0 RttWr: 2
25399246.946: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
25400246.946: mct_SendMrsCmd: Start
25401246.946: mct_SendMrsCmd: Done
25402246.946: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
25403246.946: mct_SendMrsCmd: Start
25404246.946: mct_SendMrsCmd: Done
25405246.946: DIMM 0 RttNom: 3
25406246.946: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
25407246.946: mct_SendMrsCmd: Start
25408246.946: mct_SendMrsCmd: Done
25409246.946: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
25410246.946: mct_SendMrsCmd: Start
25411246.946: mct_SendMrsCmd: Done
25412246.946: DIMM 0 RttWr: 2
25413246.946: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
25414246.946: mct_SendMrsCmd: Start
25415246.946: mct_SendMrsCmd: Done
25416246.946: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
25417246.946: mct_SendMrsCmd: Start
25418246.946: mct_SendMrsCmd: Done
25419246.946: DIMM 0 RttNom: 3
25420246.946: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
25421246.946: mct_SendMrsCmd: Start
25422246.947: mct_SendMrsCmd: Done
25423246.947: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
25424246.947: mct_SendMrsCmd: Start
25425246.947: mct_SendMrsCmd: Done
25426246.947: DIMM 1 RttWr: 2
25427246.947: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
25428246.947: mct_SendMrsCmd: Start
25429246.947: mct_SendMrsCmd: Done
25430246.947: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
25431246.947: mct_SendMrsCmd: Start
25432246.947: mct_SendMrsCmd: Done
25433246.947: DIMM 1 RttNom: 3
25434246.947: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
25435246.947: mct_SendMrsCmd: Start
25436246.947: mct_SendMrsCmd: Done
25437246.947: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
25438246.947: mct_SendMrsCmd: Start
25439246.947: mct_SendMrsCmd: Done
25440246.947: DIMM 1 RttWr: 2
25441246.947: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
25442246.947: mct_SendMrsCmd: Start
25443246.947: mct_SendMrsCmd: Done
25444246.947: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
25445246.947: mct_SendMrsCmd: Start
25446246.947: mct_SendMrsCmd: Done
25447246.947: DIMM 1 RttNom: 3
25448246.947: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
25449246.947: mct_SendMrsCmd: Start
25450246.947: mct_SendMrsCmd: Done
25451246.947: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
25452246.947: mct_SendMrsCmd: Start
25453246.947: mct_SendMrsCmd: Done
25454246.947: mct_SendZQCmd: Start
25455246.947: mct_SendZQCmd: Done
25456246.947: mct_SendZQCmd: Start
25457246.947: mct_SendZQCmd: Done
25458246.947: mct_DCTAccessDone: Start
25459246.947: mct_DCTAccessDone: Done
25460246.947: mct_DramInit_Sw_D: Done
25461246.947: <09><09>DCTFinalInit_D: StartupDCT_D Done
25462246.947: mctAutoInitMCT_D: SyncDCTsReady_D
25463246.947: mctAutoInitMCT_D: HTMemMapInit_D
25464246.947: Node: 00 base: 00 limit: fffffff BottomIO: c00000
25465246.947: Node: 00 base: 03 limit: 103fffff
25466246.948: Node: 01 base: 10400000 limit: 203fffff BottomIO: c00000
25467246.948: Node: 01 base: 10400003 limit: 203fffff
25468246.948: Node: 02 base: 20400000 limit: 303fffff BottomIO: c00000
25469246.948: Node: 02 base: 20400003 limit: 303fffff
25470246.948: Node: 03 base: 30400000 limit: 403fffff BottomIO: c00000
25471246.948: Node: 03 base: 30400003 limit: 403fffff
25472246.948: Node: 04 base: 00 limit: 00
25473246.948: Node: 05 base: 00 limit: 00
25474246.948: Node: 06 base: 00 limit: 00
25475246.948: Node: 07 base: 00 limit: 00
25476246.948: Copy dram map from Node 0 to Node 01
25477246.948: Copy dram map from Node 0 to Node 02
25478246.948: Copy dram map from Node 0 to Node 03
25479246.948: mctAutoInitMCT_D: mctHookAfterCPU
25480246.948: mctAutoInitMCT_D: DQSTiming_D
25481246.948: phyAssistedMemFnceTraining: Start
25482246.948: phyAssistedMemFnceTraining: training node 0 DCT 0
25483246.949: phyAssistedMemFnceTraining: done training node 0 DCT 0
25484246.949: phyAssistedMemFnceTraining: training node 0 DCT 1
25485246.949: phyAssistedMemFnceTraining: done training node 0 DCT 1
25486246.949: phyAssistedMemFnceTraining: training node 1 DCT 0
25487246.949: phyAssistedMemFnceTraining: done training node 1 DCT 0
25488246.949: phyAssistedMemFnceTraining: training node 1 DCT 1
25489246.949: phyAssistedMemFnceTraining: done training node 1 DCT 1
25490246.949: phyAssistedMemFnceTraining: training node 2 DCT 0
25491246.949: phyAssistedMemFnceTraining: done training node 2 DCT 0
25492246.949: phyAssistedMemFnceTraining: training node 2 DCT 1
25493246.949: phyAssistedMemFnceTraining: done training node 2 DCT 1
25494246.949: phyAssistedMemFnceTraining: training node 3 DCT 0
25495246.949: phyAssistedMemFnceTraining: done training node 3 DCT 0
25496246.950: phyAssistedMemFnceTraining: training node 3 DCT 1
25497246.950: phyAssistedMemFnceTraining: done training node 3 DCT 1
25498246.950: phyAssistedMemFnceTraining: Done
25499246.950: InitPhyCompensation: DCT 0: Start
25500246.951: Waiting for predriver calibration to be applied...done!
25501246.951: InitPhyCompensation: DCT 0: Done
25502246.951: InitPhyCompensation: DCT 1: Start
25503246.951: Waiting for predriver calibration to be applied...done!
25504246.951: InitPhyCompensation: DCT 1: Done
25505246.951: InitPhyCompensation: DCT 0: Start
25506246.951: Waiting for predriver calibration to be applied...done!
25507246.951: InitPhyCompensation: DCT 0: Done
25508246.951: InitPhyCompensation: DCT 1: Start
25509246.951: Waiting for predriver calibration to be applied...done!
25510246.951: InitPhyCompensation: DCT 1: Done
25511246.951: InitPhyCompensation: DCT 0: Start
25512246.951: Waiting for predriver calibration to be applied...done!
25513246.951: InitPhyCompensation: DCT 0: Done
25514246.951: InitPhyCompensation: DCT 1: Start
25515246.951: Waiting for predriver calibration to be applied...done!
25516246.951: InitPhyCompensation: DCT 1: Done
25517246.951: InitPhyCompensation: DCT 0: Start
25518246.951: Waiting for predriver calibration to be applied...done!
25519246.951: InitPhyCompensation: DCT 0: Done
25520246.951: InitPhyCompensation: DCT 1: Start
25521246.951: Waiting for predriver calibration to be applied...done!
25522246.952: InitPhyCompensation: DCT 1: Done
25523246.952: activate_spd_rom() for node 00
25524246.952: enable_spd_node0()
25525246.954: AgesaHwWlPhase1: training nibble 0
25526246.954: DIMM 0 RttNom: 3
25527246.954: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25528246.954: DIMM 0 RttWr: 2
25529246.954: DIMM 0 RttWr: 2
25530246.954: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25531246.954: DIMM 0 RttWr: 2
25532246.954: DIMM 0 RttNom: 3
25533246.954: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25534246.954: DIMM 0 RttNom: 3
25535246.954: DIMM 0 RttWr: 2
25536246.954: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25537246.954: DIMM 0 RttWr: 2
25538246.955: DIMM 1 RttNom: 3
25539246.955: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25540246.955: DIMM 0 RttNom: 3
25541246.955: DIMM 1 RttWr: 2
25542246.955: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25543246.955: DIMM 0 RttWr: 2
25544246.955: DIMM 1 RttNom: 3
25545246.955: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25546246.955: DIMM 0 RttNom: 3
25547246.955: DIMM 1 RttWr: 2
25548246.955: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25549246.955: DIMM 0 RttWr: 2
25550246.956: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
25551246.956: <09>Lane 00 initial seed: 0041
25552246.956: <09>Lane 01 initial seed: 0041
25553246.956: <09>Lane 02 initial seed: 0041
25554246.956: <09>Lane 03 initial seed: 0041
25555246.956: <09>Lane 04 initial seed: 0041
25556246.956: <09>Lane 05 initial seed: 0041
25557246.956: <09>Lane 06 initial seed: 0041
25558246.956: <09>Lane 07 initial seed: 0041
25559246.956: <09>Lane 08 initial seed: 0041
25560246.957: <09>Lane 00 nibble 0 raw readback: 004d
25561246.957: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
25562246.957: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
25563246.957: <09>Lane 01 nibble 0 raw readback: 0047
25564246.957: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
25565246.957: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
25566246.957: <09>Lane 02 nibble 0 raw readback: 0045
25567246.957: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
25568246.957: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
25569246.957: <09>Lane 03 nibble 0 raw readback: 0042
25570246.957: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
25571246.957: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
25572246.957: <09>Lane 04 nibble 0 raw readback: 003a
25573246.957: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
25574246.957: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
25575246.957: <09>Lane 05 nibble 0 raw readback: 003d
25576246.957: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
25577246.957: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
25578246.957: <09>Lane 06 nibble 0 raw readback: 0040
25579246.957: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
25580246.957: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
25581246.957: <09>Lane 07 nibble 0 raw readback: 0041
25582246.957: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
25583246.957: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
25584246.957: <09>Lane 08 nibble 0 raw readback: 003b
25585246.957: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
25586246.957: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
25587246.957: AgesaHwWlPhase1: training nibble 1
25588246.957: DIMM 0 RttNom: 3
25589246.957: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25590246.957: DIMM 0 RttWr: 2
25591246.957: DIMM 0 RttWr: 2
25592246.957: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25593246.957: DIMM 0 RttWr: 2
25594246.957: DIMM 0 RttNom: 3
25595246.957: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25596246.957: DIMM 0 RttNom: 3
25597246.957: DIMM 0 RttWr: 2
25598246.957: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25599246.957: DIMM 0 RttWr: 2
25600246.957: DIMM 1 RttNom: 3
25601246.957: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25602246.957: DIMM 0 RttNom: 3
25603246.957: DIMM 1 RttWr: 2
25604246.957: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25605246.957: DIMM 0 RttWr: 2
25606246.957: DIMM 1 RttNom: 3
25607246.957: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25608246.957: DIMM 0 RttNom: 3
25609246.957: DIMM 1 RttWr: 2
25610246.957: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25611246.957: DIMM 0 RttWr: 2
25612246.957: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
25613246.957: <09>Lane 00 initial seed: 0041
25614246.958: <09>Lane 01 initial seed: 0041
25615246.958: <09>Lane 02 initial seed: 0041
25616246.958: <09>Lane 03 initial seed: 0041
25617246.958: <09>Lane 04 initial seed: 0041
25618246.958: <09>Lane 05 initial seed: 0041
25619246.958: <09>Lane 06 initial seed: 0041
25620246.958: <09>Lane 07 initial seed: 0041
25621246.958: <09>Lane 08 initial seed: 0041
25622246.958: <09>Lane 00 nibble 1 raw readback: 004c
25623246.958: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004c
25624246.958: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
25625246.958: <09>Lane 01 nibble 1 raw readback: 0047
25626246.958: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
25627246.958: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
25628246.958: <09>Lane 02 nibble 1 raw readback: 0046
25629246.958: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
25630246.958: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
25631246.958: <09>Lane 03 nibble 1 raw readback: 0043
25632246.958: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
25633246.958: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
25634246.958: <09>Lane 04 nibble 1 raw readback: 003a
25635246.958: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
25636246.958: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
25637246.958: <09>Lane 05 nibble 1 raw readback: 003d
25638246.958: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
25639246.958: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
25640246.958: <09>Lane 06 nibble 1 raw readback: 0040
25641246.958: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
25642246.958: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
25643246.958: <09>Lane 07 nibble 1 raw readback: 0041
25644246.958: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
25645246.958: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
25646246.958: <09>Lane 08 nibble 1 raw readback: 003b
25647246.958: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
25648246.958: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
25649246.958: <09>original critical gross delay: 0
25650246.958: <09>new critical gross delay: 0
25651246.958: DIMM 0 RttNom: 3
25652246.958: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25653246.958: DIMM 0 RttNom: 3
25654246.958: DIMM 0 RttWr: 2
25655246.958: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25656246.958: DIMM 0 RttWr: 2
25657246.958: DIMM 0 RttNom: 3
25658246.958: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25659246.958: DIMM 0 RttNom: 3
25660246.958: DIMM 0 RttWr: 2
25661246.958: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25662246.959: DIMM 0 RttWr: 2
25663246.959: DIMM 1 RttNom: 3
25664246.959: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25665246.959: DIMM 0 RttNom: 3
25666246.959: DIMM 1 RttWr: 2
25667246.959: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25668246.959: DIMM 0 RttWr: 2
25669246.959: DIMM 1 RttNom: 3
25670246.959: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25671246.959: DIMM 0 RttNom: 3
25672246.959: DIMM 1 RttWr: 2
25673246.959: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25674246.959: DIMM 0 RttWr: 2
25675246.959: AgesaHwWlPhase1: training nibble 0
25676246.959: DIMM 1 RttNom: 3
25677246.959: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25678246.959: DIMM 1 RttWr: 2
25679246.959: DIMM 1 RttWr: 2
25680246.959: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25681246.959: DIMM 1 RttWr: 2
25682246.959: DIMM 1 RttNom: 3
25683246.959: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25684246.959: DIMM 1 RttNom: 3
25685246.959: DIMM 1 RttWr: 2
25686246.959: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25687246.959: DIMM 1 RttWr: 2
25688246.959: DIMM 0 RttNom: 3
25689246.959: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25690246.959: DIMM 1 RttNom: 3
25691246.959: DIMM 0 RttWr: 2
25692246.959: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25693246.959: DIMM 1 RttWr: 2
25694246.959: DIMM 0 RttNom: 3
25695246.959: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25696246.959: DIMM 1 RttNom: 3
25697246.959: DIMM 0 RttWr: 2
25698246.959: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25699246.959: DIMM 1 RttWr: 2
25700246.959: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
25701246.959: <09>Lane 00 initial seed: 0041
25702246.959: <09>Lane 01 initial seed: 0041
25703246.959: <09>Lane 02 initial seed: 0041
25704246.959: <09>Lane 03 initial seed: 0041
25705246.959: <09>Lane 04 initial seed: 0041
25706246.959: <09>Lane 05 initial seed: 0041
25707246.959: <09>Lane 06 initial seed: 0041
25708246.959: <09>Lane 07 initial seed: 0041
25709246.959: <09>Lane 08 initial seed: 0041
25710246.959: <09>Lane 00 nibble 0 raw readback: 003f
25711246.959: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
25712246.959: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
25713246.959: <09>Lane 01 nibble 0 raw readback: 003a
25714246.959: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003a
25715246.959: <09>Lane 01 nibble 0 adjusted value (post nibble): 003a
25716246.959: <09>Lane 02 nibble 0 raw readback: 0038
25717246.959: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
25718246.959: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
25719246.959: <09>Lane 03 nibble 0 raw readback: 0035
25720246.959: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0035
25721246.959: <09>Lane 03 nibble 0 adjusted value (post nibble): 0035
25722246.959: <09>Lane 04 nibble 0 raw readback: 002f
25723246.959: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
25724246.959: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
25725246.959: <09>Lane 05 nibble 0 raw readback: 0031
25726246.959: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0031
25727246.959: <09>Lane 05 nibble 0 adjusted value (post nibble): 0031
25728246.959: <09>Lane 06 nibble 0 raw readback: 0033
25729246.959: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
25730246.959: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
25731246.959: <09>Lane 07 nibble 0 raw readback: 0036
25732246.959: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
25733246.959: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
25734246.959: <09>Lane 08 nibble 0 raw readback: 002f
25735246.960: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
25736246.960: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
25737246.960: AgesaHwWlPhase1: training nibble 1
25738246.960: DIMM 1 RttNom: 3
25739246.960: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25740246.960: DIMM 1 RttWr: 2
25741246.960: DIMM 1 RttWr: 2
25742246.960: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25743246.960: DIMM 1 RttWr: 2
25744246.960: DIMM 1 RttNom: 3
25745246.960: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25746246.960: DIMM 1 RttNom: 3
25747246.960: DIMM 1 RttWr: 2
25748246.960: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25749246.960: DIMM 1 RttWr: 2
25750246.960: DIMM 0 RttNom: 3
25751246.960: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25752246.960: DIMM 1 RttNom: 3
25753246.960: DIMM 0 RttWr: 2
25754246.960: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25755246.960: DIMM 1 RttWr: 2
25756246.960: DIMM 0 RttNom: 3
25757246.960: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25758246.960: DIMM 1 RttNom: 3
25759246.960: DIMM 0 RttWr: 2
25760246.960: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25761246.960: DIMM 1 RttWr: 2
25762246.960: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
25763246.960: <09>Lane 00 initial seed: 0041
25764246.960: <09>Lane 01 initial seed: 0041
25765246.960: <09>Lane 02 initial seed: 0041
25766246.960: <09>Lane 03 initial seed: 0041
25767246.960: <09>Lane 04 initial seed: 0041
25768246.960: <09>Lane 05 initial seed: 0041
25769246.960: <09>Lane 06 initial seed: 0041
25770246.960: <09>Lane 07 initial seed: 0041
25771246.960: <09>Lane 08 initial seed: 0041
25772246.960: <09>Lane 00 nibble 1 raw readback: 0040
25773246.960: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0040
25774246.960: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
25775246.960: <09>Lane 01 nibble 1 raw readback: 003b
25776246.960: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003b
25777246.960: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
25778246.960: <09>Lane 02 nibble 1 raw readback: 0039
25779246.960: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
25780246.960: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
25781246.960: <09>Lane 03 nibble 1 raw readback: 0037
25782246.960: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
25783246.960: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
25784246.960: <09>Lane 04 nibble 1 raw readback: 002e
25785246.960: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
25786246.960: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
25787246.960: <09>Lane 05 nibble 1 raw readback: 0032
25788246.960: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
25789246.960: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
25790246.960: <09>Lane 06 nibble 1 raw readback: 0034
25791246.960: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0034
25792246.960: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
25793246.960: <09>Lane 07 nibble 1 raw readback: 0036
25794246.960: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
25795246.960: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
25796246.960: <09>Lane 08 nibble 1 raw readback: 002f
25797246.960: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
25798246.960: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
25799246.960: <09>original critical gross delay: 0
25800246.960: <09>new critical gross delay: 0
25801246.961: DIMM 1 RttNom: 3
25802246.961: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
25803246.961: DIMM 1 RttNom: 3
25804246.961: DIMM 1 RttWr: 2
25805246.961: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
25806246.961: DIMM 1 RttWr: 2
25807246.961: DIMM 1 RttNom: 3
25808246.961: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
25809246.961: DIMM 1 RttNom: 3
25810246.961: DIMM 1 RttWr: 2
25811246.961: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
25812246.961: DIMM 1 RttWr: 2
25813246.961: DIMM 0 RttNom: 3
25814246.961: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
25815246.961: DIMM 1 RttNom: 3
25816246.961: DIMM 0 RttWr: 2
25817246.961: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
25818246.961: DIMM 1 RttWr: 2
25819246.961: DIMM 0 RttNom: 3
25820246.961: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
25821246.961: DIMM 1 RttNom: 3
25822246.961: DIMM 0 RttWr: 2
25823246.961: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
25824246.961: DIMM 1 RttWr: 2
25825246.961: AgesaHwWlPhase1: training nibble 0
25826246.961: DIMM 0 RttNom: 3
25827246.961: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
25828246.961: DIMM 0 RttWr: 2
25829246.961: DIMM 0 RttWr: 2
25830246.961: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
25831246.961: DIMM 0 RttWr: 2
25832246.961: DIMM 0 RttNom: 3
25833246.961: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
25834246.961: DIMM 0 RttNom: 3
25835246.961: DIMM 0 RttWr: 2
25836246.961: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
25837246.961: DIMM 0 RttWr: 2
25838246.961: DIMM 1 RttNom: 3
25839246.961: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
25840246.961: DIMM 0 RttNom: 3
25841246.961: DIMM 1 RttWr: 2
25842246.961: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
25843246.961: DIMM 0 RttWr: 2
25844246.961: DIMM 1 RttNom: 3
25845246.961: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
25846246.961: DIMM 0 RttNom: 3
25847246.961: DIMM 1 RttWr: 2
25848246.961: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
25849246.961: DIMM 0 RttWr: 2
25850246.961: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
25851246.961: <09>Lane 00 initial seed: 0041
25852246.961: <09>Lane 01 initial seed: 0041
25853246.961: <09>Lane 02 initial seed: 0041
25854246.961: <09>Lane 03 initial seed: 0041
25855246.961: <09>Lane 04 initial seed: 0041
25856246.961: <09>Lane 05 initial seed: 0041
25857246.961: <09>Lane 06 initial seed: 0041
25858246.961: <09>Lane 07 initial seed: 0041
25859246.961: <09>Lane 08 initial seed: 0041
25860246.961: <09>Lane 00 nibble 0 raw readback: 0049
25861246.961: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0049
25862246.961: <09>Lane 00 nibble 0 adjusted value (post nibble): 0049
25863246.961: <09>Lane 01 nibble 0 raw readback: 0046
25864246.961: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0046
25865246.962: <09>Lane 01 nibble 0 adjusted value (post nibble): 0046
25866246.961: <09>Lane 02 nibble 0 raw readback: 0043
25867246.962: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
25868246.962: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
25869246.962: <09>Lane 03 nibble 0 raw readback: 0040
25870246.962: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0040
25871246.962: <09>Lane 03 nibble 0 adjusted value (post nibble): 0040
25872246.962: <09>Lane 04 nibble 0 raw readback: 0039
25873246.962: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
25874246.962: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
25875246.962: <09>Lane 05 nibble 0 raw readback: 003b
25876246.962: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
25877246.962: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
25878246.962: <09>Lane 06 nibble 0 raw readback: 003d
25879246.962: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
25880246.962: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
25881246.962: <09>Lane 07 nibble 0 raw readback: 003f
25882246.962: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
25883246.962: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
25884246.962: <09>Lane 08 nibble 0 raw readback: 003a
25885246.962: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
25886246.962: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
25887246.962: AgesaHwWlPhase1: training nibble 1
25888246.962: DIMM 0 RttNom: 3
25889246.962: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
25890246.962: DIMM 0 RttWr: 2
25891246.962: DIMM 0 RttWr: 2
25892246.962: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
25893246.962: DIMM 0 RttWr: 2
25894246.962: DIMM 0 RttNom: 3
25895246.962: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
25896246.962: DIMM 0 RttNom: 3
25897246.962: DIMM 0 RttWr: 2
25898246.962: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
25899246.962: DIMM 0 RttWr: 2
25900246.962: DIMM 1 RttNom: 3
25901246.962: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
25902246.962: DIMM 0 RttNom: 3
25903246.962: DIMM 1 RttWr: 2
25904246.962: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
25905246.962: DIMM 0 RttWr: 2
25906246.962: DIMM 1 RttNom: 3
25907246.962: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
25908246.962: DIMM 0 RttNom: 3
25909246.962: DIMM 1 RttWr: 2
25910246.962: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
25911246.962: DIMM 0 RttWr: 2
25912246.962: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
25913246.962: <09>Lane 00 initial seed: 0041
25914246.962: <09>Lane 01 initial seed: 0041
25915246.962: <09>Lane 02 initial seed: 0041
25916246.962: <09>Lane 03 initial seed: 0041
25917246.962: <09>Lane 04 initial seed: 0041
25918246.962: <09>Lane 05 initial seed: 0041
25919246.962: <09>Lane 06 initial seed: 0041
25920246.962: <09>Lane 07 initial seed: 0041
25921246.962: <09>Lane 08 initial seed: 0041
25922246.962: <09>Lane 00 nibble 1 raw readback: 0049
25923246.962: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0049
25924246.962: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
25925246.962: <09>Lane 01 nibble 1 raw readback: 0045
25926246.962: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0045
25927246.962: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
25928246.962: <09>Lane 02 nibble 1 raw readback: 0043
25929246.962: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0043
25930246.962: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
25931246.962: <09>Lane 03 nibble 1 raw readback: 0041
25932246.962: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0041
25933246.962: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
25934246.962: <09>Lane 04 nibble 1 raw readback: 0038
25935246.962: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
25936246.962: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
25937246.962: <09>Lane 05 nibble 1 raw readback: 003a
25938246.962: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
25939246.962: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
25940246.962: <09>Lane 06 nibble 1 raw readback: 003e
25941246.962: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
25942246.962: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
25943246.962: <09>Lane 07 nibble 1 raw readback: 003f
25944246.962: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
25945246.962: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
25946246.962: <09>Lane 08 nibble 1 raw readback: 003a
25947246.963: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
25948246.963: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
25949246.963: <09>original critical gross delay: 0
25950246.963: <09>new critical gross delay: 0
25951246.963: DIMM 0 RttNom: 3
25952246.963: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
25953246.963: DIMM 0 RttNom: 3
25954246.963: DIMM 0 RttWr: 2
25955246.963: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
25956246.963: DIMM 0 RttWr: 2
25957246.963: DIMM 0 RttNom: 3
25958246.963: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
25959246.963: DIMM 0 RttNom: 3
25960246.963: DIMM 0 RttWr: 2
25961246.963: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
25962246.963: DIMM 0 RttWr: 2
25963246.963: DIMM 1 RttNom: 3
25964246.963: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
25965246.963: DIMM 0 RttNom: 3
25966246.963: DIMM 1 RttWr: 2
25967246.963: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
25968246.963: DIMM 0 RttWr: 2
25969246.963: DIMM 1 RttNom: 3
25970246.963: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
25971246.963: DIMM 0 RttNom: 3
25972246.963: DIMM 1 RttWr: 2
25973246.963: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
25974246.963: DIMM 0 RttWr: 2
25975246.963: AgesaHwWlPhase1: training nibble 0
25976246.963: DIMM 1 RttNom: 3
25977246.963: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
25978246.963: DIMM 1 RttWr: 2
25979246.963: DIMM 1 RttWr: 2
25980246.963: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
25981246.963: DIMM 1 RttWr: 2
25982246.963: DIMM 1 RttNom: 3
25983246.963: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
25984246.963: DIMM 1 RttNom: 3
25985246.963: DIMM 1 RttWr: 2
25986246.963: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
25987246.963: DIMM 1 RttWr: 2
25988246.963: DIMM 0 RttNom: 3
25989246.963: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
25990246.963: DIMM 1 RttNom: 3
25991246.963: DIMM 0 RttWr: 2
25992246.963: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
25993246.963: DIMM 1 RttWr: 2
25994246.963: DIMM 0 RttNom: 3
25995246.963: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
25996246.963: DIMM 1 RttNom: 3
25997246.963: DIMM 0 RttWr: 2
25998246.963: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
25999246.963: DIMM 1 RttWr: 2
26000246.963: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
26001246.963: <09>Lane 00 initial seed: 0041
26002246.963: <09>Lane 01 initial seed: 0041
26003246.963: <09>Lane 02 initial seed: 0041
26004246.963: <09>Lane 03 initial seed: 0041
26005246.964: <09>Lane 04 initial seed: 0041
26006246.963: <09>Lane 05 initial seed: 0041
26007246.963: <09>Lane 06 initial seed: 0041
26008246.963: <09>Lane 07 initial seed: 0041
26009246.963: <09>Lane 08 initial seed: 0041
26010246.964: <09>Lane 00 nibble 0 raw readback: 003f
26011246.964: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
26012246.964: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
26013246.964: <09>Lane 01 nibble 0 raw readback: 003d
26014246.964: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003d
26015246.964: <09>Lane 01 nibble 0 adjusted value (post nibble): 003d
26016246.964: <09>Lane 02 nibble 0 raw readback: 0039
26017246.964: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
26018246.964: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
26019246.964: <09>Lane 03 nibble 0 raw readback: 0037
26020246.964: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0037
26021246.964: <09>Lane 03 nibble 0 adjusted value (post nibble): 0037
26022246.964: <09>Lane 04 nibble 0 raw readback: 002e
26023246.964: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
26024246.964: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
26025246.964: <09>Lane 05 nibble 0 raw readback: 0030
26026246.964: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0030
26027246.964: <09>Lane 05 nibble 0 adjusted value (post nibble): 0030
26028246.964: <09>Lane 06 nibble 0 raw readback: 0034
26029246.964: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0034
26030246.964: <09>Lane 06 nibble 0 adjusted value (post nibble): 0034
26031246.964: <09>Lane 07 nibble 0 raw readback: 0036
26032246.964: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
26033246.964: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
26034246.964: <09>Lane 08 nibble 0 raw readback: 0030
26035246.964: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
26036246.964: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
26037246.964: AgesaHwWlPhase1: training nibble 1
26038246.964: DIMM 1 RttNom: 3
26039246.964: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26040246.964: DIMM 1 RttWr: 2
26041246.964: DIMM 1 RttWr: 2
26042246.964: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26043246.964: DIMM 1 RttWr: 2
26044246.964: DIMM 1 RttNom: 3
26045246.964: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26046246.964: DIMM 1 RttNom: 3
26047246.964: DIMM 1 RttWr: 2
26048246.964: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26049246.964: DIMM 1 RttWr: 2
26050246.964: DIMM 0 RttNom: 3
26051246.964: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26052246.964: DIMM 1 RttNom: 3
26053246.964: DIMM 0 RttWr: 2
26054246.964: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26055246.964: DIMM 1 RttWr: 2
26056246.964: DIMM 0 RttNom: 3
26057246.964: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26058246.964: DIMM 1 RttNom: 3
26059246.964: DIMM 0 RttWr: 2
26060246.964: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26061246.964: DIMM 1 RttWr: 2
26062246.964: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
26063246.964: <09>Lane 00 initial seed: 0041
26064246.964: <09>Lane 01 initial seed: 0041
26065246.964: <09>Lane 02 initial seed: 0041
26066246.964: <09>Lane 03 initial seed: 0041
26067246.964: <09>Lane 04 initial seed: 0041
26068246.964: <09>Lane 05 initial seed: 0041
26069246.964: <09>Lane 06 initial seed: 0041
26070246.964: <09>Lane 07 initial seed: 0041
26071246.964: <09>Lane 08 initial seed: 0041
26072246.964: <09>Lane 00 nibble 1 raw readback: 003f
26073246.964: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
26074246.964: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
26075246.964: <09>Lane 01 nibble 1 raw readback: 003c
26076246.964: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
26077246.964: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
26078246.964: <09>Lane 02 nibble 1 raw readback: 0039
26079246.964: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
26080246.964: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
26081246.964: <09>Lane 03 nibble 1 raw readback: 0039
26082246.964: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0039
26083246.964: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
26084246.964: <09>Lane 04 nibble 1 raw readback: 002f
26085246.964: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002f
26086246.964: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
26087246.964: <09>Lane 05 nibble 1 raw readback: 0031
26088246.964: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
26089246.965: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
26090246.964: <09>Lane 06 nibble 1 raw readback: 0033
26091246.965: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
26092246.965: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
26093246.965: <09>Lane 07 nibble 1 raw readback: 0036
26094246.965: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
26095246.965: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
26096246.965: <09>Lane 08 nibble 1 raw readback: 0030
26097246.965: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0030
26098246.965: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
26099246.965: <09>original critical gross delay: 0
26100246.965: <09>new critical gross delay: 0
26101246.965: DIMM 1 RttNom: 3
26102246.965: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26103246.965: DIMM 1 RttNom: 3
26104246.965: DIMM 1 RttWr: 2
26105246.965: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26106246.965: DIMM 1 RttWr: 2
26107246.965: DIMM 1 RttNom: 3
26108246.965: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26109246.965: DIMM 1 RttNom: 3
26110246.965: DIMM 1 RttWr: 2
26111246.965: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26112246.965: DIMM 1 RttWr: 2
26113246.965: DIMM 0 RttNom: 3
26114246.965: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26115246.965: DIMM 1 RttNom: 3
26116246.965: DIMM 0 RttWr: 2
26117246.965: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26118246.965: DIMM 1 RttWr: 2
26119246.965: DIMM 0 RttNom: 3
26120246.965: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26121246.965: DIMM 1 RttNom: 3
26122246.965: DIMM 0 RttWr: 2
26123246.965: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26124246.965: DIMM 1 RttWr: 2
26125246.965: activate_spd_rom() for node 01
26126246.965: enable_spd_node1()
26127246.965: AgesaHwWlPhase1: training nibble 0
26128246.966: DIMM 0 RttNom: 3
26129246.966: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26130246.966: DIMM 0 RttWr: 2
26131246.966: DIMM 0 RttWr: 2
26132246.966: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26133246.966: DIMM 0 RttWr: 2
26134246.966: DIMM 0 RttNom: 3
26135246.966: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26136246.966: DIMM 0 RttNom: 3
26137246.966: DIMM 0 RttWr: 2
26138246.966: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26139246.966: DIMM 0 RttWr: 2
26140246.966: DIMM 1 RttNom: 3
26141246.966: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26142246.966: DIMM 0 RttNom: 3
26143246.966: DIMM 1 RttWr: 2
26144246.966: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26145246.966: DIMM 0 RttWr: 2
26146246.966: DIMM 1 RttNom: 3
26147246.966: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26148246.966: DIMM 0 RttNom: 3
26149246.966: DIMM 1 RttWr: 2
26150246.966: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26151246.966: DIMM 0 RttWr: 2
26152246.966: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
26153246.966: <09>Lane 00 initial seed: 0041
26154246.966: <09>Lane 01 initial seed: 0041
26155246.966: <09>Lane 02 initial seed: 0041
26156246.966: <09>Lane 03 initial seed: 0041
26157246.966: <09>Lane 04 initial seed: 0041
26158246.966: <09>Lane 05 initial seed: 0041
26159246.966: <09>Lane 06 initial seed: 0041
26160246.966: <09>Lane 07 initial seed: 0041
26161246.966: <09>Lane 08 initial seed: 0041
26162246.966: <09>Lane 00 nibble 0 raw readback: 003b
26163246.966: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003b
26164246.966: <09>Lane 00 nibble 0 adjusted value (post nibble): 003b
26165246.966: <09>Lane 01 nibble 0 raw readback: 0037
26166246.966: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
26167246.966: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
26168246.966: <09>Lane 02 nibble 0 raw readback: 0033
26169246.966: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0033
26170246.966: <09>Lane 02 nibble 0 adjusted value (post nibble): 0033
26171246.966: <09>Lane 03 nibble 0 raw readback: 0031
26172246.966: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0031
26173246.966: <09>Lane 03 nibble 0 adjusted value (post nibble): 0031
26174246.966: <09>Lane 04 nibble 0 raw readback: 002f
26175246.966: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
26176246.966: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
26177246.966: <09>Lane 05 nibble 0 raw readback: 0032
26178246.966: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
26179246.966: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
26180246.966: <09>Lane 06 nibble 0 raw readback: 0035
26181246.966: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0035
26182246.966: <09>Lane 06 nibble 0 adjusted value (post nibble): 0035
26183246.966: <09>Lane 07 nibble 0 raw readback: 0038
26184246.966: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0038
26185246.966: <09>Lane 07 nibble 0 adjusted value (post nibble): 0038
26186246.966: <09>Lane 08 nibble 0 raw readback: 002f
26187246.966: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
26188246.966: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
26189246.966: AgesaHwWlPhase1: training nibble 1
26190246.966: DIMM 0 RttNom: 3
26191246.966: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26192246.966: DIMM 0 RttWr: 2
26193246.967: DIMM 0 RttWr: 2
26194246.967: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26195246.967: DIMM 0 RttWr: 2
26196246.967: DIMM 0 RttNom: 3
26197246.967: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26198246.967: DIMM 0 RttNom: 3
26199246.967: DIMM 0 RttWr: 2
26200246.967: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26201246.967: DIMM 0 RttWr: 2
26202246.967: DIMM 1 RttNom: 3
26203246.967: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26204246.967: DIMM 0 RttNom: 3
26205246.967: DIMM 1 RttWr: 2
26206246.967: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26207246.967: DIMM 0 RttWr: 2
26208246.967: DIMM 1 RttNom: 3
26209246.967: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26210246.967: DIMM 0 RttNom: 3
26211246.967: DIMM 1 RttWr: 2
26212246.967: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26213246.967: DIMM 0 RttWr: 2
26214246.967: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
26215246.967: <09>Lane 00 initial seed: 0041
26216246.967: <09>Lane 01 initial seed: 0041
26217246.967: <09>Lane 02 initial seed: 0041
26218246.967: <09>Lane 03 initial seed: 0041
26219246.967: <09>Lane 04 initial seed: 0041
26220246.967: <09>Lane 05 initial seed: 0041
26221246.967: <09>Lane 06 initial seed: 0041
26222246.967: <09>Lane 07 initial seed: 0041
26223246.967: <09>Lane 08 initial seed: 0041
26224246.967: <09>Lane 00 nibble 1 raw readback: 0039
26225246.967: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0039
26226246.967: <09>Lane 00 nibble 1 adjusted value (post nibble): 003d
26227246.967: <09>Lane 01 nibble 1 raw readback: 0037
26228246.967: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
26229246.967: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
26230246.967: <09>Lane 02 nibble 1 raw readback: 0033
26231246.967: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0033
26232246.967: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
26233246.967: <09>Lane 03 nibble 1 raw readback: 0032
26234246.967: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0032
26235246.967: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
26236246.967: <09>Lane 04 nibble 1 raw readback: 0030
26237246.967: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
26238246.967: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
26239246.967: <09>Lane 05 nibble 1 raw readback: 0031
26240246.967: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
26241246.967: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
26242246.967: <09>Lane 06 nibble 1 raw readback: 0035
26243246.967: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
26244246.967: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
26245246.967: <09>Lane 07 nibble 1 raw readback: 0038
26246246.967: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0038
26247246.967: <09>Lane 07 nibble 1 adjusted value (post nibble): 003c
26248246.967: <09>Lane 08 nibble 1 raw readback: 002f
26249246.967: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
26250246.967: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
26251246.967: <09>original critical gross delay: 0
26252246.967: <09>new critical gross delay: 0
26253246.968: DIMM 0 RttNom: 3
26254246.968: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26255246.968: DIMM 0 RttNom: 3
26256246.968: DIMM 0 RttWr: 2
26257246.968: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26258246.968: DIMM 0 RttWr: 2
26259246.968: DIMM 0 RttNom: 3
26260246.968: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26261246.968: DIMM 0 RttNom: 3
26262246.968: DIMM 0 RttWr: 2
26263246.968: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26264246.968: DIMM 0 RttWr: 2
26265246.968: DIMM 1 RttNom: 3
26266246.968: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26267246.968: DIMM 0 RttNom: 3
26268246.968: DIMM 1 RttWr: 2
26269246.968: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26270246.968: DIMM 0 RttWr: 2
26271246.968: DIMM 1 RttNom: 3
26272246.968: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26273246.968: DIMM 0 RttNom: 3
26274246.968: DIMM 1 RttWr: 2
26275246.968: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26276246.968: DIMM 0 RttWr: 2
26277246.968: AgesaHwWlPhase1: training nibble 0
26278246.968: DIMM 1 RttNom: 3
26279246.968: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26280246.968: DIMM 1 RttWr: 2
26281246.968: DIMM 1 RttWr: 2
26282246.968: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26283246.968: DIMM 1 RttWr: 2
26284246.968: DIMM 1 RttNom: 3
26285246.968: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26286246.968: DIMM 1 RttNom: 3
26287246.968: DIMM 1 RttWr: 2
26288246.968: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26289246.968: DIMM 1 RttWr: 2
26290246.968: DIMM 0 RttNom: 3
26291246.968: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26292246.968: DIMM 1 RttNom: 3
26293246.968: DIMM 0 RttWr: 2
26294246.968: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26295246.968: DIMM 1 RttWr: 2
26296246.968: DIMM 0 RttNom: 3
26297246.968: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26298246.968: DIMM 1 RttNom: 3
26299246.968: DIMM 0 RttWr: 2
26300246.968: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26301246.968: DIMM 1 RttWr: 2
26302246.968: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
26303246.968: <09>Lane 00 initial seed: 0041
26304246.968: <09>Lane 01 initial seed: 0041
26305246.968: <09>Lane 02 initial seed: 0041
26306246.968: <09>Lane 03 initial seed: 0041
26307246.968: <09>Lane 04 initial seed: 0041
26308246.968: <09>Lane 05 initial seed: 0041
26309246.968: <09>Lane 06 initial seed: 0041
26310246.968: <09>Lane 07 initial seed: 0041
26311246.968: <09>Lane 08 initial seed: 0041
26312246.968: <09>Lane 00 nibble 0 raw readback: 0043
26313246.968: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
26314246.968: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
26315246.968: <09>Lane 01 nibble 0 raw readback: 003e
26316246.968: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
26317246.969: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
26318246.969: <09>Lane 02 nibble 0 raw readback: 003b
26319246.969: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
26320246.969: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
26321246.969: <09>Lane 03 nibble 0 raw readback: 003a
26322246.969: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
26323246.969: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
26324246.969: <09>Lane 04 nibble 0 raw readback: 0038
26325246.969: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
26326246.969: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
26327246.969: <09>Lane 05 nibble 0 raw readback: 003b
26328246.969: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
26329246.969: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
26330246.969: <09>Lane 06 nibble 0 raw readback: 003c
26331246.969: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003c
26332246.969: <09>Lane 06 nibble 0 adjusted value (post nibble): 003c
26333246.969: <09>Lane 07 nibble 0 raw readback: 0040
26334246.969: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
26335246.969: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
26336246.969: <09>Lane 08 nibble 0 raw readback: 0036
26337246.969: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
26338246.969: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
26339246.969: AgesaHwWlPhase1: training nibble 1
26340246.969: DIMM 1 RttNom: 3
26341246.969: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26342246.969: DIMM 1 RttWr: 2
26343246.969: DIMM 1 RttWr: 2
26344246.969: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26345246.969: DIMM 1 RttWr: 2
26346246.969: DIMM 1 RttNom: 3
26347246.969: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26348246.969: DIMM 1 RttNom: 3
26349246.969: DIMM 1 RttWr: 2
26350246.969: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26351246.969: DIMM 1 RttWr: 2
26352246.969: DIMM 0 RttNom: 3
26353246.969: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26354246.969: DIMM 1 RttNom: 3
26355246.969: DIMM 0 RttWr: 2
26356246.969: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26357246.969: DIMM 1 RttWr: 2
26358246.969: DIMM 0 RttNom: 3
26359246.969: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26360246.969: DIMM 1 RttNom: 3
26361246.969: DIMM 0 RttWr: 2
26362246.969: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26363246.969: DIMM 1 RttWr: 2
26364246.969: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
26365246.969: <09>Lane 00 initial seed: 0041
26366246.969: <09>Lane 01 initial seed: 0041
26367246.969: <09>Lane 02 initial seed: 0041
26368246.969: <09>Lane 03 initial seed: 0041
26369246.969: <09>Lane 04 initial seed: 0041
26370246.969: <09>Lane 05 initial seed: 0041
26371246.969: <09>Lane 06 initial seed: 0041
26372246.969: <09>Lane 07 initial seed: 0041
26373246.969: <09>Lane 08 initial seed: 0041
26374246.969: <09>Lane 00 nibble 1 raw readback: 0044
26375246.969: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
26376246.969: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
26377246.969: <09>Lane 01 nibble 1 raw readback: 003e
26378246.969: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003e
26379246.969: <09>Lane 01 nibble 1 adjusted value (post nibble): 003f
26380246.969: <09>Lane 02 nibble 1 raw readback: 003c
26381246.969: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
26382246.969: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
26383246.969: <09>Lane 03 nibble 1 raw readback: 003b
26384246.969: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
26385246.969: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
26386246.969: <09>Lane 04 nibble 1 raw readback: 0038
26387246.969: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
26388246.969: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
26389246.969: <09>Lane 05 nibble 1 raw readback: 003b
26390246.969: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
26391246.969: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
26392246.969: <09>Lane 06 nibble 1 raw readback: 003d
26393246.969: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
26394246.969: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
26395246.970: <09>Lane 07 nibble 1 raw readback: 0040
26396246.970: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
26397246.970: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
26398246.970: <09>Lane 08 nibble 1 raw readback: 0037
26399246.970: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
26400246.970: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
26401246.970: <09>original critical gross delay: 0
26402246.970: <09>new critical gross delay: 0
26403246.970: DIMM 1 RttNom: 3
26404246.970: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26405246.970: DIMM 1 RttNom: 3
26406246.970: DIMM 1 RttWr: 2
26407246.970: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26408246.970: DIMM 1 RttWr: 2
26409246.970: DIMM 1 RttNom: 3
26410246.970: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26411246.970: DIMM 1 RttNom: 3
26412246.970: DIMM 1 RttWr: 2
26413246.970: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26414246.970: DIMM 1 RttWr: 2
26415246.970: DIMM 0 RttNom: 3
26416246.970: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26417246.970: DIMM 1 RttNom: 3
26418246.970: DIMM 0 RttWr: 2
26419246.970: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26420246.970: DIMM 1 RttWr: 2
26421246.970: DIMM 0 RttNom: 3
26422246.970: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26423246.970: DIMM 1 RttNom: 3
26424246.970: DIMM 0 RttWr: 2
26425246.970: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26426246.970: DIMM 1 RttWr: 2
26427246.970: AgesaHwWlPhase1: training nibble 0
26428246.970: DIMM 0 RttNom: 3
26429246.970: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26430246.970: DIMM 0 RttWr: 2
26431246.970: DIMM 0 RttWr: 2
26432246.970: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26433246.970: DIMM 0 RttWr: 2
26434246.970: DIMM 0 RttNom: 3
26435246.970: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26436246.970: DIMM 0 RttNom: 3
26437246.970: DIMM 0 RttWr: 2
26438246.970: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26439246.970: DIMM 0 RttWr: 2
26440246.970: DIMM 1 RttNom: 3
26441246.970: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26442246.970: DIMM 0 RttNom: 3
26443246.970: DIMM 1 RttWr: 2
26444246.970: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26445246.970: DIMM 0 RttWr: 2
26446246.970: DIMM 1 RttNom: 3
26447246.970: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26448246.970: DIMM 0 RttNom: 3
26449246.970: DIMM 1 RttWr: 2
26450246.970: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26451246.970: DIMM 0 RttWr: 2
26452246.970: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
26453246.970: <09>Lane 00 initial seed: 0041
26454246.971: <09>Lane 01 initial seed: 0041
26455246.971: <09>Lane 02 initial seed: 0041
26456246.971: <09>Lane 03 initial seed: 0041
26457246.971: <09>Lane 04 initial seed: 0041
26458246.971: <09>Lane 05 initial seed: 0041
26459246.971: <09>Lane 06 initial seed: 0041
26460246.971: <09>Lane 07 initial seed: 0041
26461246.971: <09>Lane 08 initial seed: 0041
26462246.971: <09>Lane 00 nibble 0 raw readback: 003c
26463246.971: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003c
26464246.971: <09>Lane 00 nibble 0 adjusted value (post nibble): 003c
26465246.971: <09>Lane 01 nibble 0 raw readback: 0037
26466246.971: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
26467246.971: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
26468246.971: <09>Lane 02 nibble 0 raw readback: 0034
26469246.971: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0034
26470246.971: <09>Lane 02 nibble 0 adjusted value (post nibble): 0034
26471246.971: <09>Lane 03 nibble 0 raw readback: 0031
26472246.971: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0031
26473246.971: <09>Lane 03 nibble 0 adjusted value (post nibble): 0031
26474246.971: <09>Lane 04 nibble 0 raw readback: 0030
26475246.971: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
26476246.971: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
26477246.971: <09>Lane 05 nibble 0 raw readback: 0034
26478246.971: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0034
26479246.971: <09>Lane 05 nibble 0 adjusted value (post nibble): 0034
26480246.971: <09>Lane 06 nibble 0 raw readback: 0035
26481246.971: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0035
26482246.971: <09>Lane 06 nibble 0 adjusted value (post nibble): 0035
26483246.971: <09>Lane 07 nibble 0 raw readback: 0039
26484246.971: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
26485246.971: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
26486246.971: <09>Lane 08 nibble 0 raw readback: 002f
26487246.971: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
26488246.971: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
26489246.971: AgesaHwWlPhase1: training nibble 1
26490246.971: DIMM 0 RttNom: 3
26491246.971: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26492246.971: DIMM 0 RttWr: 2
26493246.971: DIMM 0 RttWr: 2
26494246.971: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26495246.971: DIMM 0 RttWr: 2
26496246.971: DIMM 0 RttNom: 3
26497246.971: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26498246.971: DIMM 0 RttNom: 3
26499246.971: DIMM 0 RttWr: 2
26500246.971: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26501246.971: DIMM 0 RttWr: 2
26502246.971: DIMM 1 RttNom: 3
26503246.971: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26504246.971: DIMM 0 RttNom: 3
26505246.971: DIMM 1 RttWr: 2
26506246.971: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26507246.971: DIMM 0 RttWr: 2
26508246.971: DIMM 1 RttNom: 3
26509246.971: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26510246.971: DIMM 0 RttNom: 3
26511246.971: DIMM 1 RttWr: 2
26512246.971: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26513246.971: DIMM 0 RttWr: 2
26514246.971: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
26515246.971: <09>Lane 00 initial seed: 0041
26516246.971: <09>Lane 01 initial seed: 0041
26517246.971: <09>Lane 02 initial seed: 0041
26518246.971: <09>Lane 03 initial seed: 0041
26519246.971: <09>Lane 04 initial seed: 0041
26520246.971: <09>Lane 05 initial seed: 0041
26521246.971: <09>Lane 06 initial seed: 0041
26522246.971: <09>Lane 07 initial seed: 0041
26523246.971: <09>Lane 08 initial seed: 0041
26524246.971: <09>Lane 00 nibble 1 raw readback: 003b
26525246.972: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003b
26526246.972: <09>Lane 00 nibble 1 adjusted value (post nibble): 003e
26527246.972: <09>Lane 01 nibble 1 raw readback: 0037
26528246.972: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
26529246.972: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
26530246.972: <09>Lane 02 nibble 1 raw readback: 0033
26531246.972: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0033
26532246.972: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
26533246.972: <09>Lane 03 nibble 1 raw readback: 0031
26534246.972: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0031
26535246.972: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
26536246.972: <09>Lane 04 nibble 1 raw readback: 002f
26537246.972: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002f
26538246.972: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
26539246.972: <09>Lane 05 nibble 1 raw readback: 0032
26540246.972: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
26541246.972: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
26542246.972: <09>Lane 06 nibble 1 raw readback: 0035
26543246.972: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
26544246.972: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
26545246.972: <09>Lane 07 nibble 1 raw readback: 0039
26546246.972: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
26547246.972: <09>Lane 07 nibble 1 adjusted value (post nibble): 003d
26548246.972: <09>Lane 08 nibble 1 raw readback: 002e
26549246.972: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002e
26550246.972: <09>Lane 08 nibble 1 adjusted value (post nibble): 0037
26551246.972: <09>original critical gross delay: 0
26552246.972: <09>new critical gross delay: 0
26553246.972: DIMM 0 RttNom: 3
26554246.972: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26555246.972: DIMM 0 RttNom: 3
26556246.972: DIMM 0 RttWr: 2
26557246.972: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26558246.972: DIMM 0 RttWr: 2
26559246.972: DIMM 0 RttNom: 3
26560246.972: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26561246.972: DIMM 0 RttNom: 3
26562246.972: DIMM 0 RttWr: 2
26563246.972: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26564246.972: DIMM 0 RttWr: 2
26565246.972: DIMM 1 RttNom: 3
26566246.972: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26567246.972: DIMM 0 RttNom: 3
26568246.972: DIMM 1 RttWr: 2
26569246.972: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26570246.972: DIMM 0 RttWr: 2
26571246.972: DIMM 1 RttNom: 3
26572246.972: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26573246.972: DIMM 0 RttNom: 3
26574246.972: DIMM 1 RttWr: 2
26575246.972: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26576246.972: DIMM 0 RttWr: 2
26577246.972: AgesaHwWlPhase1: training nibble 0
26578246.972: DIMM 1 RttNom: 3
26579246.972: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26580246.972: DIMM 1 RttWr: 2
26581246.972: DIMM 1 RttWr: 2
26582246.972: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26583246.972: DIMM 1 RttWr: 2
26584246.972: DIMM 1 RttNom: 3
26585246.972: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26586246.972: DIMM 1 RttNom: 3
26587246.972: DIMM 1 RttWr: 2
26588246.972: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26589246.972: DIMM 1 RttWr: 2
26590246.973: DIMM 0 RttNom: 3
26591246.973: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26592246.973: DIMM 1 RttNom: 3
26593246.973: DIMM 0 RttWr: 2
26594246.973: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26595246.973: DIMM 1 RttWr: 2
26596246.973: DIMM 0 RttNom: 3
26597246.973: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26598246.973: DIMM 1 RttNom: 3
26599246.973: DIMM 0 RttWr: 2
26600246.973: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26601246.973: DIMM 1 RttWr: 2
26602246.973: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
26603246.973: <09>Lane 00 initial seed: 0041
26604246.973: <09>Lane 01 initial seed: 0041
26605246.973: <09>Lane 02 initial seed: 0041
26606246.973: <09>Lane 03 initial seed: 0041
26607246.973: <09>Lane 04 initial seed: 0041
26608246.973: <09>Lane 05 initial seed: 0041
26609246.973: <09>Lane 06 initial seed: 0041
26610246.973: <09>Lane 07 initial seed: 0041
26611246.973: <09>Lane 08 initial seed: 0041
26612246.973: <09>Lane 00 nibble 0 raw readback: 0041
26613246.973: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0041
26614246.973: <09>Lane 00 nibble 0 adjusted value (post nibble): 0041
26615246.973: <09>Lane 01 nibble 0 raw readback: 003f
26616246.973: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
26617246.973: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
26618246.973: <09>Lane 02 nibble 0 raw readback: 003c
26619246.973: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
26620246.973: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
26621246.973: <09>Lane 03 nibble 0 raw readback: 0039
26622246.973: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0039
26623246.973: <09>Lane 03 nibble 0 adjusted value (post nibble): 0039
26624246.973: <09>Lane 04 nibble 0 raw readback: 0038
26625246.973: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
26626246.973: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
26627246.973: <09>Lane 05 nibble 0 raw readback: 003b
26628246.973: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
26629246.973: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
26630246.973: <09>Lane 06 nibble 0 raw readback: 003e
26631246.973: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
26632246.973: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
26633246.973: <09>Lane 07 nibble 0 raw readback: 0040
26634246.973: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
26635246.973: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
26636246.973: <09>Lane 08 nibble 0 raw readback: 0036
26637246.973: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
26638246.973: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
26639246.973: AgesaHwWlPhase1: training nibble 1
26640246.973: DIMM 1 RttNom: 3
26641246.973: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26642246.973: DIMM 1 RttWr: 2
26643246.973: DIMM 1 RttWr: 2
26644246.973: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26645246.973: DIMM 1 RttWr: 2
26646246.973: DIMM 1 RttNom: 3
26647246.973: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26648246.973: DIMM 1 RttNom: 3
26649246.973: DIMM 1 RttWr: 2
26650246.973: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26651246.973: DIMM 1 RttWr: 2
26652246.973: DIMM 0 RttNom: 3
26653246.973: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26654246.973: DIMM 1 RttNom: 3
26655246.973: DIMM 0 RttWr: 2
26656246.973: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26657246.973: DIMM 1 RttWr: 2
26658246.973: DIMM 0 RttNom: 3
26659246.974: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26660246.973: DIMM 1 RttNom: 3
26661246.974: DIMM 0 RttWr: 2
26662246.974: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26663246.974: DIMM 1 RttWr: 2
26664246.974: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
26665246.974: <09>Lane 00 initial seed: 0041
26666246.974: <09>Lane 01 initial seed: 0041
26667246.974: <09>Lane 02 initial seed: 0041
26668246.974: <09>Lane 03 initial seed: 0041
26669246.974: <09>Lane 04 initial seed: 0041
26670246.974: <09>Lane 05 initial seed: 0041
26671246.974: <09>Lane 06 initial seed: 0041
26672246.974: <09>Lane 07 initial seed: 0041
26673246.974: <09>Lane 08 initial seed: 0041
26674246.974: <09>Lane 00 nibble 1 raw readback: 0043
26675246.974: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
26676246.974: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
26677246.974: <09>Lane 01 nibble 1 raw readback: 0040
26678246.974: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
26679246.974: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
26680246.974: <09>Lane 02 nibble 1 raw readback: 003c
26681246.974: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
26682246.974: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
26683246.974: <09>Lane 03 nibble 1 raw readback: 003a
26684246.974: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
26685246.974: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
26686246.974: <09>Lane 04 nibble 1 raw readback: 0037
26687246.974: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
26688246.974: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
26689246.974: <09>Lane 05 nibble 1 raw readback: 003b
26690246.974: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
26691246.974: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
26692246.974: <09>Lane 06 nibble 1 raw readback: 003e
26693246.974: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
26694246.974: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
26695246.974: <09>Lane 07 nibble 1 raw readback: 0042
26696246.974: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
26697246.974: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
26698246.974: <09>Lane 08 nibble 1 raw readback: 0037
26699246.974: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
26700246.974: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
26701246.974: <09>original critical gross delay: 0
26702246.974: <09>new critical gross delay: 0
26703246.974: DIMM 1 RttNom: 3
26704246.974: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
26705246.974: DIMM 1 RttNom: 3
26706246.974: DIMM 1 RttWr: 2
26707246.974: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
26708246.974: DIMM 1 RttWr: 2
26709246.974: DIMM 1 RttNom: 3
26710246.974: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
26711246.974: DIMM 1 RttNom: 3
26712246.974: DIMM 1 RttWr: 2
26713246.974: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
26714246.974: DIMM 1 RttWr: 2
26715246.974: DIMM 0 RttNom: 3
26716246.974: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
26717246.974: DIMM 1 RttNom: 3
26718246.974: DIMM 0 RttWr: 2
26719246.974: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
26720246.974: DIMM 1 RttWr: 2
26721246.974: DIMM 0 RttNom: 3
26722246.974: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
26723246.974: DIMM 1 RttNom: 3
26724246.974: DIMM 0 RttWr: 2
26725246.974: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
26726246.975: DIMM 1 RttWr: 2
26727246.975: activate_spd_rom() for node 02
26728246.975: enable_spd_node2()
26729246.975: AgesaHwWlPhase1: training nibble 0
26730246.975: DIMM 0 RttNom: 3
26731246.975: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26732246.975: DIMM 0 RttWr: 2
26733246.975: DIMM 0 RttWr: 2
26734246.975: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26735246.975: DIMM 0 RttWr: 2
26736246.975: DIMM 0 RttNom: 3
26737246.975: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26738246.975: DIMM 0 RttNom: 3
26739246.975: DIMM 0 RttWr: 2
26740246.975: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26741246.975: DIMM 0 RttWr: 2
26742246.975: DIMM 1 RttNom: 3
26743246.975: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26744246.975: DIMM 0 RttNom: 3
26745246.975: DIMM 1 RttWr: 2
26746246.975: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26747246.975: DIMM 0 RttWr: 2
26748246.975: DIMM 1 RttNom: 3
26749246.975: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26750246.975: DIMM 0 RttNom: 3
26751246.975: DIMM 1 RttWr: 2
26752246.975: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26753246.975: DIMM 0 RttWr: 2
26754246.975: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
26755246.975: <09>Lane 00 initial seed: 0041
26756246.975: <09>Lane 01 initial seed: 0041
26757246.975: <09>Lane 02 initial seed: 0041
26758246.975: <09>Lane 03 initial seed: 0041
26759246.975: <09>Lane 04 initial seed: 0041
26760246.975: <09>Lane 05 initial seed: 0041
26761246.975: <09>Lane 06 initial seed: 0041
26762246.975: <09>Lane 07 initial seed: 0041
26763246.975: <09>Lane 08 initial seed: 0041
26764246.975: <09>Lane 00 nibble 0 raw readback: 004b
26765246.975: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004b
26766246.975: <09>Lane 00 nibble 0 adjusted value (post nibble): 004b
26767246.975: <09>Lane 01 nibble 0 raw readback: 0045
26768246.975: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0045
26769246.976: <09>Lane 01 nibble 0 adjusted value (post nibble): 0045
26770246.976: <09>Lane 02 nibble 0 raw readback: 0043
26771246.976: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
26772246.976: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
26773246.976: <09>Lane 03 nibble 0 raw readback: 0042
26774246.976: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
26775246.976: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
26776246.976: <09>Lane 04 nibble 0 raw readback: 0039
26777246.976: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
26778246.976: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
26779246.976: <09>Lane 05 nibble 0 raw readback: 003c
26780246.976: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
26781246.976: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
26782246.976: <09>Lane 06 nibble 0 raw readback: 003f
26783246.976: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
26784246.976: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
26785246.976: <09>Lane 07 nibble 0 raw readback: 0041
26786246.976: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
26787246.976: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
26788246.976: <09>Lane 08 nibble 0 raw readback: 003b
26789246.976: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
26790246.976: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
26791246.976: AgesaHwWlPhase1: training nibble 1
26792246.976: DIMM 0 RttNom: 3
26793246.976: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26794246.976: DIMM 0 RttWr: 2
26795246.976: DIMM 0 RttWr: 2
26796246.976: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26797246.976: DIMM 0 RttWr: 2
26798246.976: DIMM 0 RttNom: 3
26799246.976: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26800246.976: DIMM 0 RttNom: 3
26801246.976: DIMM 0 RttWr: 2
26802246.976: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26803246.976: DIMM 0 RttWr: 2
26804246.976: DIMM 1 RttNom: 3
26805246.976: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26806246.976: DIMM 0 RttNom: 3
26807246.976: DIMM 1 RttWr: 2
26808246.976: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26809246.976: DIMM 0 RttWr: 2
26810246.976: DIMM 1 RttNom: 3
26811246.976: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26812246.976: DIMM 0 RttNom: 3
26813246.976: DIMM 1 RttWr: 2
26814246.976: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26815246.976: DIMM 0 RttWr: 2
26816246.976: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
26817246.976: <09>Lane 00 initial seed: 0041
26818246.976: <09>Lane 01 initial seed: 0041
26819246.976: <09>Lane 02 initial seed: 0041
26820246.976: <09>Lane 03 initial seed: 0041
26821246.976: <09>Lane 04 initial seed: 0041
26822246.976: <09>Lane 05 initial seed: 0041
26823246.976: <09>Lane 06 initial seed: 0041
26824246.976: <09>Lane 07 initial seed: 0041
26825246.976: <09>Lane 08 initial seed: 0041
26826246.976: <09>Lane 00 nibble 1 raw readback: 004a
26827246.976: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
26828246.976: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
26829246.976: <09>Lane 01 nibble 1 raw readback: 0046
26830246.976: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0046
26831246.976: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
26832246.976: <09>Lane 02 nibble 1 raw readback: 0044
26833246.976: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
26834246.976: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
26835246.976: <09>Lane 03 nibble 1 raw readback: 0042
26836246.977: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0042
26837246.976: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
26838246.976: <09>Lane 04 nibble 1 raw readback: 0039
26839246.977: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
26840246.977: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
26841246.977: <09>Lane 05 nibble 1 raw readback: 003b
26842246.977: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
26843246.977: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
26844246.977: <09>Lane 06 nibble 1 raw readback: 003f
26845246.977: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
26846246.977: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
26847246.977: <09>Lane 07 nibble 1 raw readback: 0040
26848246.977: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
26849246.977: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
26850246.977: <09>Lane 08 nibble 1 raw readback: 0039
26851246.977: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
26852246.977: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
26853246.977: <09>original critical gross delay: 0
26854246.977: <09>new critical gross delay: 0
26855246.977: DIMM 0 RttNom: 3
26856246.977: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26857246.977: DIMM 0 RttNom: 3
26858246.977: DIMM 0 RttWr: 2
26859246.977: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26860246.977: DIMM 0 RttWr: 2
26861246.977: DIMM 0 RttNom: 3
26862246.977: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26863246.977: DIMM 0 RttNom: 3
26864246.977: DIMM 0 RttWr: 2
26865246.977: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26866246.977: DIMM 0 RttWr: 2
26867246.977: DIMM 1 RttNom: 3
26868246.977: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26869246.977: DIMM 0 RttNom: 3
26870246.977: DIMM 1 RttWr: 2
26871246.977: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26872246.977: DIMM 0 RttWr: 2
26873246.977: DIMM 1 RttNom: 3
26874246.977: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26875246.977: DIMM 0 RttNom: 3
26876246.977: DIMM 1 RttWr: 2
26877246.977: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26878246.977: DIMM 0 RttWr: 2
26879246.977: AgesaHwWlPhase1: training nibble 0
26880246.977: DIMM 1 RttNom: 3
26881246.977: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26882246.977: DIMM 1 RttWr: 2
26883246.977: DIMM 1 RttWr: 2
26884246.977: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26885246.977: DIMM 1 RttWr: 2
26886246.977: DIMM 1 RttNom: 3
26887246.977: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26888246.977: DIMM 1 RttNom: 3
26889246.977: DIMM 1 RttWr: 2
26890246.977: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26891246.977: DIMM 1 RttWr: 2
26892246.977: DIMM 0 RttNom: 3
26893246.977: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26894246.977: DIMM 1 RttNom: 3
26895246.977: DIMM 0 RttWr: 2
26896246.977: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26897246.977: DIMM 1 RttWr: 2
26898246.977: DIMM 0 RttNom: 3
26899246.978: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26900246.978: DIMM 1 RttNom: 3
26901246.978: DIMM 0 RttWr: 2
26902246.978: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26903246.978: DIMM 1 RttWr: 2
26904246.978: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
26905246.978: <09>Lane 00 initial seed: 0041
26906246.978: <09>Lane 01 initial seed: 0041
26907246.978: <09>Lane 02 initial seed: 0041
26908246.978: <09>Lane 03 initial seed: 0041
26909246.978: <09>Lane 04 initial seed: 0041
26910246.978: <09>Lane 05 initial seed: 0041
26911246.978: <09>Lane 06 initial seed: 0041
26912246.978: <09>Lane 07 initial seed: 0041
26913246.978: <09>Lane 08 initial seed: 0041
26914246.978: <09>Lane 00 nibble 0 raw readback: 0040
26915246.978: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0040
26916246.978: <09>Lane 00 nibble 0 adjusted value (post nibble): 0040
26917246.978: <09>Lane 01 nibble 0 raw readback: 003a
26918246.978: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003a
26919246.978: <09>Lane 01 nibble 0 adjusted value (post nibble): 003a
26920246.978: <09>Lane 02 nibble 0 raw readback: 0039
26921246.978: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
26922246.978: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
26923246.978: <09>Lane 03 nibble 0 raw readback: 0036
26924246.978: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
26925246.978: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
26926246.978: <09>Lane 04 nibble 0 raw readback: 002d
26927246.978: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002d
26928246.978: <09>Lane 04 nibble 0 adjusted value (post nibble): 002d
26929246.978: <09>Lane 05 nibble 0 raw readback: 0031
26930246.978: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0031
26931246.978: <09>Lane 05 nibble 0 adjusted value (post nibble): 0031
26932246.978: <09>Lane 06 nibble 0 raw readback: 0033
26933246.978: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
26934246.978: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
26935246.978: <09>Lane 07 nibble 0 raw readback: 0036
26936246.978: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
26937246.978: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
26938246.978: <09>Lane 08 nibble 0 raw readback: 0030
26939246.978: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
26940246.978: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
26941246.978: AgesaHwWlPhase1: training nibble 1
26942246.978: DIMM 1 RttNom: 3
26943246.978: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
26944246.978: DIMM 1 RttWr: 2
26945246.978: DIMM 1 RttWr: 2
26946246.978: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
26947246.978: DIMM 1 RttWr: 2
26948246.978: DIMM 1 RttNom: 3
26949246.978: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
26950246.978: DIMM 1 RttNom: 3
26951246.978: DIMM 1 RttWr: 2
26952246.978: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
26953246.978: DIMM 1 RttWr: 2
26954246.978: DIMM 0 RttNom: 3
26955246.978: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
26956246.978: DIMM 1 RttNom: 3
26957246.978: DIMM 0 RttWr: 2
26958246.978: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
26959246.978: DIMM 1 RttWr: 2
26960246.978: DIMM 0 RttNom: 3
26961246.978: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
26962246.978: DIMM 1 RttNom: 3
26963246.978: DIMM 0 RttWr: 2
26964246.978: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
26965246.978: DIMM 1 RttWr: 2
26966246.978: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
26967246.978: <09>Lane 00 initial seed: 0041
26968246.979: <09>Lane 01 initial seed: 0041
26969246.978: <09>Lane 02 initial seed: 0041
26970246.978: <09>Lane 03 initial seed: 0041
26971246.979: <09>Lane 04 initial seed: 0041
26972246.979: <09>Lane 05 initial seed: 0041
26973246.979: <09>Lane 06 initial seed: 0041
26974246.979: <09>Lane 07 initial seed: 0041
26975246.979: <09>Lane 08 initial seed: 0041
26976246.979: <09>Lane 00 nibble 1 raw readback: 003e
26977246.979: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003e
26978246.979: <09>Lane 00 nibble 1 adjusted value (post nibble): 003f
26979246.979: <09>Lane 01 nibble 1 raw readback: 003a
26980246.979: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003a
26981246.979: <09>Lane 01 nibble 1 adjusted value (post nibble): 003d
26982246.979: <09>Lane 02 nibble 1 raw readback: 003a
26983246.979: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003a
26984246.979: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
26985246.979: <09>Lane 03 nibble 1 raw readback: 0037
26986246.979: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
26987246.979: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
26988246.979: <09>Lane 04 nibble 1 raw readback: 002e
26989246.979: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
26990246.979: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
26991246.979: <09>Lane 05 nibble 1 raw readback: 0031
26992246.979: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
26993246.979: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
26994246.979: <09>Lane 06 nibble 1 raw readback: 0033
26995246.979: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
26996246.979: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
26997246.979: <09>Lane 07 nibble 1 raw readback: 0036
26998246.979: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
26999246.979: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
27000246.979: <09>Lane 08 nibble 1 raw readback: 002f
27001246.979: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
27002246.979: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
27003246.979: <09>original critical gross delay: 0
27004246.979: <09>new critical gross delay: 0
27005246.979: DIMM 1 RttNom: 3
27006246.979: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27007246.979: DIMM 1 RttNom: 3
27008246.979: DIMM 1 RttWr: 2
27009246.979: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27010246.979: DIMM 1 RttWr: 2
27011246.979: DIMM 1 RttNom: 3
27012246.979: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27013246.979: DIMM 1 RttNom: 3
27014246.979: DIMM 1 RttWr: 2
27015246.979: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27016246.979: DIMM 1 RttWr: 2
27017246.979: DIMM 0 RttNom: 3
27018246.979: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27019246.979: DIMM 1 RttNom: 3
27020246.979: DIMM 0 RttWr: 2
27021246.979: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27022246.979: DIMM 1 RttWr: 2
27023246.979: DIMM 0 RttNom: 3
27024246.979: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27025246.979: DIMM 1 RttNom: 3
27026246.979: DIMM 0 RttWr: 2
27027246.979: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27028246.979: DIMM 1 RttWr: 2
27029246.979: AgesaHwWlPhase1: training nibble 0
27030246.979: DIMM 0 RttNom: 3
27031246.979: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27032246.979: DIMM 0 RttWr: 2
27033246.980: DIMM 0 RttWr: 2
27034246.980: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27035246.980: DIMM 0 RttWr: 2
27036246.980: DIMM 0 RttNom: 3
27037246.980: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27038246.980: DIMM 0 RttNom: 3
27039246.980: DIMM 0 RttWr: 2
27040246.980: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27041246.980: DIMM 0 RttWr: 2
27042246.980: DIMM 1 RttNom: 3
27043246.980: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27044246.980: DIMM 0 RttNom: 3
27045246.980: DIMM 1 RttWr: 2
27046246.980: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27047246.980: DIMM 0 RttWr: 2
27048246.980: DIMM 1 RttNom: 3
27049246.980: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27050246.980: DIMM 0 RttNom: 3
27051246.980: DIMM 1 RttWr: 2
27052246.980: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27053246.980: DIMM 0 RttWr: 2
27054246.980: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
27055246.980: <09>Lane 00 initial seed: 0041
27056246.980: <09>Lane 01 initial seed: 0041
27057246.980: <09>Lane 02 initial seed: 0041
27058246.980: <09>Lane 03 initial seed: 0041
27059246.980: <09>Lane 04 initial seed: 0041
27060246.980: <09>Lane 05 initial seed: 0041
27061246.980: <09>Lane 06 initial seed: 0041
27062246.980: <09>Lane 07 initial seed: 0041
27063246.980: <09>Lane 08 initial seed: 0041
27064246.980: <09>Lane 00 nibble 0 raw readback: 004a
27065246.980: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004a
27066246.980: <09>Lane 00 nibble 0 adjusted value (post nibble): 004a
27067246.980: <09>Lane 01 nibble 0 raw readback: 0046
27068246.980: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0046
27069246.980: <09>Lane 01 nibble 0 adjusted value (post nibble): 0046
27070246.980: <09>Lane 02 nibble 0 raw readback: 0044
27071246.980: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0044
27072246.980: <09>Lane 02 nibble 0 adjusted value (post nibble): 0044
27073246.980: <09>Lane 03 nibble 0 raw readback: 0041
27074246.980: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0041
27075246.980: <09>Lane 03 nibble 0 adjusted value (post nibble): 0041
27076246.980: <09>Lane 04 nibble 0 raw readback: 0039
27077246.980: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
27078246.980: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
27079246.980: <09>Lane 05 nibble 0 raw readback: 003c
27080246.980: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
27081246.980: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
27082246.980: <09>Lane 06 nibble 0 raw readback: 003f
27083246.980: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
27084246.980: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
27085246.980: <09>Lane 07 nibble 0 raw readback: 0040
27086246.980: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
27087246.980: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
27088246.980: <09>Lane 08 nibble 0 raw readback: 003b
27089246.980: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
27090246.980: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
27091246.980: AgesaHwWlPhase1: training nibble 1
27092246.980: DIMM 0 RttNom: 3
27093246.980: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27094246.980: DIMM 0 RttWr: 2
27095246.980: DIMM 0 RttWr: 2
27096246.980: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27097246.980: DIMM 0 RttWr: 2
27098246.980: DIMM 0 RttNom: 3
27099246.980: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27100246.980: DIMM 0 RttNom: 3
27101246.980: DIMM 0 RttWr: 2
27102246.980: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27103246.980: DIMM 0 RttWr: 2
27104246.981: DIMM 1 RttNom: 3
27105246.981: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27106246.981: DIMM 0 RttNom: 3
27107246.981: DIMM 1 RttWr: 2
27108246.981: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27109246.981: DIMM 0 RttWr: 2
27110246.981: DIMM 1 RttNom: 3
27111246.981: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27112246.981: DIMM 0 RttNom: 3
27113246.981: DIMM 1 RttWr: 2
27114246.981: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27115246.981: DIMM 0 RttWr: 2
27116246.981: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
27117246.981: <09>Lane 00 initial seed: 0041
27118246.981: <09>Lane 01 initial seed: 0041
27119246.981: <09>Lane 02 initial seed: 0041
27120246.981: <09>Lane 03 initial seed: 0041
27121246.981: <09>Lane 04 initial seed: 0041
27122246.981: <09>Lane 05 initial seed: 0041
27123246.981: <09>Lane 06 initial seed: 0041
27124246.981: <09>Lane 07 initial seed: 0041
27125246.981: <09>Lane 08 initial seed: 0041
27126246.981: <09>Lane 00 nibble 1 raw readback: 004a
27127246.981: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
27128246.981: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
27129246.981: <09>Lane 01 nibble 1 raw readback: 0047
27130246.981: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
27131246.981: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
27132246.981: <09>Lane 02 nibble 1 raw readback: 0044
27133246.981: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
27134246.981: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
27135246.981: <09>Lane 03 nibble 1 raw readback: 0042
27136246.981: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0042
27137246.981: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
27138246.981: <09>Lane 04 nibble 1 raw readback: 0039
27139246.981: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
27140246.981: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
27141246.981: <09>Lane 05 nibble 1 raw readback: 003c
27142246.981: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
27143246.981: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
27144246.981: <09>Lane 06 nibble 1 raw readback: 003f
27145246.981: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
27146246.981: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
27147246.981: <09>Lane 07 nibble 1 raw readback: 0040
27148246.981: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
27149246.981: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
27150246.981: <09>Lane 08 nibble 1 raw readback: 003b
27151246.981: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
27152246.981: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
27153246.981: <09>original critical gross delay: 0
27154246.981: <09>new critical gross delay: 0
27155246.981: DIMM 0 RttNom: 3
27156246.981: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27157246.981: DIMM 0 RttNom: 3
27158246.981: DIMM 0 RttWr: 2
27159246.981: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27160246.981: DIMM 0 RttWr: 2
27161246.981: DIMM 0 RttNom: 3
27162246.981: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27163246.981: DIMM 0 RttNom: 3
27164246.981: DIMM 0 RttWr: 2
27165246.981: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27166246.982: DIMM 0 RttWr: 2
27167246.981: DIMM 1 RttNom: 3
27168246.981: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27169246.982: DIMM 0 RttNom: 3
27170246.982: DIMM 1 RttWr: 2
27171246.982: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27172246.982: DIMM 0 RttWr: 2
27173246.982: DIMM 1 RttNom: 3
27174246.982: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27175246.982: DIMM 0 RttNom: 3
27176246.982: DIMM 1 RttWr: 2
27177246.982: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27178246.982: DIMM 0 RttWr: 2
27179246.982: AgesaHwWlPhase1: training nibble 0
27180246.982: DIMM 1 RttNom: 3
27181246.982: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27182246.982: DIMM 1 RttWr: 2
27183246.982: DIMM 1 RttWr: 2
27184246.982: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27185246.982: DIMM 1 RttWr: 2
27186246.982: DIMM 1 RttNom: 3
27187246.982: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27188246.982: DIMM 1 RttNom: 3
27189246.982: DIMM 1 RttWr: 2
27190246.982: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27191246.982: DIMM 1 RttWr: 2
27192246.982: DIMM 0 RttNom: 3
27193246.982: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27194246.982: DIMM 1 RttNom: 3
27195246.982: DIMM 0 RttWr: 2
27196246.982: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27197246.982: DIMM 1 RttWr: 2
27198246.982: DIMM 0 RttNom: 3
27199246.982: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27200246.982: DIMM 1 RttNom: 3
27201246.982: DIMM 0 RttWr: 2
27202246.982: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27203246.982: DIMM 1 RttWr: 2
27204246.982: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
27205246.982: <09>Lane 00 initial seed: 0041
27206246.982: <09>Lane 01 initial seed: 0041
27207246.982: <09>Lane 02 initial seed: 0041
27208246.982: <09>Lane 03 initial seed: 0041
27209246.982: <09>Lane 04 initial seed: 0041
27210246.982: <09>Lane 05 initial seed: 0041
27211246.982: <09>Lane 06 initial seed: 0041
27212246.982: <09>Lane 07 initial seed: 0041
27213246.982: <09>Lane 08 initial seed: 0041
27214246.982: <09>Lane 00 nibble 0 raw readback: 003f
27215246.982: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
27216246.982: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
27217246.982: <09>Lane 01 nibble 0 raw readback: 003c
27218246.982: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
27219246.982: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
27220246.982: <09>Lane 02 nibble 0 raw readback: 0038
27221246.982: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
27222246.982: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
27223246.982: <09>Lane 03 nibble 0 raw readback: 0036
27224246.982: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
27225246.982: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
27226246.982: <09>Lane 04 nibble 0 raw readback: 002d
27227246.982: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002d
27228246.982: <09>Lane 04 nibble 0 adjusted value (post nibble): 002d
27229246.982: <09>Lane 05 nibble 0 raw readback: 0030
27230246.982: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0030
27231246.982: <09>Lane 05 nibble 0 adjusted value (post nibble): 0030
27232246.982: <09>Lane 06 nibble 0 raw readback: 0033
27233246.982: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
27234246.982: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
27235246.982: <09>Lane 07 nibble 0 raw readback: 0036
27236246.982: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
27237246.982: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
27238246.982: <09>Lane 08 nibble 0 raw readback: 0030
27239246.982: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
27240246.982: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
27241246.983: AgesaHwWlPhase1: training nibble 1
27242246.983: DIMM 1 RttNom: 3
27243246.983: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27244246.983: DIMM 1 RttWr: 2
27245246.983: DIMM 1 RttWr: 2
27246246.983: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27247246.983: DIMM 1 RttWr: 2
27248246.983: DIMM 1 RttNom: 3
27249246.983: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27250246.983: DIMM 1 RttNom: 3
27251246.983: DIMM 1 RttWr: 2
27252246.983: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27253246.983: DIMM 1 RttWr: 2
27254246.983: DIMM 0 RttNom: 3
27255246.983: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27256246.983: DIMM 1 RttNom: 3
27257246.983: DIMM 0 RttWr: 2
27258246.983: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27259246.983: DIMM 1 RttWr: 2
27260246.983: DIMM 0 RttNom: 3
27261246.983: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27262246.983: DIMM 1 RttNom: 3
27263246.983: DIMM 0 RttWr: 2
27264246.983: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27265246.983: DIMM 1 RttWr: 2
27266246.983: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
27267246.983: <09>Lane 00 initial seed: 0041
27268246.983: <09>Lane 01 initial seed: 0041
27269246.983: <09>Lane 02 initial seed: 0041
27270246.983: <09>Lane 03 initial seed: 0041
27271246.983: <09>Lane 04 initial seed: 0041
27272246.983: <09>Lane 05 initial seed: 0041
27273246.983: <09>Lane 06 initial seed: 0041
27274246.983: <09>Lane 07 initial seed: 0041
27275246.983: <09>Lane 08 initial seed: 0041
27276246.983: <09>Lane 00 nibble 1 raw readback: 003e
27277246.983: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003e
27278246.983: <09>Lane 00 nibble 1 adjusted value (post nibble): 003f
27279246.983: <09>Lane 01 nibble 1 raw readback: 003c
27280246.983: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
27281246.983: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
27282246.983: <09>Lane 02 nibble 1 raw readback: 0038
27283246.983: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0038
27284246.983: <09>Lane 02 nibble 1 adjusted value (post nibble): 003c
27285246.983: <09>Lane 03 nibble 1 raw readback: 0037
27286246.983: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
27287246.983: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
27288246.983: <09>Lane 04 nibble 1 raw readback: 002d
27289246.983: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002d
27290246.983: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
27291246.983: <09>Lane 05 nibble 1 raw readback: 0030
27292246.983: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0030
27293246.983: <09>Lane 05 nibble 1 adjusted value (post nibble): 0038
27294246.983: <09>Lane 06 nibble 1 raw readback: 0033
27295246.983: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
27296246.983: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
27297246.983: <09>Lane 07 nibble 1 raw readback: 0035
27298246.983: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0035
27299246.983: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
27300246.983: <09>Lane 08 nibble 1 raw readback: 002f
27301246.983: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
27302246.983: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
27303246.983: <09>original critical gross delay: 0
27304246.983: <09>new critical gross delay: 0
27305246.984: DIMM 1 RttNom: 3
27306246.984: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27307246.984: DIMM 1 RttNom: 3
27308246.984: DIMM 1 RttWr: 2
27309246.984: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27310246.984: DIMM 1 RttWr: 2
27311246.984: DIMM 1 RttNom: 3
27312246.984: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27313246.984: DIMM 1 RttNom: 3
27314246.984: DIMM 1 RttWr: 2
27315246.984: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27316246.984: DIMM 1 RttWr: 2
27317246.984: DIMM 0 RttNom: 3
27318246.984: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27319246.984: DIMM 1 RttNom: 3
27320246.984: DIMM 0 RttWr: 2
27321246.984: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27322246.984: DIMM 1 RttWr: 2
27323246.984: DIMM 0 RttNom: 3
27324246.984: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27325246.984: DIMM 1 RttNom: 3
27326246.984: DIMM 0 RttWr: 2
27327246.984: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27328246.984: DIMM 1 RttWr: 2
27329246.984: activate_spd_rom() for node 03
27330246.984: enable_spd_node3()
27331246.984: AgesaHwWlPhase1: training nibble 0
27332246.984: DIMM 0 RttNom: 3
27333246.984: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27334246.984: DIMM 0 RttWr: 2
27335246.984: DIMM 0 RttWr: 2
27336246.984: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27337246.984: DIMM 0 RttWr: 2
27338246.984: DIMM 0 RttNom: 3
27339246.984: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27340246.984: DIMM 0 RttNom: 3
27341246.984: DIMM 0 RttWr: 2
27342246.984: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27343246.984: DIMM 0 RttWr: 2
27344246.984: DIMM 1 RttNom: 3
27345246.984: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27346246.984: DIMM 0 RttNom: 3
27347246.984: DIMM 1 RttWr: 2
27348246.984: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27349246.984: DIMM 0 RttWr: 2
27350246.984: DIMM 1 RttNom: 3
27351246.984: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27352246.984: DIMM 0 RttNom: 3
27353246.984: DIMM 1 RttWr: 2
27354246.984: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27355246.984: DIMM 0 RttWr: 2
27356246.985: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
27357246.985: <09>Lane 00 initial seed: 0041
27358246.985: <09>Lane 01 initial seed: 0041
27359246.985: <09>Lane 02 initial seed: 0041
27360246.985: <09>Lane 03 initial seed: 0041
27361246.985: <09>Lane 04 initial seed: 0041
27362246.985: <09>Lane 05 initial seed: 0041
27363246.985: <09>Lane 06 initial seed: 0041
27364246.985: <09>Lane 07 initial seed: 0041
27365246.985: <09>Lane 08 initial seed: 0041
27366246.985: <09>Lane 00 nibble 0 raw readback: 0043
27367246.985: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
27368246.985: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
27369246.985: <09>Lane 01 nibble 0 raw readback: 003e
27370246.985: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
27371246.985: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
27372246.985: <09>Lane 02 nibble 0 raw readback: 003b
27373246.985: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
27374246.985: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
27375246.985: <09>Lane 03 nibble 0 raw readback: 003b
27376246.985: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
27377246.985: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
27378246.985: <09>Lane 04 nibble 0 raw readback: 003a
27379246.985: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
27380246.985: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
27381246.985: <09>Lane 05 nibble 0 raw readback: 003c
27382246.985: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
27383246.985: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
27384246.985: <09>Lane 06 nibble 0 raw readback: 003e
27385246.985: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
27386246.985: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
27387246.985: <09>Lane 07 nibble 0 raw readback: 0041
27388246.985: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
27389246.985: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
27390246.985: <09>Lane 08 nibble 0 raw readback: 0036
27391246.985: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
27392246.985: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
27393246.985: AgesaHwWlPhase1: training nibble 1
27394246.985: DIMM 0 RttNom: 3
27395246.985: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27396246.985: DIMM 0 RttWr: 2
27397246.985: DIMM 0 RttWr: 2
27398246.985: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27399246.985: DIMM 0 RttWr: 2
27400246.985: DIMM 0 RttNom: 3
27401246.985: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27402246.985: DIMM 0 RttNom: 3
27403246.985: DIMM 0 RttWr: 2
27404246.985: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27405246.985: DIMM 0 RttWr: 2
27406246.985: DIMM 1 RttNom: 3
27407246.985: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27408246.985: DIMM 0 RttNom: 3
27409246.985: DIMM 1 RttWr: 2
27410246.985: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27411246.985: DIMM 0 RttWr: 2
27412246.985: DIMM 1 RttNom: 3
27413246.985: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27414246.985: DIMM 0 RttNom: 3
27415246.985: DIMM 1 RttWr: 2
27416246.985: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27417246.985: DIMM 0 RttWr: 2
27418246.985: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
27419246.985: <09>Lane 00 initial seed: 0041
27420246.985: <09>Lane 01 initial seed: 0041
27421246.985: <09>Lane 02 initial seed: 0041
27422246.985: <09>Lane 03 initial seed: 0041
27423246.986: <09>Lane 04 initial seed: 0041
27424246.986: <09>Lane 05 initial seed: 0041
27425246.986: <09>Lane 06 initial seed: 0041
27426246.986: <09>Lane 07 initial seed: 0041
27427246.986: <09>Lane 08 initial seed: 0041
27428246.986: <09>Lane 00 nibble 1 raw readback: 0044
27429246.986: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
27430246.986: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
27431246.986: <09>Lane 01 nibble 1 raw readback: 003f
27432246.986: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
27433246.986: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
27434246.986: <09>Lane 02 nibble 1 raw readback: 003c
27435246.986: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
27436246.986: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
27437246.986: <09>Lane 03 nibble 1 raw readback: 003a
27438246.986: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
27439246.986: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
27440246.986: <09>Lane 04 nibble 1 raw readback: 0038
27441246.986: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
27442246.986: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
27443246.986: <09>Lane 05 nibble 1 raw readback: 003b
27444246.986: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
27445246.986: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
27446246.986: <09>Lane 06 nibble 1 raw readback: 003e
27447246.986: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
27448246.986: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
27449246.986: <09>Lane 07 nibble 1 raw readback: 0041
27450246.986: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
27451246.986: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
27452246.986: <09>Lane 08 nibble 1 raw readback: 0037
27453246.986: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
27454246.986: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
27455246.986: <09>original critical gross delay: 0
27456246.986: <09>new critical gross delay: 0
27457246.986: DIMM 0 RttNom: 3
27458246.986: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27459246.986: DIMM 0 RttNom: 3
27460246.986: DIMM 0 RttWr: 2
27461246.986: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27462246.986: DIMM 0 RttWr: 2
27463246.986: DIMM 0 RttNom: 3
27464246.986: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27465246.986: DIMM 0 RttNom: 3
27466246.986: DIMM 0 RttWr: 2
27467246.986: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27468246.986: DIMM 0 RttWr: 2
27469246.986: DIMM 1 RttNom: 3
27470246.986: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27471246.986: DIMM 0 RttNom: 3
27472246.986: DIMM 1 RttWr: 2
27473246.986: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27474246.986: DIMM 0 RttWr: 2
27475246.986: DIMM 1 RttNom: 3
27476246.986: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27477246.986: DIMM 0 RttNom: 3
27478246.986: DIMM 1 RttWr: 2
27479246.986: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27480246.986: DIMM 0 RttWr: 2
27481246.986: AgesaHwWlPhase1: training nibble 0
27482246.986: DIMM 1 RttNom: 3
27483246.986: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27484246.986: DIMM 1 RttWr: 2
27485246.987: DIMM 1 RttWr: 2
27486246.986: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27487246.987: DIMM 1 RttWr: 2
27488246.987: DIMM 1 RttNom: 3
27489246.987: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27490246.987: DIMM 1 RttNom: 3
27491246.987: DIMM 1 RttWr: 2
27492246.987: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27493246.987: DIMM 1 RttWr: 2
27494246.987: DIMM 0 RttNom: 3
27495246.987: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27496246.987: DIMM 1 RttNom: 3
27497246.987: DIMM 0 RttWr: 2
27498246.987: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27499246.987: DIMM 1 RttWr: 2
27500246.987: DIMM 0 RttNom: 3
27501246.987: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27502246.987: DIMM 1 RttNom: 3
27503246.987: DIMM 0 RttWr: 2
27504246.987: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27505246.987: DIMM 1 RttWr: 2
27506246.987: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
27507246.987: <09>Lane 00 initial seed: 0041
27508246.987: <09>Lane 01 initial seed: 0041
27509246.987: <09>Lane 02 initial seed: 0041
27510246.987: <09>Lane 03 initial seed: 0041
27511246.987: <09>Lane 04 initial seed: 0041
27512246.987: <09>Lane 05 initial seed: 0041
27513246.987: <09>Lane 06 initial seed: 0041
27514246.987: <09>Lane 07 initial seed: 0041
27515246.987: <09>Lane 08 initial seed: 0041
27516246.987: <09>Lane 00 nibble 0 raw readback: 0042
27517246.987: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0042
27518246.987: <09>Lane 00 nibble 0 adjusted value (post nibble): 0042
27519246.987: <09>Lane 01 nibble 0 raw readback: 003e
27520246.987: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
27521246.987: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
27522246.987: <09>Lane 02 nibble 0 raw readback: 003c
27523246.987: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
27524246.987: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
27525246.987: <09>Lane 03 nibble 0 raw readback: 003b
27526246.987: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
27527246.987: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
27528246.987: <09>Lane 04 nibble 0 raw readback: 0038
27529246.987: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
27530246.987: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
27531246.987: <09>Lane 05 nibble 0 raw readback: 003b
27532246.987: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
27533246.987: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
27534246.987: <09>Lane 06 nibble 0 raw readback: 003d
27535246.987: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
27536246.987: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
27537246.987: <09>Lane 07 nibble 0 raw readback: 0040
27538246.987: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
27539246.987: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
27540246.987: <09>Lane 08 nibble 0 raw readback: 0037
27541246.987: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
27542246.987: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
27543246.987: AgesaHwWlPhase1: training nibble 1
27544246.987: DIMM 1 RttNom: 3
27545246.987: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27546246.987: DIMM 1 RttWr: 2
27547246.987: DIMM 1 RttWr: 2
27548246.987: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27549246.987: DIMM 1 RttWr: 2
27550246.987: DIMM 1 RttNom: 3
27551246.987: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27552246.987: DIMM 1 RttNom: 3
27553246.987: DIMM 1 RttWr: 2
27554246.987: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27555246.987: DIMM 1 RttWr: 2
27556246.987: DIMM 0 RttNom: 3
27557246.987: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27558246.987: DIMM 1 RttNom: 3
27559246.988: DIMM 0 RttWr: 2
27560246.988: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27561246.988: DIMM 1 RttWr: 2
27562246.988: DIMM 0 RttNom: 3
27563246.988: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27564246.988: DIMM 1 RttNom: 3
27565246.988: DIMM 0 RttWr: 2
27566246.988: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27567246.988: DIMM 1 RttWr: 2
27568246.988: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
27569246.988: <09>Lane 00 initial seed: 0041
27570246.988: <09>Lane 01 initial seed: 0041
27571246.988: <09>Lane 02 initial seed: 0041
27572246.988: <09>Lane 03 initial seed: 0041
27573246.988: <09>Lane 04 initial seed: 0041
27574246.988: <09>Lane 05 initial seed: 0041
27575246.988: <09>Lane 06 initial seed: 0041
27576246.988: <09>Lane 07 initial seed: 0041
27577246.988: <09>Lane 08 initial seed: 0041
27578246.988: <09>Lane 00 nibble 1 raw readback: 0043
27579246.988: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
27580246.988: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
27581246.988: <09>Lane 01 nibble 1 raw readback: 003f
27582246.988: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
27583246.988: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
27584246.988: <09>Lane 02 nibble 1 raw readback: 003c
27585246.988: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
27586246.988: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
27587246.988: <09>Lane 03 nibble 1 raw readback: 003c
27588246.988: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
27589246.988: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
27590246.988: <09>Lane 04 nibble 1 raw readback: 0038
27591246.988: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
27592246.988: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
27593246.988: <09>Lane 05 nibble 1 raw readback: 003b
27594246.988: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
27595246.988: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
27596246.988: <09>Lane 06 nibble 1 raw readback: 003c
27597246.988: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003c
27598246.988: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
27599246.988: <09>Lane 07 nibble 1 raw readback: 0040
27600246.988: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
27601246.988: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
27602246.988: <09>Lane 08 nibble 1 raw readback: 0036
27603246.988: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
27604246.988: <09>Lane 08 nibble 1 adjusted value (post nibble): 003b
27605246.988: <09>original critical gross delay: 0
27606246.988: <09>new critical gross delay: 0
27607246.988: DIMM 1 RttNom: 3
27608246.988: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
27609246.988: DIMM 1 RttNom: 3
27610246.988: DIMM 1 RttWr: 2
27611246.988: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
27612246.988: DIMM 1 RttWr: 2
27613246.988: DIMM 1 RttNom: 3
27614246.988: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
27615246.988: DIMM 1 RttNom: 3
27616246.988: DIMM 1 RttWr: 2
27617246.988: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
27618246.988: DIMM 1 RttWr: 2
27619246.988: DIMM 0 RttNom: 3
27620246.988: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
27621246.988: DIMM 1 RttNom: 3
27622246.988: DIMM 0 RttWr: 2
27623246.988: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
27624246.988: DIMM 1 RttWr: 2
27625246.989: DIMM 0 RttNom: 3
27626246.989: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
27627246.989: DIMM 1 RttNom: 3
27628246.989: DIMM 0 RttWr: 2
27629246.989: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
27630246.989: DIMM 1 RttWr: 2
27631246.989: AgesaHwWlPhase1: training nibble 0
27632246.989: DIMM 0 RttNom: 3
27633246.989: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27634246.989: DIMM 0 RttWr: 2
27635246.989: DIMM 0 RttWr: 2
27636246.989: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27637246.989: DIMM 0 RttWr: 2
27638246.989: DIMM 0 RttNom: 3
27639246.989: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27640246.989: DIMM 0 RttNom: 3
27641246.989: DIMM 0 RttWr: 2
27642246.989: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27643246.989: DIMM 0 RttWr: 2
27644246.989: DIMM 1 RttNom: 3
27645246.989: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27646246.989: DIMM 0 RttNom: 3
27647246.989: DIMM 1 RttWr: 2
27648246.989: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27649246.989: DIMM 0 RttWr: 2
27650246.989: DIMM 1 RttNom: 3
27651246.989: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27652246.989: DIMM 0 RttNom: 3
27653246.989: DIMM 1 RttWr: 2
27654246.989: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27655246.989: DIMM 0 RttWr: 2
27656246.989: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
27657246.989: <09>Lane 00 initial seed: 0041
27658246.989: <09>Lane 01 initial seed: 0041
27659246.989: <09>Lane 02 initial seed: 0041
27660246.989: <09>Lane 03 initial seed: 0041
27661246.989: <09>Lane 04 initial seed: 0041
27662246.989: <09>Lane 05 initial seed: 0041
27663246.989: <09>Lane 06 initial seed: 0041
27664246.989: <09>Lane 07 initial seed: 0041
27665246.989: <09>Lane 08 initial seed: 0041
27666246.989: <09>Lane 00 nibble 0 raw readback: 0044
27667246.989: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
27668246.989: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
27669246.989: <09>Lane 01 nibble 0 raw readback: 003f
27670246.989: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
27671246.989: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
27672246.989: <09>Lane 02 nibble 0 raw readback: 003d
27673246.989: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
27674246.989: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
27675246.989: <09>Lane 03 nibble 0 raw readback: 003a
27676246.989: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
27677246.989: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
27678246.989: <09>Lane 04 nibble 0 raw readback: 003a
27679246.989: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
27680246.989: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
27681246.989: <09>Lane 05 nibble 0 raw readback: 003d
27682246.989: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
27683246.989: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
27684246.989: <09>Lane 06 nibble 0 raw readback: 0040
27685246.989: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
27686246.989: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
27687246.989: <09>Lane 07 nibble 0 raw readback: 0043
27688246.989: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
27689246.989: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
27690246.989: <09>Lane 08 nibble 0 raw readback: 0037
27691246.989: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
27692246.990: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
27693246.989: AgesaHwWlPhase1: training nibble 1
27694246.990: DIMM 0 RttNom: 3
27695246.990: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27696246.990: DIMM 0 RttWr: 2
27697246.990: DIMM 0 RttWr: 2
27698246.990: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27699246.990: DIMM 0 RttWr: 2
27700246.990: DIMM 0 RttNom: 3
27701246.990: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27702246.990: DIMM 0 RttNom: 3
27703246.990: DIMM 0 RttWr: 2
27704246.990: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27705246.990: DIMM 0 RttWr: 2
27706246.990: DIMM 1 RttNom: 3
27707246.990: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27708246.990: DIMM 0 RttNom: 3
27709246.990: DIMM 1 RttWr: 2
27710246.990: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27711246.990: DIMM 0 RttWr: 2
27712246.990: DIMM 1 RttNom: 3
27713246.990: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27714246.990: DIMM 0 RttNom: 3
27715246.990: DIMM 1 RttWr: 2
27716246.990: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27717246.990: DIMM 0 RttWr: 2
27718246.990: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
27719246.990: <09>Lane 00 initial seed: 0041
27720246.990: <09>Lane 01 initial seed: 0041
27721246.990: <09>Lane 02 initial seed: 0041
27722246.990: <09>Lane 03 initial seed: 0041
27723246.990: <09>Lane 04 initial seed: 0041
27724246.990: <09>Lane 05 initial seed: 0041
27725246.990: <09>Lane 06 initial seed: 0041
27726246.990: <09>Lane 07 initial seed: 0041
27727246.990: <09>Lane 08 initial seed: 0041
27728246.990: <09>Lane 00 nibble 1 raw readback: 0044
27729246.990: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
27730246.990: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
27731246.990: <09>Lane 01 nibble 1 raw readback: 0041
27732246.990: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
27733246.990: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
27734246.990: <09>Lane 02 nibble 1 raw readback: 003d
27735246.990: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
27736246.990: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
27737246.990: <09>Lane 03 nibble 1 raw readback: 003a
27738246.990: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
27739246.990: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
27740246.990: <09>Lane 04 nibble 1 raw readback: 0039
27741246.990: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
27742246.990: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
27743246.990: <09>Lane 05 nibble 1 raw readback: 003c
27744246.990: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
27745246.990: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
27746246.990: <09>Lane 06 nibble 1 raw readback: 003f
27747246.990: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
27748246.990: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
27749246.990: <09>Lane 07 nibble 1 raw readback: 0042
27750246.990: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
27751246.990: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
27752246.990: <09>Lane 08 nibble 1 raw readback: 0038
27753246.990: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
27754246.990: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
27755246.990: <09>original critical gross delay: 0
27756246.990: <09>new critical gross delay: 0
27757246.990: DIMM 0 RttNom: 3
27758246.990: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27759246.991: DIMM 0 RttNom: 3
27760246.991: DIMM 0 RttWr: 2
27761246.991: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27762246.991: DIMM 0 RttWr: 2
27763246.991: DIMM 0 RttNom: 3
27764246.991: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27765246.991: DIMM 0 RttNom: 3
27766246.991: DIMM 0 RttWr: 2
27767246.991: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27768246.991: DIMM 0 RttWr: 2
27769246.991: DIMM 1 RttNom: 3
27770246.991: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27771246.991: DIMM 0 RttNom: 3
27772246.991: DIMM 1 RttWr: 2
27773246.991: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27774246.991: DIMM 0 RttWr: 2
27775246.991: DIMM 1 RttNom: 3
27776246.991: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27777246.991: DIMM 0 RttNom: 3
27778246.991: DIMM 1 RttWr: 2
27779246.991: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27780246.991: DIMM 0 RttWr: 2
27781246.991: AgesaHwWlPhase1: training nibble 0
27782246.991: DIMM 1 RttNom: 3
27783246.991: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27784246.991: DIMM 1 RttWr: 2
27785246.991: DIMM 1 RttWr: 2
27786246.991: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27787246.991: DIMM 1 RttWr: 2
27788246.991: DIMM 1 RttNom: 3
27789246.991: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27790246.991: DIMM 1 RttNom: 3
27791246.991: DIMM 1 RttWr: 2
27792246.991: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27793246.991: DIMM 1 RttWr: 2
27794246.991: DIMM 0 RttNom: 3
27795246.991: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27796246.991: DIMM 1 RttNom: 3
27797246.991: DIMM 0 RttWr: 2
27798246.991: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27799246.991: DIMM 1 RttWr: 2
27800246.991: DIMM 0 RttNom: 3
27801246.991: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27802246.991: DIMM 1 RttNom: 3
27803246.991: DIMM 0 RttWr: 2
27804246.991: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27805246.991: DIMM 1 RttWr: 2
27806246.991: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
27807246.991: <09>Lane 00 initial seed: 0041
27808246.991: <09>Lane 01 initial seed: 0041
27809246.991: <09>Lane 02 initial seed: 0041
27810246.991: <09>Lane 03 initial seed: 0041
27811246.991: <09>Lane 04 initial seed: 0041
27812246.991: <09>Lane 05 initial seed: 0041
27813246.991: <09>Lane 06 initial seed: 0041
27814246.991: <09>Lane 07 initial seed: 0041
27815246.991: <09>Lane 08 initial seed: 0041
27816246.991: <09>Lane 00 nibble 0 raw readback: 0044
27817246.991: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
27818246.991: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
27819246.991: <09>Lane 01 nibble 0 raw readback: 0040
27820246.991: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
27821246.991: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
27822246.991: <09>Lane 02 nibble 0 raw readback: 003c
27823246.992: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
27824246.992: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
27825246.992: <09>Lane 03 nibble 0 raw readback: 003a
27826246.992: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
27827246.992: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
27828246.992: <09>Lane 04 nibble 0 raw readback: 0039
27829246.992: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
27830246.992: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
27831246.992: <09>Lane 05 nibble 0 raw readback: 003d
27832246.992: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
27833246.992: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
27834246.992: <09>Lane 06 nibble 0 raw readback: 0040
27835246.992: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
27836246.992: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
27837246.992: <09>Lane 07 nibble 0 raw readback: 0042
27838246.992: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
27839246.992: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
27840246.992: <09>Lane 08 nibble 0 raw readback: 0039
27841246.992: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
27842246.992: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
27843246.992: AgesaHwWlPhase1: training nibble 1
27844246.992: DIMM 1 RttNom: 3
27845246.992: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27846246.992: DIMM 1 RttWr: 2
27847246.992: DIMM 1 RttWr: 2
27848246.992: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27849246.992: DIMM 1 RttWr: 2
27850246.992: DIMM 1 RttNom: 3
27851246.992: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27852246.992: DIMM 1 RttNom: 3
27853246.992: DIMM 1 RttWr: 2
27854246.992: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27855246.992: DIMM 1 RttWr: 2
27856246.992: DIMM 0 RttNom: 3
27857246.992: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27858246.992: DIMM 1 RttNom: 3
27859246.992: DIMM 0 RttWr: 2
27860246.992: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27861246.992: DIMM 1 RttWr: 2
27862246.992: DIMM 0 RttNom: 3
27863246.992: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27864246.992: DIMM 1 RttNom: 3
27865246.992: DIMM 0 RttWr: 2
27866246.992: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27867246.992: DIMM 1 RttWr: 2
27868246.992: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
27869246.992: <09>Lane 00 initial seed: 0041
27870246.992: <09>Lane 01 initial seed: 0041
27871246.992: <09>Lane 02 initial seed: 0041
27872246.992: <09>Lane 03 initial seed: 0041
27873246.992: <09>Lane 04 initial seed: 0041
27874246.992: <09>Lane 05 initial seed: 0041
27875246.992: <09>Lane 06 initial seed: 0041
27876246.992: <09>Lane 07 initial seed: 0041
27877246.992: <09>Lane 08 initial seed: 0041
27878246.992: <09>Lane 00 nibble 1 raw readback: 0044
27879246.992: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
27880246.992: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
27881246.992: <09>Lane 01 nibble 1 raw readback: 0041
27882246.992: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
27883246.992: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
27884246.992: <09>Lane 02 nibble 1 raw readback: 003c
27885246.992: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
27886246.992: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
27887246.992: <09>Lane 03 nibble 1 raw readback: 003b
27888246.992: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
27889246.992: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
27890246.992: <09>Lane 04 nibble 1 raw readback: 0038
27891246.992: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
27892246.992: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
27893246.992: <09>Lane 05 nibble 1 raw readback: 003c
27894246.992: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
27895246.992: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
27896246.992: <09>Lane 06 nibble 1 raw readback: 003f
27897246.992: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
27898246.992: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
27899246.993: <09>Lane 07 nibble 1 raw readback: 0042
27900246.993: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
27901246.993: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
27902246.993: <09>Lane 08 nibble 1 raw readback: 0037
27903246.993: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
27904246.993: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
27905246.993: <09>original critical gross delay: 0
27906246.993: <09>new critical gross delay: 0
27907246.993: DIMM 1 RttNom: 3
27908246.993: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
27909246.993: DIMM 1 RttNom: 3
27910246.993: DIMM 1 RttWr: 2
27911246.993: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
27912246.993: DIMM 1 RttWr: 2
27913246.993: DIMM 1 RttNom: 3
27914246.993: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
27915246.993: DIMM 1 RttNom: 3
27916246.993: DIMM 1 RttWr: 2
27917246.993: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
27918246.993: DIMM 1 RttWr: 2
27919246.993: DIMM 0 RttNom: 3
27920246.993: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
27921246.993: DIMM 1 RttNom: 3
27922246.993: DIMM 0 RttWr: 2
27923246.993: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
27924246.993: DIMM 1 RttWr: 2
27925246.993: DIMM 0 RttNom: 3
27926246.993: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
27927246.993: DIMM 1 RttNom: 3
27928246.993: DIMM 0 RttWr: 2
27929246.993: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
27930246.993: DIMM 1 RttWr: 2
27931246.995: fam15_receiver_enable_training_seed: using seed: 0054
27932246.996: fam15_receiver_enable_training_seed: using seed: 0054
27933246.996: fam15_receiver_enable_training_seed: using seed: 0054
27934246.997: fam15_receiver_enable_training_seed: using seed: 0054
27935246.997: fam15_receiver_enable_training_seed: using seed: 0054
27936246.997: fam15_receiver_enable_training_seed: using seed: 0054
27937246.997: fam15_receiver_enable_training_seed: using seed: 0054
27938246.997: fam15_receiver_enable_training_seed: using seed: 0054
27939246.997: fam15_receiver_enable_training_seed: using seed: 004d
27940246.997: fam15_receiver_enable_training_seed: using seed: 004d
27941246.997: fam15_receiver_enable_training_seed: using seed: 004d
27942246.997: fam15_receiver_enable_training_seed: using seed: 004d
27943246.997: fam15_receiver_enable_training_seed: using seed: 004d
27944246.997: fam15_receiver_enable_training_seed: using seed: 004d
27945246.997: fam15_receiver_enable_training_seed: using seed: 004d
27946246.997: fam15_receiver_enable_training_seed: using seed: 004d
27947246.998: TrainRcvrEn: Status 2205
27948246.998: TrainRcvrEn: ErrStatus 0
27949246.998: TrainRcvrEn: ErrCode 0
27950246.998: TrainRcvrEn: Done
27951246.998:
27952246.998: fam15_receiver_enable_training_seed: using seed: 0045
27953246.998: fam15_receiver_enable_training_seed: using seed: 0045
27954246.999: fam15_receiver_enable_training_seed: using seed: 0045
27955246.999: fam15_receiver_enable_training_seed: using seed: 0045
27956246.999: fam15_receiver_enable_training_seed: using seed: 0045
27957246.999: fam15_receiver_enable_training_seed: using seed: 0045
27958246.999: fam15_receiver_enable_training_seed: using seed: 0045
27959246.999: fam15_receiver_enable_training_seed: using seed: 0045
27960246.999: fam15_receiver_enable_training_seed: using seed: 0040
27961246.999: fam15_receiver_enable_training_seed: using seed: 0040
27962246.999: fam15_receiver_enable_training_seed: using seed: 0040
27963246.999: fam15_receiver_enable_training_seed: using seed: 0040
27964246.999: fam15_receiver_enable_training_seed: using seed: 0040
27965247.000: fam15_receiver_enable_training_seed: using seed: 0040
27966247.000: fam15_receiver_enable_training_seed: using seed: 0040
27967247.000: fam15_receiver_enable_training_seed: using seed: 0040
27968247.000: TrainRcvrEn: Status 2005
27969247.000: TrainRcvrEn: ErrStatus 0
27970247.000: TrainRcvrEn: ErrCode 0
27971247.000: TrainRcvrEn: Done
27972247.000:
27973247.000: fam15_receiver_enable_training_seed: using seed: 0054
27974247.000: fam15_receiver_enable_training_seed: using seed: 0054
27975247.000: fam15_receiver_enable_training_seed: using seed: 0054
27976247.000: fam15_receiver_enable_training_seed: using seed: 0054
27977247.000: fam15_receiver_enable_training_seed: using seed: 0054
27978247.001: fam15_receiver_enable_training_seed: using seed: 0054
27979247.001: fam15_receiver_enable_training_seed: using seed: 0054
27980247.001: fam15_receiver_enable_training_seed: using seed: 0054
27981247.001: fam15_receiver_enable_training_seed: using seed: 004d
27982247.001: fam15_receiver_enable_training_seed: using seed: 004d
27983247.001: fam15_receiver_enable_training_seed: using seed: 004d
27984247.001: fam15_receiver_enable_training_seed: using seed: 004d
27985247.001: fam15_receiver_enable_training_seed: using seed: 004d
27986247.001: fam15_receiver_enable_training_seed: using seed: 004d
27987247.001: fam15_receiver_enable_training_seed: using seed: 004d
27988247.001: fam15_receiver_enable_training_seed: using seed: 004d
27989247.002: TrainRcvrEn: Status 2005
27990247.002: TrainRcvrEn: ErrStatus 0
27991247.002: TrainRcvrEn: ErrCode 0
27992247.002: TrainRcvrEn: Done
27993247.002:
27994247.002: fam15_receiver_enable_training_seed: using seed: 0045
27995247.002: fam15_receiver_enable_training_seed: using seed: 0045
27996247.002: fam15_receiver_enable_training_seed: using seed: 0045
27997247.002: fam15_receiver_enable_training_seed: using seed: 0045
27998247.002: fam15_receiver_enable_training_seed: using seed: 0045
27999247.002: fam15_receiver_enable_training_seed: using seed: 0045
28000247.002: fam15_receiver_enable_training_seed: using seed: 0045
28001247.002: fam15_receiver_enable_training_seed: using seed: 0045
28002247.002: fam15_receiver_enable_training_seed: using seed: 0040
28003247.003: fam15_receiver_enable_training_seed: using seed: 0040
28004247.003: fam15_receiver_enable_training_seed: using seed: 0040
28005247.003: fam15_receiver_enable_training_seed: using seed: 0040
28006247.003: fam15_receiver_enable_training_seed: using seed: 0040
28007247.003: fam15_receiver_enable_training_seed: using seed: 0040
28008247.003: fam15_receiver_enable_training_seed: using seed: 0040
28009247.003: fam15_receiver_enable_training_seed: using seed: 0040
28010247.003: TrainRcvrEn: Status 2005
28011247.003: TrainRcvrEn: ErrStatus 0
28012247.003: TrainRcvrEn: ErrCode 0
28013247.003: TrainRcvrEn: Done
28014247.003:
28015247.003: activate_spd_rom() for node 00
28016247.003: enable_spd_node0()
28017247.004: SetTargetFreq: Start
28018247.004: SetTargetFreq: Node 0: New frequency code: 0006
28019247.004: ChangeMemClk: Start
28020247.004: set_2t_configuration: Start
28021247.004: set_2t_configuration: Done
28022247.004: mct_BeforePlatformSpec: Start
28023247.004: mct_BeforePlatformSpec: Done
28024247.004: mct_PlatformSpec: Start
28025247.005: Programmed DCT 0 timing/termination pattern 00000000 20222222
28026247.005: mct_PlatformSpec: Done
28027247.005: set_2t_configuration: Start
28028247.005: set_2t_configuration: Done
28029247.005: mct_BeforePlatformSpec: Start
28030247.005: mct_BeforePlatformSpec: Done
28031247.005: mct_PlatformSpec: Start
28032247.005: Programmed DCT 1 timing/termination pattern 00000000 20222222
28033247.005: mct_PlatformSpec: Done
28034247.005: ChangeMemClk: Done
28035247.005: phyAssistedMemFnceTraining: Start
28036247.005: phyAssistedMemFnceTraining: training node 0 DCT 0
28037247.005: phyAssistedMemFnceTraining: done training node 0 DCT 0
28038247.005: phyAssistedMemFnceTraining: training node 0 DCT 1
28039247.005: phyAssistedMemFnceTraining: done training node 0 DCT 1
28040247.005: phyAssistedMemFnceTraining: Done
28041247.005: InitPhyCompensation: DCT 0: Start
28042247.005: Waiting for predriver calibration to be applied...done!
28043247.005: InitPhyCompensation: DCT 0: Done
28044247.005: phyAssistedMemFnceTraining: Start
28045247.005: phyAssistedMemFnceTraining: training node 0 DCT 0
28046247.006: phyAssistedMemFnceTraining: done training node 0 DCT 0
28047247.006: phyAssistedMemFnceTraining: training node 0 DCT 1
28048247.006: phyAssistedMemFnceTraining: done training node 0 DCT 1
28049247.006: phyAssistedMemFnceTraining: Done
28050247.006: InitPhyCompensation: DCT 1: Start
28051247.006: Waiting for predriver calibration to be applied...done!
28052247.006: InitPhyCompensation: DCT 1: Done
28053247.006: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
28054247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28055247.006: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
28056247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28057247.006: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
28058247.006: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
28059247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28060247.007: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
28061247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28062247.006: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
28063247.007: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
28064247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28065247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
28066247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28067247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
28068247.007: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
28069247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28070247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
28071247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28072247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
28073247.007: SetTargetFreq: Done
28074247.007: SPD2ndTiming: Start
28075247.007: SPD2ndTiming: Done
28076247.007: mct_BeforeDramInit_Prod_D: Start
28077247.007: mct_ProgramODT_D: Start
28078247.007: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
28079247.007: mct_ProgramODT_D: Done
28080247.007: mct_BeforeDramInit_Prod_D: Done
28081247.007: mct_DramInit_Sw_D: Start
28082247.007: DIMM 0 RttWr: 2
28083247.007: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28084247.008: mct_SendMrsCmd: Start
28085247.008: mct_SendMrsCmd: Done
28086247.008: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
28087247.008: mct_SendMrsCmd: Start
28088247.008: mct_SendMrsCmd: Done
28089247.008: DIMM 0 RttNom: 3
28090247.008: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28091247.008: mct_SendMrsCmd: Start
28092247.008: mct_SendMrsCmd: Done
28093247.008: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
28094247.008: mct_SendMrsCmd: Start
28095247.008: mct_SendMrsCmd: Done
28096247.008: DIMM 0 RttWr: 2
28097247.008: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28098247.008: mct_SendMrsCmd: Start
28099247.008: mct_SendMrsCmd: Done
28100247.008: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
28101247.008: mct_SendMrsCmd: Start
28102247.008: mct_SendMrsCmd: Done
28103247.008: DIMM 0 RttNom: 3
28104247.008: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28105247.008: mct_SendMrsCmd: Start
28106247.008: mct_SendMrsCmd: Done
28107247.008: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
28108247.008: mct_SendMrsCmd: Start
28109247.008: mct_SendMrsCmd: Done
28110247.008: DIMM 1 RttWr: 2
28111247.008: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28112247.008: mct_SendMrsCmd: Start
28113247.008: mct_SendMrsCmd: Done
28114247.008: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
28115247.008: mct_SendMrsCmd: Start
28116247.008: mct_SendMrsCmd: Done
28117247.008: DIMM 1 RttNom: 3
28118247.008: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28119247.008: mct_SendMrsCmd: Start
28120247.008: mct_SendMrsCmd: Done
28121247.008: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
28122247.008: mct_SendMrsCmd: Start
28123247.008: mct_SendMrsCmd: Done
28124247.008: DIMM 1 RttWr: 2
28125247.008: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28126247.008: mct_SendMrsCmd: Start
28127247.008: mct_SendMrsCmd: Done
28128247.008: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
28129247.008: mct_SendMrsCmd: Start
28130247.008: mct_SendMrsCmd: Done
28131247.008: DIMM 1 RttNom: 3
28132247.008: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28133247.008: mct_SendMrsCmd: Start
28134247.008: mct_SendMrsCmd: Done
28135247.008: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
28136247.008: mct_SendMrsCmd: Start
28137247.008: mct_SendMrsCmd: Done
28138247.008: mct_DramInit_Sw_D: Done
28139247.009: AgesaHwWlPhase1: training nibble 0
28140247.009: DIMM 0 RttNom: 3
28141247.009: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28142247.009: DIMM 0 RttWr: 2
28143247.009: DIMM 0 RttWr: 2
28144247.009: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28145247.009: DIMM 0 RttWr: 2
28146247.009: DIMM 0 RttNom: 3
28147247.009: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28148247.009: DIMM 0 RttNom: 3
28149247.009: DIMM 0 RttWr: 2
28150247.009: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28151247.009: DIMM 0 RttWr: 2
28152247.009: DIMM 1 RttNom: 3
28153247.009: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28154247.009: DIMM 0 RttNom: 3
28155247.009: DIMM 1 RttWr: 2
28156247.009: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28157247.009: DIMM 0 RttWr: 2
28158247.009: DIMM 1 RttNom: 3
28159247.009: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28160247.009: DIMM 0 RttNom: 3
28161247.009: DIMM 1 RttWr: 2
28162247.009: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28163247.009: DIMM 0 RttWr: 2
28164247.009: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
28165247.010: <09>Lane 00 scaled delay: 0047
28166247.009: <09>Lane 00 new seed: 0047
28167247.010: <09>Lane 01 scaled delay: 0047
28168247.010: <09>Lane 01 new seed: 0047
28169247.010: <09>Lane 02 scaled delay: 0047
28170247.010: <09>Lane 02 new seed: 0047
28171247.010: <09>Lane 03 scaled delay: 0047
28172247.010: <09>Lane 03 new seed: 0047
28173247.010: <09>Lane 04 scaled delay: 0047
28174247.010: <09>Lane 04 new seed: 0047
28175247.010: <09>Lane 05 scaled delay: 0047
28176247.010: <09>Lane 05 new seed: 0047
28177247.010: <09>Lane 06 scaled delay: 0047
28178247.010: <09>Lane 06 new seed: 0047
28179247.010: <09>Lane 07 scaled delay: 0047
28180247.010: <09>Lane 07 new seed: 0047
28181247.010: <09>Lane 08 scaled delay: 0047
28182247.010: <09>Lane 08 new seed: 0047
28183247.010: <09>Lane 00 nibble 0 raw readback: 0050
28184247.010: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
28185247.010: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
28186247.010: <09>Lane 01 nibble 0 raw readback: 004a
28187247.010: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
28188247.010: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
28189247.010: <09>Lane 02 nibble 0 raw readback: 0048
28190247.010: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
28191247.010: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
28192247.010: <09>Lane 03 nibble 0 raw readback: 0044
28193247.010: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
28194247.010: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
28195247.010: <09>Lane 04 nibble 0 raw readback: 003a
28196247.010: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
28197247.010: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
28198247.010: <09>Lane 05 nibble 0 raw readback: 003e
28199247.010: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
28200247.010: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
28201247.010: <09>Lane 06 nibble 0 raw readback: 0040
28202247.010: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
28203247.010: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
28204247.010: <09>Lane 07 nibble 0 raw readback: 0043
28205247.010: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
28206247.010: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
28207247.010: <09>Lane 08 nibble 0 raw readback: 003c
28208247.010: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
28209247.010: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
28210247.010: AgesaHwWlPhase1: training nibble 1
28211247.010: DIMM 0 RttNom: 3
28212247.010: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28213247.010: DIMM 0 RttWr: 2
28214247.010: DIMM 0 RttWr: 2
28215247.010: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28216247.010: DIMM 0 RttWr: 2
28217247.010: DIMM 0 RttNom: 3
28218247.010: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28219247.010: DIMM 0 RttNom: 3
28220247.010: DIMM 0 RttWr: 2
28221247.010: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28222247.010: DIMM 0 RttWr: 2
28223247.010: DIMM 1 RttNom: 3
28224247.011: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28225247.011: DIMM 0 RttNom: 3
28226247.011: DIMM 1 RttWr: 2
28227247.011: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28228247.011: DIMM 0 RttWr: 2
28229247.011: DIMM 1 RttNom: 3
28230247.011: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28231247.011: DIMM 0 RttNom: 3
28232247.011: DIMM 1 RttWr: 2
28233247.011: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28234247.011: DIMM 0 RttWr: 2
28235247.011: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
28236247.011: <09>Lane 00 new seed: 0047
28237247.011: <09>Lane 01 new seed: 0047
28238247.011: <09>Lane 02 new seed: 0047
28239247.011: <09>Lane 03 new seed: 0047
28240247.011: <09>Lane 04 new seed: 0047
28241247.011: <09>Lane 05 new seed: 0047
28242247.011: <09>Lane 06 new seed: 0047
28243247.011: <09>Lane 07 new seed: 0047
28244247.011: <09>Lane 08 new seed: 0047
28245247.011: <09>Lane 00 nibble 1 raw readback: 004f
28246247.011: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
28247247.011: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
28248247.011: <09>Lane 01 nibble 1 raw readback: 004a
28249247.011: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
28250247.011: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
28251247.011: <09>Lane 02 nibble 1 raw readback: 0049
28252247.011: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
28253247.011: <09>Lane 02 nibble 1 adjusted value (post nibble): 0048
28254247.011: <09>Lane 03 nibble 1 raw readback: 0046
28255247.011: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
28256247.011: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
28257247.011: <09>Lane 04 nibble 1 raw readback: 003b
28258247.011: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
28259247.011: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
28260247.011: <09>Lane 05 nibble 1 raw readback: 003f
28261247.011: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003f
28262247.011: <09>Lane 05 nibble 1 adjusted value (post nibble): 0043
28263247.011: <09>Lane 06 nibble 1 raw readback: 0041
28264247.011: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
28265247.011: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
28266247.011: <09>Lane 07 nibble 1 raw readback: 0043
28267247.011: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0043
28268247.011: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
28269247.011: <09>Lane 08 nibble 1 raw readback: 003d
28270247.011: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
28271247.011: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
28272247.011: <09>original critical gross delay: 0
28273247.011: <09>new critical gross delay: 0
28274247.011: DIMM 0 RttNom: 3
28275247.011: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28276247.011: DIMM 0 RttNom: 3
28277247.011: DIMM 0 RttWr: 2
28278247.011: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28279247.011: DIMM 0 RttWr: 2
28280247.011: DIMM 0 RttNom: 3
28281247.011: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28282247.011: DIMM 0 RttNom: 3
28283247.011: DIMM 0 RttWr: 2
28284247.012: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28285247.012: DIMM 0 RttWr: 2
28286247.012: DIMM 1 RttNom: 3
28287247.012: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28288247.012: DIMM 0 RttNom: 3
28289247.012: DIMM 1 RttWr: 2
28290247.012: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28291247.012: DIMM 0 RttWr: 2
28292247.012: DIMM 1 RttNom: 3
28293247.012: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28294247.012: DIMM 0 RttNom: 3
28295247.012: DIMM 1 RttWr: 2
28296247.012: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28297247.012: DIMM 0 RttWr: 2
28298247.012: AgesaHwWlPhase1: training nibble 0
28299247.012: DIMM 1 RttNom: 3
28300247.012: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28301247.012: DIMM 1 RttWr: 2
28302247.012: DIMM 1 RttWr: 2
28303247.012: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28304247.012: DIMM 1 RttWr: 2
28305247.012: DIMM 1 RttNom: 3
28306247.012: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28307247.012: DIMM 1 RttNom: 3
28308247.012: DIMM 1 RttWr: 2
28309247.012: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28310247.012: DIMM 1 RttWr: 2
28311247.012: DIMM 0 RttNom: 3
28312247.012: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28313247.012: DIMM 1 RttNom: 3
28314247.012: DIMM 0 RttWr: 2
28315247.012: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28316247.012: DIMM 1 RttWr: 2
28317247.012: DIMM 0 RttNom: 3
28318247.012: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28319247.012: DIMM 1 RttNom: 3
28320247.012: DIMM 0 RttWr: 2
28321247.012: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28322247.012: DIMM 1 RttWr: 2
28323247.012: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
28324247.012: <09>Lane 00 scaled delay: 0047
28325247.012: <09>Lane 00 new seed: 0047
28326247.012: <09>Lane 01 scaled delay: 0047
28327247.012: <09>Lane 01 new seed: 0047
28328247.012: <09>Lane 02 scaled delay: 0047
28329247.012: <09>Lane 02 new seed: 0047
28330247.012: <09>Lane 03 scaled delay: 0047
28331247.012: <09>Lane 03 new seed: 0047
28332247.012: <09>Lane 04 scaled delay: 0047
28333247.012: <09>Lane 04 new seed: 0047
28334247.012: <09>Lane 05 scaled delay: 0047
28335247.012: <09>Lane 05 new seed: 0047
28336247.012: <09>Lane 06 scaled delay: 0047
28337247.012: <09>Lane 06 new seed: 0047
28338247.012: <09>Lane 07 scaled delay: 0047
28339247.012: <09>Lane 07 new seed: 0047
28340247.012: <09>Lane 08 scaled delay: 0047
28341247.012: <09>Lane 08 new seed: 0047
28342247.012: <09>Lane 00 nibble 0 raw readback: 0046
28343247.012: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
28344247.012: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
28345247.012: <09>Lane 01 nibble 0 raw readback: 003f
28346247.012: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
28347247.012: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
28348247.012: <09>Lane 02 nibble 0 raw readback: 003e
28349247.013: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
28350247.012: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
28351247.012: <09>Lane 03 nibble 0 raw readback: 003b
28352247.012: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
28353247.012: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
28354247.013: <09>Lane 04 nibble 0 raw readback: 0030
28355247.013: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
28356247.013: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
28357247.013: <09>Lane 05 nibble 0 raw readback: 0035
28358247.013: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
28359247.013: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
28360247.013: <09>Lane 06 nibble 0 raw readback: 0037
28361247.013: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
28362247.013: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
28363247.013: <09>Lane 07 nibble 0 raw readback: 003a
28364247.013: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
28365247.013: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
28366247.013: <09>Lane 08 nibble 0 raw readback: 0032
28367247.013: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
28368247.013: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
28369247.013: AgesaHwWlPhase1: training nibble 1
28370247.013: DIMM 1 RttNom: 3
28371247.013: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28372247.013: DIMM 1 RttWr: 2
28373247.013: DIMM 1 RttWr: 2
28374247.013: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28375247.013: DIMM 1 RttWr: 2
28376247.013: DIMM 1 RttNom: 3
28377247.013: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28378247.013: DIMM 1 RttNom: 3
28379247.013: DIMM 1 RttWr: 2
28380247.013: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28381247.013: DIMM 1 RttWr: 2
28382247.013: DIMM 0 RttNom: 3
28383247.013: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28384247.013: DIMM 1 RttNom: 3
28385247.013: DIMM 0 RttWr: 2
28386247.013: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28387247.013: DIMM 1 RttWr: 2
28388247.013: DIMM 0 RttNom: 3
28389247.013: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28390247.013: DIMM 1 RttNom: 3
28391247.013: DIMM 0 RttWr: 2
28392247.013: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28393247.013: DIMM 1 RttWr: 2
28394247.013: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
28395247.013: <09>Lane 00 new seed: 0047
28396247.013: <09>Lane 01 new seed: 0047
28397247.013: <09>Lane 02 new seed: 0047
28398247.013: <09>Lane 03 new seed: 0047
28399247.013: <09>Lane 04 new seed: 0047
28400247.013: <09>Lane 05 new seed: 0047
28401247.013: <09>Lane 06 new seed: 0047
28402247.013: <09>Lane 07 new seed: 0047
28403247.013: <09>Lane 08 new seed: 0047
28404247.013: <09>Lane 00 nibble 1 raw readback: 0046
28405247.013: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
28406247.013: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
28407247.013: <09>Lane 01 nibble 1 raw readback: 0040
28408247.013: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
28409247.013: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
28410247.013: <09>Lane 02 nibble 1 raw readback: 003f
28411247.013: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
28412247.013: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
28413247.013: <09>Lane 03 nibble 1 raw readback: 003b
28414247.013: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
28415247.013: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
28416247.013: <09>Lane 04 nibble 1 raw readback: 0030
28417247.013: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
28418247.013: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
28419247.013: <09>Lane 05 nibble 1 raw readback: 0035
28420247.013: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
28421247.013: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
28422247.013: <09>Lane 06 nibble 1 raw readback: 0036
28423247.013: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0036
28424247.013: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
28425247.013: <09>Lane 07 nibble 1 raw readback: 003a
28426247.013: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
28427247.013: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
28428247.013: <09>Lane 08 nibble 1 raw readback: 0032
28429247.013: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
28430247.013: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
28431247.013: <09>original critical gross delay: 0
28432247.013: <09>new critical gross delay: 0
28433247.014: DIMM 1 RttNom: 3
28434247.014: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28435247.014: DIMM 1 RttNom: 3
28436247.014: DIMM 1 RttWr: 2
28437247.014: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
28438247.014: DIMM 1 RttWr: 2
28439247.014: DIMM 1 RttNom: 3
28440247.014: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28441247.014: DIMM 1 RttNom: 3
28442247.014: DIMM 1 RttWr: 2
28443247.014: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
28444247.014: DIMM 1 RttWr: 2
28445247.014: DIMM 0 RttNom: 3
28446247.014: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28447247.014: DIMM 1 RttNom: 3
28448247.014: DIMM 0 RttWr: 2
28449247.014: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
28450247.014: DIMM 1 RttWr: 2
28451247.014: DIMM 0 RttNom: 3
28452247.014: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28453247.014: DIMM 1 RttNom: 3
28454247.014: DIMM 0 RttWr: 2
28455247.014: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
28456247.014: DIMM 1 RttWr: 2
28457247.014: SPD2ndTiming: Start
28458247.015: SPD2ndTiming: Done
28459247.015: mct_BeforeDramInit_Prod_D: Start
28460247.015: mct_ProgramODT_D: Start
28461247.015: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
28462247.015: mct_ProgramODT_D: Done
28463247.015: mct_BeforeDramInit_Prod_D: Done
28464247.015: mct_DramInit_Sw_D: Start
28465247.015: DIMM 0 RttWr: 2
28466247.015: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28467247.015: mct_SendMrsCmd: Start
28468247.015: mct_SendMrsCmd: Done
28469247.015: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
28470247.015: mct_SendMrsCmd: Start
28471247.015: mct_SendMrsCmd: Done
28472247.015: DIMM 0 RttNom: 3
28473247.015: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28474247.015: mct_SendMrsCmd: Start
28475247.015: mct_SendMrsCmd: Done
28476247.015: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
28477247.015: mct_SendMrsCmd: Start
28478247.015: mct_SendMrsCmd: Done
28479247.015: DIMM 0 RttWr: 2
28480247.015: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28481247.015: mct_SendMrsCmd: Start
28482247.015: mct_SendMrsCmd: Done
28483247.015: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
28484247.015: mct_SendMrsCmd: Start
28485247.015: mct_SendMrsCmd: Done
28486247.015: DIMM 0 RttNom: 3
28487247.015: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28488247.015: mct_SendMrsCmd: Start
28489247.015: mct_SendMrsCmd: Done
28490247.015: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
28491247.015: mct_SendMrsCmd: Start
28492247.015: mct_SendMrsCmd: Done
28493247.015: DIMM 1 RttWr: 2
28494247.015: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28495247.015: mct_SendMrsCmd: Start
28496247.015: mct_SendMrsCmd: Done
28497247.015: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
28498247.015: mct_SendMrsCmd: Start
28499247.015: mct_SendMrsCmd: Done
28500247.015: DIMM 1 RttNom: 3
28501247.015: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28502247.015: mct_SendMrsCmd: Start
28503247.015: mct_SendMrsCmd: Done
28504247.015: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
28505247.015: mct_SendMrsCmd: Start
28506247.015: mct_SendMrsCmd: Done
28507247.015: DIMM 1 RttWr: 2
28508247.015: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28509247.015: mct_SendMrsCmd: Start
28510247.015: mct_SendMrsCmd: Done
28511247.015: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
28512247.015: mct_SendMrsCmd: Start
28513247.015: mct_SendMrsCmd: Done
28514247.015: DIMM 1 RttNom: 3
28515247.015: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28516247.015: mct_SendMrsCmd: Start
28517247.015: mct_SendMrsCmd: Done
28518247.015: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
28519247.016: mct_SendMrsCmd: Start
28520247.016: mct_SendMrsCmd: Done
28521247.016: mct_DramInit_Sw_D: Done
28522247.016: AgesaHwWlPhase1: training nibble 0
28523247.016: DIMM 0 RttNom: 3
28524247.016: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28525247.016: DIMM 0 RttWr: 2
28526247.016: DIMM 0 RttWr: 2
28527247.016: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28528247.016: DIMM 0 RttWr: 2
28529247.016: DIMM 0 RttNom: 3
28530247.016: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28531247.016: DIMM 0 RttNom: 3
28532247.016: DIMM 0 RttWr: 2
28533247.016: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28534247.016: DIMM 0 RttWr: 2
28535247.016: DIMM 1 RttNom: 3
28536247.016: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28537247.016: DIMM 0 RttNom: 3
28538247.016: DIMM 1 RttWr: 2
28539247.016: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28540247.016: DIMM 0 RttWr: 2
28541247.016: DIMM 1 RttNom: 3
28542247.016: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28543247.016: DIMM 0 RttNom: 3
28544247.016: DIMM 1 RttWr: 2
28545247.016: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28546247.016: DIMM 0 RttWr: 2
28547247.016: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
28548247.016: <09>Lane 00 scaled delay: 0047
28549247.016: <09>Lane 00 new seed: 0047
28550247.016: <09>Lane 01 scaled delay: 0047
28551247.016: <09>Lane 01 new seed: 0047
28552247.016: <09>Lane 02 scaled delay: 0047
28553247.016: <09>Lane 02 new seed: 0047
28554247.016: <09>Lane 03 scaled delay: 0047
28555247.016: <09>Lane 03 new seed: 0047
28556247.016: <09>Lane 04 scaled delay: 0047
28557247.016: <09>Lane 04 new seed: 0047
28558247.016: <09>Lane 05 scaled delay: 0047
28559247.016: <09>Lane 05 new seed: 0047
28560247.016: <09>Lane 06 scaled delay: 0047
28561247.016: <09>Lane 06 new seed: 0047
28562247.016: <09>Lane 07 scaled delay: 0047
28563247.016: <09>Lane 07 new seed: 0047
28564247.016: <09>Lane 08 scaled delay: 0047
28565247.016: <09>Lane 08 new seed: 0047
28566247.016: <09>Lane 00 nibble 0 raw readback: 004c
28567247.016: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
28568247.016: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
28569247.016: <09>Lane 01 nibble 0 raw readback: 0049
28570247.016: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
28571247.016: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
28572247.016: <09>Lane 02 nibble 0 raw readback: 0045
28573247.016: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
28574247.017: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
28575247.017: <09>Lane 03 nibble 0 raw readback: 0042
28576247.017: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
28577247.017: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
28578247.017: <09>Lane 04 nibble 0 raw readback: 0039
28579247.017: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
28580247.017: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
28581247.017: <09>Lane 05 nibble 0 raw readback: 003c
28582247.017: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
28583247.017: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
28584247.017: <09>Lane 06 nibble 0 raw readback: 003e
28585247.017: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
28586247.017: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
28587247.017: <09>Lane 07 nibble 0 raw readback: 0040
28588247.017: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
28589247.017: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
28590247.017: <09>Lane 08 nibble 0 raw readback: 003a
28591247.017: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
28592247.017: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
28593247.017: AgesaHwWlPhase1: training nibble 1
28594247.017: DIMM 0 RttNom: 3
28595247.017: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28596247.017: DIMM 0 RttWr: 2
28597247.017: DIMM 0 RttWr: 2
28598247.017: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28599247.017: DIMM 0 RttWr: 2
28600247.017: DIMM 0 RttNom: 3
28601247.017: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28602247.017: DIMM 0 RttNom: 3
28603247.017: DIMM 0 RttWr: 2
28604247.017: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28605247.017: DIMM 0 RttWr: 2
28606247.017: DIMM 1 RttNom: 3
28607247.017: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28608247.017: DIMM 0 RttNom: 3
28609247.017: DIMM 1 RttWr: 2
28610247.017: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28611247.017: DIMM 0 RttWr: 2
28612247.017: DIMM 1 RttNom: 3
28613247.017: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28614247.017: DIMM 0 RttNom: 3
28615247.017: DIMM 1 RttWr: 2
28616247.017: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28617247.017: DIMM 0 RttWr: 2
28618247.017: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
28619247.017: <09>Lane 00 new seed: 0047
28620247.017: <09>Lane 01 new seed: 0047
28621247.017: <09>Lane 02 new seed: 0047
28622247.017: <09>Lane 03 new seed: 0047
28623247.017: <09>Lane 04 new seed: 0047
28624247.017: <09>Lane 05 new seed: 0047
28625247.017: <09>Lane 06 new seed: 0047
28626247.017: <09>Lane 07 new seed: 0047
28627247.017: <09>Lane 08 new seed: 0047
28628247.017: <09>Lane 00 nibble 1 raw readback: 004d
28629247.017: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004d
28630247.017: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
28631247.017: <09>Lane 01 nibble 1 raw readback: 0049
28632247.017: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0049
28633247.017: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
28634247.017: <09>Lane 02 nibble 1 raw readback: 0046
28635247.017: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
28636247.017: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
28637247.017: <09>Lane 03 nibble 1 raw readback: 0043
28638247.017: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
28639247.017: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
28640247.017: <09>Lane 04 nibble 1 raw readback: 0038
28641247.017: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
28642247.017: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
28643247.017: <09>Lane 05 nibble 1 raw readback: 003b
28644247.017: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
28645247.017: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
28646247.017: <09>Lane 06 nibble 1 raw readback: 003f
28647247.018: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
28648247.018: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
28649247.018: <09>Lane 07 nibble 1 raw readback: 0041
28650247.018: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
28651247.018: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
28652247.018: <09>Lane 08 nibble 1 raw readback: 003a
28653247.018: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
28654247.018: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
28655247.018: <09>original critical gross delay: 0
28656247.018: <09>new critical gross delay: 0
28657247.018: DIMM 0 RttNom: 3
28658247.018: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28659247.018: DIMM 0 RttNom: 3
28660247.018: DIMM 0 RttWr: 2
28661247.018: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28662247.018: DIMM 0 RttWr: 2
28663247.018: DIMM 0 RttNom: 3
28664247.018: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28665247.018: DIMM 0 RttNom: 3
28666247.018: DIMM 0 RttWr: 2
28667247.018: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28668247.018: DIMM 0 RttWr: 2
28669247.018: DIMM 1 RttNom: 3
28670247.018: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28671247.018: DIMM 0 RttNom: 3
28672247.018: DIMM 1 RttWr: 2
28673247.018: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28674247.018: DIMM 0 RttWr: 2
28675247.018: DIMM 1 RttNom: 3
28676247.018: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28677247.018: DIMM 0 RttNom: 3
28678247.018: DIMM 1 RttWr: 2
28679247.018: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28680247.018: DIMM 0 RttWr: 2
28681247.018: AgesaHwWlPhase1: training nibble 0
28682247.018: DIMM 1 RttNom: 3
28683247.018: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28684247.018: DIMM 1 RttWr: 2
28685247.018: DIMM 1 RttWr: 2
28686247.018: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28687247.018: DIMM 1 RttWr: 2
28688247.018: DIMM 1 RttNom: 3
28689247.018: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28690247.018: DIMM 1 RttNom: 3
28691247.018: DIMM 1 RttWr: 2
28692247.018: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28693247.018: DIMM 1 RttWr: 2
28694247.018: DIMM 0 RttNom: 3
28695247.018: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28696247.018: DIMM 1 RttNom: 3
28697247.018: DIMM 0 RttWr: 2
28698247.018: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28699247.018: DIMM 1 RttWr: 2
28700247.018: DIMM 0 RttNom: 3
28701247.018: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28702247.018: DIMM 1 RttNom: 3
28703247.019: DIMM 0 RttWr: 2
28704247.019: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28705247.019: DIMM 1 RttWr: 2
28706247.019: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
28707247.019: <09>Lane 00 scaled delay: 0047
28708247.019: <09>Lane 00 new seed: 0047
28709247.019: <09>Lane 01 scaled delay: 0047
28710247.019: <09>Lane 01 new seed: 0047
28711247.019: <09>Lane 02 scaled delay: 0047
28712247.019: <09>Lane 02 new seed: 0047
28713247.019: <09>Lane 03 scaled delay: 0047
28714247.019: <09>Lane 03 new seed: 0047
28715247.019: <09>Lane 04 scaled delay: 0047
28716247.019: <09>Lane 04 new seed: 0047
28717247.019: <09>Lane 05 scaled delay: 0047
28718247.019: <09>Lane 05 new seed: 0047
28719247.019: <09>Lane 06 scaled delay: 0047
28720247.019: <09>Lane 06 new seed: 0047
28721247.019: <09>Lane 07 scaled delay: 0047
28722247.019: <09>Lane 07 new seed: 0047
28723247.019: <09>Lane 08 scaled delay: 0047
28724247.019: <09>Lane 08 new seed: 0047
28725247.019: <09>Lane 00 nibble 0 raw readback: 0045
28726247.019: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
28727247.019: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
28728247.019: <09>Lane 01 nibble 0 raw readback: 0042
28729247.019: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
28730247.019: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
28731247.019: <09>Lane 02 nibble 0 raw readback: 003e
28732247.019: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
28733247.019: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
28734247.019: <09>Lane 03 nibble 0 raw readback: 003b
28735247.019: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
28736247.019: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
28737247.019: <09>Lane 04 nibble 0 raw readback: 0031
28738247.019: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0031
28739247.019: <09>Lane 04 nibble 0 adjusted value (post nibble): 0031
28740247.019: <09>Lane 05 nibble 0 raw readback: 0034
28741247.019: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0034
28742247.019: <09>Lane 05 nibble 0 adjusted value (post nibble): 0034
28743247.019: <09>Lane 06 nibble 0 raw readback: 0037
28744247.019: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
28745247.019: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
28746247.019: <09>Lane 07 nibble 0 raw readback: 003a
28747247.019: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
28748247.019: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
28749247.019: <09>Lane 08 nibble 0 raw readback: 0033
28750247.019: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
28751247.019: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
28752247.019: AgesaHwWlPhase1: training nibble 1
28753247.019: DIMM 1 RttNom: 3
28754247.019: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28755247.019: DIMM 1 RttWr: 2
28756247.019: DIMM 1 RttWr: 2
28757247.019: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28758247.019: DIMM 1 RttWr: 2
28759247.019: DIMM 1 RttNom: 3
28760247.019: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28761247.019: DIMM 1 RttNom: 3
28762247.019: DIMM 1 RttWr: 2
28763247.019: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28764247.019: DIMM 1 RttWr: 2
28765247.019: DIMM 0 RttNom: 3
28766247.019: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28767247.019: DIMM 1 RttNom: 3
28768247.019: DIMM 0 RttWr: 2
28769247.019: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28770247.019: DIMM 1 RttWr: 2
28771247.019: DIMM 0 RttNom: 3
28772247.019: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28773247.019: DIMM 1 RttNom: 3
28774247.019: DIMM 0 RttWr: 2
28775247.019: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28776247.019: DIMM 1 RttWr: 2
28777247.019: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
28778247.019: <09>Lane 00 new seed: 0047
28779247.019: <09>Lane 01 new seed: 0047
28780247.020: <09>Lane 02 new seed: 0047
28781247.020: <09>Lane 03 new seed: 0047
28782247.020: <09>Lane 04 new seed: 0047
28783247.020: <09>Lane 05 new seed: 0047
28784247.020: <09>Lane 06 new seed: 0047
28785247.020: <09>Lane 07 new seed: 0047
28786247.020: <09>Lane 08 new seed: 0047
28787247.020: <09>Lane 00 nibble 1 raw readback: 0045
28788247.020: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
28789247.020: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
28790247.020: <09>Lane 01 nibble 1 raw readback: 0041
28791247.020: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
28792247.020: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
28793247.020: <09>Lane 02 nibble 1 raw readback: 003f
28794247.020: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
28795247.020: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
28796247.020: <09>Lane 03 nibble 1 raw readback: 003d
28797247.020: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003d
28798247.020: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
28799247.020: <09>Lane 04 nibble 1 raw readback: 0031
28800247.020: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
28801247.020: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
28802247.020: <09>Lane 05 nibble 1 raw readback: 0035
28803247.020: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
28804247.020: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
28805247.020: <09>Lane 06 nibble 1 raw readback: 0037
28806247.020: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
28807247.020: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
28808247.020: <09>Lane 07 nibble 1 raw readback: 0039
28809247.020: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
28810247.020: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
28811247.020: <09>Lane 08 nibble 1 raw readback: 0034
28812247.020: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0034
28813247.020: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
28814247.020: <09>original critical gross delay: 0
28815247.020: <09>new critical gross delay: 0
28816247.020: DIMM 1 RttNom: 3
28817247.020: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
28818247.020: DIMM 1 RttNom: 3
28819247.020: DIMM 1 RttWr: 2
28820247.020: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
28821247.020: DIMM 1 RttWr: 2
28822247.020: DIMM 1 RttNom: 3
28823247.020: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
28824247.020: DIMM 1 RttNom: 3
28825247.020: DIMM 1 RttWr: 2
28826247.020: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
28827247.020: DIMM 1 RttWr: 2
28828247.020: DIMM 0 RttNom: 3
28829247.020: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
28830247.020: DIMM 1 RttNom: 3
28831247.020: DIMM 0 RttWr: 2
28832247.020: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
28833247.020: DIMM 1 RttWr: 2
28834247.020: DIMM 0 RttNom: 3
28835247.020: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
28836247.020: DIMM 1 RttNom: 3
28837247.020: DIMM 0 RttWr: 2
28838247.020: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
28839247.020: DIMM 1 RttWr: 2
28840247.021: SetTargetFreq: Start
28841247.021: SetTargetFreq: Node 0: New frequency code: 000a
28842247.021: ChangeMemClk: Start
28843247.021: set_2t_configuration: Start
28844247.021: set_2t_configuration: Done
28845247.021: mct_BeforePlatformSpec: Start
28846247.021: mct_BeforePlatformSpec: Done
28847247.021: mct_PlatformSpec: Start
28848247.021: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
28849247.021: mct_PlatformSpec: Done
28850247.021: set_2t_configuration: Start
28851247.021: set_2t_configuration: Done
28852247.021: mct_BeforePlatformSpec: Start
28853247.021: mct_BeforePlatformSpec: Done
28854247.021: mct_PlatformSpec: Start
28855247.021: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
28856247.021: mct_PlatformSpec: Done
28857247.021: ChangeMemClk: Done
28858247.021: phyAssistedMemFnceTraining: Start
28859247.021: phyAssistedMemFnceTraining: training node 0 DCT 0
28860247.021: phyAssistedMemFnceTraining: done training node 0 DCT 0
28861247.021: phyAssistedMemFnceTraining: training node 0 DCT 1
28862247.021: phyAssistedMemFnceTraining: done training node 0 DCT 1
28863247.021: phyAssistedMemFnceTraining: Done
28864247.021: InitPhyCompensation: DCT 0: Start
28865247.022: Waiting for predriver calibration to be applied...done!
28866247.022: InitPhyCompensation: DCT 0: Done
28867247.022: phyAssistedMemFnceTraining: Start
28868247.022: phyAssistedMemFnceTraining: training node 0 DCT 0
28869247.022: phyAssistedMemFnceTraining: done training node 0 DCT 0
28870247.022: phyAssistedMemFnceTraining: training node 0 DCT 1
28871247.022: phyAssistedMemFnceTraining: done training node 0 DCT 1
28872247.022: phyAssistedMemFnceTraining: Done
28873247.022: InitPhyCompensation: DCT 1: Start
28874247.022: Waiting for predriver calibration to be applied...done!
28875247.022: InitPhyCompensation: DCT 1: Done
28876247.022: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
28877247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28878247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
28879247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28880247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
28881247.022: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
28882247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28883247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
28884247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
28885247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
28886247.022: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
28887247.022: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28888247.022: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
28889247.022: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28890247.022: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
28891247.023: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
28892247.023: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28893247.023: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
28894247.023: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
28895247.023: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
28896247.023: SetTargetFreq: Done
28897247.023: SPD2ndTiming: Start
28898247.023: SPD2ndTiming: Done
28899247.023: mct_BeforeDramInit_Prod_D: Start
28900247.023: mct_ProgramODT_D: Start
28901247.023: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
28902247.023: mct_ProgramODT_D: Done
28903247.023: mct_BeforeDramInit_Prod_D: Done
28904247.023: mct_DramInit_Sw_D: Start
28905247.023: DIMM 0 RttWr: 1
28906247.023: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
28907247.023: mct_SendMrsCmd: Start
28908247.023: mct_SendMrsCmd: Done
28909247.023: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
28910247.023: mct_SendMrsCmd: Start
28911247.023: mct_SendMrsCmd: Done
28912247.023: DIMM 0 RttNom: 3
28913247.023: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28914247.023: mct_SendMrsCmd: Start
28915247.023: mct_SendMrsCmd: Done
28916247.023: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
28917247.023: mct_SendMrsCmd: Start
28918247.023: mct_SendMrsCmd: Done
28919247.023: DIMM 0 RttWr: 1
28920247.023: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
28921247.023: mct_SendMrsCmd: Start
28922247.023: mct_SendMrsCmd: Done
28923247.023: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
28924247.023: mct_SendMrsCmd: Start
28925247.023: mct_SendMrsCmd: Done
28926247.023: DIMM 0 RttNom: 3
28927247.023: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28928247.023: mct_SendMrsCmd: Start
28929247.023: mct_SendMrsCmd: Done
28930247.023: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
28931247.023: mct_SendMrsCmd: Start
28932247.024: mct_SendMrsCmd: Done
28933247.023: DIMM 1 RttWr: 1
28934247.024: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
28935247.024: mct_SendMrsCmd: Start
28936247.024: mct_SendMrsCmd: Done
28937247.024: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
28938247.024: mct_SendMrsCmd: Start
28939247.024: mct_SendMrsCmd: Done
28940247.024: DIMM 1 RttNom: 3
28941247.024: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28942247.024: mct_SendMrsCmd: Start
28943247.024: mct_SendMrsCmd: Done
28944247.024: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
28945247.024: mct_SendMrsCmd: Start
28946247.024: mct_SendMrsCmd: Done
28947247.024: DIMM 1 RttWr: 1
28948247.024: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
28949247.024: mct_SendMrsCmd: Start
28950247.024: mct_SendMrsCmd: Done
28951247.024: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
28952247.024: mct_SendMrsCmd: Start
28953247.024: mct_SendMrsCmd: Done
28954247.024: DIMM 1 RttNom: 3
28955247.024: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28956247.024: mct_SendMrsCmd: Start
28957247.024: mct_SendMrsCmd: Done
28958247.024: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
28959247.024: mct_SendMrsCmd: Start
28960247.024: mct_SendMrsCmd: Done
28961247.024: mct_DramInit_Sw_D: Done
28962247.024: AgesaHwWlPhase1: training nibble 0
28963247.024: DIMM 0 RttNom: 3
28964247.024: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
28965247.024: DIMM 0 RttWr: 1
28966247.024: DIMM 0 RttWr: 1
28967247.024: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
28968247.024: DIMM 0 RttWr: 1
28969247.024: DIMM 0 RttNom: 3
28970247.024: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
28971247.024: DIMM 0 RttNom: 3
28972247.024: DIMM 0 RttWr: 1
28973247.024: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
28974247.024: DIMM 0 RttWr: 1
28975247.024: DIMM 1 RttNom: 3
28976247.024: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
28977247.024: DIMM 0 RttNom: 3
28978247.024: DIMM 1 RttWr: 1
28979247.024: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
28980247.024: DIMM 0 RttWr: 1
28981247.024: DIMM 1 RttNom: 3
28982247.024: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
28983247.024: DIMM 0 RttNom: 3
28984247.024: DIMM 1 RttWr: 1
28985247.024: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
28986247.024: DIMM 0 RttWr: 1
28987247.024: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
28988247.025: <09>Lane 00 scaled delay: 0059
28989247.025: <09>Lane 00 new seed: 0059
28990247.025: <09>Lane 01 scaled delay: 0055
28991247.025: <09>Lane 01 new seed: 0055
28992247.025: <09>Lane 02 scaled delay: 0055
28993247.025: <09>Lane 02 new seed: 0055
28994247.025: <09>Lane 03 scaled delay: 0052
28995247.025: <09>Lane 03 new seed: 0052
28996247.025: <09>Lane 04 scaled delay: 004b
28997247.025: <09>Lane 04 new seed: 004b
28998247.025: <09>Lane 05 scaled delay: 004e
28999247.025: <09>Lane 05 new seed: 004e
29000247.025: <09>Lane 06 scaled delay: 004f
29001247.025: <09>Lane 06 new seed: 004f
29002247.025: <09>Lane 07 scaled delay: 0051
29003247.025: <09>Lane 07 new seed: 0051
29004247.025: <09>Lane 08 scaled delay: 004d
29005247.025: <09>Lane 08 new seed: 004d
29006247.025: <09>Lane 00 nibble 0 raw readback: 0060
29007247.025: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
29008247.025: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
29009247.025: <09>Lane 01 nibble 0 raw readback: 0058
29010247.025: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
29011247.025: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
29012247.025: <09>Lane 02 nibble 0 raw readback: 0055
29013247.025: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
29014247.025: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
29015247.025: <09>Lane 03 nibble 0 raw readback: 0050
29016247.025: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
29017247.025: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
29018247.025: <09>Lane 04 nibble 0 raw readback: 0042
29019247.025: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
29020247.025: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
29021247.025: <09>Lane 05 nibble 0 raw readback: 0049
29022247.025: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
29023247.025: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
29024247.025: <09>Lane 06 nibble 0 raw readback: 004d
29025247.025: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
29026247.025: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
29027247.025: <09>Lane 07 nibble 0 raw readback: 0050
29028247.025: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
29029247.025: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
29030247.025: <09>Lane 08 nibble 0 raw readback: 0046
29031247.025: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0046
29032247.025: <09>Lane 08 nibble 0 adjusted value (post nibble): 0046
29033247.025: AgesaHwWlPhase1: training nibble 1
29034247.025: DIMM 0 RttNom: 3
29035247.025: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
29036247.025: DIMM 0 RttWr: 1
29037247.025: DIMM 0 RttWr: 1
29038247.025: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
29039247.025: DIMM 0 RttWr: 1
29040247.025: DIMM 0 RttNom: 3
29041247.026: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
29042247.025: DIMM 0 RttNom: 3
29043247.025: DIMM 0 RttWr: 1
29044247.026: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
29045247.025: DIMM 0 RttWr: 1
29046247.026: DIMM 1 RttNom: 3
29047247.026: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
29048247.026: DIMM 0 RttNom: 3
29049247.026: DIMM 1 RttWr: 1
29050247.026: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
29051247.026: DIMM 0 RttWr: 1
29052247.026: DIMM 1 RttNom: 3
29053247.026: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
29054247.026: DIMM 0 RttNom: 3
29055247.026: DIMM 1 RttWr: 1
29056247.026: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
29057247.026: DIMM 0 RttWr: 1
29058247.026: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
29059247.026: <09>Lane 00 new seed: 0059
29060247.026: <09>Lane 01 new seed: 0055
29061247.026: <09>Lane 02 new seed: 0055
29062247.026: <09>Lane 03 new seed: 0052
29063247.026: <09>Lane 04 new seed: 004b
29064247.026: <09>Lane 05 new seed: 004e
29065247.026: <09>Lane 06 new seed: 004f
29066247.026: <09>Lane 07 new seed: 0051
29067247.026: <09>Lane 08 new seed: 004d
29068247.026: <09>Lane 00 nibble 1 raw readback: 0060
29069247.026: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
29070247.026: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
29071247.026: <09>Lane 01 nibble 1 raw readback: 0057
29072247.026: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0057
29073247.026: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
29074247.026: <09>Lane 02 nibble 1 raw readback: 0056
29075247.026: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
29076247.026: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
29077247.026: <09>Lane 03 nibble 1 raw readback: 0051
29078247.026: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
29079247.026: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
29080247.026: <09>Lane 04 nibble 1 raw readback: 0042
29081247.026: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
29082247.026: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
29083247.026: <09>Lane 05 nibble 1 raw readback: 0048
29084247.026: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
29085247.026: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
29086247.026: <09>Lane 06 nibble 1 raw readback: 004d
29087247.026: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
29088247.026: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
29089247.026: <09>Lane 07 nibble 1 raw readback: 004f
29090247.026: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004f
29091247.026: <09>Lane 07 nibble 1 adjusted value (post nibble): 0050
29092247.026: <09>Lane 08 nibble 1 raw readback: 0045
29093247.026: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
29094247.026: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
29095247.026: <09>original critical gross delay: 0
29096247.026: <09>new critical gross delay: 0
29097247.026: DIMM 0 RttNom: 3
29098247.026: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
29099247.026: DIMM 0 RttNom: 3
29100247.026: DIMM 0 RttWr: 1
29101247.026: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
29102247.026: DIMM 0 RttWr: 1
29103247.026: DIMM 0 RttNom: 3
29104247.026: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
29105247.026: DIMM 0 RttNom: 3
29106247.026: DIMM 0 RttWr: 1
29107247.026: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
29108247.026: DIMM 0 RttWr: 1
29109247.026: DIMM 1 RttNom: 3
29110247.027: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
29111247.027: DIMM 0 RttNom: 3
29112247.027: DIMM 1 RttWr: 1
29113247.027: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
29114247.027: DIMM 0 RttWr: 1
29115247.027: DIMM 1 RttNom: 3
29116247.027: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
29117247.027: DIMM 0 RttNom: 3
29118247.027: DIMM 1 RttWr: 1
29119247.027: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
29120247.027: DIMM 0 RttWr: 1
29121247.027: AgesaHwWlPhase1: training nibble 0
29122247.027: DIMM 1 RttNom: 3
29123247.027: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
29124247.027: DIMM 1 RttWr: 1
29125247.027: DIMM 1 RttWr: 1
29126247.027: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
29127247.027: DIMM 1 RttWr: 1
29128247.027: DIMM 1 RttNom: 3
29129247.027: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
29130247.027: DIMM 1 RttNom: 3
29131247.027: DIMM 1 RttWr: 1
29132247.027: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
29133247.027: DIMM 1 RttWr: 1
29134247.027: DIMM 0 RttNom: 3
29135247.027: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
29136247.027: DIMM 1 RttNom: 3
29137247.027: DIMM 0 RttWr: 1
29138247.027: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
29139247.027: DIMM 1 RttWr: 1
29140247.027: DIMM 0 RttNom: 3
29141247.027: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
29142247.027: DIMM 1 RttNom: 3
29143247.027: DIMM 0 RttWr: 1
29144247.027: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
29145247.027: DIMM 1 RttWr: 1
29146247.027: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
29147247.027: <09>Lane 00 scaled delay: 0052
29148247.027: <09>Lane 00 new seed: 0052
29149247.027: <09>Lane 01 scaled delay: 004e
29150247.027: <09>Lane 01 new seed: 004e
29151247.027: <09>Lane 02 scaled delay: 004e
29152247.027: <09>Lane 02 new seed: 004e
29153247.027: <09>Lane 03 scaled delay: 004b
29154247.027: <09>Lane 03 new seed: 004b
29155247.027: <09>Lane 04 scaled delay: 0043
29156247.027: <09>Lane 04 new seed: 0043
29157247.027: <09>Lane 05 scaled delay: 0047
29158247.027: <09>Lane 05 new seed: 0047
29159247.027: <09>Lane 06 scaled delay: 0047
29160247.027: <09>Lane 06 new seed: 0047
29161247.027: <09>Lane 07 scaled delay: 004a
29162247.027: <09>Lane 07 new seed: 004a
29163247.027: <09>Lane 08 scaled delay: 0045
29164247.027: <09>Lane 08 new seed: 0045
29165247.027: <09>Lane 00 nibble 0 raw readback: 0052
29166247.027: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
29167247.027: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
29168247.027: <09>Lane 01 nibble 0 raw readback: 004b
29169247.027: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
29170247.027: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
29171247.027: <09>Lane 02 nibble 0 raw readback: 0048
29172247.027: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
29173247.027: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
29174247.027: <09>Lane 03 nibble 0 raw readback: 0044
29175247.027: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
29176247.027: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
29177247.027: <09>Lane 04 nibble 0 raw readback: 0037
29178247.027: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0037
29179247.027: <09>Lane 04 nibble 0 adjusted value (post nibble): 0037
29180247.027: <09>Lane 05 nibble 0 raw readback: 003d
29181247.027: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
29182247.027: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
29183247.027: <09>Lane 06 nibble 0 raw readback: 0040
29184247.027: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
29185247.027: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
29186247.028: <09>Lane 07 nibble 0 raw readback: 0044
29187247.028: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
29188247.028: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
29189247.028: <09>Lane 08 nibble 0 raw readback: 0038
29190247.028: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
29191247.028: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
29192247.028: AgesaHwWlPhase1: training nibble 1
29193247.028: DIMM 1 RttNom: 3
29194247.028: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
29195247.028: DIMM 1 RttWr: 1
29196247.028: DIMM 1 RttWr: 1
29197247.028: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
29198247.028: DIMM 1 RttWr: 1
29199247.028: DIMM 1 RttNom: 3
29200247.028: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
29201247.028: DIMM 1 RttNom: 3
29202247.028: DIMM 1 RttWr: 1
29203247.028: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
29204247.028: DIMM 1 RttWr: 1
29205247.028: DIMM 0 RttNom: 3
29206247.028: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
29207247.028: DIMM 1 RttNom: 3
29208247.028: DIMM 0 RttWr: 1
29209247.028: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
29210247.028: DIMM 1 RttWr: 1
29211247.028: DIMM 0 RttNom: 3
29212247.028: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
29213247.028: DIMM 1 RttNom: 3
29214247.028: DIMM 0 RttWr: 1
29215247.028: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
29216247.028: DIMM 1 RttWr: 1
29217247.028: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
29218247.028: <09>Lane 00 new seed: 0052
29219247.028: <09>Lane 01 new seed: 004e
29220247.028: <09>Lane 02 new seed: 004e
29221247.028: <09>Lane 03 new seed: 004b
29222247.028: <09>Lane 04 new seed: 0043
29223247.028: <09>Lane 05 new seed: 0047
29224247.028: <09>Lane 06 new seed: 0047
29225247.028: <09>Lane 07 new seed: 004a
29226247.028: <09>Lane 08 new seed: 0045
29227247.028: <09>Lane 00 nibble 1 raw readback: 0053
29228247.028: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
29229247.028: <09>Lane 00 nibble 1 adjusted value (post nibble): 0052
29230247.028: <09>Lane 01 nibble 1 raw readback: 004c
29231247.028: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004c
29232247.028: <09>Lane 01 nibble 1 adjusted value (post nibble): 004d
29233247.028: <09>Lane 02 nibble 1 raw readback: 004a
29234247.028: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
29235247.028: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
29236247.028: <09>Lane 03 nibble 1 raw readback: 0044
29237247.028: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
29238247.028: <09>Lane 03 nibble 1 adjusted value (post nibble): 0047
29239247.028: <09>Lane 04 nibble 1 raw readback: 0036
29240247.028: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
29241247.028: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
29242247.028: <09>Lane 05 nibble 1 raw readback: 003d
29243247.028: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
29244247.028: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
29245247.028: <09>Lane 06 nibble 1 raw readback: 0040
29246247.028: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
29247247.028: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
29248247.028: <09>Lane 07 nibble 1 raw readback: 0045
29249247.028: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
29250247.028: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
29251247.028: <09>Lane 08 nibble 1 raw readback: 0039
29252247.028: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
29253247.028: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
29254247.028: <09>original critical gross delay: 0
29255247.028: <09>new critical gross delay: 0
29256247.028: DIMM 1 RttNom: 3
29257247.028: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
29258247.028: DIMM 1 RttNom: 3
29259247.029: DIMM 1 RttWr: 1
29260247.029: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
29261247.029: DIMM 1 RttWr: 1
29262247.029: DIMM 1 RttNom: 3
29263247.029: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
29264247.029: DIMM 1 RttNom: 3
29265247.029: DIMM 1 RttWr: 1
29266247.029: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
29267247.029: DIMM 1 RttWr: 1
29268247.029: DIMM 0 RttNom: 3
29269247.029: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
29270247.029: DIMM 1 RttNom: 3
29271247.029: DIMM 0 RttWr: 1
29272247.029: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
29273247.029: DIMM 1 RttWr: 1
29274247.029: DIMM 0 RttNom: 3
29275247.029: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
29276247.029: DIMM 1 RttNom: 3
29277247.029: DIMM 0 RttWr: 1
29278247.029: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
29279247.029: DIMM 1 RttWr: 1
29280247.029: SPD2ndTiming: Start
29281247.029: SPD2ndTiming: Done
29282247.029: mct_BeforeDramInit_Prod_D: Start
29283247.029: mct_ProgramODT_D: Start
29284247.029: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
29285247.029: mct_ProgramODT_D: Done
29286247.029: mct_BeforeDramInit_Prod_D: Done
29287247.029: mct_DramInit_Sw_D: Start
29288247.029: DIMM 0 RttWr: 1
29289247.029: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29290247.029: mct_SendMrsCmd: Start
29291247.029: mct_SendMrsCmd: Done
29292247.029: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
29293247.029: mct_SendMrsCmd: Start
29294247.030: mct_SendMrsCmd: Done
29295247.030: DIMM 0 RttNom: 3
29296247.030: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29297247.030: mct_SendMrsCmd: Start
29298247.030: mct_SendMrsCmd: Done
29299247.030: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
29300247.030: mct_SendMrsCmd: Start
29301247.030: mct_SendMrsCmd: Done
29302247.030: DIMM 0 RttWr: 1
29303247.030: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29304247.030: mct_SendMrsCmd: Start
29305247.030: mct_SendMrsCmd: Done
29306247.030: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
29307247.030: mct_SendMrsCmd: Start
29308247.030: mct_SendMrsCmd: Done
29309247.030: DIMM 0 RttNom: 3
29310247.030: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29311247.030: mct_SendMrsCmd: Start
29312247.030: mct_SendMrsCmd: Done
29313247.030: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
29314247.030: mct_SendMrsCmd: Start
29315247.030: mct_SendMrsCmd: Done
29316247.030: DIMM 1 RttWr: 1
29317247.030: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29318247.030: mct_SendMrsCmd: Start
29319247.030: mct_SendMrsCmd: Done
29320247.030: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
29321247.030: mct_SendMrsCmd: Start
29322247.030: mct_SendMrsCmd: Done
29323247.030: DIMM 1 RttNom: 3
29324247.030: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29325247.030: mct_SendMrsCmd: Start
29326247.030: mct_SendMrsCmd: Done
29327247.030: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
29328247.030: mct_SendMrsCmd: Start
29329247.030: mct_SendMrsCmd: Done
29330247.030: DIMM 1 RttWr: 1
29331247.030: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29332247.030: mct_SendMrsCmd: Start
29333247.030: mct_SendMrsCmd: Done
29334247.030: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
29335247.030: mct_SendMrsCmd: Start
29336247.030: mct_SendMrsCmd: Done
29337247.030: DIMM 1 RttNom: 3
29338247.030: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29339247.030: mct_SendMrsCmd: Start
29340247.030: mct_SendMrsCmd: Done
29341247.030: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
29342247.030: mct_SendMrsCmd: Start
29343247.030: mct_SendMrsCmd: Done
29344247.030: mct_DramInit_Sw_D: Done
29345247.030: AgesaHwWlPhase1: training nibble 0
29346247.030: DIMM 0 RttNom: 3
29347247.030: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29348247.030: DIMM 0 RttWr: 1
29349247.030: DIMM 0 RttWr: 1
29350247.030: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29351247.030: DIMM 0 RttWr: 1
29352247.030: DIMM 0 RttNom: 3
29353247.030: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29354247.030: DIMM 0 RttNom: 3
29355247.030: DIMM 0 RttWr: 1
29356247.030: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29357247.030: DIMM 0 RttWr: 1
29358247.030: DIMM 1 RttNom: 3
29359247.030: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29360247.030: DIMM 0 RttNom: 3
29361247.030: DIMM 1 RttWr: 1
29362247.030: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29363247.030: DIMM 0 RttWr: 1
29364247.031: DIMM 1 RttNom: 3
29365247.031: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29366247.031: DIMM 0 RttNom: 3
29367247.031: DIMM 1 RttWr: 1
29368247.031: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29369247.031: DIMM 0 RttWr: 1
29370247.031: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
29371247.031: <09>Lane 00 scaled delay: 0057
29372247.031: <09>Lane 00 new seed: 0057
29373247.031: <09>Lane 01 scaled delay: 0055
29374247.031: <09>Lane 01 new seed: 0055
29375247.031: <09>Lane 02 scaled delay: 0052
29376247.031: <09>Lane 02 new seed: 0052
29377247.031: <09>Lane 03 scaled delay: 0051
29378247.031: <09>Lane 03 new seed: 0051
29379247.031: <09>Lane 04 scaled delay: 0049
29380247.031: <09>Lane 04 new seed: 0049
29381247.031: <09>Lane 05 scaled delay: 004b
29382247.031: <09>Lane 05 new seed: 004b
29383247.031: <09>Lane 06 scaled delay: 004e
29384247.031: <09>Lane 06 new seed: 004e
29385247.031: <09>Lane 07 scaled delay: 004f
29386247.031: <09>Lane 07 new seed: 004f
29387247.031: <09>Lane 08 scaled delay: 004a
29388247.031: <09>Lane 08 new seed: 004a
29389247.031: <09>Lane 00 nibble 0 raw readback: 005c
29390247.031: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
29391247.031: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
29392247.031: <09>Lane 01 nibble 0 raw readback: 0059
29393247.031: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
29394247.031: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
29395247.031: <09>Lane 02 nibble 0 raw readback: 0054
29396247.031: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
29397247.031: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
29398247.031: <09>Lane 03 nibble 0 raw readback: 0050
29399247.031: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
29400247.031: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
29401247.031: <09>Lane 04 nibble 0 raw readback: 0043
29402247.031: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
29403247.031: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
29404247.031: <09>Lane 05 nibble 0 raw readback: 0046
29405247.031: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
29406247.031: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
29407247.031: <09>Lane 06 nibble 0 raw readback: 0049
29408247.031: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
29409247.031: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
29410247.031: <09>Lane 07 nibble 0 raw readback: 004d
29411247.031: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
29412247.031: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
29413247.031: <09>Lane 08 nibble 0 raw readback: 0045
29414247.031: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
29415247.031: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
29416247.031: AgesaHwWlPhase1: training nibble 1
29417247.031: DIMM 0 RttNom: 3
29418247.031: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29419247.031: DIMM 0 RttWr: 1
29420247.031: DIMM 0 RttWr: 1
29421247.031: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29422247.031: DIMM 0 RttWr: 1
29423247.031: DIMM 0 RttNom: 3
29424247.031: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29425247.031: DIMM 0 RttNom: 3
29426247.031: DIMM 0 RttWr: 1
29427247.031: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29428247.031: DIMM 0 RttWr: 1
29429247.032: DIMM 1 RttNom: 3
29430247.032: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29431247.032: DIMM 0 RttNom: 3
29432247.032: DIMM 1 RttWr: 1
29433247.032: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29434247.032: DIMM 0 RttWr: 1
29435247.032: DIMM 1 RttNom: 3
29436247.032: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29437247.032: DIMM 0 RttNom: 3
29438247.032: DIMM 1 RttWr: 1
29439247.032: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29440247.032: DIMM 0 RttWr: 1
29441247.032: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
29442247.032: <09>Lane 00 new seed: 0057
29443247.032: <09>Lane 01 new seed: 0055
29444247.032: <09>Lane 02 new seed: 0052
29445247.032: <09>Lane 03 new seed: 0051
29446247.032: <09>Lane 04 new seed: 0049
29447247.032: <09>Lane 05 new seed: 004b
29448247.032: <09>Lane 06 new seed: 004e
29449247.032: <09>Lane 07 new seed: 004f
29450247.032: <09>Lane 08 new seed: 004a
29451247.032: <09>Lane 00 nibble 1 raw readback: 005d
29452247.032: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
29453247.032: <09>Lane 00 nibble 1 adjusted value (post nibble): 005a
29454247.032: <09>Lane 01 nibble 1 raw readback: 0056
29455247.032: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
29456247.032: <09>Lane 01 nibble 1 adjusted value (post nibble): 0055
29457247.032: <09>Lane 02 nibble 1 raw readback: 0055
29458247.032: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
29459247.032: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
29460247.032: <09>Lane 03 nibble 1 raw readback: 0050
29461247.032: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
29462247.032: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
29463247.032: <09>Lane 04 nibble 1 raw readback: 0041
29464247.032: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
29465247.032: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
29466247.032: <09>Lane 05 nibble 1 raw readback: 0044
29467247.032: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0044
29468247.032: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
29469247.032: <09>Lane 06 nibble 1 raw readback: 004a
29470247.032: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
29471247.032: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
29472247.032: <09>Lane 07 nibble 1 raw readback: 004d
29473247.032: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
29474247.032: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
29475247.032: <09>Lane 08 nibble 1 raw readback: 0045
29476247.032: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
29477247.032: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
29478247.032: <09>original critical gross delay: 0
29479247.032: <09>new critical gross delay: 0
29480247.032: DIMM 0 RttNom: 3
29481247.032: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29482247.032: DIMM 0 RttNom: 3
29483247.032: DIMM 0 RttWr: 1
29484247.032: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29485247.032: DIMM 0 RttWr: 1
29486247.032: DIMM 0 RttNom: 3
29487247.032: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29488247.032: DIMM 0 RttNom: 3
29489247.032: DIMM 0 RttWr: 1
29490247.032: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29491247.032: DIMM 0 RttWr: 1
29492247.032: DIMM 1 RttNom: 3
29493247.032: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29494247.033: DIMM 0 RttNom: 3
29495247.033: DIMM 1 RttWr: 1
29496247.033: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29497247.033: DIMM 0 RttWr: 1
29498247.033: DIMM 1 RttNom: 3
29499247.033: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29500247.033: DIMM 0 RttNom: 3
29501247.033: DIMM 1 RttWr: 1
29502247.033: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29503247.033: DIMM 0 RttWr: 1
29504247.033: AgesaHwWlPhase1: training nibble 0
29505247.033: DIMM 1 RttNom: 3
29506247.033: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29507247.033: DIMM 1 RttWr: 1
29508247.033: DIMM 1 RttWr: 1
29509247.033: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29510247.033: DIMM 1 RttWr: 1
29511247.033: DIMM 1 RttNom: 3
29512247.033: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29513247.033: DIMM 1 RttNom: 3
29514247.033: DIMM 1 RttWr: 1
29515247.033: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29516247.033: DIMM 1 RttWr: 1
29517247.033: DIMM 0 RttNom: 3
29518247.033: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29519247.033: DIMM 1 RttNom: 3
29520247.033: DIMM 0 RttWr: 1
29521247.033: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29522247.033: DIMM 1 RttWr: 1
29523247.033: DIMM 0 RttNom: 3
29524247.033: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29525247.033: DIMM 1 RttNom: 3
29526247.033: DIMM 0 RttWr: 1
29527247.033: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29528247.033: DIMM 1 RttWr: 1
29529247.033: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
29530247.033: <09>Lane 00 scaled delay: 0052
29531247.033: <09>Lane 00 new seed: 0052
29532247.033: <09>Lane 01 scaled delay: 004f
29533247.033: <09>Lane 01 new seed: 004f
29534247.033: <09>Lane 02 scaled delay: 004e
29535247.033: <09>Lane 02 new seed: 004e
29536247.033: <09>Lane 03 scaled delay: 004d
29537247.033: <09>Lane 03 new seed: 004d
29538247.033: <09>Lane 04 scaled delay: 0045
29539247.033: <09>Lane 04 new seed: 0045
29540247.033: <09>Lane 05 scaled delay: 0047
29541247.033: <09>Lane 05 new seed: 0047
29542247.033: <09>Lane 06 scaled delay: 0049
29543247.033: <09>Lane 06 new seed: 0049
29544247.033: <09>Lane 07 scaled delay: 004a
29545247.033: <09>Lane 07 new seed: 004a
29546247.033: <09>Lane 08 scaled delay: 0046
29547247.033: <09>Lane 08 new seed: 0046
29548247.033: <09>Lane 00 nibble 0 raw readback: 0052
29549247.033: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
29550247.033: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
29551247.033: <09>Lane 01 nibble 0 raw readback: 004e
29552247.033: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
29553247.033: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
29554247.033: <09>Lane 02 nibble 0 raw readback: 0049
29555247.033: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
29556247.033: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
29557247.033: <09>Lane 03 nibble 0 raw readback: 0045
29558247.033: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
29559247.033: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
29560247.033: <09>Lane 04 nibble 0 raw readback: 0038
29561247.033: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
29562247.033: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
29563247.033: <09>Lane 05 nibble 0 raw readback: 003b
29564247.033: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
29565247.034: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
29566247.033: <09>Lane 06 nibble 0 raw readback: 0041
29567247.034: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
29568247.034: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
29569247.034: <09>Lane 07 nibble 0 raw readback: 0044
29570247.034: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
29571247.034: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
29572247.034: <09>Lane 08 nibble 0 raw readback: 003b
29573247.034: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
29574247.034: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
29575247.034: AgesaHwWlPhase1: training nibble 1
29576247.034: DIMM 1 RttNom: 3
29577247.034: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29578247.034: DIMM 1 RttWr: 1
29579247.034: DIMM 1 RttWr: 1
29580247.034: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29581247.034: DIMM 1 RttWr: 1
29582247.034: DIMM 1 RttNom: 3
29583247.034: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29584247.034: DIMM 1 RttNom: 3
29585247.034: DIMM 1 RttWr: 1
29586247.034: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29587247.034: DIMM 1 RttWr: 1
29588247.034: DIMM 0 RttNom: 3
29589247.034: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29590247.034: DIMM 1 RttNom: 3
29591247.034: DIMM 0 RttWr: 1
29592247.034: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29593247.034: DIMM 1 RttWr: 1
29594247.034: DIMM 0 RttNom: 3
29595247.034: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29596247.034: DIMM 1 RttNom: 3
29597247.034: DIMM 0 RttWr: 1
29598247.034: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29599247.034: DIMM 1 RttWr: 1
29600247.034: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
29601247.034: <09>Lane 00 new seed: 0052
29602247.034: <09>Lane 01 new seed: 004f
29603247.034: <09>Lane 02 new seed: 004e
29604247.034: <09>Lane 03 new seed: 004d
29605247.034: <09>Lane 04 new seed: 0045
29606247.034: <09>Lane 05 new seed: 0047
29607247.034: <09>Lane 06 new seed: 0049
29608247.034: <09>Lane 07 new seed: 004a
29609247.034: <09>Lane 08 new seed: 0046
29610247.034: <09>Lane 00 nibble 1 raw readback: 0052
29611247.034: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0052
29612247.034: <09>Lane 00 nibble 1 adjusted value (post nibble): 0052
29613247.034: <09>Lane 01 nibble 1 raw readback: 004d
29614247.034: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004d
29615247.034: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
29616247.034: <09>Lane 02 nibble 1 raw readback: 0049
29617247.034: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
29618247.034: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
29619247.034: <09>Lane 03 nibble 1 raw readback: 0047
29620247.034: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
29621247.034: <09>Lane 03 nibble 1 adjusted value (post nibble): 004a
29622247.034: <09>Lane 04 nibble 1 raw readback: 0037
29623247.034: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
29624247.034: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
29625247.034: <09>Lane 05 nibble 1 raw readback: 003d
29626247.034: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
29627247.034: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
29628247.034: <09>Lane 06 nibble 1 raw readback: 0040
29629247.034: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
29630247.034: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
29631247.034: <09>Lane 07 nibble 1 raw readback: 0043
29632247.034: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0043
29633247.034: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
29634247.034: <09>Lane 08 nibble 1 raw readback: 003c
29635247.034: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
29636247.034: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
29637247.034: <09>original critical gross delay: 0
29638247.034: <09>new critical gross delay: 0
29639247.035: DIMM 1 RttNom: 3
29640247.035: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
29641247.035: DIMM 1 RttNom: 3
29642247.035: DIMM 1 RttWr: 1
29643247.035: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
29644247.035: DIMM 1 RttWr: 1
29645247.035: DIMM 1 RttNom: 3
29646247.035: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
29647247.035: DIMM 1 RttNom: 3
29648247.035: DIMM 1 RttWr: 1
29649247.035: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
29650247.035: DIMM 1 RttWr: 1
29651247.035: DIMM 0 RttNom: 3
29652247.035: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
29653247.035: DIMM 1 RttNom: 3
29654247.035: DIMM 0 RttWr: 1
29655247.035: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
29656247.035: DIMM 1 RttWr: 1
29657247.035: DIMM 0 RttNom: 3
29658247.035: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
29659247.035: DIMM 1 RttNom: 3
29660247.035: DIMM 0 RttWr: 1
29661247.035: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
29662247.035: DIMM 1 RttWr: 1
29663247.035: SetTargetFreq: Start
29664247.035: SetTargetFreq: Node 0: New frequency code: 000e
29665247.035: ChangeMemClk: Start
29666247.035: set_2t_configuration: Start
29667247.035: set_2t_configuration: Done
29668247.035: mct_BeforePlatformSpec: Start
29669247.035: mct_BeforePlatformSpec: Done
29670247.035: mct_PlatformSpec: Start
29671247.035: Programmed DCT 0 timing/termination pattern 00383a38 30222222
29672247.035: mct_PlatformSpec: Done
29673247.035: set_2t_configuration: Start
29674247.036: set_2t_configuration: Done
29675247.035: mct_BeforePlatformSpec: Start
29676247.035: mct_BeforePlatformSpec: Done
29677247.036: mct_PlatformSpec: Start
29678247.036: Programmed DCT 1 timing/termination pattern 00383a38 30222222
29679247.036: mct_PlatformSpec: Done
29680247.036: ChangeMemClk: Done
29681247.036: phyAssistedMemFnceTraining: Start
29682247.036: phyAssistedMemFnceTraining: training node 0 DCT 0
29683247.036: phyAssistedMemFnceTraining: done training node 0 DCT 0
29684247.036: phyAssistedMemFnceTraining: training node 0 DCT 1
29685247.036: phyAssistedMemFnceTraining: done training node 0 DCT 1
29686247.036: phyAssistedMemFnceTraining: Done
29687247.036: InitPhyCompensation: DCT 0: Start
29688247.036: Waiting for predriver calibration to be applied...done!
29689247.036: InitPhyCompensation: DCT 0: Done
29690247.036: phyAssistedMemFnceTraining: Start
29691247.036: phyAssistedMemFnceTraining: training node 0 DCT 0
29692247.036: phyAssistedMemFnceTraining: done training node 0 DCT 0
29693247.036: phyAssistedMemFnceTraining: training node 0 DCT 1
29694247.036: phyAssistedMemFnceTraining: done training node 0 DCT 1
29695247.036: phyAssistedMemFnceTraining: Done
29696247.036: InitPhyCompensation: DCT 1: Start
29697247.036: Waiting for predriver calibration to be applied...done!
29698247.036: InitPhyCompensation: DCT 1: Done
29699247.036: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
29700247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
29701247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
29702247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
29703247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
29704247.037: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
29705247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
29706247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
29707247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
29708247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
29709247.037: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
29710247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
29711247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
29712247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
29713247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
29714247.037: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
29715247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
29716247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
29717247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
29718247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
29719247.037: SetTargetFreq: Done
29720247.037: SPD2ndTiming: Start
29721247.037: SPD2ndTiming: Done
29722247.037: mct_BeforeDramInit_Prod_D: Start
29723247.037: mct_ProgramODT_D: Start
29724247.037: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
29725247.037: mct_ProgramODT_D: Done
29726247.037: mct_BeforeDramInit_Prod_D: Done
29727247.037: mct_DramInit_Sw_D: Start
29728247.037: DIMM 0 RttWr: 2
29729247.037: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
29730247.037: mct_SendMrsCmd: Start
29731247.037: mct_SendMrsCmd: Done
29732247.037: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
29733247.037: mct_SendMrsCmd: Start
29734247.037: mct_SendMrsCmd: Done
29735247.038: DIMM 0 RttNom: 5
29736247.038: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
29737247.038: mct_SendMrsCmd: Start
29738247.038: mct_SendMrsCmd: Done
29739247.038: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
29740247.038: mct_SendMrsCmd: Start
29741247.038: mct_SendMrsCmd: Done
29742247.038: DIMM 0 RttWr: 2
29743247.038: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
29744247.038: mct_SendMrsCmd: Start
29745247.038: mct_SendMrsCmd: Done
29746247.038: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
29747247.038: mct_SendMrsCmd: Start
29748247.038: mct_SendMrsCmd: Done
29749247.038: DIMM 0 RttNom: 5
29750247.038: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
29751247.038: mct_SendMrsCmd: Start
29752247.038: mct_SendMrsCmd: Done
29753247.038: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
29754247.038: mct_SendMrsCmd: Start
29755247.038: mct_SendMrsCmd: Done
29756247.038: DIMM 1 RttWr: 2
29757247.038: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
29758247.038: mct_SendMrsCmd: Start
29759247.038: mct_SendMrsCmd: Done
29760247.038: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
29761247.038: mct_SendMrsCmd: Start
29762247.038: mct_SendMrsCmd: Done
29763247.038: DIMM 1 RttNom: 5
29764247.038: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
29765247.038: mct_SendMrsCmd: Start
29766247.038: mct_SendMrsCmd: Done
29767247.038: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
29768247.038: mct_SendMrsCmd: Start
29769247.038: mct_SendMrsCmd: Done
29770247.038: DIMM 1 RttWr: 2
29771247.038: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
29772247.038: mct_SendMrsCmd: Start
29773247.038: mct_SendMrsCmd: Done
29774247.038: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
29775247.038: mct_SendMrsCmd: Start
29776247.038: mct_SendMrsCmd: Done
29777247.038: DIMM 1 RttNom: 5
29778247.038: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
29779247.038: mct_SendMrsCmd: Start
29780247.038: mct_SendMrsCmd: Done
29781247.038: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
29782247.038: mct_SendMrsCmd: Start
29783247.038: mct_SendMrsCmd: Done
29784247.038: mct_DramInit_Sw_D: Done
29785247.039: AgesaHwWlPhase1: training nibble 0
29786247.039: DIMM 0 RttNom: 5
29787247.039: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
29788247.039: DIMM 0 RttWr: 2
29789247.039: DIMM 0 RttWr: 2
29790247.039: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
29791247.039: DIMM 0 RttWr: 2
29792247.039: DIMM 0 RttNom: 5
29793247.039: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
29794247.039: DIMM 0 RttNom: 5
29795247.039: DIMM 0 RttWr: 2
29796247.039: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
29797247.039: DIMM 0 RttWr: 2
29798247.039: DIMM 1 RttNom: 5
29799247.039: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
29800247.039: DIMM 0 RttNom: 5
29801247.039: DIMM 1 RttWr: 2
29802247.039: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
29803247.039: DIMM 0 RttWr: 2
29804247.039: DIMM 1 RttNom: 5
29805247.039: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
29806247.039: DIMM 0 RttNom: 5
29807247.039: DIMM 1 RttWr: 2
29808247.039: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
29809247.039: DIMM 0 RttWr: 2
29810247.039: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
29811247.039: <09>Lane 00 scaled delay: 006b
29812247.039: <09>Lane 00 new seed: 006b
29813247.039: <09>Lane 01 scaled delay: 0063
29814247.039: <09>Lane 01 new seed: 0063
29815247.039: <09>Lane 02 scaled delay: 0062
29816247.039: <09>Lane 02 new seed: 0062
29817247.039: <09>Lane 03 scaled delay: 005d
29818247.039: <09>Lane 03 new seed: 005d
29819247.039: <09>Lane 04 scaled delay: 004f
29820247.039: <09>Lane 04 new seed: 004f
29821247.039: <09>Lane 05 scaled delay: 0055
29822247.039: <09>Lane 05 new seed: 0055
29823247.039: <09>Lane 06 scaled delay: 0059
29824247.039: <09>Lane 06 new seed: 0059
29825247.039: <09>Lane 07 scaled delay: 005c
29826247.039: <09>Lane 07 new seed: 005c
29827247.039: <09>Lane 08 scaled delay: 0053
29828247.039: <09>Lane 08 new seed: 0053
29829247.039: <09>Lane 00 nibble 0 raw readback: 0030
29830247.039: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
29831247.040: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
29832247.039: <09>Lane 01 nibble 0 raw readback: 0026
29833247.039: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
29834247.039: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
29835247.040: <09>Lane 02 nibble 0 raw readback: 0022
29836247.040: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0062
29837247.040: <09>Lane 02 nibble 0 adjusted value (post nibble): 0062
29838247.040: <09>Lane 03 nibble 0 raw readback: 005c
29839247.040: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
29840247.040: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
29841247.040: <09>Lane 04 nibble 0 raw readback: 004a
29842247.040: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
29843247.040: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
29844247.040: <09>Lane 05 nibble 0 raw readback: 0053
29845247.040: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
29846247.040: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
29847247.040: <09>Lane 06 nibble 0 raw readback: 0058
29848247.040: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
29849247.040: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
29850247.040: <09>Lane 07 nibble 0 raw readback: 005b
29851247.040: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
29852247.040: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
29853247.040: <09>Lane 08 nibble 0 raw readback: 004f
29854247.040: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004f
29855247.040: <09>Lane 08 nibble 0 adjusted value (post nibble): 004f
29856247.040: AgesaHwWlPhase1: training nibble 1
29857247.040: DIMM 0 RttNom: 5
29858247.040: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
29859247.040: DIMM 0 RttWr: 2
29860247.040: DIMM 0 RttWr: 2
29861247.040: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
29862247.040: DIMM 0 RttWr: 2
29863247.040: DIMM 0 RttNom: 5
29864247.040: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
29865247.040: DIMM 0 RttNom: 5
29866247.040: DIMM 0 RttWr: 2
29867247.040: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
29868247.040: DIMM 0 RttWr: 2
29869247.040: DIMM 1 RttNom: 5
29870247.040: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
29871247.040: DIMM 0 RttNom: 5
29872247.040: DIMM 1 RttWr: 2
29873247.040: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
29874247.040: DIMM 0 RttWr: 2
29875247.040: DIMM 1 RttNom: 5
29876247.040: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
29877247.040: DIMM 0 RttNom: 5
29878247.040: DIMM 1 RttWr: 2
29879247.040: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
29880247.040: DIMM 0 RttWr: 2
29881247.040: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
29882247.040: <09>Lane 00 new seed: 006b
29883247.040: <09>Lane 01 new seed: 0063
29884247.040: <09>Lane 02 new seed: 0062
29885247.040: <09>Lane 03 new seed: 005d
29886247.040: <09>Lane 04 new seed: 004f
29887247.040: <09>Lane 05 new seed: 0055
29888247.040: <09>Lane 06 new seed: 0059
29889247.040: <09>Lane 07 new seed: 005c
29890247.040: <09>Lane 08 new seed: 0053
29891247.040: <09>Lane 00 nibble 1 raw readback: 002f
29892247.040: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
29893247.040: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
29894247.040: <09>Lane 01 nibble 1 raw readback: 0026
29895247.040: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
29896247.040: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
29897247.040: <09>Lane 02 nibble 1 raw readback: 0022
29898247.040: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
29899247.040: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
29900247.040: <09>Lane 03 nibble 1 raw readback: 005d
29901247.040: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
29902247.040: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
29903247.040: <09>Lane 04 nibble 1 raw readback: 004a
29904247.040: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
29905247.040: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
29906247.040: <09>Lane 05 nibble 1 raw readback: 0053
29907247.040: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0053
29908247.041: <09>Lane 05 nibble 1 adjusted value (post nibble): 0054
29909247.041: <09>Lane 06 nibble 1 raw readback: 0058
29910247.041: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
29911247.041: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
29912247.041: <09>Lane 07 nibble 1 raw readback: 005a
29913247.041: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005a
29914247.041: <09>Lane 07 nibble 1 adjusted value (post nibble): 005b
29915247.041: <09>Lane 08 nibble 1 raw readback: 004e
29916247.041: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
29917247.041: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
29918247.041: <09>original critical gross delay: 0
29919247.041: <09>new critical gross delay: 0
29920247.041: DIMM 0 RttNom: 5
29921247.041: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
29922247.041: DIMM 0 RttNom: 5
29923247.041: DIMM 0 RttWr: 2
29924247.041: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
29925247.041: DIMM 0 RttWr: 2
29926247.041: DIMM 0 RttNom: 5
29927247.041: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
29928247.041: DIMM 0 RttNom: 5
29929247.041: DIMM 0 RttWr: 2
29930247.041: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
29931247.041: DIMM 0 RttWr: 2
29932247.041: DIMM 1 RttNom: 5
29933247.041: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
29934247.041: DIMM 0 RttNom: 5
29935247.041: DIMM 1 RttWr: 2
29936247.041: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
29937247.041: DIMM 0 RttWr: 2
29938247.041: DIMM 1 RttNom: 5
29939247.041: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
29940247.041: DIMM 0 RttNom: 5
29941247.041: DIMM 1 RttWr: 2
29942247.041: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
29943247.041: DIMM 0 RttWr: 2
29944247.041: AgesaHwWlPhase1: training nibble 0
29945247.041: DIMM 1 RttNom: 5
29946247.041: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
29947247.041: DIMM 1 RttWr: 2
29948247.041: DIMM 1 RttWr: 2
29949247.041: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
29950247.041: DIMM 1 RttWr: 2
29951247.041: DIMM 1 RttNom: 5
29952247.041: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
29953247.041: DIMM 1 RttNom: 5
29954247.041: DIMM 1 RttWr: 2
29955247.041: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
29956247.041: DIMM 1 RttWr: 2
29957247.041: DIMM 0 RttNom: 5
29958247.041: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
29959247.041: DIMM 1 RttNom: 5
29960247.041: DIMM 0 RttWr: 2
29961247.041: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
29962247.041: DIMM 1 RttWr: 2
29963247.041: DIMM 0 RttNom: 5
29964247.041: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
29965247.041: DIMM 1 RttNom: 5
29966247.041: DIMM 0 RttWr: 2
29967247.041: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
29968247.041: DIMM 1 RttWr: 2
29969247.042: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
29970247.041: <09>Lane 00 scaled delay: 005e
29971247.041: <09>Lane 00 new seed: 005e
29972247.042: <09>Lane 01 scaled delay: 0058
29973247.042: <09>Lane 01 new seed: 0058
29974247.042: <09>Lane 02 scaled delay: 0057
29975247.042: <09>Lane 02 new seed: 0057
29976247.042: <09>Lane 03 scaled delay: 0050
29977247.042: <09>Lane 03 new seed: 0050
29978247.042: <09>Lane 04 scaled delay: 0043
29979247.042: <09>Lane 04 new seed: 0043
29980247.042: <09>Lane 05 scaled delay: 004a
29981247.042: <09>Lane 05 new seed: 004a
29982247.042: <09>Lane 06 scaled delay: 004b
29983247.042: <09>Lane 06 new seed: 004b
29984247.042: <09>Lane 07 scaled delay: 0050
29985247.042: <09>Lane 07 new seed: 0050
29986247.042: <09>Lane 08 scaled delay: 0046
29987247.042: <09>Lane 08 new seed: 0046
29988247.042: <09>Lane 00 nibble 0 raw readback: 0060
29989247.042: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
29990247.042: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
29991247.042: <09>Lane 01 nibble 0 raw readback: 0056
29992247.042: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
29993247.042: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
29994247.042: <09>Lane 02 nibble 0 raw readback: 0051
29995247.042: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0051
29996247.042: <09>Lane 02 nibble 0 adjusted value (post nibble): 0051
29997247.042: <09>Lane 03 nibble 0 raw readback: 004d
29998247.042: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
29999247.042: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
30000247.042: <09>Lane 04 nibble 0 raw readback: 003c
30001247.042: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003c
30002247.042: <09>Lane 04 nibble 0 adjusted value (post nibble): 003c
30003247.042: <09>Lane 05 nibble 0 raw readback: 0045
30004247.042: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0045
30005247.042: <09>Lane 05 nibble 0 adjusted value (post nibble): 0045
30006247.042: <09>Lane 06 nibble 0 raw readback: 0047
30007247.042: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0047
30008247.042: <09>Lane 06 nibble 0 adjusted value (post nibble): 0047
30009247.042: <09>Lane 07 nibble 0 raw readback: 004c
30010247.042: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004c
30011247.042: <09>Lane 07 nibble 0 adjusted value (post nibble): 004c
30012247.042: <09>Lane 08 nibble 0 raw readback: 003f
30013247.042: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
30014247.042: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
30015247.042: AgesaHwWlPhase1: training nibble 1
30016247.042: DIMM 1 RttNom: 5
30017247.042: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
30018247.042: DIMM 1 RttWr: 2
30019247.042: DIMM 1 RttWr: 2
30020247.042: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
30021247.042: DIMM 1 RttWr: 2
30022247.042: DIMM 1 RttNom: 5
30023247.042: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
30024247.042: DIMM 1 RttNom: 5
30025247.042: DIMM 1 RttWr: 2
30026247.042: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
30027247.042: DIMM 1 RttWr: 2
30028247.042: DIMM 0 RttNom: 5
30029247.042: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
30030247.042: DIMM 1 RttNom: 5
30031247.042: DIMM 0 RttWr: 2
30032247.042: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
30033247.042: DIMM 1 RttWr: 2
30034247.042: DIMM 0 RttNom: 5
30035247.042: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
30036247.042: DIMM 1 RttNom: 5
30037247.042: DIMM 0 RttWr: 2
30038247.042: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
30039247.042: DIMM 1 RttWr: 2
30040247.042: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
30041247.042: <09>Lane 00 new seed: 005e
30042247.042: <09>Lane 01 new seed: 0058
30043247.042: <09>Lane 02 new seed: 0057
30044247.042: <09>Lane 03 new seed: 0050
30045247.042: <09>Lane 04 new seed: 0043
30046247.042: <09>Lane 05 new seed: 004a
30047247.042: <09>Lane 06 new seed: 004b
30048247.043: <09>Lane 07 new seed: 0050
30049247.043: <09>Lane 08 new seed: 0046
30050247.043: <09>Lane 00 nibble 1 raw readback: 005f
30051247.043: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
30052247.043: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
30053247.043: <09>Lane 01 nibble 1 raw readback: 0057
30054247.043: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0057
30055247.043: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
30056247.043: <09>Lane 02 nibble 1 raw readback: 0054
30057247.043: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
30058247.043: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
30059247.043: <09>Lane 03 nibble 1 raw readback: 004e
30060247.043: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
30061247.043: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
30062247.043: <09>Lane 04 nibble 1 raw readback: 003c
30063247.043: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003c
30064247.043: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
30065247.043: <09>Lane 05 nibble 1 raw readback: 0044
30066247.043: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0044
30067247.043: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
30068247.043: <09>Lane 06 nibble 1 raw readback: 0049
30069247.043: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
30070247.043: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
30071247.043: <09>Lane 07 nibble 1 raw readback: 004d
30072247.043: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
30073247.043: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
30074247.043: <09>Lane 08 nibble 1 raw readback: 003f
30075247.043: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
30076247.043: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
30077247.043: <09>original critical gross delay: 0
30078247.043: <09>new critical gross delay: 0
30079247.043: DIMM 1 RttNom: 5
30080247.043: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
30081247.043: DIMM 1 RttNom: 5
30082247.043: DIMM 1 RttWr: 2
30083247.043: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
30084247.043: DIMM 1 RttWr: 2
30085247.043: DIMM 1 RttNom: 5
30086247.043: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
30087247.043: DIMM 1 RttNom: 5
30088247.043: DIMM 1 RttWr: 2
30089247.043: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
30090247.043: DIMM 1 RttWr: 2
30091247.043: DIMM 0 RttNom: 5
30092247.043: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
30093247.043: DIMM 1 RttNom: 5
30094247.043: DIMM 0 RttWr: 2
30095247.043: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
30096247.043: DIMM 1 RttWr: 2
30097247.043: DIMM 0 RttNom: 5
30098247.043: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
30099247.043: DIMM 1 RttNom: 5
30100247.043: DIMM 0 RttWr: 2
30101247.043: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
30102247.043: DIMM 1 RttWr: 2
30103247.043: SPD2ndTiming: Start
30104247.044: SPD2ndTiming: Done
30105247.044: mct_BeforeDramInit_Prod_D: Start
30106247.044: mct_ProgramODT_D: Start
30107247.044: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
30108247.044: mct_ProgramODT_D: Done
30109247.044: mct_BeforeDramInit_Prod_D: Done
30110247.044: mct_DramInit_Sw_D: Start
30111247.044: DIMM 0 RttWr: 2
30112247.044: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30113247.044: mct_SendMrsCmd: Start
30114247.044: mct_SendMrsCmd: Done
30115247.044: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
30116247.044: mct_SendMrsCmd: Start
30117247.044: mct_SendMrsCmd: Done
30118247.044: DIMM 0 RttNom: 5
30119247.044: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30120247.044: mct_SendMrsCmd: Start
30121247.044: mct_SendMrsCmd: Done
30122247.044: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
30123247.044: mct_SendMrsCmd: Start
30124247.044: mct_SendMrsCmd: Done
30125247.044: DIMM 0 RttWr: 2
30126247.044: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30127247.044: mct_SendMrsCmd: Start
30128247.044: mct_SendMrsCmd: Done
30129247.044: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
30130247.044: mct_SendMrsCmd: Start
30131247.044: mct_SendMrsCmd: Done
30132247.044: DIMM 0 RttNom: 5
30133247.044: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30134247.044: mct_SendMrsCmd: Start
30135247.044: mct_SendMrsCmd: Done
30136247.044: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
30137247.044: mct_SendMrsCmd: Start
30138247.044: mct_SendMrsCmd: Done
30139247.044: DIMM 1 RttWr: 2
30140247.044: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30141247.044: mct_SendMrsCmd: Start
30142247.044: mct_SendMrsCmd: Done
30143247.044: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
30144247.044: mct_SendMrsCmd: Start
30145247.044: mct_SendMrsCmd: Done
30146247.045: DIMM 1 RttNom: 5
30147247.045: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30148247.045: mct_SendMrsCmd: Start
30149247.045: mct_SendMrsCmd: Done
30150247.045: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
30151247.045: mct_SendMrsCmd: Start
30152247.045: mct_SendMrsCmd: Done
30153247.045: DIMM 1 RttWr: 2
30154247.045: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30155247.045: mct_SendMrsCmd: Start
30156247.045: mct_SendMrsCmd: Done
30157247.045: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
30158247.045: mct_SendMrsCmd: Start
30159247.045: mct_SendMrsCmd: Done
30160247.045: DIMM 1 RttNom: 5
30161247.045: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30162247.045: mct_SendMrsCmd: Start
30163247.045: mct_SendMrsCmd: Done
30164247.045: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
30165247.045: mct_SendMrsCmd: Start
30166247.045: mct_SendMrsCmd: Done
30167247.045: mct_DramInit_Sw_D: Done
30168247.045: AgesaHwWlPhase1: training nibble 0
30169247.045: DIMM 0 RttNom: 5
30170247.045: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30171247.045: DIMM 0 RttWr: 2
30172247.045: DIMM 0 RttWr: 2
30173247.045: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30174247.045: DIMM 0 RttWr: 2
30175247.045: DIMM 0 RttNom: 5
30176247.045: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30177247.045: DIMM 0 RttNom: 5
30178247.045: DIMM 0 RttWr: 2
30179247.045: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30180247.045: DIMM 0 RttWr: 2
30181247.045: DIMM 1 RttNom: 5
30182247.045: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30183247.045: DIMM 0 RttNom: 5
30184247.045: DIMM 1 RttWr: 2
30185247.045: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30186247.045: DIMM 0 RttWr: 2
30187247.045: DIMM 1 RttNom: 5
30188247.045: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30189247.045: DIMM 0 RttNom: 5
30190247.045: DIMM 1 RttWr: 2
30191247.045: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30192247.045: DIMM 0 RttWr: 2
30193247.045: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
30194247.045: <09>Lane 00 scaled delay: 0068
30195247.045: <09>Lane 00 new seed: 0068
30196247.045: <09>Lane 01 scaled delay: 0062
30197247.045: <09>Lane 01 new seed: 0062
30198247.045: <09>Lane 02 scaled delay: 005f
30199247.045: <09>Lane 02 new seed: 005f
30200247.045: <09>Lane 03 scaled delay: 005c
30201247.045: <09>Lane 03 new seed: 005c
30202247.045: <09>Lane 04 scaled delay: 004e
30203247.045: <09>Lane 04 new seed: 004e
30204247.045: <09>Lane 05 scaled delay: 0050
30205247.045: <09>Lane 05 new seed: 0050
30206247.045: <09>Lane 06 scaled delay: 0057
30207247.045: <09>Lane 06 new seed: 0057
30208247.045: <09>Lane 07 scaled delay: 0059
30209247.046: <09>Lane 07 new seed: 0059
30210247.045: <09>Lane 08 scaled delay: 0050
30211247.046: <09>Lane 08 new seed: 0050
30212247.046: <09>Lane 00 nibble 0 raw readback: 002b
30213247.046: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006b
30214247.046: <09>Lane 00 nibble 0 adjusted value (post nibble): 006b
30215247.046: <09>Lane 01 nibble 0 raw readback: 0025
30216247.046: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
30217247.046: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
30218247.046: <09>Lane 02 nibble 0 raw readback: 0060
30219247.046: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
30220247.046: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
30221247.046: <09>Lane 03 nibble 0 raw readback: 005b
30222247.046: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
30223247.046: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
30224247.046: <09>Lane 04 nibble 0 raw readback: 004a
30225247.046: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
30226247.046: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
30227247.046: <09>Lane 05 nibble 0 raw readback: 0050
30228247.046: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0050
30229247.046: <09>Lane 05 nibble 0 adjusted value (post nibble): 0050
30230247.046: <09>Lane 06 nibble 0 raw readback: 0053
30231247.046: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0053
30232247.046: <09>Lane 06 nibble 0 adjusted value (post nibble): 0053
30233247.046: <09>Lane 07 nibble 0 raw readback: 0058
30234247.046: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
30235247.046: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
30236247.046: <09>Lane 08 nibble 0 raw readback: 004d
30237247.046: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004d
30238247.046: <09>Lane 08 nibble 0 adjusted value (post nibble): 004d
30239247.046: AgesaHwWlPhase1: training nibble 1
30240247.046: DIMM 0 RttNom: 5
30241247.046: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30242247.046: DIMM 0 RttWr: 2
30243247.046: DIMM 0 RttWr: 2
30244247.046: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30245247.046: DIMM 0 RttWr: 2
30246247.046: DIMM 0 RttNom: 5
30247247.046: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30248247.046: DIMM 0 RttNom: 5
30249247.046: DIMM 0 RttWr: 2
30250247.046: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30251247.046: DIMM 0 RttWr: 2
30252247.046: DIMM 1 RttNom: 5
30253247.046: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30254247.046: DIMM 0 RttNom: 5
30255247.046: DIMM 1 RttWr: 2
30256247.046: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30257247.046: DIMM 0 RttWr: 2
30258247.046: DIMM 1 RttNom: 5
30259247.046: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30260247.046: DIMM 0 RttNom: 5
30261247.046: DIMM 1 RttWr: 2
30262247.046: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30263247.046: DIMM 0 RttWr: 2
30264247.046: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
30265247.046: <09>Lane 00 new seed: 0068
30266247.046: <09>Lane 01 new seed: 0062
30267247.046: <09>Lane 02 new seed: 005f
30268247.046: <09>Lane 03 new seed: 005c
30269247.046: <09>Lane 04 new seed: 004e
30270247.046: <09>Lane 05 new seed: 0050
30271247.046: <09>Lane 06 new seed: 0057
30272247.046: <09>Lane 07 new seed: 0059
30273247.046: <09>Lane 08 new seed: 0050
30274247.047: <09>Lane 00 nibble 1 raw readback: 002c
30275247.047: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
30276247.047: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
30277247.047: <09>Lane 01 nibble 1 raw readback: 0024
30278247.047: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0064
30279247.047: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
30280247.047: <09>Lane 02 nibble 1 raw readback: 0061
30281247.047: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
30282247.047: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
30283247.047: <09>Lane 03 nibble 1 raw readback: 005b
30284247.047: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
30285247.047: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
30286247.047: <09>Lane 04 nibble 1 raw readback: 0049
30287247.047: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
30288247.047: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
30289247.047: <09>Lane 05 nibble 1 raw readback: 004f
30290247.047: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
30291247.047: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
30292247.047: <09>Lane 06 nibble 1 raw readback: 0055
30293247.047: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
30294247.047: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
30295247.047: <09>Lane 07 nibble 1 raw readback: 0059
30296247.047: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0059
30297247.047: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
30298247.047: <09>Lane 08 nibble 1 raw readback: 004d
30299247.047: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004d
30300247.047: <09>Lane 08 nibble 1 adjusted value (post nibble): 004e
30301247.047: <09>original critical gross delay: 0
30302247.047: <09>new critical gross delay: 0
30303247.047: DIMM 0 RttNom: 5
30304247.047: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30305247.047: DIMM 0 RttNom: 5
30306247.047: DIMM 0 RttWr: 2
30307247.047: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30308247.047: DIMM 0 RttWr: 2
30309247.047: DIMM 0 RttNom: 5
30310247.047: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30311247.047: DIMM 0 RttNom: 5
30312247.047: DIMM 0 RttWr: 2
30313247.047: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30314247.047: DIMM 0 RttWr: 2
30315247.047: DIMM 1 RttNom: 5
30316247.047: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30317247.047: DIMM 0 RttNom: 5
30318247.047: DIMM 1 RttWr: 2
30319247.047: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30320247.047: DIMM 0 RttWr: 2
30321247.047: DIMM 1 RttNom: 5
30322247.047: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30323247.047: DIMM 0 RttNom: 5
30324247.047: DIMM 1 RttWr: 2
30325247.047: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30326247.047: DIMM 0 RttWr: 2
30327247.047: AgesaHwWlPhase1: training nibble 0
30328247.047: DIMM 1 RttNom: 5
30329247.047: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30330247.047: DIMM 1 RttWr: 2
30331247.047: DIMM 1 RttWr: 2
30332247.047: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30333247.047: DIMM 1 RttWr: 2
30334247.047: DIMM 1 RttNom: 5
30335247.047: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30336247.047: DIMM 1 RttNom: 5
30337247.047: DIMM 1 RttWr: 2
30338247.047: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30339247.047: DIMM 1 RttWr: 2
30340247.047: DIMM 0 RttNom: 5
30341247.047: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30342247.047: DIMM 1 RttNom: 5
30343247.047: DIMM 0 RttWr: 2
30344247.048: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30345247.048: DIMM 1 RttWr: 2
30346247.048: DIMM 0 RttNom: 5
30347247.048: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30348247.048: DIMM 1 RttNom: 5
30349247.048: DIMM 0 RttWr: 2
30350247.048: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30351247.048: DIMM 1 RttWr: 2
30352247.048: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
30353247.048: <09>Lane 00 scaled delay: 005e
30354247.048: <09>Lane 00 new seed: 005e
30355247.048: <09>Lane 01 scaled delay: 0059
30356247.048: <09>Lane 01 new seed: 0059
30357247.048: <09>Lane 02 scaled delay: 0055
30358247.048: <09>Lane 02 new seed: 0055
30359247.048: <09>Lane 03 scaled delay: 0054
30360247.048: <09>Lane 03 new seed: 0054
30361247.048: <09>Lane 04 scaled delay: 0045
30362247.048: <09>Lane 04 new seed: 0045
30363247.048: <09>Lane 05 scaled delay: 004a
30364247.048: <09>Lane 05 new seed: 004a
30365247.048: <09>Lane 06 scaled delay: 004d
30366247.048: <09>Lane 06 new seed: 004d
30367247.048: <09>Lane 07 scaled delay: 004f
30368247.048: <09>Lane 07 new seed: 004f
30369247.048: <09>Lane 08 scaled delay: 0049
30370247.048: <09>Lane 08 new seed: 0049
30371247.048: <09>Lane 00 nibble 0 raw readback: 005e
30372247.048: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
30373247.048: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
30374247.048: <09>Lane 01 nibble 0 raw readback: 0059
30375247.048: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
30376247.048: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
30377247.048: <09>Lane 02 nibble 0 raw readback: 0051
30378247.048: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0051
30379247.048: <09>Lane 02 nibble 0 adjusted value (post nibble): 0051
30380247.048: <09>Lane 03 nibble 0 raw readback: 004d
30381247.048: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
30382247.048: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
30383247.048: <09>Lane 04 nibble 0 raw readback: 003d
30384247.048: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003d
30385247.048: <09>Lane 04 nibble 0 adjusted value (post nibble): 003d
30386247.048: <09>Lane 05 nibble 0 raw readback: 0041
30387247.048: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
30388247.048: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
30389247.048: <09>Lane 06 nibble 0 raw readback: 0048
30390247.048: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
30391247.048: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
30392247.048: <09>Lane 07 nibble 0 raw readback: 004d
30393247.048: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
30394247.048: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
30395247.048: <09>Lane 08 nibble 0 raw readback: 0041
30396247.048: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
30397247.048: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
30398247.048: AgesaHwWlPhase1: training nibble 1
30399247.048: DIMM 1 RttNom: 5
30400247.048: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30401247.048: DIMM 1 RttWr: 2
30402247.048: DIMM 1 RttWr: 2
30403247.048: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30404247.048: DIMM 1 RttWr: 2
30405247.048: DIMM 1 RttNom: 5
30406247.048: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30407247.048: DIMM 1 RttNom: 5
30408247.048: DIMM 1 RttWr: 2
30409247.048: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30410247.048: DIMM 1 RttWr: 2
30411247.048: DIMM 0 RttNom: 5
30412247.048: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30413247.048: DIMM 1 RttNom: 5
30414247.048: DIMM 0 RttWr: 2
30415247.048: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30416247.048: DIMM 1 RttWr: 2
30417247.048: DIMM 0 RttNom: 5
30418247.048: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30419247.049: DIMM 1 RttNom: 5
30420247.049: DIMM 0 RttWr: 2
30421247.049: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30422247.049: DIMM 1 RttWr: 2
30423247.049: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
30424247.049: <09>Lane 00 new seed: 005e
30425247.049: <09>Lane 01 new seed: 0059
30426247.049: <09>Lane 02 new seed: 0055
30427247.049: <09>Lane 03 new seed: 0054
30428247.049: <09>Lane 04 new seed: 0045
30429247.049: <09>Lane 05 new seed: 004a
30430247.049: <09>Lane 06 new seed: 004d
30431247.049: <09>Lane 07 new seed: 004f
30432247.049: <09>Lane 08 new seed: 0049
30433247.049: <09>Lane 00 nibble 1 raw readback: 005e
30434247.049: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005e
30435247.049: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
30436247.049: <09>Lane 01 nibble 1 raw readback: 0059
30437247.049: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
30438247.049: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
30439247.049: <09>Lane 02 nibble 1 raw readback: 0052
30440247.049: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0052
30441247.049: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
30442247.049: <09>Lane 03 nibble 1 raw readback: 0050
30443247.049: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
30444247.049: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
30445247.049: <09>Lane 04 nibble 1 raw readback: 003d
30446247.049: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003d
30447247.049: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
30448247.049: <09>Lane 05 nibble 1 raw readback: 0045
30449247.049: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
30450247.049: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
30451247.049: <09>Lane 06 nibble 1 raw readback: 0048
30452247.049: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0048
30453247.049: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
30454247.049: <09>Lane 07 nibble 1 raw readback: 004c
30455247.049: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
30456247.049: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
30457247.049: <09>Lane 08 nibble 1 raw readback: 0042
30458247.049: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0042
30459247.049: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
30460247.049: <09>original critical gross delay: 0
30461247.049: <09>new critical gross delay: 0
30462247.049: DIMM 1 RttNom: 5
30463247.049: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
30464247.049: DIMM 1 RttNom: 5
30465247.049: DIMM 1 RttWr: 2
30466247.049: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
30467247.049: DIMM 1 RttWr: 2
30468247.049: DIMM 1 RttNom: 5
30469247.049: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
30470247.049: DIMM 1 RttNom: 5
30471247.049: DIMM 1 RttWr: 2
30472247.049: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
30473247.049: DIMM 1 RttWr: 2
30474247.049: DIMM 0 RttNom: 5
30475247.049: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
30476247.049: DIMM 1 RttNom: 5
30477247.049: DIMM 0 RttWr: 2
30478247.049: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
30479247.049: DIMM 1 RttWr: 2
30480247.049: DIMM 0 RttNom: 5
30481247.049: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
30482247.049: DIMM 1 RttNom: 5
30483247.049: DIMM 0 RttWr: 2
30484247.049: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
30485247.049: DIMM 1 RttWr: 2
30486247.050: SetTargetFreq: Start
30487247.050: SetTargetFreq: Node 0: New frequency code: 0012
30488247.050: ChangeMemClk: Start
30489247.050: set_2t_configuration: Start
30490247.050: set_2t_configuration: Done
30491247.050: mct_BeforePlatformSpec: Start
30492247.050: mct_BeforePlatformSpec: Done
30493247.050: mct_PlatformSpec: Start
30494247.050: Programmed DCT 0 timing/termination pattern 00353935 30222222
30495247.050: mct_PlatformSpec: Done
30496247.050: set_2t_configuration: Start
30497247.050: set_2t_configuration: Done
30498247.050: mct_BeforePlatformSpec: Start
30499247.050: mct_BeforePlatformSpec: Done
30500247.050: mct_PlatformSpec: Start
30501247.050: Programmed DCT 1 timing/termination pattern 00353935 30222222
30502247.050: mct_PlatformSpec: Done
30503247.050: ChangeMemClk: Done
30504247.050: phyAssistedMemFnceTraining: Start
30505247.050: phyAssistedMemFnceTraining: training node 0 DCT 0
30506247.050: phyAssistedMemFnceTraining: done training node 0 DCT 0
30507247.050: phyAssistedMemFnceTraining: training node 0 DCT 1
30508247.050: phyAssistedMemFnceTraining: done training node 0 DCT 1
30509247.050: phyAssistedMemFnceTraining: Done
30510247.050: InitPhyCompensation: DCT 0: Start
30511247.050: Waiting for predriver calibration to be applied...done!
30512247.050: InitPhyCompensation: DCT 0: Done
30513247.051: phyAssistedMemFnceTraining: Start
30514247.051: phyAssistedMemFnceTraining: training node 0 DCT 0
30515247.051: phyAssistedMemFnceTraining: done training node 0 DCT 0
30516247.051: phyAssistedMemFnceTraining: training node 0 DCT 1
30517247.051: phyAssistedMemFnceTraining: done training node 0 DCT 1
30518247.051: phyAssistedMemFnceTraining: Done
30519247.051: InitPhyCompensation: DCT 1: Start
30520247.051: Waiting for predriver calibration to be applied...done!
30521247.051: InitPhyCompensation: DCT 1: Done
30522247.051: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
30523247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
30524247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
30525247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
30526247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
30527247.051: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
30528247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
30529247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
30530247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
30531247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
30532247.051: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
30533247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
30534247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
30535247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
30536247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
30537247.051: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
30538247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
30539247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
30540247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
30541247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
30542247.051: SetTargetFreq: Done
30543247.051: SPD2ndTiming: Start
30544247.052: SPD2ndTiming: Done
30545247.052: mct_BeforeDramInit_Prod_D: Start
30546247.052: mct_ProgramODT_D: Start
30547247.052: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
30548247.052: mct_ProgramODT_D: Done
30549247.052: mct_BeforeDramInit_Prod_D: Done
30550247.052: mct_DramInit_Sw_D: Start
30551247.052: DIMM 0 RttWr: 1
30552247.052: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30553247.052: mct_SendMrsCmd: Start
30554247.052: mct_SendMrsCmd: Done
30555247.052: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
30556247.052: mct_SendMrsCmd: Start
30557247.052: mct_SendMrsCmd: Done
30558247.052: DIMM 0 RttNom: 4
30559247.052: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30560247.052: mct_SendMrsCmd: Start
30561247.052: mct_SendMrsCmd: Done
30562247.052: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
30563247.052: mct_SendMrsCmd: Start
30564247.052: mct_SendMrsCmd: Done
30565247.052: DIMM 0 RttWr: 1
30566247.052: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30567247.052: mct_SendMrsCmd: Start
30568247.052: mct_SendMrsCmd: Done
30569247.052: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
30570247.052: mct_SendMrsCmd: Start
30571247.052: mct_SendMrsCmd: Done
30572247.052: DIMM 0 RttNom: 4
30573247.052: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30574247.052: mct_SendMrsCmd: Start
30575247.052: mct_SendMrsCmd: Done
30576247.052: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
30577247.052: mct_SendMrsCmd: Start
30578247.053: mct_SendMrsCmd: Done
30579247.052: DIMM 1 RttWr: 1
30580247.052: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30581247.052: mct_SendMrsCmd: Start
30582247.052: mct_SendMrsCmd: Done
30583247.052: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
30584247.053: mct_SendMrsCmd: Start
30585247.053: mct_SendMrsCmd: Done
30586247.053: DIMM 1 RttNom: 4
30587247.053: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30588247.053: mct_SendMrsCmd: Start
30589247.053: mct_SendMrsCmd: Done
30590247.053: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
30591247.053: mct_SendMrsCmd: Start
30592247.053: mct_SendMrsCmd: Done
30593247.053: DIMM 1 RttWr: 1
30594247.053: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30595247.053: mct_SendMrsCmd: Start
30596247.053: mct_SendMrsCmd: Done
30597247.053: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
30598247.053: mct_SendMrsCmd: Start
30599247.053: mct_SendMrsCmd: Done
30600247.053: DIMM 1 RttNom: 4
30601247.053: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30602247.053: mct_SendMrsCmd: Start
30603247.053: mct_SendMrsCmd: Done
30604247.053: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
30605247.053: mct_SendMrsCmd: Start
30606247.053: mct_SendMrsCmd: Done
30607247.053: mct_DramInit_Sw_D: Done
30608247.053: AgesaHwWlPhase1: training nibble 0
30609247.053: DIMM 0 RttNom: 4
30610247.053: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30611247.053: DIMM 0 RttWr: 1
30612247.053: DIMM 0 RttWr: 1
30613247.053: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30614247.053: DIMM 0 RttWr: 1
30615247.053: DIMM 0 RttNom: 4
30616247.053: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30617247.053: DIMM 0 RttNom: 4
30618247.053: DIMM 0 RttWr: 1
30619247.053: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30620247.053: DIMM 0 RttWr: 1
30621247.053: DIMM 1 RttNom: 4
30622247.053: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30623247.053: DIMM 0 RttNom: 4
30624247.053: DIMM 1 RttWr: 1
30625247.053: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30626247.053: DIMM 0 RttWr: 1
30627247.053: DIMM 1 RttNom: 4
30628247.053: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30629247.053: DIMM 0 RttNom: 4
30630247.053: DIMM 1 RttWr: 1
30631247.053: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30632247.053: DIMM 0 RttWr: 1
30633247.053: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
30634247.054: <09>Lane 00 scaled delay: 007c
30635247.054: <09>Lane 00 new seed: 007c
30636247.054: <09>Lane 01 scaled delay: 0071
30637247.054: <09>Lane 01 new seed: 0071
30638247.054: <09>Lane 02 scaled delay: 006f
30639247.054: <09>Lane 02 new seed: 006f
30640247.054: <09>Lane 03 scaled delay: 0069
30641247.054: <09>Lane 03 new seed: 0069
30642247.054: <09>Lane 04 scaled delay: 0054
30643247.054: <09>Lane 04 new seed: 0054
30644247.054: <09>Lane 05 scaled delay: 005e
30645247.054: <09>Lane 05 new seed: 005e
30646247.054: <09>Lane 06 scaled delay: 0063
30647247.054: <09>Lane 06 new seed: 0063
30648247.054: <09>Lane 07 scaled delay: 0066
30649247.054: <09>Lane 07 new seed: 0066
30650247.054: <09>Lane 08 scaled delay: 0059
30651247.054: <09>Lane 08 new seed: 0059
30652247.054: <09>Lane 00 nibble 0 raw readback: 0042
30653247.054: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0082
30654247.054: <09>Lane 00 nibble 0 adjusted value (post nibble): 0082
30655247.054: <09>Lane 01 nibble 0 raw readback: 0036
30656247.054: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0076
30657247.054: <09>Lane 01 nibble 0 adjusted value (post nibble): 0076
30658247.054: <09>Lane 02 nibble 0 raw readback: 0031
30659247.054: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0071
30660247.054: <09>Lane 02 nibble 0 adjusted value (post nibble): 0071
30661247.054: <09>Lane 03 nibble 0 raw readback: 002a
30662247.054: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
30663247.054: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
30664247.054: <09>Lane 04 nibble 0 raw readback: 0057
30665247.054: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
30666247.054: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
30667247.054: <09>Lane 05 nibble 0 raw readback: 005f
30668247.054: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005f
30669247.054: <09>Lane 05 nibble 0 adjusted value (post nibble): 005f
30670247.054: <09>Lane 06 nibble 0 raw readback: 0025
30671247.054: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
30672247.054: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
30673247.054: <09>Lane 07 nibble 0 raw readback: 0029
30674247.054: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
30675247.054: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
30676247.054: <09>Lane 08 nibble 0 raw readback: 005b
30677247.054: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005b
30678247.054: <09>Lane 08 nibble 0 adjusted value (post nibble): 005b
30679247.054: AgesaHwWlPhase1: training nibble 1
30680247.054: DIMM 0 RttNom: 4
30681247.054: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30682247.054: DIMM 0 RttWr: 1
30683247.054: DIMM 0 RttWr: 1
30684247.054: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30685247.054: DIMM 0 RttWr: 1
30686247.054: DIMM 0 RttNom: 4
30687247.054: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30688247.054: DIMM 0 RttNom: 4
30689247.055: DIMM 0 RttWr: 1
30690247.055: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30691247.055: DIMM 0 RttWr: 1
30692247.055: DIMM 1 RttNom: 4
30693247.055: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30694247.055: DIMM 0 RttNom: 4
30695247.055: DIMM 1 RttWr: 1
30696247.055: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30697247.055: DIMM 0 RttWr: 1
30698247.055: DIMM 1 RttNom: 4
30699247.055: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30700247.055: DIMM 0 RttNom: 4
30701247.055: DIMM 1 RttWr: 1
30702247.055: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30703247.055: DIMM 0 RttWr: 1
30704247.055: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
30705247.055: <09>Lane 00 new seed: 007c
30706247.055: <09>Lane 01 new seed: 0071
30707247.055: <09>Lane 02 new seed: 006f
30708247.055: <09>Lane 03 new seed: 0069
30709247.055: <09>Lane 04 new seed: 0054
30710247.055: <09>Lane 05 new seed: 005e
30711247.055: <09>Lane 06 new seed: 0063
30712247.055: <09>Lane 07 new seed: 0066
30713247.055: <09>Lane 08 new seed: 0059
30714247.055: <09>Lane 00 nibble 1 raw readback: 0040
30715247.055: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0080
30716247.055: <09>Lane 00 nibble 1 adjusted value (post nibble): 007e
30717247.055: <09>Lane 01 nibble 1 raw readback: 0036
30718247.055: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0076
30719247.055: <09>Lane 01 nibble 1 adjusted value (post nibble): 0073
30720247.055: <09>Lane 02 nibble 1 raw readback: 0032
30721247.055: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
30722247.055: <09>Lane 02 nibble 1 adjusted value (post nibble): 0070
30723247.055: <09>Lane 03 nibble 1 raw readback: 002c
30724247.055: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
30725247.055: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
30726247.055: <09>Lane 04 nibble 1 raw readback: 0056
30727247.055: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
30728247.055: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
30729247.055: <09>Lane 05 nibble 1 raw readback: 005f
30730247.055: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
30731247.055: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
30732247.055: <09>Lane 06 nibble 1 raw readback: 0025
30733247.055: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0065
30734247.055: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
30735247.055: <09>Lane 07 nibble 1 raw readback: 0029
30736247.055: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0069
30737247.055: <09>Lane 07 nibble 1 adjusted value (post nibble): 0067
30738247.055: <09>Lane 08 nibble 1 raw readback: 005c
30739247.055: <09>Lane 08 nibble 1 adjusted value (pre nibble): 005c
30740247.055: <09>Lane 08 nibble 1 adjusted value (post nibble): 005a
30741247.055: <09>original critical gross delay: 0
30742247.055: <09>new critical gross delay: 0
30743247.055: DIMM 0 RttNom: 4
30744247.055: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30745247.055: DIMM 0 RttNom: 4
30746247.055: DIMM 0 RttWr: 1
30747247.055: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30748247.055: DIMM 0 RttWr: 1
30749247.055: DIMM 0 RttNom: 4
30750247.055: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30751247.055: DIMM 0 RttNom: 4
30752247.056: DIMM 0 RttWr: 1
30753247.055: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30754247.055: DIMM 0 RttWr: 1
30755247.056: DIMM 1 RttNom: 4
30756247.056: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30757247.056: DIMM 0 RttNom: 4
30758247.056: DIMM 1 RttWr: 1
30759247.056: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30760247.056: DIMM 0 RttWr: 1
30761247.056: DIMM 1 RttNom: 4
30762247.056: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30763247.056: DIMM 0 RttNom: 4
30764247.056: DIMM 1 RttWr: 1
30765247.056: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30766247.056: DIMM 0 RttWr: 1
30767247.056: AgesaHwWlPhase1: training nibble 0
30768247.056: DIMM 1 RttNom: 4
30769247.056: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30770247.056: DIMM 1 RttWr: 1
30771247.056: DIMM 1 RttWr: 1
30772247.056: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30773247.056: DIMM 1 RttWr: 1
30774247.056: DIMM 1 RttNom: 4
30775247.056: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30776247.056: DIMM 1 RttNom: 4
30777247.056: DIMM 1 RttWr: 1
30778247.056: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30779247.056: DIMM 1 RttWr: 1
30780247.056: DIMM 0 RttNom: 4
30781247.056: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30782247.056: DIMM 1 RttNom: 4
30783247.056: DIMM 0 RttWr: 1
30784247.056: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30785247.056: DIMM 1 RttWr: 1
30786247.056: DIMM 0 RttNom: 4
30787247.056: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30788247.056: DIMM 1 RttNom: 4
30789247.056: DIMM 0 RttWr: 1
30790247.056: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30791247.056: DIMM 1 RttWr: 1
30792247.056: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
30793247.056: <09>Lane 00 scaled delay: 006a
30794247.056: <09>Lane 00 new seed: 006a
30795247.056: <09>Lane 01 scaled delay: 0061
30796247.056: <09>Lane 01 new seed: 0061
30797247.056: <09>Lane 02 scaled delay: 005f
30798247.056: <09>Lane 02 new seed: 005f
30799247.056: <09>Lane 03 scaled delay: 0058
30800247.056: <09>Lane 03 new seed: 0058
30801247.056: <09>Lane 04 scaled delay: 0045
30802247.056: <09>Lane 04 new seed: 0045
30803247.056: <09>Lane 05 scaled delay: 004e
30804247.056: <09>Lane 05 new seed: 004e
30805247.056: <09>Lane 06 scaled delay: 0052
30806247.056: <09>Lane 06 new seed: 0052
30807247.056: <09>Lane 07 scaled delay: 0057
30808247.056: <09>Lane 07 new seed: 0057
30809247.056: <09>Lane 08 scaled delay: 0048
30810247.056: <09>Lane 08 new seed: 0048
30811247.056: <09>Lane 00 nibble 0 raw readback: 0030
30812247.056: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
30813247.056: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
30814247.056: <09>Lane 01 nibble 0 raw readback: 0025
30815247.056: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
30816247.056: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
30817247.056: <09>Lane 02 nibble 0 raw readback: 0060
30818247.056: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
30819247.056: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
30820247.056: <09>Lane 03 nibble 0 raw readback: 005b
30821247.056: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
30822247.056: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
30823247.056: <09>Lane 04 nibble 0 raw readback: 0047
30824247.056: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0047
30825247.056: <09>Lane 04 nibble 0 adjusted value (post nibble): 0047
30826247.056: <09>Lane 05 nibble 0 raw readback: 0050
30827247.057: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0050
30828247.056: <09>Lane 05 nibble 0 adjusted value (post nibble): 0050
30829247.057: <09>Lane 06 nibble 0 raw readback: 0054
30830247.057: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0054
30831247.057: <09>Lane 06 nibble 0 adjusted value (post nibble): 0054
30832247.057: <09>Lane 07 nibble 0 raw readback: 005a
30833247.057: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
30834247.057: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
30835247.057: <09>Lane 08 nibble 0 raw readback: 004a
30836247.057: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
30837247.057: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
30838247.057: AgesaHwWlPhase1: training nibble 1
30839247.057: DIMM 1 RttNom: 4
30840247.057: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30841247.057: DIMM 1 RttWr: 1
30842247.057: DIMM 1 RttWr: 1
30843247.057: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30844247.057: DIMM 1 RttWr: 1
30845247.057: DIMM 1 RttNom: 4
30846247.057: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30847247.057: DIMM 1 RttNom: 4
30848247.057: DIMM 1 RttWr: 1
30849247.057: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30850247.057: DIMM 1 RttWr: 1
30851247.057: DIMM 0 RttNom: 4
30852247.057: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30853247.057: DIMM 1 RttNom: 4
30854247.057: DIMM 0 RttWr: 1
30855247.057: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30856247.057: DIMM 1 RttWr: 1
30857247.057: DIMM 0 RttNom: 4
30858247.057: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30859247.057: DIMM 1 RttNom: 4
30860247.057: DIMM 0 RttWr: 1
30861247.057: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30862247.057: DIMM 1 RttWr: 1
30863247.057: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
30864247.057: <09>Lane 00 new seed: 006a
30865247.057: <09>Lane 01 new seed: 0061
30866247.057: <09>Lane 02 new seed: 005f
30867247.057: <09>Lane 03 new seed: 0058
30868247.057: <09>Lane 04 new seed: 0045
30869247.057: <09>Lane 05 new seed: 004e
30870247.057: <09>Lane 06 new seed: 0052
30871247.057: <09>Lane 07 new seed: 0057
30872247.057: <09>Lane 08 new seed: 0048
30873247.057: <09>Lane 00 nibble 1 raw readback: 0031
30874247.057: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0071
30875247.057: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
30876247.057: <09>Lane 01 nibble 1 raw readback: 0027
30877247.057: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
30878247.057: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
30879247.057: <09>Lane 02 nibble 1 raw readback: 0062
30880247.057: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
30881247.057: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
30882247.057: <09>Lane 03 nibble 1 raw readback: 005c
30883247.057: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
30884247.057: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
30885247.057: <09>Lane 04 nibble 1 raw readback: 0047
30886247.057: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0047
30887247.057: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
30888247.057: <09>Lane 05 nibble 1 raw readback: 0050
30889247.057: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
30890247.057: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
30891247.057: <09>Lane 06 nibble 1 raw readback: 0055
30892247.057: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
30893247.057: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
30894247.057: <09>Lane 07 nibble 1 raw readback: 005c
30895247.057: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
30896247.057: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
30897247.057: <09>Lane 08 nibble 1 raw readback: 004a
30898247.057: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
30899247.057: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
30900247.057: <09>original critical gross delay: 0
30901247.057: <09>new critical gross delay: 0
30902247.058: DIMM 1 RttNom: 4
30903247.058: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
30904247.058: DIMM 1 RttNom: 4
30905247.058: DIMM 1 RttWr: 1
30906247.058: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
30907247.058: DIMM 1 RttWr: 1
30908247.058: DIMM 1 RttNom: 4
30909247.058: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
30910247.058: DIMM 1 RttNom: 4
30911247.058: DIMM 1 RttWr: 1
30912247.058: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
30913247.058: DIMM 1 RttWr: 1
30914247.058: DIMM 0 RttNom: 4
30915247.058: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
30916247.058: DIMM 1 RttNom: 4
30917247.058: DIMM 0 RttWr: 1
30918247.058: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
30919247.058: DIMM 1 RttWr: 1
30920247.058: DIMM 0 RttNom: 4
30921247.058: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
30922247.058: DIMM 1 RttNom: 4
30923247.058: DIMM 0 RttWr: 1
30924247.058: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
30925247.058: DIMM 1 RttWr: 1
30926247.058: SPD2ndTiming: Start
30927247.058: SPD2ndTiming: Done
30928247.058: mct_BeforeDramInit_Prod_D: Start
30929247.058: mct_ProgramODT_D: Start
30930247.058: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
30931247.058: mct_ProgramODT_D: Done
30932247.058: mct_BeforeDramInit_Prod_D: Done
30933247.059: mct_DramInit_Sw_D: Start
30934247.059: DIMM 0 RttWr: 1
30935247.059: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
30936247.059: mct_SendMrsCmd: Start
30937247.059: mct_SendMrsCmd: Done
30938247.059: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
30939247.059: mct_SendMrsCmd: Start
30940247.059: mct_SendMrsCmd: Done
30941247.059: DIMM 0 RttNom: 4
30942247.059: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
30943247.059: mct_SendMrsCmd: Start
30944247.059: mct_SendMrsCmd: Done
30945247.059: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
30946247.059: mct_SendMrsCmd: Start
30947247.059: mct_SendMrsCmd: Done
30948247.059: DIMM 0 RttWr: 1
30949247.059: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
30950247.059: mct_SendMrsCmd: Start
30951247.059: mct_SendMrsCmd: Done
30952247.059: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
30953247.059: mct_SendMrsCmd: Start
30954247.059: mct_SendMrsCmd: Done
30955247.059: DIMM 0 RttNom: 4
30956247.059: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
30957247.059: mct_SendMrsCmd: Start
30958247.059: mct_SendMrsCmd: Done
30959247.059: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
30960247.059: mct_SendMrsCmd: Start
30961247.059: mct_SendMrsCmd: Done
30962247.059: DIMM 1 RttWr: 1
30963247.059: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
30964247.059: mct_SendMrsCmd: Start
30965247.059: mct_SendMrsCmd: Done
30966247.059: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
30967247.059: mct_SendMrsCmd: Start
30968247.059: mct_SendMrsCmd: Done
30969247.059: DIMM 1 RttNom: 4
30970247.059: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
30971247.059: mct_SendMrsCmd: Start
30972247.059: mct_SendMrsCmd: Done
30973247.059: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
30974247.059: mct_SendMrsCmd: Start
30975247.059: mct_SendMrsCmd: Done
30976247.059: DIMM 1 RttWr: 1
30977247.059: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
30978247.059: mct_SendMrsCmd: Start
30979247.059: mct_SendMrsCmd: Done
30980247.059: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
30981247.059: mct_SendMrsCmd: Start
30982247.059: mct_SendMrsCmd: Done
30983247.059: DIMM 1 RttNom: 4
30984247.059: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
30985247.059: mct_SendMrsCmd: Start
30986247.059: mct_SendMrsCmd: Done
30987247.059: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
30988247.059: mct_SendMrsCmd: Start
30989247.059: mct_SendMrsCmd: Done
30990247.059: mct_DramInit_Sw_D: Done
30991247.059: AgesaHwWlPhase1: training nibble 0
30992247.059: DIMM 0 RttNom: 4
30993247.059: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
30994247.059: DIMM 0 RttWr: 1
30995247.059: DIMM 0 RttWr: 1
30996247.059: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
30997247.059: DIMM 0 RttWr: 1
30998247.059: DIMM 0 RttNom: 4
30999247.059: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
31000247.060: DIMM 0 RttNom: 4
31001247.059: DIMM 0 RttWr: 1
31002247.059: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
31003247.060: DIMM 0 RttWr: 1
31004247.060: DIMM 1 RttNom: 4
31005247.060: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
31006247.060: DIMM 0 RttNom: 4
31007247.060: DIMM 1 RttWr: 1
31008247.060: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
31009247.060: DIMM 0 RttWr: 1
31010247.060: DIMM 1 RttNom: 4
31011247.060: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
31012247.060: DIMM 0 RttNom: 4
31013247.060: DIMM 1 RttWr: 1
31014247.060: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
31015247.060: DIMM 0 RttWr: 1
31016247.060: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
31017247.060: <09>Lane 00 scaled delay: 0078
31018247.060: <09>Lane 00 new seed: 0078
31019247.060: <09>Lane 01 scaled delay: 0070
31020247.060: <09>Lane 01 new seed: 0070
31021247.060: <09>Lane 02 scaled delay: 006c
31022247.060: <09>Lane 02 new seed: 006c
31023247.060: <09>Lane 03 scaled delay: 0066
31024247.060: <09>Lane 03 new seed: 0066
31025247.060: <09>Lane 04 scaled delay: 0053
31026247.060: <09>Lane 04 new seed: 0053
31027247.060: <09>Lane 05 scaled delay: 0058
31028247.060: <09>Lane 05 new seed: 0058
31029247.060: <09>Lane 06 scaled delay: 0060
31030247.060: <09>Lane 06 new seed: 0060
31031247.060: <09>Lane 07 scaled delay: 0064
31032247.060: <09>Lane 07 new seed: 0064
31033247.060: <09>Lane 08 scaled delay: 0057
31034247.060: <09>Lane 08 new seed: 0057
31035247.060: <09>Lane 00 nibble 0 raw readback: 003d
31036247.060: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007d
31037247.060: <09>Lane 00 nibble 0 adjusted value (post nibble): 007d
31038247.060: <09>Lane 01 nibble 0 raw readback: 0037
31039247.060: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0077
31040247.060: <09>Lane 01 nibble 0 adjusted value (post nibble): 0077
31041247.060: <09>Lane 02 nibble 0 raw readback: 002e
31042247.060: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006e
31043247.060: <09>Lane 02 nibble 0 adjusted value (post nibble): 006e
31044247.060: <09>Lane 03 nibble 0 raw readback: 0029
31045247.060: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0069
31046247.060: <09>Lane 03 nibble 0 adjusted value (post nibble): 0069
31047247.060: <09>Lane 04 nibble 0 raw readback: 0057
31048247.060: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
31049247.060: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
31050247.060: <09>Lane 05 nibble 0 raw readback: 005d
31051247.060: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
31052247.060: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
31053247.060: <09>Lane 06 nibble 0 raw readback: 0020
31054247.060: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0060
31055247.060: <09>Lane 06 nibble 0 adjusted value (post nibble): 0060
31056247.060: <09>Lane 07 nibble 0 raw readback: 0025
31057247.060: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0065
31058247.060: <09>Lane 07 nibble 0 adjusted value (post nibble): 0065
31059247.060: <09>Lane 08 nibble 0 raw readback: 0059
31060247.060: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0059
31061247.060: <09>Lane 08 nibble 0 adjusted value (post nibble): 0059
31062247.060: AgesaHwWlPhase1: training nibble 1
31063247.060: DIMM 0 RttNom: 4
31064247.060: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
31065247.061: DIMM 0 RttWr: 1
31066247.061: DIMM 0 RttWr: 1
31067247.061: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
31068247.061: DIMM 0 RttWr: 1
31069247.061: DIMM 0 RttNom: 4
31070247.061: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
31071247.061: DIMM 0 RttNom: 4
31072247.061: DIMM 0 RttWr: 1
31073247.061: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
31074247.061: DIMM 0 RttWr: 1
31075247.061: DIMM 1 RttNom: 4
31076247.061: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
31077247.061: DIMM 0 RttNom: 4
31078247.061: DIMM 1 RttWr: 1
31079247.061: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
31080247.061: DIMM 0 RttWr: 1
31081247.061: DIMM 1 RttNom: 4
31082247.061: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
31083247.061: DIMM 0 RttNom: 4
31084247.061: DIMM 1 RttWr: 1
31085247.061: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
31086247.061: DIMM 0 RttWr: 1
31087247.061: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
31088247.061: <09>Lane 00 new seed: 0078
31089247.061: <09>Lane 01 new seed: 0070
31090247.061: <09>Lane 02 new seed: 006c
31091247.061: <09>Lane 03 new seed: 0066
31092247.061: <09>Lane 04 new seed: 0053
31093247.061: <09>Lane 05 new seed: 0058
31094247.061: <09>Lane 06 new seed: 0060
31095247.061: <09>Lane 07 new seed: 0064
31096247.061: <09>Lane 08 new seed: 0057
31097247.061: <09>Lane 00 nibble 1 raw readback: 003c
31098247.061: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007c
31099247.061: <09>Lane 00 nibble 1 adjusted value (post nibble): 007a
31100247.061: <09>Lane 01 nibble 1 raw readback: 0035
31101247.061: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0075
31102247.061: <09>Lane 01 nibble 1 adjusted value (post nibble): 0072
31103247.061: <09>Lane 02 nibble 1 raw readback: 002f
31104247.061: <09>Lane 02 nibble 1 adjusted value (pre nibble): 006f
31105247.061: <09>Lane 02 nibble 1 adjusted value (post nibble): 006d
31106247.061: <09>Lane 03 nibble 1 raw readback: 0029
31107247.061: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0069
31108247.061: <09>Lane 03 nibble 1 adjusted value (post nibble): 0067
31109247.061: <09>Lane 04 nibble 1 raw readback: 0054
31110247.061: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
31111247.061: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
31112247.061: <09>Lane 05 nibble 1 raw readback: 005b
31113247.061: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005b
31114247.061: <09>Lane 05 nibble 1 adjusted value (post nibble): 0059
31115247.061: <09>Lane 06 nibble 1 raw readback: 0022
31116247.061: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0062
31117247.061: <09>Lane 06 nibble 1 adjusted value (post nibble): 0061
31118247.061: <09>Lane 07 nibble 1 raw readback: 0026
31119247.061: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
31120247.061: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
31121247.061: <09>Lane 08 nibble 1 raw readback: 0059
31122247.061: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
31123247.061: <09>Lane 08 nibble 1 adjusted value (post nibble): 0058
31124247.061: <09>original critical gross delay: 0
31125247.061: <09>new critical gross delay: 0
31126247.061: DIMM 0 RttNom: 4
31127247.061: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
31128247.061: DIMM 0 RttNom: 4
31129247.061: DIMM 0 RttWr: 1
31130247.061: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
31131247.062: DIMM 0 RttWr: 1
31132247.062: DIMM 0 RttNom: 4
31133247.062: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
31134247.062: DIMM 0 RttNom: 4
31135247.062: DIMM 0 RttWr: 1
31136247.062: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
31137247.062: DIMM 0 RttWr: 1
31138247.062: DIMM 1 RttNom: 4
31139247.062: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
31140247.062: DIMM 0 RttNom: 4
31141247.062: DIMM 1 RttWr: 1
31142247.062: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
31143247.062: DIMM 0 RttWr: 1
31144247.062: DIMM 1 RttNom: 4
31145247.062: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
31146247.062: DIMM 0 RttNom: 4
31147247.062: DIMM 1 RttWr: 1
31148247.062: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
31149247.062: DIMM 0 RttWr: 1
31150247.062: AgesaHwWlPhase1: training nibble 0
31151247.062: DIMM 1 RttNom: 4
31152247.062: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
31153247.062: DIMM 1 RttWr: 1
31154247.062: DIMM 1 RttWr: 1
31155247.062: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
31156247.062: DIMM 1 RttWr: 1
31157247.062: DIMM 1 RttNom: 4
31158247.062: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
31159247.062: DIMM 1 RttNom: 4
31160247.062: DIMM 1 RttWr: 1
31161247.062: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
31162247.062: DIMM 1 RttWr: 1
31163247.062: DIMM 0 RttNom: 4
31164247.062: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
31165247.062: DIMM 1 RttNom: 4
31166247.062: DIMM 0 RttWr: 1
31167247.062: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
31168247.062: DIMM 1 RttWr: 1
31169247.062: DIMM 0 RttNom: 4
31170247.062: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
31171247.062: DIMM 1 RttNom: 4
31172247.062: DIMM 0 RttWr: 1
31173247.062: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
31174247.062: DIMM 1 RttWr: 1
31175247.062: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
31176247.062: <09>Lane 00 scaled delay: 006a
31177247.062: <09>Lane 00 new seed: 006a
31178247.062: <09>Lane 01 scaled delay: 0064
31179247.062: <09>Lane 01 new seed: 0064
31180247.062: <09>Lane 02 scaled delay: 005d
31181247.062: <09>Lane 02 new seed: 005d
31182247.062: <09>Lane 03 scaled delay: 005b
31183247.062: <09>Lane 03 new seed: 005b
31184247.062: <09>Lane 04 scaled delay: 0047
31185247.062: <09>Lane 04 new seed: 0047
31186247.062: <09>Lane 05 scaled delay: 004e
31187247.062: <09>Lane 05 new seed: 004e
31188247.062: <09>Lane 06 scaled delay: 0052
31189247.062: <09>Lane 06 new seed: 0052
31190247.062: <09>Lane 07 scaled delay: 0055
31191247.062: <09>Lane 07 new seed: 0055
31192247.062: <09>Lane 08 scaled delay: 004c
31193247.062: <09>Lane 08 new seed: 004c
31194247.062: <09>Lane 00 nibble 0 raw readback: 002f
31195247.062: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
31196247.062: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
31197247.062: <09>Lane 01 nibble 0 raw readback: 002a
31198247.062: <09>Lane 01 nibble 0 adjusted value (pre nibble): 006a
31199247.062: <09>Lane 01 nibble 0 adjusted value (post nibble): 006a
31200247.062: <09>Lane 02 nibble 0 raw readback: 0060
31201247.062: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
31202247.062: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
31203247.062: <09>Lane 03 nibble 0 raw readback: 005b
31204247.063: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
31205247.063: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
31206247.063: <09>Lane 04 nibble 0 raw readback: 0049
31207247.063: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
31208247.063: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
31209247.063: <09>Lane 05 nibble 0 raw readback: 004d
31210247.063: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004d
31211247.063: <09>Lane 05 nibble 0 adjusted value (post nibble): 004d
31212247.063: <09>Lane 06 nibble 0 raw readback: 0054
31213247.063: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0054
31214247.063: <09>Lane 06 nibble 0 adjusted value (post nibble): 0054
31215247.063: <09>Lane 07 nibble 0 raw readback: 0059
31216247.063: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
31217247.063: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
31218247.063: <09>Lane 08 nibble 0 raw readback: 004b
31219247.063: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
31220247.063: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
31221247.063: AgesaHwWlPhase1: training nibble 1
31222247.063: DIMM 1 RttNom: 4
31223247.063: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
31224247.063: DIMM 1 RttWr: 1
31225247.063: DIMM 1 RttWr: 1
31226247.063: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
31227247.063: DIMM 1 RttWr: 1
31228247.063: DIMM 1 RttNom: 4
31229247.063: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
31230247.063: DIMM 1 RttNom: 4
31231247.063: DIMM 1 RttWr: 1
31232247.063: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
31233247.063: DIMM 1 RttWr: 1
31234247.063: DIMM 0 RttNom: 4
31235247.063: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
31236247.063: DIMM 1 RttNom: 4
31237247.063: DIMM 0 RttWr: 1
31238247.063: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
31239247.063: DIMM 1 RttWr: 1
31240247.063: DIMM 0 RttNom: 4
31241247.063: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
31242247.063: DIMM 1 RttNom: 4
31243247.063: DIMM 0 RttWr: 1
31244247.063: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
31245247.063: DIMM 1 RttWr: 1
31246247.063: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
31247247.063: <09>Lane 00 new seed: 006a
31248247.063: <09>Lane 01 new seed: 0064
31249247.063: <09>Lane 02 new seed: 005d
31250247.063: <09>Lane 03 new seed: 005b
31251247.063: <09>Lane 04 new seed: 0047
31252247.063: <09>Lane 05 new seed: 004e
31253247.063: <09>Lane 06 new seed: 0052
31254247.063: <09>Lane 07 new seed: 0055
31255247.063: <09>Lane 08 new seed: 004c
31256247.063: <09>Lane 00 nibble 1 raw readback: 002e
31257247.063: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
31258247.063: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
31259247.063: <09>Lane 01 nibble 1 raw readback: 0027
31260247.063: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
31261247.063: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
31262247.063: <09>Lane 02 nibble 1 raw readback: 005f
31263247.063: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005f
31264247.063: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
31265247.063: <09>Lane 03 nibble 1 raw readback: 005d
31266247.063: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
31267247.063: <09>Lane 03 nibble 1 adjusted value (post nibble): 005c
31268247.063: <09>Lane 04 nibble 1 raw readback: 0046
31269247.063: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
31270247.063: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
31271247.063: <09>Lane 05 nibble 1 raw readback: 004f
31272247.063: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
31273247.063: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
31274247.063: <09>Lane 06 nibble 1 raw readback: 0053
31275247.063: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0053
31276247.063: <09>Lane 06 nibble 1 adjusted value (post nibble): 0052
31277247.063: <09>Lane 07 nibble 1 raw readback: 0057
31278247.063: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
31279247.063: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
31280247.063: <09>Lane 08 nibble 1 raw readback: 004c
31281247.063: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004c
31282247.063: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
31283247.063: <09>original critical gross delay: 0
31284247.064: <09>new critical gross delay: 0
31285247.064: DIMM 1 RttNom: 4
31286247.064: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
31287247.064: DIMM 1 RttNom: 4
31288247.064: DIMM 1 RttWr: 1
31289247.064: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
31290247.064: DIMM 1 RttWr: 1
31291247.064: DIMM 1 RttNom: 4
31292247.064: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
31293247.064: DIMM 1 RttNom: 4
31294247.064: DIMM 1 RttWr: 1
31295247.064: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
31296247.064: DIMM 1 RttWr: 1
31297247.064: DIMM 0 RttNom: 4
31298247.064: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
31299247.064: DIMM 1 RttNom: 4
31300247.064: DIMM 0 RttWr: 1
31301247.064: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
31302247.064: DIMM 1 RttWr: 1
31303247.064: DIMM 0 RttNom: 4
31304247.064: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
31305247.064: DIMM 1 RttNom: 4
31306247.064: DIMM 0 RttWr: 1
31307247.064: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
31308247.064: DIMM 1 RttWr: 1
31309247.064: activate_spd_rom() for node 01
31310247.064: enable_spd_node1()
31311247.064: SetTargetFreq: Start
31312247.065: SetTargetFreq: Node 1: New frequency code: 0006
31313247.065: ChangeMemClk: Start
31314247.065: set_2t_configuration: Start
31315247.065: set_2t_configuration: Done
31316247.065: mct_BeforePlatformSpec: Start
31317247.065: mct_BeforePlatformSpec: Done
31318247.065: mct_PlatformSpec: Start
31319247.065: Programmed DCT 0 timing/termination pattern 00000000 20222222
31320247.065: mct_PlatformSpec: Done
31321247.065: set_2t_configuration: Start
31322247.065: set_2t_configuration: Done
31323247.065: mct_BeforePlatformSpec: Start
31324247.065: mct_BeforePlatformSpec: Done
31325247.065: mct_PlatformSpec: Start
31326247.065: Programmed DCT 1 timing/termination pattern 00000000 20222222
31327247.065: mct_PlatformSpec: Done
31328247.065: ChangeMemClk: Done
31329247.065: phyAssistedMemFnceTraining: Start
31330247.065: phyAssistedMemFnceTraining: training node 1 DCT 0
31331247.065: phyAssistedMemFnceTraining: done training node 1 DCT 0
31332247.065: phyAssistedMemFnceTraining: training node 1 DCT 1
31333247.065: phyAssistedMemFnceTraining: done training node 1 DCT 1
31334247.065: phyAssistedMemFnceTraining: Done
31335247.065: InitPhyCompensation: DCT 0: Start
31336247.065: Waiting for predriver calibration to be applied...done!
31337247.065: InitPhyCompensation: DCT 0: Done
31338247.066: phyAssistedMemFnceTraining: Start
31339247.066: phyAssistedMemFnceTraining: training node 1 DCT 0
31340247.066: phyAssistedMemFnceTraining: done training node 1 DCT 0
31341247.066: phyAssistedMemFnceTraining: training node 1 DCT 1
31342247.066: phyAssistedMemFnceTraining: done training node 1 DCT 1
31343247.066: phyAssistedMemFnceTraining: Done
31344247.066: InitPhyCompensation: DCT 1: Start
31345247.066: Waiting for predriver calibration to be applied...done!
31346247.066: InitPhyCompensation: DCT 1: Done
31347247.066: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
31348247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
31349247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
31350247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
31351247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
31352247.066: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
31353247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
31354247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
31355247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
31356247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
31357247.066: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
31358247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
31359247.066: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
31360247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
31361247.066: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
31362247.066: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
31363247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
31364247.066: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
31365247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
31366247.067: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
31367247.067: SetTargetFreq: Done
31368247.067: SPD2ndTiming: Start
31369247.067: SPD2ndTiming: Done
31370247.067: mct_BeforeDramInit_Prod_D: Start
31371247.067: mct_ProgramODT_D: Start
31372247.067: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
31373247.067: mct_ProgramODT_D: Done
31374247.067: mct_BeforeDramInit_Prod_D: Done
31375247.067: mct_DramInit_Sw_D: Start
31376247.067: DIMM 0 RttWr: 2
31377247.067: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31378247.067: mct_SendMrsCmd: Start
31379247.067: mct_SendMrsCmd: Done
31380247.067: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
31381247.067: mct_SendMrsCmd: Start
31382247.067: mct_SendMrsCmd: Done
31383247.067: DIMM 0 RttNom: 3
31384247.067: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31385247.067: mct_SendMrsCmd: Start
31386247.067: mct_SendMrsCmd: Done
31387247.067: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
31388247.067: mct_SendMrsCmd: Start
31389247.067: mct_SendMrsCmd: Done
31390247.067: DIMM 0 RttWr: 2
31391247.067: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31392247.067: mct_SendMrsCmd: Start
31393247.067: mct_SendMrsCmd: Done
31394247.067: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
31395247.067: mct_SendMrsCmd: Start
31396247.067: mct_SendMrsCmd: Done
31397247.067: DIMM 0 RttNom: 3
31398247.067: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31399247.067: mct_SendMrsCmd: Start
31400247.067: mct_SendMrsCmd: Done
31401247.068: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
31402247.068: mct_SendMrsCmd: Start
31403247.068: mct_SendMrsCmd: Done
31404247.068: DIMM 1 RttWr: 2
31405247.068: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31406247.068: mct_SendMrsCmd: Start
31407247.068: mct_SendMrsCmd: Done
31408247.068: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
31409247.068: mct_SendMrsCmd: Start
31410247.068: mct_SendMrsCmd: Done
31411247.068: DIMM 1 RttNom: 3
31412247.068: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31413247.068: mct_SendMrsCmd: Start
31414247.068: mct_SendMrsCmd: Done
31415247.068: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
31416247.068: mct_SendMrsCmd: Start
31417247.068: mct_SendMrsCmd: Done
31418247.068: DIMM 1 RttWr: 2
31419247.068: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31420247.068: mct_SendMrsCmd: Start
31421247.068: mct_SendMrsCmd: Done
31422247.068: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
31423247.068: mct_SendMrsCmd: Start
31424247.068: mct_SendMrsCmd: Done
31425247.068: DIMM 1 RttNom: 3
31426247.068: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31427247.068: mct_SendMrsCmd: Start
31428247.068: mct_SendMrsCmd: Done
31429247.068: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
31430247.068: mct_SendMrsCmd: Start
31431247.068: mct_SendMrsCmd: Done
31432247.068: mct_DramInit_Sw_D: Done
31433247.068: AgesaHwWlPhase1: training nibble 0
31434247.068: DIMM 0 RttNom: 3
31435247.068: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31436247.068: DIMM 0 RttWr: 2
31437247.068: DIMM 0 RttWr: 2
31438247.068: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31439247.068: DIMM 0 RttWr: 2
31440247.068: DIMM 0 RttNom: 3
31441247.068: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31442247.068: DIMM 0 RttNom: 3
31443247.068: DIMM 0 RttWr: 2
31444247.068: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31445247.068: DIMM 0 RttWr: 2
31446247.068: DIMM 1 RttNom: 3
31447247.068: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31448247.068: DIMM 0 RttNom: 3
31449247.068: DIMM 1 RttWr: 2
31450247.068: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31451247.068: DIMM 0 RttWr: 2
31452247.068: DIMM 1 RttNom: 3
31453247.068: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31454247.068: DIMM 0 RttNom: 3
31455247.068: DIMM 1 RttWr: 2
31456247.068: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31457247.069: DIMM 0 RttWr: 2
31458247.069: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
31459247.069: <09>Lane 00 scaled delay: 0047
31460247.069: <09>Lane 00 new seed: 0047
31461247.069: <09>Lane 01 scaled delay: 0047
31462247.069: <09>Lane 01 new seed: 0047
31463247.069: <09>Lane 02 scaled delay: 0047
31464247.069: <09>Lane 02 new seed: 0047
31465247.069: <09>Lane 03 scaled delay: 0047
31466247.069: <09>Lane 03 new seed: 0047
31467247.069: <09>Lane 04 scaled delay: 0047
31468247.069: <09>Lane 04 new seed: 0047
31469247.069: <09>Lane 05 scaled delay: 0047
31470247.069: <09>Lane 05 new seed: 0047
31471247.069: <09>Lane 06 scaled delay: 0047
31472247.069: <09>Lane 06 new seed: 0047
31473247.069: <09>Lane 07 scaled delay: 0047
31474247.069: <09>Lane 07 new seed: 0047
31475247.069: <09>Lane 08 scaled delay: 0047
31476247.069: <09>Lane 08 new seed: 0047
31477247.069: <09>Lane 00 nibble 0 raw readback: 0040
31478247.069: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0040
31479247.069: <09>Lane 00 nibble 0 adjusted value (post nibble): 0040
31480247.069: <09>Lane 01 nibble 0 raw readback: 003c
31481247.069: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
31482247.069: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
31483247.069: <09>Lane 02 nibble 0 raw readback: 0038
31484247.069: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
31485247.069: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
31486247.069: <09>Lane 03 nibble 0 raw readback: 0036
31487247.069: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
31488247.069: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
31489247.069: <09>Lane 04 nibble 0 raw readback: 0033
31490247.069: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0033
31491247.069: <09>Lane 04 nibble 0 adjusted value (post nibble): 0033
31492247.069: <09>Lane 05 nibble 0 raw readback: 0037
31493247.069: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0037
31494247.069: <09>Lane 05 nibble 0 adjusted value (post nibble): 0037
31495247.069: <09>Lane 06 nibble 0 raw readback: 0039
31496247.069: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0039
31497247.069: <09>Lane 06 nibble 0 adjusted value (post nibble): 0039
31498247.069: <09>Lane 07 nibble 0 raw readback: 003d
31499247.069: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003d
31500247.069: <09>Lane 07 nibble 0 adjusted value (post nibble): 003d
31501247.069: <09>Lane 08 nibble 0 raw readback: 0031
31502247.069: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0031
31503247.069: <09>Lane 08 nibble 0 adjusted value (post nibble): 0031
31504247.069: AgesaHwWlPhase1: training nibble 1
31505247.070: DIMM 0 RttNom: 3
31506247.070: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31507247.070: DIMM 0 RttWr: 2
31508247.070: DIMM 0 RttWr: 2
31509247.070: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31510247.070: DIMM 0 RttWr: 2
31511247.070: DIMM 0 RttNom: 3
31512247.070: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31513247.070: DIMM 0 RttNom: 3
31514247.070: DIMM 0 RttWr: 2
31515247.070: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31516247.070: DIMM 0 RttWr: 2
31517247.070: DIMM 1 RttNom: 3
31518247.070: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31519247.070: DIMM 0 RttNom: 3
31520247.070: DIMM 1 RttWr: 2
31521247.070: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31522247.070: DIMM 0 RttWr: 2
31523247.070: DIMM 1 RttNom: 3
31524247.070: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31525247.070: DIMM 0 RttNom: 3
31526247.070: DIMM 1 RttWr: 2
31527247.070: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31528247.070: DIMM 0 RttWr: 2
31529247.070: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
31530247.070: <09>Lane 00 new seed: 0047
31531247.070: <09>Lane 01 new seed: 0047
31532247.070: <09>Lane 02 new seed: 0047
31533247.070: <09>Lane 03 new seed: 0047
31534247.070: <09>Lane 04 new seed: 0047
31535247.070: <09>Lane 05 new seed: 0047
31536247.070: <09>Lane 06 new seed: 0047
31537247.070: <09>Lane 07 new seed: 0047
31538247.070: <09>Lane 08 new seed: 0047
31539247.070: <09>Lane 00 nibble 1 raw readback: 003f
31540247.070: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
31541247.070: <09>Lane 00 nibble 1 adjusted value (post nibble): 0043
31542247.070: <09>Lane 01 nibble 1 raw readback: 003c
31543247.070: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
31544247.070: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
31545247.070: <09>Lane 02 nibble 1 raw readback: 0039
31546247.070: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
31547247.070: <09>Lane 02 nibble 1 adjusted value (post nibble): 0040
31548247.070: <09>Lane 03 nibble 1 raw readback: 0037
31549247.070: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
31550247.070: <09>Lane 03 nibble 1 adjusted value (post nibble): 003f
31551247.070: <09>Lane 04 nibble 1 raw readback: 0032
31552247.070: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0032
31553247.070: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
31554247.070: <09>Lane 05 nibble 1 raw readback: 0037
31555247.070: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0037
31556247.070: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
31557247.070: <09>Lane 06 nibble 1 raw readback: 003a
31558247.070: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003a
31559247.070: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
31560247.070: <09>Lane 07 nibble 1 raw readback: 003d
31561247.070: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003d
31562247.070: <09>Lane 07 nibble 1 adjusted value (post nibble): 0042
31563247.070: <09>Lane 08 nibble 1 raw readback: 0031
31564247.070: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
31565247.070: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
31566247.070: <09>original critical gross delay: 0
31567247.070: <09>new critical gross delay: 0
31568247.071: DIMM 0 RttNom: 3
31569247.071: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31570247.071: DIMM 0 RttNom: 3
31571247.071: DIMM 0 RttWr: 2
31572247.071: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31573247.071: DIMM 0 RttWr: 2
31574247.071: DIMM 0 RttNom: 3
31575247.071: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31576247.071: DIMM 0 RttNom: 3
31577247.071: DIMM 0 RttWr: 2
31578247.071: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31579247.071: DIMM 0 RttWr: 2
31580247.071: DIMM 1 RttNom: 3
31581247.071: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31582247.071: DIMM 0 RttNom: 3
31583247.071: DIMM 1 RttWr: 2
31584247.071: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31585247.071: DIMM 0 RttWr: 2
31586247.071: DIMM 1 RttNom: 3
31587247.071: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31588247.071: DIMM 0 RttNom: 3
31589247.071: DIMM 1 RttWr: 2
31590247.071: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31591247.071: DIMM 0 RttWr: 2
31592247.071: AgesaHwWlPhase1: training nibble 0
31593247.071: DIMM 1 RttNom: 3
31594247.071: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31595247.071: DIMM 1 RttWr: 2
31596247.071: DIMM 1 RttWr: 2
31597247.071: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31598247.071: DIMM 1 RttWr: 2
31599247.071: DIMM 1 RttNom: 3
31600247.071: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31601247.071: DIMM 1 RttNom: 3
31602247.071: DIMM 1 RttWr: 2
31603247.071: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31604247.071: DIMM 1 RttWr: 2
31605247.071: DIMM 0 RttNom: 3
31606247.071: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31607247.071: DIMM 1 RttNom: 3
31608247.071: DIMM 0 RttWr: 2
31609247.071: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31610247.071: DIMM 1 RttWr: 2
31611247.071: DIMM 0 RttNom: 3
31612247.071: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31613247.071: DIMM 1 RttNom: 3
31614247.071: DIMM 0 RttWr: 2
31615247.071: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31616247.071: DIMM 1 RttWr: 2
31617247.071: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
31618247.071: <09>Lane 00 scaled delay: 0047
31619247.071: <09>Lane 00 new seed: 0047
31620247.071: <09>Lane 01 scaled delay: 0047
31621247.071: <09>Lane 01 new seed: 0047
31622247.071: <09>Lane 02 scaled delay: 0047
31623247.071: <09>Lane 02 new seed: 0047
31624247.071: <09>Lane 03 scaled delay: 0047
31625247.071: <09>Lane 03 new seed: 0047
31626247.071: <09>Lane 04 scaled delay: 0047
31627247.071: <09>Lane 04 new seed: 0047
31628247.071: <09>Lane 05 scaled delay: 0047
31629247.071: <09>Lane 05 new seed: 0047
31630247.071: <09>Lane 06 scaled delay: 0047
31631247.072: <09>Lane 06 new seed: 0047
31632247.072: <09>Lane 07 scaled delay: 0047
31633247.072: <09>Lane 07 new seed: 0047
31634247.072: <09>Lane 08 scaled delay: 0047
31635247.072: <09>Lane 08 new seed: 0047
31636247.072: <09>Lane 00 nibble 0 raw readback: 0045
31637247.072: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
31638247.072: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
31639247.072: <09>Lane 01 nibble 0 raw readback: 0040
31640247.072: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
31641247.072: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
31642247.072: <09>Lane 02 nibble 0 raw readback: 003c
31643247.072: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
31644247.072: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
31645247.072: <09>Lane 03 nibble 0 raw readback: 003b
31646247.072: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
31647247.072: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
31648247.072: <09>Lane 04 nibble 0 raw readback: 0038
31649247.072: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
31650247.072: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
31651247.072: <09>Lane 05 nibble 0 raw readback: 003d
31652247.072: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
31653247.072: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
31654247.072: <09>Lane 06 nibble 0 raw readback: 003d
31655247.072: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
31656247.072: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
31657247.072: <09>Lane 07 nibble 0 raw readback: 0042
31658247.072: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
31659247.072: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
31660247.072: <09>Lane 08 nibble 0 raw readback: 0036
31661247.072: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
31662247.072: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
31663247.072: AgesaHwWlPhase1: training nibble 1
31664247.072: DIMM 1 RttNom: 3
31665247.072: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31666247.072: DIMM 1 RttWr: 2
31667247.072: DIMM 1 RttWr: 2
31668247.072: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31669247.072: DIMM 1 RttWr: 2
31670247.072: DIMM 1 RttNom: 3
31671247.072: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31672247.072: DIMM 1 RttNom: 3
31673247.072: DIMM 1 RttWr: 2
31674247.072: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31675247.072: DIMM 1 RttWr: 2
31676247.072: DIMM 0 RttNom: 3
31677247.072: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31678247.072: DIMM 1 RttNom: 3
31679247.072: DIMM 0 RttWr: 2
31680247.072: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31681247.072: DIMM 1 RttWr: 2
31682247.072: DIMM 0 RttNom: 3
31683247.072: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31684247.072: DIMM 1 RttNom: 3
31685247.072: DIMM 0 RttWr: 2
31686247.072: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31687247.072: DIMM 1 RttWr: 2
31688247.072: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
31689247.072: <09>Lane 00 new seed: 0047
31690247.072: <09>Lane 01 new seed: 0047
31691247.072: <09>Lane 02 new seed: 0047
31692247.072: <09>Lane 03 new seed: 0047
31693247.072: <09>Lane 04 new seed: 0047
31694247.072: <09>Lane 05 new seed: 0047
31695247.072: <09>Lane 06 new seed: 0047
31696247.072: <09>Lane 07 new seed: 0047
31697247.072: <09>Lane 08 new seed: 0047
31698247.072: <09>Lane 00 nibble 1 raw readback: 0046
31699247.072: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
31700247.072: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
31701247.072: <09>Lane 01 nibble 1 raw readback: 003f
31702247.073: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
31703247.073: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
31704247.073: <09>Lane 02 nibble 1 raw readback: 003d
31705247.073: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
31706247.073: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
31707247.073: <09>Lane 03 nibble 1 raw readback: 003b
31708247.073: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
31709247.073: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
31710247.073: <09>Lane 04 nibble 1 raw readback: 0037
31711247.073: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
31712247.073: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
31713247.073: <09>Lane 05 nibble 1 raw readback: 003c
31714247.073: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
31715247.073: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
31716247.073: <09>Lane 06 nibble 1 raw readback: 003f
31717247.073: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
31718247.073: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
31719247.073: <09>Lane 07 nibble 1 raw readback: 0042
31720247.073: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
31721247.073: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
31722247.073: <09>Lane 08 nibble 1 raw readback: 0037
31723247.073: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
31724247.073: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
31725247.073: <09>original critical gross delay: 0
31726247.073: <09>new critical gross delay: 0
31727247.073: DIMM 1 RttNom: 3
31728247.073: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
31729247.073: DIMM 1 RttNom: 3
31730247.073: DIMM 1 RttWr: 2
31731247.073: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
31732247.073: DIMM 1 RttWr: 2
31733247.073: DIMM 1 RttNom: 3
31734247.073: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
31735247.073: DIMM 1 RttNom: 3
31736247.073: DIMM 1 RttWr: 2
31737247.073: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
31738247.073: DIMM 1 RttWr: 2
31739247.073: DIMM 0 RttNom: 3
31740247.073: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
31741247.073: DIMM 1 RttNom: 3
31742247.073: DIMM 0 RttWr: 2
31743247.073: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
31744247.073: DIMM 1 RttWr: 2
31745247.073: DIMM 0 RttNom: 3
31746247.073: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
31747247.073: DIMM 1 RttNom: 3
31748247.073: DIMM 0 RttWr: 2
31749247.073: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
31750247.073: DIMM 1 RttWr: 2
31751247.073: SPD2ndTiming: Start
31752247.074: SPD2ndTiming: Done
31753247.074: mct_BeforeDramInit_Prod_D: Start
31754247.074: mct_ProgramODT_D: Start
31755247.074: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
31756247.074: mct_ProgramODT_D: Done
31757247.074: mct_BeforeDramInit_Prod_D: Done
31758247.074: mct_DramInit_Sw_D: Start
31759247.074: DIMM 0 RttWr: 2
31760247.074: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
31761247.074: mct_SendMrsCmd: Start
31762247.074: mct_SendMrsCmd: Done
31763247.074: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
31764247.074: mct_SendMrsCmd: Start
31765247.074: mct_SendMrsCmd: Done
31766247.074: DIMM 0 RttNom: 3
31767247.074: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
31768247.074: mct_SendMrsCmd: Start
31769247.074: mct_SendMrsCmd: Done
31770247.074: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
31771247.074: mct_SendMrsCmd: Start
31772247.074: mct_SendMrsCmd: Done
31773247.074: DIMM 0 RttWr: 2
31774247.074: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
31775247.074: mct_SendMrsCmd: Start
31776247.074: mct_SendMrsCmd: Done
31777247.074: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
31778247.074: mct_SendMrsCmd: Start
31779247.074: mct_SendMrsCmd: Done
31780247.074: DIMM 0 RttNom: 3
31781247.074: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
31782247.074: mct_SendMrsCmd: Start
31783247.074: mct_SendMrsCmd: Done
31784247.074: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
31785247.074: mct_SendMrsCmd: Start
31786247.074: mct_SendMrsCmd: Done
31787247.074: DIMM 1 RttWr: 2
31788247.074: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
31789247.074: mct_SendMrsCmd: Start
31790247.074: mct_SendMrsCmd: Done
31791247.074: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
31792247.074: mct_SendMrsCmd: Start
31793247.074: mct_SendMrsCmd: Done
31794247.074: DIMM 1 RttNom: 3
31795247.074: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
31796247.074: mct_SendMrsCmd: Start
31797247.074: mct_SendMrsCmd: Done
31798247.074: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
31799247.074: mct_SendMrsCmd: Start
31800247.074: mct_SendMrsCmd: Done
31801247.074: DIMM 1 RttWr: 2
31802247.074: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
31803247.074: mct_SendMrsCmd: Start
31804247.075: mct_SendMrsCmd: Done
31805247.075: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
31806247.075: mct_SendMrsCmd: Start
31807247.075: mct_SendMrsCmd: Done
31808247.075: DIMM 1 RttNom: 3
31809247.075: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
31810247.075: mct_SendMrsCmd: Start
31811247.075: mct_SendMrsCmd: Done
31812247.075: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
31813247.075: mct_SendMrsCmd: Start
31814247.075: mct_SendMrsCmd: Done
31815247.075: mct_DramInit_Sw_D: Done
31816247.075: AgesaHwWlPhase1: training nibble 0
31817247.075: DIMM 0 RttNom: 3
31818247.075: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
31819247.075: DIMM 0 RttWr: 2
31820247.075: DIMM 0 RttWr: 2
31821247.075: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
31822247.075: DIMM 0 RttWr: 2
31823247.075: DIMM 0 RttNom: 3
31824247.075: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
31825247.075: DIMM 0 RttNom: 3
31826247.075: DIMM 0 RttWr: 2
31827247.075: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
31828247.075: DIMM 0 RttWr: 2
31829247.075: DIMM 1 RttNom: 3
31830247.075: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
31831247.075: DIMM 0 RttNom: 3
31832247.075: DIMM 1 RttWr: 2
31833247.075: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
31834247.075: DIMM 0 RttWr: 2
31835247.075: DIMM 1 RttNom: 3
31836247.075: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
31837247.075: DIMM 0 RttNom: 3
31838247.075: DIMM 1 RttWr: 2
31839247.075: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
31840247.075: DIMM 0 RttWr: 2
31841247.075: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
31842247.075: <09>Lane 00 scaled delay: 0047
31843247.075: <09>Lane 00 new seed: 0047
31844247.075: <09>Lane 01 scaled delay: 0047
31845247.075: <09>Lane 01 new seed: 0047
31846247.075: <09>Lane 02 scaled delay: 0047
31847247.075: <09>Lane 02 new seed: 0047
31848247.075: <09>Lane 03 scaled delay: 0047
31849247.075: <09>Lane 03 new seed: 0047
31850247.075: <09>Lane 04 scaled delay: 0047
31851247.075: <09>Lane 04 new seed: 0047
31852247.075: <09>Lane 05 scaled delay: 0047
31853247.075: <09>Lane 05 new seed: 0047
31854247.075: <09>Lane 06 scaled delay: 0047
31855247.075: <09>Lane 06 new seed: 0047
31856247.075: <09>Lane 07 scaled delay: 0047
31857247.075: <09>Lane 07 new seed: 0047
31858247.075: <09>Lane 08 scaled delay: 0047
31859247.075: <09>Lane 08 new seed: 0047
31860247.076: <09>Lane 00 nibble 0 raw readback: 0041
31861247.076: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0041
31862247.076: <09>Lane 00 nibble 0 adjusted value (post nibble): 0041
31863247.076: <09>Lane 01 nibble 0 raw readback: 003c
31864247.076: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
31865247.076: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
31866247.076: <09>Lane 02 nibble 0 raw readback: 0039
31867247.076: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
31868247.076: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
31869247.076: <09>Lane 03 nibble 0 raw readback: 0036
31870247.076: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
31871247.076: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
31872247.076: <09>Lane 04 nibble 0 raw readback: 0034
31873247.076: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0034
31874247.076: <09>Lane 04 nibble 0 adjusted value (post nibble): 0034
31875247.076: <09>Lane 05 nibble 0 raw readback: 0038
31876247.076: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0038
31877247.076: <09>Lane 05 nibble 0 adjusted value (post nibble): 0038
31878247.076: <09>Lane 06 nibble 0 raw readback: 003a
31879247.076: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003a
31880247.076: <09>Lane 06 nibble 0 adjusted value (post nibble): 003a
31881247.076: <09>Lane 07 nibble 0 raw readback: 003e
31882247.076: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003e
31883247.076: <09>Lane 07 nibble 0 adjusted value (post nibble): 003e
31884247.076: <09>Lane 08 nibble 0 raw readback: 0032
31885247.076: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
31886247.076: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
31887247.076: AgesaHwWlPhase1: training nibble 1
31888247.076: DIMM 0 RttNom: 3
31889247.076: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
31890247.076: DIMM 0 RttWr: 2
31891247.076: DIMM 0 RttWr: 2
31892247.076: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
31893247.076: DIMM 0 RttWr: 2
31894247.076: DIMM 0 RttNom: 3
31895247.076: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
31896247.076: DIMM 0 RttNom: 3
31897247.076: DIMM 0 RttWr: 2
31898247.076: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
31899247.076: DIMM 0 RttWr: 2
31900247.076: DIMM 1 RttNom: 3
31901247.076: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
31902247.076: DIMM 0 RttNom: 3
31903247.076: DIMM 1 RttWr: 2
31904247.076: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
31905247.076: DIMM 0 RttWr: 2
31906247.076: DIMM 1 RttNom: 3
31907247.076: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
31908247.076: DIMM 0 RttNom: 3
31909247.076: DIMM 1 RttWr: 2
31910247.076: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
31911247.076: DIMM 0 RttWr: 2
31912247.076: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
31913247.076: <09>Lane 00 new seed: 0047
31914247.076: <09>Lane 01 new seed: 0047
31915247.076: <09>Lane 02 new seed: 0047
31916247.076: <09>Lane 03 new seed: 0047
31917247.076: <09>Lane 04 new seed: 0047
31918247.076: <09>Lane 05 new seed: 0047
31919247.076: <09>Lane 06 new seed: 0047
31920247.076: <09>Lane 07 new seed: 0047
31921247.076: <09>Lane 08 new seed: 0047
31922247.076: <09>Lane 00 nibble 1 raw readback: 0040
31923247.076: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0040
31924247.076: <09>Lane 00 nibble 1 adjusted value (post nibble): 0043
31925247.076: <09>Lane 01 nibble 1 raw readback: 003d
31926247.076: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003d
31927247.076: <09>Lane 01 nibble 1 adjusted value (post nibble): 0042
31928247.077: <09>Lane 02 nibble 1 raw readback: 0039
31929247.077: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
31930247.077: <09>Lane 02 nibble 1 adjusted value (post nibble): 0040
31931247.077: <09>Lane 03 nibble 1 raw readback: 0036
31932247.077: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
31933247.077: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
31934247.077: <09>Lane 04 nibble 1 raw readback: 0034
31935247.077: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0034
31936247.077: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
31937247.077: <09>Lane 05 nibble 1 raw readback: 0037
31938247.077: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0037
31939247.077: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
31940247.077: <09>Lane 06 nibble 1 raw readback: 003b
31941247.077: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003b
31942247.077: <09>Lane 06 nibble 1 adjusted value (post nibble): 0041
31943247.077: <09>Lane 07 nibble 1 raw readback: 003f
31944247.077: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
31945247.077: <09>Lane 07 nibble 1 adjusted value (post nibble): 0043
31946247.077: <09>Lane 08 nibble 1 raw readback: 0031
31947247.077: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
31948247.077: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
31949247.077: <09>original critical gross delay: 0
31950247.077: <09>new critical gross delay: 0
31951247.077: DIMM 0 RttNom: 3
31952247.077: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
31953247.077: DIMM 0 RttNom: 3
31954247.077: DIMM 0 RttWr: 2
31955247.077: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
31956247.077: DIMM 0 RttWr: 2
31957247.077: DIMM 0 RttNom: 3
31958247.077: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
31959247.077: DIMM 0 RttNom: 3
31960247.077: DIMM 0 RttWr: 2
31961247.077: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
31962247.077: DIMM 0 RttWr: 2
31963247.077: DIMM 1 RttNom: 3
31964247.077: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
31965247.077: DIMM 0 RttNom: 3
31966247.077: DIMM 1 RttWr: 2
31967247.077: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
31968247.077: DIMM 0 RttWr: 2
31969247.077: DIMM 1 RttNom: 3
31970247.077: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
31971247.077: DIMM 0 RttNom: 3
31972247.077: DIMM 1 RttWr: 2
31973247.077: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
31974247.077: DIMM 0 RttWr: 2
31975247.077: AgesaHwWlPhase1: training nibble 0
31976247.077: DIMM 1 RttNom: 3
31977247.077: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
31978247.077: DIMM 1 RttWr: 2
31979247.077: DIMM 1 RttWr: 2
31980247.077: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
31981247.077: DIMM 1 RttWr: 2
31982247.077: DIMM 1 RttNom: 3
31983247.077: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
31984247.077: DIMM 1 RttNom: 3
31985247.077: DIMM 1 RttWr: 2
31986247.077: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
31987247.077: DIMM 1 RttWr: 2
31988247.077: DIMM 0 RttNom: 3
31989247.077: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
31990247.078: DIMM 1 RttNom: 3
31991247.078: DIMM 0 RttWr: 2
31992247.078: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
31993247.078: DIMM 1 RttWr: 2
31994247.078: DIMM 0 RttNom: 3
31995247.078: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
31996247.078: DIMM 1 RttNom: 3
31997247.078: DIMM 0 RttWr: 2
31998247.078: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
31999247.078: DIMM 1 RttWr: 2
32000247.078: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
32001247.078: <09>Lane 00 scaled delay: 0047
32002247.078: <09>Lane 00 new seed: 0047
32003247.078: <09>Lane 01 scaled delay: 0047
32004247.078: <09>Lane 01 new seed: 0047
32005247.078: <09>Lane 02 scaled delay: 0047
32006247.078: <09>Lane 02 new seed: 0047
32007247.078: <09>Lane 03 scaled delay: 0047
32008247.078: <09>Lane 03 new seed: 0047
32009247.078: <09>Lane 04 scaled delay: 0047
32010247.078: <09>Lane 04 new seed: 0047
32011247.078: <09>Lane 05 scaled delay: 0047
32012247.078: <09>Lane 05 new seed: 0047
32013247.078: <09>Lane 06 scaled delay: 0047
32014247.078: <09>Lane 06 new seed: 0047
32015247.078: <09>Lane 07 scaled delay: 0047
32016247.078: <09>Lane 07 new seed: 0047
32017247.078: <09>Lane 08 scaled delay: 0047
32018247.078: <09>Lane 08 new seed: 0047
32019247.078: <09>Lane 00 nibble 0 raw readback: 0044
32020247.078: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
32021247.078: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
32022247.078: <09>Lane 01 nibble 0 raw readback: 0043
32023247.078: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0043
32024247.078: <09>Lane 01 nibble 0 adjusted value (post nibble): 0043
32025247.078: <09>Lane 02 nibble 0 raw readback: 003e
32026247.078: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
32027247.078: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
32028247.078: <09>Lane 03 nibble 0 raw readback: 003a
32029247.078: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
32030247.078: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
32031247.078: <09>Lane 04 nibble 0 raw readback: 0039
32032247.078: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
32033247.078: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
32034247.078: <09>Lane 05 nibble 0 raw readback: 003d
32035247.078: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
32036247.078: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
32037247.078: <09>Lane 06 nibble 0 raw readback: 0041
32038247.078: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
32039247.078: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
32040247.078: <09>Lane 07 nibble 0 raw readback: 0044
32041247.078: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
32042247.078: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
32043247.078: <09>Lane 08 nibble 0 raw readback: 0036
32044247.078: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
32045247.078: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
32046247.078: AgesaHwWlPhase1: training nibble 1
32047247.078: DIMM 1 RttNom: 3
32048247.078: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32049247.078: DIMM 1 RttWr: 2
32050247.078: DIMM 1 RttWr: 2
32051247.078: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
32052247.078: DIMM 1 RttWr: 2
32053247.078: DIMM 1 RttNom: 3
32054247.078: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32055247.078: DIMM 1 RttNom: 3
32056247.078: DIMM 1 RttWr: 2
32057247.078: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
32058247.078: DIMM 1 RttWr: 2
32059247.078: DIMM 0 RttNom: 3
32060247.078: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32061247.078: DIMM 1 RttNom: 3
32062247.079: DIMM 0 RttWr: 2
32063247.079: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
32064247.079: DIMM 1 RttWr: 2
32065247.079: DIMM 0 RttNom: 3
32066247.079: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32067247.079: DIMM 1 RttNom: 3
32068247.079: DIMM 0 RttWr: 2
32069247.079: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
32070247.079: DIMM 1 RttWr: 2
32071247.079: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
32072247.079: <09>Lane 00 new seed: 0047
32073247.079: <09>Lane 01 new seed: 0047
32074247.079: <09>Lane 02 new seed: 0047
32075247.079: <09>Lane 03 new seed: 0047
32076247.079: <09>Lane 04 new seed: 0047
32077247.079: <09>Lane 05 new seed: 0047
32078247.079: <09>Lane 06 new seed: 0047
32079247.079: <09>Lane 07 new seed: 0047
32080247.079: <09>Lane 08 new seed: 0047
32081247.079: <09>Lane 00 nibble 1 raw readback: 0046
32082247.079: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
32083247.079: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
32084247.079: <09>Lane 01 nibble 1 raw readback: 0042
32085247.079: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
32086247.079: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
32087247.079: <09>Lane 02 nibble 1 raw readback: 003e
32088247.079: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
32089247.079: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
32090247.079: <09>Lane 03 nibble 1 raw readback: 003b
32091247.079: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
32092247.079: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
32093247.079: <09>Lane 04 nibble 1 raw readback: 0038
32094247.079: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
32095247.079: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
32096247.079: <09>Lane 05 nibble 1 raw readback: 003b
32097247.079: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
32098247.079: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
32099247.079: <09>Lane 06 nibble 1 raw readback: 0040
32100247.079: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
32101247.079: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
32102247.079: <09>Lane 07 nibble 1 raw readback: 0044
32103247.079: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0044
32104247.079: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
32105247.079: <09>Lane 08 nibble 1 raw readback: 0037
32106247.079: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
32107247.079: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
32108247.079: <09>original critical gross delay: 0
32109247.079: <09>new critical gross delay: 0
32110247.079: DIMM 1 RttNom: 3
32111247.079: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32112247.079: DIMM 1 RttNom: 3
32113247.079: DIMM 1 RttWr: 2
32114247.079: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
32115247.079: DIMM 1 RttWr: 2
32116247.079: DIMM 1 RttNom: 3
32117247.079: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32118247.079: DIMM 1 RttNom: 3
32119247.079: DIMM 1 RttWr: 2
32120247.079: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
32121247.079: DIMM 1 RttWr: 2
32122247.079: DIMM 0 RttNom: 3
32123247.079: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32124247.079: DIMM 1 RttNom: 3
32125247.079: DIMM 0 RttWr: 2
32126247.080: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
32127247.080: DIMM 1 RttWr: 2
32128247.080: DIMM 0 RttNom: 3
32129247.080: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32130247.080: DIMM 1 RttNom: 3
32131247.080: DIMM 0 RttWr: 2
32132247.080: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
32133247.080: DIMM 1 RttWr: 2
32134247.080: SetTargetFreq: Start
32135247.080: SetTargetFreq: Node 1: New frequency code: 000a
32136247.080: ChangeMemClk: Start
32137247.080: set_2t_configuration: Start
32138247.080: set_2t_configuration: Done
32139247.080: mct_BeforePlatformSpec: Start
32140247.080: mct_BeforePlatformSpec: Done
32141247.080: mct_PlatformSpec: Start
32142247.080: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
32143247.080: mct_PlatformSpec: Done
32144247.080: set_2t_configuration: Start
32145247.080: set_2t_configuration: Done
32146247.080: mct_BeforePlatformSpec: Start
32147247.080: mct_BeforePlatformSpec: Done
32148247.080: mct_PlatformSpec: Start
32149247.080: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
32150247.080: mct_PlatformSpec: Done
32151247.080: ChangeMemClk: Done
32152247.080: phyAssistedMemFnceTraining: Start
32153247.080: phyAssistedMemFnceTraining: training node 1 DCT 0
32154247.080: phyAssistedMemFnceTraining: done training node 1 DCT 0
32155247.080: phyAssistedMemFnceTraining: training node 1 DCT 1
32156247.081: phyAssistedMemFnceTraining: done training node 1 DCT 1
32157247.081: phyAssistedMemFnceTraining: Done
32158247.081: InitPhyCompensation: DCT 0: Start
32159247.081: Waiting for predriver calibration to be applied...done!
32160247.081: InitPhyCompensation: DCT 0: Done
32161247.081: phyAssistedMemFnceTraining: Start
32162247.081: phyAssistedMemFnceTraining: training node 1 DCT 0
32163247.081: phyAssistedMemFnceTraining: done training node 1 DCT 0
32164247.081: phyAssistedMemFnceTraining: training node 1 DCT 1
32165247.081: phyAssistedMemFnceTraining: done training node 1 DCT 1
32166247.081: phyAssistedMemFnceTraining: Done
32167247.081: InitPhyCompensation: DCT 1: Start
32168247.081: Waiting for predriver calibration to be applied...done!
32169247.081: InitPhyCompensation: DCT 1: Done
32170247.081: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
32171247.081: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
32172247.081: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
32173247.081: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
32174247.081: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
32175247.082: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
32176247.082: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
32177247.082: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
32178247.082: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
32179247.082: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
32180247.082: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
32181247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
32182247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
32183247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
32184247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
32185247.082: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
32186247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
32187247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
32188247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
32189247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
32190247.082: SetTargetFreq: Done
32191247.082: SPD2ndTiming: Start
32192247.082: SPD2ndTiming: Done
32193247.082: mct_BeforeDramInit_Prod_D: Start
32194247.082: mct_ProgramODT_D: Start
32195247.082: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
32196247.082: mct_ProgramODT_D: Done
32197247.082: mct_BeforeDramInit_Prod_D: Done
32198247.082: mct_DramInit_Sw_D: Start
32199247.082: DIMM 0 RttWr: 1
32200247.082: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32201247.082: mct_SendMrsCmd: Start
32202247.082: mct_SendMrsCmd: Done
32203247.082: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
32204247.082: mct_SendMrsCmd: Start
32205247.082: mct_SendMrsCmd: Done
32206247.082: DIMM 0 RttNom: 3
32207247.082: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32208247.082: mct_SendMrsCmd: Start
32209247.082: mct_SendMrsCmd: Done
32210247.082: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
32211247.082: mct_SendMrsCmd: Start
32212247.082: mct_SendMrsCmd: Done
32213247.082: DIMM 0 RttWr: 1
32214247.082: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32215247.082: mct_SendMrsCmd: Start
32216247.082: mct_SendMrsCmd: Done
32217247.082: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
32218247.083: mct_SendMrsCmd: Start
32219247.083: mct_SendMrsCmd: Done
32220247.083: DIMM 0 RttNom: 3
32221247.083: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32222247.083: mct_SendMrsCmd: Start
32223247.083: mct_SendMrsCmd: Done
32224247.083: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
32225247.083: mct_SendMrsCmd: Start
32226247.083: mct_SendMrsCmd: Done
32227247.083: DIMM 1 RttWr: 1
32228247.083: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32229247.083: mct_SendMrsCmd: Start
32230247.083: mct_SendMrsCmd: Done
32231247.083: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
32232247.083: mct_SendMrsCmd: Start
32233247.083: mct_SendMrsCmd: Done
32234247.083: DIMM 1 RttNom: 3
32235247.083: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32236247.083: mct_SendMrsCmd: Start
32237247.083: mct_SendMrsCmd: Done
32238247.083: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
32239247.083: mct_SendMrsCmd: Start
32240247.083: mct_SendMrsCmd: Done
32241247.083: DIMM 1 RttWr: 1
32242247.083: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32243247.083: mct_SendMrsCmd: Start
32244247.083: mct_SendMrsCmd: Done
32245247.083: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
32246247.083: mct_SendMrsCmd: Start
32247247.083: mct_SendMrsCmd: Done
32248247.083: DIMM 1 RttNom: 3
32249247.083: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32250247.083: mct_SendMrsCmd: Start
32251247.083: mct_SendMrsCmd: Done
32252247.083: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
32253247.083: mct_SendMrsCmd: Start
32254247.083: mct_SendMrsCmd: Done
32255247.083: mct_DramInit_Sw_D: Done
32256247.083: AgesaHwWlPhase1: training nibble 0
32257247.083: DIMM 0 RttNom: 3
32258247.083: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32259247.083: DIMM 0 RttWr: 1
32260247.083: DIMM 0 RttWr: 1
32261247.083: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32262247.083: DIMM 0 RttWr: 1
32263247.083: DIMM 0 RttNom: 3
32264247.083: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32265247.083: DIMM 0 RttNom: 3
32266247.083: DIMM 0 RttWr: 1
32267247.083: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32268247.083: DIMM 0 RttWr: 1
32269247.084: DIMM 1 RttNom: 3
32270247.084: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32271247.084: DIMM 0 RttNom: 3
32272247.084: DIMM 1 RttWr: 1
32273247.084: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32274247.084: DIMM 0 RttWr: 1
32275247.084: DIMM 1 RttNom: 3
32276247.084: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32277247.084: DIMM 0 RttNom: 3
32278247.084: DIMM 1 RttWr: 1
32279247.084: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32280247.084: DIMM 0 RttWr: 1
32281247.084: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
32282247.084: <09>Lane 00 scaled delay: 004e
32283247.084: <09>Lane 00 new seed: 004e
32284247.084: <09>Lane 01 scaled delay: 004b
32285247.084: <09>Lane 01 new seed: 004b
32286247.084: <09>Lane 02 scaled delay: 004a
32287247.084: <09>Lane 02 new seed: 004a
32288247.084: <09>Lane 03 scaled delay: 0049
32289247.084: <09>Lane 03 new seed: 0049
32290247.084: <09>Lane 04 scaled delay: 0045
32291247.084: <09>Lane 04 new seed: 0045
32292247.084: <09>Lane 05 scaled delay: 0049
32293247.084: <09>Lane 05 new seed: 0049
32294247.084: <09>Lane 06 scaled delay: 004a
32295247.084: <09>Lane 06 new seed: 004a
32296247.084: <09>Lane 07 scaled delay: 004d
32297247.084: <09>Lane 07 new seed: 004d
32298247.084: <09>Lane 08 scaled delay: 0045
32299247.084: <09>Lane 08 new seed: 0045
32300247.084: <09>Lane 00 nibble 0 raw readback: 004a
32301247.084: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004a
32302247.084: <09>Lane 00 nibble 0 adjusted value (post nibble): 004a
32303247.084: <09>Lane 01 nibble 0 raw readback: 0043
32304247.084: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0043
32305247.084: <09>Lane 01 nibble 0 adjusted value (post nibble): 0043
32306247.084: <09>Lane 02 nibble 0 raw readback: 0040
32307247.084: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0040
32308247.084: <09>Lane 02 nibble 0 adjusted value (post nibble): 0040
32309247.084: <09>Lane 03 nibble 0 raw readback: 003d
32310247.084: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003d
32311247.084: <09>Lane 03 nibble 0 adjusted value (post nibble): 003d
32312247.084: <09>Lane 04 nibble 0 raw readback: 003a
32313247.084: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
32314247.084: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
32315247.084: <09>Lane 05 nibble 0 raw readback: 003e
32316247.084: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
32317247.084: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
32318247.084: <09>Lane 06 nibble 0 raw readback: 0041
32319247.084: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
32320247.084: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
32321247.084: <09>Lane 07 nibble 0 raw readback: 0045
32322247.084: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
32323247.084: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
32324247.085: <09>Lane 08 nibble 0 raw readback: 0037
32325247.085: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
32326247.085: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
32327247.085: AgesaHwWlPhase1: training nibble 1
32328247.085: DIMM 0 RttNom: 3
32329247.085: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32330247.085: DIMM 0 RttWr: 1
32331247.085: DIMM 0 RttWr: 1
32332247.085: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32333247.085: DIMM 0 RttWr: 1
32334247.085: DIMM 0 RttNom: 3
32335247.085: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32336247.085: DIMM 0 RttNom: 3
32337247.085: DIMM 0 RttWr: 1
32338247.085: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32339247.085: DIMM 0 RttWr: 1
32340247.085: DIMM 1 RttNom: 3
32341247.085: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32342247.085: DIMM 0 RttNom: 3
32343247.085: DIMM 1 RttWr: 1
32344247.085: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32345247.085: DIMM 0 RttWr: 1
32346247.085: DIMM 1 RttNom: 3
32347247.085: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32348247.085: DIMM 0 RttNom: 3
32349247.085: DIMM 1 RttWr: 1
32350247.085: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32351247.085: DIMM 0 RttWr: 1
32352247.085: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
32353247.085: <09>Lane 00 new seed: 004e
32354247.085: <09>Lane 01 new seed: 004b
32355247.085: <09>Lane 02 new seed: 004a
32356247.085: <09>Lane 03 new seed: 0049
32357247.085: <09>Lane 04 new seed: 0045
32358247.085: <09>Lane 05 new seed: 0049
32359247.085: <09>Lane 06 new seed: 004a
32360247.085: <09>Lane 07 new seed: 004d
32361247.085: <09>Lane 08 new seed: 0045
32362247.085: <09>Lane 00 nibble 1 raw readback: 0048
32363247.085: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0048
32364247.085: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
32365247.085: <09>Lane 01 nibble 1 raw readback: 0043
32366247.085: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0043
32367247.085: <09>Lane 01 nibble 1 adjusted value (post nibble): 0047
32368247.085: <09>Lane 02 nibble 1 raw readback: 003f
32369247.085: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
32370247.085: <09>Lane 02 nibble 1 adjusted value (post nibble): 0044
32371247.085: <09>Lane 03 nibble 1 raw readback: 003e
32372247.085: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003e
32373247.085: <09>Lane 03 nibble 1 adjusted value (post nibble): 0043
32374247.085: <09>Lane 04 nibble 1 raw readback: 0039
32375247.085: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
32376247.085: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
32377247.085: <09>Lane 05 nibble 1 raw readback: 003f
32378247.085: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003f
32379247.085: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
32380247.085: <09>Lane 06 nibble 1 raw readback: 0042
32381247.085: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0042
32382247.085: <09>Lane 06 nibble 1 adjusted value (post nibble): 0046
32383247.085: <09>Lane 07 nibble 1 raw readback: 0045
32384247.085: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
32385247.085: <09>Lane 07 nibble 1 adjusted value (post nibble): 0049
32386247.085: <09>Lane 08 nibble 1 raw readback: 0036
32387247.085: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
32388247.085: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
32389247.085: <09>original critical gross delay: 0
32390247.085: <09>new critical gross delay: 0
32391247.086: DIMM 0 RttNom: 3
32392247.086: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32393247.086: DIMM 0 RttNom: 3
32394247.086: DIMM 0 RttWr: 1
32395247.086: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32396247.086: DIMM 0 RttWr: 1
32397247.086: DIMM 0 RttNom: 3
32398247.086: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32399247.086: DIMM 0 RttNom: 3
32400247.086: DIMM 0 RttWr: 1
32401247.086: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32402247.086: DIMM 0 RttWr: 1
32403247.086: DIMM 1 RttNom: 3
32404247.086: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32405247.086: DIMM 0 RttNom: 3
32406247.086: DIMM 1 RttWr: 1
32407247.086: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32408247.086: DIMM 0 RttWr: 1
32409247.086: DIMM 1 RttNom: 3
32410247.086: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32411247.086: DIMM 0 RttNom: 3
32412247.086: DIMM 1 RttWr: 1
32413247.086: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32414247.086: DIMM 0 RttWr: 1
32415247.086: AgesaHwWlPhase1: training nibble 0
32416247.086: DIMM 1 RttNom: 3
32417247.086: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32418247.086: DIMM 1 RttWr: 1
32419247.086: DIMM 1 RttWr: 1
32420247.086: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32421247.086: DIMM 1 RttWr: 1
32422247.086: DIMM 1 RttNom: 3
32423247.086: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32424247.086: DIMM 1 RttNom: 3
32425247.086: DIMM 1 RttWr: 1
32426247.086: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32427247.086: DIMM 1 RttWr: 1
32428247.086: DIMM 0 RttNom: 3
32429247.086: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32430247.086: DIMM 1 RttNom: 3
32431247.086: DIMM 0 RttWr: 1
32432247.086: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32433247.086: DIMM 1 RttWr: 1
32434247.086: DIMM 0 RttNom: 3
32435247.086: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32436247.086: DIMM 1 RttNom: 3
32437247.086: DIMM 0 RttWr: 1
32438247.086: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32439247.086: DIMM 1 RttWr: 1
32440247.086: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
32441247.086: <09>Lane 00 scaled delay: 0052
32442247.086: <09>Lane 00 new seed: 0052
32443247.086: <09>Lane 01 scaled delay: 004e
32444247.086: <09>Lane 01 new seed: 004e
32445247.086: <09>Lane 02 scaled delay: 004d
32446247.086: <09>Lane 02 new seed: 004d
32447247.086: <09>Lane 03 scaled delay: 004b
32448247.087: <09>Lane 03 new seed: 004b
32449247.086: <09>Lane 04 scaled delay: 0049
32450247.087: <09>Lane 04 new seed: 0049
32451247.087: <09>Lane 05 scaled delay: 004b
32452247.087: <09>Lane 05 new seed: 004b
32453247.087: <09>Lane 06 scaled delay: 004e
32454247.087: <09>Lane 06 new seed: 004e
32455247.087: <09>Lane 07 scaled delay: 004f
32456247.087: <09>Lane 07 new seed: 004f
32457247.087: <09>Lane 08 scaled delay: 0049
32458247.087: <09>Lane 08 new seed: 0049
32459247.087: <09>Lane 00 nibble 0 raw readback: 0051
32460247.087: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0051
32461247.087: <09>Lane 00 nibble 0 adjusted value (post nibble): 0051
32462247.087: <09>Lane 01 nibble 0 raw readback: 004b
32463247.087: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
32464247.087: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
32465247.087: <09>Lane 02 nibble 0 raw readback: 0046
32466247.087: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
32467247.087: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
32468247.087: <09>Lane 03 nibble 0 raw readback: 0046
32469247.087: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0046
32470247.087: <09>Lane 03 nibble 0 adjusted value (post nibble): 0046
32471247.087: <09>Lane 04 nibble 0 raw readback: 0042
32472247.087: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
32473247.087: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
32474247.087: <09>Lane 05 nibble 0 raw readback: 0048
32475247.087: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
32476247.087: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
32477247.087: <09>Lane 06 nibble 0 raw readback: 0049
32478247.087: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
32479247.087: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
32480247.087: <09>Lane 07 nibble 0 raw readback: 004e
32481247.087: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
32482247.087: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
32483247.087: <09>Lane 08 nibble 0 raw readback: 003f
32484247.087: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
32485247.087: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
32486247.087: AgesaHwWlPhase1: training nibble 1
32487247.087: DIMM 1 RttNom: 3
32488247.087: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32489247.087: DIMM 1 RttWr: 1
32490247.087: DIMM 1 RttWr: 1
32491247.087: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32492247.087: DIMM 1 RttWr: 1
32493247.087: DIMM 1 RttNom: 3
32494247.087: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32495247.087: DIMM 1 RttNom: 3
32496247.087: DIMM 1 RttWr: 1
32497247.087: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32498247.087: DIMM 1 RttWr: 1
32499247.087: DIMM 0 RttNom: 3
32500247.087: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32501247.087: DIMM 1 RttNom: 3
32502247.087: DIMM 0 RttWr: 1
32503247.087: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32504247.087: DIMM 1 RttWr: 1
32505247.087: DIMM 0 RttNom: 3
32506247.087: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32507247.087: DIMM 1 RttNom: 3
32508247.087: DIMM 0 RttWr: 1
32509247.087: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32510247.087: DIMM 1 RttWr: 1
32511247.087: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
32512247.087: <09>Lane 00 new seed: 0052
32513247.087: <09>Lane 01 new seed: 004e
32514247.087: <09>Lane 02 new seed: 004d
32515247.087: <09>Lane 03 new seed: 004b
32516247.087: <09>Lane 04 new seed: 0049
32517247.087: <09>Lane 05 new seed: 004b
32518247.087: <09>Lane 06 new seed: 004e
32519247.087: <09>Lane 07 new seed: 004f
32520247.087: <09>Lane 08 new seed: 0049
32521247.088: <09>Lane 00 nibble 1 raw readback: 0051
32522247.088: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
32523247.088: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
32524247.088: <09>Lane 01 nibble 1 raw readback: 004b
32525247.088: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004b
32526247.088: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
32527247.088: <09>Lane 02 nibble 1 raw readback: 0047
32528247.088: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
32529247.088: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
32530247.088: <09>Lane 03 nibble 1 raw readback: 0045
32531247.088: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
32532247.088: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
32533247.088: <09>Lane 04 nibble 1 raw readback: 0040
32534247.088: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
32535247.088: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
32536247.088: <09>Lane 05 nibble 1 raw readback: 0045
32537247.088: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
32538247.088: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
32539247.088: <09>Lane 06 nibble 1 raw readback: 0049
32540247.088: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
32541247.088: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
32542247.088: <09>Lane 07 nibble 1 raw readback: 004e
32543247.088: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
32544247.088: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
32545247.088: <09>Lane 08 nibble 1 raw readback: 003f
32546247.088: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
32547247.088: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
32548247.088: <09>original critical gross delay: 0
32549247.088: <09>new critical gross delay: 0
32550247.088: DIMM 1 RttNom: 3
32551247.088: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
32552247.088: DIMM 1 RttNom: 3
32553247.088: DIMM 1 RttWr: 1
32554247.088: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
32555247.088: DIMM 1 RttWr: 1
32556247.088: DIMM 1 RttNom: 3
32557247.088: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
32558247.088: DIMM 1 RttNom: 3
32559247.088: DIMM 1 RttWr: 1
32560247.088: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
32561247.088: DIMM 1 RttWr: 1
32562247.088: DIMM 0 RttNom: 3
32563247.088: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
32564247.088: DIMM 1 RttNom: 3
32565247.088: DIMM 0 RttWr: 1
32566247.088: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
32567247.088: DIMM 1 RttWr: 1
32568247.088: DIMM 0 RttNom: 3
32569247.088: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
32570247.088: DIMM 1 RttNom: 3
32571247.088: DIMM 0 RttWr: 1
32572247.088: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
32573247.088: DIMM 1 RttWr: 1
32574247.088: SPD2ndTiming: Start
32575247.089: SPD2ndTiming: Done
32576247.089: mct_BeforeDramInit_Prod_D: Start
32577247.089: mct_ProgramODT_D: Start
32578247.089: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
32579247.089: mct_ProgramODT_D: Done
32580247.089: mct_BeforeDramInit_Prod_D: Done
32581247.089: mct_DramInit_Sw_D: Start
32582247.089: DIMM 0 RttWr: 1
32583247.089: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32584247.089: mct_SendMrsCmd: Start
32585247.089: mct_SendMrsCmd: Done
32586247.089: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
32587247.089: mct_SendMrsCmd: Start
32588247.089: mct_SendMrsCmd: Done
32589247.089: DIMM 0 RttNom: 3
32590247.089: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32591247.089: mct_SendMrsCmd: Start
32592247.089: mct_SendMrsCmd: Done
32593247.089: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
32594247.089: mct_SendMrsCmd: Start
32595247.089: mct_SendMrsCmd: Done
32596247.089: DIMM 0 RttWr: 1
32597247.089: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32598247.089: mct_SendMrsCmd: Start
32599247.089: mct_SendMrsCmd: Done
32600247.089: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
32601247.089: mct_SendMrsCmd: Start
32602247.089: mct_SendMrsCmd: Done
32603247.089: DIMM 0 RttNom: 3
32604247.089: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32605247.089: mct_SendMrsCmd: Start
32606247.089: mct_SendMrsCmd: Done
32607247.089: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
32608247.089: mct_SendMrsCmd: Start
32609247.089: mct_SendMrsCmd: Done
32610247.089: DIMM 1 RttWr: 1
32611247.089: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32612247.089: mct_SendMrsCmd: Start
32613247.089: mct_SendMrsCmd: Done
32614247.089: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
32615247.089: mct_SendMrsCmd: Start
32616247.089: mct_SendMrsCmd: Done
32617247.089: DIMM 1 RttNom: 3
32618247.089: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32619247.089: mct_SendMrsCmd: Start
32620247.089: mct_SendMrsCmd: Done
32621247.089: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
32622247.089: mct_SendMrsCmd: Start
32623247.089: mct_SendMrsCmd: Done
32624247.089: DIMM 1 RttWr: 1
32625247.089: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32626247.089: mct_SendMrsCmd: Start
32627247.089: mct_SendMrsCmd: Done
32628247.090: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
32629247.090: mct_SendMrsCmd: Start
32630247.090: mct_SendMrsCmd: Done
32631247.090: DIMM 1 RttNom: 3
32632247.090: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32633247.090: mct_SendMrsCmd: Start
32634247.090: mct_SendMrsCmd: Done
32635247.090: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
32636247.090: mct_SendMrsCmd: Start
32637247.090: mct_SendMrsCmd: Done
32638247.090: mct_DramInit_Sw_D: Done
32639247.090: AgesaHwWlPhase1: training nibble 0
32640247.090: DIMM 0 RttNom: 3
32641247.090: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32642247.090: DIMM 0 RttWr: 1
32643247.090: DIMM 0 RttWr: 1
32644247.090: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32645247.090: DIMM 0 RttWr: 1
32646247.090: DIMM 0 RttNom: 3
32647247.090: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32648247.090: DIMM 0 RttNom: 3
32649247.090: DIMM 0 RttWr: 1
32650247.090: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32651247.090: DIMM 0 RttWr: 1
32652247.090: DIMM 1 RttNom: 3
32653247.090: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32654247.090: DIMM 0 RttNom: 3
32655247.090: DIMM 1 RttWr: 1
32656247.090: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32657247.090: DIMM 0 RttWr: 1
32658247.090: DIMM 1 RttNom: 3
32659247.090: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32660247.090: DIMM 0 RttNom: 3
32661247.090: DIMM 1 RttWr: 1
32662247.090: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32663247.090: DIMM 0 RttWr: 1
32664247.090: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
32665247.090: <09>Lane 00 scaled delay: 004e
32666247.090: <09>Lane 00 new seed: 004e
32667247.090: <09>Lane 01 scaled delay: 004d
32668247.090: <09>Lane 01 new seed: 004d
32669247.090: <09>Lane 02 scaled delay: 004a
32670247.090: <09>Lane 02 new seed: 004a
32671247.090: <09>Lane 03 scaled delay: 0047
32672247.090: <09>Lane 03 new seed: 0047
32673247.090: <09>Lane 04 scaled delay: 0046
32674247.090: <09>Lane 04 new seed: 0046
32675247.090: <09>Lane 05 scaled delay: 0049
32676247.090: <09>Lane 05 new seed: 0049
32677247.090: <09>Lane 06 scaled delay: 004b
32678247.090: <09>Lane 06 new seed: 004b
32679247.090: <09>Lane 07 scaled delay: 004e
32680247.090: <09>Lane 07 new seed: 004e
32681247.090: <09>Lane 08 scaled delay: 0045
32682247.090: <09>Lane 08 new seed: 0045
32683247.091: <09>Lane 00 nibble 0 raw readback: 004d
32684247.091: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
32685247.091: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
32686247.091: <09>Lane 01 nibble 0 raw readback: 0047
32687247.091: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
32688247.091: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
32689247.091: <09>Lane 02 nibble 0 raw readback: 0042
32690247.091: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0042
32691247.091: <09>Lane 02 nibble 0 adjusted value (post nibble): 0042
32692247.091: <09>Lane 03 nibble 0 raw readback: 003f
32693247.091: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003f
32694247.091: <09>Lane 03 nibble 0 adjusted value (post nibble): 003f
32695247.091: <09>Lane 04 nibble 0 raw readback: 003c
32696247.091: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003c
32697247.091: <09>Lane 04 nibble 0 adjusted value (post nibble): 003c
32698247.091: <09>Lane 05 nibble 0 raw readback: 0041
32699247.091: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
32700247.091: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
32701247.091: <09>Lane 06 nibble 0 raw readback: 0044
32702247.091: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0044
32703247.091: <09>Lane 06 nibble 0 adjusted value (post nibble): 0044
32704247.091: <09>Lane 07 nibble 0 raw readback: 004a
32705247.091: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004a
32706247.091: <09>Lane 07 nibble 0 adjusted value (post nibble): 004a
32707247.091: <09>Lane 08 nibble 0 raw readback: 0039
32708247.091: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
32709247.091: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
32710247.091: AgesaHwWlPhase1: training nibble 1
32711247.091: DIMM 0 RttNom: 3
32712247.091: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32713247.091: DIMM 0 RttWr: 1
32714247.091: DIMM 0 RttWr: 1
32715247.091: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32716247.091: DIMM 0 RttWr: 1
32717247.091: DIMM 0 RttNom: 3
32718247.091: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32719247.091: DIMM 0 RttNom: 3
32720247.091: DIMM 0 RttWr: 1
32721247.091: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32722247.091: DIMM 0 RttWr: 1
32723247.091: DIMM 1 RttNom: 3
32724247.091: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32725247.091: DIMM 0 RttNom: 3
32726247.091: DIMM 1 RttWr: 1
32727247.091: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32728247.091: DIMM 0 RttWr: 1
32729247.091: DIMM 1 RttNom: 3
32730247.091: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32731247.091: DIMM 0 RttNom: 3
32732247.091: DIMM 1 RttWr: 1
32733247.091: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32734247.091: DIMM 0 RttWr: 1
32735247.091: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
32736247.091: <09>Lane 00 new seed: 004e
32737247.091: <09>Lane 01 new seed: 004d
32738247.091: <09>Lane 02 new seed: 004a
32739247.091: <09>Lane 03 new seed: 0047
32740247.091: <09>Lane 04 new seed: 0046
32741247.091: <09>Lane 05 new seed: 0049
32742247.091: <09>Lane 06 new seed: 004b
32743247.091: <09>Lane 07 new seed: 004e
32744247.091: <09>Lane 08 new seed: 0045
32745247.091: <09>Lane 00 nibble 1 raw readback: 004d
32746247.091: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004d
32747247.091: <09>Lane 00 nibble 1 adjusted value (post nibble): 004d
32748247.091: <09>Lane 01 nibble 1 raw readback: 0048
32749247.091: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0048
32750247.092: <09>Lane 01 nibble 1 adjusted value (post nibble): 004a
32751247.091: <09>Lane 02 nibble 1 raw readback: 0042
32752247.092: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0042
32753247.092: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
32754247.092: <09>Lane 03 nibble 1 raw readback: 003e
32755247.092: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003e
32756247.092: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
32757247.092: <09>Lane 04 nibble 1 raw readback: 003b
32758247.092: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
32759247.092: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
32760247.092: <09>Lane 05 nibble 1 raw readback: 0040
32761247.092: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0040
32762247.092: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
32763247.092: <09>Lane 06 nibble 1 raw readback: 0045
32764247.092: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0045
32765247.092: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
32766247.092: <09>Lane 07 nibble 1 raw readback: 004b
32767247.092: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
32768247.092: <09>Lane 07 nibble 1 adjusted value (post nibble): 004c
32769247.092: <09>Lane 08 nibble 1 raw readback: 0039
32770247.092: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
32771247.092: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
32772247.092: <09>original critical gross delay: 0
32773247.092: <09>new critical gross delay: 0
32774247.092: DIMM 0 RttNom: 3
32775247.092: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32776247.092: DIMM 0 RttNom: 3
32777247.092: DIMM 0 RttWr: 1
32778247.092: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32779247.092: DIMM 0 RttWr: 1
32780247.092: DIMM 0 RttNom: 3
32781247.092: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32782247.092: DIMM 0 RttNom: 3
32783247.092: DIMM 0 RttWr: 1
32784247.092: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32785247.092: DIMM 0 RttWr: 1
32786247.092: DIMM 1 RttNom: 3
32787247.092: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32788247.092: DIMM 0 RttNom: 3
32789247.092: DIMM 1 RttWr: 1
32790247.092: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32791247.092: DIMM 0 RttWr: 1
32792247.092: DIMM 1 RttNom: 3
32793247.092: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32794247.092: DIMM 0 RttNom: 3
32795247.092: DIMM 1 RttWr: 1
32796247.092: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32797247.092: DIMM 0 RttWr: 1
32798247.092: AgesaHwWlPhase1: training nibble 0
32799247.092: DIMM 1 RttNom: 3
32800247.092: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32801247.092: DIMM 1 RttWr: 1
32802247.092: DIMM 1 RttWr: 1
32803247.092: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32804247.092: DIMM 1 RttWr: 1
32805247.092: DIMM 1 RttNom: 3
32806247.092: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32807247.092: DIMM 1 RttNom: 3
32808247.092: DIMM 1 RttWr: 1
32809247.092: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32810247.092: DIMM 1 RttWr: 1
32811247.092: DIMM 0 RttNom: 3
32812247.092: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32813247.092: DIMM 1 RttNom: 3
32814247.093: DIMM 0 RttWr: 1
32815247.093: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32816247.093: DIMM 1 RttWr: 1
32817247.093: DIMM 0 RttNom: 3
32818247.093: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32819247.093: DIMM 1 RttNom: 3
32820247.093: DIMM 0 RttWr: 1
32821247.093: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32822247.093: DIMM 1 RttWr: 1
32823247.093: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
32824247.093: <09>Lane 00 scaled delay: 0052
32825247.093: <09>Lane 00 new seed: 0052
32826247.093: <09>Lane 01 scaled delay: 004f
32827247.093: <09>Lane 01 new seed: 004f
32828247.093: <09>Lane 02 scaled delay: 004d
32829247.093: <09>Lane 02 new seed: 004d
32830247.093: <09>Lane 03 scaled delay: 004b
32831247.093: <09>Lane 03 new seed: 004b
32832247.093: <09>Lane 04 scaled delay: 0049
32833247.093: <09>Lane 04 new seed: 0049
32834247.093: <09>Lane 05 scaled delay: 004b
32835247.093: <09>Lane 05 new seed: 004b
32836247.093: <09>Lane 06 scaled delay: 004e
32837247.093: <09>Lane 06 new seed: 004e
32838247.093: <09>Lane 07 scaled delay: 0051
32839247.093: <09>Lane 07 new seed: 0051
32840247.093: <09>Lane 08 scaled delay: 0049
32841247.093: <09>Lane 08 new seed: 0049
32842247.093: <09>Lane 00 nibble 0 raw readback: 0050
32843247.093: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
32844247.093: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
32845247.093: <09>Lane 01 nibble 0 raw readback: 004e
32846247.093: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
32847247.093: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
32848247.093: <09>Lane 02 nibble 0 raw readback: 0049
32849247.093: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
32850247.093: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
32851247.093: <09>Lane 03 nibble 0 raw readback: 0044
32852247.093: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
32853247.093: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
32854247.093: <09>Lane 04 nibble 0 raw readback: 0042
32855247.093: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
32856247.093: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
32857247.093: <09>Lane 05 nibble 0 raw readback: 0047
32858247.093: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
32859247.093: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
32860247.093: <09>Lane 06 nibble 0 raw readback: 004d
32861247.093: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
32862247.093: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
32863247.093: <09>Lane 07 nibble 0 raw readback: 0050
32864247.093: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
32865247.093: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
32866247.093: <09>Lane 08 nibble 0 raw readback: 003e
32867247.093: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
32868247.093: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
32869247.093: AgesaHwWlPhase1: training nibble 1
32870247.093: DIMM 1 RttNom: 3
32871247.093: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32872247.093: DIMM 1 RttWr: 1
32873247.093: DIMM 1 RttWr: 1
32874247.093: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32875247.093: DIMM 1 RttWr: 1
32876247.093: DIMM 1 RttNom: 3
32877247.093: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32878247.093: DIMM 1 RttNom: 3
32879247.093: DIMM 1 RttWr: 1
32880247.093: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32881247.093: DIMM 1 RttWr: 1
32882247.093: DIMM 0 RttNom: 3
32883247.093: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32884247.093: DIMM 1 RttNom: 3
32885247.094: DIMM 0 RttWr: 1
32886247.094: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32887247.094: DIMM 1 RttWr: 1
32888247.094: DIMM 0 RttNom: 3
32889247.094: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32890247.094: DIMM 1 RttNom: 3
32891247.094: DIMM 0 RttWr: 1
32892247.094: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32893247.094: DIMM 1 RttWr: 1
32894247.094: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
32895247.094: <09>Lane 00 new seed: 0052
32896247.094: <09>Lane 01 new seed: 004f
32897247.094: <09>Lane 02 new seed: 004d
32898247.094: <09>Lane 03 new seed: 004b
32899247.094: <09>Lane 04 new seed: 0049
32900247.094: <09>Lane 05 new seed: 004b
32901247.094: <09>Lane 06 new seed: 004e
32902247.094: <09>Lane 07 new seed: 0051
32903247.094: <09>Lane 08 new seed: 0049
32904247.094: <09>Lane 00 nibble 1 raw readback: 0054
32905247.094: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
32906247.094: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
32907247.094: <09>Lane 01 nibble 1 raw readback: 004e
32908247.094: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
32909247.094: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
32910247.094: <09>Lane 02 nibble 1 raw readback: 0049
32911247.094: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
32912247.094: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
32913247.094: <09>Lane 03 nibble 1 raw readback: 0045
32914247.094: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
32915247.094: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
32916247.094: <09>Lane 04 nibble 1 raw readback: 0040
32917247.094: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
32918247.094: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
32919247.094: <09>Lane 05 nibble 1 raw readback: 0046
32920247.094: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0046
32921247.094: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
32922247.094: <09>Lane 06 nibble 1 raw readback: 004c
32923247.094: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004c
32924247.094: <09>Lane 06 nibble 1 adjusted value (post nibble): 004d
32925247.094: <09>Lane 07 nibble 1 raw readback: 0051
32926247.094: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
32927247.094: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
32928247.094: <09>Lane 08 nibble 1 raw readback: 0040
32929247.094: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
32930247.094: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
32931247.094: <09>original critical gross delay: 0
32932247.094: <09>new critical gross delay: 0
32933247.094: DIMM 1 RttNom: 3
32934247.094: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
32935247.094: DIMM 1 RttNom: 3
32936247.094: DIMM 1 RttWr: 1
32937247.094: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
32938247.094: DIMM 1 RttWr: 1
32939247.094: DIMM 1 RttNom: 3
32940247.094: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
32941247.094: DIMM 1 RttNom: 3
32942247.094: DIMM 1 RttWr: 1
32943247.094: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
32944247.094: DIMM 1 RttWr: 1
32945247.094: DIMM 0 RttNom: 3
32946247.094: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
32947247.094: DIMM 1 RttNom: 3
32948247.094: DIMM 0 RttWr: 1
32949247.094: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
32950247.094: DIMM 1 RttWr: 1
32951247.095: DIMM 0 RttNom: 3
32952247.095: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
32953247.095: DIMM 1 RttNom: 3
32954247.095: DIMM 0 RttWr: 1
32955247.095: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
32956247.095: DIMM 1 RttWr: 1
32957247.095: SetTargetFreq: Start
32958247.095: SetTargetFreq: Node 1: New frequency code: 000e
32959247.095: ChangeMemClk: Start
32960247.095: set_2t_configuration: Start
32961247.095: set_2t_configuration: Done
32962247.095: mct_BeforePlatformSpec: Start
32963247.095: mct_BeforePlatformSpec: Done
32964247.095: mct_PlatformSpec: Start
32965247.095: Programmed DCT 0 timing/termination pattern 00383a38 30222222
32966247.095: mct_PlatformSpec: Done
32967247.095: set_2t_configuration: Start
32968247.095: set_2t_configuration: Done
32969247.095: mct_BeforePlatformSpec: Start
32970247.095: mct_BeforePlatformSpec: Done
32971247.095: mct_PlatformSpec: Start
32972247.095: Programmed DCT 1 timing/termination pattern 00383a38 30222222
32973247.095: mct_PlatformSpec: Done
32974247.095: ChangeMemClk: Done
32975247.095: phyAssistedMemFnceTraining: Start
32976247.095: phyAssistedMemFnceTraining: training node 1 DCT 0
32977247.095: phyAssistedMemFnceTraining: done training node 1 DCT 0
32978247.095: phyAssistedMemFnceTraining: training node 1 DCT 1
32979247.095: phyAssistedMemFnceTraining: done training node 1 DCT 1
32980247.096: phyAssistedMemFnceTraining: Done
32981247.096: InitPhyCompensation: DCT 0: Start
32982247.096: Waiting for predriver calibration to be applied...done!
32983247.096: InitPhyCompensation: DCT 0: Done
32984247.096: phyAssistedMemFnceTraining: Start
32985247.096: phyAssistedMemFnceTraining: training node 1 DCT 0
32986247.096: phyAssistedMemFnceTraining: done training node 1 DCT 0
32987247.096: phyAssistedMemFnceTraining: training node 1 DCT 1
32988247.096: phyAssistedMemFnceTraining: done training node 1 DCT 1
32989247.096: phyAssistedMemFnceTraining: Done
32990247.096: InitPhyCompensation: DCT 1: Start
32991247.096: Waiting for predriver calibration to be applied...done!
32992247.096: InitPhyCompensation: DCT 1: Done
32993247.096: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
32994247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
32995247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
32996247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
32997247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
32998247.096: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
32999247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
33000247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
33001247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
33002247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
33003247.097: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
33004247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33005247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
33006247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33007247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
33008247.097: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
33009247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33010247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
33011247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33012247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
33013247.097: SetTargetFreq: Done
33014247.097: SPD2ndTiming: Start
33015247.097: SPD2ndTiming: Done
33016247.097: mct_BeforeDramInit_Prod_D: Start
33017247.097: mct_ProgramODT_D: Start
33018247.097: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
33019247.097: mct_ProgramODT_D: Done
33020247.097: mct_BeforeDramInit_Prod_D: Done
33021247.097: mct_DramInit_Sw_D: Start
33022247.097: DIMM 0 RttWr: 2
33023247.097: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33024247.097: mct_SendMrsCmd: Start
33025247.097: mct_SendMrsCmd: Done
33026247.097: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
33027247.097: mct_SendMrsCmd: Start
33028247.097: mct_SendMrsCmd: Done
33029247.097: DIMM 0 RttNom: 5
33030247.097: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33031247.097: mct_SendMrsCmd: Start
33032247.097: mct_SendMrsCmd: Done
33033247.097: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
33034247.097: mct_SendMrsCmd: Start
33035247.097: mct_SendMrsCmd: Done
33036247.097: DIMM 0 RttWr: 2
33037247.097: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33038247.097: mct_SendMrsCmd: Start
33039247.097: mct_SendMrsCmd: Done
33040247.098: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
33041247.097: mct_SendMrsCmd: Start
33042247.098: mct_SendMrsCmd: Done
33043247.098: DIMM 0 RttNom: 5
33044247.098: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33045247.098: mct_SendMrsCmd: Start
33046247.098: mct_SendMrsCmd: Done
33047247.098: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
33048247.098: mct_SendMrsCmd: Start
33049247.098: mct_SendMrsCmd: Done
33050247.098: DIMM 1 RttWr: 2
33051247.098: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33052247.098: mct_SendMrsCmd: Start
33053247.098: mct_SendMrsCmd: Done
33054247.098: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
33055247.098: mct_SendMrsCmd: Start
33056247.098: mct_SendMrsCmd: Done
33057247.098: DIMM 1 RttNom: 5
33058247.098: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33059247.098: mct_SendMrsCmd: Start
33060247.098: mct_SendMrsCmd: Done
33061247.098: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
33062247.098: mct_SendMrsCmd: Start
33063247.098: mct_SendMrsCmd: Done
33064247.098: DIMM 1 RttWr: 2
33065247.098: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33066247.098: mct_SendMrsCmd: Start
33067247.098: mct_SendMrsCmd: Done
33068247.098: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
33069247.098: mct_SendMrsCmd: Start
33070247.098: mct_SendMrsCmd: Done
33071247.098: DIMM 1 RttNom: 5
33072247.098: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33073247.098: mct_SendMrsCmd: Start
33074247.098: mct_SendMrsCmd: Done
33075247.098: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
33076247.098: mct_SendMrsCmd: Start
33077247.098: mct_SendMrsCmd: Done
33078247.098: mct_DramInit_Sw_D: Done
33079247.098: AgesaHwWlPhase1: training nibble 0
33080247.098: DIMM 0 RttNom: 5
33081247.098: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33082247.098: DIMM 0 RttWr: 2
33083247.098: DIMM 0 RttWr: 2
33084247.098: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33085247.098: DIMM 0 RttWr: 2
33086247.098: DIMM 0 RttNom: 5
33087247.098: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33088247.098: DIMM 0 RttNom: 5
33089247.098: DIMM 0 RttWr: 2
33090247.098: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33091247.098: DIMM 0 RttWr: 2
33092247.098: DIMM 1 RttNom: 5
33093247.098: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33094247.098: DIMM 0 RttNom: 5
33095247.098: DIMM 1 RttWr: 2
33096247.098: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33097247.098: DIMM 0 RttWr: 2
33098247.098: DIMM 1 RttNom: 5
33099247.098: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33100247.099: DIMM 0 RttNom: 5
33101247.099: DIMM 1 RttWr: 2
33102247.099: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33103247.099: DIMM 0 RttWr: 2
33104247.099: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
33105247.099: <09>Lane 00 scaled delay: 0055
33106247.099: <09>Lane 00 new seed: 0055
33107247.099: <09>Lane 01 scaled delay: 0050
33108247.099: <09>Lane 01 new seed: 0050
33109247.099: <09>Lane 02 scaled delay: 004d
33110247.099: <09>Lane 02 new seed: 004d
33111247.099: <09>Lane 03 scaled delay: 004b
33112247.099: <09>Lane 03 new seed: 004b
33113247.099: <09>Lane 04 scaled delay: 0046
33114247.099: <09>Lane 04 new seed: 0046
33115247.099: <09>Lane 05 scaled delay: 004d
33116247.099: <09>Lane 05 new seed: 004d
33117247.099: <09>Lane 06 scaled delay: 004f
33118247.099: <09>Lane 06 new seed: 004f
33119247.099: <09>Lane 07 scaled delay: 0053
33120247.099: <09>Lane 07 new seed: 0053
33121247.099: <09>Lane 08 scaled delay: 0044
33122247.099: <09>Lane 08 new seed: 0044
33123247.099: <09>Lane 00 nibble 0 raw readback: 0056
33124247.099: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0056
33125247.099: <09>Lane 00 nibble 0 adjusted value (post nibble): 0056
33126247.099: <09>Lane 01 nibble 0 raw readback: 004f
33127247.099: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
33128247.099: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
33129247.099: <09>Lane 02 nibble 0 raw readback: 0049
33130247.099: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
33131247.099: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
33132247.099: <09>Lane 03 nibble 0 raw readback: 0047
33133247.099: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
33134247.099: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
33135247.099: <09>Lane 04 nibble 0 raw readback: 0042
33136247.099: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
33137247.099: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
33138247.099: <09>Lane 05 nibble 0 raw readback: 0048
33139247.099: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
33140247.099: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
33141247.099: <09>Lane 06 nibble 0 raw readback: 004b
33142247.099: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
33143247.099: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
33144247.099: <09>Lane 07 nibble 0 raw readback: 0050
33145247.099: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
33146247.099: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
33147247.099: <09>Lane 08 nibble 0 raw readback: 003e
33148247.099: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
33149247.099: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
33150247.099: AgesaHwWlPhase1: training nibble 1
33151247.099: DIMM 0 RttNom: 5
33152247.099: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33153247.099: DIMM 0 RttWr: 2
33154247.100: DIMM 0 RttWr: 2
33155247.100: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33156247.100: DIMM 0 RttWr: 2
33157247.100: DIMM 0 RttNom: 5
33158247.100: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33159247.100: DIMM 0 RttNom: 5
33160247.100: DIMM 0 RttWr: 2
33161247.100: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33162247.100: DIMM 0 RttWr: 2
33163247.100: DIMM 1 RttNom: 5
33164247.100: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33165247.100: DIMM 0 RttNom: 5
33166247.100: DIMM 1 RttWr: 2
33167247.100: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33168247.100: DIMM 0 RttWr: 2
33169247.100: DIMM 1 RttNom: 5
33170247.100: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33171247.100: DIMM 0 RttNom: 5
33172247.100: DIMM 1 RttWr: 2
33173247.100: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33174247.100: DIMM 0 RttWr: 2
33175247.100: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
33176247.100: <09>Lane 00 new seed: 0055
33177247.100: <09>Lane 01 new seed: 0050
33178247.100: <09>Lane 02 new seed: 004d
33179247.100: <09>Lane 03 new seed: 004b
33180247.100: <09>Lane 04 new seed: 0046
33181247.100: <09>Lane 05 new seed: 004d
33182247.100: <09>Lane 06 new seed: 004f
33183247.100: <09>Lane 07 new seed: 0053
33184247.100: <09>Lane 08 new seed: 0044
33185247.100: <09>Lane 00 nibble 1 raw readback: 0054
33186247.100: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
33187247.100: <09>Lane 00 nibble 1 adjusted value (post nibble): 0054
33188247.100: <09>Lane 01 nibble 1 raw readback: 004e
33189247.100: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
33190247.100: <09>Lane 01 nibble 1 adjusted value (post nibble): 004f
33191247.100: <09>Lane 02 nibble 1 raw readback: 0049
33192247.100: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
33193247.100: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
33194247.100: <09>Lane 03 nibble 1 raw readback: 0047
33195247.100: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
33196247.100: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
33197247.100: <09>Lane 04 nibble 1 raw readback: 0041
33198247.100: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
33199247.100: <09>Lane 04 nibble 1 adjusted value (post nibble): 0043
33200247.100: <09>Lane 05 nibble 1 raw readback: 0047
33201247.100: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
33202247.100: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
33203247.100: <09>Lane 06 nibble 1 raw readback: 004a
33204247.100: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
33205247.100: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
33206247.100: <09>Lane 07 nibble 1 raw readback: 004f
33207247.100: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004f
33208247.100: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
33209247.100: <09>Lane 08 nibble 1 raw readback: 003d
33210247.100: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
33211247.100: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
33212247.100: <09>original critical gross delay: 0
33213247.100: <09>new critical gross delay: 0
33214247.101: DIMM 0 RttNom: 5
33215247.100: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33216247.101: DIMM 0 RttNom: 5
33217247.101: DIMM 0 RttWr: 2
33218247.101: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33219247.101: DIMM 0 RttWr: 2
33220247.101: DIMM 0 RttNom: 5
33221247.101: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33222247.101: DIMM 0 RttNom: 5
33223247.101: DIMM 0 RttWr: 2
33224247.101: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33225247.101: DIMM 0 RttWr: 2
33226247.101: DIMM 1 RttNom: 5
33227247.101: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33228247.101: DIMM 0 RttNom: 5
33229247.101: DIMM 1 RttWr: 2
33230247.101: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33231247.101: DIMM 0 RttWr: 2
33232247.101: DIMM 1 RttNom: 5
33233247.101: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33234247.101: DIMM 0 RttNom: 5
33235247.101: DIMM 1 RttWr: 2
33236247.101: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33237247.101: DIMM 0 RttWr: 2
33238247.101: AgesaHwWlPhase1: training nibble 0
33239247.101: DIMM 1 RttNom: 5
33240247.101: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33241247.101: DIMM 1 RttWr: 2
33242247.101: DIMM 1 RttWr: 2
33243247.101: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33244247.101: DIMM 1 RttWr: 2
33245247.101: DIMM 1 RttNom: 5
33246247.101: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33247247.101: DIMM 1 RttNom: 5
33248247.101: DIMM 1 RttWr: 2
33249247.101: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33250247.101: DIMM 1 RttWr: 2
33251247.101: DIMM 0 RttNom: 5
33252247.101: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33253247.101: DIMM 1 RttNom: 5
33254247.101: DIMM 0 RttWr: 2
33255247.101: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33256247.101: DIMM 1 RttWr: 2
33257247.101: DIMM 0 RttNom: 5
33258247.101: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33259247.101: DIMM 1 RttNom: 5
33260247.101: DIMM 0 RttWr: 2
33261247.101: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33262247.101: DIMM 1 RttWr: 2
33263247.101: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
33264247.101: <09>Lane 00 scaled delay: 005d
33265247.101: <09>Lane 00 new seed: 005d
33266247.101: <09>Lane 01 scaled delay: 0057
33267247.101: <09>Lane 01 new seed: 0057
33268247.101: <09>Lane 02 scaled delay: 0054
33269247.101: <09>Lane 02 new seed: 0054
33270247.101: <09>Lane 03 scaled delay: 0052
33271247.101: <09>Lane 03 new seed: 0052
33272247.101: <09>Lane 04 scaled delay: 004d
33273247.101: <09>Lane 04 new seed: 004d
33274247.101: <09>Lane 05 scaled delay: 0052
33275247.101: <09>Lane 05 new seed: 0052
33276247.101: <09>Lane 06 scaled delay: 0055
33277247.101: <09>Lane 06 new seed: 0055
33278247.101: <09>Lane 07 scaled delay: 0059
33279247.101: <09>Lane 07 new seed: 0059
33280247.101: <09>Lane 08 scaled delay: 004d
33281247.101: <09>Lane 08 new seed: 004d
33282247.102: <09>Lane 00 nibble 0 raw readback: 005e
33283247.102: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
33284247.102: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
33285247.102: <09>Lane 01 nibble 0 raw readback: 0056
33286247.102: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
33287247.102: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
33288247.102: <09>Lane 02 nibble 0 raw readback: 004f
33289247.102: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
33290247.102: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
33291247.102: <09>Lane 03 nibble 0 raw readback: 004e
33292247.102: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
33293247.102: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
33294247.102: <09>Lane 04 nibble 0 raw readback: 004a
33295247.102: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
33296247.102: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
33297247.102: <09>Lane 05 nibble 0 raw readback: 0051
33298247.102: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
33299247.102: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
33300247.102: <09>Lane 06 nibble 0 raw readback: 0051
33301247.102: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
33302247.102: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
33303247.102: <09>Lane 07 nibble 0 raw readback: 0059
33304247.102: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
33305247.102: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
33306247.102: <09>Lane 08 nibble 0 raw readback: 0045
33307247.102: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
33308247.102: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
33309247.102: AgesaHwWlPhase1: training nibble 1
33310247.102: DIMM 1 RttNom: 5
33311247.102: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33312247.102: DIMM 1 RttWr: 2
33313247.102: DIMM 1 RttWr: 2
33314247.102: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33315247.102: DIMM 1 RttWr: 2
33316247.102: DIMM 1 RttNom: 5
33317247.102: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33318247.102: DIMM 1 RttNom: 5
33319247.102: DIMM 1 RttWr: 2
33320247.102: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33321247.102: DIMM 1 RttWr: 2
33322247.102: DIMM 0 RttNom: 5
33323247.102: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33324247.102: DIMM 1 RttNom: 5
33325247.102: DIMM 0 RttWr: 2
33326247.102: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33327247.102: DIMM 1 RttWr: 2
33328247.102: DIMM 0 RttNom: 5
33329247.102: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33330247.102: DIMM 1 RttNom: 5
33331247.102: DIMM 0 RttWr: 2
33332247.102: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33333247.102: DIMM 1 RttWr: 2
33334247.102: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
33335247.102: <09>Lane 00 new seed: 005d
33336247.102: <09>Lane 01 new seed: 0057
33337247.102: <09>Lane 02 new seed: 0054
33338247.102: <09>Lane 03 new seed: 0052
33339247.102: <09>Lane 04 new seed: 004d
33340247.102: <09>Lane 05 new seed: 0052
33341247.102: <09>Lane 06 new seed: 0055
33342247.102: <09>Lane 07 new seed: 0059
33343247.102: <09>Lane 08 new seed: 004d
33344247.102: <09>Lane 00 nibble 1 raw readback: 005e
33345247.102: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005e
33346247.102: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
33347247.102: <09>Lane 01 nibble 1 raw readback: 0055
33348247.102: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
33349247.102: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
33350247.102: <09>Lane 02 nibble 1 raw readback: 004f
33351247.103: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004f
33352247.102: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
33353247.103: <09>Lane 03 nibble 1 raw readback: 004d
33354247.102: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
33355247.103: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
33356247.103: <09>Lane 04 nibble 1 raw readback: 0048
33357247.103: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
33358247.103: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
33359247.103: <09>Lane 05 nibble 1 raw readback: 004e
33360247.103: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004e
33361247.103: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
33362247.103: <09>Lane 06 nibble 1 raw readback: 0051
33363247.103: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0051
33364247.103: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
33365247.103: <09>Lane 07 nibble 1 raw readback: 0058
33366247.103: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0058
33367247.103: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
33368247.103: <09>Lane 08 nibble 1 raw readback: 0047
33369247.103: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0047
33370247.103: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
33371247.103: <09>original critical gross delay: 0
33372247.103: <09>new critical gross delay: 0
33373247.103: DIMM 1 RttNom: 5
33374247.103: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
33375247.103: DIMM 1 RttNom: 5
33376247.103: DIMM 1 RttWr: 2
33377247.103: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
33378247.103: DIMM 1 RttWr: 2
33379247.103: DIMM 1 RttNom: 5
33380247.103: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
33381247.103: DIMM 1 RttNom: 5
33382247.103: DIMM 1 RttWr: 2
33383247.103: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
33384247.103: DIMM 1 RttWr: 2
33385247.103: DIMM 0 RttNom: 5
33386247.103: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
33387247.103: DIMM 1 RttNom: 5
33388247.103: DIMM 0 RttWr: 2
33389247.103: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
33390247.103: DIMM 1 RttWr: 2
33391247.103: DIMM 0 RttNom: 5
33392247.103: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
33393247.103: DIMM 1 RttNom: 5
33394247.103: DIMM 0 RttWr: 2
33395247.103: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
33396247.103: DIMM 1 RttWr: 2
33397247.103: SPD2ndTiming: Start
33398247.104: SPD2ndTiming: Done
33399247.104: mct_BeforeDramInit_Prod_D: Start
33400247.104: mct_ProgramODT_D: Start
33401247.104: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
33402247.104: mct_ProgramODT_D: Done
33403247.104: mct_BeforeDramInit_Prod_D: Done
33404247.104: mct_DramInit_Sw_D: Start
33405247.104: DIMM 0 RttWr: 2
33406247.104: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33407247.104: mct_SendMrsCmd: Start
33408247.104: mct_SendMrsCmd: Done
33409247.104: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
33410247.104: mct_SendMrsCmd: Start
33411247.104: mct_SendMrsCmd: Done
33412247.104: DIMM 0 RttNom: 5
33413247.104: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33414247.104: mct_SendMrsCmd: Start
33415247.104: mct_SendMrsCmd: Done
33416247.104: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
33417247.104: mct_SendMrsCmd: Start
33418247.104: mct_SendMrsCmd: Done
33419247.104: DIMM 0 RttWr: 2
33420247.104: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33421247.104: mct_SendMrsCmd: Start
33422247.104: mct_SendMrsCmd: Done
33423247.104: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
33424247.104: mct_SendMrsCmd: Start
33425247.104: mct_SendMrsCmd: Done
33426247.104: DIMM 0 RttNom: 5
33427247.104: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33428247.104: mct_SendMrsCmd: Start
33429247.104: mct_SendMrsCmd: Done
33430247.104: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
33431247.104: mct_SendMrsCmd: Start
33432247.104: mct_SendMrsCmd: Done
33433247.104: DIMM 1 RttWr: 2
33434247.104: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33435247.104: mct_SendMrsCmd: Start
33436247.104: mct_SendMrsCmd: Done
33437247.104: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
33438247.104: mct_SendMrsCmd: Start
33439247.104: mct_SendMrsCmd: Done
33440247.104: DIMM 1 RttNom: 5
33441247.104: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33442247.104: mct_SendMrsCmd: Start
33443247.104: mct_SendMrsCmd: Done
33444247.104: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
33445247.104: mct_SendMrsCmd: Start
33446247.104: mct_SendMrsCmd: Done
33447247.104: DIMM 1 RttWr: 2
33448247.104: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33449247.104: mct_SendMrsCmd: Start
33450247.104: mct_SendMrsCmd: Done
33451247.104: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
33452247.104: mct_SendMrsCmd: Start
33453247.104: mct_SendMrsCmd: Done
33454247.104: DIMM 1 RttNom: 5
33455247.104: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33456247.104: mct_SendMrsCmd: Start
33457247.104: mct_SendMrsCmd: Done
33458247.104: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
33459247.105: mct_SendMrsCmd: Start
33460247.105: mct_SendMrsCmd: Done
33461247.105: mct_DramInit_Sw_D: Done
33462247.105: AgesaHwWlPhase1: training nibble 0
33463247.105: DIMM 0 RttNom: 5
33464247.105: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33465247.105: DIMM 0 RttWr: 2
33466247.105: DIMM 0 RttWr: 2
33467247.105: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33468247.105: DIMM 0 RttWr: 2
33469247.105: DIMM 0 RttNom: 5
33470247.105: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33471247.105: DIMM 0 RttNom: 5
33472247.105: DIMM 0 RttWr: 2
33473247.105: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33474247.105: DIMM 0 RttWr: 2
33475247.105: DIMM 1 RttNom: 5
33476247.105: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33477247.105: DIMM 0 RttNom: 5
33478247.105: DIMM 1 RttWr: 2
33479247.105: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33480247.105: DIMM 0 RttWr: 2
33481247.105: DIMM 1 RttNom: 5
33482247.105: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33483247.105: DIMM 0 RttNom: 5
33484247.105: DIMM 1 RttWr: 2
33485247.105: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33486247.105: DIMM 0 RttWr: 2
33487247.105: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
33488247.105: <09>Lane 00 scaled delay: 0058
33489247.105: <09>Lane 00 new seed: 0058
33490247.105: <09>Lane 01 scaled delay: 0054
33491247.105: <09>Lane 01 new seed: 0054
33492247.105: <09>Lane 02 scaled delay: 004f
33493247.105: <09>Lane 02 new seed: 004f
33494247.105: <09>Lane 03 scaled delay: 004a
33495247.105: <09>Lane 03 new seed: 004a
33496247.105: <09>Lane 04 scaled delay: 0048
33497247.105: <09>Lane 04 new seed: 0048
33498247.105: <09>Lane 05 scaled delay: 004d
33499247.105: <09>Lane 05 new seed: 004d
33500247.105: <09>Lane 06 scaled delay: 0052
33501247.105: <09>Lane 06 new seed: 0052
33502247.105: <09>Lane 07 scaled delay: 0057
33503247.105: <09>Lane 07 new seed: 0057
33504247.105: <09>Lane 08 scaled delay: 0046
33505247.105: <09>Lane 08 new seed: 0046
33506247.105: <09>Lane 00 nibble 0 raw readback: 0058
33507247.105: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0058
33508247.105: <09>Lane 00 nibble 0 adjusted value (post nibble): 0058
33509247.106: <09>Lane 01 nibble 0 raw readback: 0050
33510247.106: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0050
33511247.106: <09>Lane 01 nibble 0 adjusted value (post nibble): 0050
33512247.106: <09>Lane 02 nibble 0 raw readback: 004d
33513247.106: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004d
33514247.106: <09>Lane 02 nibble 0 adjusted value (post nibble): 004d
33515247.106: <09>Lane 03 nibble 0 raw readback: 0047
33516247.106: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
33517247.106: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
33518247.106: <09>Lane 04 nibble 0 raw readback: 0043
33519247.106: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
33520247.106: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
33521247.106: <09>Lane 05 nibble 0 raw readback: 004b
33522247.106: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004b
33523247.106: <09>Lane 05 nibble 0 adjusted value (post nibble): 004b
33524247.106: <09>Lane 06 nibble 0 raw readback: 004e
33525247.106: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
33526247.106: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
33527247.106: <09>Lane 07 nibble 0 raw readback: 0055
33528247.106: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0055
33529247.106: <09>Lane 07 nibble 0 adjusted value (post nibble): 0055
33530247.106: <09>Lane 08 nibble 0 raw readback: 0041
33531247.106: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
33532247.106: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
33533247.106: AgesaHwWlPhase1: training nibble 1
33534247.106: DIMM 0 RttNom: 5
33535247.106: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33536247.106: DIMM 0 RttWr: 2
33537247.106: DIMM 0 RttWr: 2
33538247.106: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33539247.106: DIMM 0 RttWr: 2
33540247.106: DIMM 0 RttNom: 5
33541247.106: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33542247.106: DIMM 0 RttNom: 5
33543247.106: DIMM 0 RttWr: 2
33544247.106: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33545247.106: DIMM 0 RttWr: 2
33546247.106: DIMM 1 RttNom: 5
33547247.106: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33548247.106: DIMM 0 RttNom: 5
33549247.106: DIMM 1 RttWr: 2
33550247.106: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33551247.106: DIMM 0 RttWr: 2
33552247.106: DIMM 1 RttNom: 5
33553247.106: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33554247.106: DIMM 0 RttNom: 5
33555247.106: DIMM 1 RttWr: 2
33556247.106: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33557247.106: DIMM 0 RttWr: 2
33558247.106: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
33559247.106: <09>Lane 00 new seed: 0058
33560247.106: <09>Lane 01 new seed: 0054
33561247.106: <09>Lane 02 new seed: 004f
33562247.106: <09>Lane 03 new seed: 004a
33563247.106: <09>Lane 04 new seed: 0048
33564247.106: <09>Lane 05 new seed: 004d
33565247.106: <09>Lane 06 new seed: 0052
33566247.106: <09>Lane 07 new seed: 0057
33567247.106: <09>Lane 08 new seed: 0046
33568247.106: <09>Lane 00 nibble 1 raw readback: 0058
33569247.106: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0058
33570247.106: <09>Lane 00 nibble 1 adjusted value (post nibble): 0058
33571247.106: <09>Lane 01 nibble 1 raw readback: 0051
33572247.106: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0051
33573247.106: <09>Lane 01 nibble 1 adjusted value (post nibble): 0052
33574247.106: <09>Lane 02 nibble 1 raw readback: 004c
33575247.106: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004c
33576247.106: <09>Lane 02 nibble 1 adjusted value (post nibble): 004d
33577247.107: <09>Lane 03 nibble 1 raw readback: 0048
33578247.106: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0048
33579247.106: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
33580247.106: <09>Lane 04 nibble 1 raw readback: 0042
33581247.107: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
33582247.107: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
33583247.107: <09>Lane 05 nibble 1 raw readback: 004a
33584247.107: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004a
33585247.107: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
33586247.107: <09>Lane 06 nibble 1 raw readback: 004f
33587247.107: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
33588247.107: <09>Lane 06 nibble 1 adjusted value (post nibble): 0050
33589247.107: <09>Lane 07 nibble 1 raw readback: 0056
33590247.107: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0056
33591247.107: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
33592247.107: <09>Lane 08 nibble 1 raw readback: 0040
33593247.107: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
33594247.107: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
33595247.107: <09>original critical gross delay: 0
33596247.107: <09>new critical gross delay: 0
33597247.107: DIMM 0 RttNom: 5
33598247.107: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33599247.107: DIMM 0 RttNom: 5
33600247.107: DIMM 0 RttWr: 2
33601247.107: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33602247.107: DIMM 0 RttWr: 2
33603247.107: DIMM 0 RttNom: 5
33604247.107: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33605247.107: DIMM 0 RttNom: 5
33606247.107: DIMM 0 RttWr: 2
33607247.107: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33608247.107: DIMM 0 RttWr: 2
33609247.107: DIMM 1 RttNom: 5
33610247.107: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33611247.107: DIMM 0 RttNom: 5
33612247.107: DIMM 1 RttWr: 2
33613247.107: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33614247.107: DIMM 0 RttWr: 2
33615247.107: DIMM 1 RttNom: 5
33616247.107: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33617247.107: DIMM 0 RttNom: 5
33618247.107: DIMM 1 RttWr: 2
33619247.107: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33620247.107: DIMM 0 RttWr: 2
33621247.107: AgesaHwWlPhase1: training nibble 0
33622247.107: DIMM 1 RttNom: 5
33623247.107: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33624247.107: DIMM 1 RttWr: 2
33625247.107: DIMM 1 RttWr: 2
33626247.107: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33627247.107: DIMM 1 RttWr: 2
33628247.107: DIMM 1 RttNom: 5
33629247.107: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33630247.107: DIMM 1 RttNom: 5
33631247.107: DIMM 1 RttWr: 2
33632247.107: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33633247.107: DIMM 1 RttWr: 2
33634247.107: DIMM 0 RttNom: 5
33635247.107: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33636247.107: DIMM 1 RttNom: 5
33637247.107: DIMM 0 RttWr: 2
33638247.107: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33639247.107: DIMM 1 RttWr: 2
33640247.108: DIMM 0 RttNom: 5
33641247.108: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33642247.108: DIMM 1 RttNom: 5
33643247.108: DIMM 0 RttWr: 2
33644247.108: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33645247.108: DIMM 1 RttWr: 2
33646247.108: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
33647247.108: <09>Lane 00 scaled delay: 005f
33648247.108: <09>Lane 00 new seed: 005f
33649247.108: <09>Lane 01 scaled delay: 0059
33650247.108: <09>Lane 01 new seed: 0059
33651247.108: <09>Lane 02 scaled delay: 0055
33652247.108: <09>Lane 02 new seed: 0055
33653247.108: <09>Lane 03 scaled delay: 0052
33654247.108: <09>Lane 03 new seed: 0052
33655247.108: <09>Lane 04 scaled delay: 004d
33656247.108: <09>Lane 04 new seed: 004d
33657247.108: <09>Lane 05 scaled delay: 0052
33658247.108: <09>Lane 05 new seed: 0052
33659247.108: <09>Lane 06 scaled delay: 0058
33660247.108: <09>Lane 06 new seed: 0058
33661247.108: <09>Lane 07 scaled delay: 005d
33662247.108: <09>Lane 07 new seed: 005d
33663247.108: <09>Lane 08 scaled delay: 004d
33664247.108: <09>Lane 08 new seed: 004d
33665247.108: <09>Lane 00 nibble 0 raw readback: 005c
33666247.108: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
33667247.108: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
33668247.108: <09>Lane 01 nibble 0 raw readback: 0059
33669247.108: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
33670247.108: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
33671247.108: <09>Lane 02 nibble 0 raw readback: 0053
33672247.108: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
33673247.108: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
33674247.108: <09>Lane 03 nibble 0 raw readback: 004d
33675247.108: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
33676247.108: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
33677247.108: <09>Lane 04 nibble 0 raw readback: 004a
33678247.108: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
33679247.108: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
33680247.108: <09>Lane 05 nibble 0 raw readback: 0051
33681247.108: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
33682247.108: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
33683247.108: <09>Lane 06 nibble 0 raw readback: 0058
33684247.108: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
33685247.108: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
33686247.108: <09>Lane 07 nibble 0 raw readback: 005b
33687247.108: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
33688247.108: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
33689247.108: <09>Lane 08 nibble 0 raw readback: 0047
33690247.108: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
33691247.108: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
33692247.108: AgesaHwWlPhase1: training nibble 1
33693247.108: DIMM 1 RttNom: 5
33694247.108: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33695247.108: DIMM 1 RttWr: 2
33696247.108: DIMM 1 RttWr: 2
33697247.108: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33698247.108: DIMM 1 RttWr: 2
33699247.108: DIMM 1 RttNom: 5
33700247.108: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33701247.108: DIMM 1 RttNom: 5
33702247.108: DIMM 1 RttWr: 2
33703247.108: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33704247.108: DIMM 1 RttWr: 2
33705247.108: DIMM 0 RttNom: 5
33706247.108: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33707247.108: DIMM 1 RttNom: 5
33708247.108: DIMM 0 RttWr: 2
33709247.108: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33710247.108: DIMM 1 RttWr: 2
33711247.108: DIMM 0 RttNom: 5
33712247.108: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33713247.109: DIMM 1 RttNom: 5
33714247.109: DIMM 0 RttWr: 2
33715247.109: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33716247.109: DIMM 1 RttWr: 2
33717247.109: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
33718247.109: <09>Lane 00 new seed: 005f
33719247.109: <09>Lane 01 new seed: 0059
33720247.109: <09>Lane 02 new seed: 0055
33721247.109: <09>Lane 03 new seed: 0052
33722247.109: <09>Lane 04 new seed: 004d
33723247.109: <09>Lane 05 new seed: 0052
33724247.109: <09>Lane 06 new seed: 0058
33725247.109: <09>Lane 07 new seed: 005d
33726247.109: <09>Lane 08 new seed: 004d
33727247.109: <09>Lane 00 nibble 1 raw readback: 005f
33728247.109: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
33729247.109: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
33730247.109: <09>Lane 01 nibble 1 raw readback: 005a
33731247.109: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005a
33732247.109: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
33733247.109: <09>Lane 02 nibble 1 raw readback: 0053
33734247.109: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0053
33735247.109: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
33736247.109: <09>Lane 03 nibble 1 raw readback: 004e
33737247.109: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
33738247.109: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
33739247.109: <09>Lane 04 nibble 1 raw readback: 0049
33740247.109: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
33741247.109: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
33742247.109: <09>Lane 05 nibble 1 raw readback: 004f
33743247.109: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
33744247.109: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
33745247.109: <09>Lane 06 nibble 1 raw readback: 0057
33746247.109: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0057
33747247.109: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
33748247.109: <09>Lane 07 nibble 1 raw readback: 005d
33749247.109: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
33750247.109: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
33751247.109: <09>Lane 08 nibble 1 raw readback: 0048
33752247.109: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
33753247.109: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
33754247.109: <09>original critical gross delay: 0
33755247.109: <09>new critical gross delay: 0
33756247.109: DIMM 1 RttNom: 5
33757247.109: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
33758247.109: DIMM 1 RttNom: 5
33759247.109: DIMM 1 RttWr: 2
33760247.109: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
33761247.109: DIMM 1 RttWr: 2
33762247.109: DIMM 1 RttNom: 5
33763247.109: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
33764247.109: DIMM 1 RttNom: 5
33765247.109: DIMM 1 RttWr: 2
33766247.109: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
33767247.109: DIMM 1 RttWr: 2
33768247.109: DIMM 0 RttNom: 5
33769247.109: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
33770247.109: DIMM 1 RttNom: 5
33771247.109: DIMM 0 RttWr: 2
33772247.109: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
33773247.109: DIMM 1 RttWr: 2
33774247.109: DIMM 0 RttNom: 5
33775247.109: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
33776247.109: DIMM 1 RttNom: 5
33777247.109: DIMM 0 RttWr: 2
33778247.110: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
33779247.110: DIMM 1 RttWr: 2
33780247.110: SetTargetFreq: Start
33781247.110: SetTargetFreq: Node 1: New frequency code: 0012
33782247.110: ChangeMemClk: Start
33783247.110: set_2t_configuration: Start
33784247.110: set_2t_configuration: Done
33785247.110: mct_BeforePlatformSpec: Start
33786247.110: mct_BeforePlatformSpec: Done
33787247.110: mct_PlatformSpec: Start
33788247.110: Programmed DCT 0 timing/termination pattern 00353935 30222222
33789247.110: mct_PlatformSpec: Done
33790247.110: set_2t_configuration: Start
33791247.110: set_2t_configuration: Done
33792247.110: mct_BeforePlatformSpec: Start
33793247.110: mct_BeforePlatformSpec: Done
33794247.110: mct_PlatformSpec: Start
33795247.110: Programmed DCT 1 timing/termination pattern 00353935 30222222
33796247.110: mct_PlatformSpec: Done
33797247.110: ChangeMemClk: Done
33798247.110: phyAssistedMemFnceTraining: Start
33799247.110: phyAssistedMemFnceTraining: training node 1 DCT 0
33800247.110: phyAssistedMemFnceTraining: done training node 1 DCT 0
33801247.110: phyAssistedMemFnceTraining: training node 1 DCT 1
33802247.110: phyAssistedMemFnceTraining: done training node 1 DCT 1
33803247.110: phyAssistedMemFnceTraining: Done
33804247.110: InitPhyCompensation: DCT 0: Start
33805247.111: Waiting for predriver calibration to be applied...done!
33806247.111: InitPhyCompensation: DCT 0: Done
33807247.111: phyAssistedMemFnceTraining: Start
33808247.111: phyAssistedMemFnceTraining: training node 1 DCT 0
33809247.111: phyAssistedMemFnceTraining: done training node 1 DCT 0
33810247.111: phyAssistedMemFnceTraining: training node 1 DCT 1
33811247.111: phyAssistedMemFnceTraining: done training node 1 DCT 1
33812247.111: phyAssistedMemFnceTraining: Done
33813247.111: InitPhyCompensation: DCT 1: Start
33814247.111: Waiting for predriver calibration to be applied...done!
33815247.111: InitPhyCompensation: DCT 1: Done
33816247.111: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
33817247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
33818247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
33819247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
33820247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
33821247.111: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
33822247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
33823247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
33824247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
33825247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
33826247.111: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
33827247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33828247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
33829247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33830247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
33831247.111: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
33832247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33833247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
33834247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
33835247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
33836247.112: SetTargetFreq: Done
33837247.112: SPD2ndTiming: Start
33838247.112: SPD2ndTiming: Done
33839247.112: mct_BeforeDramInit_Prod_D: Start
33840247.112: mct_ProgramODT_D: Start
33841247.112: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
33842247.112: mct_ProgramODT_D: Done
33843247.112: mct_BeforeDramInit_Prod_D: Done
33844247.112: mct_DramInit_Sw_D: Start
33845247.112: DIMM 0 RttWr: 1
33846247.112: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
33847247.112: mct_SendMrsCmd: Start
33848247.112: mct_SendMrsCmd: Done
33849247.112: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
33850247.112: mct_SendMrsCmd: Start
33851247.112: mct_SendMrsCmd: Done
33852247.112: DIMM 0 RttNom: 4
33853247.112: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
33854247.112: mct_SendMrsCmd: Start
33855247.112: mct_SendMrsCmd: Done
33856247.112: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
33857247.112: mct_SendMrsCmd: Start
33858247.112: mct_SendMrsCmd: Done
33859247.112: DIMM 0 RttWr: 1
33860247.112: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
33861247.112: mct_SendMrsCmd: Start
33862247.112: mct_SendMrsCmd: Done
33863247.112: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
33864247.112: mct_SendMrsCmd: Start
33865247.112: mct_SendMrsCmd: Done
33866247.112: DIMM 0 RttNom: 4
33867247.112: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
33868247.112: mct_SendMrsCmd: Start
33869247.112: mct_SendMrsCmd: Done
33870247.112: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
33871247.112: mct_SendMrsCmd: Start
33872247.112: mct_SendMrsCmd: Done
33873247.112: DIMM 1 RttWr: 1
33874247.113: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
33875247.112: mct_SendMrsCmd: Start
33876247.112: mct_SendMrsCmd: Done
33877247.112: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
33878247.113: mct_SendMrsCmd: Start
33879247.113: mct_SendMrsCmd: Done
33880247.113: DIMM 1 RttNom: 4
33881247.113: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
33882247.113: mct_SendMrsCmd: Start
33883247.113: mct_SendMrsCmd: Done
33884247.113: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
33885247.113: mct_SendMrsCmd: Start
33886247.113: mct_SendMrsCmd: Done
33887247.113: DIMM 1 RttWr: 1
33888247.113: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
33889247.113: mct_SendMrsCmd: Start
33890247.113: mct_SendMrsCmd: Done
33891247.113: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
33892247.113: mct_SendMrsCmd: Start
33893247.113: mct_SendMrsCmd: Done
33894247.113: DIMM 1 RttNom: 4
33895247.113: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
33896247.113: mct_SendMrsCmd: Start
33897247.113: mct_SendMrsCmd: Done
33898247.113: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
33899247.113: mct_SendMrsCmd: Start
33900247.113: mct_SendMrsCmd: Done
33901247.113: mct_DramInit_Sw_D: Done
33902247.113: AgesaHwWlPhase1: training nibble 0
33903247.113: DIMM 0 RttNom: 4
33904247.113: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
33905247.113: DIMM 0 RttWr: 1
33906247.113: DIMM 0 RttWr: 1
33907247.113: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
33908247.113: DIMM 0 RttWr: 1
33909247.113: DIMM 0 RttNom: 4
33910247.113: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
33911247.113: DIMM 0 RttNom: 4
33912247.113: DIMM 0 RttWr: 1
33913247.113: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
33914247.113: DIMM 0 RttWr: 1
33915247.113: DIMM 1 RttNom: 4
33916247.113: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
33917247.113: DIMM 0 RttNom: 4
33918247.113: DIMM 1 RttWr: 1
33919247.113: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
33920247.113: DIMM 0 RttWr: 1
33921247.113: DIMM 1 RttNom: 4
33922247.113: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
33923247.113: DIMM 0 RttNom: 4
33924247.113: DIMM 1 RttWr: 1
33925247.113: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
33926247.113: DIMM 0 RttWr: 1
33927247.113: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
33928247.114: <09>Lane 00 scaled delay: 005e
33929247.114: <09>Lane 00 new seed: 005e
33930247.114: <09>Lane 01 scaled delay: 0058
33931247.114: <09>Lane 01 new seed: 0058
33932247.114: <09>Lane 02 scaled delay: 0053
33933247.114: <09>Lane 02 new seed: 0053
33934247.114: <09>Lane 03 scaled delay: 0051
33935247.114: <09>Lane 03 new seed: 0051
33936247.114: <09>Lane 04 scaled delay: 0049
33937247.114: <09>Lane 04 new seed: 0049
33938247.114: <09>Lane 05 scaled delay: 0052
33939247.114: <09>Lane 05 new seed: 0052
33940247.114: <09>Lane 06 scaled delay: 0054
33941247.114: <09>Lane 06 new seed: 0054
33942247.114: <09>Lane 07 scaled delay: 005a
33943247.114: <09>Lane 07 new seed: 005a
33944247.114: <09>Lane 08 scaled delay: 0046
33945247.114: <09>Lane 08 new seed: 0046
33946247.114: <09>Lane 00 nibble 0 raw readback: 0066
33947247.114: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0066
33948247.114: <09>Lane 00 nibble 0 adjusted value (post nibble): 0066
33949247.114: <09>Lane 01 nibble 0 raw readback: 005e
33950247.114: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005e
33951247.114: <09>Lane 01 nibble 0 adjusted value (post nibble): 005e
33952247.114: <09>Lane 02 nibble 0 raw readback: 0055
33953247.114: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
33954247.114: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
33955247.114: <09>Lane 03 nibble 0 raw readback: 0051
33956247.114: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
33957247.114: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
33958247.114: <09>Lane 04 nibble 0 raw readback: 004d
33959247.114: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
33960247.114: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
33961247.114: <09>Lane 05 nibble 0 raw readback: 0053
33962247.114: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
33963247.114: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
33964247.114: <09>Lane 06 nibble 0 raw readback: 0057
33965247.114: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
33966247.114: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
33967247.114: <09>Lane 07 nibble 0 raw readback: 0060
33968247.114: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0060
33969247.114: <09>Lane 07 nibble 0 adjusted value (post nibble): 0060
33970247.114: <09>Lane 08 nibble 0 raw readback: 004a
33971247.114: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
33972247.114: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
33973247.114: AgesaHwWlPhase1: training nibble 1
33974247.114: DIMM 0 RttNom: 4
33975247.114: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
33976247.114: DIMM 0 RttWr: 1
33977247.114: DIMM 0 RttWr: 1
33978247.114: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
33979247.114: DIMM 0 RttWr: 1
33980247.114: DIMM 0 RttNom: 4
33981247.114: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
33982247.114: DIMM 0 RttNom: 4
33983247.115: DIMM 0 RttWr: 1
33984247.115: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
33985247.115: DIMM 0 RttWr: 1
33986247.115: DIMM 1 RttNom: 4
33987247.115: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
33988247.115: DIMM 0 RttNom: 4
33989247.115: DIMM 1 RttWr: 1
33990247.115: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
33991247.115: DIMM 0 RttWr: 1
33992247.115: DIMM 1 RttNom: 4
33993247.115: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
33994247.115: DIMM 0 RttNom: 4
33995247.115: DIMM 1 RttWr: 1
33996247.115: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
33997247.115: DIMM 0 RttWr: 1
33998247.115: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
33999247.115: <09>Lane 00 new seed: 005e
34000247.115: <09>Lane 01 new seed: 0058
34001247.115: <09>Lane 02 new seed: 0053
34002247.115: <09>Lane 03 new seed: 0051
34003247.115: <09>Lane 04 new seed: 0049
34004247.115: <09>Lane 05 new seed: 0052
34005247.115: <09>Lane 06 new seed: 0054
34006247.115: <09>Lane 07 new seed: 005a
34007247.115: <09>Lane 08 new seed: 0046
34008247.115: <09>Lane 00 nibble 1 raw readback: 0064
34009247.115: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0064
34010247.115: <09>Lane 00 nibble 1 adjusted value (post nibble): 0061
34011247.115: <09>Lane 01 nibble 1 raw readback: 005d
34012247.115: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005d
34013247.115: <09>Lane 01 nibble 1 adjusted value (post nibble): 005a
34014247.115: <09>Lane 02 nibble 1 raw readback: 0055
34015247.115: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
34016247.115: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
34017247.115: <09>Lane 03 nibble 1 raw readback: 0052
34018247.115: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
34019247.115: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
34020247.115: <09>Lane 04 nibble 1 raw readback: 004b
34021247.115: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
34022247.115: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
34023247.115: <09>Lane 05 nibble 1 raw readback: 0052
34024247.115: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
34025247.115: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
34026247.115: <09>Lane 06 nibble 1 raw readback: 0058
34027247.115: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
34028247.115: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
34029247.115: <09>Lane 07 nibble 1 raw readback: 005f
34030247.115: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005f
34031247.115: <09>Lane 07 nibble 1 adjusted value (post nibble): 005c
34032247.115: <09>Lane 08 nibble 1 raw readback: 0048
34033247.115: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
34034247.115: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
34035247.115: <09>original critical gross delay: 0
34036247.115: <09>new critical gross delay: 0
34037247.115: DIMM 0 RttNom: 4
34038247.115: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
34039247.115: DIMM 0 RttNom: 4
34040247.115: DIMM 0 RttWr: 1
34041247.115: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
34042247.115: DIMM 0 RttWr: 1
34043247.115: DIMM 0 RttNom: 4
34044247.117: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
34045247.116: DIMM 0 RttNom: 4
34046247.116: DIMM 0 RttWr: 1
34047247.116: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
34048247.116: DIMM 0 RttWr: 1
34049247.116: DIMM 1 RttNom: 4
34050247.116: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
34051247.116: DIMM 0 RttNom: 4
34052247.116: DIMM 1 RttWr: 1
34053247.116: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
34054247.116: DIMM 0 RttWr: 1
34055247.116: DIMM 1 RttNom: 4
34056247.116: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
34057247.116: DIMM 0 RttNom: 4
34058247.116: DIMM 1 RttWr: 1
34059247.116: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
34060247.116: DIMM 0 RttWr: 1
34061247.116: AgesaHwWlPhase1: training nibble 0
34062247.116: DIMM 1 RttNom: 4
34063247.116: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
34064247.116: DIMM 1 RttWr: 1
34065247.116: DIMM 1 RttWr: 1
34066247.116: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
34067247.116: DIMM 1 RttWr: 1
34068247.116: DIMM 1 RttNom: 4
34069247.116: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
34070247.116: DIMM 1 RttNom: 4
34071247.116: DIMM 1 RttWr: 1
34072247.116: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
34073247.116: DIMM 1 RttWr: 1
34074247.116: DIMM 0 RttNom: 4
34075247.116: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
34076247.116: DIMM 1 RttNom: 4
34077247.116: DIMM 0 RttWr: 1
34078247.116: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
34079247.116: DIMM 1 RttWr: 1
34080247.116: DIMM 0 RttNom: 4
34081247.116: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
34082247.116: DIMM 1 RttNom: 4
34083247.116: DIMM 0 RttWr: 1
34084247.116: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
34085247.116: DIMM 1 RttWr: 1
34086247.116: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
34087247.116: <09>Lane 00 scaled delay: 0069
34088247.116: <09>Lane 00 new seed: 0069
34089247.116: <09>Lane 01 scaled delay: 0060
34090247.116: <09>Lane 01 new seed: 0060
34091247.116: <09>Lane 02 scaled delay: 005a
34092247.116: <09>Lane 02 new seed: 005a
34093247.116: <09>Lane 03 scaled delay: 0058
34094247.116: <09>Lane 03 new seed: 0058
34095247.116: <09>Lane 04 scaled delay: 0052
34096247.116: <09>Lane 04 new seed: 0052
34097247.116: <09>Lane 05 scaled delay: 0059
34098247.116: <09>Lane 05 new seed: 0059
34099247.116: <09>Lane 06 scaled delay: 005d
34100247.116: <09>Lane 06 new seed: 005d
34101247.116: <09>Lane 07 scaled delay: 0063
34102247.116: <09>Lane 07 new seed: 0063
34103247.116: <09>Lane 08 scaled delay: 0052
34104247.116: <09>Lane 08 new seed: 0052
34105247.116: <09>Lane 00 nibble 0 raw readback: 002f
34106247.116: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
34107247.116: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
34108247.116: <09>Lane 01 nibble 0 raw readback: 0025
34109247.117: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
34110247.117: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
34111247.117: <09>Lane 02 nibble 0 raw readback: 005d
34112247.117: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
34113247.117: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
34114247.117: <09>Lane 03 nibble 0 raw readback: 005c
34115247.117: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
34116247.117: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
34117247.117: <09>Lane 04 nibble 0 raw readback: 0057
34118247.117: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
34119247.117: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
34120247.117: <09>Lane 05 nibble 0 raw readback: 0060
34121247.117: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0060
34122247.117: <09>Lane 05 nibble 0 adjusted value (post nibble): 0060
34123247.117: <09>Lane 06 nibble 0 raw readback: 0061
34124247.117: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0061
34125247.117: <09>Lane 06 nibble 0 adjusted value (post nibble): 0061
34126247.117: <09>Lane 07 nibble 0 raw readback: 0029
34127247.117: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
34128247.117: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
34129247.117: <09>Lane 08 nibble 0 raw readback: 0052
34130247.117: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0052
34131247.117: <09>Lane 08 nibble 0 adjusted value (post nibble): 0052
34132247.117: AgesaHwWlPhase1: training nibble 1
34133247.117: DIMM 1 RttNom: 4
34134247.117: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
34135247.117: DIMM 1 RttWr: 1
34136247.117: DIMM 1 RttWr: 1
34137247.117: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
34138247.117: DIMM 1 RttWr: 1
34139247.117: DIMM 1 RttNom: 4
34140247.117: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
34141247.117: DIMM 1 RttNom: 4
34142247.117: DIMM 1 RttWr: 1
34143247.117: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
34144247.117: DIMM 1 RttWr: 1
34145247.117: DIMM 0 RttNom: 4
34146247.117: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
34147247.117: DIMM 1 RttNom: 4
34148247.117: DIMM 0 RttWr: 1
34149247.117: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
34150247.117: DIMM 1 RttWr: 1
34151247.117: DIMM 0 RttNom: 4
34152247.117: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
34153247.117: DIMM 1 RttNom: 4
34154247.117: DIMM 0 RttWr: 1
34155247.117: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
34156247.117: DIMM 1 RttWr: 1
34157247.117: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
34158247.117: <09>Lane 00 new seed: 0069
34159247.117: <09>Lane 01 new seed: 0060
34160247.117: <09>Lane 02 new seed: 005a
34161247.117: <09>Lane 03 new seed: 0058
34162247.117: <09>Lane 04 new seed: 0052
34163247.117: <09>Lane 05 new seed: 0059
34164247.117: <09>Lane 06 new seed: 005d
34165247.117: <09>Lane 07 new seed: 0063
34166247.117: <09>Lane 08 new seed: 0052
34167247.117: <09>Lane 00 nibble 1 raw readback: 002f
34168247.117: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
34169247.117: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
34170247.117: <09>Lane 01 nibble 1 raw readback: 0025
34171247.117: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
34172247.117: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
34173247.117: <09>Lane 02 nibble 1 raw readback: 005c
34174247.117: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005c
34175247.117: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
34176247.118: <09>Lane 03 nibble 1 raw readback: 005a
34177247.117: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005a
34178247.117: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
34179247.117: <09>Lane 04 nibble 1 raw readback: 0053
34180247.117: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0053
34181247.117: <09>Lane 04 nibble 1 adjusted value (post nibble): 0052
34182247.117: <09>Lane 05 nibble 1 raw readback: 005c
34183247.118: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
34184247.117: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
34185247.117: <09>Lane 06 nibble 1 raw readback: 0061
34186247.118: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0061
34187247.118: <09>Lane 06 nibble 1 adjusted value (post nibble): 005f
34188247.118: <09>Lane 07 nibble 1 raw readback: 0028
34189247.118: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
34190247.118: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
34191247.118: <09>Lane 08 nibble 1 raw readback: 0053
34192247.118: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0053
34193247.118: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
34194247.118: <09>original critical gross delay: 0
34195247.118: <09>new critical gross delay: 0
34196247.118: DIMM 1 RttNom: 4
34197247.118: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
34198247.118: DIMM 1 RttNom: 4
34199247.118: DIMM 1 RttWr: 1
34200247.118: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
34201247.118: DIMM 1 RttWr: 1
34202247.118: DIMM 1 RttNom: 4
34203247.118: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
34204247.118: DIMM 1 RttNom: 4
34205247.118: DIMM 1 RttWr: 1
34206247.118: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
34207247.118: DIMM 1 RttWr: 1
34208247.118: DIMM 0 RttNom: 4
34209247.118: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
34210247.118: DIMM 1 RttNom: 4
34211247.118: DIMM 0 RttWr: 1
34212247.118: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
34213247.118: DIMM 1 RttWr: 1
34214247.118: DIMM 0 RttNom: 4
34215247.118: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
34216247.118: DIMM 1 RttNom: 4
34217247.118: DIMM 0 RttWr: 1
34218247.118: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
34219247.118: DIMM 1 RttWr: 1
34220247.118: SPD2ndTiming: Start
34221247.119: SPD2ndTiming: Done
34222247.119: mct_BeforeDramInit_Prod_D: Start
34223247.119: mct_ProgramODT_D: Start
34224247.119: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
34225247.119: mct_ProgramODT_D: Done
34226247.119: mct_BeforeDramInit_Prod_D: Done
34227247.119: mct_DramInit_Sw_D: Start
34228247.119: DIMM 0 RttWr: 1
34229247.119: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34230247.119: mct_SendMrsCmd: Start
34231247.119: mct_SendMrsCmd: Done
34232247.119: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
34233247.119: mct_SendMrsCmd: Start
34234247.119: mct_SendMrsCmd: Done
34235247.119: DIMM 0 RttNom: 4
34236247.119: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34237247.119: mct_SendMrsCmd: Start
34238247.119: mct_SendMrsCmd: Done
34239247.119: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
34240247.119: mct_SendMrsCmd: Start
34241247.119: mct_SendMrsCmd: Done
34242247.119: DIMM 0 RttWr: 1
34243247.119: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34244247.119: mct_SendMrsCmd: Start
34245247.119: mct_SendMrsCmd: Done
34246247.119: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
34247247.119: mct_SendMrsCmd: Start
34248247.119: mct_SendMrsCmd: Done
34249247.119: DIMM 0 RttNom: 4
34250247.119: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34251247.119: mct_SendMrsCmd: Start
34252247.119: mct_SendMrsCmd: Done
34253247.119: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
34254247.119: mct_SendMrsCmd: Start
34255247.119: mct_SendMrsCmd: Done
34256247.119: DIMM 1 RttWr: 1
34257247.119: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34258247.119: mct_SendMrsCmd: Start
34259247.119: mct_SendMrsCmd: Done
34260247.119: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
34261247.119: mct_SendMrsCmd: Start
34262247.119: mct_SendMrsCmd: Done
34263247.119: DIMM 1 RttNom: 4
34264247.119: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34265247.119: mct_SendMrsCmd: Start
34266247.119: mct_SendMrsCmd: Done
34267247.119: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
34268247.119: mct_SendMrsCmd: Start
34269247.119: mct_SendMrsCmd: Done
34270247.119: DIMM 1 RttWr: 1
34271247.119: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34272247.119: mct_SendMrsCmd: Start
34273247.119: mct_SendMrsCmd: Done
34274247.119: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
34275247.119: mct_SendMrsCmd: Start
34276247.119: mct_SendMrsCmd: Done
34277247.119: DIMM 1 RttNom: 4
34278247.119: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34279247.119: mct_SendMrsCmd: Start
34280247.119: mct_SendMrsCmd: Done
34281247.119: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
34282247.119: mct_SendMrsCmd: Start
34283247.119: mct_SendMrsCmd: Done
34284247.119: mct_DramInit_Sw_D: Done
34285247.120: AgesaHwWlPhase1: training nibble 0
34286247.120: DIMM 0 RttNom: 4
34287247.120: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34288247.120: DIMM 0 RttWr: 1
34289247.120: DIMM 0 RttWr: 1
34290247.120: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34291247.120: DIMM 0 RttWr: 1
34292247.120: DIMM 0 RttNom: 4
34293247.120: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34294247.120: DIMM 0 RttNom: 4
34295247.120: DIMM 0 RttWr: 1
34296247.120: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34297247.120: DIMM 0 RttWr: 1
34298247.120: DIMM 1 RttNom: 4
34299247.120: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34300247.120: DIMM 0 RttNom: 4
34301247.120: DIMM 1 RttWr: 1
34302247.120: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34303247.120: DIMM 0 RttWr: 1
34304247.120: DIMM 1 RttNom: 4
34305247.120: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34306247.120: DIMM 0 RttNom: 4
34307247.120: DIMM 1 RttWr: 1
34308247.120: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34309247.120: DIMM 0 RttWr: 1
34310247.120: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
34311247.120: <09>Lane 00 scaled delay: 0063
34312247.120: <09>Lane 00 new seed: 0063
34313247.120: <09>Lane 01 scaled delay: 005b
34314247.120: <09>Lane 01 new seed: 005b
34315247.120: <09>Lane 02 scaled delay: 0055
34316247.120: <09>Lane 02 new seed: 0055
34317247.120: <09>Lane 03 scaled delay: 0051
34318247.120: <09>Lane 03 new seed: 0051
34319247.120: <09>Lane 04 scaled delay: 004c
34320247.120: <09>Lane 04 new seed: 004c
34321247.120: <09>Lane 05 scaled delay: 0053
34322247.120: <09>Lane 05 new seed: 0053
34323247.120: <09>Lane 06 scaled delay: 0059
34324247.120: <09>Lane 06 new seed: 0059
34325247.120: <09>Lane 07 scaled delay: 0060
34326247.120: <09>Lane 07 new seed: 0060
34327247.120: <09>Lane 08 scaled delay: 0049
34328247.120: <09>Lane 08 new seed: 0049
34329247.120: <09>Lane 00 nibble 0 raw readback: 0027
34330247.120: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0067
34331247.120: <09>Lane 00 nibble 0 adjusted value (post nibble): 0067
34332247.120: <09>Lane 01 nibble 0 raw readback: 005d
34333247.120: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005d
34334247.120: <09>Lane 01 nibble 0 adjusted value (post nibble): 005d
34335247.120: <09>Lane 02 nibble 0 raw readback: 0056
34336247.120: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0056
34337247.121: <09>Lane 02 nibble 0 adjusted value (post nibble): 0056
34338247.120: <09>Lane 03 nibble 0 raw readback: 004f
34339247.121: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
34340247.121: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
34341247.121: <09>Lane 04 nibble 0 raw readback: 004d
34342247.121: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
34343247.121: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
34344247.121: <09>Lane 05 nibble 0 raw readback: 0055
34345247.121: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0055
34346247.121: <09>Lane 05 nibble 0 adjusted value (post nibble): 0055
34347247.121: <09>Lane 06 nibble 0 raw readback: 005a
34348247.121: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005a
34349247.121: <09>Lane 06 nibble 0 adjusted value (post nibble): 005a
34350247.121: <09>Lane 07 nibble 0 raw readback: 0021
34351247.121: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0061
34352247.121: <09>Lane 07 nibble 0 adjusted value (post nibble): 0061
34353247.121: <09>Lane 08 nibble 0 raw readback: 004a
34354247.121: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
34355247.121: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
34356247.121: AgesaHwWlPhase1: training nibble 1
34357247.121: DIMM 0 RttNom: 4
34358247.121: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34359247.121: DIMM 0 RttWr: 1
34360247.121: DIMM 0 RttWr: 1
34361247.121: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34362247.121: DIMM 0 RttWr: 1
34363247.121: DIMM 0 RttNom: 4
34364247.121: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34365247.121: DIMM 0 RttNom: 4
34366247.121: DIMM 0 RttWr: 1
34367247.121: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34368247.121: DIMM 0 RttWr: 1
34369247.121: DIMM 1 RttNom: 4
34370247.121: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34371247.121: DIMM 0 RttNom: 4
34372247.121: DIMM 1 RttWr: 1
34373247.121: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34374247.121: DIMM 0 RttWr: 1
34375247.121: DIMM 1 RttNom: 4
34376247.121: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34377247.121: DIMM 0 RttNom: 4
34378247.121: DIMM 1 RttWr: 1
34379247.121: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34380247.121: DIMM 0 RttWr: 1
34381247.121: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
34382247.121: <09>Lane 00 new seed: 0063
34383247.121: <09>Lane 01 new seed: 005b
34384247.121: <09>Lane 02 new seed: 0055
34385247.121: <09>Lane 03 new seed: 0051
34386247.121: <09>Lane 04 new seed: 004c
34387247.121: <09>Lane 05 new seed: 0053
34388247.121: <09>Lane 06 new seed: 0059
34389247.121: <09>Lane 07 new seed: 0060
34390247.121: <09>Lane 08 new seed: 0049
34391247.121: <09>Lane 00 nibble 1 raw readback: 0024
34392247.121: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0064
34393247.121: <09>Lane 00 nibble 1 adjusted value (post nibble): 0063
34394247.121: <09>Lane 01 nibble 1 raw readback: 005e
34395247.121: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005e
34396247.121: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
34397247.121: <09>Lane 02 nibble 1 raw readback: 0055
34398247.121: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
34399247.121: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
34400247.121: <09>Lane 03 nibble 1 raw readback: 004f
34401247.121: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
34402247.121: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
34403247.121: <09>Lane 04 nibble 1 raw readback: 004c
34404247.121: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
34405247.121: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
34406247.121: <09>Lane 05 nibble 1 raw readback: 0053
34407247.121: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0053
34408247.121: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
34409247.121: <09>Lane 06 nibble 1 raw readback: 005a
34410247.122: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005a
34411247.122: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
34412247.122: <09>Lane 07 nibble 1 raw readback: 0022
34413247.122: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0062
34414247.122: <09>Lane 07 nibble 1 adjusted value (post nibble): 0061
34415247.122: <09>Lane 08 nibble 1 raw readback: 0047
34416247.122: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0047
34417247.122: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
34418247.122: <09>original critical gross delay: 0
34419247.122: <09>new critical gross delay: 0
34420247.122: DIMM 0 RttNom: 4
34421247.122: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34422247.122: DIMM 0 RttNom: 4
34423247.122: DIMM 0 RttWr: 1
34424247.122: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34425247.122: DIMM 0 RttWr: 1
34426247.122: DIMM 0 RttNom: 4
34427247.122: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34428247.122: DIMM 0 RttNom: 4
34429247.122: DIMM 0 RttWr: 1
34430247.122: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34431247.122: DIMM 0 RttWr: 1
34432247.122: DIMM 1 RttNom: 4
34433247.122: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34434247.122: DIMM 0 RttNom: 4
34435247.122: DIMM 1 RttWr: 1
34436247.122: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34437247.122: DIMM 0 RttWr: 1
34438247.122: DIMM 1 RttNom: 4
34439247.122: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34440247.122: DIMM 0 RttNom: 4
34441247.122: DIMM 1 RttWr: 1
34442247.122: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34443247.122: DIMM 0 RttWr: 1
34444247.122: AgesaHwWlPhase1: training nibble 0
34445247.122: DIMM 1 RttNom: 4
34446247.122: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34447247.122: DIMM 1 RttWr: 1
34448247.122: DIMM 1 RttWr: 1
34449247.122: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34450247.122: DIMM 1 RttWr: 1
34451247.122: DIMM 1 RttNom: 4
34452247.122: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34453247.122: DIMM 1 RttNom: 4
34454247.122: DIMM 1 RttWr: 1
34455247.122: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34456247.122: DIMM 1 RttWr: 1
34457247.122: DIMM 0 RttNom: 4
34458247.122: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34459247.122: DIMM 1 RttNom: 4
34460247.122: DIMM 0 RttWr: 1
34461247.122: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34462247.122: DIMM 1 RttWr: 1
34463247.122: DIMM 0 RttNom: 4
34464247.122: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34465247.122: DIMM 1 RttNom: 4
34466247.122: DIMM 0 RttWr: 1
34467247.122: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34468247.123: DIMM 1 RttWr: 1
34469247.123: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
34470247.123: <09>Lane 00 scaled delay: 006b
34471247.123: <09>Lane 00 new seed: 006b
34472247.123: <09>Lane 01 scaled delay: 0064
34473247.123: <09>Lane 01 new seed: 0064
34474247.123: <09>Lane 02 scaled delay: 005e
34475247.123: <09>Lane 02 new seed: 005e
34476247.123: <09>Lane 03 scaled delay: 0059
34477247.123: <09>Lane 03 new seed: 0059
34478247.123: <09>Lane 04 scaled delay: 0053
34479247.123: <09>Lane 04 new seed: 0053
34480247.123: <09>Lane 05 scaled delay: 0059
34481247.123: <09>Lane 05 new seed: 0059
34482247.123: <09>Lane 06 scaled delay: 0061
34483247.123: <09>Lane 06 new seed: 0061
34484247.123: <09>Lane 07 scaled delay: 0069
34485247.123: <09>Lane 07 new seed: 0069
34486247.123: <09>Lane 08 scaled delay: 0052
34487247.123: <09>Lane 08 new seed: 0052
34488247.123: <09>Lane 00 nibble 0 raw readback: 002a
34489247.123: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006a
34490247.123: <09>Lane 00 nibble 0 adjusted value (post nibble): 006a
34491247.123: <09>Lane 01 nibble 0 raw readback: 0028
34492247.123: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0068
34493247.123: <09>Lane 01 nibble 0 adjusted value (post nibble): 0068
34494247.123: <09>Lane 02 nibble 0 raw readback: 005f
34495247.123: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
34496247.123: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
34497247.123: <09>Lane 03 nibble 0 raw readback: 0058
34498247.123: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0058
34499247.123: <09>Lane 03 nibble 0 adjusted value (post nibble): 0058
34500247.123: <09>Lane 04 nibble 0 raw readback: 0055
34501247.123: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
34502247.123: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
34503247.123: <09>Lane 05 nibble 0 raw readback: 005e
34504247.123: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
34505247.123: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
34506247.123: <09>Lane 06 nibble 0 raw readback: 0025
34507247.123: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
34508247.123: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
34509247.123: <09>Lane 07 nibble 0 raw readback: 0029
34510247.123: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
34511247.123: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
34512247.123: <09>Lane 08 nibble 0 raw readback: 0051
34513247.123: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0051
34514247.123: <09>Lane 08 nibble 0 adjusted value (post nibble): 0051
34515247.123: AgesaHwWlPhase1: training nibble 1
34516247.123: DIMM 1 RttNom: 4
34517247.123: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34518247.123: DIMM 1 RttWr: 1
34519247.123: DIMM 1 RttWr: 1
34520247.123: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34521247.123: DIMM 1 RttWr: 1
34522247.123: DIMM 1 RttNom: 4
34523247.123: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34524247.123: DIMM 1 RttNom: 4
34525247.123: DIMM 1 RttWr: 1
34526247.123: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34527247.123: DIMM 1 RttWr: 1
34528247.123: DIMM 0 RttNom: 4
34529247.123: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34530247.123: DIMM 1 RttNom: 4
34531247.123: DIMM 0 RttWr: 1
34532247.123: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34533247.123: DIMM 1 RttWr: 1
34534247.123: DIMM 0 RttNom: 4
34535247.123: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34536247.123: DIMM 1 RttNom: 4
34537247.123: DIMM 0 RttWr: 1
34538247.123: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34539247.123: DIMM 1 RttWr: 1
34540247.124: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
34541247.124: <09>Lane 00 new seed: 006b
34542247.124: <09>Lane 01 new seed: 0064
34543247.124: <09>Lane 02 new seed: 005e
34544247.124: <09>Lane 03 new seed: 0059
34545247.124: <09>Lane 04 new seed: 0053
34546247.124: <09>Lane 05 new seed: 0059
34547247.124: <09>Lane 06 new seed: 0061
34548247.124: <09>Lane 07 new seed: 0069
34549247.124: <09>Lane 08 new seed: 0052
34550247.124: <09>Lane 00 nibble 1 raw readback: 002f
34551247.124: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
34552247.124: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
34553247.124: <09>Lane 01 nibble 1 raw readback: 0027
34554247.124: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
34555247.124: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
34556247.124: <09>Lane 02 nibble 1 raw readback: 005e
34557247.124: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
34558247.124: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
34559247.124: <09>Lane 03 nibble 1 raw readback: 0059
34560247.124: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
34561247.124: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
34562247.124: <09>Lane 04 nibble 1 raw readback: 0053
34563247.124: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0053
34564247.124: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
34565247.124: <09>Lane 05 nibble 1 raw readback: 005a
34566247.124: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005a
34567247.124: <09>Lane 05 nibble 1 adjusted value (post nibble): 0059
34568247.124: <09>Lane 06 nibble 1 raw readback: 0023
34569247.124: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0063
34570247.124: <09>Lane 06 nibble 1 adjusted value (post nibble): 0062
34571247.124: <09>Lane 07 nibble 1 raw readback: 002b
34572247.124: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
34573247.124: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
34574247.124: <09>Lane 08 nibble 1 raw readback: 0052
34575247.124: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0052
34576247.124: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
34577247.124: <09>original critical gross delay: 0
34578247.124: <09>new critical gross delay: 0
34579247.124: DIMM 1 RttNom: 4
34580247.124: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
34581247.124: DIMM 1 RttNom: 4
34582247.124: DIMM 1 RttWr: 1
34583247.124: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
34584247.124: DIMM 1 RttWr: 1
34585247.124: DIMM 1 RttNom: 4
34586247.124: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
34587247.124: DIMM 1 RttNom: 4
34588247.124: DIMM 1 RttWr: 1
34589247.124: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
34590247.124: DIMM 1 RttWr: 1
34591247.124: DIMM 0 RttNom: 4
34592247.124: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
34593247.124: DIMM 1 RttNom: 4
34594247.124: DIMM 0 RttWr: 1
34595247.124: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
34596247.124: DIMM 1 RttWr: 1
34597247.124: DIMM 0 RttNom: 4
34598247.124: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
34599247.124: DIMM 1 RttNom: 4
34600247.124: DIMM 0 RttWr: 1
34601247.124: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
34602247.124: DIMM 1 RttWr: 1
34603247.125: activate_spd_rom() for node 02
34604247.125: enable_spd_node2()
34605247.125: SetTargetFreq: Start
34606247.125: SetTargetFreq: Node 2: New frequency code: 0006
34607247.125: ChangeMemClk: Start
34608247.125: set_2t_configuration: Start
34609247.125: set_2t_configuration: Done
34610247.125: mct_BeforePlatformSpec: Start
34611247.125: mct_BeforePlatformSpec: Done
34612247.125: mct_PlatformSpec: Start
34613247.125: Programmed DCT 0 timing/termination pattern 00000000 20222222
34614247.125: mct_PlatformSpec: Done
34615247.125: set_2t_configuration: Start
34616247.125: set_2t_configuration: Done
34617247.125: mct_BeforePlatformSpec: Start
34618247.125: mct_BeforePlatformSpec: Done
34619247.125: mct_PlatformSpec: Start
34620247.125: Programmed DCT 1 timing/termination pattern 00000000 20222222
34621247.125: mct_PlatformSpec: Done
34622247.125: ChangeMemClk: Done
34623247.125: phyAssistedMemFnceTraining: Start
34624247.126: phyAssistedMemFnceTraining: training node 2 DCT 0
34625247.126: phyAssistedMemFnceTraining: done training node 2 DCT 0
34626247.126: phyAssistedMemFnceTraining: training node 2 DCT 1
34627247.126: phyAssistedMemFnceTraining: done training node 2 DCT 1
34628247.126: phyAssistedMemFnceTraining: Done
34629247.126: InitPhyCompensation: DCT 0: Start
34630247.126: Waiting for predriver calibration to be applied...done!
34631247.126: InitPhyCompensation: DCT 0: Done
34632247.126: phyAssistedMemFnceTraining: Start
34633247.126: phyAssistedMemFnceTraining: training node 2 DCT 0
34634247.126: phyAssistedMemFnceTraining: done training node 2 DCT 0
34635247.126: phyAssistedMemFnceTraining: training node 2 DCT 1
34636247.126: phyAssistedMemFnceTraining: done training node 2 DCT 1
34637247.126: phyAssistedMemFnceTraining: Done
34638247.126: InitPhyCompensation: DCT 1: Start
34639247.126: Waiting for predriver calibration to be applied...done!
34640247.126: InitPhyCompensation: DCT 1: Done
34641247.127: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
34642247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
34643247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
34644247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
34645247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
34646247.127: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
34647247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
34648247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
34649247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
34650247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
34651247.127: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
34652247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
34653247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
34654247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
34655247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
34656247.127: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
34657247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
34658247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
34659247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
34660247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
34661247.127: SetTargetFreq: Done
34662247.127: SPD2ndTiming: Start
34663247.128: SPD2ndTiming: Done
34664247.127: mct_BeforeDramInit_Prod_D: Start
34665247.127: mct_ProgramODT_D: Start
34666247.127: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
34667247.128: mct_ProgramODT_D: Done
34668247.128: mct_BeforeDramInit_Prod_D: Done
34669247.128: mct_DramInit_Sw_D: Start
34670247.128: DIMM 0 RttWr: 2
34671247.128: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
34672247.128: mct_SendMrsCmd: Start
34673247.128: mct_SendMrsCmd: Done
34674247.128: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
34675247.128: mct_SendMrsCmd: Start
34676247.128: mct_SendMrsCmd: Done
34677247.128: DIMM 0 RttNom: 3
34678247.128: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
34679247.128: mct_SendMrsCmd: Start
34680247.128: mct_SendMrsCmd: Done
34681247.128: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
34682247.128: mct_SendMrsCmd: Start
34683247.128: mct_SendMrsCmd: Done
34684247.128: DIMM 0 RttWr: 2
34685247.128: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
34686247.128: mct_SendMrsCmd: Start
34687247.128: mct_SendMrsCmd: Done
34688247.128: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
34689247.128: mct_SendMrsCmd: Start
34690247.128: mct_SendMrsCmd: Done
34691247.128: DIMM 0 RttNom: 3
34692247.128: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
34693247.128: mct_SendMrsCmd: Start
34694247.128: mct_SendMrsCmd: Done
34695247.128: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
34696247.128: mct_SendMrsCmd: Start
34697247.128: mct_SendMrsCmd: Done
34698247.128: DIMM 1 RttWr: 2
34699247.128: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
34700247.128: mct_SendMrsCmd: Start
34701247.128: mct_SendMrsCmd: Done
34702247.128: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
34703247.128: mct_SendMrsCmd: Start
34704247.128: mct_SendMrsCmd: Done
34705247.128: DIMM 1 RttNom: 3
34706247.128: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
34707247.128: mct_SendMrsCmd: Start
34708247.128: mct_SendMrsCmd: Done
34709247.128: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
34710247.128: mct_SendMrsCmd: Start
34711247.128: mct_SendMrsCmd: Done
34712247.128: DIMM 1 RttWr: 2
34713247.128: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
34714247.128: mct_SendMrsCmd: Start
34715247.128: mct_SendMrsCmd: Done
34716247.128: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
34717247.128: mct_SendMrsCmd: Start
34718247.128: mct_SendMrsCmd: Done
34719247.128: DIMM 1 RttNom: 3
34720247.128: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
34721247.128: mct_SendMrsCmd: Start
34722247.128: mct_SendMrsCmd: Done
34723247.128: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
34724247.128: mct_SendMrsCmd: Start
34725247.128: mct_SendMrsCmd: Done
34726247.128: mct_DramInit_Sw_D: Done
34727247.129: AgesaHwWlPhase1: training nibble 0
34728247.129: DIMM 0 RttNom: 3
34729247.129: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
34730247.129: DIMM 0 RttWr: 2
34731247.129: DIMM 0 RttWr: 2
34732247.129: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
34733247.129: DIMM 0 RttWr: 2
34734247.129: DIMM 0 RttNom: 3
34735247.129: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
34736247.129: DIMM 0 RttNom: 3
34737247.129: DIMM 0 RttWr: 2
34738247.129: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
34739247.129: DIMM 0 RttWr: 2
34740247.129: DIMM 1 RttNom: 3
34741247.129: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
34742247.129: DIMM 0 RttNom: 3
34743247.129: DIMM 1 RttWr: 2
34744247.129: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
34745247.129: DIMM 0 RttWr: 2
34746247.129: DIMM 1 RttNom: 3
34747247.129: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
34748247.129: DIMM 0 RttNom: 3
34749247.129: DIMM 1 RttWr: 2
34750247.129: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
34751247.129: DIMM 0 RttWr: 2
34752247.129: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
34753247.129: <09>Lane 00 scaled delay: 0047
34754247.129: <09>Lane 00 new seed: 0047
34755247.129: <09>Lane 01 scaled delay: 0047
34756247.129: <09>Lane 01 new seed: 0047
34757247.129: <09>Lane 02 scaled delay: 0047
34758247.129: <09>Lane 02 new seed: 0047
34759247.129: <09>Lane 03 scaled delay: 0047
34760247.129: <09>Lane 03 new seed: 0047
34761247.129: <09>Lane 04 scaled delay: 0047
34762247.129: <09>Lane 04 new seed: 0047
34763247.129: <09>Lane 05 scaled delay: 0047
34764247.129: <09>Lane 05 new seed: 0047
34765247.129: <09>Lane 06 scaled delay: 0047
34766247.129: <09>Lane 06 new seed: 0047
34767247.129: <09>Lane 07 scaled delay: 0047
34768247.129: <09>Lane 07 new seed: 0047
34769247.129: <09>Lane 08 scaled delay: 0047
34770247.129: <09>Lane 08 new seed: 0047
34771247.130: <09>Lane 00 nibble 0 raw readback: 0050
34772247.130: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
34773247.130: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
34774247.130: <09>Lane 01 nibble 0 raw readback: 0049
34775247.130: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
34776247.130: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
34777247.130: <09>Lane 02 nibble 0 raw readback: 0048
34778247.130: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
34779247.130: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
34780247.130: <09>Lane 03 nibble 0 raw readback: 0045
34781247.130: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
34782247.130: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
34783247.130: <09>Lane 04 nibble 0 raw readback: 003b
34784247.130: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
34785247.130: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
34786247.130: <09>Lane 05 nibble 0 raw readback: 003f
34787247.130: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003f
34788247.130: <09>Lane 05 nibble 0 adjusted value (post nibble): 003f
34789247.130: <09>Lane 06 nibble 0 raw readback: 0041
34790247.130: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
34791247.130: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
34792247.130: <09>Lane 07 nibble 0 raw readback: 0043
34793247.130: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
34794247.130: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
34795247.130: <09>Lane 08 nibble 0 raw readback: 003d
34796247.130: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003d
34797247.130: <09>Lane 08 nibble 0 adjusted value (post nibble): 003d
34798247.130: AgesaHwWlPhase1: training nibble 1
34799247.130: DIMM 0 RttNom: 3
34800247.130: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
34801247.130: DIMM 0 RttWr: 2
34802247.130: DIMM 0 RttWr: 2
34803247.130: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
34804247.130: DIMM 0 RttWr: 2
34805247.130: DIMM 0 RttNom: 3
34806247.130: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
34807247.130: DIMM 0 RttNom: 3
34808247.130: DIMM 0 RttWr: 2
34809247.130: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
34810247.130: DIMM 0 RttWr: 2
34811247.130: DIMM 1 RttNom: 3
34812247.130: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
34813247.130: DIMM 0 RttNom: 3
34814247.130: DIMM 1 RttWr: 2
34815247.130: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
34816247.130: DIMM 0 RttWr: 2
34817247.130: DIMM 1 RttNom: 3
34818247.130: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
34819247.130: DIMM 0 RttNom: 3
34820247.130: DIMM 1 RttWr: 2
34821247.130: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
34822247.130: DIMM 0 RttWr: 2
34823247.130: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
34824247.130: <09>Lane 00 new seed: 0047
34825247.130: <09>Lane 01 new seed: 0047
34826247.130: <09>Lane 02 new seed: 0047
34827247.130: <09>Lane 03 new seed: 0047
34828247.130: <09>Lane 04 new seed: 0047
34829247.130: <09>Lane 05 new seed: 0047
34830247.130: <09>Lane 06 new seed: 0047
34831247.130: <09>Lane 07 new seed: 0047
34832247.130: <09>Lane 08 new seed: 0047
34833247.131: <09>Lane 00 nibble 1 raw readback: 004e
34834247.131: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004e
34835247.131: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
34836247.131: <09>Lane 01 nibble 1 raw readback: 004a
34837247.131: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
34838247.131: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
34839247.131: <09>Lane 02 nibble 1 raw readback: 0047
34840247.131: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
34841247.131: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
34842247.131: <09>Lane 03 nibble 1 raw readback: 0045
34843247.131: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
34844247.131: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
34845247.131: <09>Lane 04 nibble 1 raw readback: 003b
34846247.131: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
34847247.131: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
34848247.131: <09>Lane 05 nibble 1 raw readback: 003d
34849247.131: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
34850247.131: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
34851247.131: <09>Lane 06 nibble 1 raw readback: 0041
34852247.131: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
34853247.131: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
34854247.131: <09>Lane 07 nibble 1 raw readback: 0042
34855247.131: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
34856247.131: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
34857247.131: <09>Lane 08 nibble 1 raw readback: 003b
34858247.131: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
34859247.131: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
34860247.131: <09>original critical gross delay: 0
34861247.131: <09>new critical gross delay: 0
34862247.131: DIMM 0 RttNom: 3
34863247.131: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
34864247.131: DIMM 0 RttNom: 3
34865247.131: DIMM 0 RttWr: 2
34866247.131: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
34867247.131: DIMM 0 RttWr: 2
34868247.131: DIMM 0 RttNom: 3
34869247.131: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
34870247.131: DIMM 0 RttNom: 3
34871247.131: DIMM 0 RttWr: 2
34872247.131: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
34873247.131: DIMM 0 RttWr: 2
34874247.131: DIMM 1 RttNom: 3
34875247.131: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
34876247.131: DIMM 0 RttNom: 3
34877247.131: DIMM 1 RttWr: 2
34878247.131: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
34879247.131: DIMM 0 RttWr: 2
34880247.131: DIMM 1 RttNom: 3
34881247.131: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
34882247.131: DIMM 0 RttNom: 3
34883247.131: DIMM 1 RttWr: 2
34884247.131: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
34885247.131: DIMM 0 RttWr: 2
34886247.131: AgesaHwWlPhase1: training nibble 0
34887247.131: DIMM 1 RttNom: 3
34888247.131: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
34889247.131: DIMM 1 RttWr: 2
34890247.131: DIMM 1 RttWr: 2
34891247.131: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
34892247.131: DIMM 1 RttWr: 2
34893247.131: DIMM 1 RttNom: 3
34894247.131: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
34895247.131: DIMM 1 RttNom: 3
34896247.131: DIMM 1 RttWr: 2
34897247.132: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
34898247.132: DIMM 1 RttWr: 2
34899247.132: DIMM 0 RttNom: 3
34900247.132: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
34901247.132: DIMM 1 RttNom: 3
34902247.132: DIMM 0 RttWr: 2
34903247.132: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
34904247.132: DIMM 1 RttWr: 2
34905247.132: DIMM 0 RttNom: 3
34906247.132: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
34907247.132: DIMM 1 RttNom: 3
34908247.132: DIMM 0 RttWr: 2
34909247.132: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
34910247.132: DIMM 1 RttWr: 2
34911247.132: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
34912247.132: <09>Lane 00 scaled delay: 0047
34913247.132: <09>Lane 00 new seed: 0047
34914247.132: <09>Lane 01 scaled delay: 0047
34915247.132: <09>Lane 01 new seed: 0047
34916247.132: <09>Lane 02 scaled delay: 0047
34917247.132: <09>Lane 02 new seed: 0047
34918247.132: <09>Lane 03 scaled delay: 0047
34919247.132: <09>Lane 03 new seed: 0047
34920247.132: <09>Lane 04 scaled delay: 0047
34921247.132: <09>Lane 04 new seed: 0047
34922247.132: <09>Lane 05 scaled delay: 0047
34923247.132: <09>Lane 05 new seed: 0047
34924247.132: <09>Lane 06 scaled delay: 0047
34925247.132: <09>Lane 06 new seed: 0047
34926247.132: <09>Lane 07 scaled delay: 0047
34927247.132: <09>Lane 07 new seed: 0047
34928247.132: <09>Lane 08 scaled delay: 0047
34929247.132: <09>Lane 08 new seed: 0047
34930247.132: <09>Lane 00 nibble 0 raw readback: 0046
34931247.132: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
34932247.132: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
34933247.132: <09>Lane 01 nibble 0 raw readback: 003f
34934247.132: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
34935247.132: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
34936247.132: <09>Lane 02 nibble 0 raw readback: 003e
34937247.132: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
34938247.132: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
34939247.132: <09>Lane 03 nibble 0 raw readback: 003b
34940247.132: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
34941247.132: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
34942247.132: <09>Lane 04 nibble 0 raw readback: 0030
34943247.132: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
34944247.132: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
34945247.132: <09>Lane 05 nibble 0 raw readback: 0035
34946247.132: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
34947247.132: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
34948247.132: <09>Lane 06 nibble 0 raw readback: 0038
34949247.132: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0038
34950247.132: <09>Lane 06 nibble 0 adjusted value (post nibble): 0038
34951247.132: <09>Lane 07 nibble 0 raw readback: 003a
34952247.132: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
34953247.132: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
34954247.132: <09>Lane 08 nibble 0 raw readback: 0033
34955247.132: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
34956247.132: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
34957247.132: AgesaHwWlPhase1: training nibble 1
34958247.132: DIMM 1 RttNom: 3
34959247.132: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
34960247.132: DIMM 1 RttWr: 2
34961247.132: DIMM 1 RttWr: 2
34962247.132: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
34963247.132: DIMM 1 RttWr: 2
34964247.132: DIMM 1 RttNom: 3
34965247.132: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
34966247.132: DIMM 1 RttNom: 3
34967247.133: DIMM 1 RttWr: 2
34968247.133: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
34969247.133: DIMM 1 RttWr: 2
34970247.133: DIMM 0 RttNom: 3
34971247.133: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
34972247.133: DIMM 1 RttNom: 3
34973247.133: DIMM 0 RttWr: 2
34974247.133: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
34975247.133: DIMM 1 RttWr: 2
34976247.133: DIMM 0 RttNom: 3
34977247.133: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
34978247.133: DIMM 1 RttNom: 3
34979247.133: DIMM 0 RttWr: 2
34980247.133: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
34981247.133: DIMM 1 RttWr: 2
34982247.133: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
34983247.133: <09>Lane 00 new seed: 0047
34984247.133: <09>Lane 01 new seed: 0047
34985247.133: <09>Lane 02 new seed: 0047
34986247.133: <09>Lane 03 new seed: 0047
34987247.133: <09>Lane 04 new seed: 0047
34988247.133: <09>Lane 05 new seed: 0047
34989247.133: <09>Lane 06 new seed: 0047
34990247.133: <09>Lane 07 new seed: 0047
34991247.133: <09>Lane 08 new seed: 0047
34992247.133: <09>Lane 00 nibble 1 raw readback: 0044
34993247.133: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
34994247.133: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
34995247.133: <09>Lane 01 nibble 1 raw readback: 0040
34996247.133: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
34997247.133: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
34998247.133: <09>Lane 02 nibble 1 raw readback: 0040
34999247.133: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
35000247.133: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
35001247.133: <09>Lane 03 nibble 1 raw readback: 003d
35002247.133: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003d
35003247.133: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
35004247.133: <09>Lane 04 nibble 1 raw readback: 0031
35005247.133: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
35006247.133: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
35007247.133: <09>Lane 05 nibble 1 raw readback: 0034
35008247.133: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0034
35009247.133: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
35010247.133: <09>Lane 06 nibble 1 raw readback: 0037
35011247.133: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
35012247.133: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
35013247.133: <09>Lane 07 nibble 1 raw readback: 003a
35014247.133: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
35015247.133: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
35016247.133: <09>Lane 08 nibble 1 raw readback: 0033
35017247.133: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0033
35018247.133: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
35019247.133: <09>original critical gross delay: 0
35020247.133: <09>new critical gross delay: 0
35021247.133: DIMM 1 RttNom: 3
35022247.133: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35023247.133: DIMM 1 RttNom: 3
35024247.133: DIMM 1 RttWr: 2
35025247.133: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
35026247.133: DIMM 1 RttWr: 2
35027247.133: DIMM 1 RttNom: 3
35028247.133: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35029247.133: DIMM 1 RttNom: 3
35030247.134: DIMM 1 RttWr: 2
35031247.133: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
35032247.133: DIMM 1 RttWr: 2
35033247.134: DIMM 0 RttNom: 3
35034247.134: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35035247.134: DIMM 1 RttNom: 3
35036247.134: DIMM 0 RttWr: 2
35037247.134: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
35038247.134: DIMM 1 RttWr: 2
35039247.134: DIMM 0 RttNom: 3
35040247.134: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35041247.134: DIMM 1 RttNom: 3
35042247.134: DIMM 0 RttWr: 2
35043247.134: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
35044247.134: DIMM 1 RttWr: 2
35045247.134: SPD2ndTiming: Start
35046247.134: SPD2ndTiming: Done
35047247.134: mct_BeforeDramInit_Prod_D: Start
35048247.134: mct_ProgramODT_D: Start
35049247.134: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
35050247.134: mct_ProgramODT_D: Done
35051247.134: mct_BeforeDramInit_Prod_D: Done
35052247.134: mct_DramInit_Sw_D: Start
35053247.134: DIMM 0 RttWr: 2
35054247.134: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35055247.134: mct_SendMrsCmd: Start
35056247.134: mct_SendMrsCmd: Done
35057247.134: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
35058247.134: mct_SendMrsCmd: Start
35059247.135: mct_SendMrsCmd: Done
35060247.135: DIMM 0 RttNom: 3
35061247.135: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35062247.135: mct_SendMrsCmd: Start
35063247.135: mct_SendMrsCmd: Done
35064247.135: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
35065247.135: mct_SendMrsCmd: Start
35066247.135: mct_SendMrsCmd: Done
35067247.135: DIMM 0 RttWr: 2
35068247.135: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35069247.135: mct_SendMrsCmd: Start
35070247.135: mct_SendMrsCmd: Done
35071247.135: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
35072247.135: mct_SendMrsCmd: Start
35073247.135: mct_SendMrsCmd: Done
35074247.135: DIMM 0 RttNom: 3
35075247.135: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35076247.135: mct_SendMrsCmd: Start
35077247.135: mct_SendMrsCmd: Done
35078247.135: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
35079247.135: mct_SendMrsCmd: Start
35080247.135: mct_SendMrsCmd: Done
35081247.135: DIMM 1 RttWr: 2
35082247.135: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35083247.135: mct_SendMrsCmd: Start
35084247.135: mct_SendMrsCmd: Done
35085247.135: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
35086247.135: mct_SendMrsCmd: Start
35087247.135: mct_SendMrsCmd: Done
35088247.135: DIMM 1 RttNom: 3
35089247.135: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35090247.135: mct_SendMrsCmd: Start
35091247.135: mct_SendMrsCmd: Done
35092247.135: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
35093247.135: mct_SendMrsCmd: Start
35094247.135: mct_SendMrsCmd: Done
35095247.135: DIMM 1 RttWr: 2
35096247.135: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35097247.135: mct_SendMrsCmd: Start
35098247.135: mct_SendMrsCmd: Done
35099247.135: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
35100247.135: mct_SendMrsCmd: Start
35101247.135: mct_SendMrsCmd: Done
35102247.135: DIMM 1 RttNom: 3
35103247.135: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35104247.135: mct_SendMrsCmd: Start
35105247.135: mct_SendMrsCmd: Done
35106247.135: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
35107247.135: mct_SendMrsCmd: Start
35108247.135: mct_SendMrsCmd: Done
35109247.135: mct_DramInit_Sw_D: Done
35110247.135: AgesaHwWlPhase1: training nibble 0
35111247.135: DIMM 0 RttNom: 3
35112247.135: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35113247.135: DIMM 0 RttWr: 2
35114247.135: DIMM 0 RttWr: 2
35115247.135: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35116247.135: DIMM 0 RttWr: 2
35117247.135: DIMM 0 RttNom: 3
35118247.135: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35119247.135: DIMM 0 RttNom: 3
35120247.135: DIMM 0 RttWr: 2
35121247.135: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35122247.135: DIMM 0 RttWr: 2
35123247.135: DIMM 1 RttNom: 3
35124247.135: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35125247.135: DIMM 0 RttNom: 3
35126247.135: DIMM 1 RttWr: 2
35127247.135: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35128247.135: DIMM 0 RttWr: 2
35129247.135: DIMM 1 RttNom: 3
35130247.135: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35131247.136: DIMM 0 RttNom: 3
35132247.136: DIMM 1 RttWr: 2
35133247.136: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35134247.136: DIMM 0 RttWr: 2
35135247.136: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
35136247.136: <09>Lane 00 scaled delay: 0047
35137247.136: <09>Lane 00 new seed: 0047
35138247.136: <09>Lane 01 scaled delay: 0047
35139247.136: <09>Lane 01 new seed: 0047
35140247.136: <09>Lane 02 scaled delay: 0047
35141247.136: <09>Lane 02 new seed: 0047
35142247.136: <09>Lane 03 scaled delay: 0047
35143247.136: <09>Lane 03 new seed: 0047
35144247.136: <09>Lane 04 scaled delay: 0047
35145247.136: <09>Lane 04 new seed: 0047
35146247.136: <09>Lane 05 scaled delay: 0047
35147247.136: <09>Lane 05 new seed: 0047
35148247.136: <09>Lane 06 scaled delay: 0047
35149247.136: <09>Lane 06 new seed: 0047
35150247.136: <09>Lane 07 scaled delay: 0047
35151247.136: <09>Lane 07 new seed: 0047
35152247.136: <09>Lane 08 scaled delay: 0047
35153247.136: <09>Lane 08 new seed: 0047
35154247.136: <09>Lane 00 nibble 0 raw readback: 004d
35155247.136: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
35156247.136: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
35157247.136: <09>Lane 01 nibble 0 raw readback: 004a
35158247.136: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
35159247.136: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
35160247.136: <09>Lane 02 nibble 0 raw readback: 0046
35161247.136: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
35162247.136: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
35163247.136: <09>Lane 03 nibble 0 raw readback: 0044
35164247.136: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
35165247.136: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
35166247.136: <09>Lane 04 nibble 0 raw readback: 0039
35167247.136: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
35168247.136: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
35169247.136: <09>Lane 05 nibble 0 raw readback: 003d
35170247.136: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
35171247.136: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
35172247.136: <09>Lane 06 nibble 0 raw readback: 0040
35173247.136: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
35174247.136: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
35175247.136: <09>Lane 07 nibble 0 raw readback: 0041
35176247.136: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
35177247.136: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
35178247.136: <09>Lane 08 nibble 0 raw readback: 003b
35179247.136: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
35180247.136: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
35181247.136: AgesaHwWlPhase1: training nibble 1
35182247.136: DIMM 0 RttNom: 3
35183247.136: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35184247.136: DIMM 0 RttWr: 2
35185247.136: DIMM 0 RttWr: 2
35186247.137: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35187247.136: DIMM 0 RttWr: 2
35188247.137: DIMM 0 RttNom: 3
35189247.137: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35190247.137: DIMM 0 RttNom: 3
35191247.137: DIMM 0 RttWr: 2
35192247.137: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35193247.137: DIMM 0 RttWr: 2
35194247.137: DIMM 1 RttNom: 3
35195247.137: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35196247.137: DIMM 0 RttNom: 3
35197247.137: DIMM 1 RttWr: 2
35198247.137: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35199247.137: DIMM 0 RttWr: 2
35200247.137: DIMM 1 RttNom: 3
35201247.137: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35202247.137: DIMM 0 RttNom: 3
35203247.137: DIMM 1 RttWr: 2
35204247.137: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35205247.137: DIMM 0 RttWr: 2
35206247.137: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
35207247.137: <09>Lane 00 new seed: 0047
35208247.137: <09>Lane 01 new seed: 0047
35209247.137: <09>Lane 02 new seed: 0047
35210247.137: <09>Lane 03 new seed: 0047
35211247.137: <09>Lane 04 new seed: 0047
35212247.137: <09>Lane 05 new seed: 0047
35213247.137: <09>Lane 06 new seed: 0047
35214247.137: <09>Lane 07 new seed: 0047
35215247.137: <09>Lane 08 new seed: 0047
35216247.137: <09>Lane 00 nibble 1 raw readback: 004e
35217247.137: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004e
35218247.137: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
35219247.137: <09>Lane 01 nibble 1 raw readback: 004a
35220247.137: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
35221247.137: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
35222247.137: <09>Lane 02 nibble 1 raw readback: 0047
35223247.137: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
35224247.137: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
35225247.137: <09>Lane 03 nibble 1 raw readback: 0044
35226247.137: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
35227247.137: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
35228247.137: <09>Lane 04 nibble 1 raw readback: 0039
35229247.137: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
35230247.137: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
35231247.137: <09>Lane 05 nibble 1 raw readback: 003e
35232247.137: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
35233247.137: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
35234247.137: <09>Lane 06 nibble 1 raw readback: 0040
35235247.137: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
35236247.137: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
35237247.137: <09>Lane 07 nibble 1 raw readback: 0041
35238247.137: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
35239247.137: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
35240247.137: <09>Lane 08 nibble 1 raw readback: 003b
35241247.137: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
35242247.137: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
35243247.137: <09>original critical gross delay: 0
35244247.137: <09>new critical gross delay: 0
35245247.137: DIMM 0 RttNom: 3
35246247.137: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35247247.137: DIMM 0 RttNom: 3
35248247.137: DIMM 0 RttWr: 2
35249247.137: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35250247.137: DIMM 0 RttWr: 2
35251247.137: DIMM 0 RttNom: 3
35252247.138: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35253247.138: DIMM 0 RttNom: 3
35254247.138: DIMM 0 RttWr: 2
35255247.138: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35256247.138: DIMM 0 RttWr: 2
35257247.138: DIMM 1 RttNom: 3
35258247.138: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35259247.138: DIMM 0 RttNom: 3
35260247.138: DIMM 1 RttWr: 2
35261247.138: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35262247.138: DIMM 0 RttWr: 2
35263247.138: DIMM 1 RttNom: 3
35264247.138: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35265247.138: DIMM 0 RttNom: 3
35266247.138: DIMM 1 RttWr: 2
35267247.138: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35268247.138: DIMM 0 RttWr: 2
35269247.138: AgesaHwWlPhase1: training nibble 0
35270247.138: DIMM 1 RttNom: 3
35271247.138: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35272247.138: DIMM 1 RttWr: 2
35273247.138: DIMM 1 RttWr: 2
35274247.138: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35275247.138: DIMM 1 RttWr: 2
35276247.138: DIMM 1 RttNom: 3
35277247.138: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35278247.138: DIMM 1 RttNom: 3
35279247.138: DIMM 1 RttWr: 2
35280247.138: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35281247.138: DIMM 1 RttWr: 2
35282247.138: DIMM 0 RttNom: 3
35283247.138: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35284247.138: DIMM 1 RttNom: 3
35285247.138: DIMM 0 RttWr: 2
35286247.138: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35287247.138: DIMM 1 RttWr: 2
35288247.138: DIMM 0 RttNom: 3
35289247.138: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35290247.138: DIMM 1 RttNom: 3
35291247.138: DIMM 0 RttWr: 2
35292247.138: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35293247.138: DIMM 1 RttWr: 2
35294247.138: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
35295247.138: <09>Lane 00 scaled delay: 0047
35296247.138: <09>Lane 00 new seed: 0047
35297247.138: <09>Lane 01 scaled delay: 0047
35298247.138: <09>Lane 01 new seed: 0047
35299247.138: <09>Lane 02 scaled delay: 0047
35300247.138: <09>Lane 02 new seed: 0047
35301247.138: <09>Lane 03 scaled delay: 0047
35302247.138: <09>Lane 03 new seed: 0047
35303247.138: <09>Lane 04 scaled delay: 0047
35304247.138: <09>Lane 04 new seed: 0047
35305247.138: <09>Lane 05 scaled delay: 0047
35306247.138: <09>Lane 05 new seed: 0047
35307247.138: <09>Lane 06 scaled delay: 0047
35308247.138: <09>Lane 06 new seed: 0047
35309247.138: <09>Lane 07 scaled delay: 0047
35310247.138: <09>Lane 07 new seed: 0047
35311247.138: <09>Lane 08 scaled delay: 0047
35312247.138: <09>Lane 08 new seed: 0047
35313247.138: <09>Lane 00 nibble 0 raw readback: 0044
35314247.138: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
35315247.138: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
35316247.139: <09>Lane 01 nibble 0 raw readback: 0040
35317247.138: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
35318247.139: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
35319247.139: <09>Lane 02 nibble 0 raw readback: 003d
35320247.139: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
35321247.139: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
35322247.139: <09>Lane 03 nibble 0 raw readback: 003a
35323247.139: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
35324247.139: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
35325247.139: <09>Lane 04 nibble 0 raw readback: 002f
35326247.139: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
35327247.139: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
35328247.139: <09>Lane 05 nibble 0 raw readback: 0033
35329247.139: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0033
35330247.139: <09>Lane 05 nibble 0 adjusted value (post nibble): 0033
35331247.139: <09>Lane 06 nibble 0 raw readback: 0036
35332247.139: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0036
35333247.139: <09>Lane 06 nibble 0 adjusted value (post nibble): 0036
35334247.139: <09>Lane 07 nibble 0 raw readback: 0039
35335247.139: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
35336247.139: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
35337247.139: <09>Lane 08 nibble 0 raw readback: 0032
35338247.139: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
35339247.139: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
35340247.139: AgesaHwWlPhase1: training nibble 1
35341247.139: DIMM 1 RttNom: 3
35342247.139: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35343247.139: DIMM 1 RttWr: 2
35344247.139: DIMM 1 RttWr: 2
35345247.139: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35346247.139: DIMM 1 RttWr: 2
35347247.139: DIMM 1 RttNom: 3
35348247.139: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35349247.139: DIMM 1 RttNom: 3
35350247.139: DIMM 1 RttWr: 2
35351247.139: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35352247.139: DIMM 1 RttWr: 2
35353247.139: DIMM 0 RttNom: 3
35354247.139: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35355247.139: DIMM 1 RttNom: 3
35356247.139: DIMM 0 RttWr: 2
35357247.139: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35358247.139: DIMM 1 RttWr: 2
35359247.139: DIMM 0 RttNom: 3
35360247.139: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35361247.139: DIMM 1 RttNom: 3
35362247.139: DIMM 0 RttWr: 2
35363247.139: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35364247.139: DIMM 1 RttWr: 2
35365247.139: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
35366247.139: <09>Lane 00 new seed: 0047
35367247.139: <09>Lane 01 new seed: 0047
35368247.139: <09>Lane 02 new seed: 0047
35369247.139: <09>Lane 03 new seed: 0047
35370247.139: <09>Lane 04 new seed: 0047
35371247.139: <09>Lane 05 new seed: 0047
35372247.139: <09>Lane 06 new seed: 0047
35373247.139: <09>Lane 07 new seed: 0047
35374247.139: <09>Lane 08 new seed: 0047
35375247.139: <09>Lane 00 nibble 1 raw readback: 0043
35376247.139: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
35377247.139: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
35378247.139: <09>Lane 01 nibble 1 raw readback: 0040
35379247.139: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
35380247.139: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
35381247.139: <09>Lane 02 nibble 1 raw readback: 003d
35382247.139: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
35383247.139: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
35384247.139: <09>Lane 03 nibble 1 raw readback: 003b
35385247.139: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
35386247.139: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
35387247.139: <09>Lane 04 nibble 1 raw readback: 0030
35388247.139: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
35389247.139: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
35390247.139: <09>Lane 05 nibble 1 raw readback: 0033
35391247.140: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0033
35392247.140: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
35393247.140: <09>Lane 06 nibble 1 raw readback: 0036
35394247.140: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0036
35395247.140: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
35396247.140: <09>Lane 07 nibble 1 raw readback: 0039
35397247.140: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
35398247.140: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
35399247.140: <09>Lane 08 nibble 1 raw readback: 0032
35400247.140: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
35401247.140: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
35402247.140: <09>original critical gross delay: 0
35403247.140: <09>new critical gross delay: 0
35404247.140: DIMM 1 RttNom: 3
35405247.140: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35406247.140: DIMM 1 RttNom: 3
35407247.140: DIMM 1 RttWr: 2
35408247.140: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
35409247.140: DIMM 1 RttWr: 2
35410247.140: DIMM 1 RttNom: 3
35411247.140: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35412247.140: DIMM 1 RttNom: 3
35413247.140: DIMM 1 RttWr: 2
35414247.140: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
35415247.140: DIMM 1 RttWr: 2
35416247.140: DIMM 0 RttNom: 3
35417247.140: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35418247.140: DIMM 1 RttNom: 3
35419247.140: DIMM 0 RttWr: 2
35420247.140: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
35421247.140: DIMM 1 RttWr: 2
35422247.140: DIMM 0 RttNom: 3
35423247.140: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35424247.140: DIMM 1 RttNom: 3
35425247.140: DIMM 0 RttWr: 2
35426247.140: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
35427247.140: DIMM 1 RttWr: 2
35428247.140: SetTargetFreq: Start
35429247.140: SetTargetFreq: Node 2: New frequency code: 000a
35430247.140: ChangeMemClk: Start
35431247.140: set_2t_configuration: Start
35432247.140: set_2t_configuration: Done
35433247.140: mct_BeforePlatformSpec: Start
35434247.140: mct_BeforePlatformSpec: Done
35435247.141: mct_PlatformSpec: Start
35436247.141: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
35437247.141: mct_PlatformSpec: Done
35438247.141: set_2t_configuration: Start
35439247.141: set_2t_configuration: Done
35440247.141: mct_BeforePlatformSpec: Start
35441247.141: mct_BeforePlatformSpec: Done
35442247.141: mct_PlatformSpec: Start
35443247.141: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
35444247.141: mct_PlatformSpec: Done
35445247.141: ChangeMemClk: Done
35446247.141: phyAssistedMemFnceTraining: Start
35447247.141: phyAssistedMemFnceTraining: training node 2 DCT 0
35448247.141: phyAssistedMemFnceTraining: done training node 2 DCT 0
35449247.141: phyAssistedMemFnceTraining: training node 2 DCT 1
35450247.141: phyAssistedMemFnceTraining: done training node 2 DCT 1
35451247.141: phyAssistedMemFnceTraining: Done
35452247.141: InitPhyCompensation: DCT 0: Start
35453247.141: Waiting for predriver calibration to be applied...done!
35454247.141: InitPhyCompensation: DCT 0: Done
35455247.141: phyAssistedMemFnceTraining: Start
35456247.141: phyAssistedMemFnceTraining: training node 2 DCT 0
35457247.141: phyAssistedMemFnceTraining: done training node 2 DCT 0
35458247.141: phyAssistedMemFnceTraining: training node 2 DCT 1
35459247.141: phyAssistedMemFnceTraining: done training node 2 DCT 1
35460247.141: phyAssistedMemFnceTraining: Done
35461247.141: InitPhyCompensation: DCT 1: Start
35462247.142: Waiting for predriver calibration to be applied...done!
35463247.142: InitPhyCompensation: DCT 1: Done
35464247.142: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
35465247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
35466247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
35467247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
35468247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
35469247.142: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
35470247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
35471247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
35472247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
35473247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
35474247.142: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
35475247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
35476247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
35477247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
35478247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
35479247.142: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
35480247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
35481247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
35482247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
35483247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
35484247.142: SetTargetFreq: Done
35485247.142: SPD2ndTiming: Start
35486247.143: SPD2ndTiming: Done
35487247.143: mct_BeforeDramInit_Prod_D: Start
35488247.143: mct_ProgramODT_D: Start
35489247.143: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
35490247.143: mct_ProgramODT_D: Done
35491247.143: mct_BeforeDramInit_Prod_D: Done
35492247.143: mct_DramInit_Sw_D: Start
35493247.143: DIMM 0 RttWr: 1
35494247.143: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35495247.143: mct_SendMrsCmd: Start
35496247.143: mct_SendMrsCmd: Done
35497247.143: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
35498247.143: mct_SendMrsCmd: Start
35499247.143: mct_SendMrsCmd: Done
35500247.143: DIMM 0 RttNom: 3
35501247.143: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35502247.143: mct_SendMrsCmd: Start
35503247.143: mct_SendMrsCmd: Done
35504247.143: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
35505247.143: mct_SendMrsCmd: Start
35506247.143: mct_SendMrsCmd: Done
35507247.143: DIMM 0 RttWr: 1
35508247.143: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35509247.143: mct_SendMrsCmd: Start
35510247.143: mct_SendMrsCmd: Done
35511247.143: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
35512247.143: mct_SendMrsCmd: Start
35513247.143: mct_SendMrsCmd: Done
35514247.143: DIMM 0 RttNom: 3
35515247.143: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35516247.143: mct_SendMrsCmd: Start
35517247.143: mct_SendMrsCmd: Done
35518247.143: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
35519247.143: mct_SendMrsCmd: Start
35520247.143: mct_SendMrsCmd: Done
35521247.143: DIMM 1 RttWr: 1
35522247.143: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35523247.143: mct_SendMrsCmd: Start
35524247.143: mct_SendMrsCmd: Done
35525247.143: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
35526247.143: mct_SendMrsCmd: Start
35527247.143: mct_SendMrsCmd: Done
35528247.143: DIMM 1 RttNom: 3
35529247.143: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35530247.143: mct_SendMrsCmd: Start
35531247.143: mct_SendMrsCmd: Done
35532247.143: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
35533247.143: mct_SendMrsCmd: Start
35534247.143: mct_SendMrsCmd: Done
35535247.143: DIMM 1 RttWr: 1
35536247.143: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35537247.143: mct_SendMrsCmd: Start
35538247.143: mct_SendMrsCmd: Done
35539247.143: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
35540247.144: mct_SendMrsCmd: Start
35541247.143: mct_SendMrsCmd: Done
35542247.143: DIMM 1 RttNom: 3
35543247.143: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35544247.143: mct_SendMrsCmd: Start
35545247.143: mct_SendMrsCmd: Done
35546247.143: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
35547247.143: mct_SendMrsCmd: Start
35548247.143: mct_SendMrsCmd: Done
35549247.143: mct_DramInit_Sw_D: Done
35550247.144: AgesaHwWlPhase1: training nibble 0
35551247.144: DIMM 0 RttNom: 3
35552247.144: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35553247.144: DIMM 0 RttWr: 1
35554247.144: DIMM 0 RttWr: 1
35555247.144: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35556247.144: DIMM 0 RttWr: 1
35557247.144: DIMM 0 RttNom: 3
35558247.144: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35559247.144: DIMM 0 RttNom: 3
35560247.144: DIMM 0 RttWr: 1
35561247.144: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35562247.144: DIMM 0 RttWr: 1
35563247.144: DIMM 1 RttNom: 3
35564247.144: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35565247.144: DIMM 0 RttNom: 3
35566247.144: DIMM 1 RttWr: 1
35567247.144: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35568247.144: DIMM 0 RttWr: 1
35569247.144: DIMM 1 RttNom: 3
35570247.144: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35571247.144: DIMM 0 RttNom: 3
35572247.144: DIMM 1 RttWr: 1
35573247.144: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35574247.144: DIMM 0 RttWr: 1
35575247.144: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
35576247.144: <09>Lane 00 scaled delay: 0057
35577247.144: <09>Lane 00 new seed: 0057
35578247.144: <09>Lane 01 scaled delay: 0055
35579247.144: <09>Lane 01 new seed: 0055
35580247.144: <09>Lane 02 scaled delay: 0053
35581247.144: <09>Lane 02 new seed: 0053
35582247.144: <09>Lane 03 scaled delay: 0052
35583247.144: <09>Lane 03 new seed: 0052
35584247.144: <09>Lane 04 scaled delay: 004b
35585247.144: <09>Lane 04 new seed: 004b
35586247.144: <09>Lane 05 scaled delay: 004d
35587247.144: <09>Lane 05 new seed: 004d
35588247.144: <09>Lane 06 scaled delay: 004f
35589247.144: <09>Lane 06 new seed: 004f
35590247.144: <09>Lane 07 scaled delay: 004f
35591247.144: <09>Lane 07 new seed: 004f
35592247.145: <09>Lane 08 scaled delay: 004b
35593247.145: <09>Lane 08 new seed: 004b
35594247.145: <09>Lane 00 nibble 0 raw readback: 0060
35595247.145: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
35596247.145: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
35597247.145: <09>Lane 01 nibble 0 raw readback: 0057
35598247.145: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0057
35599247.145: <09>Lane 01 nibble 0 adjusted value (post nibble): 0057
35600247.145: <09>Lane 02 nibble 0 raw readback: 0055
35601247.145: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
35602247.145: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
35603247.145: <09>Lane 03 nibble 0 raw readback: 0051
35604247.145: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
35605247.145: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
35606247.145: <09>Lane 04 nibble 0 raw readback: 0044
35607247.145: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
35608247.145: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
35609247.145: <09>Lane 05 nibble 0 raw readback: 0049
35610247.145: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
35611247.145: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
35612247.145: <09>Lane 06 nibble 0 raw readback: 004d
35613247.145: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
35614247.145: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
35615247.145: <09>Lane 07 nibble 0 raw readback: 0051
35616247.145: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0051
35617247.145: <09>Lane 07 nibble 0 adjusted value (post nibble): 0051
35618247.145: <09>Lane 08 nibble 0 raw readback: 0046
35619247.145: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0046
35620247.145: <09>Lane 08 nibble 0 adjusted value (post nibble): 0046
35621247.145: AgesaHwWlPhase1: training nibble 1
35622247.145: DIMM 0 RttNom: 3
35623247.145: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35624247.145: DIMM 0 RttWr: 1
35625247.145: DIMM 0 RttWr: 1
35626247.145: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35627247.145: DIMM 0 RttWr: 1
35628247.145: DIMM 0 RttNom: 3
35629247.145: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35630247.145: DIMM 0 RttNom: 3
35631247.145: DIMM 0 RttWr: 1
35632247.145: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35633247.145: DIMM 0 RttWr: 1
35634247.145: DIMM 1 RttNom: 3
35635247.145: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35636247.145: DIMM 0 RttNom: 3
35637247.145: DIMM 1 RttWr: 1
35638247.145: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35639247.145: DIMM 0 RttWr: 1
35640247.145: DIMM 1 RttNom: 3
35641247.145: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35642247.145: DIMM 0 RttNom: 3
35643247.145: DIMM 1 RttWr: 1
35644247.145: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35645247.145: DIMM 0 RttWr: 1
35646247.145: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
35647247.145: <09>Lane 00 new seed: 0057
35648247.145: <09>Lane 01 new seed: 0055
35649247.145: <09>Lane 02 new seed: 0053
35650247.145: <09>Lane 03 new seed: 0052
35651247.145: <09>Lane 04 new seed: 004b
35652247.145: <09>Lane 05 new seed: 004d
35653247.145: <09>Lane 06 new seed: 004f
35654247.146: <09>Lane 07 new seed: 004f
35655247.146: <09>Lane 08 new seed: 004b
35656247.146: <09>Lane 00 nibble 1 raw readback: 005f
35657247.146: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
35658247.146: <09>Lane 00 nibble 1 adjusted value (post nibble): 005b
35659247.146: <09>Lane 01 nibble 1 raw readback: 0059
35660247.146: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
35661247.146: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
35662247.146: <09>Lane 02 nibble 1 raw readback: 0056
35663247.146: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
35664247.146: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
35665247.146: <09>Lane 03 nibble 1 raw readback: 0052
35666247.146: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
35667247.146: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
35668247.146: <09>Lane 04 nibble 1 raw readback: 0043
35669247.146: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
35670247.146: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
35671247.146: <09>Lane 05 nibble 1 raw readback: 0048
35672247.146: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
35673247.146: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
35674247.146: <09>Lane 06 nibble 1 raw readback: 004e
35675247.146: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
35676247.146: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
35677247.146: <09>Lane 07 nibble 1 raw readback: 0050
35678247.146: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
35679247.146: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
35680247.146: <09>Lane 08 nibble 1 raw readback: 0045
35681247.146: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
35682247.146: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
35683247.146: <09>original critical gross delay: 0
35684247.146: <09>new critical gross delay: 0
35685247.146: DIMM 0 RttNom: 3
35686247.146: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35687247.146: DIMM 0 RttNom: 3
35688247.146: DIMM 0 RttWr: 1
35689247.146: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35690247.146: DIMM 0 RttWr: 1
35691247.146: DIMM 0 RttNom: 3
35692247.146: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35693247.146: DIMM 0 RttNom: 3
35694247.146: DIMM 0 RttWr: 1
35695247.146: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35696247.146: DIMM 0 RttWr: 1
35697247.146: DIMM 1 RttNom: 3
35698247.146: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35699247.146: DIMM 0 RttNom: 3
35700247.146: DIMM 1 RttWr: 1
35701247.146: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35702247.146: DIMM 0 RttWr: 1
35703247.146: DIMM 1 RttNom: 3
35704247.146: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35705247.146: DIMM 0 RttNom: 3
35706247.146: DIMM 1 RttWr: 1
35707247.146: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35708247.146: DIMM 0 RttWr: 1
35709247.146: AgesaHwWlPhase1: training nibble 0
35710247.146: DIMM 1 RttNom: 3
35711247.146: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35712247.146: DIMM 1 RttWr: 1
35713247.147: DIMM 1 RttWr: 1
35714247.146: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35715247.146: DIMM 1 RttWr: 1
35716247.147: DIMM 1 RttNom: 3
35717247.147: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35718247.147: DIMM 1 RttNom: 3
35719247.147: DIMM 1 RttWr: 1
35720247.147: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35721247.147: DIMM 1 RttWr: 1
35722247.147: DIMM 0 RttNom: 3
35723247.147: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35724247.147: DIMM 1 RttNom: 3
35725247.147: DIMM 0 RttWr: 1
35726247.147: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35727247.147: DIMM 1 RttWr: 1
35728247.147: DIMM 0 RttNom: 3
35729247.147: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35730247.147: DIMM 1 RttNom: 3
35731247.147: DIMM 0 RttWr: 1
35732247.147: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35733247.147: DIMM 1 RttWr: 1
35734247.147: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
35735247.147: <09>Lane 00 scaled delay: 0051
35736247.147: <09>Lane 00 new seed: 0051
35737247.147: <09>Lane 01 scaled delay: 004e
35738247.147: <09>Lane 01 new seed: 004e
35739247.147: <09>Lane 02 scaled delay: 004e
35740247.147: <09>Lane 02 new seed: 004e
35741247.147: <09>Lane 03 scaled delay: 004d
35742247.147: <09>Lane 03 new seed: 004d
35743247.147: <09>Lane 04 scaled delay: 0045
35744247.147: <09>Lane 04 new seed: 0045
35745247.147: <09>Lane 05 scaled delay: 0046
35746247.147: <09>Lane 05 new seed: 0046
35747247.147: <09>Lane 06 scaled delay: 0049
35748247.147: <09>Lane 06 new seed: 0049
35749247.147: <09>Lane 07 scaled delay: 004a
35750247.147: <09>Lane 07 new seed: 004a
35751247.147: <09>Lane 08 scaled delay: 0046
35752247.147: <09>Lane 08 new seed: 0046
35753247.147: <09>Lane 00 nibble 0 raw readback: 0054
35754247.147: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0054
35755247.147: <09>Lane 00 nibble 0 adjusted value (post nibble): 0054
35756247.147: <09>Lane 01 nibble 0 raw readback: 004b
35757247.147: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
35758247.147: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
35759247.147: <09>Lane 02 nibble 0 raw readback: 0048
35760247.147: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
35761247.147: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
35762247.147: <09>Lane 03 nibble 0 raw readback: 0044
35763247.147: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
35764247.147: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
35765247.147: <09>Lane 04 nibble 0 raw readback: 0035
35766247.147: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0035
35767247.147: <09>Lane 04 nibble 0 adjusted value (post nibble): 0035
35768247.147: <09>Lane 05 nibble 0 raw readback: 003d
35769247.147: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
35770247.147: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
35771247.147: <09>Lane 06 nibble 0 raw readback: 0040
35772247.147: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
35773247.147: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
35774247.147: <09>Lane 07 nibble 0 raw readback: 0044
35775247.147: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
35776247.147: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
35777247.147: <09>Lane 08 nibble 0 raw readback: 0039
35778247.147: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
35779247.147: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
35780247.147: AgesaHwWlPhase1: training nibble 1
35781247.147: DIMM 1 RttNom: 3
35782247.147: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35783247.147: DIMM 1 RttWr: 1
35784247.147: DIMM 1 RttWr: 1
35785247.147: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35786247.147: DIMM 1 RttWr: 1
35787247.147: DIMM 1 RttNom: 3
35788247.148: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35789247.148: DIMM 1 RttNom: 3
35790247.148: DIMM 1 RttWr: 1
35791247.148: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35792247.148: DIMM 1 RttWr: 1
35793247.148: DIMM 0 RttNom: 3
35794247.148: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35795247.148: DIMM 1 RttNom: 3
35796247.148: DIMM 0 RttWr: 1
35797247.148: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35798247.148: DIMM 1 RttWr: 1
35799247.148: DIMM 0 RttNom: 3
35800247.148: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35801247.148: DIMM 1 RttNom: 3
35802247.148: DIMM 0 RttWr: 1
35803247.148: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35804247.148: DIMM 1 RttWr: 1
35805247.148: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
35806247.148: <09>Lane 00 new seed: 0051
35807247.148: <09>Lane 01 new seed: 004e
35808247.148: <09>Lane 02 new seed: 004e
35809247.148: <09>Lane 03 new seed: 004d
35810247.148: <09>Lane 04 new seed: 0045
35811247.148: <09>Lane 05 new seed: 0046
35812247.148: <09>Lane 06 new seed: 0049
35813247.148: <09>Lane 07 new seed: 004a
35814247.148: <09>Lane 08 new seed: 0046
35815247.148: <09>Lane 00 nibble 1 raw readback: 0052
35816247.148: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0052
35817247.148: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
35818247.148: <09>Lane 01 nibble 1 raw readback: 004b
35819247.148: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004b
35820247.148: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
35821247.148: <09>Lane 02 nibble 1 raw readback: 004b
35822247.148: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004b
35823247.148: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
35824247.148: <09>Lane 03 nibble 1 raw readback: 0046
35825247.148: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
35826247.148: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
35827247.148: <09>Lane 04 nibble 1 raw readback: 0038
35828247.148: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
35829247.148: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
35830247.148: <09>Lane 05 nibble 1 raw readback: 003c
35831247.148: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
35832247.148: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
35833247.148: <09>Lane 06 nibble 1 raw readback: 0040
35834247.148: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
35835247.148: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
35836247.148: <09>Lane 07 nibble 1 raw readback: 0045
35837247.148: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
35838247.148: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
35839247.148: <09>Lane 08 nibble 1 raw readback: 003a
35840247.148: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
35841247.148: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
35842247.148: <09>original critical gross delay: 0
35843247.148: <09>new critical gross delay: 0
35844247.148: DIMM 1 RttNom: 3
35845247.148: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
35846247.148: DIMM 1 RttNom: 3
35847247.148: DIMM 1 RttWr: 1
35848247.148: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
35849247.148: DIMM 1 RttWr: 1
35850247.148: DIMM 1 RttNom: 3
35851247.148: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
35852247.148: DIMM 1 RttNom: 3
35853247.149: DIMM 1 RttWr: 1
35854247.149: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
35855247.149: DIMM 1 RttWr: 1
35856247.149: DIMM 0 RttNom: 3
35857247.149: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
35858247.149: DIMM 1 RttNom: 3
35859247.149: DIMM 0 RttWr: 1
35860247.149: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
35861247.149: DIMM 1 RttWr: 1
35862247.149: DIMM 0 RttNom: 3
35863247.149: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
35864247.149: DIMM 1 RttNom: 3
35865247.149: DIMM 0 RttWr: 1
35866247.149: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
35867247.149: DIMM 1 RttWr: 1
35868247.149: SPD2ndTiming: Start
35869247.149: SPD2ndTiming: Done
35870247.149: mct_BeforeDramInit_Prod_D: Start
35871247.149: mct_ProgramODT_D: Start
35872247.149: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
35873247.149: mct_ProgramODT_D: Done
35874247.149: mct_BeforeDramInit_Prod_D: Done
35875247.149: mct_DramInit_Sw_D: Start
35876247.149: DIMM 0 RttWr: 1
35877247.149: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
35878247.149: mct_SendMrsCmd: Start
35879247.149: mct_SendMrsCmd: Done
35880247.149: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
35881247.149: mct_SendMrsCmd: Start
35882247.149: mct_SendMrsCmd: Done
35883247.149: DIMM 0 RttNom: 3
35884247.149: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35885247.149: mct_SendMrsCmd: Start
35886247.149: mct_SendMrsCmd: Done
35887247.150: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
35888247.150: mct_SendMrsCmd: Start
35889247.150: mct_SendMrsCmd: Done
35890247.150: DIMM 0 RttWr: 1
35891247.150: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
35892247.150: mct_SendMrsCmd: Start
35893247.150: mct_SendMrsCmd: Done
35894247.150: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
35895247.150: mct_SendMrsCmd: Start
35896247.150: mct_SendMrsCmd: Done
35897247.150: DIMM 0 RttNom: 3
35898247.150: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35899247.150: mct_SendMrsCmd: Start
35900247.150: mct_SendMrsCmd: Done
35901247.150: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
35902247.150: mct_SendMrsCmd: Start
35903247.150: mct_SendMrsCmd: Done
35904247.150: DIMM 1 RttWr: 1
35905247.150: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
35906247.150: mct_SendMrsCmd: Start
35907247.150: mct_SendMrsCmd: Done
35908247.150: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
35909247.150: mct_SendMrsCmd: Start
35910247.150: mct_SendMrsCmd: Done
35911247.150: DIMM 1 RttNom: 3
35912247.150: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35913247.150: mct_SendMrsCmd: Start
35914247.150: mct_SendMrsCmd: Done
35915247.150: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
35916247.150: mct_SendMrsCmd: Start
35917247.150: mct_SendMrsCmd: Done
35918247.150: DIMM 1 RttWr: 1
35919247.150: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
35920247.150: mct_SendMrsCmd: Start
35921247.150: mct_SendMrsCmd: Done
35922247.150: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
35923247.150: mct_SendMrsCmd: Start
35924247.150: mct_SendMrsCmd: Done
35925247.150: DIMM 1 RttNom: 3
35926247.150: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35927247.150: mct_SendMrsCmd: Start
35928247.150: mct_SendMrsCmd: Done
35929247.150: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
35930247.150: mct_SendMrsCmd: Start
35931247.150: mct_SendMrsCmd: Done
35932247.150: mct_DramInit_Sw_D: Done
35933247.150: AgesaHwWlPhase1: training nibble 0
35934247.150: DIMM 0 RttNom: 3
35935247.150: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
35936247.150: DIMM 0 RttWr: 1
35937247.150: DIMM 0 RttWr: 1
35938247.150: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
35939247.150: DIMM 0 RttWr: 1
35940247.150: DIMM 0 RttNom: 3
35941247.150: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
35942247.150: DIMM 0 RttNom: 3
35943247.150: DIMM 0 RttWr: 1
35944247.150: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
35945247.150: DIMM 0 RttWr: 1
35946247.150: DIMM 1 RttNom: 3
35947247.150: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
35948247.150: DIMM 0 RttNom: 3
35949247.150: DIMM 1 RttWr: 1
35950247.150: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
35951247.150: DIMM 0 RttWr: 1
35952247.150: DIMM 1 RttNom: 3
35953247.150: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
35954247.151: DIMM 0 RttNom: 3
35955247.151: DIMM 1 RttWr: 1
35956247.151: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
35957247.151: DIMM 0 RttWr: 1
35958247.151: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
35959247.151: <09>Lane 00 scaled delay: 0057
35960247.151: <09>Lane 00 new seed: 0057
35961247.151: <09>Lane 01 scaled delay: 0055
35962247.151: <09>Lane 01 new seed: 0055
35963247.151: <09>Lane 02 scaled delay: 0053
35964247.151: <09>Lane 02 new seed: 0053
35965247.151: <09>Lane 03 scaled delay: 0051
35966247.151: <09>Lane 03 new seed: 0051
35967247.151: <09>Lane 04 scaled delay: 004a
35968247.151: <09>Lane 04 new seed: 004a
35969247.151: <09>Lane 05 scaled delay: 004d
35970247.151: <09>Lane 05 new seed: 004d
35971247.151: <09>Lane 06 scaled delay: 004e
35972247.151: <09>Lane 06 new seed: 004e
35973247.151: <09>Lane 07 scaled delay: 004f
35974247.151: <09>Lane 07 new seed: 004f
35975247.151: <09>Lane 08 scaled delay: 004b
35976247.151: <09>Lane 08 new seed: 004b
35977247.151: <09>Lane 00 nibble 0 raw readback: 005c
35978247.151: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
35979247.151: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
35980247.151: <09>Lane 01 nibble 0 raw readback: 0058
35981247.151: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
35982247.151: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
35983247.151: <09>Lane 02 nibble 0 raw readback: 0053
35984247.151: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
35985247.151: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
35986247.151: <09>Lane 03 nibble 0 raw readback: 004f
35987247.151: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
35988247.151: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
35989247.151: <09>Lane 04 nibble 0 raw readback: 0041
35990247.151: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
35991247.151: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
35992247.151: <09>Lane 05 nibble 0 raw readback: 0046
35993247.151: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
35994247.151: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
35995247.151: <09>Lane 06 nibble 0 raw readback: 004b
35996247.151: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
35997247.151: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
35998247.151: <09>Lane 07 nibble 0 raw readback: 004d
35999247.151: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
36000247.151: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
36001247.151: <09>Lane 08 nibble 0 raw readback: 0044
36002247.151: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0044
36003247.151: <09>Lane 08 nibble 0 adjusted value (post nibble): 0044
36004247.151: AgesaHwWlPhase1: training nibble 1
36005247.151: DIMM 0 RttNom: 3
36006247.151: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
36007247.151: DIMM 0 RttWr: 1
36008247.151: DIMM 0 RttWr: 1
36009247.151: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
36010247.151: DIMM 0 RttWr: 1
36011247.151: DIMM 0 RttNom: 3
36012247.151: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
36013247.151: DIMM 0 RttNom: 3
36014247.151: DIMM 0 RttWr: 1
36015247.151: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
36016247.151: DIMM 0 RttWr: 1
36017247.152: DIMM 1 RttNom: 3
36018247.152: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
36019247.152: DIMM 0 RttNom: 3
36020247.152: DIMM 1 RttWr: 1
36021247.152: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
36022247.152: DIMM 0 RttWr: 1
36023247.152: DIMM 1 RttNom: 3
36024247.152: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
36025247.152: DIMM 0 RttNom: 3
36026247.152: DIMM 1 RttWr: 1
36027247.152: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
36028247.152: DIMM 0 RttWr: 1
36029247.152: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
36030247.152: <09>Lane 00 new seed: 0057
36031247.152: <09>Lane 01 new seed: 0055
36032247.152: <09>Lane 02 new seed: 0053
36033247.152: <09>Lane 03 new seed: 0051
36034247.152: <09>Lane 04 new seed: 004a
36035247.152: <09>Lane 05 new seed: 004d
36036247.152: <09>Lane 06 new seed: 004e
36037247.152: <09>Lane 07 new seed: 004f
36038247.152: <09>Lane 08 new seed: 004b
36039247.152: <09>Lane 00 nibble 1 raw readback: 005d
36040247.152: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
36041247.152: <09>Lane 00 nibble 1 adjusted value (post nibble): 005a
36042247.152: <09>Lane 01 nibble 1 raw readback: 0058
36043247.152: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
36044247.152: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
36045247.152: <09>Lane 02 nibble 1 raw readback: 0054
36046247.152: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
36047247.152: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
36048247.152: <09>Lane 03 nibble 1 raw readback: 0051
36049247.152: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
36050247.152: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
36051247.152: <09>Lane 04 nibble 1 raw readback: 0041
36052247.152: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
36053247.152: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
36054247.152: <09>Lane 05 nibble 1 raw readback: 0047
36055247.152: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
36056247.152: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
36057247.152: <09>Lane 06 nibble 1 raw readback: 004b
36058247.152: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004b
36059247.152: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
36060247.152: <09>Lane 07 nibble 1 raw readback: 004d
36061247.152: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
36062247.152: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
36063247.152: <09>Lane 08 nibble 1 raw readback: 0045
36064247.152: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
36065247.152: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
36066247.152: <09>original critical gross delay: 0
36067247.152: <09>new critical gross delay: 0
36068247.152: DIMM 0 RttNom: 3
36069247.152: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
36070247.152: DIMM 0 RttNom: 3
36071247.152: DIMM 0 RttWr: 1
36072247.152: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
36073247.152: DIMM 0 RttWr: 1
36074247.152: DIMM 0 RttNom: 3
36075247.152: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
36076247.152: DIMM 0 RttNom: 3
36077247.152: DIMM 0 RttWr: 1
36078247.152: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
36079247.153: DIMM 0 RttWr: 1
36080247.153: DIMM 1 RttNom: 3
36081247.153: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
36082247.153: DIMM 0 RttNom: 3
36083247.153: DIMM 1 RttWr: 1
36084247.153: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
36085247.153: DIMM 0 RttWr: 1
36086247.153: DIMM 1 RttNom: 3
36087247.153: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
36088247.153: DIMM 0 RttNom: 3
36089247.153: DIMM 1 RttWr: 1
36090247.153: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
36091247.153: DIMM 0 RttWr: 1
36092247.153: AgesaHwWlPhase1: training nibble 0
36093247.153: DIMM 1 RttNom: 3
36094247.153: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
36095247.153: DIMM 1 RttWr: 1
36096247.153: DIMM 1 RttWr: 1
36097247.153: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
36098247.153: DIMM 1 RttWr: 1
36099247.153: DIMM 1 RttNom: 3
36100247.153: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
36101247.153: DIMM 1 RttNom: 3
36102247.153: DIMM 1 RttWr: 1
36103247.153: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
36104247.153: DIMM 1 RttWr: 1
36105247.153: DIMM 0 RttNom: 3
36106247.153: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
36107247.153: DIMM 1 RttNom: 3
36108247.153: DIMM 0 RttWr: 1
36109247.153: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
36110247.153: DIMM 1 RttWr: 1
36111247.153: DIMM 0 RttNom: 3
36112247.153: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
36113247.153: DIMM 1 RttNom: 3
36114247.153: DIMM 0 RttWr: 1
36115247.153: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
36116247.153: DIMM 1 RttWr: 1
36117247.153: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
36118247.153: <09>Lane 00 scaled delay: 0051
36119247.153: <09>Lane 00 new seed: 0051
36120247.153: <09>Lane 01 scaled delay: 004e
36121247.153: <09>Lane 01 new seed: 004e
36122247.153: <09>Lane 02 scaled delay: 004d
36123247.153: <09>Lane 02 new seed: 004d
36124247.153: <09>Lane 03 scaled delay: 004b
36125247.153: <09>Lane 03 new seed: 004b
36126247.153: <09>Lane 04 scaled delay: 0043
36127247.153: <09>Lane 04 new seed: 0043
36128247.153: <09>Lane 05 scaled delay: 0046
36129247.153: <09>Lane 05 new seed: 0046
36130247.153: <09>Lane 06 scaled delay: 0047
36131247.153: <09>Lane 06 new seed: 0047
36132247.153: <09>Lane 07 scaled delay: 004a
36133247.153: <09>Lane 07 new seed: 004a
36134247.153: <09>Lane 08 scaled delay: 0045
36135247.153: <09>Lane 08 new seed: 0045
36136247.153: <09>Lane 00 nibble 0 raw readback: 0050
36137247.153: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
36138247.153: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
36139247.153: <09>Lane 01 nibble 0 raw readback: 004c
36140247.153: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004c
36141247.153: <09>Lane 01 nibble 0 adjusted value (post nibble): 004c
36142247.153: <09>Lane 02 nibble 0 raw readback: 0048
36143247.154: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
36144247.153: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
36145247.154: <09>Lane 03 nibble 0 raw readback: 0044
36146247.154: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
36147247.154: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
36148247.154: <09>Lane 04 nibble 0 raw readback: 0036
36149247.154: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0036
36150247.154: <09>Lane 04 nibble 0 adjusted value (post nibble): 0036
36151247.154: <09>Lane 05 nibble 0 raw readback: 003b
36152247.154: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
36153247.154: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
36154247.154: <09>Lane 06 nibble 0 raw readback: 003e
36155247.154: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
36156247.154: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
36157247.154: <09>Lane 07 nibble 0 raw readback: 0042
36158247.154: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
36159247.154: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
36160247.154: <09>Lane 08 nibble 0 raw readback: 0039
36161247.154: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
36162247.154: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
36163247.154: AgesaHwWlPhase1: training nibble 1
36164247.154: DIMM 1 RttNom: 3
36165247.154: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
36166247.154: DIMM 1 RttWr: 1
36167247.154: DIMM 1 RttWr: 1
36168247.154: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
36169247.154: DIMM 1 RttWr: 1
36170247.154: DIMM 1 RttNom: 3
36171247.154: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
36172247.154: DIMM 1 RttNom: 3
36173247.154: DIMM 1 RttWr: 1
36174247.154: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
36175247.154: DIMM 1 RttWr: 1
36176247.154: DIMM 0 RttNom: 3
36177247.154: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
36178247.154: DIMM 1 RttNom: 3
36179247.154: DIMM 0 RttWr: 1
36180247.154: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
36181247.154: DIMM 1 RttWr: 1
36182247.154: DIMM 0 RttNom: 3
36183247.154: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
36184247.154: DIMM 1 RttNom: 3
36185247.154: DIMM 0 RttWr: 1
36186247.154: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
36187247.154: DIMM 1 RttWr: 1
36188247.154: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
36189247.154: <09>Lane 00 new seed: 0051
36190247.154: <09>Lane 01 new seed: 004e
36191247.154: <09>Lane 02 new seed: 004d
36192247.154: <09>Lane 03 new seed: 004b
36193247.154: <09>Lane 04 new seed: 0043
36194247.154: <09>Lane 05 new seed: 0046
36195247.154: <09>Lane 06 new seed: 0047
36196247.154: <09>Lane 07 new seed: 004a
36197247.154: <09>Lane 08 new seed: 0045
36198247.154: <09>Lane 00 nibble 1 raw readback: 004f
36199247.154: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
36200247.154: <09>Lane 00 nibble 1 adjusted value (post nibble): 0050
36201247.154: <09>Lane 01 nibble 1 raw readback: 004a
36202247.154: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
36203247.154: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
36204247.154: <09>Lane 02 nibble 1 raw readback: 0047
36205247.154: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
36206247.154: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
36207247.154: <09>Lane 03 nibble 1 raw readback: 0045
36208247.154: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
36209247.154: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
36210247.154: <09>Lane 04 nibble 1 raw readback: 0036
36211247.154: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
36212247.154: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
36213247.154: <09>Lane 05 nibble 1 raw readback: 003a
36214247.154: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
36215247.154: <09>Lane 05 nibble 1 adjusted value (post nibble): 0040
36216247.154: <09>Lane 06 nibble 1 raw readback: 003e
36217247.154: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
36218247.155: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
36219247.155: <09>Lane 07 nibble 1 raw readback: 0042
36220247.155: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
36221247.155: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
36222247.155: <09>Lane 08 nibble 1 raw readback: 0039
36223247.155: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
36224247.155: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
36225247.155: <09>original critical gross delay: 0
36226247.155: <09>new critical gross delay: 0
36227247.155: DIMM 1 RttNom: 3
36228247.155: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
36229247.155: DIMM 1 RttNom: 3
36230247.155: DIMM 1 RttWr: 1
36231247.155: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
36232247.155: DIMM 1 RttWr: 1
36233247.155: DIMM 1 RttNom: 3
36234247.155: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
36235247.155: DIMM 1 RttNom: 3
36236247.155: DIMM 1 RttWr: 1
36237247.155: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
36238247.155: DIMM 1 RttWr: 1
36239247.155: DIMM 0 RttNom: 3
36240247.155: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
36241247.155: DIMM 1 RttNom: 3
36242247.155: DIMM 0 RttWr: 1
36243247.155: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
36244247.155: DIMM 1 RttWr: 1
36245247.155: DIMM 0 RttNom: 3
36246247.155: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
36247247.155: DIMM 1 RttNom: 3
36248247.155: DIMM 0 RttWr: 1
36249247.155: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
36250247.155: DIMM 1 RttWr: 1
36251247.155: SetTargetFreq: Start
36252247.155: SetTargetFreq: Node 2: New frequency code: 000e
36253247.155: ChangeMemClk: Start
36254247.155: set_2t_configuration: Start
36255247.155: set_2t_configuration: Done
36256247.155: mct_BeforePlatformSpec: Start
36257247.155: mct_BeforePlatformSpec: Done
36258247.155: mct_PlatformSpec: Start
36259247.156: Programmed DCT 0 timing/termination pattern 00383a38 30222222
36260247.156: mct_PlatformSpec: Done
36261247.156: set_2t_configuration: Start
36262247.156: set_2t_configuration: Done
36263247.156: mct_BeforePlatformSpec: Start
36264247.156: mct_BeforePlatformSpec: Done
36265247.156: mct_PlatformSpec: Start
36266247.156: Programmed DCT 1 timing/termination pattern 00383a38 30222222
36267247.156: mct_PlatformSpec: Done
36268247.156: ChangeMemClk: Done
36269247.156: phyAssistedMemFnceTraining: Start
36270247.156: phyAssistedMemFnceTraining: training node 2 DCT 0
36271247.156: phyAssistedMemFnceTraining: done training node 2 DCT 0
36272247.156: phyAssistedMemFnceTraining: training node 2 DCT 1
36273247.156: phyAssistedMemFnceTraining: done training node 2 DCT 1
36274247.156: phyAssistedMemFnceTraining: Done
36275247.156: InitPhyCompensation: DCT 0: Start
36276247.156: Waiting for predriver calibration to be applied...done!
36277247.156: InitPhyCompensation: DCT 0: Done
36278247.156: phyAssistedMemFnceTraining: Start
36279247.156: phyAssistedMemFnceTraining: training node 2 DCT 0
36280247.156: phyAssistedMemFnceTraining: done training node 2 DCT 0
36281247.156: phyAssistedMemFnceTraining: training node 2 DCT 1
36282247.156: phyAssistedMemFnceTraining: done training node 2 DCT 1
36283247.157: phyAssistedMemFnceTraining: Done
36284247.156: InitPhyCompensation: DCT 1: Start
36285247.157: Waiting for predriver calibration to be applied...done!
36286247.157: InitPhyCompensation: DCT 1: Done
36287247.157: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
36288247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
36289247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
36290247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
36291247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
36292247.157: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
36293247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
36294247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
36295247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
36296247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
36297247.157: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
36298247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
36299247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
36300247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
36301247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
36302247.157: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
36303247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
36304247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
36305247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
36306247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
36307247.157: SetTargetFreq: Done
36308247.157: SPD2ndTiming: Start
36309247.158: SPD2ndTiming: Done
36310247.158: mct_BeforeDramInit_Prod_D: Start
36311247.158: mct_ProgramODT_D: Start
36312247.158: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
36313247.158: mct_ProgramODT_D: Done
36314247.158: mct_BeforeDramInit_Prod_D: Done
36315247.158: mct_DramInit_Sw_D: Start
36316247.158: DIMM 0 RttWr: 2
36317247.158: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36318247.158: mct_SendMrsCmd: Start
36319247.158: mct_SendMrsCmd: Done
36320247.158: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
36321247.158: mct_SendMrsCmd: Start
36322247.158: mct_SendMrsCmd: Done
36323247.158: DIMM 0 RttNom: 5
36324247.158: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36325247.158: mct_SendMrsCmd: Start
36326247.158: mct_SendMrsCmd: Done
36327247.158: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
36328247.158: mct_SendMrsCmd: Start
36329247.158: mct_SendMrsCmd: Done
36330247.158: DIMM 0 RttWr: 2
36331247.158: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36332247.158: mct_SendMrsCmd: Start
36333247.158: mct_SendMrsCmd: Done
36334247.158: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
36335247.158: mct_SendMrsCmd: Start
36336247.158: mct_SendMrsCmd: Done
36337247.158: DIMM 0 RttNom: 5
36338247.158: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36339247.158: mct_SendMrsCmd: Start
36340247.158: mct_SendMrsCmd: Done
36341247.158: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
36342247.158: mct_SendMrsCmd: Start
36343247.158: mct_SendMrsCmd: Done
36344247.158: DIMM 1 RttWr: 2
36345247.158: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36346247.158: mct_SendMrsCmd: Start
36347247.158: mct_SendMrsCmd: Done
36348247.158: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
36349247.158: mct_SendMrsCmd: Start
36350247.158: mct_SendMrsCmd: Done
36351247.158: DIMM 1 RttNom: 5
36352247.158: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36353247.158: mct_SendMrsCmd: Start
36354247.158: mct_SendMrsCmd: Done
36355247.158: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
36356247.158: mct_SendMrsCmd: Start
36357247.158: mct_SendMrsCmd: Done
36358247.158: DIMM 1 RttWr: 2
36359247.158: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36360247.158: mct_SendMrsCmd: Start
36361247.158: mct_SendMrsCmd: Done
36362247.158: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
36363247.158: mct_SendMrsCmd: Start
36364247.158: mct_SendMrsCmd: Done
36365247.158: DIMM 1 RttNom: 5
36366247.158: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36367247.158: mct_SendMrsCmd: Start
36368247.158: mct_SendMrsCmd: Done
36369247.158: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
36370247.158: mct_SendMrsCmd: Start
36371247.158: mct_SendMrsCmd: Done
36372247.158: mct_DramInit_Sw_D: Done
36373247.159: AgesaHwWlPhase1: training nibble 0
36374247.159: DIMM 0 RttNom: 5
36375247.159: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36376247.159: DIMM 0 RttWr: 2
36377247.159: DIMM 0 RttWr: 2
36378247.159: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36379247.159: DIMM 0 RttWr: 2
36380247.159: DIMM 0 RttNom: 5
36381247.159: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36382247.159: DIMM 0 RttNom: 5
36383247.159: DIMM 0 RttWr: 2
36384247.159: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36385247.159: DIMM 0 RttWr: 2
36386247.159: DIMM 1 RttNom: 5
36387247.159: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36388247.159: DIMM 0 RttNom: 5
36389247.159: DIMM 1 RttWr: 2
36390247.159: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36391247.159: DIMM 0 RttWr: 2
36392247.159: DIMM 1 RttNom: 5
36393247.159: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36394247.159: DIMM 0 RttNom: 5
36395247.159: DIMM 1 RttWr: 2
36396247.159: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36397247.159: DIMM 0 RttWr: 2
36398247.159: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
36399247.159: <09>Lane 00 scaled delay: 0069
36400247.159: <09>Lane 00 new seed: 0069
36401247.159: <09>Lane 01 scaled delay: 0064
36402247.159: <09>Lane 01 new seed: 0064
36403247.159: <09>Lane 02 scaled delay: 0061
36404247.159: <09>Lane 02 new seed: 0061
36405247.159: <09>Lane 03 scaled delay: 005e
36406247.159: <09>Lane 03 new seed: 005e
36407247.159: <09>Lane 04 scaled delay: 0050
36408247.159: <09>Lane 04 new seed: 0050
36409247.159: <09>Lane 05 scaled delay: 0054
36410247.159: <09>Lane 05 new seed: 0054
36411247.159: <09>Lane 06 scaled delay: 0059
36412247.160: <09>Lane 06 new seed: 0059
36413247.159: <09>Lane 07 scaled delay: 005a
36414247.160: <09>Lane 07 new seed: 005a
36415247.160: <09>Lane 08 scaled delay: 0052
36416247.160: <09>Lane 08 new seed: 0052
36417247.160: <09>Lane 00 nibble 0 raw readback: 002f
36418247.160: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
36419247.160: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
36420247.160: <09>Lane 01 nibble 0 raw readback: 0024
36421247.160: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
36422247.160: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
36423247.160: <09>Lane 02 nibble 0 raw readback: 0021
36424247.160: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
36425247.160: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
36426247.160: <09>Lane 03 nibble 0 raw readback: 005c
36427247.160: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
36428247.160: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
36429247.160: <09>Lane 04 nibble 0 raw readback: 004b
36430247.160: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004b
36431247.160: <09>Lane 04 nibble 0 adjusted value (post nibble): 004b
36432247.160: <09>Lane 05 nibble 0 raw readback: 0054
36433247.160: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
36434247.160: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
36435247.160: <09>Lane 06 nibble 0 raw readback: 0058
36436247.160: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
36437247.160: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
36438247.160: <09>Lane 07 nibble 0 raw readback: 005c
36439247.160: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005c
36440247.160: <09>Lane 07 nibble 0 adjusted value (post nibble): 005c
36441247.160: <09>Lane 08 nibble 0 raw readback: 004e
36442247.160: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
36443247.160: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
36444247.160: AgesaHwWlPhase1: training nibble 1
36445247.160: DIMM 0 RttNom: 5
36446247.160: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36447247.160: DIMM 0 RttWr: 2
36448247.160: DIMM 0 RttWr: 2
36449247.160: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36450247.160: DIMM 0 RttWr: 2
36451247.160: DIMM 0 RttNom: 5
36452247.160: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36453247.160: DIMM 0 RttNom: 5
36454247.160: DIMM 0 RttWr: 2
36455247.160: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36456247.160: DIMM 0 RttWr: 2
36457247.160: DIMM 1 RttNom: 5
36458247.160: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36459247.160: DIMM 0 RttNom: 5
36460247.160: DIMM 1 RttWr: 2
36461247.160: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36462247.160: DIMM 0 RttWr: 2
36463247.160: DIMM 1 RttNom: 5
36464247.160: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36465247.160: DIMM 0 RttNom: 5
36466247.160: DIMM 1 RttWr: 2
36467247.160: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36468247.160: DIMM 0 RttWr: 2
36469247.160: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
36470247.160: <09>Lane 00 new seed: 0069
36471247.160: <09>Lane 01 new seed: 0064
36472247.160: <09>Lane 02 new seed: 0061
36473247.160: <09>Lane 03 new seed: 005e
36474247.160: <09>Lane 04 new seed: 0050
36475247.161: <09>Lane 05 new seed: 0054
36476247.161: <09>Lane 06 new seed: 0059
36477247.161: <09>Lane 07 new seed: 005a
36478247.161: <09>Lane 08 new seed: 0052
36479247.161: <09>Lane 00 nibble 1 raw readback: 002f
36480247.161: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
36481247.161: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
36482247.161: <09>Lane 01 nibble 1 raw readback: 0026
36483247.161: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
36484247.161: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
36485247.161: <09>Lane 02 nibble 1 raw readback: 0022
36486247.161: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
36487247.161: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
36488247.161: <09>Lane 03 nibble 1 raw readback: 005d
36489247.161: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
36490247.161: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
36491247.161: <09>Lane 04 nibble 1 raw readback: 004a
36492247.161: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
36493247.161: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
36494247.161: <09>Lane 05 nibble 1 raw readback: 0052
36495247.161: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
36496247.161: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
36497247.161: <09>Lane 06 nibble 1 raw readback: 0059
36498247.161: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0059
36499247.161: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
36500247.161: <09>Lane 07 nibble 1 raw readback: 005c
36501247.161: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
36502247.161: <09>Lane 07 nibble 1 adjusted value (post nibble): 005b
36503247.161: <09>Lane 08 nibble 1 raw readback: 004d
36504247.161: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004d
36505247.161: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
36506247.161: <09>original critical gross delay: 0
36507247.161: <09>new critical gross delay: 0
36508247.161: DIMM 0 RttNom: 5
36509247.161: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36510247.161: DIMM 0 RttNom: 5
36511247.161: DIMM 0 RttWr: 2
36512247.161: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36513247.161: DIMM 0 RttWr: 2
36514247.161: DIMM 0 RttNom: 5
36515247.161: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36516247.161: DIMM 0 RttNom: 5
36517247.161: DIMM 0 RttWr: 2
36518247.161: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36519247.161: DIMM 0 RttWr: 2
36520247.161: DIMM 1 RttNom: 5
36521247.161: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36522247.161: DIMM 0 RttNom: 5
36523247.161: DIMM 1 RttWr: 2
36524247.161: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36525247.161: DIMM 0 RttWr: 2
36526247.161: DIMM 1 RttNom: 5
36527247.161: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36528247.161: DIMM 0 RttNom: 5
36529247.161: DIMM 1 RttWr: 2
36530247.161: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36531247.161: DIMM 0 RttWr: 2
36532247.161: AgesaHwWlPhase1: training nibble 0
36533247.161: DIMM 1 RttNom: 5
36534247.161: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36535247.162: DIMM 1 RttWr: 2
36536247.161: DIMM 1 RttWr: 2
36537247.161: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36538247.162: DIMM 1 RttWr: 2
36539247.162: DIMM 1 RttNom: 5
36540247.162: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36541247.162: DIMM 1 RttNom: 5
36542247.162: DIMM 1 RttWr: 2
36543247.162: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36544247.162: DIMM 1 RttWr: 2
36545247.162: DIMM 0 RttNom: 5
36546247.162: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36547247.162: DIMM 1 RttNom: 5
36548247.162: DIMM 0 RttWr: 2
36549247.162: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36550247.162: DIMM 1 RttWr: 2
36551247.162: DIMM 0 RttNom: 5
36552247.162: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36553247.162: DIMM 1 RttNom: 5
36554247.162: DIMM 0 RttWr: 2
36555247.162: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36556247.162: DIMM 1 RttWr: 2
36557247.162: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
36558247.162: <09>Lane 00 scaled delay: 005d
36559247.162: <09>Lane 00 new seed: 005d
36560247.162: <09>Lane 01 scaled delay: 0057
36561247.162: <09>Lane 01 new seed: 0057
36562247.162: <09>Lane 02 scaled delay: 0057
36563247.162: <09>Lane 02 new seed: 0057
36564247.162: <09>Lane 03 scaled delay: 0053
36565247.162: <09>Lane 03 new seed: 0053
36566247.162: <09>Lane 04 scaled delay: 0045
36567247.162: <09>Lane 04 new seed: 0045
36568247.162: <09>Lane 05 scaled delay: 0049
36569247.162: <09>Lane 05 new seed: 0049
36570247.162: <09>Lane 06 scaled delay: 004d
36571247.162: <09>Lane 06 new seed: 004d
36572247.162: <09>Lane 07 scaled delay: 0050
36573247.162: <09>Lane 07 new seed: 0050
36574247.162: <09>Lane 08 scaled delay: 0048
36575247.162: <09>Lane 08 new seed: 0048
36576247.162: <09>Lane 00 nibble 0 raw readback: 0060
36577247.162: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
36578247.162: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
36579247.162: <09>Lane 01 nibble 0 raw readback: 0055
36580247.162: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0055
36581247.162: <09>Lane 01 nibble 0 adjusted value (post nibble): 0055
36582247.162: <09>Lane 02 nibble 0 raw readback: 0053
36583247.162: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
36584247.162: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
36585247.162: <09>Lane 03 nibble 0 raw readback: 004c
36586247.162: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004c
36587247.162: <09>Lane 03 nibble 0 adjusted value (post nibble): 004c
36588247.162: <09>Lane 04 nibble 0 raw readback: 003a
36589247.162: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
36590247.162: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
36591247.162: <09>Lane 05 nibble 0 raw readback: 0044
36592247.162: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0044
36593247.162: <09>Lane 05 nibble 0 adjusted value (post nibble): 0044
36594247.162: <09>Lane 06 nibble 0 raw readback: 0049
36595247.162: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
36596247.162: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
36597247.162: <09>Lane 07 nibble 0 raw readback: 004d
36598247.162: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
36599247.162: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
36600247.162: <09>Lane 08 nibble 0 raw readback: 003f
36601247.162: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
36602247.162: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
36603247.162: AgesaHwWlPhase1: training nibble 1
36604247.162: DIMM 1 RttNom: 5
36605247.162: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36606247.162: DIMM 1 RttWr: 2
36607247.162: DIMM 1 RttWr: 2
36608247.163: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36609247.163: DIMM 1 RttWr: 2
36610247.163: DIMM 1 RttNom: 5
36611247.163: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36612247.163: DIMM 1 RttNom: 5
36613247.163: DIMM 1 RttWr: 2
36614247.163: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36615247.163: DIMM 1 RttWr: 2
36616247.163: DIMM 0 RttNom: 5
36617247.163: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36618247.163: DIMM 1 RttNom: 5
36619247.163: DIMM 0 RttWr: 2
36620247.163: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36621247.163: DIMM 1 RttWr: 2
36622247.163: DIMM 0 RttNom: 5
36623247.163: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36624247.163: DIMM 1 RttNom: 5
36625247.163: DIMM 0 RttWr: 2
36626247.163: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36627247.163: DIMM 1 RttWr: 2
36628247.163: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
36629247.163: <09>Lane 00 new seed: 005d
36630247.163: <09>Lane 01 new seed: 0057
36631247.163: <09>Lane 02 new seed: 0057
36632247.163: <09>Lane 03 new seed: 0053
36633247.163: <09>Lane 04 new seed: 0045
36634247.163: <09>Lane 05 new seed: 0049
36635247.163: <09>Lane 06 new seed: 004d
36636247.163: <09>Lane 07 new seed: 0050
36637247.163: <09>Lane 08 new seed: 0048
36638247.163: <09>Lane 00 nibble 1 raw readback: 005f
36639247.163: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
36640247.163: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
36641247.163: <09>Lane 01 nibble 1 raw readback: 0056
36642247.163: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
36643247.163: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
36644247.163: <09>Lane 02 nibble 1 raw readback: 0055
36645247.163: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
36646247.163: <09>Lane 02 nibble 1 adjusted value (post nibble): 0056
36647247.163: <09>Lane 03 nibble 1 raw readback: 004f
36648247.163: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
36649247.163: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
36650247.163: <09>Lane 04 nibble 1 raw readback: 003d
36651247.163: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003d
36652247.163: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
36653247.163: <09>Lane 05 nibble 1 raw readback: 0044
36654247.163: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0044
36655247.163: <09>Lane 05 nibble 1 adjusted value (post nibble): 0046
36656247.163: <09>Lane 06 nibble 1 raw readback: 0049
36657247.163: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
36658247.163: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
36659247.163: <09>Lane 07 nibble 1 raw readback: 004e
36660247.163: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
36661247.163: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
36662247.163: <09>Lane 08 nibble 1 raw readback: 003f
36663247.163: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
36664247.163: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
36665247.163: <09>original critical gross delay: 0
36666247.163: <09>new critical gross delay: 0
36667247.163: DIMM 1 RttNom: 5
36668247.163: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
36669247.163: DIMM 1 RttNom: 5
36670247.163: DIMM 1 RttWr: 2
36671247.163: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
36672247.163: DIMM 1 RttWr: 2
36673247.163: DIMM 1 RttNom: 5
36674247.164: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
36675247.164: DIMM 1 RttNom: 5
36676247.164: DIMM 1 RttWr: 2
36677247.164: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
36678247.164: DIMM 1 RttWr: 2
36679247.164: DIMM 0 RttNom: 5
36680247.164: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
36681247.164: DIMM 1 RttNom: 5
36682247.164: DIMM 0 RttWr: 2
36683247.164: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
36684247.164: DIMM 1 RttWr: 2
36685247.164: DIMM 0 RttNom: 5
36686247.164: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
36687247.164: DIMM 1 RttNom: 5
36688247.164: DIMM 0 RttWr: 2
36689247.164: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
36690247.164: DIMM 1 RttWr: 2
36691247.164: SPD2ndTiming: Start
36692247.164: SPD2ndTiming: Done
36693247.164: mct_BeforeDramInit_Prod_D: Start
36694247.164: mct_ProgramODT_D: Start
36695247.164: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
36696247.164: mct_ProgramODT_D: Done
36697247.164: mct_BeforeDramInit_Prod_D: Done
36698247.164: mct_DramInit_Sw_D: Start
36699247.164: DIMM 0 RttWr: 2
36700247.164: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
36701247.164: mct_SendMrsCmd: Start
36702247.164: mct_SendMrsCmd: Done
36703247.164: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
36704247.164: mct_SendMrsCmd: Start
36705247.164: mct_SendMrsCmd: Done
36706247.165: DIMM 0 RttNom: 5
36707247.165: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
36708247.164: mct_SendMrsCmd: Start
36709247.165: mct_SendMrsCmd: Done
36710247.165: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
36711247.165: mct_SendMrsCmd: Start
36712247.165: mct_SendMrsCmd: Done
36713247.165: DIMM 0 RttWr: 2
36714247.165: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
36715247.165: mct_SendMrsCmd: Start
36716247.165: mct_SendMrsCmd: Done
36717247.165: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
36718247.165: mct_SendMrsCmd: Start
36719247.165: mct_SendMrsCmd: Done
36720247.165: DIMM 0 RttNom: 5
36721247.165: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
36722247.165: mct_SendMrsCmd: Start
36723247.165: mct_SendMrsCmd: Done
36724247.165: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
36725247.165: mct_SendMrsCmd: Start
36726247.165: mct_SendMrsCmd: Done
36727247.165: DIMM 1 RttWr: 2
36728247.165: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
36729247.165: mct_SendMrsCmd: Start
36730247.165: mct_SendMrsCmd: Done
36731247.165: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
36732247.165: mct_SendMrsCmd: Start
36733247.165: mct_SendMrsCmd: Done
36734247.165: DIMM 1 RttNom: 5
36735247.165: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
36736247.165: mct_SendMrsCmd: Start
36737247.165: mct_SendMrsCmd: Done
36738247.165: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
36739247.165: mct_SendMrsCmd: Start
36740247.165: mct_SendMrsCmd: Done
36741247.165: DIMM 1 RttWr: 2
36742247.165: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
36743247.165: mct_SendMrsCmd: Start
36744247.165: mct_SendMrsCmd: Done
36745247.165: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
36746247.165: mct_SendMrsCmd: Start
36747247.165: mct_SendMrsCmd: Done
36748247.165: DIMM 1 RttNom: 5
36749247.165: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
36750247.165: mct_SendMrsCmd: Start
36751247.165: mct_SendMrsCmd: Done
36752247.165: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
36753247.165: mct_SendMrsCmd: Start
36754247.165: mct_SendMrsCmd: Done
36755247.165: mct_DramInit_Sw_D: Done
36756247.165: AgesaHwWlPhase1: training nibble 0
36757247.165: DIMM 0 RttNom: 5
36758247.165: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
36759247.165: DIMM 0 RttWr: 2
36760247.165: DIMM 0 RttWr: 2
36761247.165: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
36762247.165: DIMM 0 RttWr: 2
36763247.165: DIMM 0 RttNom: 5
36764247.165: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
36765247.165: DIMM 0 RttNom: 5
36766247.165: DIMM 0 RttWr: 2
36767247.165: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
36768247.165: DIMM 0 RttWr: 2
36769247.165: DIMM 1 RttNom: 5
36770247.165: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
36771247.165: DIMM 0 RttNom: 5
36772247.165: DIMM 1 RttWr: 2
36773247.165: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
36774247.165: DIMM 0 RttWr: 2
36775247.165: DIMM 1 RttNom: 5
36776247.166: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
36777247.166: DIMM 0 RttNom: 5
36778247.166: DIMM 1 RttWr: 2
36779247.166: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
36780247.166: DIMM 0 RttWr: 2
36781247.166: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
36782247.166: <09>Lane 00 scaled delay: 0068
36783247.166: <09>Lane 00 new seed: 0068
36784247.166: <09>Lane 01 scaled delay: 0063
36785247.166: <09>Lane 01 new seed: 0063
36786247.166: <09>Lane 02 scaled delay: 005f
36787247.166: <09>Lane 02 new seed: 005f
36788247.166: <09>Lane 03 scaled delay: 005d
36789247.166: <09>Lane 03 new seed: 005d
36790247.166: <09>Lane 04 scaled delay: 004e
36791247.166: <09>Lane 04 new seed: 004e
36792247.166: <09>Lane 05 scaled delay: 0054
36793247.166: <09>Lane 05 new seed: 0054
36794247.166: <09>Lane 06 scaled delay: 0057
36795247.166: <09>Lane 06 new seed: 0057
36796247.166: <09>Lane 07 scaled delay: 0059
36797247.166: <09>Lane 07 new seed: 0059
36798247.166: <09>Lane 08 scaled delay: 0052
36799247.166: <09>Lane 08 new seed: 0052
36800247.166: <09>Lane 00 nibble 0 raw readback: 002c
36801247.166: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006c
36802247.166: <09>Lane 00 nibble 0 adjusted value (post nibble): 006c
36803247.166: <09>Lane 01 nibble 0 raw readback: 0027
36804247.166: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
36805247.166: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
36806247.166: <09>Lane 02 nibble 0 raw readback: 0060
36807247.166: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
36808247.166: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
36809247.166: <09>Lane 03 nibble 0 raw readback: 005c
36810247.166: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
36811247.166: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
36812247.166: <09>Lane 04 nibble 0 raw readback: 0049
36813247.166: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
36814247.166: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
36815247.166: <09>Lane 05 nibble 0 raw readback: 0051
36816247.166: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
36817247.166: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
36818247.166: <09>Lane 06 nibble 0 raw readback: 0057
36819247.166: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
36820247.166: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
36821247.166: <09>Lane 07 nibble 0 raw readback: 005b
36822247.166: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
36823247.166: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
36824247.166: <09>Lane 08 nibble 0 raw readback: 004d
36825247.166: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004d
36826247.166: <09>Lane 08 nibble 0 adjusted value (post nibble): 004d
36827247.166: AgesaHwWlPhase1: training nibble 1
36828247.166: DIMM 0 RttNom: 5
36829247.166: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
36830247.166: DIMM 0 RttWr: 2
36831247.166: DIMM 0 RttWr: 2
36832247.166: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
36833247.166: DIMM 0 RttWr: 2
36834247.166: DIMM 0 RttNom: 5
36835247.167: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
36836247.167: DIMM 0 RttNom: 5
36837247.167: DIMM 0 RttWr: 2
36838247.167: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
36839247.167: DIMM 0 RttWr: 2
36840247.167: DIMM 1 RttNom: 5
36841247.167: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
36842247.167: DIMM 0 RttNom: 5
36843247.167: DIMM 1 RttWr: 2
36844247.167: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
36845247.167: DIMM 0 RttWr: 2
36846247.167: DIMM 1 RttNom: 5
36847247.167: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
36848247.167: DIMM 0 RttNom: 5
36849247.167: DIMM 1 RttWr: 2
36850247.167: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
36851247.167: DIMM 0 RttWr: 2
36852247.167: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
36853247.167: <09>Lane 00 new seed: 0068
36854247.167: <09>Lane 01 new seed: 0063
36855247.167: <09>Lane 02 new seed: 005f
36856247.167: <09>Lane 03 new seed: 005d
36857247.167: <09>Lane 04 new seed: 004e
36858247.167: <09>Lane 05 new seed: 0054
36859247.167: <09>Lane 06 new seed: 0057
36860247.167: <09>Lane 07 new seed: 0059
36861247.167: <09>Lane 08 new seed: 0052
36862247.167: <09>Lane 00 nibble 1 raw readback: 002d
36863247.167: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006d
36864247.167: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
36865247.167: <09>Lane 01 nibble 1 raw readback: 0027
36866247.167: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
36867247.167: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
36868247.167: <09>Lane 02 nibble 1 raw readback: 0062
36869247.167: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
36870247.167: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
36871247.167: <09>Lane 03 nibble 1 raw readback: 005d
36872247.167: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
36873247.167: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
36874247.167: <09>Lane 04 nibble 1 raw readback: 004a
36875247.167: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
36876247.167: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
36877247.167: <09>Lane 05 nibble 1 raw readback: 0052
36878247.167: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
36879247.167: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
36880247.167: <09>Lane 06 nibble 1 raw readback: 0057
36881247.167: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0057
36882247.167: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
36883247.167: <09>Lane 07 nibble 1 raw readback: 005b
36884247.167: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
36885247.167: <09>Lane 07 nibble 1 adjusted value (post nibble): 005a
36886247.167: <09>Lane 08 nibble 1 raw readback: 004e
36887247.167: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
36888247.167: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
36889247.167: <09>original critical gross delay: 0
36890247.167: <09>new critical gross delay: 0
36891247.167: DIMM 0 RttNom: 5
36892247.167: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
36893247.167: DIMM 0 RttNom: 5
36894247.167: DIMM 0 RttWr: 2
36895247.168: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
36896247.168: DIMM 0 RttWr: 2
36897247.168: DIMM 0 RttNom: 5
36898247.168: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
36899247.168: DIMM 0 RttNom: 5
36900247.168: DIMM 0 RttWr: 2
36901247.168: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
36902247.168: DIMM 0 RttWr: 2
36903247.168: DIMM 1 RttNom: 5
36904247.168: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
36905247.168: DIMM 0 RttNom: 5
36906247.168: DIMM 1 RttWr: 2
36907247.168: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
36908247.168: DIMM 0 RttWr: 2
36909247.168: DIMM 1 RttNom: 5
36910247.168: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
36911247.168: DIMM 0 RttNom: 5
36912247.168: DIMM 1 RttWr: 2
36913247.168: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
36914247.168: DIMM 0 RttWr: 2
36915247.168: AgesaHwWlPhase1: training nibble 0
36916247.168: DIMM 1 RttNom: 5
36917247.168: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
36918247.168: DIMM 1 RttWr: 2
36919247.168: DIMM 1 RttWr: 2
36920247.168: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
36921247.168: DIMM 1 RttWr: 2
36922247.168: DIMM 1 RttNom: 5
36923247.168: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
36924247.168: DIMM 1 RttNom: 5
36925247.168: DIMM 1 RttWr: 2
36926247.168: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
36927247.168: DIMM 1 RttWr: 2
36928247.168: DIMM 0 RttNom: 5
36929247.168: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
36930247.168: DIMM 1 RttNom: 5
36931247.168: DIMM 0 RttWr: 2
36932247.168: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
36933247.168: DIMM 1 RttWr: 2
36934247.168: DIMM 0 RttNom: 5
36935247.168: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
36936247.168: DIMM 1 RttNom: 5
36937247.168: DIMM 0 RttWr: 2
36938247.168: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
36939247.168: DIMM 1 RttWr: 2
36940247.168: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
36941247.168: <09>Lane 00 scaled delay: 005c
36942247.168: <09>Lane 00 new seed: 005c
36943247.168: <09>Lane 01 scaled delay: 0057
36944247.168: <09>Lane 01 new seed: 0057
36945247.168: <09>Lane 02 scaled delay: 0054
36946247.168: <09>Lane 02 new seed: 0054
36947247.168: <09>Lane 03 scaled delay: 0052
36948247.168: <09>Lane 03 new seed: 0052
36949247.168: <09>Lane 04 scaled delay: 0043
36950247.168: <09>Lane 04 new seed: 0043
36951247.168: <09>Lane 05 scaled delay: 0048
36952247.168: <09>Lane 05 new seed: 0048
36953247.168: <09>Lane 06 scaled delay: 004a
36954247.168: <09>Lane 06 new seed: 004a
36955247.168: <09>Lane 07 scaled delay: 004f
36956247.168: <09>Lane 07 new seed: 004f
36957247.168: <09>Lane 08 scaled delay: 0046
36958247.168: <09>Lane 08 new seed: 0046
36959247.169: <09>Lane 00 nibble 0 raw readback: 005c
36960247.169: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
36961247.169: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
36962247.169: <09>Lane 01 nibble 0 raw readback: 0056
36963247.169: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
36964247.169: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
36965247.169: <09>Lane 02 nibble 0 raw readback: 0050
36966247.169: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
36967247.169: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
36968247.169: <09>Lane 03 nibble 0 raw readback: 004b
36969247.169: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004b
36970247.169: <09>Lane 03 nibble 0 adjusted value (post nibble): 004b
36971247.169: <09>Lane 04 nibble 0 raw readback: 003a
36972247.169: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
36973247.169: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
36974247.169: <09>Lane 05 nibble 0 raw readback: 0042
36975247.169: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0042
36976247.169: <09>Lane 05 nibble 0 adjusted value (post nibble): 0042
36977247.169: <09>Lane 06 nibble 0 raw readback: 0045
36978247.169: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0045
36979247.169: <09>Lane 06 nibble 0 adjusted value (post nibble): 0045
36980247.169: <09>Lane 07 nibble 0 raw readback: 004b
36981247.169: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004b
36982247.169: <09>Lane 07 nibble 0 adjusted value (post nibble): 004b
36983247.169: <09>Lane 08 nibble 0 raw readback: 003f
36984247.169: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
36985247.169: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
36986247.169: AgesaHwWlPhase1: training nibble 1
36987247.169: DIMM 1 RttNom: 5
36988247.169: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
36989247.169: DIMM 1 RttWr: 2
36990247.169: DIMM 1 RttWr: 2
36991247.169: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
36992247.169: DIMM 1 RttWr: 2
36993247.169: DIMM 1 RttNom: 5
36994247.169: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
36995247.169: DIMM 1 RttNom: 5
36996247.169: DIMM 1 RttWr: 2
36997247.169: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
36998247.169: DIMM 1 RttWr: 2
36999247.169: DIMM 0 RttNom: 5
37000247.169: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
37001247.169: DIMM 1 RttNom: 5
37002247.169: DIMM 0 RttWr: 2
37003247.169: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
37004247.169: DIMM 1 RttWr: 2
37005247.169: DIMM 0 RttNom: 5
37006247.169: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
37007247.169: DIMM 1 RttNom: 5
37008247.169: DIMM 0 RttWr: 2
37009247.169: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
37010247.169: DIMM 1 RttWr: 2
37011247.169: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
37012247.169: <09>Lane 00 new seed: 005c
37013247.169: <09>Lane 01 new seed: 0057
37014247.169: <09>Lane 02 new seed: 0054
37015247.169: <09>Lane 03 new seed: 0052
37016247.169: <09>Lane 04 new seed: 0043
37017247.169: <09>Lane 05 new seed: 0048
37018247.169: <09>Lane 06 new seed: 004a
37019247.169: <09>Lane 07 new seed: 004f
37020247.169: <09>Lane 08 new seed: 0046
37021247.169: <09>Lane 00 nibble 1 raw readback: 005b
37022247.169: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005b
37023247.169: <09>Lane 00 nibble 1 adjusted value (post nibble): 005b
37024247.169: <09>Lane 01 nibble 1 raw readback: 0055
37025247.169: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
37026247.169: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
37027247.169: <09>Lane 02 nibble 1 raw readback: 0051
37028247.169: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
37029247.169: <09>Lane 02 nibble 1 adjusted value (post nibble): 0052
37030247.169: <09>Lane 03 nibble 1 raw readback: 004d
37031247.169: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
37032247.169: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
37033247.169: <09>Lane 04 nibble 1 raw readback: 003b
37034247.169: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
37035247.170: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
37036247.170: <09>Lane 05 nibble 1 raw readback: 0042
37037247.170: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0042
37038247.170: <09>Lane 05 nibble 1 adjusted value (post nibble): 0045
37039247.170: <09>Lane 06 nibble 1 raw readback: 0046
37040247.170: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
37041247.170: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
37042247.170: <09>Lane 07 nibble 1 raw readback: 004b
37043247.170: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
37044247.170: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
37045247.170: <09>Lane 08 nibble 1 raw readback: 0040
37046247.170: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
37047247.170: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
37048247.170: <09>original critical gross delay: 0
37049247.170: <09>new critical gross delay: 0
37050247.170: DIMM 1 RttNom: 5
37051247.170: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
37052247.170: DIMM 1 RttNom: 5
37053247.170: DIMM 1 RttWr: 2
37054247.170: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
37055247.170: DIMM 1 RttWr: 2
37056247.170: DIMM 1 RttNom: 5
37057247.170: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
37058247.170: DIMM 1 RttNom: 5
37059247.170: DIMM 1 RttWr: 2
37060247.170: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
37061247.170: DIMM 1 RttWr: 2
37062247.170: DIMM 0 RttNom: 5
37063247.170: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
37064247.170: DIMM 1 RttNom: 5
37065247.170: DIMM 0 RttWr: 2
37066247.170: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
37067247.170: DIMM 1 RttWr: 2
37068247.170: DIMM 0 RttNom: 5
37069247.170: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
37070247.170: DIMM 1 RttNom: 5
37071247.170: DIMM 0 RttWr: 2
37072247.170: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
37073247.170: DIMM 1 RttWr: 2
37074247.170: SetTargetFreq: Start
37075247.170: SetTargetFreq: Node 2: New frequency code: 0012
37076247.170: ChangeMemClk: Start
37077247.170: set_2t_configuration: Start
37078247.170: set_2t_configuration: Done
37079247.171: mct_BeforePlatformSpec: Start
37080247.171: mct_BeforePlatformSpec: Done
37081247.171: mct_PlatformSpec: Start
37082247.171: Programmed DCT 0 timing/termination pattern 00353935 30222222
37083247.171: mct_PlatformSpec: Done
37084247.171: set_2t_configuration: Start
37085247.171: set_2t_configuration: Done
37086247.171: mct_BeforePlatformSpec: Start
37087247.171: mct_BeforePlatformSpec: Done
37088247.171: mct_PlatformSpec: Start
37089247.171: Programmed DCT 1 timing/termination pattern 00353935 30222222
37090247.171: mct_PlatformSpec: Done
37091247.171: ChangeMemClk: Done
37092247.171: phyAssistedMemFnceTraining: Start
37093247.171: phyAssistedMemFnceTraining: training node 2 DCT 0
37094247.171: phyAssistedMemFnceTraining: done training node 2 DCT 0
37095247.171: phyAssistedMemFnceTraining: training node 2 DCT 1
37096247.171: phyAssistedMemFnceTraining: done training node 2 DCT 1
37097247.171: phyAssistedMemFnceTraining: Done
37098247.171: InitPhyCompensation: DCT 0: Start
37099247.171: Waiting for predriver calibration to be applied...done!
37100247.171: InitPhyCompensation: DCT 0: Done
37101247.171: phyAssistedMemFnceTraining: Start
37102247.171: phyAssistedMemFnceTraining: training node 2 DCT 0
37103247.171: phyAssistedMemFnceTraining: done training node 2 DCT 0
37104247.171: phyAssistedMemFnceTraining: training node 2 DCT 1
37105247.171: phyAssistedMemFnceTraining: done training node 2 DCT 1
37106247.172: phyAssistedMemFnceTraining: Done
37107247.172: InitPhyCompensation: DCT 1: Start
37108247.172: Waiting for predriver calibration to be applied...done!
37109247.172: InitPhyCompensation: DCT 1: Done
37110247.172: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
37111247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37112247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
37113247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37114247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
37115247.172: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
37116247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37117247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
37118247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37119247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
37120247.172: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
37121247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37122247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
37123247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37124247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
37125247.172: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
37126247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37127247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
37128247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37129247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
37130247.172: SetTargetFreq: Done
37131247.172: SPD2ndTiming: Start
37132247.173: SPD2ndTiming: Done
37133247.173: mct_BeforeDramInit_Prod_D: Start
37134247.173: mct_ProgramODT_D: Start
37135247.173: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
37136247.173: mct_ProgramODT_D: Done
37137247.173: mct_BeforeDramInit_Prod_D: Done
37138247.173: mct_DramInit_Sw_D: Start
37139247.173: DIMM 0 RttWr: 1
37140247.173: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37141247.173: mct_SendMrsCmd: Start
37142247.173: mct_SendMrsCmd: Done
37143247.173: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
37144247.173: mct_SendMrsCmd: Start
37145247.173: mct_SendMrsCmd: Done
37146247.173: DIMM 0 RttNom: 4
37147247.173: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37148247.173: mct_SendMrsCmd: Start
37149247.173: mct_SendMrsCmd: Done
37150247.173: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
37151247.173: mct_SendMrsCmd: Start
37152247.173: mct_SendMrsCmd: Done
37153247.173: DIMM 0 RttWr: 1
37154247.173: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37155247.173: mct_SendMrsCmd: Start
37156247.173: mct_SendMrsCmd: Done
37157247.173: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
37158247.173: mct_SendMrsCmd: Start
37159247.173: mct_SendMrsCmd: Done
37160247.173: DIMM 0 RttNom: 4
37161247.173: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37162247.173: mct_SendMrsCmd: Start
37163247.173: mct_SendMrsCmd: Done
37164247.173: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
37165247.173: mct_SendMrsCmd: Start
37166247.173: mct_SendMrsCmd: Done
37167247.173: DIMM 1 RttWr: 1
37168247.173: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37169247.173: mct_SendMrsCmd: Start
37170247.173: mct_SendMrsCmd: Done
37171247.173: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
37172247.173: mct_SendMrsCmd: Start
37173247.173: mct_SendMrsCmd: Done
37174247.173: DIMM 1 RttNom: 4
37175247.173: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37176247.173: mct_SendMrsCmd: Start
37177247.173: mct_SendMrsCmd: Done
37178247.173: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
37179247.173: mct_SendMrsCmd: Start
37180247.173: mct_SendMrsCmd: Done
37181247.173: DIMM 1 RttWr: 1
37182247.173: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37183247.173: mct_SendMrsCmd: Start
37184247.173: mct_SendMrsCmd: Done
37185247.173: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
37186247.173: mct_SendMrsCmd: Start
37187247.173: mct_SendMrsCmd: Done
37188247.173: DIMM 1 RttNom: 4
37189247.173: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37190247.173: mct_SendMrsCmd: Start
37191247.173: mct_SendMrsCmd: Done
37192247.173: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
37193247.173: mct_SendMrsCmd: Start
37194247.174: mct_SendMrsCmd: Done
37195247.174: mct_DramInit_Sw_D: Done
37196247.174: AgesaHwWlPhase1: training nibble 0
37197247.174: DIMM 0 RttNom: 4
37198247.174: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37199247.174: DIMM 0 RttWr: 1
37200247.174: DIMM 0 RttWr: 1
37201247.174: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37202247.174: DIMM 0 RttWr: 1
37203247.174: DIMM 0 RttNom: 4
37204247.174: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37205247.174: DIMM 0 RttNom: 4
37206247.174: DIMM 0 RttWr: 1
37207247.174: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37208247.174: DIMM 0 RttWr: 1
37209247.174: DIMM 1 RttNom: 4
37210247.174: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37211247.174: DIMM 0 RttNom: 4
37212247.174: DIMM 1 RttWr: 1
37213247.174: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37214247.174: DIMM 0 RttWr: 1
37215247.174: DIMM 1 RttNom: 4
37216247.174: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37217247.174: DIMM 0 RttNom: 4
37218247.174: DIMM 1 RttWr: 1
37219247.174: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37220247.174: DIMM 0 RttWr: 1
37221247.174: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
37222247.174: <09>Lane 00 scaled delay: 007b
37223247.174: <09>Lane 00 new seed: 007b
37224247.174: <09>Lane 01 scaled delay: 0072
37225247.174: <09>Lane 01 new seed: 0072
37226247.174: <09>Lane 02 scaled delay: 006d
37227247.174: <09>Lane 02 new seed: 006d
37228247.174: <09>Lane 03 scaled delay: 0069
37229247.174: <09>Lane 03 new seed: 0069
37230247.174: <09>Lane 04 scaled delay: 0055
37231247.174: <09>Lane 04 new seed: 0055
37232247.174: <09>Lane 05 scaled delay: 005d
37233247.174: <09>Lane 05 new seed: 005d
37234247.174: <09>Lane 06 scaled delay: 0064
37235247.175: <09>Lane 06 new seed: 0064
37236247.175: <09>Lane 07 scaled delay: 0066
37237247.175: <09>Lane 07 new seed: 0066
37238247.175: <09>Lane 08 scaled delay: 0058
37239247.175: <09>Lane 08 new seed: 0058
37240247.175: <09>Lane 00 nibble 0 raw readback: 0041
37241247.175: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0081
37242247.175: <09>Lane 00 nibble 0 adjusted value (post nibble): 0081
37243247.175: <09>Lane 01 nibble 0 raw readback: 0034
37244247.175: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0074
37245247.175: <09>Lane 01 nibble 0 adjusted value (post nibble): 0074
37246247.175: <09>Lane 02 nibble 0 raw readback: 0032
37247247.175: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0072
37248247.175: <09>Lane 02 nibble 0 adjusted value (post nibble): 0072
37249247.175: <09>Lane 03 nibble 0 raw readback: 002c
37250247.175: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006c
37251247.175: <09>Lane 03 nibble 0 adjusted value (post nibble): 006c
37252247.175: <09>Lane 04 nibble 0 raw readback: 0058
37253247.175: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0058
37254247.175: <09>Lane 04 nibble 0 adjusted value (post nibble): 0058
37255247.175: <09>Lane 05 nibble 0 raw readback: 0060
37256247.175: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0060
37257247.175: <09>Lane 05 nibble 0 adjusted value (post nibble): 0060
37258247.175: <09>Lane 06 nibble 0 raw readback: 0025
37259247.175: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
37260247.175: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
37261247.175: <09>Lane 07 nibble 0 raw readback: 002b
37262247.175: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
37263247.175: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
37264247.175: <09>Lane 08 nibble 0 raw readback: 005c
37265247.175: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005c
37266247.175: <09>Lane 08 nibble 0 adjusted value (post nibble): 005c
37267247.175: AgesaHwWlPhase1: training nibble 1
37268247.175: DIMM 0 RttNom: 4
37269247.175: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37270247.175: DIMM 0 RttWr: 1
37271247.175: DIMM 0 RttWr: 1
37272247.175: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37273247.175: DIMM 0 RttWr: 1
37274247.175: DIMM 0 RttNom: 4
37275247.175: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37276247.175: DIMM 0 RttNom: 4
37277247.175: DIMM 0 RttWr: 1
37278247.175: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37279247.175: DIMM 0 RttWr: 1
37280247.175: DIMM 1 RttNom: 4
37281247.175: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37282247.175: DIMM 0 RttNom: 4
37283247.175: DIMM 1 RttWr: 1
37284247.175: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37285247.175: DIMM 0 RttWr: 1
37286247.175: DIMM 1 RttNom: 4
37287247.175: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37288247.175: DIMM 0 RttNom: 4
37289247.175: DIMM 1 RttWr: 1
37290247.175: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37291247.175: DIMM 0 RttWr: 1
37292247.175: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
37293247.175: <09>Lane 00 new seed: 007b
37294247.175: <09>Lane 01 new seed: 0072
37295247.175: <09>Lane 02 new seed: 006d
37296247.175: <09>Lane 03 new seed: 0069
37297247.176: <09>Lane 04 new seed: 0055
37298247.176: <09>Lane 05 new seed: 005d
37299247.176: <09>Lane 06 new seed: 0064
37300247.176: <09>Lane 07 new seed: 0066
37301247.176: <09>Lane 08 new seed: 0058
37302247.176: <09>Lane 00 nibble 1 raw readback: 0040
37303247.176: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0080
37304247.176: <09>Lane 00 nibble 1 adjusted value (post nibble): 007d
37305247.176: <09>Lane 01 nibble 1 raw readback: 0037
37306247.176: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0077
37307247.176: <09>Lane 01 nibble 1 adjusted value (post nibble): 0074
37308247.176: <09>Lane 02 nibble 1 raw readback: 0032
37309247.176: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
37310247.176: <09>Lane 02 nibble 1 adjusted value (post nibble): 006f
37311247.176: <09>Lane 03 nibble 1 raw readback: 002c
37312247.176: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
37313247.176: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
37314247.176: <09>Lane 04 nibble 1 raw readback: 0057
37315247.176: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0057
37316247.176: <09>Lane 04 nibble 1 adjusted value (post nibble): 0056
37317247.176: <09>Lane 05 nibble 1 raw readback: 0060
37318247.176: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0060
37319247.176: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
37320247.176: <09>Lane 06 nibble 1 raw readback: 0026
37321247.176: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
37322247.176: <09>Lane 06 nibble 1 adjusted value (post nibble): 0065
37323247.176: <09>Lane 07 nibble 1 raw readback: 002a
37324247.176: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006a
37325247.176: <09>Lane 07 nibble 1 adjusted value (post nibble): 0068
37326247.176: <09>Lane 08 nibble 1 raw readback: 005a
37327247.176: <09>Lane 08 nibble 1 adjusted value (pre nibble): 005a
37328247.176: <09>Lane 08 nibble 1 adjusted value (post nibble): 0059
37329247.176: <09>original critical gross delay: 0
37330247.176: <09>new critical gross delay: 0
37331247.176: DIMM 0 RttNom: 4
37332247.176: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37333247.176: DIMM 0 RttNom: 4
37334247.176: DIMM 0 RttWr: 1
37335247.176: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37336247.176: DIMM 0 RttWr: 1
37337247.176: DIMM 0 RttNom: 4
37338247.176: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37339247.176: DIMM 0 RttNom: 4
37340247.176: DIMM 0 RttWr: 1
37341247.176: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37342247.176: DIMM 0 RttWr: 1
37343247.176: DIMM 1 RttNom: 4
37344247.176: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37345247.176: DIMM 0 RttNom: 4
37346247.176: DIMM 1 RttWr: 1
37347247.176: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37348247.176: DIMM 0 RttWr: 1
37349247.176: DIMM 1 RttNom: 4
37350247.176: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37351247.176: DIMM 0 RttNom: 4
37352247.176: DIMM 1 RttWr: 1
37353247.176: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37354247.176: DIMM 0 RttWr: 1
37355247.176: AgesaHwWlPhase1: training nibble 0
37356247.176: DIMM 1 RttNom: 4
37357247.177: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37358247.176: DIMM 1 RttWr: 1
37359247.177: DIMM 1 RttWr: 1
37360247.177: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37361247.177: DIMM 1 RttWr: 1
37362247.177: DIMM 1 RttNom: 4
37363247.177: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37364247.177: DIMM 1 RttNom: 4
37365247.177: DIMM 1 RttWr: 1
37366247.177: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37367247.177: DIMM 1 RttWr: 1
37368247.177: DIMM 0 RttNom: 4
37369247.177: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37370247.177: DIMM 1 RttNom: 4
37371247.177: DIMM 0 RttWr: 1
37372247.177: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37373247.177: DIMM 1 RttWr: 1
37374247.177: DIMM 0 RttNom: 4
37375247.177: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37376247.177: DIMM 1 RttNom: 4
37377247.177: DIMM 0 RttWr: 1
37378247.177: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37379247.177: DIMM 1 RttWr: 1
37380247.177: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
37381247.177: <09>Lane 00 scaled delay: 006a
37382247.177: <09>Lane 00 new seed: 006a
37383247.177: <09>Lane 01 scaled delay: 0060
37384247.177: <09>Lane 01 new seed: 0060
37385247.177: <09>Lane 02 scaled delay: 0060
37386247.177: <09>Lane 02 new seed: 0060
37387247.177: <09>Lane 03 scaled delay: 005a
37388247.177: <09>Lane 03 new seed: 005a
37389247.177: <09>Lane 04 scaled delay: 0047
37390247.177: <09>Lane 04 new seed: 0047
37391247.177: <09>Lane 05 scaled delay: 004d
37392247.177: <09>Lane 05 new seed: 004d
37393247.177: <09>Lane 06 scaled delay: 0053
37394247.177: <09>Lane 06 new seed: 0053
37395247.177: <09>Lane 07 scaled delay: 0058
37396247.177: <09>Lane 07 new seed: 0058
37397247.177: <09>Lane 08 scaled delay: 0049
37398247.177: <09>Lane 08 new seed: 0049
37399247.177: <09>Lane 00 nibble 0 raw readback: 0031
37400247.177: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0071
37401247.177: <09>Lane 00 nibble 0 adjusted value (post nibble): 0071
37402247.177: <09>Lane 01 nibble 0 raw readback: 0024
37403247.177: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
37404247.177: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
37405247.177: <09>Lane 02 nibble 0 raw readback: 0022
37406247.177: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0062
37407247.177: <09>Lane 02 nibble 0 adjusted value (post nibble): 0062
37408247.177: <09>Lane 03 nibble 0 raw readback: 0059
37409247.177: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
37410247.177: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
37411247.177: <09>Lane 04 nibble 0 raw readback: 0045
37412247.177: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0045
37413247.177: <09>Lane 04 nibble 0 adjusted value (post nibble): 0045
37414247.177: <09>Lane 05 nibble 0 raw readback: 004f
37415247.177: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
37416247.177: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
37417247.177: <09>Lane 06 nibble 0 raw readback: 0055
37418247.177: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
37419247.177: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
37420247.177: <09>Lane 07 nibble 0 raw readback: 005a
37421247.177: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
37422247.177: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
37423247.177: <09>Lane 08 nibble 0 raw readback: 004b
37424247.177: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
37425247.177: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
37426247.177: AgesaHwWlPhase1: training nibble 1
37427247.178: DIMM 1 RttNom: 4
37428247.177: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37429247.177: DIMM 1 RttWr: 1
37430247.177: DIMM 1 RttWr: 1
37431247.178: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37432247.178: DIMM 1 RttWr: 1
37433247.178: DIMM 1 RttNom: 4
37434247.178: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37435247.178: DIMM 1 RttNom: 4
37436247.178: DIMM 1 RttWr: 1
37437247.178: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37438247.178: DIMM 1 RttWr: 1
37439247.178: DIMM 0 RttNom: 4
37440247.178: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37441247.178: DIMM 1 RttNom: 4
37442247.178: DIMM 0 RttWr: 1
37443247.178: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37444247.178: DIMM 1 RttWr: 1
37445247.178: DIMM 0 RttNom: 4
37446247.178: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37447247.178: DIMM 1 RttNom: 4
37448247.178: DIMM 0 RttWr: 1
37449247.178: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37450247.178: DIMM 1 RttWr: 1
37451247.178: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
37452247.178: <09>Lane 00 new seed: 006a
37453247.178: <09>Lane 01 new seed: 0060
37454247.178: <09>Lane 02 new seed: 0060
37455247.178: <09>Lane 03 new seed: 005a
37456247.178: <09>Lane 04 new seed: 0047
37457247.178: <09>Lane 05 new seed: 004d
37458247.178: <09>Lane 06 new seed: 0053
37459247.178: <09>Lane 07 new seed: 0058
37460247.178: <09>Lane 08 new seed: 0049
37461247.178: <09>Lane 00 nibble 1 raw readback: 0030
37462247.178: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
37463247.178: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
37464247.178: <09>Lane 01 nibble 1 raw readback: 0025
37465247.178: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
37466247.178: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
37467247.178: <09>Lane 02 nibble 1 raw readback: 0025
37468247.178: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0065
37469247.178: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
37470247.178: <09>Lane 03 nibble 1 raw readback: 005d
37471247.178: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
37472247.178: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
37473247.178: <09>Lane 04 nibble 1 raw readback: 0048
37474247.178: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
37475247.178: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
37476247.178: <09>Lane 05 nibble 1 raw readback: 0050
37477247.178: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
37478247.178: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
37479247.178: <09>Lane 06 nibble 1 raw readback: 0056
37480247.178: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
37481247.178: <09>Lane 06 nibble 1 adjusted value (post nibble): 0054
37482247.178: <09>Lane 07 nibble 1 raw readback: 005b
37483247.178: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
37484247.178: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
37485247.178: <09>Lane 08 nibble 1 raw readback: 004c
37486247.178: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004c
37487247.178: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
37488247.178: <09>original critical gross delay: 0
37489247.178: <09>new critical gross delay: 0
37490247.179: DIMM 1 RttNom: 4
37491247.179: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
37492247.178: DIMM 1 RttNom: 4
37493247.178: DIMM 1 RttWr: 1
37494247.178: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
37495247.178: DIMM 1 RttWr: 1
37496247.179: DIMM 1 RttNom: 4
37497247.179: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
37498247.179: DIMM 1 RttNom: 4
37499247.179: DIMM 1 RttWr: 1
37500247.179: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
37501247.179: DIMM 1 RttWr: 1
37502247.179: DIMM 0 RttNom: 4
37503247.179: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
37504247.179: DIMM 1 RttNom: 4
37505247.179: DIMM 0 RttWr: 1
37506247.179: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
37507247.179: DIMM 1 RttWr: 1
37508247.179: DIMM 0 RttNom: 4
37509247.179: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
37510247.179: DIMM 1 RttNom: 4
37511247.179: DIMM 0 RttWr: 1
37512247.179: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
37513247.179: DIMM 1 RttWr: 1
37514247.179: SPD2ndTiming: Start
37515247.179: SPD2ndTiming: Done
37516247.179: mct_BeforeDramInit_Prod_D: Start
37517247.179: mct_ProgramODT_D: Start
37518247.179: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
37519247.179: mct_ProgramODT_D: Done
37520247.179: mct_BeforeDramInit_Prod_D: Done
37521247.179: mct_DramInit_Sw_D: Start
37522247.179: DIMM 0 RttWr: 1
37523247.179: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37524247.179: mct_SendMrsCmd: Start
37525247.179: mct_SendMrsCmd: Done
37526247.179: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
37527247.179: mct_SendMrsCmd: Start
37528247.179: mct_SendMrsCmd: Done
37529247.179: DIMM 0 RttNom: 4
37530247.179: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37531247.180: mct_SendMrsCmd: Start
37532247.180: mct_SendMrsCmd: Done
37533247.180: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
37534247.180: mct_SendMrsCmd: Start
37535247.180: mct_SendMrsCmd: Done
37536247.180: DIMM 0 RttWr: 1
37537247.180: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37538247.180: mct_SendMrsCmd: Start
37539247.180: mct_SendMrsCmd: Done
37540247.180: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
37541247.180: mct_SendMrsCmd: Start
37542247.180: mct_SendMrsCmd: Done
37543247.180: DIMM 0 RttNom: 4
37544247.180: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37545247.180: mct_SendMrsCmd: Start
37546247.180: mct_SendMrsCmd: Done
37547247.180: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
37548247.180: mct_SendMrsCmd: Start
37549247.180: mct_SendMrsCmd: Done
37550247.180: DIMM 1 RttWr: 1
37551247.180: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37552247.180: mct_SendMrsCmd: Start
37553247.180: mct_SendMrsCmd: Done
37554247.180: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
37555247.180: mct_SendMrsCmd: Start
37556247.180: mct_SendMrsCmd: Done
37557247.180: DIMM 1 RttNom: 4
37558247.180: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37559247.180: mct_SendMrsCmd: Start
37560247.180: mct_SendMrsCmd: Done
37561247.180: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
37562247.180: mct_SendMrsCmd: Start
37563247.180: mct_SendMrsCmd: Done
37564247.180: DIMM 1 RttWr: 1
37565247.180: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37566247.180: mct_SendMrsCmd: Start
37567247.180: mct_SendMrsCmd: Done
37568247.180: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
37569247.180: mct_SendMrsCmd: Start
37570247.180: mct_SendMrsCmd: Done
37571247.180: DIMM 1 RttNom: 4
37572247.180: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37573247.180: mct_SendMrsCmd: Start
37574247.180: mct_SendMrsCmd: Done
37575247.180: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
37576247.180: mct_SendMrsCmd: Start
37577247.180: mct_SendMrsCmd: Done
37578247.180: mct_DramInit_Sw_D: Done
37579247.180: AgesaHwWlPhase1: training nibble 0
37580247.180: DIMM 0 RttNom: 4
37581247.180: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37582247.180: DIMM 0 RttWr: 1
37583247.180: DIMM 0 RttWr: 1
37584247.180: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37585247.180: DIMM 0 RttWr: 1
37586247.180: DIMM 0 RttNom: 4
37587247.180: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37588247.180: DIMM 0 RttNom: 4
37589247.180: DIMM 0 RttWr: 1
37590247.180: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37591247.180: DIMM 0 RttWr: 1
37592247.180: DIMM 1 RttNom: 4
37593247.180: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37594247.180: DIMM 0 RttNom: 4
37595247.180: DIMM 1 RttWr: 1
37596247.181: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37597247.180: DIMM 0 RttWr: 1
37598247.181: DIMM 1 RttNom: 4
37599247.181: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37600247.180: DIMM 0 RttNom: 4
37601247.181: DIMM 1 RttWr: 1
37602247.181: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37603247.181: DIMM 0 RttWr: 1
37604247.181: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
37605247.181: <09>Lane 00 scaled delay: 0078
37606247.181: <09>Lane 00 new seed: 0078
37607247.181: <09>Lane 01 scaled delay: 0072
37608247.181: <09>Lane 01 new seed: 0072
37609247.181: <09>Lane 02 scaled delay: 006c
37610247.181: <09>Lane 02 new seed: 006c
37611247.181: <09>Lane 03 scaled delay: 0069
37612247.181: <09>Lane 03 new seed: 0069
37613247.181: <09>Lane 04 scaled delay: 0054
37614247.181: <09>Lane 04 new seed: 0054
37615247.181: <09>Lane 05 scaled delay: 005d
37616247.181: <09>Lane 05 new seed: 005d
37617247.181: <09>Lane 06 scaled delay: 0061
37618247.181: <09>Lane 06 new seed: 0061
37619247.181: <09>Lane 07 scaled delay: 0065
37620247.181: <09>Lane 07 new seed: 0065
37621247.181: <09>Lane 08 scaled delay: 0059
37622247.181: <09>Lane 08 new seed: 0059
37623247.181: <09>Lane 00 nibble 0 raw readback: 003e
37624247.181: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007e
37625247.181: <09>Lane 00 nibble 0 adjusted value (post nibble): 007e
37626247.181: <09>Lane 01 nibble 0 raw readback: 0038
37627247.181: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0078
37628247.181: <09>Lane 01 nibble 0 adjusted value (post nibble): 0078
37629247.181: <09>Lane 02 nibble 0 raw readback: 002f
37630247.181: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006f
37631247.181: <09>Lane 02 nibble 0 adjusted value (post nibble): 006f
37632247.181: <09>Lane 03 nibble 0 raw readback: 002a
37633247.181: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
37634247.181: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
37635247.181: <09>Lane 04 nibble 0 raw readback: 0056
37636247.181: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
37637247.181: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
37638247.181: <09>Lane 05 nibble 0 raw readback: 005e
37639247.181: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
37640247.181: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
37641247.181: <09>Lane 06 nibble 0 raw readback: 0024
37642247.181: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
37643247.181: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
37644247.181: <09>Lane 07 nibble 0 raw readback: 0027
37645247.181: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0067
37646247.181: <09>Lane 07 nibble 0 adjusted value (post nibble): 0067
37647247.181: <09>Lane 08 nibble 0 raw readback: 005a
37648247.181: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005a
37649247.181: <09>Lane 08 nibble 0 adjusted value (post nibble): 005a
37650247.181: AgesaHwWlPhase1: training nibble 1
37651247.181: DIMM 0 RttNom: 4
37652247.181: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37653247.181: DIMM 0 RttWr: 1
37654247.181: DIMM 0 RttWr: 1
37655247.181: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37656247.181: DIMM 0 RttWr: 1
37657247.181: DIMM 0 RttNom: 4
37658247.182: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37659247.181: DIMM 0 RttNom: 4
37660247.181: DIMM 0 RttWr: 1
37661247.181: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37662247.182: DIMM 0 RttWr: 1
37663247.182: DIMM 1 RttNom: 4
37664247.182: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37665247.182: DIMM 0 RttNom: 4
37666247.182: DIMM 1 RttWr: 1
37667247.182: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37668247.182: DIMM 0 RttWr: 1
37669247.182: DIMM 1 RttNom: 4
37670247.182: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37671247.182: DIMM 0 RttNom: 4
37672247.182: DIMM 1 RttWr: 1
37673247.182: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37674247.182: DIMM 0 RttWr: 1
37675247.182: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
37676247.182: <09>Lane 00 new seed: 0078
37677247.182: <09>Lane 01 new seed: 0072
37678247.182: <09>Lane 02 new seed: 006c
37679247.182: <09>Lane 03 new seed: 0069
37680247.182: <09>Lane 04 new seed: 0054
37681247.182: <09>Lane 05 new seed: 005d
37682247.182: <09>Lane 06 new seed: 0061
37683247.182: <09>Lane 07 new seed: 0065
37684247.182: <09>Lane 08 new seed: 0059
37685247.182: <09>Lane 00 nibble 1 raw readback: 003e
37686247.182: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007e
37687247.182: <09>Lane 00 nibble 1 adjusted value (post nibble): 007b
37688247.182: <09>Lane 01 nibble 1 raw readback: 0037
37689247.182: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0077
37690247.182: <09>Lane 01 nibble 1 adjusted value (post nibble): 0074
37691247.182: <09>Lane 02 nibble 1 raw readback: 0030
37692247.182: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0070
37693247.182: <09>Lane 02 nibble 1 adjusted value (post nibble): 006e
37694247.182: <09>Lane 03 nibble 1 raw readback: 002b
37695247.182: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006b
37696247.182: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
37697247.182: <09>Lane 04 nibble 1 raw readback: 0055
37698247.182: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0055
37699247.182: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
37700247.182: <09>Lane 05 nibble 1 raw readback: 005e
37701247.182: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005e
37702247.182: <09>Lane 05 nibble 1 adjusted value (post nibble): 005d
37703247.182: <09>Lane 06 nibble 1 raw readback: 0024
37704247.182: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0064
37705247.182: <09>Lane 06 nibble 1 adjusted value (post nibble): 0062
37706247.182: <09>Lane 07 nibble 1 raw readback: 0026
37707247.182: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
37708247.182: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
37709247.182: <09>Lane 08 nibble 1 raw readback: 0059
37710247.182: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
37711247.182: <09>Lane 08 nibble 1 adjusted value (post nibble): 0059
37712247.182: <09>original critical gross delay: 0
37713247.182: <09>new critical gross delay: 0
37714247.182: DIMM 0 RttNom: 4
37715247.182: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37716247.182: DIMM 0 RttNom: 4
37717247.182: DIMM 0 RttWr: 1
37718247.182: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37719247.182: DIMM 0 RttWr: 1
37720247.182: DIMM 0 RttNom: 4
37721247.183: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37722247.183: DIMM 0 RttNom: 4
37723247.183: DIMM 0 RttWr: 1
37724247.183: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37725247.183: DIMM 0 RttWr: 1
37726247.183: DIMM 1 RttNom: 4
37727247.183: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37728247.183: DIMM 0 RttNom: 4
37729247.183: DIMM 1 RttWr: 1
37730247.183: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37731247.183: DIMM 0 RttWr: 1
37732247.183: DIMM 1 RttNom: 4
37733247.183: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37734247.183: DIMM 0 RttNom: 4
37735247.183: DIMM 1 RttWr: 1
37736247.183: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37737247.183: DIMM 0 RttWr: 1
37738247.183: AgesaHwWlPhase1: training nibble 0
37739247.183: DIMM 1 RttNom: 4
37740247.183: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37741247.183: DIMM 1 RttWr: 1
37742247.183: DIMM 1 RttWr: 1
37743247.183: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37744247.183: DIMM 1 RttWr: 1
37745247.183: DIMM 1 RttNom: 4
37746247.183: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37747247.183: DIMM 1 RttNom: 4
37748247.183: DIMM 1 RttWr: 1
37749247.183: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37750247.183: DIMM 1 RttWr: 1
37751247.183: DIMM 0 RttNom: 4
37752247.183: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37753247.183: DIMM 1 RttNom: 4
37754247.183: DIMM 0 RttWr: 1
37755247.183: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37756247.183: DIMM 1 RttWr: 1
37757247.183: DIMM 0 RttNom: 4
37758247.183: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37759247.183: DIMM 1 RttNom: 4
37760247.183: DIMM 0 RttWr: 1
37761247.183: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37762247.183: DIMM 1 RttWr: 1
37763247.183: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
37764247.183: <09>Lane 00 scaled delay: 0066
37765247.183: <09>Lane 00 new seed: 0066
37766247.183: <09>Lane 01 scaled delay: 0060
37767247.183: <09>Lane 01 new seed: 0060
37768247.183: <09>Lane 02 scaled delay: 005b
37769247.183: <09>Lane 02 new seed: 005b
37770247.183: <09>Lane 03 scaled delay: 0058
37771247.183: <09>Lane 03 new seed: 0058
37772247.183: <09>Lane 04 scaled delay: 0045
37773247.183: <09>Lane 04 new seed: 0045
37774247.183: <09>Lane 05 scaled delay: 004c
37775247.183: <09>Lane 05 new seed: 004c
37776247.183: <09>Lane 06 scaled delay: 004f
37777247.183: <09>Lane 06 new seed: 004f
37778247.183: <09>Lane 07 scaled delay: 0055
37779247.183: <09>Lane 07 new seed: 0055
37780247.183: <09>Lane 08 scaled delay: 0049
37781247.183: <09>Lane 08 new seed: 0049
37782247.183: <09>Lane 00 nibble 0 raw readback: 002d
37783247.183: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006d
37784247.184: <09>Lane 00 nibble 0 adjusted value (post nibble): 006d
37785247.183: <09>Lane 01 nibble 0 raw readback: 0025
37786247.183: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
37787247.183: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
37788247.184: <09>Lane 02 nibble 0 raw readback: 005e
37789247.184: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005e
37790247.184: <09>Lane 02 nibble 0 adjusted value (post nibble): 005e
37791247.184: <09>Lane 03 nibble 0 raw readback: 0058
37792247.184: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0058
37793247.184: <09>Lane 03 nibble 0 adjusted value (post nibble): 0058
37794247.184: <09>Lane 04 nibble 0 raw readback: 0043
37795247.184: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
37796247.184: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
37797247.184: <09>Lane 05 nibble 0 raw readback: 004d
37798247.184: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004d
37799247.184: <09>Lane 05 nibble 0 adjusted value (post nibble): 004d
37800247.184: <09>Lane 06 nibble 0 raw readback: 0051
37801247.184: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
37802247.184: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
37803247.184: <09>Lane 07 nibble 0 raw readback: 0057
37804247.184: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0057
37805247.184: <09>Lane 07 nibble 0 adjusted value (post nibble): 0057
37806247.184: <09>Lane 08 nibble 0 raw readback: 0049
37807247.184: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
37808247.184: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
37809247.184: AgesaHwWlPhase1: training nibble 1
37810247.184: DIMM 1 RttNom: 4
37811247.184: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37812247.184: DIMM 1 RttWr: 1
37813247.184: DIMM 1 RttWr: 1
37814247.184: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37815247.184: DIMM 1 RttWr: 1
37816247.184: DIMM 1 RttNom: 4
37817247.184: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37818247.184: DIMM 1 RttNom: 4
37819247.184: DIMM 1 RttWr: 1
37820247.184: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37821247.184: DIMM 1 RttWr: 1
37822247.184: DIMM 0 RttNom: 4
37823247.184: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37824247.184: DIMM 1 RttNom: 4
37825247.184: DIMM 0 RttWr: 1
37826247.184: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37827247.184: DIMM 1 RttWr: 1
37828247.184: DIMM 0 RttNom: 4
37829247.184: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37830247.184: DIMM 1 RttNom: 4
37831247.184: DIMM 0 RttWr: 1
37832247.184: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37833247.184: DIMM 1 RttWr: 1
37834247.184: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
37835247.184: <09>Lane 00 new seed: 0066
37836247.184: <09>Lane 01 new seed: 0060
37837247.184: <09>Lane 02 new seed: 005b
37838247.184: <09>Lane 03 new seed: 0058
37839247.184: <09>Lane 04 new seed: 0045
37840247.184: <09>Lane 05 new seed: 004c
37841247.184: <09>Lane 06 new seed: 004f
37842247.184: <09>Lane 07 new seed: 0055
37843247.184: <09>Lane 08 new seed: 0049
37844247.184: <09>Lane 00 nibble 1 raw readback: 002c
37845247.184: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
37846247.184: <09>Lane 00 nibble 1 adjusted value (post nibble): 0069
37847247.184: <09>Lane 01 nibble 1 raw readback: 0026
37848247.184: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
37849247.184: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
37850247.184: <09>Lane 02 nibble 1 raw readback: 005e
37851247.184: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
37852247.184: <09>Lane 02 nibble 1 adjusted value (post nibble): 005c
37853247.184: <09>Lane 03 nibble 1 raw readback: 005a
37854247.184: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005a
37855247.184: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
37856247.184: <09>Lane 04 nibble 1 raw readback: 0046
37857247.184: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
37858247.184: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
37859247.184: <09>Lane 05 nibble 1 raw readback: 004d
37860247.184: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004d
37861247.184: <09>Lane 05 nibble 1 adjusted value (post nibble): 004c
37862247.185: <09>Lane 06 nibble 1 raw readback: 0053
37863247.185: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0053
37864247.185: <09>Lane 06 nibble 1 adjusted value (post nibble): 0051
37865247.185: <09>Lane 07 nibble 1 raw readback: 0058
37866247.185: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0058
37867247.185: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
37868247.185: <09>Lane 08 nibble 1 raw readback: 004a
37869247.185: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
37870247.185: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
37871247.185: <09>original critical gross delay: 0
37872247.185: <09>new critical gross delay: 0
37873247.185: DIMM 1 RttNom: 4
37874247.185: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
37875247.185: DIMM 1 RttNom: 4
37876247.185: DIMM 1 RttWr: 1
37877247.185: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
37878247.185: DIMM 1 RttWr: 1
37879247.185: DIMM 1 RttNom: 4
37880247.185: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
37881247.185: DIMM 1 RttNom: 4
37882247.185: DIMM 1 RttWr: 1
37883247.185: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
37884247.185: DIMM 1 RttWr: 1
37885247.185: DIMM 0 RttNom: 4
37886247.185: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
37887247.185: DIMM 1 RttNom: 4
37888247.185: DIMM 0 RttWr: 1
37889247.185: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
37890247.185: DIMM 1 RttWr: 1
37891247.185: DIMM 0 RttNom: 4
37892247.185: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
37893247.185: DIMM 1 RttNom: 4
37894247.185: DIMM 0 RttWr: 1
37895247.185: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
37896247.185: DIMM 1 RttWr: 1
37897247.186: activate_spd_rom() for node 03
37898247.186: enable_spd_node3()
37899247.186: SetTargetFreq: Start
37900247.186: SetTargetFreq: Node 3: New frequency code: 0006
37901247.186: ChangeMemClk: Start
37902247.186: set_2t_configuration: Start
37903247.186: set_2t_configuration: Done
37904247.186: mct_BeforePlatformSpec: Start
37905247.186: mct_BeforePlatformSpec: Done
37906247.186: mct_PlatformSpec: Start
37907247.186: Programmed DCT 0 timing/termination pattern 00000000 20222222
37908247.186: mct_PlatformSpec: Done
37909247.186: set_2t_configuration: Start
37910247.186: set_2t_configuration: Done
37911247.186: mct_BeforePlatformSpec: Start
37912247.186: mct_BeforePlatformSpec: Done
37913247.186: mct_PlatformSpec: Start
37914247.186: Programmed DCT 1 timing/termination pattern 00000000 20222222
37915247.186: mct_PlatformSpec: Done
37916247.186: ChangeMemClk: Done
37917247.186: phyAssistedMemFnceTraining: Start
37918247.186: phyAssistedMemFnceTraining: training node 3 DCT 0
37919247.186: phyAssistedMemFnceTraining: done training node 3 DCT 0
37920247.186: phyAssistedMemFnceTraining: training node 3 DCT 1
37921247.186: phyAssistedMemFnceTraining: done training node 3 DCT 1
37922247.186: phyAssistedMemFnceTraining: Done
37923247.186: InitPhyCompensation: DCT 0: Start
37924247.187: Waiting for predriver calibration to be applied...done!
37925247.187: InitPhyCompensation: DCT 0: Done
37926247.187: phyAssistedMemFnceTraining: Start
37927247.187: phyAssistedMemFnceTraining: training node 3 DCT 0
37928247.187: phyAssistedMemFnceTraining: done training node 3 DCT 0
37929247.187: phyAssistedMemFnceTraining: training node 3 DCT 1
37930247.187: phyAssistedMemFnceTraining: done training node 3 DCT 1
37931247.187: phyAssistedMemFnceTraining: Done
37932247.187: InitPhyCompensation: DCT 1: Start
37933247.187: Waiting for predriver calibration to be applied...done!
37934247.187: InitPhyCompensation: DCT 1: Done
37935247.187: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
37936247.187: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37937247.187: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
37938247.188: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37939247.187: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
37940247.187: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
37941247.187: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37942247.187: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
37943247.187: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
37944247.188: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
37945247.188: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
37946247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37947247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
37948247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37949247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
37950247.188: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
37951247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37952247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
37953247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
37954247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
37955247.188: SetTargetFreq: Done
37956247.188: SPD2ndTiming: Start
37957247.188: SPD2ndTiming: Done
37958247.188: mct_BeforeDramInit_Prod_D: Start
37959247.188: mct_ProgramODT_D: Start
37960247.188: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
37961247.188: mct_ProgramODT_D: Done
37962247.188: mct_BeforeDramInit_Prod_D: Done
37963247.188: mct_DramInit_Sw_D: Start
37964247.188: DIMM 0 RttWr: 2
37965247.188: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
37966247.188: mct_SendMrsCmd: Start
37967247.188: mct_SendMrsCmd: Done
37968247.188: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
37969247.188: mct_SendMrsCmd: Start
37970247.188: mct_SendMrsCmd: Done
37971247.188: DIMM 0 RttNom: 3
37972247.188: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
37973247.188: mct_SendMrsCmd: Start
37974247.189: mct_SendMrsCmd: Done
37975247.188: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
37976247.189: mct_SendMrsCmd: Start
37977247.188: mct_SendMrsCmd: Done
37978247.189: DIMM 0 RttWr: 2
37979247.189: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
37980247.189: mct_SendMrsCmd: Start
37981247.189: mct_SendMrsCmd: Done
37982247.189: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
37983247.189: mct_SendMrsCmd: Start
37984247.189: mct_SendMrsCmd: Done
37985247.189: DIMM 0 RttNom: 3
37986247.189: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
37987247.189: mct_SendMrsCmd: Start
37988247.189: mct_SendMrsCmd: Done
37989247.189: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
37990247.189: mct_SendMrsCmd: Start
37991247.189: mct_SendMrsCmd: Done
37992247.189: DIMM 1 RttWr: 2
37993247.189: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
37994247.189: mct_SendMrsCmd: Start
37995247.189: mct_SendMrsCmd: Done
37996247.189: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
37997247.189: mct_SendMrsCmd: Start
37998247.189: mct_SendMrsCmd: Done
37999247.189: DIMM 1 RttNom: 3
38000247.189: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38001247.189: mct_SendMrsCmd: Start
38002247.189: mct_SendMrsCmd: Done
38003247.189: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
38004247.189: mct_SendMrsCmd: Start
38005247.189: mct_SendMrsCmd: Done
38006247.189: DIMM 1 RttWr: 2
38007247.189: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38008247.189: mct_SendMrsCmd: Start
38009247.189: mct_SendMrsCmd: Done
38010247.189: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
38011247.189: mct_SendMrsCmd: Start
38012247.189: mct_SendMrsCmd: Done
38013247.189: DIMM 1 RttNom: 3
38014247.189: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38015247.189: mct_SendMrsCmd: Start
38016247.189: mct_SendMrsCmd: Done
38017247.189: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
38018247.189: mct_SendMrsCmd: Start
38019247.189: mct_SendMrsCmd: Done
38020247.189: mct_DramInit_Sw_D: Done
38021247.189: AgesaHwWlPhase1: training nibble 0
38022247.189: DIMM 0 RttNom: 3
38023247.189: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38024247.189: DIMM 0 RttWr: 2
38025247.189: DIMM 0 RttWr: 2
38026247.189: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
38027247.189: DIMM 0 RttWr: 2
38028247.189: DIMM 0 RttNom: 3
38029247.189: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38030247.189: DIMM 0 RttNom: 3
38031247.189: DIMM 0 RttWr: 2
38032247.189: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
38033247.189: DIMM 0 RttWr: 2
38034247.189: DIMM 1 RttNom: 3
38035247.189: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38036247.189: DIMM 0 RttNom: 3
38037247.190: DIMM 1 RttWr: 2
38038247.190: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
38039247.190: DIMM 0 RttWr: 2
38040247.190: DIMM 1 RttNom: 3
38041247.190: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38042247.190: DIMM 0 RttNom: 3
38043247.190: DIMM 1 RttWr: 2
38044247.190: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38045247.190: DIMM 0 RttWr: 2
38046247.190: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
38047247.190: <09>Lane 00 scaled delay: 0047
38048247.190: <09>Lane 00 new seed: 0047
38049247.190: <09>Lane 01 scaled delay: 0047
38050247.190: <09>Lane 01 new seed: 0047
38051247.190: <09>Lane 02 scaled delay: 0047
38052247.190: <09>Lane 02 new seed: 0047
38053247.190: <09>Lane 03 scaled delay: 0047
38054247.190: <09>Lane 03 new seed: 0047
38055247.190: <09>Lane 04 scaled delay: 0047
38056247.190: <09>Lane 04 new seed: 0047
38057247.190: <09>Lane 05 scaled delay: 0047
38058247.190: <09>Lane 05 new seed: 0047
38059247.190: <09>Lane 06 scaled delay: 0047
38060247.190: <09>Lane 06 new seed: 0047
38061247.190: <09>Lane 07 scaled delay: 0047
38062247.190: <09>Lane 07 new seed: 0047
38063247.190: <09>Lane 08 scaled delay: 0047
38064247.190: <09>Lane 08 new seed: 0047
38065247.190: <09>Lane 00 nibble 0 raw readback: 0046
38066247.190: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
38067247.190: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
38068247.190: <09>Lane 01 nibble 0 raw readback: 003f
38069247.190: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
38070247.190: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
38071247.190: <09>Lane 02 nibble 0 raw readback: 003d
38072247.190: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
38073247.190: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
38074247.190: <09>Lane 03 nibble 0 raw readback: 003e
38075247.190: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003e
38076247.190: <09>Lane 03 nibble 0 adjusted value (post nibble): 003e
38077247.190: <09>Lane 04 nibble 0 raw readback: 003b
38078247.190: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
38079247.190: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
38080247.190: <09>Lane 05 nibble 0 raw readback: 003e
38081247.190: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
38082247.190: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
38083247.190: <09>Lane 06 nibble 0 raw readback: 0040
38084247.190: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
38085247.190: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
38086247.191: <09>Lane 07 nibble 0 raw readback: 0043
38087247.191: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
38088247.191: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
38089247.191: <09>Lane 08 nibble 0 raw readback: 0037
38090247.191: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
38091247.191: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
38092247.191: AgesaHwWlPhase1: training nibble 1
38093247.191: DIMM 0 RttNom: 3
38094247.191: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38095247.191: DIMM 0 RttWr: 2
38096247.191: DIMM 0 RttWr: 2
38097247.191: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
38098247.191: DIMM 0 RttWr: 2
38099247.191: DIMM 0 RttNom: 3
38100247.191: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38101247.191: DIMM 0 RttNom: 3
38102247.191: DIMM 0 RttWr: 2
38103247.191: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
38104247.191: DIMM 0 RttWr: 2
38105247.191: DIMM 1 RttNom: 3
38106247.191: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38107247.191: DIMM 0 RttNom: 3
38108247.191: DIMM 1 RttWr: 2
38109247.191: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
38110247.191: DIMM 0 RttWr: 2
38111247.191: DIMM 1 RttNom: 3
38112247.191: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38113247.191: DIMM 0 RttNom: 3
38114247.191: DIMM 1 RttWr: 2
38115247.191: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38116247.191: DIMM 0 RttWr: 2
38117247.191: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
38118247.191: <09>Lane 00 new seed: 0047
38119247.191: <09>Lane 01 new seed: 0047
38120247.191: <09>Lane 02 new seed: 0047
38121247.191: <09>Lane 03 new seed: 0047
38122247.191: <09>Lane 04 new seed: 0047
38123247.191: <09>Lane 05 new seed: 0047
38124247.191: <09>Lane 06 new seed: 0047
38125247.191: <09>Lane 07 new seed: 0047
38126247.191: <09>Lane 08 new seed: 0047
38127247.191: <09>Lane 00 nibble 1 raw readback: 0047
38128247.191: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
38129247.191: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
38130247.191: <09>Lane 01 nibble 1 raw readback: 0042
38131247.191: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
38132247.191: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
38133247.191: <09>Lane 02 nibble 1 raw readback: 003e
38134247.191: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
38135247.191: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
38136247.191: <09>Lane 03 nibble 1 raw readback: 003c
38137247.191: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
38138247.191: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
38139247.191: <09>Lane 04 nibble 1 raw readback: 003a
38140247.191: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
38141247.191: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
38142247.191: <09>Lane 05 nibble 1 raw readback: 003d
38143247.191: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
38144247.194: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
38145247.191: <09>Lane 06 nibble 1 raw readback: 0041
38146247.191: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
38147247.191: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
38148247.191: <09>Lane 07 nibble 1 raw readback: 0044
38149247.191: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0044
38150247.191: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
38151247.191: <09>Lane 08 nibble 1 raw readback: 0038
38152247.191: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
38153247.191: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
38154247.192: <09>original critical gross delay: 0
38155247.192: <09>new critical gross delay: 0
38156247.192: DIMM 0 RttNom: 3
38157247.192: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38158247.192: DIMM 0 RttNom: 3
38159247.192: DIMM 0 RttWr: 2
38160247.192: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
38161247.192: DIMM 0 RttWr: 2
38162247.192: DIMM 0 RttNom: 3
38163247.192: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38164247.192: DIMM 0 RttNom: 3
38165247.192: DIMM 0 RttWr: 2
38166247.192: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
38167247.192: DIMM 0 RttWr: 2
38168247.192: DIMM 1 RttNom: 3
38169247.192: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38170247.192: DIMM 0 RttNom: 3
38171247.192: DIMM 1 RttWr: 2
38172247.192: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
38173247.192: DIMM 0 RttWr: 2
38174247.192: DIMM 1 RttNom: 3
38175247.192: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38176247.192: DIMM 0 RttNom: 3
38177247.192: DIMM 1 RttWr: 2
38178247.192: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38179247.192: DIMM 0 RttWr: 2
38180247.192: AgesaHwWlPhase1: training nibble 0
38181247.192: DIMM 1 RttNom: 3
38182247.192: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38183247.192: DIMM 1 RttWr: 2
38184247.192: DIMM 1 RttWr: 2
38185247.192: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
38186247.192: DIMM 1 RttWr: 2
38187247.192: DIMM 1 RttNom: 3
38188247.192: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38189247.192: DIMM 1 RttNom: 3
38190247.192: DIMM 1 RttWr: 2
38191247.192: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38192247.192: DIMM 1 RttWr: 2
38193247.192: DIMM 0 RttNom: 3
38194247.192: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38195247.192: DIMM 1 RttNom: 3
38196247.192: DIMM 0 RttWr: 2
38197247.192: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
38198247.192: DIMM 1 RttWr: 2
38199247.192: DIMM 0 RttNom: 3
38200247.192: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38201247.192: DIMM 1 RttNom: 3
38202247.192: DIMM 0 RttWr: 2
38203247.192: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
38204247.192: DIMM 1 RttWr: 2
38205247.192: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
38206247.192: <09>Lane 00 scaled delay: 0047
38207247.192: <09>Lane 00 new seed: 0047
38208247.192: <09>Lane 01 scaled delay: 0047
38209247.192: <09>Lane 01 new seed: 0047
38210247.192: <09>Lane 02 scaled delay: 0047
38211247.192: <09>Lane 02 new seed: 0047
38212247.193: <09>Lane 03 scaled delay: 0047
38213247.193: <09>Lane 03 new seed: 0047
38214247.193: <09>Lane 04 scaled delay: 0047
38215247.193: <09>Lane 04 new seed: 0047
38216247.193: <09>Lane 05 scaled delay: 0047
38217247.193: <09>Lane 05 new seed: 0047
38218247.193: <09>Lane 06 scaled delay: 0047
38219247.193: <09>Lane 06 new seed: 0047
38220247.193: <09>Lane 07 scaled delay: 0047
38221247.193: <09>Lane 07 new seed: 0047
38222247.193: <09>Lane 08 scaled delay: 0047
38223247.193: <09>Lane 08 new seed: 0047
38224247.193: <09>Lane 00 nibble 0 raw readback: 0045
38225247.193: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
38226247.193: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
38227247.193: <09>Lane 01 nibble 0 raw readback: 0040
38228247.193: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
38229247.193: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
38230247.193: <09>Lane 02 nibble 0 raw readback: 003d
38231247.193: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
38232247.193: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
38233247.193: <09>Lane 03 nibble 0 raw readback: 003c
38234247.193: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003c
38235247.193: <09>Lane 03 nibble 0 adjusted value (post nibble): 003c
38236247.193: <09>Lane 04 nibble 0 raw readback: 0038
38237247.193: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
38238247.193: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
38239247.193: <09>Lane 05 nibble 0 raw readback: 003c
38240247.193: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
38241247.193: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
38242247.193: <09>Lane 06 nibble 0 raw readback: 003e
38243247.193: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
38244247.193: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
38245247.193: <09>Lane 07 nibble 0 raw readback: 0042
38246247.193: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
38247247.193: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
38248247.193: <09>Lane 08 nibble 0 raw readback: 0037
38249247.193: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
38250247.193: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
38251247.193: AgesaHwWlPhase1: training nibble 1
38252247.193: DIMM 1 RttNom: 3
38253247.193: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38254247.193: DIMM 1 RttWr: 2
38255247.193: DIMM 1 RttWr: 2
38256247.193: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
38257247.193: DIMM 1 RttWr: 2
38258247.193: DIMM 1 RttNom: 3
38259247.193: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38260247.193: DIMM 1 RttNom: 3
38261247.193: DIMM 1 RttWr: 2
38262247.193: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38263247.193: DIMM 1 RttWr: 2
38264247.193: DIMM 0 RttNom: 3
38265247.193: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38266247.193: DIMM 1 RttNom: 3
38267247.193: DIMM 0 RttWr: 2
38268247.193: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
38269247.193: DIMM 1 RttWr: 2
38270247.193: DIMM 0 RttNom: 3
38271247.193: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38272247.193: DIMM 1 RttNom: 3
38273247.193: DIMM 0 RttWr: 2
38274247.193: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
38275247.193: DIMM 1 RttWr: 2
38276247.193: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
38277247.193: <09>Lane 00 new seed: 0047
38278247.193: <09>Lane 01 new seed: 0047
38279247.193: <09>Lane 02 new seed: 0047
38280247.193: <09>Lane 03 new seed: 0047
38281247.194: <09>Lane 04 new seed: 0047
38282247.194: <09>Lane 05 new seed: 0047
38283247.194: <09>Lane 06 new seed: 0047
38284247.194: <09>Lane 07 new seed: 0047
38285247.194: <09>Lane 08 new seed: 0047
38286247.194: <09>Lane 00 nibble 1 raw readback: 0044
38287247.194: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
38288247.194: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
38289247.194: <09>Lane 01 nibble 1 raw readback: 0040
38290247.194: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
38291247.194: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
38292247.194: <09>Lane 02 nibble 1 raw readback: 003d
38293247.194: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
38294247.194: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
38295247.194: <09>Lane 03 nibble 1 raw readback: 003c
38296247.194: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
38297247.194: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
38298247.194: <09>Lane 04 nibble 1 raw readback: 0039
38299247.194: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
38300247.194: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
38301247.194: <09>Lane 05 nibble 1 raw readback: 003c
38302247.194: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
38303247.194: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
38304247.194: <09>Lane 06 nibble 1 raw readback: 003d
38305247.194: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
38306247.194: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
38307247.194: <09>Lane 07 nibble 1 raw readback: 0042
38308247.194: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
38309247.194: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
38310247.194: <09>Lane 08 nibble 1 raw readback: 0036
38311247.194: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
38312247.194: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
38313247.194: <09>original critical gross delay: 0
38314247.194: <09>new critical gross delay: 0
38315247.194: DIMM 1 RttNom: 3
38316247.194: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38317247.194: DIMM 1 RttNom: 3
38318247.194: DIMM 1 RttWr: 2
38319247.194: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
38320247.194: DIMM 1 RttWr: 2
38321247.194: DIMM 1 RttNom: 3
38322247.194: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38323247.194: DIMM 1 RttNom: 3
38324247.194: DIMM 1 RttWr: 2
38325247.194: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
38326247.194: DIMM 1 RttWr: 2
38327247.194: DIMM 0 RttNom: 3
38328247.194: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38329247.194: DIMM 1 RttNom: 3
38330247.194: DIMM 0 RttWr: 2
38331247.194: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
38332247.194: DIMM 1 RttWr: 2
38333247.194: DIMM 0 RttNom: 3
38334247.194: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38335247.194: DIMM 1 RttNom: 3
38336247.194: DIMM 0 RttWr: 2
38337247.194: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
38338247.194: DIMM 1 RttWr: 2
38339247.195: SPD2ndTiming: Start
38340247.195: SPD2ndTiming: Done
38341247.195: mct_BeforeDramInit_Prod_D: Start
38342247.195: mct_ProgramODT_D: Start
38343247.195: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
38344247.195: mct_ProgramODT_D: Done
38345247.195: mct_BeforeDramInit_Prod_D: Done
38346247.195: mct_DramInit_Sw_D: Start
38347247.195: DIMM 0 RttWr: 2
38348247.195: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38349247.195: mct_SendMrsCmd: Start
38350247.195: mct_SendMrsCmd: Done
38351247.195: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
38352247.195: mct_SendMrsCmd: Start
38353247.195: mct_SendMrsCmd: Done
38354247.195: DIMM 0 RttNom: 3
38355247.195: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38356247.195: mct_SendMrsCmd: Start
38357247.195: mct_SendMrsCmd: Done
38358247.195: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
38359247.195: mct_SendMrsCmd: Start
38360247.195: mct_SendMrsCmd: Done
38361247.195: DIMM 0 RttWr: 2
38362247.195: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38363247.195: mct_SendMrsCmd: Start
38364247.195: mct_SendMrsCmd: Done
38365247.195: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
38366247.195: mct_SendMrsCmd: Start
38367247.195: mct_SendMrsCmd: Done
38368247.195: DIMM 0 RttNom: 3
38369247.195: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38370247.195: mct_SendMrsCmd: Start
38371247.195: mct_SendMrsCmd: Done
38372247.195: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
38373247.195: mct_SendMrsCmd: Start
38374247.195: mct_SendMrsCmd: Done
38375247.195: DIMM 1 RttWr: 2
38376247.195: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38377247.195: mct_SendMrsCmd: Start
38378247.195: mct_SendMrsCmd: Done
38379247.195: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
38380247.196: mct_SendMrsCmd: Start
38381247.196: mct_SendMrsCmd: Done
38382247.196: DIMM 1 RttNom: 3
38383247.196: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38384247.196: mct_SendMrsCmd: Start
38385247.196: mct_SendMrsCmd: Done
38386247.196: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
38387247.196: mct_SendMrsCmd: Start
38388247.196: mct_SendMrsCmd: Done
38389247.196: DIMM 1 RttWr: 2
38390247.196: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38391247.196: mct_SendMrsCmd: Start
38392247.196: mct_SendMrsCmd: Done
38393247.196: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
38394247.196: mct_SendMrsCmd: Start
38395247.196: mct_SendMrsCmd: Done
38396247.196: DIMM 1 RttNom: 3
38397247.196: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38398247.196: mct_SendMrsCmd: Start
38399247.196: mct_SendMrsCmd: Done
38400247.196: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
38401247.196: mct_SendMrsCmd: Start
38402247.196: mct_SendMrsCmd: Done
38403247.196: mct_DramInit_Sw_D: Done
38404247.196: AgesaHwWlPhase1: training nibble 0
38405247.196: DIMM 0 RttNom: 3
38406247.196: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38407247.196: DIMM 0 RttWr: 2
38408247.196: DIMM 0 RttWr: 2
38409247.196: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38410247.196: DIMM 0 RttWr: 2
38411247.196: DIMM 0 RttNom: 3
38412247.196: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38413247.196: DIMM 0 RttNom: 3
38414247.196: DIMM 0 RttWr: 2
38415247.196: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38416247.196: DIMM 0 RttWr: 2
38417247.196: DIMM 1 RttNom: 3
38418247.196: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38419247.196: DIMM 0 RttNom: 3
38420247.196: DIMM 1 RttWr: 2
38421247.196: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38422247.196: DIMM 0 RttWr: 2
38423247.196: DIMM 1 RttNom: 3
38424247.196: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38425247.197: DIMM 0 RttNom: 3
38426247.196: DIMM 1 RttWr: 2
38427247.196: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38428247.196: DIMM 0 RttWr: 2
38429247.196: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
38430247.196: <09>Lane 00 scaled delay: 0047
38431247.196: <09>Lane 00 new seed: 0047
38432247.196: <09>Lane 01 scaled delay: 0047
38433247.196: <09>Lane 01 new seed: 0047
38434247.196: <09>Lane 02 scaled delay: 0047
38435247.196: <09>Lane 02 new seed: 0047
38436247.196: <09>Lane 03 scaled delay: 0047
38437247.196: <09>Lane 03 new seed: 0047
38438247.196: <09>Lane 04 scaled delay: 0047
38439247.196: <09>Lane 04 new seed: 0047
38440247.196: <09>Lane 05 scaled delay: 0047
38441247.197: <09>Lane 05 new seed: 0047
38442247.196: <09>Lane 06 scaled delay: 0047
38443247.196: <09>Lane 06 new seed: 0047
38444247.196: <09>Lane 07 scaled delay: 0047
38445247.197: <09>Lane 07 new seed: 0047
38446247.197: <09>Lane 08 scaled delay: 0047
38447247.197: <09>Lane 08 new seed: 0047
38448247.197: <09>Lane 00 nibble 0 raw readback: 0047
38449247.197: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0047
38450247.197: <09>Lane 00 nibble 0 adjusted value (post nibble): 0047
38451247.197: <09>Lane 01 nibble 0 raw readback: 0042
38452247.197: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
38453247.197: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
38454247.197: <09>Lane 02 nibble 0 raw readback: 003e
38455247.197: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
38456247.197: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
38457247.197: <09>Lane 03 nibble 0 raw readback: 003b
38458247.197: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
38459247.197: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
38460247.197: <09>Lane 04 nibble 0 raw readback: 003a
38461247.197: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
38462247.197: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
38463247.197: <09>Lane 05 nibble 0 raw readback: 003e
38464247.197: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
38465247.197: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
38466247.197: <09>Lane 06 nibble 0 raw readback: 0041
38467247.197: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
38468247.197: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
38469247.197: <09>Lane 07 nibble 0 raw readback: 0045
38470247.197: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
38471247.197: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
38472247.197: <09>Lane 08 nibble 0 raw readback: 0037
38473247.197: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
38474247.197: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
38475247.197: AgesaHwWlPhase1: training nibble 1
38476247.197: DIMM 0 RttNom: 3
38477247.197: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38478247.197: DIMM 0 RttWr: 2
38479247.197: DIMM 0 RttWr: 2
38480247.197: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38481247.197: DIMM 0 RttWr: 2
38482247.197: DIMM 0 RttNom: 3
38483247.197: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38484247.197: DIMM 0 RttNom: 3
38485247.197: DIMM 0 RttWr: 2
38486247.197: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38487247.197: DIMM 0 RttWr: 2
38488247.197: DIMM 1 RttNom: 3
38489247.197: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38490247.197: DIMM 0 RttNom: 3
38491247.197: DIMM 1 RttWr: 2
38492247.197: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38493247.197: DIMM 0 RttWr: 2
38494247.197: DIMM 1 RttNom: 3
38495247.197: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38496247.197: DIMM 0 RttNom: 3
38497247.197: DIMM 1 RttWr: 2
38498247.197: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38499247.197: DIMM 0 RttWr: 2
38500247.197: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
38501247.197: <09>Lane 00 new seed: 0047
38502247.197: <09>Lane 01 new seed: 0047
38503247.197: <09>Lane 02 new seed: 0047
38504247.198: <09>Lane 03 new seed: 0047
38505247.197: <09>Lane 04 new seed: 0047
38506247.197: <09>Lane 05 new seed: 0047
38507247.198: <09>Lane 06 new seed: 0047
38508247.198: <09>Lane 07 new seed: 0047
38509247.198: <09>Lane 08 new seed: 0047
38510247.198: <09>Lane 00 nibble 1 raw readback: 0048
38511247.198: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0048
38512247.198: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
38513247.198: <09>Lane 01 nibble 1 raw readback: 0044
38514247.198: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
38515247.198: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
38516247.198: <09>Lane 02 nibble 1 raw readback: 0040
38517247.198: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
38518247.198: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
38519247.198: <09>Lane 03 nibble 1 raw readback: 003b
38520247.198: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
38521247.198: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
38522247.198: <09>Lane 04 nibble 1 raw readback: 003a
38523247.198: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
38524247.198: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
38525247.198: <09>Lane 05 nibble 1 raw readback: 003d
38526247.198: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
38527247.198: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
38528247.198: <09>Lane 06 nibble 1 raw readback: 0041
38529247.198: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
38530247.198: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
38531247.198: <09>Lane 07 nibble 1 raw readback: 0046
38532247.198: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
38533247.198: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
38534247.198: <09>Lane 08 nibble 1 raw readback: 0039
38535247.198: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
38536247.198: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
38537247.198: <09>original critical gross delay: 0
38538247.198: <09>new critical gross delay: 0
38539247.198: DIMM 0 RttNom: 3
38540247.198: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38541247.198: DIMM 0 RttNom: 3
38542247.198: DIMM 0 RttWr: 2
38543247.198: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38544247.198: DIMM 0 RttWr: 2
38545247.198: DIMM 0 RttNom: 3
38546247.198: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38547247.198: DIMM 0 RttNom: 3
38548247.198: DIMM 0 RttWr: 2
38549247.198: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38550247.198: DIMM 0 RttWr: 2
38551247.198: DIMM 1 RttNom: 3
38552247.198: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38553247.198: DIMM 0 RttNom: 3
38554247.198: DIMM 1 RttWr: 2
38555247.198: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38556247.198: DIMM 0 RttWr: 2
38557247.198: DIMM 1 RttNom: 3
38558247.198: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38559247.198: DIMM 0 RttNom: 3
38560247.198: DIMM 1 RttWr: 2
38561247.198: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38562247.198: DIMM 0 RttWr: 2
38563247.198: AgesaHwWlPhase1: training nibble 0
38564247.198: DIMM 1 RttNom: 3
38565247.198: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38566247.198: DIMM 1 RttWr: 2
38567247.198: DIMM 1 RttWr: 2
38568247.199: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38569247.198: DIMM 1 RttWr: 2
38570247.199: DIMM 1 RttNom: 3
38571247.199: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38572247.199: DIMM 1 RttNom: 3
38573247.199: DIMM 1 RttWr: 2
38574247.199: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38575247.199: DIMM 1 RttWr: 2
38576247.199: DIMM 0 RttNom: 3
38577247.199: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38578247.199: DIMM 1 RttNom: 3
38579247.199: DIMM 0 RttWr: 2
38580247.199: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38581247.199: DIMM 1 RttWr: 2
38582247.199: DIMM 0 RttNom: 3
38583247.199: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38584247.199: DIMM 1 RttNom: 3
38585247.199: DIMM 0 RttWr: 2
38586247.199: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38587247.199: DIMM 1 RttWr: 2
38588247.199: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
38589247.199: <09>Lane 00 scaled delay: 0047
38590247.199: <09>Lane 00 new seed: 0047
38591247.199: <09>Lane 01 scaled delay: 0047
38592247.199: <09>Lane 01 new seed: 0047
38593247.199: <09>Lane 02 scaled delay: 0047
38594247.199: <09>Lane 02 new seed: 0047
38595247.199: <09>Lane 03 scaled delay: 0047
38596247.199: <09>Lane 03 new seed: 0047
38597247.199: <09>Lane 04 scaled delay: 0047
38598247.199: <09>Lane 04 new seed: 0047
38599247.199: <09>Lane 05 scaled delay: 0047
38600247.199: <09>Lane 05 new seed: 0047
38601247.199: <09>Lane 06 scaled delay: 0047
38602247.199: <09>Lane 06 new seed: 0047
38603247.199: <09>Lane 07 scaled delay: 0047
38604247.199: <09>Lane 07 new seed: 0047
38605247.199: <09>Lane 08 scaled delay: 0047
38606247.199: <09>Lane 08 new seed: 0047
38607247.199: <09>Lane 00 nibble 0 raw readback: 0047
38608247.199: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0047
38609247.199: <09>Lane 00 nibble 0 adjusted value (post nibble): 0047
38610247.199: <09>Lane 01 nibble 0 raw readback: 0042
38611247.199: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
38612247.199: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
38613247.199: <09>Lane 02 nibble 0 raw readback: 003d
38614247.199: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
38615247.199: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
38616247.199: <09>Lane 03 nibble 0 raw readback: 003b
38617247.199: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
38618247.199: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
38619247.199: <09>Lane 04 nibble 0 raw readback: 0039
38620247.199: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
38621247.199: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
38622247.199: <09>Lane 05 nibble 0 raw readback: 003e
38623247.199: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
38624247.199: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
38625247.199: <09>Lane 06 nibble 0 raw readback: 0042
38626247.199: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0042
38627247.199: <09>Lane 06 nibble 0 adjusted value (post nibble): 0042
38628247.199: <09>Lane 07 nibble 0 raw readback: 0045
38629247.199: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
38630247.199: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
38631247.199: <09>Lane 08 nibble 0 raw readback: 0039
38632247.199: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
38633247.199: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
38634247.199: AgesaHwWlPhase1: training nibble 1
38635247.199: DIMM 1 RttNom: 3
38636247.199: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38637247.199: DIMM 1 RttWr: 2
38638247.199: DIMM 1 RttWr: 2
38639247.200: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38640247.199: DIMM 1 RttWr: 2
38641247.200: DIMM 1 RttNom: 3
38642247.200: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38643247.200: DIMM 1 RttNom: 3
38644247.200: DIMM 1 RttWr: 2
38645247.200: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38646247.200: DIMM 1 RttWr: 2
38647247.200: DIMM 0 RttNom: 3
38648247.200: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38649247.200: DIMM 1 RttNom: 3
38650247.200: DIMM 0 RttWr: 2
38651247.200: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38652247.200: DIMM 1 RttWr: 2
38653247.200: DIMM 0 RttNom: 3
38654247.200: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38655247.200: DIMM 1 RttNom: 3
38656247.200: DIMM 0 RttWr: 2
38657247.200: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38658247.200: DIMM 1 RttWr: 2
38659247.200: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
38660247.200: <09>Lane 00 new seed: 0047
38661247.200: <09>Lane 01 new seed: 0047
38662247.200: <09>Lane 02 new seed: 0047
38663247.200: <09>Lane 03 new seed: 0047
38664247.200: <09>Lane 04 new seed: 0047
38665247.200: <09>Lane 05 new seed: 0047
38666247.200: <09>Lane 06 new seed: 0047
38667247.200: <09>Lane 07 new seed: 0047
38668247.200: <09>Lane 08 new seed: 0047
38669247.200: <09>Lane 00 nibble 1 raw readback: 0047
38670247.200: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
38671247.200: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
38672247.200: <09>Lane 01 nibble 1 raw readback: 0043
38673247.200: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0043
38674247.200: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
38675247.200: <09>Lane 02 nibble 1 raw readback: 003e
38676247.200: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
38677247.200: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
38678247.200: <09>Lane 03 nibble 1 raw readback: 003c
38679247.200: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
38680247.200: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
38681247.200: <09>Lane 04 nibble 1 raw readback: 0039
38682247.200: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
38683247.200: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
38684247.200: <09>Lane 05 nibble 1 raw readback: 003d
38685247.200: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
38686247.200: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
38687247.200: <09>Lane 06 nibble 1 raw readback: 0042
38688247.200: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0042
38689247.200: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
38690247.200: <09>Lane 07 nibble 1 raw readback: 0045
38691247.200: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
38692247.200: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
38693247.200: <09>Lane 08 nibble 1 raw readback: 0037
38694247.200: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
38695247.200: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
38696247.200: <09>original critical gross delay: 0
38697247.200: <09>new critical gross delay: 0
38698247.200: DIMM 1 RttNom: 3
38699247.200: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
38700247.200: DIMM 1 RttNom: 3
38701247.200: DIMM 1 RttWr: 2
38702247.200: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
38703247.200: DIMM 1 RttWr: 2
38704247.200: DIMM 1 RttNom: 3
38705247.200: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
38706247.201: DIMM 1 RttNom: 3
38707247.201: DIMM 1 RttWr: 2
38708247.201: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
38709247.201: DIMM 1 RttWr: 2
38710247.201: DIMM 0 RttNom: 3
38711247.201: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
38712247.201: DIMM 1 RttNom: 3
38713247.201: DIMM 0 RttWr: 2
38714247.201: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
38715247.201: DIMM 1 RttWr: 2
38716247.201: DIMM 0 RttNom: 3
38717247.201: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
38718247.201: DIMM 1 RttNom: 3
38719247.201: DIMM 0 RttWr: 2
38720247.201: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
38721247.201: DIMM 1 RttWr: 2
38722247.201: SetTargetFreq: Start
38723247.201: SetTargetFreq: Node 3: New frequency code: 000a
38724247.201: ChangeMemClk: Start
38725247.201: set_2t_configuration: Start
38726247.201: set_2t_configuration: Done
38727247.201: mct_BeforePlatformSpec: Start
38728247.201: mct_BeforePlatformSpec: Done
38729247.201: mct_PlatformSpec: Start
38730247.201: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
38731247.201: mct_PlatformSpec: Done
38732247.201: set_2t_configuration: Start
38733247.201: set_2t_configuration: Done
38734247.201: mct_BeforePlatformSpec: Start
38735247.201: mct_BeforePlatformSpec: Done
38736247.201: mct_PlatformSpec: Start
38737247.201: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
38738247.201: mct_PlatformSpec: Done
38739247.201: ChangeMemClk: Done
38740247.201: phyAssistedMemFnceTraining: Start
38741247.201: phyAssistedMemFnceTraining: training node 3 DCT 0
38742247.202: phyAssistedMemFnceTraining: done training node 3 DCT 0
38743247.202: phyAssistedMemFnceTraining: training node 3 DCT 1
38744247.202: phyAssistedMemFnceTraining: done training node 3 DCT 1
38745247.202: phyAssistedMemFnceTraining: Done
38746247.202: InitPhyCompensation: DCT 0: Start
38747247.202: Waiting for predriver calibration to be applied...done!
38748247.202: InitPhyCompensation: DCT 0: Done
38749247.202: phyAssistedMemFnceTraining: Start
38750247.202: phyAssistedMemFnceTraining: training node 3 DCT 0
38751247.202: phyAssistedMemFnceTraining: done training node 3 DCT 0
38752247.202: phyAssistedMemFnceTraining: training node 3 DCT 1
38753247.202: phyAssistedMemFnceTraining: done training node 3 DCT 1
38754247.202: phyAssistedMemFnceTraining: Done
38755247.202: InitPhyCompensation: DCT 1: Start
38756247.202: Waiting for predriver calibration to be applied...done!
38757247.202: InitPhyCompensation: DCT 1: Done
38758247.202: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
38759247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
38760247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
38761247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
38762247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
38763247.203: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
38764247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
38765247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
38766247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
38767247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
38768247.203: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
38769247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
38770247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
38771247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
38772247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
38773247.203: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
38774247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
38775247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
38776247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
38777247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
38778247.203: SetTargetFreq: Done
38779247.203: SPD2ndTiming: Start
38780247.203: SPD2ndTiming: Done
38781247.203: mct_BeforeDramInit_Prod_D: Start
38782247.203: mct_ProgramODT_D: Start
38783247.203: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
38784247.203: mct_ProgramODT_D: Done
38785247.203: mct_BeforeDramInit_Prod_D: Done
38786247.203: mct_DramInit_Sw_D: Start
38787247.203: DIMM 0 RttWr: 1
38788247.203: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
38789247.203: mct_SendMrsCmd: Start
38790247.203: mct_SendMrsCmd: Done
38791247.203: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
38792247.203: mct_SendMrsCmd: Start
38793247.203: mct_SendMrsCmd: Done
38794247.203: DIMM 0 RttNom: 3
38795247.203: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38796247.203: mct_SendMrsCmd: Start
38797247.204: mct_SendMrsCmd: Done
38798247.204: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
38799247.204: mct_SendMrsCmd: Start
38800247.204: mct_SendMrsCmd: Done
38801247.204: DIMM 0 RttWr: 1
38802247.204: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
38803247.204: mct_SendMrsCmd: Start
38804247.204: mct_SendMrsCmd: Done
38805247.204: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
38806247.204: mct_SendMrsCmd: Start
38807247.204: mct_SendMrsCmd: Done
38808247.204: DIMM 0 RttNom: 3
38809247.204: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38810247.204: mct_SendMrsCmd: Start
38811247.204: mct_SendMrsCmd: Done
38812247.204: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
38813247.204: mct_SendMrsCmd: Start
38814247.204: mct_SendMrsCmd: Done
38815247.204: DIMM 1 RttWr: 1
38816247.204: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
38817247.204: mct_SendMrsCmd: Start
38818247.204: mct_SendMrsCmd: Done
38819247.204: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
38820247.204: mct_SendMrsCmd: Start
38821247.204: mct_SendMrsCmd: Done
38822247.204: DIMM 1 RttNom: 3
38823247.204: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38824247.204: mct_SendMrsCmd: Start
38825247.204: mct_SendMrsCmd: Done
38826247.204: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
38827247.204: mct_SendMrsCmd: Start
38828247.204: mct_SendMrsCmd: Done
38829247.204: DIMM 1 RttWr: 1
38830247.204: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
38831247.204: mct_SendMrsCmd: Start
38832247.204: mct_SendMrsCmd: Done
38833247.204: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
38834247.204: mct_SendMrsCmd: Start
38835247.204: mct_SendMrsCmd: Done
38836247.204: DIMM 1 RttNom: 3
38837247.204: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38838247.204: mct_SendMrsCmd: Start
38839247.204: mct_SendMrsCmd: Done
38840247.204: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
38841247.204: mct_SendMrsCmd: Start
38842247.204: mct_SendMrsCmd: Done
38843247.204: mct_DramInit_Sw_D: Done
38844247.204: AgesaHwWlPhase1: training nibble 0
38845247.204: DIMM 0 RttNom: 3
38846247.204: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38847247.204: DIMM 0 RttWr: 1
38848247.204: DIMM 0 RttWr: 1
38849247.204: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
38850247.204: DIMM 0 RttWr: 1
38851247.204: DIMM 0 RttNom: 3
38852247.204: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38853247.204: DIMM 0 RttNom: 3
38854247.204: DIMM 0 RttWr: 1
38855247.205: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
38856247.204: DIMM 0 RttWr: 1
38857247.205: DIMM 1 RttNom: 3
38858247.205: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38859247.205: DIMM 0 RttNom: 3
38860247.205: DIMM 1 RttWr: 1
38861247.205: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
38862247.205: DIMM 0 RttWr: 1
38863247.205: DIMM 1 RttNom: 3
38864247.205: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38865247.205: DIMM 0 RttNom: 3
38866247.205: DIMM 1 RttWr: 1
38867247.205: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
38868247.205: DIMM 0 RttWr: 1
38869247.205: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
38870247.205: <09>Lane 00 scaled delay: 0053
38871247.205: <09>Lane 00 new seed: 0053
38872247.205: <09>Lane 01 scaled delay: 004f
38873247.205: <09>Lane 01 new seed: 004f
38874247.205: <09>Lane 02 scaled delay: 004d
38875247.205: <09>Lane 02 new seed: 004d
38876247.205: <09>Lane 03 scaled delay: 004b
38877247.205: <09>Lane 03 new seed: 004b
38878247.205: <09>Lane 04 scaled delay: 004a
38879247.205: <09>Lane 04 new seed: 004a
38880247.205: <09>Lane 05 scaled delay: 004d
38881247.205: <09>Lane 05 new seed: 004d
38882247.205: <09>Lane 06 scaled delay: 004f
38883247.205: <09>Lane 06 new seed: 004f
38884247.205: <09>Lane 07 scaled delay: 0051
38885247.205: <09>Lane 07 new seed: 0051
38886247.205: <09>Lane 08 scaled delay: 0049
38887247.205: <09>Lane 08 new seed: 0049
38888247.205: <09>Lane 00 nibble 0 raw readback: 0052
38889247.205: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
38890247.205: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
38891247.205: <09>Lane 01 nibble 0 raw readback: 0049
38892247.205: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
38893247.205: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
38894247.205: <09>Lane 02 nibble 0 raw readback: 0047
38895247.205: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
38896247.205: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
38897247.205: <09>Lane 03 nibble 0 raw readback: 0048
38898247.205: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0048
38899247.205: <09>Lane 03 nibble 0 adjusted value (post nibble): 0048
38900247.205: <09>Lane 04 nibble 0 raw readback: 0045
38901247.205: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0045
38902247.205: <09>Lane 04 nibble 0 adjusted value (post nibble): 0045
38903247.205: <09>Lane 05 nibble 0 raw readback: 004a
38904247.205: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004a
38905247.205: <09>Lane 05 nibble 0 adjusted value (post nibble): 004a
38906247.205: <09>Lane 06 nibble 0 raw readback: 004b
38907247.205: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
38908247.205: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
38909247.205: <09>Lane 07 nibble 0 raw readback: 004f
38910247.205: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004f
38911247.205: <09>Lane 07 nibble 0 adjusted value (post nibble): 004f
38912247.205: <09>Lane 08 nibble 0 raw readback: 003f
38913247.206: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
38914247.206: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
38915247.206: AgesaHwWlPhase1: training nibble 1
38916247.206: DIMM 0 RttNom: 3
38917247.206: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38918247.206: DIMM 0 RttWr: 1
38919247.206: DIMM 0 RttWr: 1
38920247.206: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
38921247.206: DIMM 0 RttWr: 1
38922247.206: DIMM 0 RttNom: 3
38923247.206: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38924247.206: DIMM 0 RttNom: 3
38925247.206: DIMM 0 RttWr: 1
38926247.206: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
38927247.206: DIMM 0 RttWr: 1
38928247.206: DIMM 1 RttNom: 3
38929247.206: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38930247.206: DIMM 0 RttNom: 3
38931247.206: DIMM 1 RttWr: 1
38932247.206: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
38933247.206: DIMM 0 RttWr: 1
38934247.206: DIMM 1 RttNom: 3
38935247.206: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38936247.206: DIMM 0 RttNom: 3
38937247.206: DIMM 1 RttWr: 1
38938247.206: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
38939247.206: DIMM 0 RttWr: 1
38940247.206: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
38941247.206: <09>Lane 00 new seed: 0053
38942247.206: <09>Lane 01 new seed: 004f
38943247.206: <09>Lane 02 new seed: 004d
38944247.206: <09>Lane 03 new seed: 004b
38945247.206: <09>Lane 04 new seed: 004a
38946247.206: <09>Lane 05 new seed: 004d
38947247.206: <09>Lane 06 new seed: 004f
38948247.206: <09>Lane 07 new seed: 0051
38949247.206: <09>Lane 08 new seed: 0049
38950247.206: <09>Lane 00 nibble 1 raw readback: 0054
38951247.206: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
38952247.206: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
38953247.206: <09>Lane 01 nibble 1 raw readback: 004e
38954247.206: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
38955247.206: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
38956247.206: <09>Lane 02 nibble 1 raw readback: 004a
38957247.206: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
38958247.206: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
38959247.206: <09>Lane 03 nibble 1 raw readback: 0045
38960247.206: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
38961247.206: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
38962247.206: <09>Lane 04 nibble 1 raw readback: 0044
38963247.206: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0044
38964247.206: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
38965247.206: <09>Lane 05 nibble 1 raw readback: 0047
38966247.206: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
38967247.206: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
38968247.206: <09>Lane 06 nibble 1 raw readback: 004d
38969247.206: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
38970247.206: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
38971247.206: <09>Lane 07 nibble 1 raw readback: 0051
38972247.206: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
38973247.206: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
38974247.206: <09>Lane 08 nibble 1 raw readback: 0041
38975247.206: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
38976247.206: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
38977247.206: <09>original critical gross delay: 0
38978247.206: <09>new critical gross delay: 0
38979247.207: DIMM 0 RttNom: 3
38980247.207: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
38981247.207: DIMM 0 RttNom: 3
38982247.207: DIMM 0 RttWr: 1
38983247.207: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
38984247.207: DIMM 0 RttWr: 1
38985247.207: DIMM 0 RttNom: 3
38986247.207: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
38987247.207: DIMM 0 RttNom: 3
38988247.207: DIMM 0 RttWr: 1
38989247.207: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
38990247.207: DIMM 0 RttWr: 1
38991247.207: DIMM 1 RttNom: 3
38992247.207: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
38993247.207: DIMM 0 RttNom: 3
38994247.207: DIMM 1 RttWr: 1
38995247.207: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
38996247.207: DIMM 0 RttWr: 1
38997247.207: DIMM 1 RttNom: 3
38998247.207: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
38999247.207: DIMM 0 RttNom: 3
39000247.207: DIMM 1 RttWr: 1
39001247.207: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
39002247.207: DIMM 0 RttWr: 1
39003247.207: AgesaHwWlPhase1: training nibble 0
39004247.207: DIMM 1 RttNom: 3
39005247.207: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
39006247.207: DIMM 1 RttWr: 1
39007247.207: DIMM 1 RttWr: 1
39008247.207: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
39009247.207: DIMM 1 RttWr: 1
39010247.207: DIMM 1 RttNom: 3
39011247.207: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
39012247.207: DIMM 1 RttNom: 3
39013247.207: DIMM 1 RttWr: 1
39014247.207: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
39015247.207: DIMM 1 RttWr: 1
39016247.207: DIMM 0 RttNom: 3
39017247.207: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
39018247.207: DIMM 1 RttNom: 3
39019247.207: DIMM 0 RttWr: 1
39020247.207: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
39021247.207: DIMM 1 RttWr: 1
39022247.207: DIMM 0 RttNom: 3
39023247.207: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
39024247.207: DIMM 1 RttNom: 3
39025247.207: DIMM 0 RttWr: 1
39026247.207: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
39027247.207: DIMM 1 RttWr: 1
39028247.207: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
39029247.207: <09>Lane 00 scaled delay: 0051
39030247.207: <09>Lane 00 new seed: 0051
39031247.207: <09>Lane 01 scaled delay: 004e
39032247.207: <09>Lane 01 new seed: 004e
39033247.207: <09>Lane 02 scaled delay: 004d
39034247.207: <09>Lane 02 new seed: 004d
39035247.207: <09>Lane 03 scaled delay: 004b
39036247.207: <09>Lane 03 new seed: 004b
39037247.207: <09>Lane 04 scaled delay: 004a
39038247.208: <09>Lane 04 new seed: 004a
39039247.207: <09>Lane 05 scaled delay: 004b
39040247.208: <09>Lane 05 new seed: 004b
39041247.208: <09>Lane 06 scaled delay: 004d
39042247.208: <09>Lane 06 new seed: 004d
39043247.208: <09>Lane 07 scaled delay: 004f
39044247.208: <09>Lane 07 new seed: 004f
39045247.208: <09>Lane 08 scaled delay: 0047
39046247.208: <09>Lane 08 new seed: 0047
39047247.208: <09>Lane 00 nibble 0 raw readback: 0051
39048247.208: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0051
39049247.208: <09>Lane 00 nibble 0 adjusted value (post nibble): 0051
39050247.208: <09>Lane 01 nibble 0 raw readback: 004b
39051247.208: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
39052247.208: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
39053247.208: <09>Lane 02 nibble 0 raw readback: 0046
39054247.208: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
39055247.208: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
39056247.208: <09>Lane 03 nibble 0 raw readback: 0045
39057247.208: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
39058247.208: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
39059247.208: <09>Lane 04 nibble 0 raw readback: 0042
39060247.208: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
39061247.208: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
39062247.208: <09>Lane 05 nibble 0 raw readback: 0046
39063247.208: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
39064247.208: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
39065247.208: <09>Lane 06 nibble 0 raw readback: 0048
39066247.208: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
39067247.208: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
39068247.208: <09>Lane 07 nibble 0 raw readback: 004d
39069247.208: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
39070247.208: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
39071247.208: <09>Lane 08 nibble 0 raw readback: 003e
39072247.208: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
39073247.208: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
39074247.208: AgesaHwWlPhase1: training nibble 1
39075247.208: DIMM 1 RttNom: 3
39076247.208: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
39077247.208: DIMM 1 RttWr: 1
39078247.208: DIMM 1 RttWr: 1
39079247.208: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
39080247.208: DIMM 1 RttWr: 1
39081247.208: DIMM 1 RttNom: 3
39082247.208: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
39083247.208: DIMM 1 RttNom: 3
39084247.208: DIMM 1 RttWr: 1
39085247.208: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
39086247.208: DIMM 1 RttWr: 1
39087247.208: DIMM 0 RttNom: 3
39088247.208: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
39089247.208: DIMM 1 RttNom: 3
39090247.208: DIMM 0 RttWr: 1
39091247.208: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
39092247.208: DIMM 1 RttWr: 1
39093247.208: DIMM 0 RttNom: 3
39094247.208: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
39095247.208: DIMM 1 RttNom: 3
39096247.208: DIMM 0 RttWr: 1
39097247.208: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
39098247.208: DIMM 1 RttWr: 1
39099247.208: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
39100247.208: <09>Lane 00 new seed: 0051
39101247.208: <09>Lane 01 new seed: 004e
39102247.208: <09>Lane 02 new seed: 004d
39103247.208: <09>Lane 03 new seed: 004b
39104247.208: <09>Lane 04 new seed: 004a
39105247.208: <09>Lane 05 new seed: 004b
39106247.208: <09>Lane 06 new seed: 004d
39107247.209: <09>Lane 07 new seed: 004f
39108247.208: <09>Lane 08 new seed: 0047
39109247.209: <09>Lane 00 nibble 1 raw readback: 0050
39110247.209: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0050
39111247.209: <09>Lane 00 nibble 1 adjusted value (post nibble): 0050
39112247.209: <09>Lane 01 nibble 1 raw readback: 004a
39113247.209: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
39114247.209: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
39115247.209: <09>Lane 02 nibble 1 raw readback: 0046
39116247.209: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
39117247.209: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
39118247.209: <09>Lane 03 nibble 1 raw readback: 0044
39119247.209: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
39120247.209: <09>Lane 03 nibble 1 adjusted value (post nibble): 0047
39121247.209: <09>Lane 04 nibble 1 raw readback: 0040
39122247.209: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
39123247.209: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
39124247.209: <09>Lane 05 nibble 1 raw readback: 0045
39125247.209: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
39126247.209: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
39127247.209: <09>Lane 06 nibble 1 raw readback: 0046
39128247.209: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
39129247.209: <09>Lane 06 nibble 1 adjusted value (post nibble): 0049
39130247.209: <09>Lane 07 nibble 1 raw readback: 004c
39131247.209: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
39132247.209: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
39133247.209: <09>Lane 08 nibble 1 raw readback: 003c
39134247.209: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
39135247.209: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
39136247.209: <09>original critical gross delay: 0
39137247.209: <09>new critical gross delay: 0
39138247.209: DIMM 1 RttNom: 3
39139247.209: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
39140247.209: DIMM 1 RttNom: 3
39141247.209: DIMM 1 RttWr: 1
39142247.209: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
39143247.209: DIMM 1 RttWr: 1
39144247.209: DIMM 1 RttNom: 3
39145247.209: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
39146247.209: DIMM 1 RttNom: 3
39147247.209: DIMM 1 RttWr: 1
39148247.209: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
39149247.209: DIMM 1 RttWr: 1
39150247.209: DIMM 0 RttNom: 3
39151247.209: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
39152247.209: DIMM 1 RttNom: 3
39153247.209: DIMM 0 RttWr: 1
39154247.209: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
39155247.209: DIMM 1 RttWr: 1
39156247.209: DIMM 0 RttNom: 3
39157247.209: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
39158247.209: DIMM 1 RttNom: 3
39159247.209: DIMM 0 RttWr: 1
39160247.209: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
39161247.209: DIMM 1 RttWr: 1
39162247.209: SPD2ndTiming: Start
39163247.210: SPD2ndTiming: Done
39164247.210: mct_BeforeDramInit_Prod_D: Start
39165247.210: mct_ProgramODT_D: Start
39166247.210: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
39167247.210: mct_ProgramODT_D: Done
39168247.210: mct_BeforeDramInit_Prod_D: Done
39169247.210: mct_DramInit_Sw_D: Start
39170247.210: DIMM 0 RttWr: 1
39171247.210: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39172247.210: mct_SendMrsCmd: Start
39173247.210: mct_SendMrsCmd: Done
39174247.210: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
39175247.210: mct_SendMrsCmd: Start
39176247.210: mct_SendMrsCmd: Done
39177247.210: DIMM 0 RttNom: 3
39178247.210: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39179247.210: mct_SendMrsCmd: Start
39180247.210: mct_SendMrsCmd: Done
39181247.210: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
39182247.210: mct_SendMrsCmd: Start
39183247.210: mct_SendMrsCmd: Done
39184247.210: DIMM 0 RttWr: 1
39185247.210: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39186247.210: mct_SendMrsCmd: Start
39187247.210: mct_SendMrsCmd: Done
39188247.210: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
39189247.210: mct_SendMrsCmd: Start
39190247.210: mct_SendMrsCmd: Done
39191247.210: DIMM 0 RttNom: 3
39192247.210: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39193247.210: mct_SendMrsCmd: Start
39194247.210: mct_SendMrsCmd: Done
39195247.210: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
39196247.210: mct_SendMrsCmd: Start
39197247.210: mct_SendMrsCmd: Done
39198247.210: DIMM 1 RttWr: 1
39199247.210: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39200247.210: mct_SendMrsCmd: Start
39201247.210: mct_SendMrsCmd: Done
39202247.210: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
39203247.210: mct_SendMrsCmd: Start
39204247.210: mct_SendMrsCmd: Done
39205247.210: DIMM 1 RttNom: 3
39206247.210: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39207247.210: mct_SendMrsCmd: Start
39208247.210: mct_SendMrsCmd: Done
39209247.210: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
39210247.210: mct_SendMrsCmd: Start
39211247.210: mct_SendMrsCmd: Done
39212247.210: DIMM 1 RttWr: 1
39213247.210: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39214247.210: mct_SendMrsCmd: Start
39215247.210: mct_SendMrsCmd: Done
39216247.210: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
39217247.211: mct_SendMrsCmd: Start
39218247.211: mct_SendMrsCmd: Done
39219247.211: DIMM 1 RttNom: 3
39220247.211: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39221247.211: mct_SendMrsCmd: Start
39222247.211: mct_SendMrsCmd: Done
39223247.211: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
39224247.211: mct_SendMrsCmd: Start
39225247.211: mct_SendMrsCmd: Done
39226247.211: mct_DramInit_Sw_D: Done
39227247.211: AgesaHwWlPhase1: training nibble 0
39228247.211: DIMM 0 RttNom: 3
39229247.211: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39230247.211: DIMM 0 RttWr: 1
39231247.211: DIMM 0 RttWr: 1
39232247.211: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39233247.211: DIMM 0 RttWr: 1
39234247.211: DIMM 0 RttNom: 3
39235247.211: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39236247.211: DIMM 0 RttNom: 3
39237247.211: DIMM 0 RttWr: 1
39238247.211: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39239247.211: DIMM 0 RttWr: 1
39240247.211: DIMM 1 RttNom: 3
39241247.211: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39242247.211: DIMM 0 RttNom: 3
39243247.211: DIMM 1 RttWr: 1
39244247.211: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39245247.211: DIMM 0 RttWr: 1
39246247.211: DIMM 1 RttNom: 3
39247247.211: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39248247.211: DIMM 0 RttNom: 3
39249247.211: DIMM 1 RttWr: 1
39250247.211: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39251247.211: DIMM 0 RttWr: 1
39252247.211: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
39253247.211: <09>Lane 00 scaled delay: 0053
39254247.211: <09>Lane 00 new seed: 0053
39255247.211: <09>Lane 01 scaled delay: 0051
39256247.211: <09>Lane 01 new seed: 0051
39257247.211: <09>Lane 02 scaled delay: 004e
39258247.211: <09>Lane 02 new seed: 004e
39259247.211: <09>Lane 03 scaled delay: 004b
39260247.211: <09>Lane 03 new seed: 004b
39261247.211: <09>Lane 04 scaled delay: 004a
39262247.211: <09>Lane 04 new seed: 004a
39263247.211: <09>Lane 05 scaled delay: 004d
39264247.211: <09>Lane 05 new seed: 004d
39265247.211: <09>Lane 06 scaled delay: 004f
39266247.211: <09>Lane 06 new seed: 004f
39267247.211: <09>Lane 07 scaled delay: 0052
39268247.211: <09>Lane 07 new seed: 0052
39269247.211: <09>Lane 08 scaled delay: 004a
39270247.211: <09>Lane 08 new seed: 004a
39271247.211: <09>Lane 00 nibble 0 raw readback: 0055
39272247.212: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0055
39273247.212: <09>Lane 00 nibble 0 adjusted value (post nibble): 0055
39274247.212: <09>Lane 01 nibble 0 raw readback: 004f
39275247.212: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
39276247.212: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
39277247.212: <09>Lane 02 nibble 0 raw readback: 004a
39278247.212: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004a
39279247.212: <09>Lane 02 nibble 0 adjusted value (post nibble): 004a
39280247.212: <09>Lane 03 nibble 0 raw readback: 0046
39281247.212: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0046
39282247.212: <09>Lane 03 nibble 0 adjusted value (post nibble): 0046
39283247.212: <09>Lane 04 nibble 0 raw readback: 0044
39284247.212: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
39285247.212: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
39286247.212: <09>Lane 05 nibble 0 raw readback: 004b
39287247.212: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004b
39288247.212: <09>Lane 05 nibble 0 adjusted value (post nibble): 004b
39289247.212: <09>Lane 06 nibble 0 raw readback: 004e
39290247.212: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
39291247.212: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
39292247.212: <09>Lane 07 nibble 0 raw readback: 0054
39293247.212: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0054
39294247.212: <09>Lane 07 nibble 0 adjusted value (post nibble): 0054
39295247.212: <09>Lane 08 nibble 0 raw readback: 0041
39296247.212: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
39297247.212: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
39298247.212: AgesaHwWlPhase1: training nibble 1
39299247.212: DIMM 0 RttNom: 3
39300247.212: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39301247.212: DIMM 0 RttWr: 1
39302247.212: DIMM 0 RttWr: 1
39303247.212: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39304247.212: DIMM 0 RttWr: 1
39305247.212: DIMM 0 RttNom: 3
39306247.212: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39307247.212: DIMM 0 RttNom: 3
39308247.212: DIMM 0 RttWr: 1
39309247.212: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39310247.212: DIMM 0 RttWr: 1
39311247.212: DIMM 1 RttNom: 3
39312247.212: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39313247.212: DIMM 0 RttNom: 3
39314247.212: DIMM 1 RttWr: 1
39315247.212: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39316247.212: DIMM 0 RttWr: 1
39317247.212: DIMM 1 RttNom: 3
39318247.212: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39319247.212: DIMM 0 RttNom: 3
39320247.212: DIMM 1 RttWr: 1
39321247.212: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39322247.212: DIMM 0 RttWr: 1
39323247.212: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
39324247.212: <09>Lane 00 new seed: 0053
39325247.212: <09>Lane 01 new seed: 0051
39326247.212: <09>Lane 02 new seed: 004e
39327247.212: <09>Lane 03 new seed: 004b
39328247.212: <09>Lane 04 new seed: 004a
39329247.212: <09>Lane 05 new seed: 004d
39330247.212: <09>Lane 06 new seed: 004f
39331247.212: <09>Lane 07 new seed: 0052
39332247.212: <09>Lane 08 new seed: 004a
39333247.212: <09>Lane 00 nibble 1 raw readback: 0055
39334247.212: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0055
39335247.212: <09>Lane 00 nibble 1 adjusted value (post nibble): 0054
39336247.212: <09>Lane 01 nibble 1 raw readback: 0050
39337247.212: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0050
39338247.212: <09>Lane 01 nibble 1 adjusted value (post nibble): 0050
39339247.212: <09>Lane 02 nibble 1 raw readback: 004b
39340247.213: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004b
39341247.213: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
39342247.213: <09>Lane 03 nibble 1 raw readback: 0046
39343247.213: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
39344247.213: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
39345247.213: <09>Lane 04 nibble 1 raw readback: 0043
39346247.213: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
39347247.213: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
39348247.213: <09>Lane 05 nibble 1 raw readback: 0049
39349247.213: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0049
39350247.213: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
39351247.213: <09>Lane 06 nibble 1 raw readback: 004e
39352247.213: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
39353247.213: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
39354247.213: <09>Lane 07 nibble 1 raw readback: 0052
39355247.213: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0052
39356247.213: <09>Lane 07 nibble 1 adjusted value (post nibble): 0052
39357247.213: <09>Lane 08 nibble 1 raw readback: 0041
39358247.213: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
39359247.213: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
39360247.213: <09>original critical gross delay: 0
39361247.213: <09>new critical gross delay: 0
39362247.213: DIMM 0 RttNom: 3
39363247.213: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39364247.213: DIMM 0 RttNom: 3
39365247.213: DIMM 0 RttWr: 1
39366247.213: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39367247.213: DIMM 0 RttWr: 1
39368247.213: DIMM 0 RttNom: 3
39369247.213: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39370247.213: DIMM 0 RttNom: 3
39371247.213: DIMM 0 RttWr: 1
39372247.213: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39373247.213: DIMM 0 RttWr: 1
39374247.213: DIMM 1 RttNom: 3
39375247.213: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39376247.213: DIMM 0 RttNom: 3
39377247.213: DIMM 1 RttWr: 1
39378247.213: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39379247.213: DIMM 0 RttWr: 1
39380247.213: DIMM 1 RttNom: 3
39381247.213: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39382247.213: DIMM 0 RttNom: 3
39383247.213: DIMM 1 RttWr: 1
39384247.213: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39385247.213: DIMM 0 RttWr: 1
39386247.213: AgesaHwWlPhase1: training nibble 0
39387247.213: DIMM 1 RttNom: 3
39388247.213: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39389247.213: DIMM 1 RttWr: 1
39390247.213: DIMM 1 RttWr: 1
39391247.213: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39392247.213: DIMM 1 RttWr: 1
39393247.213: DIMM 1 RttNom: 3
39394247.213: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39395247.213: DIMM 1 RttNom: 3
39396247.213: DIMM 1 RttWr: 1
39397247.213: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39398247.213: DIMM 1 RttWr: 1
39399247.213: DIMM 0 RttNom: 3
39400247.214: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39401247.213: DIMM 1 RttNom: 3
39402247.214: DIMM 0 RttWr: 1
39403247.214: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39404247.214: DIMM 1 RttWr: 1
39405247.214: DIMM 0 RttNom: 3
39406247.214: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39407247.214: DIMM 1 RttNom: 3
39408247.214: DIMM 0 RttWr: 1
39409247.214: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39410247.214: DIMM 1 RttWr: 1
39411247.214: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
39412247.214: <09>Lane 00 scaled delay: 0053
39413247.214: <09>Lane 00 new seed: 0053
39414247.214: <09>Lane 01 scaled delay: 0051
39415247.214: <09>Lane 01 new seed: 0051
39416247.214: <09>Lane 02 scaled delay: 004d
39417247.214: <09>Lane 02 new seed: 004d
39418247.214: <09>Lane 03 scaled delay: 004b
39419247.214: <09>Lane 03 new seed: 004b
39420247.214: <09>Lane 04 scaled delay: 004a
39421247.214: <09>Lane 04 new seed: 004a
39422247.214: <09>Lane 05 scaled delay: 004d
39423247.214: <09>Lane 05 new seed: 004d
39424247.214: <09>Lane 06 scaled delay: 004f
39425247.214: <09>Lane 06 new seed: 004f
39426247.214: <09>Lane 07 scaled delay: 0052
39427247.214: <09>Lane 07 new seed: 0052
39428247.214: <09>Lane 08 scaled delay: 0049
39429247.214: <09>Lane 08 new seed: 0049
39430247.214: <09>Lane 00 nibble 0 raw readback: 0052
39431247.214: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
39432247.214: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
39433247.214: <09>Lane 01 nibble 0 raw readback: 004d
39434247.214: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004d
39435247.214: <09>Lane 01 nibble 0 adjusted value (post nibble): 004d
39436247.214: <09>Lane 02 nibble 0 raw readback: 0047
39437247.214: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
39438247.214: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
39439247.214: <09>Lane 03 nibble 0 raw readback: 0044
39440247.214: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
39441247.214: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
39442247.214: <09>Lane 04 nibble 0 raw readback: 0041
39443247.214: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
39444247.214: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
39445247.214: <09>Lane 05 nibble 0 raw readback: 0049
39446247.214: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
39447247.214: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
39448247.214: <09>Lane 06 nibble 0 raw readback: 004d
39449247.214: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
39450247.214: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
39451247.214: <09>Lane 07 nibble 0 raw readback: 0051
39452247.214: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0051
39453247.214: <09>Lane 07 nibble 0 adjusted value (post nibble): 0051
39454247.214: <09>Lane 08 nibble 0 raw readback: 0040
39455247.214: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0040
39456247.214: <09>Lane 08 nibble 0 adjusted value (post nibble): 0040
39457247.214: AgesaHwWlPhase1: training nibble 1
39458247.214: DIMM 1 RttNom: 3
39459247.214: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39460247.214: DIMM 1 RttWr: 1
39461247.214: DIMM 1 RttWr: 1
39462247.214: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39463247.214: DIMM 1 RttWr: 1
39464247.214: DIMM 1 RttNom: 3
39465247.214: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39466247.214: DIMM 1 RttNom: 3
39467247.214: DIMM 1 RttWr: 1
39468247.214: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39469247.214: DIMM 1 RttWr: 1
39470247.214: DIMM 0 RttNom: 3
39471247.214: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39472247.214: DIMM 1 RttNom: 3
39473247.214: DIMM 0 RttWr: 1
39474247.214: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39475247.214: DIMM 1 RttWr: 1
39476247.215: DIMM 0 RttNom: 3
39477247.215: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39478247.215: DIMM 1 RttNom: 3
39479247.215: DIMM 0 RttWr: 1
39480247.215: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39481247.215: DIMM 1 RttWr: 1
39482247.215: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
39483247.215: <09>Lane 00 new seed: 0053
39484247.215: <09>Lane 01 new seed: 0051
39485247.215: <09>Lane 02 new seed: 004d
39486247.215: <09>Lane 03 new seed: 004b
39487247.215: <09>Lane 04 new seed: 004a
39488247.215: <09>Lane 05 new seed: 004d
39489247.215: <09>Lane 06 new seed: 004f
39490247.215: <09>Lane 07 new seed: 0052
39491247.215: <09>Lane 08 new seed: 0049
39492247.215: <09>Lane 00 nibble 1 raw readback: 0053
39493247.215: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
39494247.215: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
39495247.215: <09>Lane 01 nibble 1 raw readback: 004f
39496247.215: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004f
39497247.215: <09>Lane 01 nibble 1 adjusted value (post nibble): 0050
39498247.215: <09>Lane 02 nibble 1 raw readback: 0048
39499247.215: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0048
39500247.215: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
39501247.215: <09>Lane 03 nibble 1 raw readback: 0045
39502247.215: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
39503247.215: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
39504247.215: <09>Lane 04 nibble 1 raw readback: 0041
39505247.215: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
39506247.215: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
39507247.215: <09>Lane 05 nibble 1 raw readback: 0047
39508247.215: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
39509247.215: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
39510247.215: <09>Lane 06 nibble 1 raw readback: 004d
39511247.215: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
39512247.215: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
39513247.215: <09>Lane 07 nibble 1 raw readback: 0051
39514247.215: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
39515247.215: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
39516247.215: <09>Lane 08 nibble 1 raw readback: 003e
39517247.215: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003e
39518247.215: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
39519247.215: <09>original critical gross delay: 0
39520247.215: <09>new critical gross delay: 0
39521247.215: DIMM 1 RttNom: 3
39522247.215: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
39523247.215: DIMM 1 RttNom: 3
39524247.215: DIMM 1 RttWr: 1
39525247.215: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
39526247.215: DIMM 1 RttWr: 1
39527247.215: DIMM 1 RttNom: 3
39528247.215: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
39529247.215: DIMM 1 RttNom: 3
39530247.215: DIMM 1 RttWr: 1
39531247.215: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
39532247.215: DIMM 1 RttWr: 1
39533247.215: DIMM 0 RttNom: 3
39534247.215: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
39535247.216: DIMM 1 RttNom: 3
39536247.215: DIMM 0 RttWr: 1
39537247.215: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
39538247.216: DIMM 1 RttWr: 1
39539247.216: DIMM 0 RttNom: 3
39540247.216: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
39541247.216: DIMM 1 RttNom: 3
39542247.216: DIMM 0 RttWr: 1
39543247.216: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
39544247.216: DIMM 1 RttWr: 1
39545247.216: SetTargetFreq: Start
39546247.216: SetTargetFreq: Node 3: New frequency code: 000e
39547247.216: ChangeMemClk: Start
39548247.216: set_2t_configuration: Start
39549247.216: set_2t_configuration: Done
39550247.216: mct_BeforePlatformSpec: Start
39551247.216: mct_BeforePlatformSpec: Done
39552247.216: mct_PlatformSpec: Start
39553247.216: Programmed DCT 0 timing/termination pattern 00383a38 30222222
39554247.216: mct_PlatformSpec: Done
39555247.216: set_2t_configuration: Start
39556247.216: set_2t_configuration: Done
39557247.216: mct_BeforePlatformSpec: Start
39558247.216: mct_BeforePlatformSpec: Done
39559247.216: mct_PlatformSpec: Start
39560247.216: Programmed DCT 1 timing/termination pattern 00383a38 30222222
39561247.216: mct_PlatformSpec: Done
39562247.216: ChangeMemClk: Done
39563247.216: phyAssistedMemFnceTraining: Start
39564247.216: phyAssistedMemFnceTraining: training node 3 DCT 0
39565247.216: phyAssistedMemFnceTraining: done training node 3 DCT 0
39566247.216: phyAssistedMemFnceTraining: training node 3 DCT 1
39567247.217: phyAssistedMemFnceTraining: done training node 3 DCT 1
39568247.217: phyAssistedMemFnceTraining: Done
39569247.217: InitPhyCompensation: DCT 0: Start
39570247.217: Waiting for predriver calibration to be applied...done!
39571247.217: InitPhyCompensation: DCT 0: Done
39572247.217: phyAssistedMemFnceTraining: Start
39573247.217: phyAssistedMemFnceTraining: training node 3 DCT 0
39574247.217: phyAssistedMemFnceTraining: done training node 3 DCT 0
39575247.217: phyAssistedMemFnceTraining: training node 3 DCT 1
39576247.217: phyAssistedMemFnceTraining: done training node 3 DCT 1
39577247.217: phyAssistedMemFnceTraining: Done
39578247.217: InitPhyCompensation: DCT 1: Start
39579247.217: Waiting for predriver calibration to be applied...done!
39580247.217: InitPhyCompensation: DCT 1: Done
39581247.217: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
39582247.217: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
39583247.217: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
39584247.217: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
39585247.217: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
39586247.217: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
39587247.218: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
39588247.218: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
39589247.217: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
39590247.217: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
39591247.218: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
39592247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
39593247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
39594247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
39595247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
39596247.218: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
39597247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
39598247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
39599247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
39600247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
39601247.218: SetTargetFreq: Done
39602247.218: SPD2ndTiming: Start
39603247.218: SPD2ndTiming: Done
39604247.218: mct_BeforeDramInit_Prod_D: Start
39605247.218: mct_ProgramODT_D: Start
39606247.218: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
39607247.218: mct_ProgramODT_D: Done
39608247.218: mct_BeforeDramInit_Prod_D: Done
39609247.218: mct_DramInit_Sw_D: Start
39610247.218: DIMM 0 RttWr: 2
39611247.218: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39612247.218: mct_SendMrsCmd: Start
39613247.218: mct_SendMrsCmd: Done
39614247.218: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
39615247.218: mct_SendMrsCmd: Start
39616247.218: mct_SendMrsCmd: Done
39617247.218: DIMM 0 RttNom: 5
39618247.218: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39619247.218: mct_SendMrsCmd: Start
39620247.218: mct_SendMrsCmd: Done
39621247.218: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
39622247.218: mct_SendMrsCmd: Start
39623247.218: mct_SendMrsCmd: Done
39624247.218: DIMM 0 RttWr: 2
39625247.218: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39626247.218: mct_SendMrsCmd: Start
39627247.218: mct_SendMrsCmd: Done
39628247.218: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
39629247.218: mct_SendMrsCmd: Start
39630247.218: mct_SendMrsCmd: Done
39631247.219: DIMM 0 RttNom: 5
39632247.219: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39633247.219: mct_SendMrsCmd: Start
39634247.219: mct_SendMrsCmd: Done
39635247.219: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
39636247.219: mct_SendMrsCmd: Start
39637247.219: mct_SendMrsCmd: Done
39638247.219: DIMM 1 RttWr: 2
39639247.219: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39640247.219: mct_SendMrsCmd: Start
39641247.219: mct_SendMrsCmd: Done
39642247.219: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
39643247.219: mct_SendMrsCmd: Start
39644247.219: mct_SendMrsCmd: Done
39645247.219: DIMM 1 RttNom: 5
39646247.219: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39647247.219: mct_SendMrsCmd: Start
39648247.219: mct_SendMrsCmd: Done
39649247.219: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
39650247.219: mct_SendMrsCmd: Start
39651247.219: mct_SendMrsCmd: Done
39652247.219: DIMM 1 RttWr: 2
39653247.219: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39654247.219: mct_SendMrsCmd: Start
39655247.219: mct_SendMrsCmd: Done
39656247.219: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
39657247.219: mct_SendMrsCmd: Start
39658247.219: mct_SendMrsCmd: Done
39659247.219: DIMM 1 RttNom: 5
39660247.219: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39661247.219: mct_SendMrsCmd: Start
39662247.219: mct_SendMrsCmd: Done
39663247.219: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
39664247.219: mct_SendMrsCmd: Start
39665247.219: mct_SendMrsCmd: Done
39666247.219: mct_DramInit_Sw_D: Done
39667247.219: AgesaHwWlPhase1: training nibble 0
39668247.219: DIMM 0 RttNom: 5
39669247.219: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39670247.219: DIMM 0 RttWr: 2
39671247.219: DIMM 0 RttWr: 2
39672247.219: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39673247.219: DIMM 0 RttWr: 2
39674247.219: DIMM 0 RttNom: 5
39675247.219: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39676247.219: DIMM 0 RttNom: 5
39677247.219: DIMM 0 RttWr: 2
39678247.219: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39679247.219: DIMM 0 RttWr: 2
39680247.219: DIMM 1 RttNom: 5
39681247.219: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39682247.219: DIMM 0 RttNom: 5
39683247.219: DIMM 1 RttWr: 2
39684247.219: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39685247.220: DIMM 0 RttWr: 2
39686247.220: DIMM 1 RttNom: 5
39687247.220: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39688247.220: DIMM 0 RttNom: 5
39689247.220: DIMM 1 RttWr: 2
39690247.220: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39691247.220: DIMM 0 RttWr: 2
39692247.220: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
39693247.220: <09>Lane 00 scaled delay: 005f
39694247.220: <09>Lane 00 new seed: 005f
39695247.220: <09>Lane 01 scaled delay: 0059
39696247.220: <09>Lane 01 new seed: 0059
39697247.220: <09>Lane 02 scaled delay: 0055
39698247.220: <09>Lane 02 new seed: 0055
39699247.220: <09>Lane 03 scaled delay: 0052
39700247.220: <09>Lane 03 new seed: 0052
39701247.220: <09>Lane 04 scaled delay: 0050
39702247.220: <09>Lane 04 new seed: 0050
39703247.220: <09>Lane 05 scaled delay: 0054
39704247.220: <09>Lane 05 new seed: 0054
39705247.220: <09>Lane 06 scaled delay: 0059
39706247.220: <09>Lane 06 new seed: 0059
39707247.220: <09>Lane 07 scaled delay: 005d
39708247.220: <09>Lane 07 new seed: 005d
39709247.220: <09>Lane 08 scaled delay: 004e
39710247.220: <09>Lane 08 new seed: 004e
39711247.220: <09>Lane 00 nibble 0 raw readback: 005e
39712247.220: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
39713247.220: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
39714247.220: <09>Lane 01 nibble 0 raw readback: 0053
39715247.220: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0053
39716247.220: <09>Lane 01 nibble 0 adjusted value (post nibble): 0053
39717247.220: <09>Lane 02 nibble 0 raw readback: 004f
39718247.220: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
39719247.220: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
39720247.220: <09>Lane 03 nibble 0 raw readback: 0051
39721247.220: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
39722247.220: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
39723247.220: <09>Lane 04 nibble 0 raw readback: 004d
39724247.220: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
39725247.220: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
39726247.220: <09>Lane 05 nibble 0 raw readback: 0053
39727247.220: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
39728247.220: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
39729247.220: <09>Lane 06 nibble 0 raw readback: 0055
39730247.220: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
39731247.220: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
39732247.220: <09>Lane 07 nibble 0 raw readback: 0059
39733247.220: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
39734247.220: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
39735247.220: <09>Lane 08 nibble 0 raw readback: 0047
39736247.220: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
39737247.220: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
39738247.220: AgesaHwWlPhase1: training nibble 1
39739247.220: DIMM 0 RttNom: 5
39740247.221: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39741247.221: DIMM 0 RttWr: 2
39742247.221: DIMM 0 RttWr: 2
39743247.221: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39744247.221: DIMM 0 RttWr: 2
39745247.221: DIMM 0 RttNom: 5
39746247.221: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39747247.221: DIMM 0 RttNom: 5
39748247.221: DIMM 0 RttWr: 2
39749247.221: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39750247.221: DIMM 0 RttWr: 2
39751247.221: DIMM 1 RttNom: 5
39752247.221: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39753247.221: DIMM 0 RttNom: 5
39754247.221: DIMM 1 RttWr: 2
39755247.221: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39756247.221: DIMM 0 RttWr: 2
39757247.221: DIMM 1 RttNom: 5
39758247.221: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39759247.221: DIMM 0 RttNom: 5
39760247.221: DIMM 1 RttWr: 2
39761247.221: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39762247.221: DIMM 0 RttWr: 2
39763247.221: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
39764247.221: <09>Lane 00 new seed: 005f
39765247.221: <09>Lane 01 new seed: 0059
39766247.221: <09>Lane 02 new seed: 0055
39767247.221: <09>Lane 03 new seed: 0052
39768247.221: <09>Lane 04 new seed: 0050
39769247.221: <09>Lane 05 new seed: 0054
39770247.221: <09>Lane 06 new seed: 0059
39771247.221: <09>Lane 07 new seed: 005d
39772247.221: <09>Lane 08 new seed: 004e
39773247.221: <09>Lane 00 nibble 1 raw readback: 0060
39774247.221: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
39775247.221: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
39776247.221: <09>Lane 01 nibble 1 raw readback: 0059
39777247.221: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
39778247.221: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
39779247.221: <09>Lane 02 nibble 1 raw readback: 0053
39780247.221: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0053
39781247.221: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
39782247.221: <09>Lane 03 nibble 1 raw readback: 004f
39783247.221: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
39784247.221: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
39785247.221: <09>Lane 04 nibble 1 raw readback: 004c
39786247.221: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
39787247.221: <09>Lane 04 nibble 1 adjusted value (post nibble): 004e
39788247.221: <09>Lane 05 nibble 1 raw readback: 0050
39789247.221: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
39790247.221: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
39791247.221: <09>Lane 06 nibble 1 raw readback: 0056
39792247.221: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
39793247.221: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
39794247.221: <09>Lane 07 nibble 1 raw readback: 005d
39795247.221: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
39796247.221: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
39797247.221: <09>Lane 08 nibble 1 raw readback: 0049
39798247.221: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0049
39799247.221: <09>Lane 08 nibble 1 adjusted value (post nibble): 004b
39800247.221: <09>original critical gross delay: 0
39801247.221: <09>new critical gross delay: 0
39802247.222: DIMM 0 RttNom: 5
39803247.222: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39804247.222: DIMM 0 RttNom: 5
39805247.222: DIMM 0 RttWr: 2
39806247.222: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39807247.222: DIMM 0 RttWr: 2
39808247.222: DIMM 0 RttNom: 5
39809247.222: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39810247.222: DIMM 0 RttNom: 5
39811247.222: DIMM 0 RttWr: 2
39812247.222: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39813247.222: DIMM 0 RttWr: 2
39814247.222: DIMM 1 RttNom: 5
39815247.222: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39816247.222: DIMM 0 RttNom: 5
39817247.222: DIMM 1 RttWr: 2
39818247.222: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39819247.222: DIMM 0 RttWr: 2
39820247.222: DIMM 1 RttNom: 5
39821247.222: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39822247.222: DIMM 0 RttNom: 5
39823247.222: DIMM 1 RttWr: 2
39824247.222: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39825247.222: DIMM 0 RttWr: 2
39826247.222: AgesaHwWlPhase1: training nibble 0
39827247.222: DIMM 1 RttNom: 5
39828247.222: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39829247.222: DIMM 1 RttWr: 2
39830247.222: DIMM 1 RttWr: 2
39831247.222: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39832247.222: DIMM 1 RttWr: 2
39833247.222: DIMM 1 RttNom: 5
39834247.222: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39835247.222: DIMM 1 RttNom: 5
39836247.222: DIMM 1 RttWr: 2
39837247.222: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39838247.222: DIMM 1 RttWr: 2
39839247.222: DIMM 0 RttNom: 5
39840247.222: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39841247.222: DIMM 1 RttNom: 5
39842247.222: DIMM 0 RttWr: 2
39843247.222: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39844247.222: DIMM 1 RttWr: 2
39845247.222: DIMM 0 RttNom: 5
39846247.222: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39847247.222: DIMM 1 RttNom: 5
39848247.222: DIMM 0 RttWr: 2
39849247.222: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39850247.222: DIMM 1 RttWr: 2
39851247.222: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
39852247.222: <09>Lane 00 scaled delay: 005c
39853247.222: <09>Lane 00 new seed: 005c
39854247.222: <09>Lane 01 scaled delay: 0057
39855247.222: <09>Lane 01 new seed: 0057
39856247.222: <09>Lane 02 scaled delay: 0053
39857247.222: <09>Lane 02 new seed: 0053
39858247.222: <09>Lane 03 scaled delay: 0050
39859247.222: <09>Lane 03 new seed: 0050
39860247.222: <09>Lane 04 scaled delay: 004e
39861247.222: <09>Lane 04 new seed: 004e
39862247.222: <09>Lane 05 scaled delay: 0052
39863247.222: <09>Lane 05 new seed: 0052
39864247.222: <09>Lane 06 scaled delay: 0053
39865247.222: <09>Lane 06 new seed: 0053
39866247.223: <09>Lane 07 scaled delay: 0058
39867247.223: <09>Lane 07 new seed: 0058
39868247.223: <09>Lane 08 scaled delay: 0049
39869247.223: <09>Lane 08 new seed: 0049
39870247.223: <09>Lane 00 nibble 0 raw readback: 005c
39871247.223: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
39872247.223: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
39873247.223: <09>Lane 01 nibble 0 raw readback: 0054
39874247.223: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0054
39875247.223: <09>Lane 01 nibble 0 adjusted value (post nibble): 0054
39876247.223: <09>Lane 02 nibble 0 raw readback: 004e
39877247.223: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004e
39878247.223: <09>Lane 02 nibble 0 adjusted value (post nibble): 004e
39879247.223: <09>Lane 03 nibble 0 raw readback: 004e
39880247.223: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
39881247.223: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
39882247.223: <09>Lane 04 nibble 0 raw readback: 0049
39883247.223: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
39884247.223: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
39885247.223: <09>Lane 05 nibble 0 raw readback: 004f
39886247.223: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
39887247.223: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
39888247.223: <09>Lane 06 nibble 0 raw readback: 004f
39889247.223: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004f
39890247.223: <09>Lane 06 nibble 0 adjusted value (post nibble): 004f
39891247.223: <09>Lane 07 nibble 0 raw readback: 0058
39892247.223: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
39893247.223: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
39894247.223: <09>Lane 08 nibble 0 raw readback: 0045
39895247.223: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
39896247.223: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
39897247.223: AgesaHwWlPhase1: training nibble 1
39898247.223: DIMM 1 RttNom: 5
39899247.223: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39900247.223: DIMM 1 RttWr: 2
39901247.223: DIMM 1 RttWr: 2
39902247.223: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39903247.223: DIMM 1 RttWr: 2
39904247.223: DIMM 1 RttNom: 5
39905247.223: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39906247.223: DIMM 1 RttNom: 5
39907247.223: DIMM 1 RttWr: 2
39908247.223: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39909247.223: DIMM 1 RttWr: 2
39910247.223: DIMM 0 RttNom: 5
39911247.223: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39912247.223: DIMM 1 RttNom: 5
39913247.223: DIMM 0 RttWr: 2
39914247.223: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39915247.223: DIMM 1 RttWr: 2
39916247.223: DIMM 0 RttNom: 5
39917247.223: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39918247.223: DIMM 1 RttNom: 5
39919247.223: DIMM 0 RttWr: 2
39920247.223: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39921247.223: DIMM 1 RttWr: 2
39922247.223: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
39923247.223: <09>Lane 00 new seed: 005c
39924247.223: <09>Lane 01 new seed: 0057
39925247.223: <09>Lane 02 new seed: 0053
39926247.223: <09>Lane 03 new seed: 0050
39927247.223: <09>Lane 04 new seed: 004e
39928247.223: <09>Lane 05 new seed: 0052
39929247.223: <09>Lane 06 new seed: 0053
39930247.223: <09>Lane 07 new seed: 0058
39931247.223: <09>Lane 08 new seed: 0049
39932247.223: <09>Lane 00 nibble 1 raw readback: 005d
39933247.223: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
39934247.223: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
39935247.223: <09>Lane 01 nibble 1 raw readback: 0055
39936247.223: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
39937247.223: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
39938247.223: <09>Lane 02 nibble 1 raw readback: 0050
39939247.224: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0050
39940247.224: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
39941247.224: <09>Lane 03 nibble 1 raw readback: 004d
39942247.224: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
39943247.224: <09>Lane 03 nibble 1 adjusted value (post nibble): 004e
39944247.224: <09>Lane 04 nibble 1 raw readback: 0048
39945247.224: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
39946247.224: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
39947247.224: <09>Lane 05 nibble 1 raw readback: 004d
39948247.224: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004d
39949247.224: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
39950247.224: <09>Lane 06 nibble 1 raw readback: 004f
39951247.224: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
39952247.224: <09>Lane 06 nibble 1 adjusted value (post nibble): 0051
39953247.224: <09>Lane 07 nibble 1 raw readback: 0057
39954247.224: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
39955247.224: <09>Lane 07 nibble 1 adjusted value (post nibble): 0057
39956247.224: <09>Lane 08 nibble 1 raw readback: 0043
39957247.224: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0043
39958247.224: <09>Lane 08 nibble 1 adjusted value (post nibble): 0046
39959247.224: <09>original critical gross delay: 0
39960247.224: <09>new critical gross delay: 0
39961247.224: DIMM 1 RttNom: 5
39962247.224: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
39963247.224: DIMM 1 RttNom: 5
39964247.224: DIMM 1 RttWr: 2
39965247.224: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
39966247.224: DIMM 1 RttWr: 2
39967247.224: DIMM 1 RttNom: 5
39968247.224: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
39969247.224: DIMM 1 RttNom: 5
39970247.224: DIMM 1 RttWr: 2
39971247.224: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
39972247.224: DIMM 1 RttWr: 2
39973247.224: DIMM 0 RttNom: 5
39974247.224: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
39975247.224: DIMM 1 RttNom: 5
39976247.224: DIMM 0 RttWr: 2
39977247.224: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
39978247.224: DIMM 1 RttWr: 2
39979247.224: DIMM 0 RttNom: 5
39980247.224: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
39981247.224: DIMM 1 RttNom: 5
39982247.224: DIMM 0 RttWr: 2
39983247.224: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
39984247.224: DIMM 1 RttWr: 2
39985247.224: SPD2ndTiming: Start
39986247.225: SPD2ndTiming: Done
39987247.225: mct_BeforeDramInit_Prod_D: Start
39988247.225: mct_ProgramODT_D: Start
39989247.225: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
39990247.225: mct_ProgramODT_D: Done
39991247.225: mct_BeforeDramInit_Prod_D: Done
39992247.225: mct_DramInit_Sw_D: Start
39993247.225: DIMM 0 RttWr: 2
39994247.225: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
39995247.225: mct_SendMrsCmd: Start
39996247.225: mct_SendMrsCmd: Done
39997247.225: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
39998247.225: mct_SendMrsCmd: Start
39999247.225: mct_SendMrsCmd: Done
40000247.225: DIMM 0 RttNom: 5
40001247.225: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40002247.225: mct_SendMrsCmd: Start
40003247.225: mct_SendMrsCmd: Done
40004247.225: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
40005247.225: mct_SendMrsCmd: Start
40006247.225: mct_SendMrsCmd: Done
40007247.225: DIMM 0 RttWr: 2
40008247.225: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40009247.225: mct_SendMrsCmd: Start
40010247.225: mct_SendMrsCmd: Done
40011247.225: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
40012247.225: mct_SendMrsCmd: Start
40013247.225: mct_SendMrsCmd: Done
40014247.225: DIMM 0 RttNom: 5
40015247.225: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40016247.225: mct_SendMrsCmd: Start
40017247.225: mct_SendMrsCmd: Done
40018247.225: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
40019247.225: mct_SendMrsCmd: Start
40020247.225: mct_SendMrsCmd: Done
40021247.225: DIMM 1 RttWr: 2
40022247.225: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40023247.225: mct_SendMrsCmd: Start
40024247.225: mct_SendMrsCmd: Done
40025247.225: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
40026247.225: mct_SendMrsCmd: Start
40027247.225: mct_SendMrsCmd: Done
40028247.225: DIMM 1 RttNom: 5
40029247.225: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40030247.225: mct_SendMrsCmd: Start
40031247.225: mct_SendMrsCmd: Done
40032247.225: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
40033247.225: mct_SendMrsCmd: Start
40034247.225: mct_SendMrsCmd: Done
40035247.225: DIMM 1 RttWr: 2
40036247.225: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40037247.225: mct_SendMrsCmd: Start
40038247.225: mct_SendMrsCmd: Done
40039247.225: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
40040247.226: mct_SendMrsCmd: Start
40041247.226: mct_SendMrsCmd: Done
40042247.226: DIMM 1 RttNom: 5
40043247.226: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40044247.226: mct_SendMrsCmd: Start
40045247.226: mct_SendMrsCmd: Done
40046247.226: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
40047247.226: mct_SendMrsCmd: Start
40048247.226: mct_SendMrsCmd: Done
40049247.226: mct_DramInit_Sw_D: Done
40050247.226: AgesaHwWlPhase1: training nibble 0
40051247.226: DIMM 0 RttNom: 5
40052247.226: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40053247.226: DIMM 0 RttWr: 2
40054247.226: DIMM 0 RttWr: 2
40055247.226: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
40056247.226: DIMM 0 RttWr: 2
40057247.226: DIMM 0 RttNom: 5
40058247.226: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40059247.226: DIMM 0 RttNom: 5
40060247.226: DIMM 0 RttWr: 2
40061247.226: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40062247.226: DIMM 0 RttWr: 2
40063247.226: DIMM 1 RttNom: 5
40064247.226: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40065247.226: DIMM 0 RttNom: 5
40066247.226: DIMM 1 RttWr: 2
40067247.226: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40068247.226: DIMM 0 RttWr: 2
40069247.226: DIMM 1 RttNom: 5
40070247.226: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40071247.226: DIMM 0 RttNom: 5
40072247.226: DIMM 1 RttWr: 2
40073247.226: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40074247.226: DIMM 0 RttWr: 2
40075247.226: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
40076247.226: <09>Lane 00 scaled delay: 0061
40077247.226: <09>Lane 00 new seed: 0061
40078247.226: <09>Lane 01 scaled delay: 005c
40079247.226: <09>Lane 01 new seed: 005c
40080247.226: <09>Lane 02 scaled delay: 0057
40081247.226: <09>Lane 02 new seed: 0057
40082247.226: <09>Lane 03 scaled delay: 0052
40083247.226: <09>Lane 03 new seed: 0052
40084247.226: <09>Lane 04 scaled delay: 004f
40085247.226: <09>Lane 04 new seed: 004f
40086247.226: <09>Lane 05 scaled delay: 0055
40087247.226: <09>Lane 05 new seed: 0055
40088247.226: <09>Lane 06 scaled delay: 0059
40089247.226: <09>Lane 06 new seed: 0059
40090247.226: <09>Lane 07 scaled delay: 005e
40091247.226: <09>Lane 07 new seed: 005e
40092247.226: <09>Lane 08 scaled delay: 004e
40093247.226: <09>Lane 08 new seed: 004e
40094247.226: <09>Lane 00 nibble 0 raw readback: 0020
40095247.227: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
40096247.227: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
40097247.227: <09>Lane 01 nibble 0 raw readback: 0058
40098247.227: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
40099247.227: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
40100247.227: <09>Lane 02 nibble 0 raw readback: 0054
40101247.227: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
40102247.227: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
40103247.227: <09>Lane 03 nibble 0 raw readback: 004f
40104247.227: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
40105247.227: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
40106247.227: <09>Lane 04 nibble 0 raw readback: 004c
40107247.227: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
40108247.227: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
40109247.227: <09>Lane 05 nibble 0 raw readback: 0054
40110247.227: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
40111247.227: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
40112247.227: <09>Lane 06 nibble 0 raw readback: 0059
40113247.227: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0059
40114247.227: <09>Lane 06 nibble 0 adjusted value (post nibble): 0059
40115247.227: <09>Lane 07 nibble 0 raw readback: 005f
40116247.227: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005f
40117247.227: <09>Lane 07 nibble 0 adjusted value (post nibble): 005f
40118247.227: <09>Lane 08 nibble 0 raw readback: 0049
40119247.227: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
40120247.227: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
40121247.227: AgesaHwWlPhase1: training nibble 1
40122247.227: DIMM 0 RttNom: 5
40123247.227: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40124247.227: DIMM 0 RttWr: 2
40125247.227: DIMM 0 RttWr: 2
40126247.227: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
40127247.227: DIMM 0 RttWr: 2
40128247.227: DIMM 0 RttNom: 5
40129247.227: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40130247.227: DIMM 0 RttNom: 5
40131247.227: DIMM 0 RttWr: 2
40132247.227: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40133247.227: DIMM 0 RttWr: 2
40134247.227: DIMM 1 RttNom: 5
40135247.227: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40136247.227: DIMM 0 RttNom: 5
40137247.227: DIMM 1 RttWr: 2
40138247.227: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40139247.227: DIMM 0 RttWr: 2
40140247.227: DIMM 1 RttNom: 5
40141247.227: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40142247.227: DIMM 0 RttNom: 5
40143247.227: DIMM 1 RttWr: 2
40144247.227: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40145247.227: DIMM 0 RttWr: 2
40146247.227: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
40147247.227: <09>Lane 00 new seed: 0061
40148247.227: <09>Lane 01 new seed: 005c
40149247.227: <09>Lane 02 new seed: 0057
40150247.227: <09>Lane 03 new seed: 0052
40151247.227: <09>Lane 04 new seed: 004f
40152247.227: <09>Lane 05 new seed: 0055
40153247.227: <09>Lane 06 new seed: 0059
40154247.227: <09>Lane 07 new seed: 005e
40155247.227: <09>Lane 08 new seed: 004e
40156247.227: <09>Lane 00 nibble 1 raw readback: 0020
40157247.227: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
40158247.227: <09>Lane 00 nibble 1 adjusted value (post nibble): 0060
40159247.227: <09>Lane 01 nibble 1 raw readback: 005c
40160247.227: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005c
40161247.228: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
40162247.228: <09>Lane 02 nibble 1 raw readback: 0056
40163247.228: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
40164247.228: <09>Lane 02 nibble 1 adjusted value (post nibble): 0056
40165247.228: <09>Lane 03 nibble 1 raw readback: 004f
40166247.228: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
40167247.228: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
40168247.228: <09>Lane 04 nibble 1 raw readback: 004b
40169247.228: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
40170247.228: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
40171247.228: <09>Lane 05 nibble 1 raw readback: 0052
40172247.228: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
40173247.228: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
40174247.228: <09>Lane 06 nibble 1 raw readback: 0059
40175247.228: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0059
40176247.228: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
40177247.228: <09>Lane 07 nibble 1 raw readback: 005f
40178247.228: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005f
40179247.228: <09>Lane 07 nibble 1 adjusted value (post nibble): 005e
40180247.228: <09>Lane 08 nibble 1 raw readback: 004a
40181247.228: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
40182247.228: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
40183247.228: <09>original critical gross delay: 0
40184247.228: <09>new critical gross delay: 0
40185247.228: DIMM 0 RttNom: 5
40186247.228: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40187247.228: DIMM 0 RttNom: 5
40188247.228: DIMM 0 RttWr: 2
40189247.228: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
40190247.228: DIMM 0 RttWr: 2
40191247.228: DIMM 0 RttNom: 5
40192247.228: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40193247.228: DIMM 0 RttNom: 5
40194247.228: DIMM 0 RttWr: 2
40195247.228: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40196247.228: DIMM 0 RttWr: 2
40197247.228: DIMM 1 RttNom: 5
40198247.228: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40199247.228: DIMM 0 RttNom: 5
40200247.228: DIMM 1 RttWr: 2
40201247.228: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40202247.228: DIMM 0 RttWr: 2
40203247.228: DIMM 1 RttNom: 5
40204247.228: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40205247.228: DIMM 0 RttNom: 5
40206247.228: DIMM 1 RttWr: 2
40207247.228: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40208247.228: DIMM 0 RttWr: 2
40209247.228: AgesaHwWlPhase1: training nibble 0
40210247.228: DIMM 1 RttNom: 5
40211247.228: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40212247.228: DIMM 1 RttWr: 2
40213247.228: DIMM 1 RttWr: 2
40214247.228: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40215247.228: DIMM 1 RttWr: 2
40216247.228: DIMM 1 RttNom: 5
40217247.228: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40218247.228: DIMM 1 RttNom: 5
40219247.228: DIMM 1 RttWr: 2
40220247.228: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40221247.228: DIMM 1 RttWr: 2
40222247.228: DIMM 0 RttNom: 5
40223247.229: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40224247.229: DIMM 1 RttNom: 5
40225247.229: DIMM 0 RttWr: 2
40226247.229: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
40227247.229: DIMM 1 RttWr: 2
40228247.229: DIMM 0 RttNom: 5
40229247.229: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40230247.229: DIMM 1 RttNom: 5
40231247.229: DIMM 0 RttWr: 2
40232247.229: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40233247.229: DIMM 1 RttWr: 2
40234247.229: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
40235247.229: <09>Lane 00 scaled delay: 005f
40236247.229: <09>Lane 00 new seed: 005f
40237247.229: <09>Lane 01 scaled delay: 005c
40238247.229: <09>Lane 01 new seed: 005c
40239247.229: <09>Lane 02 scaled delay: 0054
40240247.229: <09>Lane 02 new seed: 0054
40241247.229: <09>Lane 03 scaled delay: 0052
40242247.229: <09>Lane 03 new seed: 0052
40243247.229: <09>Lane 04 scaled delay: 004e
40244247.229: <09>Lane 04 new seed: 004e
40245247.229: <09>Lane 05 scaled delay: 0054
40246247.229: <09>Lane 05 new seed: 0054
40247247.229: <09>Lane 06 scaled delay: 0059
40248247.229: <09>Lane 06 new seed: 0059
40249247.229: <09>Lane 07 scaled delay: 005d
40250247.229: <09>Lane 07 new seed: 005d
40251247.229: <09>Lane 08 scaled delay: 004b
40252247.229: <09>Lane 08 new seed: 004b
40253247.229: <09>Lane 00 nibble 0 raw readback: 005e
40254247.229: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
40255247.229: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
40256247.229: <09>Lane 01 nibble 0 raw readback: 0058
40257247.229: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
40258247.229: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
40259247.229: <09>Lane 02 nibble 0 raw readback: 0051
40260247.229: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0051
40261247.229: <09>Lane 02 nibble 0 adjusted value (post nibble): 0051
40262247.229: <09>Lane 03 nibble 0 raw readback: 004d
40263247.229: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
40264247.229: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
40265247.229: <09>Lane 04 nibble 0 raw readback: 0049
40266247.229: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
40267247.229: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
40268247.229: <09>Lane 05 nibble 0 raw readback: 0052
40269247.229: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0052
40270247.229: <09>Lane 05 nibble 0 adjusted value (post nibble): 0052
40271247.229: <09>Lane 06 nibble 0 raw readback: 0058
40272247.229: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
40273247.229: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
40274247.229: <09>Lane 07 nibble 0 raw readback: 005d
40275247.229: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005d
40276247.229: <09>Lane 07 nibble 0 adjusted value (post nibble): 005d
40277247.229: <09>Lane 08 nibble 0 raw readback: 0049
40278247.229: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
40279247.229: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
40280247.229: AgesaHwWlPhase1: training nibble 1
40281247.229: DIMM 1 RttNom: 5
40282247.229: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40283247.229: DIMM 1 RttWr: 2
40284247.229: DIMM 1 RttWr: 2
40285247.229: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40286247.229: DIMM 1 RttWr: 2
40287247.229: DIMM 1 RttNom: 5
40288247.229: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40289247.229: DIMM 1 RttNom: 5
40290247.229: DIMM 1 RttWr: 2
40291247.229: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40292247.229: DIMM 1 RttWr: 2
40293247.229: DIMM 0 RttNom: 5
40294247.229: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40295247.230: DIMM 1 RttNom: 5
40296247.230: DIMM 0 RttWr: 2
40297247.230: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
40298247.230: DIMM 1 RttWr: 2
40299247.230: DIMM 0 RttNom: 5
40300247.230: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40301247.230: DIMM 1 RttNom: 5
40302247.230: DIMM 0 RttWr: 2
40303247.230: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40304247.230: DIMM 1 RttWr: 2
40305247.230: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
40306247.230: <09>Lane 00 new seed: 005f
40307247.230: <09>Lane 01 new seed: 005c
40308247.230: <09>Lane 02 new seed: 0054
40309247.230: <09>Lane 03 new seed: 0052
40310247.230: <09>Lane 04 new seed: 004e
40311247.230: <09>Lane 05 new seed: 0054
40312247.230: <09>Lane 06 new seed: 0059
40313247.230: <09>Lane 07 new seed: 005d
40314247.230: <09>Lane 08 new seed: 004b
40315247.230: <09>Lane 00 nibble 1 raw readback: 005f
40316247.230: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
40317247.230: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
40318247.230: <09>Lane 01 nibble 1 raw readback: 005a
40319247.230: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005a
40320247.230: <09>Lane 01 nibble 1 adjusted value (post nibble): 005b
40321247.230: <09>Lane 02 nibble 1 raw readback: 0051
40322247.230: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
40323247.230: <09>Lane 02 nibble 1 adjusted value (post nibble): 0052
40324247.230: <09>Lane 03 nibble 1 raw readback: 004f
40325247.230: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
40326247.230: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
40327247.230: <09>Lane 04 nibble 1 raw readback: 004a
40328247.230: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
40329247.230: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
40330247.230: <09>Lane 05 nibble 1 raw readback: 0050
40331247.230: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
40332247.230: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
40333247.230: <09>Lane 06 nibble 1 raw readback: 0058
40334247.230: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
40335247.230: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
40336247.230: <09>Lane 07 nibble 1 raw readback: 005d
40337247.230: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
40338247.230: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
40339247.230: <09>Lane 08 nibble 1 raw readback: 0047
40340247.230: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0047
40341247.230: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
40342247.230: <09>original critical gross delay: 0
40343247.230: <09>new critical gross delay: 0
40344247.230: DIMM 1 RttNom: 5
40345247.230: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
40346247.230: DIMM 1 RttNom: 5
40347247.230: DIMM 1 RttWr: 2
40348247.230: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
40349247.230: DIMM 1 RttWr: 2
40350247.230: DIMM 1 RttNom: 5
40351247.230: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
40352247.230: DIMM 1 RttNom: 5
40353247.230: DIMM 1 RttWr: 2
40354247.230: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
40355247.230: DIMM 1 RttWr: 2
40356247.230: DIMM 0 RttNom: 5
40357247.230: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
40358247.230: DIMM 1 RttNom: 5
40359247.231: DIMM 0 RttWr: 2
40360247.231: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
40361247.231: DIMM 1 RttWr: 2
40362247.231: DIMM 0 RttNom: 5
40363247.231: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
40364247.231: DIMM 1 RttNom: 5
40365247.231: DIMM 0 RttWr: 2
40366247.231: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
40367247.231: DIMM 1 RttWr: 2
40368247.231: SetTargetFreq: Start
40369247.231: SetTargetFreq: Node 3: New frequency code: 0012
40370247.231: ChangeMemClk: Start
40371247.231: set_2t_configuration: Start
40372247.231: set_2t_configuration: Done
40373247.231: mct_BeforePlatformSpec: Start
40374247.231: mct_BeforePlatformSpec: Done
40375247.231: mct_PlatformSpec: Start
40376247.231: Programmed DCT 0 timing/termination pattern 00353935 30222222
40377247.231: mct_PlatformSpec: Done
40378247.231: set_2t_configuration: Start
40379247.231: set_2t_configuration: Done
40380247.231: mct_BeforePlatformSpec: Start
40381247.231: mct_BeforePlatformSpec: Done
40382247.231: mct_PlatformSpec: Start
40383247.231: Programmed DCT 1 timing/termination pattern 00353935 30222222
40384247.231: mct_PlatformSpec: Done
40385247.231: ChangeMemClk: Done
40386247.231: phyAssistedMemFnceTraining: Start
40387247.231: phyAssistedMemFnceTraining: training node 3 DCT 0
40388247.231: phyAssistedMemFnceTraining: done training node 3 DCT 0
40389247.231: phyAssistedMemFnceTraining: training node 3 DCT 1
40390247.232: phyAssistedMemFnceTraining: done training node 3 DCT 1
40391247.232: phyAssistedMemFnceTraining: Done
40392247.232: InitPhyCompensation: DCT 0: Start
40393247.232: Waiting for predriver calibration to be applied...done!
40394247.232: InitPhyCompensation: DCT 0: Done
40395247.232: phyAssistedMemFnceTraining: Start
40396247.232: phyAssistedMemFnceTraining: training node 3 DCT 0
40397247.232: phyAssistedMemFnceTraining: done training node 3 DCT 0
40398247.232: phyAssistedMemFnceTraining: training node 3 DCT 1
40399247.232: phyAssistedMemFnceTraining: done training node 3 DCT 1
40400247.232: phyAssistedMemFnceTraining: Done
40401247.232: InitPhyCompensation: DCT 1: Start
40402247.232: Waiting for predriver calibration to be applied...done!
40403247.232: InitPhyCompensation: DCT 1: Done
40404247.232: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
40405247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
40406247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
40407247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
40408247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
40409247.232: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
40410247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
40411247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
40412247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
40413247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
40414247.233: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
40415247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
40416247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
40417247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
40418247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
40419247.233: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
40420247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
40421247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
40422247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
40423247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
40424247.233: SetTargetFreq: Done
40425247.233: SPD2ndTiming: Start
40426247.233: SPD2ndTiming: Done
40427247.233: mct_BeforeDramInit_Prod_D: Start
40428247.233: mct_ProgramODT_D: Start
40429247.233: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
40430247.233: mct_ProgramODT_D: Done
40431247.233: mct_BeforeDramInit_Prod_D: Done
40432247.233: mct_DramInit_Sw_D: Start
40433247.233: DIMM 0 RttWr: 1
40434247.233: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40435247.233: mct_SendMrsCmd: Start
40436247.233: mct_SendMrsCmd: Done
40437247.233: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
40438247.233: mct_SendMrsCmd: Start
40439247.233: mct_SendMrsCmd: Done
40440247.233: DIMM 0 RttNom: 4
40441247.233: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40442247.233: mct_SendMrsCmd: Start
40443247.233: mct_SendMrsCmd: Done
40444247.233: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
40445247.233: mct_SendMrsCmd: Start
40446247.233: mct_SendMrsCmd: Done
40447247.233: DIMM 0 RttWr: 1
40448247.233: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40449247.233: mct_SendMrsCmd: Start
40450247.233: mct_SendMrsCmd: Done
40451247.233: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
40452247.233: mct_SendMrsCmd: Start
40453247.233: mct_SendMrsCmd: Done
40454247.234: DIMM 0 RttNom: 4
40455247.234: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40456247.234: mct_SendMrsCmd: Start
40457247.234: mct_SendMrsCmd: Done
40458247.234: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
40459247.234: mct_SendMrsCmd: Start
40460247.234: mct_SendMrsCmd: Done
40461247.234: DIMM 1 RttWr: 1
40462247.234: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40463247.234: mct_SendMrsCmd: Start
40464247.234: mct_SendMrsCmd: Done
40465247.234: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
40466247.234: mct_SendMrsCmd: Start
40467247.234: mct_SendMrsCmd: Done
40468247.234: DIMM 1 RttNom: 4
40469247.234: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40470247.234: mct_SendMrsCmd: Start
40471247.234: mct_SendMrsCmd: Done
40472247.234: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
40473247.234: mct_SendMrsCmd: Start
40474247.234: mct_SendMrsCmd: Done
40475247.234: DIMM 1 RttWr: 1
40476247.234: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40477247.234: mct_SendMrsCmd: Start
40478247.234: mct_SendMrsCmd: Done
40479247.234: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
40480247.234: mct_SendMrsCmd: Start
40481247.234: mct_SendMrsCmd: Done
40482247.234: DIMM 1 RttNom: 4
40483247.234: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40484247.234: mct_SendMrsCmd: Start
40485247.234: mct_SendMrsCmd: Done
40486247.234: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
40487247.234: mct_SendMrsCmd: Start
40488247.234: mct_SendMrsCmd: Done
40489247.234: mct_DramInit_Sw_D: Done
40490247.234: AgesaHwWlPhase1: training nibble 0
40491247.234: DIMM 0 RttNom: 4
40492247.234: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40493247.234: DIMM 0 RttWr: 1
40494247.234: DIMM 0 RttWr: 1
40495247.234: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40496247.234: DIMM 0 RttWr: 1
40497247.234: DIMM 0 RttNom: 4
40498247.234: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40499247.234: DIMM 0 RttNom: 4
40500247.234: DIMM 0 RttWr: 1
40501247.234: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40502247.234: DIMM 0 RttWr: 1
40503247.234: DIMM 1 RttNom: 4
40504247.234: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40505247.234: DIMM 0 RttNom: 4
40506247.235: DIMM 1 RttWr: 1
40507247.235: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40508247.235: DIMM 0 RttWr: 1
40509247.235: DIMM 1 RttNom: 4
40510247.235: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40511247.235: DIMM 0 RttNom: 4
40512247.235: DIMM 1 RttWr: 1
40513247.235: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40514247.235: DIMM 0 RttWr: 1
40515247.235: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
40516247.235: <09>Lane 00 scaled delay: 006b
40517247.235: <09>Lane 00 new seed: 006b
40518247.235: <09>Lane 01 scaled delay: 0064
40519247.235: <09>Lane 01 new seed: 0064
40520247.235: <09>Lane 02 scaled delay: 005e
40521247.235: <09>Lane 02 new seed: 005e
40522247.235: <09>Lane 03 scaled delay: 0059
40523247.235: <09>Lane 03 new seed: 0059
40524247.235: <09>Lane 04 scaled delay: 0057
40525247.235: <09>Lane 04 new seed: 0057
40526247.235: <09>Lane 05 scaled delay: 005b
40527247.235: <09>Lane 05 new seed: 005b
40528247.235: <09>Lane 06 scaled delay: 0061
40529247.235: <09>Lane 06 new seed: 0061
40530247.235: <09>Lane 07 scaled delay: 0069
40531247.235: <09>Lane 07 new seed: 0069
40532247.235: <09>Lane 08 scaled delay: 0053
40533247.235: <09>Lane 08 new seed: 0053
40534247.235: <09>Lane 00 nibble 0 raw readback: 0030
40535247.235: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
40536247.235: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
40537247.235: <09>Lane 01 nibble 0 raw readback: 0023
40538247.235: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0063
40539247.235: <09>Lane 01 nibble 0 adjusted value (post nibble): 0063
40540247.235: <09>Lane 02 nibble 0 raw readback: 005d
40541247.235: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
40542247.235: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
40543247.235: <09>Lane 03 nibble 0 raw readback: 005e
40544247.235: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005e
40545247.235: <09>Lane 03 nibble 0 adjusted value (post nibble): 005e
40546247.235: <09>Lane 04 nibble 0 raw readback: 005a
40547247.235: <09>Lane 04 nibble 0 adjusted value (pre nibble): 005a
40548247.235: <09>Lane 04 nibble 0 adjusted value (post nibble): 005a
40549247.235: <09>Lane 05 nibble 0 raw readback: 0061
40550247.235: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0061
40551247.235: <09>Lane 05 nibble 0 adjusted value (post nibble): 0061
40552247.235: <09>Lane 06 nibble 0 raw readback: 0025
40553247.235: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
40554247.235: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
40555247.235: <09>Lane 07 nibble 0 raw readback: 002a
40556247.235: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006a
40557247.235: <09>Lane 07 nibble 0 adjusted value (post nibble): 006a
40558247.235: <09>Lane 08 nibble 0 raw readback: 0053
40559247.235: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
40560247.235: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
40561247.235: AgesaHwWlPhase1: training nibble 1
40562247.236: DIMM 0 RttNom: 4
40563247.236: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40564247.236: DIMM 0 RttWr: 1
40565247.236: DIMM 0 RttWr: 1
40566247.236: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40567247.236: DIMM 0 RttWr: 1
40568247.236: DIMM 0 RttNom: 4
40569247.236: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40570247.236: DIMM 0 RttNom: 4
40571247.236: DIMM 0 RttWr: 1
40572247.236: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40573247.236: DIMM 0 RttWr: 1
40574247.236: DIMM 1 RttNom: 4
40575247.236: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40576247.236: DIMM 0 RttNom: 4
40577247.236: DIMM 1 RttWr: 1
40578247.236: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40579247.236: DIMM 0 RttWr: 1
40580247.236: DIMM 1 RttNom: 4
40581247.236: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40582247.236: DIMM 0 RttNom: 4
40583247.236: DIMM 1 RttWr: 1
40584247.236: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40585247.236: DIMM 0 RttWr: 1
40586247.236: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
40587247.236: <09>Lane 00 new seed: 006b
40588247.236: <09>Lane 01 new seed: 0064
40589247.236: <09>Lane 02 new seed: 005e
40590247.236: <09>Lane 03 new seed: 0059
40591247.236: <09>Lane 04 new seed: 0057
40592247.236: <09>Lane 05 new seed: 005b
40593247.236: <09>Lane 06 new seed: 0061
40594247.236: <09>Lane 07 new seed: 0069
40595247.236: <09>Lane 08 new seed: 0053
40596247.236: <09>Lane 00 nibble 1 raw readback: 0033
40597247.236: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0073
40598247.236: <09>Lane 00 nibble 1 adjusted value (post nibble): 006f
40599247.236: <09>Lane 01 nibble 1 raw readback: 002a
40600247.236: <09>Lane 01 nibble 1 adjusted value (pre nibble): 006a
40601247.236: <09>Lane 01 nibble 1 adjusted value (post nibble): 0067
40602247.236: <09>Lane 02 nibble 1 raw readback: 0061
40603247.236: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
40604247.236: <09>Lane 02 nibble 1 adjusted value (post nibble): 005f
40605247.236: <09>Lane 03 nibble 1 raw readback: 005c
40606247.236: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
40607247.236: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
40608247.236: <09>Lane 04 nibble 1 raw readback: 0059
40609247.236: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0059
40610247.236: <09>Lane 04 nibble 1 adjusted value (post nibble): 0058
40611247.236: <09>Lane 05 nibble 1 raw readback: 005f
40612247.236: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
40613247.236: <09>Lane 05 nibble 1 adjusted value (post nibble): 005d
40614247.236: <09>Lane 06 nibble 1 raw readback: 0026
40615247.236: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
40616247.236: <09>Lane 06 nibble 1 adjusted value (post nibble): 0063
40617247.236: <09>Lane 07 nibble 1 raw readback: 002d
40618247.236: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006d
40619247.236: <09>Lane 07 nibble 1 adjusted value (post nibble): 006b
40620247.236: <09>Lane 08 nibble 1 raw readback: 0055
40621247.236: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
40622247.236: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
40623247.236: <09>original critical gross delay: 0
40624247.236: <09>new critical gross delay: 0
40625247.237: DIMM 0 RttNom: 4
40626247.237: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40627247.237: DIMM 0 RttNom: 4
40628247.237: DIMM 0 RttWr: 1
40629247.237: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40630247.237: DIMM 0 RttWr: 1
40631247.237: DIMM 0 RttNom: 4
40632247.237: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40633247.237: DIMM 0 RttNom: 4
40634247.237: DIMM 0 RttWr: 1
40635247.237: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40636247.237: DIMM 0 RttWr: 1
40637247.237: DIMM 1 RttNom: 4
40638247.237: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40639247.237: DIMM 0 RttNom: 4
40640247.237: DIMM 1 RttWr: 1
40641247.237: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40642247.237: DIMM 0 RttWr: 1
40643247.237: DIMM 1 RttNom: 4
40644247.237: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40645247.237: DIMM 0 RttNom: 4
40646247.237: DIMM 1 RttWr: 1
40647247.237: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40648247.237: DIMM 0 RttWr: 1
40649247.237: AgesaHwWlPhase1: training nibble 0
40650247.237: DIMM 1 RttNom: 4
40651247.237: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40652247.237: DIMM 1 RttWr: 1
40653247.237: DIMM 1 RttWr: 1
40654247.237: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40655247.237: DIMM 1 RttWr: 1
40656247.237: DIMM 1 RttNom: 4
40657247.237: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40658247.237: DIMM 1 RttNom: 4
40659247.237: DIMM 1 RttWr: 1
40660247.237: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40661247.237: DIMM 1 RttWr: 1
40662247.237: DIMM 0 RttNom: 4
40663247.237: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40664247.237: DIMM 1 RttNom: 4
40665247.237: DIMM 0 RttWr: 1
40666247.237: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40667247.237: DIMM 1 RttWr: 1
40668247.237: DIMM 0 RttNom: 4
40669247.237: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40670247.237: DIMM 1 RttNom: 4
40671247.237: DIMM 0 RttWr: 1
40672247.237: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40673247.237: DIMM 1 RttWr: 1
40674247.237: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
40675247.237: <09>Lane 00 scaled delay: 0067
40676247.237: <09>Lane 00 new seed: 0067
40677247.237: <09>Lane 01 scaled delay: 0060
40678247.237: <09>Lane 01 new seed: 0060
40679247.237: <09>Lane 02 scaled delay: 005a
40680247.237: <09>Lane 02 new seed: 005a
40681247.237: <09>Lane 03 scaled delay: 0057
40682247.237: <09>Lane 03 new seed: 0057
40683247.237: <09>Lane 04 scaled delay: 0053
40684247.237: <09>Lane 04 new seed: 0053
40685247.237: <09>Lane 05 scaled delay: 0058
40686247.237: <09>Lane 05 new seed: 0058
40687247.238: <09>Lane 06 scaled delay: 005a
40688247.238: <09>Lane 06 new seed: 005a
40689247.238: <09>Lane 07 scaled delay: 0061
40690247.238: <09>Lane 07 new seed: 0061
40691247.238: <09>Lane 08 scaled delay: 004d
40692247.238: <09>Lane 08 new seed: 004d
40693247.238: <09>Lane 00 nibble 0 raw readback: 002e
40694247.238: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
40695247.238: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
40696247.238: <09>Lane 01 nibble 0 raw readback: 0024
40697247.238: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
40698247.238: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
40699247.238: <09>Lane 02 nibble 0 raw readback: 005d
40700247.238: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
40701247.238: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
40702247.238: <09>Lane 03 nibble 0 raw readback: 005b
40703247.238: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
40704247.238: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
40705247.238: <09>Lane 04 nibble 0 raw readback: 0056
40706247.238: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
40707247.238: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
40708247.238: <09>Lane 05 nibble 0 raw readback: 005d
40709247.238: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
40710247.238: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
40711247.238: <09>Lane 06 nibble 0 raw readback: 005f
40712247.238: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005f
40713247.238: <09>Lane 06 nibble 0 adjusted value (post nibble): 005f
40714247.238: <09>Lane 07 nibble 0 raw readback: 0028
40715247.238: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0068
40716247.238: <09>Lane 07 nibble 0 adjusted value (post nibble): 0068
40717247.238: <09>Lane 08 nibble 0 raw readback: 0051
40718247.238: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0051
40719247.238: <09>Lane 08 nibble 0 adjusted value (post nibble): 0051
40720247.238: AgesaHwWlPhase1: training nibble 1
40721247.238: DIMM 1 RttNom: 4
40722247.238: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40723247.238: DIMM 1 RttWr: 1
40724247.238: DIMM 1 RttWr: 1
40725247.238: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40726247.238: DIMM 1 RttWr: 1
40727247.238: DIMM 1 RttNom: 4
40728247.238: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40729247.238: DIMM 1 RttNom: 4
40730247.238: DIMM 1 RttWr: 1
40731247.238: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40732247.238: DIMM 1 RttWr: 1
40733247.238: DIMM 0 RttNom: 4
40734247.238: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40735247.238: DIMM 1 RttNom: 4
40736247.238: DIMM 0 RttWr: 1
40737247.238: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40738247.238: DIMM 1 RttWr: 1
40739247.238: DIMM 0 RttNom: 4
40740247.238: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40741247.238: DIMM 1 RttNom: 4
40742247.238: DIMM 0 RttWr: 1
40743247.238: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40744247.238: DIMM 1 RttWr: 1
40745247.238: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
40746247.238: <09>Lane 00 new seed: 0067
40747247.238: <09>Lane 01 new seed: 0060
40748247.238: <09>Lane 02 new seed: 005a
40749247.238: <09>Lane 03 new seed: 0057
40750247.238: <09>Lane 04 new seed: 0053
40751247.238: <09>Lane 05 new seed: 0058
40752247.238: <09>Lane 06 new seed: 005a
40753247.238: <09>Lane 07 new seed: 0061
40754247.238: <09>Lane 08 new seed: 004d
40755247.238: <09>Lane 00 nibble 1 raw readback: 002e
40756247.238: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
40757247.239: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
40758247.239: <09>Lane 01 nibble 1 raw readback: 0026
40759247.239: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
40760247.239: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
40761247.239: <09>Lane 02 nibble 1 raw readback: 005e
40762247.239: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
40763247.239: <09>Lane 02 nibble 1 adjusted value (post nibble): 005c
40764247.239: <09>Lane 03 nibble 1 raw readback: 005b
40765247.239: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
40766247.239: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
40767247.239: <09>Lane 04 nibble 1 raw readback: 0055
40768247.239: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0055
40769247.239: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
40770247.239: <09>Lane 05 nibble 1 raw readback: 005c
40771247.239: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
40772247.239: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
40773247.239: <09>Lane 06 nibble 1 raw readback: 005e
40774247.239: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005e
40775247.239: <09>Lane 06 nibble 1 adjusted value (post nibble): 005c
40776247.239: <09>Lane 07 nibble 1 raw readback: 0028
40777247.239: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
40778247.239: <09>Lane 07 nibble 1 adjusted value (post nibble): 0064
40779247.239: <09>Lane 08 nibble 1 raw readback: 0050
40780247.239: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0050
40781247.239: <09>Lane 08 nibble 1 adjusted value (post nibble): 004e
40782247.239: <09>original critical gross delay: 0
40783247.239: <09>new critical gross delay: 0
40784247.239: DIMM 1 RttNom: 4
40785247.239: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
40786247.239: DIMM 1 RttNom: 4
40787247.239: DIMM 1 RttWr: 1
40788247.239: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
40789247.239: DIMM 1 RttWr: 1
40790247.239: DIMM 1 RttNom: 4
40791247.239: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
40792247.239: DIMM 1 RttNom: 4
40793247.239: DIMM 1 RttWr: 1
40794247.239: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
40795247.239: DIMM 1 RttWr: 1
40796247.239: DIMM 0 RttNom: 4
40797247.239: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
40798247.239: DIMM 1 RttNom: 4
40799247.239: DIMM 0 RttWr: 1
40800247.239: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
40801247.239: DIMM 1 RttWr: 1
40802247.239: DIMM 0 RttNom: 4
40803247.239: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
40804247.239: DIMM 1 RttNom: 4
40805247.239: DIMM 0 RttWr: 1
40806247.239: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
40807247.239: DIMM 1 RttWr: 1
40808247.239: SPD2ndTiming: Start
40809247.240: SPD2ndTiming: Done
40810247.240: mct_BeforeDramInit_Prod_D: Start
40811247.240: mct_ProgramODT_D: Start
40812247.240: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
40813247.240: mct_ProgramODT_D: Done
40814247.240: mct_BeforeDramInit_Prod_D: Done
40815247.240: mct_DramInit_Sw_D: Start
40816247.240: DIMM 0 RttWr: 1
40817247.240: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
40818247.240: mct_SendMrsCmd: Start
40819247.240: mct_SendMrsCmd: Done
40820247.240: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
40821247.240: mct_SendMrsCmd: Start
40822247.240: mct_SendMrsCmd: Done
40823247.240: DIMM 0 RttNom: 4
40824247.240: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
40825247.240: mct_SendMrsCmd: Start
40826247.240: mct_SendMrsCmd: Done
40827247.240: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
40828247.240: mct_SendMrsCmd: Start
40829247.240: mct_SendMrsCmd: Done
40830247.240: DIMM 0 RttWr: 1
40831247.240: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
40832247.240: mct_SendMrsCmd: Start
40833247.240: mct_SendMrsCmd: Done
40834247.240: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
40835247.240: mct_SendMrsCmd: Start
40836247.240: mct_SendMrsCmd: Done
40837247.240: DIMM 0 RttNom: 4
40838247.240: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
40839247.240: mct_SendMrsCmd: Start
40840247.240: mct_SendMrsCmd: Done
40841247.240: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
40842247.240: mct_SendMrsCmd: Start
40843247.240: mct_SendMrsCmd: Done
40844247.240: DIMM 1 RttWr: 1
40845247.240: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
40846247.240: mct_SendMrsCmd: Start
40847247.240: mct_SendMrsCmd: Done
40848247.240: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
40849247.240: mct_SendMrsCmd: Start
40850247.240: mct_SendMrsCmd: Done
40851247.240: DIMM 1 RttNom: 4
40852247.240: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
40853247.240: mct_SendMrsCmd: Start
40854247.240: mct_SendMrsCmd: Done
40855247.240: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
40856247.240: mct_SendMrsCmd: Start
40857247.240: mct_SendMrsCmd: Done
40858247.240: DIMM 1 RttWr: 1
40859247.240: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
40860247.240: mct_SendMrsCmd: Start
40861247.240: mct_SendMrsCmd: Done
40862247.240: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
40863247.240: mct_SendMrsCmd: Start
40864247.241: mct_SendMrsCmd: Done
40865247.241: DIMM 1 RttNom: 4
40866247.241: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
40867247.241: mct_SendMrsCmd: Start
40868247.241: mct_SendMrsCmd: Done
40869247.241: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
40870247.241: mct_SendMrsCmd: Start
40871247.241: mct_SendMrsCmd: Done
40872247.241: mct_DramInit_Sw_D: Done
40873247.241: AgesaHwWlPhase1: training nibble 0
40874247.241: DIMM 0 RttNom: 4
40875247.241: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
40876247.241: DIMM 0 RttWr: 1
40877247.241: DIMM 0 RttWr: 1
40878247.241: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
40879247.241: DIMM 0 RttWr: 1
40880247.241: DIMM 0 RttNom: 4
40881247.241: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
40882247.241: DIMM 0 RttNom: 4
40883247.241: DIMM 0 RttWr: 1
40884247.241: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
40885247.241: DIMM 0 RttWr: 1
40886247.241: DIMM 1 RttNom: 4
40887247.241: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
40888247.241: DIMM 0 RttNom: 4
40889247.241: DIMM 1 RttWr: 1
40890247.241: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
40891247.241: DIMM 0 RttWr: 1
40892247.241: DIMM 1 RttNom: 4
40893247.241: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
40894247.241: DIMM 0 RttNom: 4
40895247.241: DIMM 1 RttWr: 1
40896247.241: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
40897247.241: DIMM 0 RttWr: 1
40898247.241: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
40899247.241: <09>Lane 00 scaled delay: 006c
40900247.241: <09>Lane 00 new seed: 006c
40901247.241: <09>Lane 01 scaled delay: 0067
40902247.241: <09>Lane 01 new seed: 0067
40903247.241: <09>Lane 02 scaled delay: 0060
40904247.241: <09>Lane 02 new seed: 0060
40905247.241: <09>Lane 03 scaled delay: 0059
40906247.241: <09>Lane 03 new seed: 0059
40907247.241: <09>Lane 04 scaled delay: 0055
40908247.241: <09>Lane 04 new seed: 0055
40909247.241: <09>Lane 05 scaled delay: 005d
40910247.241: <09>Lane 05 new seed: 005d
40911247.241: <09>Lane 06 scaled delay: 0064
40912247.241: <09>Lane 06 new seed: 0064
40913247.241: <09>Lane 07 scaled delay: 006a
40914247.241: <09>Lane 07 new seed: 006a
40915247.241: <09>Lane 08 scaled delay: 0054
40916247.241: <09>Lane 08 new seed: 0054
40917247.242: <09>Lane 00 nibble 0 raw readback: 002f
40918247.242: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
40919247.242: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
40920247.242: <09>Lane 01 nibble 0 raw readback: 0027
40921247.242: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
40922247.242: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
40923247.242: <09>Lane 02 nibble 0 raw readback: 001f
40924247.242: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
40925247.242: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
40926247.242: <09>Lane 03 nibble 0 raw readback: 005a
40927247.242: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005a
40928247.242: <09>Lane 03 nibble 0 adjusted value (post nibble): 005a
40929247.242: <09>Lane 04 nibble 0 raw readback: 0058
40930247.242: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0058
40931247.242: <09>Lane 04 nibble 0 adjusted value (post nibble): 0058
40932247.242: <09>Lane 05 nibble 0 raw readback: 0062
40933247.242: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0062
40934247.242: <09>Lane 05 nibble 0 adjusted value (post nibble): 0062
40935247.242: <09>Lane 06 nibble 0 raw readback: 0026
40936247.242: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0066
40937247.242: <09>Lane 06 nibble 0 adjusted value (post nibble): 0066
40938247.242: <09>Lane 07 nibble 0 raw readback: 002e
40939247.242: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006e
40940247.242: <09>Lane 07 nibble 0 adjusted value (post nibble): 006e
40941247.242: <09>Lane 08 nibble 0 raw readback: 0054
40942247.242: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0054
40943247.242: <09>Lane 08 nibble 0 adjusted value (post nibble): 0054
40944247.242: AgesaHwWlPhase1: training nibble 1
40945247.242: DIMM 0 RttNom: 4
40946247.242: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
40947247.242: DIMM 0 RttWr: 1
40948247.242: DIMM 0 RttWr: 1
40949247.242: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
40950247.242: DIMM 0 RttWr: 1
40951247.242: DIMM 0 RttNom: 4
40952247.242: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
40953247.242: DIMM 0 RttNom: 4
40954247.242: DIMM 0 RttWr: 1
40955247.242: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
40956247.242: DIMM 0 RttWr: 1
40957247.242: DIMM 1 RttNom: 4
40958247.242: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
40959247.242: DIMM 0 RttNom: 4
40960247.242: DIMM 1 RttWr: 1
40961247.242: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
40962247.242: DIMM 0 RttWr: 1
40963247.242: DIMM 1 RttNom: 4
40964247.242: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
40965247.242: DIMM 0 RttNom: 4
40966247.242: DIMM 1 RttWr: 1
40967247.242: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
40968247.242: DIMM 0 RttWr: 1
40969247.242: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
40970247.242: <09>Lane 00 new seed: 006c
40971247.242: <09>Lane 01 new seed: 0067
40972247.242: <09>Lane 02 new seed: 0060
40973247.242: <09>Lane 03 new seed: 0059
40974247.242: <09>Lane 04 new seed: 0055
40975247.242: <09>Lane 05 new seed: 005d
40976247.242: <09>Lane 06 new seed: 0064
40977247.242: <09>Lane 07 new seed: 006a
40978247.242: <09>Lane 08 new seed: 0054
40979247.242: <09>Lane 00 nibble 1 raw readback: 0030
40980247.243: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
40981247.243: <09>Lane 00 nibble 1 adjusted value (post nibble): 006e
40982247.243: <09>Lane 01 nibble 1 raw readback: 002a
40983247.243: <09>Lane 01 nibble 1 adjusted value (pre nibble): 006a
40984247.243: <09>Lane 01 nibble 1 adjusted value (post nibble): 0068
40985247.243: <09>Lane 02 nibble 1 raw readback: 0021
40986247.243: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
40987247.243: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
40988247.243: <09>Lane 03 nibble 1 raw readback: 005b
40989247.243: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
40990247.243: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
40991247.243: <09>Lane 04 nibble 1 raw readback: 0056
40992247.243: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
40993247.243: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
40994247.243: <09>Lane 05 nibble 1 raw readback: 005f
40995247.243: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
40996247.243: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
40997247.243: <09>Lane 06 nibble 1 raw readback: 0026
40998247.243: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
40999247.243: <09>Lane 06 nibble 1 adjusted value (post nibble): 0065
41000247.243: <09>Lane 07 nibble 1 raw readback: 002d
41001247.243: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006d
41002247.243: <09>Lane 07 nibble 1 adjusted value (post nibble): 006b
41003247.243: <09>Lane 08 nibble 1 raw readback: 0055
41004247.243: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
41005247.243: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
41006247.243: <09>original critical gross delay: 0
41007247.243: <09>new critical gross delay: 0
41008247.243: DIMM 0 RttNom: 4
41009247.243: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
41010247.243: DIMM 0 RttNom: 4
41011247.243: DIMM 0 RttWr: 1
41012247.243: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
41013247.243: DIMM 0 RttWr: 1
41014247.243: DIMM 0 RttNom: 4
41015247.243: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
41016247.243: DIMM 0 RttNom: 4
41017247.243: DIMM 0 RttWr: 1
41018247.243: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
41019247.243: DIMM 0 RttWr: 1
41020247.243: DIMM 1 RttNom: 4
41021247.243: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
41022247.243: DIMM 0 RttNom: 4
41023247.243: DIMM 1 RttWr: 1
41024247.243: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
41025247.243: DIMM 0 RttWr: 1
41026247.243: DIMM 1 RttNom: 4
41027247.243: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
41028247.243: DIMM 0 RttNom: 4
41029247.243: DIMM 1 RttWr: 1
41030247.243: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
41031247.243: DIMM 0 RttWr: 1
41032247.243: AgesaHwWlPhase1: training nibble 0
41033247.243: DIMM 1 RttNom: 4
41034247.243: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
41035247.243: DIMM 1 RttWr: 1
41036247.243: DIMM 1 RttWr: 1
41037247.243: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
41038247.243: DIMM 1 RttWr: 1
41039247.243: DIMM 1 RttNom: 4
41040247.243: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
41041247.243: DIMM 1 RttNom: 4
41042247.243: DIMM 1 RttWr: 1
41043247.243: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
41044247.244: DIMM 1 RttWr: 1
41045247.244: DIMM 0 RttNom: 4
41046247.244: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
41047247.244: DIMM 1 RttNom: 4
41048247.244: DIMM 0 RttWr: 1
41049247.244: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
41050247.244: DIMM 1 RttWr: 1
41051247.244: DIMM 0 RttNom: 4
41052247.244: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
41053247.244: DIMM 1 RttNom: 4
41054247.244: DIMM 0 RttWr: 1
41055247.244: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
41056247.244: DIMM 1 RttWr: 1
41057247.244: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
41058247.244: <09>Lane 00 scaled delay: 006b
41059247.244: <09>Lane 00 new seed: 006b
41060247.244: <09>Lane 01 scaled delay: 0066
41061247.244: <09>Lane 01 new seed: 0066
41062247.244: <09>Lane 02 scaled delay: 005b
41063247.244: <09>Lane 02 new seed: 005b
41064247.244: <09>Lane 03 scaled delay: 0059
41065247.244: <09>Lane 03 new seed: 0059
41066247.244: <09>Lane 04 scaled delay: 0054
41067247.244: <09>Lane 04 new seed: 0054
41068247.244: <09>Lane 05 scaled delay: 005b
41069247.244: <09>Lane 05 new seed: 005b
41070247.244: <09>Lane 06 scaled delay: 0063
41071247.244: <09>Lane 06 new seed: 0063
41072247.244: <09>Lane 07 scaled delay: 0069
41073247.244: <09>Lane 07 new seed: 0069
41074247.244: <09>Lane 08 scaled delay: 0051
41075247.244: <09>Lane 08 new seed: 0051
41076247.244: <09>Lane 00 nibble 0 raw readback: 002d
41077247.244: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006d
41078247.244: <09>Lane 00 nibble 0 adjusted value (post nibble): 006d
41079247.244: <09>Lane 01 nibble 0 raw readback: 0025
41080247.244: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
41081247.244: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
41082247.244: <09>Lane 02 nibble 0 raw readback: 005b
41083247.244: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005b
41084247.244: <09>Lane 02 nibble 0 adjusted value (post nibble): 005b
41085247.244: <09>Lane 03 nibble 0 raw readback: 0057
41086247.244: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0057
41087247.244: <09>Lane 03 nibble 0 adjusted value (post nibble): 0057
41088247.244: <09>Lane 04 nibble 0 raw readback: 0053
41089247.244: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0053
41090247.244: <09>Lane 04 nibble 0 adjusted value (post nibble): 0053
41091247.244: <09>Lane 05 nibble 0 raw readback: 005e
41092247.244: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
41093247.244: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
41094247.244: <09>Lane 06 nibble 0 raw readback: 0025
41095247.244: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
41096247.244: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
41097247.244: <09>Lane 07 nibble 0 raw readback: 002b
41098247.244: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
41099247.244: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
41100247.244: <09>Lane 08 nibble 0 raw readback: 0053
41101247.244: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
41102247.244: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
41103247.244: AgesaHwWlPhase1: training nibble 1
41104247.244: DIMM 1 RttNom: 4
41105247.244: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
41106247.244: DIMM 1 RttWr: 1
41107247.244: DIMM 1 RttWr: 1
41108247.244: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
41109247.244: DIMM 1 RttWr: 1
41110247.244: DIMM 1 RttNom: 4
41111247.244: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
41112247.244: DIMM 1 RttNom: 4
41113247.244: DIMM 1 RttWr: 1
41114247.245: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
41115247.244: DIMM 1 RttWr: 1
41116247.245: DIMM 0 RttNom: 4
41117247.245: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
41118247.245: DIMM 1 RttNom: 4
41119247.245: DIMM 0 RttWr: 1
41120247.245: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
41121247.245: DIMM 1 RttWr: 1
41122247.245: DIMM 0 RttNom: 4
41123247.245: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
41124247.245: DIMM 1 RttNom: 4
41125247.245: DIMM 0 RttWr: 1
41126247.245: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
41127247.245: DIMM 1 RttWr: 1
41128247.245: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
41129247.245: <09>Lane 00 new seed: 006b
41130247.245: <09>Lane 01 new seed: 0066
41131247.245: <09>Lane 02 new seed: 005b
41132247.245: <09>Lane 03 new seed: 0059
41133247.245: <09>Lane 04 new seed: 0054
41134247.245: <09>Lane 05 new seed: 005b
41135247.245: <09>Lane 06 new seed: 0063
41136247.245: <09>Lane 07 new seed: 0069
41137247.245: <09>Lane 08 new seed: 0051
41138247.245: <09>Lane 00 nibble 1 raw readback: 002e
41139247.245: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
41140247.245: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
41141247.245: <09>Lane 01 nibble 1 raw readback: 0028
41142247.245: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0068
41143247.245: <09>Lane 01 nibble 1 adjusted value (post nibble): 0067
41144247.245: <09>Lane 02 nibble 1 raw readback: 005c
41145247.245: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005c
41146247.245: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
41147247.245: <09>Lane 03 nibble 1 raw readback: 0059
41148247.245: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
41149247.245: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
41150247.245: <09>Lane 04 nibble 1 raw readback: 0054
41151247.245: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
41152247.245: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
41153247.245: <09>Lane 05 nibble 1 raw readback: 005d
41154247.245: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005d
41155247.245: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
41156247.245: <09>Lane 06 nibble 1 raw readback: 0025
41157247.245: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0065
41158247.245: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
41159247.245: <09>Lane 07 nibble 1 raw readback: 002b
41160247.245: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
41161247.245: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
41162247.245: <09>Lane 08 nibble 1 raw readback: 0050
41163247.245: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0050
41164247.245: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
41165247.245: <09>original critical gross delay: 0
41166247.245: <09>new critical gross delay: 0
41167247.245: DIMM 1 RttNom: 4
41168247.245: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
41169247.245: DIMM 1 RttNom: 4
41170247.245: DIMM 1 RttWr: 1
41171247.245: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
41172247.245: DIMM 1 RttWr: 1
41173247.245: DIMM 1 RttNom: 4
41174247.245: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
41175247.245: DIMM 1 RttNom: 4
41176247.245: DIMM 1 RttWr: 1
41177247.245: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
41178247.245: DIMM 1 RttWr: 1
41179247.245: DIMM 0 RttNom: 4
41180247.245: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
41181247.245: DIMM 1 RttNom: 4
41182247.246: DIMM 0 RttWr: 1
41183247.246: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
41184247.246: DIMM 1 RttWr: 1
41185247.246: DIMM 0 RttNom: 4
41186247.246: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
41187247.246: DIMM 1 RttNom: 4
41188247.246: DIMM 0 RttWr: 1
41189247.246: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
41190247.246: DIMM 1 RttWr: 1
41191247.247: fam15_receiver_enable_training_seed: using seed: 0054
41192247.247: fam15_receiver_enable_training_seed: using seed: 0054
41193247.247: fam15_receiver_enable_training_seed: using seed: 0054
41194247.247: fam15_receiver_enable_training_seed: using seed: 0054
41195247.247: fam15_receiver_enable_training_seed: using seed: 0054
41196247.247: fam15_receiver_enable_training_seed: using seed: 0054
41197247.247: fam15_receiver_enable_training_seed: using seed: 0054
41198247.247: fam15_receiver_enable_training_seed: using seed: 0054
41199247.247: fam15_receiver_enable_training_seed: using seed: 004d
41200247.247: fam15_receiver_enable_training_seed: using seed: 004d
41201247.247: fam15_receiver_enable_training_seed: using seed: 004d
41202247.247: fam15_receiver_enable_training_seed: using seed: 004d
41203247.247: fam15_receiver_enable_training_seed: using seed: 004d
41204247.247: fam15_receiver_enable_training_seed: using seed: 004d
41205247.248: fam15_receiver_enable_training_seed: using seed: 004d
41206247.248: fam15_receiver_enable_training_seed: using seed: 004d
41207247.248: TrainRcvrEn: Status 2205
41208247.248: TrainRcvrEn: ErrStatus 0
41209247.248: TrainRcvrEn: ErrCode 0
41210247.248: TrainRcvrEn: Done
41211247.248:
41212247.248: fam15_receiver_enable_training_seed: using seed: 0045
41213247.248: fam15_receiver_enable_training_seed: using seed: 0045
41214247.248: fam15_receiver_enable_training_seed: using seed: 0045
41215247.248: fam15_receiver_enable_training_seed: using seed: 0045
41216247.248: fam15_receiver_enable_training_seed: using seed: 0045
41217247.248: fam15_receiver_enable_training_seed: using seed: 0045
41218247.249: fam15_receiver_enable_training_seed: using seed: 0045
41219247.249: fam15_receiver_enable_training_seed: using seed: 0045
41220247.249: fam15_receiver_enable_training_seed: using seed: 0040
41221247.249: fam15_receiver_enable_training_seed: using seed: 0040
41222247.249: fam15_receiver_enable_training_seed: using seed: 0040
41223247.249: fam15_receiver_enable_training_seed: using seed: 0040
41224247.249: fam15_receiver_enable_training_seed: using seed: 0040
41225247.249: fam15_receiver_enable_training_seed: using seed: 0040
41226247.249: fam15_receiver_enable_training_seed: using seed: 0040
41227247.249: fam15_receiver_enable_training_seed: using seed: 0040
41228247.249: TrainRcvrEn: Status 2005
41229247.250: TrainRcvrEn: ErrStatus 0
41230247.250: TrainRcvrEn: ErrCode 0
41231247.250: TrainRcvrEn: Done
41232247.250:
41233247.250: fam15_receiver_enable_training_seed: using seed: 0054
41234247.250: fam15_receiver_enable_training_seed: using seed: 0054
41235247.250: fam15_receiver_enable_training_seed: using seed: 0054
41236247.250: fam15_receiver_enable_training_seed: using seed: 0054
41237247.250: fam15_receiver_enable_training_seed: using seed: 0054
41238247.250: fam15_receiver_enable_training_seed: using seed: 0054
41239247.250: fam15_receiver_enable_training_seed: using seed: 0054
41240247.250: fam15_receiver_enable_training_seed: using seed: 0054
41241247.250: fam15_receiver_enable_training_seed: using seed: 004d
41242247.250: fam15_receiver_enable_training_seed: using seed: 004d
41243247.251: fam15_receiver_enable_training_seed: using seed: 004d
41244247.251: fam15_receiver_enable_training_seed: using seed: 004d
41245247.251: fam15_receiver_enable_training_seed: using seed: 004d
41246247.251: fam15_receiver_enable_training_seed: using seed: 004d
41247247.251: fam15_receiver_enable_training_seed: using seed: 004d
41248247.251: fam15_receiver_enable_training_seed: using seed: 004d
41249247.251: TrainRcvrEn: Status 2005
41250247.251: TrainRcvrEn: ErrStatus 0
41251247.251: TrainRcvrEn: ErrCode 0
41252247.251: TrainRcvrEn: Done
41253247.251:
41254247.251: fam15_receiver_enable_training_seed: using seed: 0045
41255247.251: fam15_receiver_enable_training_seed: using seed: 0045
41256247.252: fam15_receiver_enable_training_seed: using seed: 0045
41257247.252: fam15_receiver_enable_training_seed: using seed: 0045
41258247.252: fam15_receiver_enable_training_seed: using seed: 0045
41259247.252: fam15_receiver_enable_training_seed: using seed: 0045
41260247.252: fam15_receiver_enable_training_seed: using seed: 0045
41261247.252: fam15_receiver_enable_training_seed: using seed: 0045
41262247.252: fam15_receiver_enable_training_seed: using seed: 0040
41263247.252: fam15_receiver_enable_training_seed: using seed: 0040
41264247.252: fam15_receiver_enable_training_seed: using seed: 0040
41265247.252: fam15_receiver_enable_training_seed: using seed: 0040
41266247.252: fam15_receiver_enable_training_seed: using seed: 0040
41267247.253: fam15_receiver_enable_training_seed: using seed: 0040
41268247.253: fam15_receiver_enable_training_seed: using seed: 0040
41269247.253: fam15_receiver_enable_training_seed: using seed: 0040
41270247.253: TrainRcvrEn: Status 2005
41271247.253: TrainRcvrEn: ErrStatus 0
41272247.253: TrainRcvrEn: ErrCode 0
41273247.253: TrainRcvrEn: Done
41274247.253:
41275257.287: TrainDQSReceiverEnCyc: Status 2205
41276257.286: TrainDQSReceiverEnCyc: TrainErrors 4000
41277257.287: TrainDQSReceiverEnCyc: ErrStatus 4000
41278257.287: TrainDQSReceiverEnCyc: ErrCode 0
41279257.287: TrainDQSReceiverEnCyc: Done
41280257.287:
41281268.920: TrainDQSReceiverEnCyc: Status 2005
41282268.920: TrainDQSReceiverEnCyc: TrainErrors 4000
41283268.920: TrainDQSReceiverEnCyc: ErrStatus 4000
41284268.920: TrainDQSReceiverEnCyc: ErrCode 0
41285268.920: TrainDQSReceiverEnCyc: Done
41286268.920:
41287282.320: TrainDQSReceiverEnCyc: Status 2005
41288282.320: TrainDQSReceiverEnCyc: TrainErrors 4000
41289282.320: TrainDQSReceiverEnCyc: ErrStatus 4000
41290282.320: TrainDQSReceiverEnCyc: ErrCode 0
41291282.320: TrainDQSReceiverEnCyc: Done
41292282.320:
41293293.934: TrainDQSReceiverEnCyc: Status 2005
41294293.934: TrainDQSReceiverEnCyc: TrainErrors 4000
41295293.934: TrainDQSReceiverEnCyc: ErrStatus 4000
41296293.934: TrainDQSReceiverEnCyc: ErrCode 0
41297293.934: TrainDQSReceiverEnCyc: Done
41298293.934:
41299293.935: TrainMaxRdLatency: Status 2205
41300293.935: TrainMaxRdLatency: ErrStatus 4000
41301293.935: TrainMaxRdLatency: ErrCode 0
41302293.935: TrainMaxRdLatency: Done
41303293.935:
41304293.936: TrainMaxRdLatency: Status 2005
41305293.936: TrainMaxRdLatency: ErrStatus 4000
41306293.936: TrainMaxRdLatency: ErrCode 0
41307293.936: TrainMaxRdLatency: Done
41308293.936:
41309293.937: TrainMaxRdLatency: Status 2005
41310293.937: TrainMaxRdLatency: ErrStatus 4000
41311293.937: TrainMaxRdLatency: ErrCode 0
41312293.937: TrainMaxRdLatency: Done
41313293.937:
41314293.937: TrainMaxRdLatency: Status 2005
41315293.937: TrainMaxRdLatency: ErrStatus 4000
41316293.937: TrainMaxRdLatency: ErrCode 0
41317293.937: TrainMaxRdLatency: Done
41318293.937:
41319293.938: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41320293.938: CBFS: Locating 'cmos_layout.bin'
41321293.939: CBFS: Found @ offset 2b0c0 size e88
41322293.940: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41323293.940: CBFS: Locating 'cmos_layout.bin'
41324293.940: CBFS: Found @ offset 2b0c0 size e88
41325293.940: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41326293.940: CBFS: Locating 'cmos_layout.bin'
41327293.940: CBFS: Found @ offset 2b0c0 size e88
41328293.941: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41329293.941: CBFS: Locating 'cmos_layout.bin'
41330293.941: CBFS: Found @ offset 2b0c0 size e88
41331293.941: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41332293.941: CBFS: Locating 'cmos_layout.bin'
41333293.941: CBFS: Found @ offset 2b0c0 size e88
41334293.941: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41335293.941: CBFS: Locating 'cmos_layout.bin'
41336293.941: CBFS: Found @ offset 2b0c0 size e88
41337293.942: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41338293.942: CBFS: Locating 'cmos_layout.bin'
41339293.942: CBFS: Found @ offset 2b0c0 size e88
41340293.942: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41341293.942: CBFS: Locating 'cmos_layout.bin'
41342293.942: CBFS: Found @ offset 2b0c0 size e88
41343293.942: mctAutoInitMCT_D: :OtherTiming
41344293.943: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41345293.943: CBFS: Locating 'cmos_layout.bin'
41346293.943: CBFS: Found @ offset 2b0c0 size e88
41347293.944: InterleaveNodes_D: Status 2205
41348293.944: InterleaveNodes_D: ErrStatus 4000
41349293.944: InterleaveNodes_D: ErrCode 0
41350293.944: InterleaveNodes_D: Done
41351293.944:
41352293.944: InterleaveChannels_D: Node 0
41353293.944: InterleaveChannels_D: Status 2205
41354293.944: InterleaveChannels_D: ErrStatus 4000
41355293.944: InterleaveChannels_D: ErrCode 0
41356293.944: InterleaveChannels_D: Node 1
41357293.944: InterleaveChannels_D: Status 2005
41358293.944: InterleaveChannels_D: ErrStatus 4000
41359293.944: InterleaveChannels_D: ErrCode 0
41360293.944: InterleaveChannels_D: Node 2
41361293.944: InterleaveChannels_D: Status 2005
41362293.944: InterleaveChannels_D: ErrStatus 4000
41363293.944: InterleaveChannels_D: ErrCode 0
41364293.944: InterleaveChannels_D: Node 3
41365293.944: InterleaveChannels_D: Status 2005
41366293.944: InterleaveChannels_D: ErrStatus 4000
41367293.944: InterleaveChannels_D: ErrCode 0
41368293.944: InterleaveChannels_D: Node 4
41369293.944: InterleaveChannels_D: Status 2000
41370293.944: InterleaveChannels_D: ErrStatus 0
41371293.944: InterleaveChannels_D: ErrCode 0
41372293.944: InterleaveChannels_D: Node 5
41373293.944: InterleaveChannels_D: Status 2000
41374293.944: InterleaveChannels_D: ErrStatus 0
41375293.944: InterleaveChannels_D: ErrCode 0
41376293.944: InterleaveChannels_D: Node 6
41377293.944: InterleaveChannels_D: Status 2000
41378293.944: InterleaveChannels_D: ErrStatus 0
41379293.944: InterleaveChannels_D: ErrCode 0
41380293.944: InterleaveChannels_D: Node 7
41381293.944: InterleaveChannels_D: Status 2000
41382293.944: InterleaveChannels_D: ErrStatus 0
41383293.944: InterleaveChannels_D: ErrCode 0
41384293.944: InterleaveChannels_D: Done
41385293.944:
41386293.944: mctAutoInitMCT_D: ECCInit_D
41387293.945: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41388293.945: CBFS: Locating 'cmos_layout.bin'
41389293.945: CBFS: Found @ offset 2b0c0 size e88
41390293.945: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41391293.945: CBFS: Locating 'cmos_layout.bin'
41392293.945: CBFS: Found @ offset 2b0c0 size e88
41393293.946: ECC enabled on node: 00
41394293.946: DCTMemClr_Sync_D: Start
41395293.946: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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41396294.925: .
41397294.925: DCTMemClr_Sync_D: Done
41398294.925: ECC enabled on node: 01
41399294.925: DCTMemClr_Sync_D: Start
41400294.925: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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41401295.904: .
41402295.904: DCTMemClr_Sync_D: Done
41403295.904: ECC enabled on node: 02
41404295.904: DCTMemClr_Sync_D: Start
41405295.904: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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41406296.883: .
41407296.883: DCTMemClr_Sync_D: Done
41408296.883: ECC enabled on node: 03
41409296.883: DCTMemClr_Sync_D: Start
41410296.883: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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41411297.862: .
41412297.862: DCTMemClr_Sync_D: Done
41413297.862: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41414297.862: CBFS: Locating 'cmos_layout.bin'
41415297.862: CBFS: Found @ offset 2b0c0 size e88
41416297.862: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41417297.862: CBFS: Locating 'cmos_layout.bin'
41418297.862: CBFS: Found @ offset 2b0c0 size e88
41419297.862: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41420297.862: CBFS: Locating 'cmos_layout.bin'
41421297.862: CBFS: Found @ offset 2b0c0 size e88
41422297.863: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41423297.863: CBFS: Locating 'cmos_layout.bin'
41424297.863: CBFS: Found @ offset 2b0c0 size e88
41425297.863: ECCInit: Node 00
41426297.863: ECCInit: Status 2205
41427297.863: ECCInit: ErrStatus 4000
41428297.863: ECCInit: ErrCode 0
41429297.863: ECCInit: Done
41430297.863: ECCInit: Node 01
41431297.863: ECCInit: Status 2005
41432297.863: ECCInit: ErrStatus 4000
41433297.863: ECCInit: ErrCode 0
41434297.863: ECCInit: Done
41435297.863: ECCInit: Node 02
41436297.863: ECCInit: Status 2005
41437297.863: ECCInit: ErrStatus 4000
41438297.863: ECCInit: ErrCode 0
41439297.863: ECCInit: Done
41440297.863: ECCInit: Node 03
41441297.863: ECCInit: Status 2005
41442297.863: ECCInit: ErrStatus 4000
41443297.863: ECCInit: ErrCode 0
41444297.863: ECCInit: Done
41445297.863: mctAutoInitMCT_D: CPUMemTyping_D
41446297.864: <09> CPUMemTyping: Cache32bTOP:c00000
41447297.864: <09> CPUMemTyping: Bottom32bIO:c00000
41448297.864: <09> CPUMemTyping: Bottom40bIO:40400000
41449297.864: mctAutoInitMCT_D: UMAMemTyping_D
41450297.864: mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
41451297.864: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41452297.864: CBFS: Locating 'cmos_layout.bin'
41453297.864: CBFS: Found @ offset 2b0c0 size e88
41454297.864: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 0 (interleaved: 0)
41455297.864: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 103fffffff
41456297.865: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
41457297.865: set_up_cc6_storage_fam15:<09>Target node: 3
41458297.865: set_up_cc6_storage_fam15:<09>Done
41459297.865: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 1 (interleaved: 0)
41460297.865: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 203fffffff
41461297.865: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
41462297.865: set_up_cc6_storage_fam15:<09>Target node: 3
41463297.865: set_up_cc6_storage_fam15:<09>Done
41464297.865: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 2 (interleaved: 0)
41465297.865: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 303fffffff
41466297.865: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
41467297.865: set_up_cc6_storage_fam15:<09>Target node: 3
41468297.865: set_up_cc6_storage_fam15:<09>Done
41469297.865: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 3 (interleaved: 0)
41470297.865: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit: 403fffffff DRAM limit: 403fffffff
41471297.865: set_up_cc6_storage_fam15:<09>new max_range_limit: 403effffff
41472297.865: set_up_cc6_storage_fam15:<09>Target node: 3
41473297.865: set_up_cc6_storage_fam15:<09>Done
41474297.865: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41475297.865: CBFS: Locating 'cmos_layout.bin'
41476297.865: CBFS: Found @ offset 2b0c0 size e88
41477297.866: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41478297.866: CBFS: Locating 'cmos_layout.bin'
41479297.866: CBFS: Found @ offset 2b0c0 size e88
41480297.866: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41481297.866: CBFS: Locating 'cmos_layout.bin'
41482297.866: CBFS: Found @ offset 2b0c0 size e88
41483297.866: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41484297.866: CBFS: Locating 'cmos_layout.bin'
41485297.866: CBFS: Found @ offset 2b0c0 size e88
41486297.866: mctAutoInitMCT_D Done: Global Status: 12
41487297.866: raminit_amdmct end:
41488297.867: CBMEM:
41489297.867: IMD: root @ b7fff000 254 entries.
41490297.867: IMD: root @ b7ffec00 62 entries.
41491297.868: amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
41492297.868: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41493297.868: CBFS: Locating 'cmos_layout.bin'
41494297.868: CBFS: Found @ offset 2b0c0 size e88
41495297.869: disable_spd()
41496297.995: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41497297.995: CBFS: Locating 'fallback/ramstage'
41498297.996: CBFS: Found @ offset 3ff00 size 1544c
41499298.039: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41500298.039: CBFS: Locating 'cmos_layout.bin'
41501298.039: CBFS: Found @ offset 2b0c0 size e88
41502298.040: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41503298.040: CBFS: Locating 'cmos_layout.bin'
41504298.040: CBFS: Found @ offset 2b0c0 size e88
41505298.040:
41506298.040:
41507298.040: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 ramstage starting...
41508298.040: Moving GDT to b7ffe9e0...ok
41509298.040: Normal boot.
41510298.040: BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
41511298.040: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
41512298.040: Enumerating buses...
41513298.040: Show all devs... Before device enumeration.
41514298.040: Root Device: enabled 1
41515298.040: CPU_CLUSTER: 0: enabled 1
41516298.040: APIC: 00: enabled 1
41517298.040: DOMAIN: 0000: enabled 1
41518298.040: PCI: 00:18.0: enabled 1
41519298.040: PCI: 00:00.0: enabled 1
41520298.040: PCI: 00:00.1: enabled 1
41521298.040: PCI: 00:00.2: enabled 1
41522298.040: PCI: 00:02.0: enabled 1
41523298.040: PCI: 00:03.0: enabled 0
41524298.040: PCI: 00:04.0: enabled 1
41525298.040: PCI: 00:05.0: enabled 0
41526298.040: PCI: 00:06.0: enabled 0
41527298.040: PCI: 00:07.0: enabled 0
41528298.040: PCI: 00:08.0: enabled 0
41529298.040: PCI: 00:09.0: enabled 1
41530298.040: PCI: 00:0a.0: enabled 1
41531298.040: PCI: 00:0b.0: enabled 1
41532298.040: PCI: 00:0c.0: enabled 1
41533298.040: PCI: 00:0d.0: enabled 1
41534298.040: PCI: 00:11.0: enabled 1
41535298.040: PCI: 00:12.0: enabled 1
41536298.040: PCI: 00:12.1: enabled 1
41537298.040: PCI: 00:12.2: enabled 1
41538298.040: PCI: 00:13.0: enabled 1
41539298.040: PCI: 00:13.1: enabled 1
41540298.040: PCI: 00:13.2: enabled 1
41541298.040: PCI: 00:14.0: enabled 1
41542298.040: I2C: 00:50: enabled 1
41543298.040: I2C: 00:51: enabled 1
41544298.040: I2C: 00:52: enabled 1
41545298.040: I2C: 00:53: enabled 1
41546298.040: I2C: 00:54: enabled 1
41547298.040: I2C: 00:55: enabled 1
41548298.041: I2C: 00:56: enabled 1
41549298.041: I2C: 00:57: enabled 1
41550298.041: I2C: 00:2f: enabled 1
41551298.041: PCI: 00:14.1: enabled 1
41552298.041: PCI: 00:14.2: enabled 1
41553298.041: PCI: 00:14.3: enabled 1
41554298.041: PNP: 002e.0: enabled 0
41555298.041: PNP: 002e.1: enabled 0
41556298.041: PNP: 002e.2: enabled 1
41557298.041: PNP: 002e.3: enabled 1
41558298.041: PNP: 002e.5: enabled 1
41559298.041: PNP: 002e.106: enabled 0
41560298.041: PNP: 002e.107: enabled 0
41561298.041: PNP: 002e.207: enabled 0
41562298.041: PNP: 002e.307: enabled 0
41563298.041: PNP: 002e.407: enabled 0
41564298.041: PNP: 002e.8: enabled 0
41565298.041: PNP: 002e.108: enabled 0
41566298.041: PNP: 002e.9: enabled 0
41567298.041: PNP: 002e.109: enabled 0
41568298.041: PNP: 002e.209: enabled 0
41569298.041: PNP: 002e.309: enabled 0
41570298.041: PNP: 002e.a: enabled 1
41571298.041: PNP: 002e.b: enabled 1
41572298.041: PNP: 002e.c: enabled 0
41573298.041: PNP: 002e.d: enabled 0
41574298.041: PNP: 002e.f: enabled 0
41575298.041: PNP: 004e.0: enabled 1
41576298.041: PCI: 00:14.4: enabled 1
41577298.041: PCI: 00:01.0: enabled 1
41578298.041: PCI: 00:02.0: enabled 1
41579298.041: PCI: 00:03.0: enabled 1
41580298.041: PCI: 00:14.5: enabled 1
41581298.041: PCI: 00:18.1: enabled 1
41582298.041: PCI: 00:18.2: enabled 1
41583298.041: PCI: 00:18.3: enabled 1
41584298.041: PCI: 00:18.4: enabled 1
41585298.041: PCI: 00:18.5: enabled 1
41586298.041: PCI: 00:19.0: enabled 1
41587298.041: PCI: 00:19.1: enabled 1
41588298.041: PCI: 00:19.2: enabled 1
41589298.041: PCI: 00:19.3: enabled 1
41590298.041: PCI: 00:19.4: enabled 1
41591298.041: PCI: 00:19.5: enabled 1
41592298.041: PCI: 00:1a.0: enabled 1
41593298.041: PCI: 00:1a.1: enabled 1
41594298.041: PCI: 00:1a.2: enabled 1
41595298.041: PCI: 00:1a.3: enabled 1
41596298.041: PCI: 00:1a.4: enabled 1
41597298.041: PCI: 00:1a.5: enabled 1
41598298.041: PCI: 00:1b.0: enabled 1
41599298.041: PCI: 00:1b.1: enabled 1
41600298.041: PCI: 00:1b.2: enabled 1
41601298.041: PCI: 00:1b.3: enabled 1
41602298.041: PCI: 00:1b.4: enabled 1
41603298.041: PCI: 00:1b.5: enabled 1
41604298.041: Compare with tree...
41605298.041: Root Device: enabled 1
41606298.041: CPU_CLUSTER: 0: enabled 1
41607298.041: APIC: 00: enabled 1
41608298.041: DOMAIN: 0000: enabled 1
41609298.041: PCI: 00:18.0: enabled 1
41610298.041: PCI: 00:00.0: enabled 1
41611298.041: PCI: 00:00.1: enabled 1
41612298.041: PCI: 00:00.2: enabled 1
41613298.041: PCI: 00:02.0: enabled 1
41614298.041: PCI: 00:03.0: enabled 0
41615298.041: PCI: 00:04.0: enabled 1
41616298.041: PCI: 00:05.0: enabled 0
41617298.041: PCI: 00:06.0: enabled 0
41618298.041: PCI: 00:07.0: enabled 0
41619298.041: PCI: 00:08.0: enabled 0
41620298.042: PCI: 00:09.0: enabled 1
41621298.042: PCI: 00:0a.0: enabled 1
41622298.042: PCI: 00:0b.0: enabled 1
41623298.042: PCI: 00:0c.0: enabled 1
41624298.042: PCI: 00:0d.0: enabled 1
41625298.042: PCI: 00:11.0: enabled 1
41626298.042: PCI: 00:12.0: enabled 1
41627298.042: PCI: 00:12.1: enabled 1
41628298.042: PCI: 00:12.2: enabled 1
41629298.042: PCI: 00:13.0: enabled 1
41630298.042: PCI: 00:13.1: enabled 1
41631298.042: PCI: 00:13.2: enabled 1
41632298.042: PCI: 00:14.0: enabled 1
41633298.042: I2C: 00:50: enabled 1
41634298.042: I2C: 00:51: enabled 1
41635298.042: I2C: 00:52: enabled 1
41636298.042: I2C: 00:53: enabled 1
41637298.042: I2C: 00:54: enabled 1
41638298.042: I2C: 00:55: enabled 1
41639298.042: I2C: 00:56: enabled 1
41640298.042: I2C: 00:57: enabled 1
41641298.042: I2C: 00:2f: enabled 1
41642298.042: PCI: 00:14.1: enabled 1
41643298.042: PCI: 00:14.2: enabled 1
41644298.042: PCI: 00:14.3: enabled 1
41645298.042: PNP: 002e.0: enabled 0
41646298.042: PNP: 002e.1: enabled 0
41647298.042: PNP: 002e.2: enabled 1
41648298.042: PNP: 002e.3: enabled 1
41649298.042: PNP: 002e.5: enabled 1
41650298.042: PNP: 002e.106: enabled 0
41651298.042: PNP: 002e.107: enabled 0
41652298.042: PNP: 002e.207: enabled 0
41653298.042: PNP: 002e.307: enabled 0
41654298.042: PNP: 002e.407: enabled 0
41655298.042: PNP: 002e.8: enabled 0
41656298.042: PNP: 002e.108: enabled 0
41657298.042: PNP: 002e.9: enabled 0
41658298.042: PNP: 002e.109: enabled 0
41659298.042: PNP: 002e.209: enabled 0
41660298.042: PNP: 002e.309: enabled 0
41661298.042: PNP: 002e.a: enabled 1
41662298.042: PNP: 002e.b: enabled 1
41663298.042: PNP: 002e.c: enabled 0
41664298.042: PNP: 002e.d: enabled 0
41665298.042: PNP: 002e.f: enabled 0
41666298.042: PNP: 004e.0: enabled 1
41667298.042: PCI: 00:14.4: enabled 1
41668298.042: PCI: 00:01.0: enabled 1
41669298.042: PCI: 00:02.0: enabled 1
41670298.042: PCI: 00:03.0: enabled 1
41671298.042: PCI: 00:14.5: enabled 1
41672298.042: PCI: 00:18.1: enabled 1
41673298.042: PCI: 00:18.2: enabled 1
41674298.042: PCI: 00:18.3: enabled 1
41675298.042: PCI: 00:18.4: enabled 1
41676298.042: PCI: 00:18.5: enabled 1
41677298.042: PCI: 00:19.0: enabled 1
41678298.042: PCI: 00:19.1: enabled 1
41679298.042: PCI: 00:19.2: enabled 1
41680298.042: PCI: 00:19.3: enabled 1
41681298.042: PCI: 00:19.4: enabled 1
41682298.042: PCI: 00:19.5: enabled 1
41683298.042: PCI: 00:1a.0: enabled 1
41684298.042: PCI: 00:1a.1: enabled 1
41685298.042: PCI: 00:1a.2: enabled 1
41686298.042: PCI: 00:1a.3: enabled 1
41687298.042: PCI: 00:1a.4: enabled 1
41688298.042: PCI: 00:1a.5: enabled 1
41689298.042: PCI: 00:1b.0: enabled 1
41690298.042: PCI: 00:1b.1: enabled 1
41691298.042: PCI: 00:1b.2: enabled 1
41692298.042: PCI: 00:1b.3: enabled 1
41693298.042: PCI: 00:1b.4: enabled 1
41694298.042: PCI: 00:1b.5: enabled 1
41695298.043: Mainboard KGPE-D16 Enable. dev=0x0012cbe0
41696298.043: mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
41697298.043: mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000040
41698298.043: Root Device scanning...
41699298.043: root_dev_scan_bus for Root Device
41700298.043: setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
41701298.043: setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000040
41702298.043: CPU_CLUSTER: 0 enabled
41703298.043: DOMAIN: 0000 enabled
41704298.043: CPU_CLUSTER: 0 scanning...
41705298.043: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41706298.043: CBFS: Locating 'cmos_layout.bin'
41707298.043: CBFS: Found @ offset 2b0c0 size e88
41708298.043: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
41709298.043: CBFS: Locating 'cmos_layout.bin'
41710298.043: CBFS: Found @ offset 2b0c0 size e88
41711298.044: PCI: 00:18.5 siblings=7
41712298.044: CPU: APIC: 00 enabled
41713298.044: CPU: APIC: 01 enabled
41714298.044: CPU: APIC: 02 enabled
41715298.044: CPU: APIC: 03 enabled
41716298.044: CPU: APIC: 04 enabled
41717298.044: CPU: APIC: 05 enabled
41718298.044: CPU: APIC: 06 enabled
41719298.044: CPU: APIC: 07 enabled
41720298.044: PCI: 00:19.5 siblings=7
41721298.044: CPU: APIC: 08 enabled
41722298.044: CPU: APIC: 09 enabled
41723298.044: CPU: APIC: 0a enabled
41724298.044: CPU: APIC: 0b enabled
41725298.044: CPU: APIC: 0c enabled
41726298.044: CPU: APIC: 0d enabled
41727298.044: CPU: APIC: 0e enabled
41728298.044: CPU: APIC: 0f enabled
41729298.044: PCI: 00:1a.5 siblings=7
41730298.044: CPU: APIC: 20 enabled
41731298.044: CPU: APIC: 21 enabled
41732298.044: CPU: APIC: 22 enabled
41733298.044: CPU: APIC: 23 enabled
41734298.044: CPU: APIC: 24 enabled
41735298.044: CPU: APIC: 25 enabled
41736298.044: CPU: APIC: 26 enabled
41737298.044: CPU: APIC: 27 enabled
41738298.044: PCI: 00:1b.5 siblings=7
41739298.044: CPU: APIC: 28 enabled
41740298.044: CPU: APIC: 29 enabled
41741298.044: CPU: APIC: 2a enabled
41742298.044: CPU: APIC: 2b enabled
41743298.044: CPU: APIC: 2c enabled
41744298.044: CPU: APIC: 2d enabled
41745298.044: CPU: APIC: 2e enabled
41746298.044: CPU: APIC: 2f enabled
41747298.044: scan_bus: scanning of bus CPU_CLUSTER: 0 took 72680 usecs
41748298.044: DOMAIN: 0000 scanning...
41749298.044: PCI: pci_scan_bus for bus 00
41750298.044: PCI: 00:18.0 [1022/1600] bus ops
41751298.044: PCI: 00:18.0 [1022/1600] enabled
41752298.044: PCI: 00:18.1 [1022/1601] enabled
41753298.044: PCI: 00:18.2 [1022/1602] enabled
41754298.044: PCI: 00:18.3 [1022/1603] ops
41755298.044: PCI: 00:18.3 [1022/1603] enabled
41756298.044: PCI: 00:18.4 [1022/1604] ops
41757298.044: PCI: 00:18.4 [1022/1604] enabled
41758298.044: PCI: 00:18.5 [1022/1605] ops
41759298.044: PCI: 00:18.5 [1022/1605] enabled
41760298.044: PCI: 00:19.0 [1022/1600] bus ops
41761298.044: PCI: 00:19.0 [1022/1600] enabled
41762298.044: PCI: 00:19.1 [1022/1601] enabled
41763298.044: PCI: 00:19.2 [1022/1602] enabled
41764298.044: PCI: 00:19.3 [1022/1603] ops
41765298.044: PCI: 00:19.3 [1022/1603] enabled
41766298.044: PCI: 00:19.4 [1022/1604] ops
41767298.044: PCI: 00:19.4 [1022/1604] enabled
41768298.044: PCI: 00:19.5 [1022/1605] ops
41769298.044: PCI: 00:19.5 [1022/1605] enabled
41770298.045: PCI: 00:1a.0 [1022/1600] bus ops
41771298.045: PCI: 00:1a.0 [1022/1600] enabled
41772298.045: PCI: 00:1a.1 [1022/1601] enabled
41773298.045: PCI: 00:1a.2 [1022/1602] enabled
41774298.045: PCI: 00:1a.3 [1022/1603] ops
41775298.045: PCI: 00:1a.3 [1022/1603] enabled
41776298.045: PCI: 00:1a.4 [1022/1604] ops
41777298.045: PCI: 00:1a.4 [1022/1604] enabled
41778298.045: PCI: 00:1a.5 [1022/1605] ops
41779298.045: PCI: 00:1a.5 [1022/1605] enabled
41780298.045: PCI: 00:1b.0 [1022/1600] bus ops
41781298.045: PCI: 00:1b.0 [1022/1600] enabled
41782298.045: PCI: 00:1b.1 [1022/1601] enabled
41783298.045: PCI: 00:1b.2 [1022/1602] enabled
41784298.045: PCI: 00:1b.3 [1022/1603] ops
41785298.045: PCI: 00:1b.3 [1022/1603] enabled
41786298.045: PCI: 00:1b.4 [1022/1604] ops
41787298.045: PCI: 00:1b.4 [1022/1604] enabled
41788298.045: PCI: 00:1b.5 [1022/1605] ops
41789298.045: PCI: 00:1b.5 [1022/1605] enabled
41790298.045: PCI: 00:18.0 scanning...
41791298.045: do_hypertransport_scan_chain for bus 00
41792298.045: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
41793298.045: Bus-0, Dev-0, Fun-0.
41794298.045: enable_pcie_bar3
41795298.048: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
41796298.048: PciePowerOffGppPorts() port 8
41797298.048: NB_PCI_REG04 = 2.
41798298.048: NB_PCI_REG84 = 3000010.
41799298.048: NB_PCI_REG4C = 52042.
41800298.048: Sysmem TOM = 0_c0000000
41801298.048: Sysmem TOM2 = 40_40000000
41802298.048: PCI: 00:00.0 [1002/5a10] ops
41803298.048: PCI: 00:00.0 [1002/5a10] enabled
41804298.048: Capability: type 0x08 @ 0xf0
41805298.048: flags: 0xa803
41806298.048: Capability: type 0x08 @ 0xf0
41807298.048: Capability: type 0x08 @ 0xc4
41808298.048: flags: 0x0280
41809298.048: PCI: 00:00.0 count: 0014 static_count: 0015
41810298.048: PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015
41811298.048: PCI: pci_scan_bus for bus 00
41812298.048: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
41813298.048: Bus-0, Dev-0, Fun-0.
41814298.048: enable_pcie_bar3
41815298.051: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
41816298.051: PciePowerOffGppPorts() port 8
41817298.051: NB_PCI_REG04 = 2.
41818298.051: NB_PCI_REG84 = 3000010.
41819298.051: NB_PCI_REG4C = 52042.
41820298.051: Sysmem TOM = 0_c0000000
41821298.051: Sysmem TOM2 = 40_40000000
41822298.051: PCI: 00:00.0 [1002/5a10] enabled
41823298.051: sr5650_enable: dev=0012f460, VID_DID=0xffffffff
41824298.051: Bus-0, Dev-0, Fun-1.
41825298.051: PCI: Static device PCI: 00:00.1 not found, disabling it.
41826298.051: sr5650_enable: dev=0012f3c0, VID_DID=0x5a231002
41827298.051: Bus-0, Dev-0, Fun-2.
41828298.051: PCI: 00:00.2 [1002/5a23] ops
41829298.051: PCI: 00:00.2 [1002/5a23] enabled
41830298.051: sr5650_enable: dev=0012f320, VID_DID=0xffffffff
41831298.051: Bus-0, Dev-2,3, Fun-0. enable=1
41832298.052: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f320, port=0x2
41833298.092: PcieLinkTraining port=2:lc current state=2030400
41834298.093: sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0
41835298.093: PciePowerOffGppPorts() port 2
41836298.093: Capability: type 0x01 @ 0x50
41837298.093: Capability: type 0x10 @ 0x58
41838298.093: Capability: type 0x05 @ 0xa0
41839298.093: Capability: type 0x0d @ 0xb0
41840298.093: Capability: type 0x08 @ 0xb8
41841298.093: Capability: type 0x01 @ 0x50
41842298.093: Capability: type 0x10 @ 0x58
41843298.093: Capability: type 0x05 @ 0xa0
41844298.093: Capability: type 0x0d @ 0xb0
41845298.093: Capability: type 0x08 @ 0xb8
41846298.093: Capability: type 0x01 @ 0x50
41847298.093: Capability: type 0x10 @ 0x58
41848298.093: Capability: type 0x05 @ 0xa0
41849298.093: Capability: type 0x0d @ 0xb0
41850298.093: Capability: type 0x08 @ 0xb8
41851298.093: Capability: type 0x01 @ 0x50
41852298.093: Capability: type 0x10 @ 0x58
41853298.093: PCI: 00:02.0 subordinate bus PCI Express
41854298.093: PCI: 00:02.0 [1002/5a16] enabled
41855298.093: sr5650_enable: dev=0012f280, VID_DID=0xffffffff
41856298.093: Bus-0, Dev-2,3, Fun-0. enable=0
41857298.093: sr5650_enable: dev=0012f1e0, VID_DID=0xffffffff
41858298.093: enable_pcie_bar3
41859298.093: Bus-0, Dev-4,5,6,7, Fun-0. enable=1
41860298.093: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f1e0, port=0x4
41861298.133: PcieLinkTraining port=4:lc current state=2030400
41862298.134: sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
41863298.134: PciePowerOffGppPorts() port 4
41864298.134: Capability: type 0x01 @ 0x50
41865298.134: Capability: type 0x10 @ 0x58
41866298.134: Capability: type 0x05 @ 0xa0
41867298.134: Capability: type 0x0d @ 0xb0
41868298.134: Capability: type 0x08 @ 0xb8
41869298.134: Capability: type 0x01 @ 0x50
41870298.134: Capability: type 0x10 @ 0x58
41871298.134: Capability: type 0x05 @ 0xa0
41872298.134: Capability: type 0x0d @ 0xb0
41873298.134: Capability: type 0x08 @ 0xb8
41874298.134: Capability: type 0x01 @ 0x50
41875298.135: Capability: type 0x10 @ 0x58
41876298.135: Capability: type 0x05 @ 0xa0
41877298.135: Capability: type 0x0d @ 0xb0
41878298.135: Capability: type 0x08 @ 0xb8
41879298.135: Capability: type 0x01 @ 0x50
41880298.135: Capability: type 0x10 @ 0x58
41881298.135: PCI: 00:04.0 subordinate bus PCI Express
41882298.135: PCI: 00:04.0 [1002/5a18] enabled
41883298.135: sr5650_enable: dev=0012f140, VID_DID=0xffffffff
41884298.135: enable_pcie_bar3
41885298.135: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
41886298.135: sr5650_enable: dev=0012f0a0, VID_DID=0xffffffff
41887298.135: enable_pcie_bar3
41888298.135: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
41889298.135: sr5650_enable: dev=0012f000, VID_DID=0xffffffff
41890298.135: enable_pcie_bar3
41891298.135: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
41892298.135: sr5650_enable: dev=0012ef60, VID_DID=0xffffffff
41893298.135: Bus-0, Dev-8, Fun-0. enable=0
41894298.135: disable_pcie_bar3
41895298.135: sr5650_enable: dev=0012eec0, VID_DID=0xffffffff
41896298.135: Bus-0, Dev-9, 10, Fun-0. enable=1
41897298.135: enable_pcie_bar3
41898298.135: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012eec0, port=0x9
41899298.175: PcieLinkTraining port=5:lc current state=a0b0f10
41900298.175: addr=c0000000,bus=0,devfn=48
41901298.175: PcieTrainPort reg=0x10000
41902298.175: sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
41903298.175: Capability: type 0x01 @ 0x50
41904298.175: Capability: type 0x10 @ 0x58
41905298.175: Capability: type 0x05 @ 0xa0
41906298.175: Capability: type 0x0d @ 0xb0
41907298.175: Capability: type 0x08 @ 0xb8
41908298.175: Capability: type 0x01 @ 0x50
41909298.175: Capability: type 0x10 @ 0x58
41910298.175: Capability: type 0x05 @ 0xa0
41911298.175: Capability: type 0x0d @ 0xb0
41912298.175: Capability: type 0x08 @ 0xb8
41913298.175: Capability: type 0x01 @ 0x50
41914298.175: Capability: type 0x10 @ 0x58
41915298.175: Capability: type 0x05 @ 0xa0
41916298.175: Capability: type 0x0d @ 0xb0
41917298.175: Capability: type 0x08 @ 0xb8
41918298.175: Capability: type 0x01 @ 0x50
41919298.175: Capability: type 0x10 @ 0x58
41920298.175: PCI: 00:09.0 subordinate bus PCI Express
41921298.175: PCI: 00:09.0 [1002/5a1c] enabled
41922298.175: sr5650_enable: dev=0012ee20, VID_DID=0xffffffff
41923298.175: Bus-0, Dev-9, 10, Fun-0. enable=1
41924298.175: enable_pcie_bar3
41925298.175: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ee20, port=0xa
41926298.216: PcieLinkTraining port=6:lc current state=a0b0f10
41927298.216: addr=c0000000,bus=0,devfn=50
41928298.216: PcieTrainPort reg=0x10000
41929298.216: sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
41930298.216: Capability: type 0x01 @ 0x50
41931298.216: Capability: type 0x10 @ 0x58
41932298.216: Capability: type 0x05 @ 0xa0
41933298.216: Capability: type 0x0d @ 0xb0
41934298.216: Capability: type 0x08 @ 0xb8
41935298.216: Capability: type 0x01 @ 0x50
41936298.216: Capability: type 0x10 @ 0x58
41937298.216: Capability: type 0x05 @ 0xa0
41938298.216: Capability: type 0x0d @ 0xb0
41939298.216: Capability: type 0x08 @ 0xb8
41940298.216: Capability: type 0x01 @ 0x50
41941298.216: Capability: type 0x10 @ 0x58
41942298.216: Capability: type 0x05 @ 0xa0
41943298.216: Capability: type 0x0d @ 0xb0
41944298.216: Capability: type 0x08 @ 0xb8
41945298.216: Capability: type 0x01 @ 0x50
41946298.216: Capability: type 0x10 @ 0x58
41947298.216: PCI: 00:0a.0 subordinate bus PCI Express
41948298.216: PCI: 00:0a.0 [1002/5a1d] enabled
41949298.216: sr5650_enable: dev=0012ed80, VID_DID=0xffffffff
41950298.216: Bus-0, Dev-11,12, Fun-0. enable=1
41951298.216: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ed80, port=0xb
41952298.256: PcieLinkTraining port=b:lc current state=2030400
41953298.257: sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0
41954298.257: PciePowerOffGppPorts() port 11
41955298.257: Capability: type 0x01 @ 0x50
41956298.257: Capability: type 0x10 @ 0x58
41957298.257: Capability: type 0x05 @ 0xa0
41958298.257: Capability: type 0x0d @ 0xb0
41959298.257: Capability: type 0x08 @ 0xb8
41960298.257: Capability: type 0x01 @ 0x50
41961298.257: Capability: type 0x10 @ 0x58
41962298.257: Capability: type 0x05 @ 0xa0
41963298.257: Capability: type 0x0d @ 0xb0
41964298.257: Capability: type 0x08 @ 0xb8
41965298.257: Capability: type 0x01 @ 0x50
41966298.257: Capability: type 0x10 @ 0x58
41967298.257: Capability: type 0x05 @ 0xa0
41968298.257: Capability: type 0x0d @ 0xb0
41969298.257: Capability: type 0x08 @ 0xb8
41970298.257: Capability: type 0x01 @ 0x50
41971298.257: Capability: type 0x10 @ 0x58
41972298.257: PCI: 00:0b.0 subordinate bus PCI Express
41973298.257: PCI: 00:0b.0 [1002/5a1f] enabled
41974298.257: sr5650_enable: dev=0012ece0, VID_DID=0xffffffff
41975298.257: Bus-0, Dev-11,12, Fun-0. enable=1
41976298.257: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ece0, port=0xc
41977298.298: PcieLinkTraining port=c:lc current state=2030400
41978298.299: sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0
41979298.299: PciePowerOffGppPorts() port 12
41980298.299: Capability: type 0x01 @ 0x50
41981298.299: Capability: type 0x10 @ 0x58
41982298.299: Capability: type 0x05 @ 0xa0
41983298.299: Capability: type 0x0d @ 0xb0
41984298.299: Capability: type 0x08 @ 0xb8
41985298.299: Capability: type 0x01 @ 0x50
41986298.299: Capability: type 0x10 @ 0x58
41987298.299: Capability: type 0x05 @ 0xa0
41988298.299: Capability: type 0x0d @ 0xb0
41989298.299: Capability: type 0x08 @ 0xb8
41990298.299: Capability: type 0x01 @ 0x50
41991298.299: Capability: type 0x10 @ 0x58
41992298.299: Capability: type 0x05 @ 0xa0
41993298.299: Capability: type 0x0d @ 0xb0
41994298.299: Capability: type 0x08 @ 0xb8
41995298.299: Capability: type 0x01 @ 0x50
41996298.299: Capability: type 0x10 @ 0x58
41997298.299: PCI: 00:0c.0 subordinate bus PCI Express
41998298.299: PCI: 00:0c.0 [1002/5a20] enabled
41999298.299: sr5650_enable: dev=0012ec40, VID_DID=0xffffffff
42000298.299: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ec40, port=0xd
42001298.339: PcieLinkTraining port=d:lc current state=20212210
42002298.339: addr=c0000000,bus=0,devfn=68
42003298.339: PcieTrainPort reg=0x10000
42004298.339: sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1
42005299.339: Capability: type 0x01 @ 0x50
42006299.339: Capability: type 0x10 @ 0x58
42007299.339: Capability: type 0x05 @ 0xa0
42008299.339: Capability: type 0x0d @ 0xb0
42009299.339: Capability: type 0x08 @ 0xb8
42010299.339: Capability: type 0x01 @ 0x50
42011299.339: Capability: type 0x10 @ 0x58
42012299.339: Capability: type 0x05 @ 0xa0
42013299.339: Capability: type 0x0d @ 0xb0
42014299.339: Capability: type 0x08 @ 0xb8
42015299.339: Capability: type 0x01 @ 0x50
42016299.339: Capability: type 0x10 @ 0x58
42017299.339: Capability: type 0x05 @ 0xa0
42018299.339: Capability: type 0x0d @ 0xb0
42019299.339: Capability: type 0x08 @ 0xb8
42020299.339: Capability: type 0x01 @ 0x50
42021299.339: Capability: type 0x10 @ 0x58
42022299.339: PCI: 00:0d.0 subordinate bus PCI Express
42023299.339: PCI: 00:0d.0 [1002/5a1e] enabled
42024299.339: sb7xx_51xx_enable()
42025299.340: PCI: 00:11.0 [1002/4394] ops
42026299.340: PCI: 00:11.0 [1002/4394] enabled
42027299.340: sb7xx_51xx_enable()
42028299.340: PCI: 00:12.0 [1002/4397] ops
42029299.340: PCI: 00:12.0 [1002/4397] enabled
42030299.340: sb7xx_51xx_enable()
42031299.340: PCI: 00:12.1 [1002/4398] ops
42032299.340: PCI: 00:12.1 [1002/4398] enabled
42033299.340: sb7xx_51xx_enable()
42034299.340: PCI: 00:12.2 [1002/4396] ops
42035299.340: PCI: 00:12.2 [1002/4396] enabled
42036299.340: sb7xx_51xx_enable()
42037299.340: PCI: 00:13.0 [1002/4397] ops
42038299.340: PCI: 00:13.0 [1002/4397] enabled
42039299.340: sb7xx_51xx_enable()
42040299.340: PCI: 00:13.1 [1002/4398] ops
42041299.340: PCI: 00:13.1 [1002/4398] enabled
42042299.340: sb7xx_51xx_enable()
42043299.340: PCI: 00:13.2 [1002/4396] ops
42044299.340: PCI: 00:13.2 [1002/4396] enabled
42045299.340: sb7xx_51xx_enable()
42046299.340: PCI: 00:14.0 [1002/4385] bus ops
42047299.340: PCI: 00:14.0 [1002/4385] enabled
42048299.340: sb7xx_51xx_enable()
42049299.340: PCI: 00:14.1 [1002/439c] ops
42050299.340: PCI: 00:14.1 [1002/439c] enabled
42051299.340: sb7xx_51xx_enable()
42052299.340: PCI: 00:14.2 [1002/4383] ops
42053299.340: PCI: 00:14.2 [1002/4383] enabled
42054299.340: sb7xx_51xx_enable()
42055299.340: PCI: 00:14.3 [1002/439d] bus ops
42056299.340: PCI: 00:14.3 [1002/439d] enabled
42057299.340: sb7xx_51xx_enable()
42058299.340: PCI: 00:14.4 [1002/4384] bus ops
42059299.340: PCI: 00:14.4 [1002/4384] enabled
42060299.340: sb7xx_51xx_enable()
42061299.340: PCI: 00:14.5 [1002/4399] ops
42062299.340: PCI: 00:14.5 [1002/4399] enabled
42063299.340: PCI: 00:02.0 scanning...
42064299.340: do_pci_scan_bridge for PCI: 00:02.0
42065299.340: PCI: pci_scan_bus for bus 01
42066299.340: scan_bus: scanning of bus PCI: 00:02.0 took 5919 usecs
42067299.340: PCI: 00:04.0 scanning...
42068299.340: do_pci_scan_bridge for PCI: 00:04.0
42069299.340: PCI: pci_scan_bus for bus 02
42070299.340: scan_bus: scanning of bus PCI: 00:04.0 took 5920 usecs
42071299.340: PCI: 00:09.0 scanning...
42072299.340: do_pci_scan_bridge for PCI: 00:09.0
42073299.340: PCI: pci_scan_bus for bus 03
42074299.340: PCI: 03:00.0 [8086/10d3] enabled
42075299.340: Capability: type 0x01 @ 0xc8
42076299.340: Capability: type 0x05 @ 0xd0
42077299.340: Capability: type 0x10 @ 0xe0
42078299.340: Capability: type 0x01 @ 0x50
42079299.340: Capability: type 0x10 @ 0x58
42080299.340: Enabling Common Clock Configuration
42081299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
42082299.341: scan_bus: scanning of bus PCI: 00:09.0 took 23869 usecs
42083299.341: PCI: 00:0a.0 scanning...
42084299.341: do_pci_scan_bridge for PCI: 00:0a.0
42085299.341: PCI: pci_scan_bus for bus 04
42086299.341: PCI: 04:00.0 [8086/10d3] enabled
42087299.341: Capability: type 0x01 @ 0xc8
42088299.341: Capability: type 0x05 @ 0xd0
42089299.341: Capability: type 0x10 @ 0xe0
42090299.341: Capability: type 0x01 @ 0x50
42091299.341: Capability: type 0x10 @ 0x58
42092299.341: Enabling Common Clock Configuration
42093299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
42094299.341: scan_bus: scanning of bus PCI: 00:0a.0 took 23825 usecs
42095299.341: PCI: 00:0b.0 scanning...
42096299.341: do_pci_scan_bridge for PCI: 00:0b.0
42097299.341: PCI: pci_scan_bus for bus 05
42098299.341: scan_bus: scanning of bus PCI: 00:0b.0 took 5921 usecs
42099299.341: PCI: 00:0c.0 scanning...
42100299.341: do_pci_scan_bridge for PCI: 00:0c.0
42101299.341: PCI: pci_scan_bus for bus 06
42102299.341: scan_bus: scanning of bus PCI: 00:0c.0 took 5921 usecs
42103299.341: PCI: 00:0d.0 scanning...
42104299.341: do_pci_scan_bridge for PCI: 00:0d.0
42105299.341: PCI: pci_scan_bus for bus 07
42106299.341: PCI: 07:00.0 [8086/10fb] enabled
42107299.341: PCI: 07:00.1 [8086/10fb] enabled
42108299.341: Capability: type 0x01 @ 0x40
42109299.341: Capability: type 0x05 @ 0x50
42110299.341: Capability: type 0x11 @ 0x70
42111299.341: Capability: type 0x10 @ 0xa0
42112299.341: Capability: type 0x01 @ 0x50
42113299.341: Capability: type 0x10 @ 0x58
42114299.341: Enabling Common Clock Configuration
42115299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
42116299.341: Capability: type 0x01 @ 0x40
42117299.341: Capability: type 0x05 @ 0x50
42118299.341: Capability: type 0x11 @ 0x70
42119299.341: Capability: type 0x10 @ 0xa0
42120299.341: Capability: type 0x01 @ 0x50
42121299.341: Capability: type 0x10 @ 0x58
42122299.341: Enabling Common Clock Configuration
42123299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
42124299.342: scan_bus: scanning of bus PCI: 00:0d.0 took 45514 usecs
42125299.342: PCI: 00:14.0 scanning...
42126299.342: scan_generic_bus for PCI: 00:14.0
42127299.342: bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
42128299.342: bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
42129299.342: bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
42130299.342: bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
42131299.342: bus: PCI: 00:14.0[0]->I2C: 01:54 enabled
42132299.342: bus: PCI: 00:14.0[0]->I2C: 01:55 enabled
42133299.342: bus: PCI: 00:14.0[0]->I2C: 01:56 enabled
42134299.342: bus: PCI: 00:14.0[0]->I2C: 01:57 enabled
42135299.342: bus: PCI: 00:14.0[0]->I2C: 01:2f enabled
42136299.342: scan_generic_bus for PCI: 00:14.0 done
42137299.342: scan_bus: scanning of bus PCI: 00:14.0 took 30456 usecs
42138299.342: PCI: 00:14.3 scanning...
42139299.342: scan_lpc_bus for PCI: 00:14.3
42140299.342: PNP: 002e.0 disabled
42141299.342: PNP: 002e.1 disabled
42142299.342: PNP: 002e.2 enabled
42143299.342: PNP: 002e.3 enabled
42144299.342: PNP: 002e.5 enabled
42145299.342: PNP: 002e.106 disabled
42146299.342: PNP: 002e.107 disabled
42147299.342: PNP: 002e.207 disabled
42148299.342: PNP: 002e.307 disabled
42149299.342: PNP: 002e.407 disabled
42150299.342: PNP: 002e.8 disabled
42151299.342: PNP: 002e.108 disabled
42152299.342: PNP: 002e.9 disabled
42153299.342: PNP: 002e.109 disabled
42154299.342: PNP: 002e.209 disabled
42155299.342: PNP: 002e.309 disabled
42156299.342: PNP: 002e.a enabled
42157299.342: PNP: 002e.b enabled
42158299.343: PNP: 002e.c disabled
42159299.343: PNP: 002e.d disabled
42160299.343: PNP: 002e.f disabled
42161299.343: PNP: 004e.0 enabled
42162299.343: scan_lpc_bus for PCI: 00:14.3 done
42163299.343: scan_bus: scanning of bus PCI: 00:14.3 took 37761 usecs
42164299.343: PCI: 00:14.4 scanning...
42165299.343: do_pci_scan_bridge for PCI: 00:14.4
42166299.343: PCI: pci_scan_bus for bus 08
42167299.343: sb7xx_51xx_enable()
42168299.343: PCI: 08:01.0 [1a03/2000] ops
42169299.343: PCI: 08:01.0 [1a03/2000] enabled
42170299.343: sb7xx_51xx_enable()
42171299.343: PCI: 08:02.0 [11c1/5811] enabled
42172299.343: sb7xx_51xx_enable()
42173299.343: PCI: Static device PCI: 08:03.0 not found, disabling it.
42174299.343: scan_bus: scanning of bus PCI: 00:14.4 took 19826 usecs
42175299.343: scan_bus: scanning of bus PCI: 00:18.0 took 1754962 usecs
42176299.343: PCI: 00:19.0 scanning...
42177299.343: scan_bus: scanning of bus PCI: 00:19.0 took 1652 usecs
42178299.343: PCI: 00:1a.0 scanning...
42179299.343: scan_bus: scanning of bus PCI: 00:1a.0 took 1652 usecs
42180299.343: PCI: 00:1b.0 scanning...
42181299.343: scan_bus: scanning of bus PCI: 00:1b.0 took 1652 usecs
42182299.343: DOMAIN: 0000 passpw: enabled
42183299.343: DOMAIN: 0000 passpw: enabled
42184299.343: DOMAIN: 0000 passpw: enabled
42185299.343: DOMAIN: 0000 passpw: enabled
42186299.343: scan_bus: scanning of bus DOMAIN: 0000 took 1868725 usecs
42187299.343: root_dev_scan_bus for Root Device done
42188299.343: scan_bus: scanning of bus Root Device took 1966989 usecs
42189299.343: done
42190299.343: BS: BS_DEV_ENUMERATE times (us): entry 0 run 2288308 exit 0
42191299.343: found VGA at PCI: 08:01.0
42192299.343: Setting up VGA for PCI: 08:01.0
42193299.343: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4
42194299.343: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
42195299.343: Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
42196299.343: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
42197299.343: Allocating resources...
42198299.343: Reading resources...
42199299.343: Root Device read_resources bus 0 link: 0
42200299.343: CPU_CLUSTER: 0 read_resources bus 0 link: 0
42201299.343: CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
42202299.343: Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
42203299.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
42204299.343: CBFS: Locating 'cmos_layout.bin'
42205299.343: CBFS: Found @ offset 2b0c0 size e88
42206299.344: Reserving CC6 save segment base: 4038000000 size: 08000000
42207299.344: DOMAIN: 0000 read_resources bus 0 link: 0
42208299.344: PCI: 00:18.0 read_resources bus 0 link: 2
42209299.344: PCI: 00:18.0 read_resources bus 0 link: 2 done
42210299.344: PCI: 00:18.0 read_resources bus 0 link: 3
42211299.344: PCI: 00:18.0 read_resources bus 0 link: 3 done
42212299.344: PCI: 00:18.0 read_resources bus 0 link: 0
42213299.344: PCI: 00:18.0 read_resources bus 0 link: 0 done
42214299.344: PCI: 00:18.0 read_resources bus 0 link: 1
42215299.344: sr5690_read_resource: PCI: 00:00.0
42216299.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
42217299.344: CBFS: Locating 'cmos_layout.bin'
42218299.344: CBFS: Found @ offset 2b0c0 size e88
42219299.345: PCI: 00:02.0 read_resources bus 1 link: 0
42220299.345: PCI: 00:02.0 read_resources bus 1 link: 0 done
42221299.345: PCI: 00:04.0 read_resources bus 2 link: 0
42222299.345: PCI: 00:04.0 read_resources bus 2 link: 0 done
42223299.345: PCI: 00:09.0 read_resources bus 3 link: 0
42224299.345: PCI: 00:09.0 read_resources bus 3 link: 0 done
42225299.345: PCI: 00:0a.0 read_resources bus 4 link: 0
42226299.345: PCI: 00:0a.0 read_resources bus 4 link: 0 done
42227299.345: PCI: 00:0b.0 read_resources bus 5 link: 0
42228299.345: PCI: 00:0b.0 read_resources bus 5 link: 0 done
42229299.345: PCI: 00:0c.0 read_resources bus 6 link: 0
42230299.345: PCI: 00:0c.0 read_resources bus 6 link: 0 done
42231299.345: PCI: 00:0d.0 read_resources bus 7 link: 0
42232299.345: PCI: 00:0d.0 read_resources bus 7 link: 0 done
42233299.345: PCI: 00:14.0 read_resources bus 1 link: 0
42234299.345: I2C: 01:50 missing read_resources
42235299.345: I2C: 01:51 missing read_resources
42236299.345: I2C: 01:52 missing read_resources
42237299.345: I2C: 01:53 missing read_resources
42238299.345: I2C: 01:54 missing read_resources
42239299.345: I2C: 01:55 missing read_resources
42240299.345: I2C: 01:56 missing read_resources
42241299.345: I2C: 01:57 missing read_resources
42242299.345: PCI: 00:14.0 read_resources bus 1 link: 0 done
42243299.346: PCI: 00:14.3 read_resources bus 0 link: 0
42244299.346: PNP: 004e.0 missing read_resources
42245299.346: PCI: 00:14.3 read_resources bus 0 link: 0 done
42246299.346: PCI: 00:14.4 read_resources bus 8 link: 0
42247299.346: PCI: 00:14.4 read_resources bus 8 link: 0 done
42248299.346: PCI: 00:18.0 read_resources bus 0 link: 1 done
42249299.346: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
42250299.346: CBFS: Locating 'cmos_layout.bin'
42251299.346: CBFS: Found @ offset 2b0c0 size e88
42252299.346: PCI: 00:18.4 read_resources bus 0 link: 0
42253299.346: PCI: 00:18.4 read_resources bus 0 link: 0 done
42254299.346: PCI: 00:18.4 read_resources bus 0 link: 1
42255299.346: PCI: 00:18.4 read_resources bus 0 link: 1 done
42256299.346: PCI: 00:18.4 read_resources bus 0 link: 2
42257299.347: PCI: 00:18.4 read_resources bus 0 link: 2 done
42258299.347: PCI: 00:18.4 read_resources bus 0 link: 3
42259299.347: PCI: 00:18.4 read_resources bus 0 link: 3 done
42260299.347: PCI: 00:19.0 read_resources bus 0 link: 3
42261299.347: PCI: 00:19.0 read_resources bus 0 link: 3 done
42262299.347: PCI: 00:19.0 read_resources bus 0 link: 2
42263299.347: PCI: 00:19.0 read_resources bus 0 link: 2 done
42264299.347: PCI: 00:19.0 read_resources bus 0 link: 0
42265299.347: PCI: 00:19.0 read_resources bus 0 link: 0 done
42266299.347: PCI: 00:19.0 read_resources bus 0 link: 1
42267299.347: PCI: 00:19.0 read_resources bus 0 link: 1 done
42268299.347: PCI: 00:19.4 read_resources bus 0 link: 0
42269299.347: PCI: 00:19.4 read_resources bus 0 link: 0 done
42270299.347: PCI: 00:19.4 read_resources bus 0 link: 1
42271299.347: PCI: 00:19.4 read_resources bus 0 link: 1 done
42272299.347: PCI: 00:19.4 read_resources bus 0 link: 2
42273299.347: PCI: 00:19.4 read_resources bus 0 link: 2 done
42274299.347: PCI: 00:19.4 read_resources bus 0 link: 3
42275299.347: PCI: 00:19.4 read_resources bus 0 link: 3 done
42276299.347: PCI: 00:1a.0 read_resources bus 0 link: 3
42277299.347: PCI: 00:1a.0 read_resources bus 0 link: 3 done
42278299.347: PCI: 00:1a.0 read_resources bus 0 link: 2
42279299.347: PCI: 00:1a.0 read_resources bus 0 link: 2 done
42280299.347: PCI: 00:1a.0 read_resources bus 0 link: 0
42281299.347: PCI: 00:1a.0 read_resources bus 0 link: 0 done
42282299.347: PCI: 00:1a.0 read_resources bus 0 link: 1
42283299.347: PCI: 00:1a.0 read_resources bus 0 link: 1 done
42284299.347: PCI: 00:1a.4 read_resources bus 0 link: 0
42285299.347: PCI: 00:1a.4 read_resources bus 0 link: 0 done
42286299.347: PCI: 00:1a.4 read_resources bus 0 link: 1
42287299.347: PCI: 00:1a.4 read_resources bus 0 link: 1 done
42288299.347: PCI: 00:1a.4 read_resources bus 0 link: 2
42289299.347: PCI: 00:1a.4 read_resources bus 0 link: 2 done
42290299.347: PCI: 00:1a.4 read_resources bus 0 link: 3
42291299.347: PCI: 00:1a.4 read_resources bus 0 link: 3 done
42292299.347: PCI: 00:1b.0 read_resources bus 0 link: 3
42293299.347: PCI: 00:1b.0 read_resources bus 0 link: 3 done
42294299.347: PCI: 00:1b.0 read_resources bus 0 link: 2
42295299.347: PCI: 00:1b.0 read_resources bus 0 link: 2 done
42296299.347: PCI: 00:1b.0 read_resources bus 0 link: 0
42297299.347: PCI: 00:1b.0 read_resources bus 0 link: 0 done
42298299.347: PCI: 00:1b.0 read_resources bus 0 link: 1
42299299.347: PCI: 00:1b.0 read_resources bus 0 link: 1 done
42300299.347: PCI: 00:1b.4 read_resources bus 0 link: 0
42301299.347: PCI: 00:1b.4 read_resources bus 0 link: 0 done
42302299.347: PCI: 00:1b.4 read_resources bus 0 link: 1
42303299.347: PCI: 00:1b.4 read_resources bus 0 link: 1 done
42304299.347: PCI: 00:1b.4 read_resources bus 0 link: 2
42305299.347: PCI: 00:1b.4 read_resources bus 0 link: 2 done
42306299.347: PCI: 00:1b.4 read_resources bus 0 link: 3
42307299.347: PCI: 00:1b.4 read_resources bus 0 link: 3 done
42308299.347: DOMAIN: 0000 read_resources bus 0 link: 0 done
42309299.347: Root Device read_resources bus 0 link: 0 done
42310299.347: Done reading resources.
42311299.347: Show resources in subtree (Root Device)...After reading.
42312299.347: Root Device child on link 0 CPU_CLUSTER: 0
42313299.347: CPU_CLUSTER: 0 child on link 0 APIC: 00
42314299.347: APIC: 00
42315299.347: APIC: 01
42316299.347: APIC: 02
42317299.347: APIC: 03
42318299.347: APIC: 04
42319299.347: APIC: 05
42320299.347: APIC: 06
42321299.348: APIC: 07
42322299.348: APIC: 08
42323299.348: APIC: 09
42324299.348: APIC: 0a
42325299.348: APIC: 0b
42326299.348: APIC: 0c
42327299.348: APIC: 0d
42328299.348: APIC: 0e
42329299.348: APIC: 0f
42330299.348: APIC: 20
42331299.348: APIC: 21
42332299.348: APIC: 22
42333299.348: APIC: 23
42334299.348: APIC: 24
42335299.348: APIC: 25
42336299.348: APIC: 26
42337299.348: APIC: 27
42338299.348: APIC: 28
42339299.348: APIC: 29
42340299.348: APIC: 2a
42341299.348: APIC: 2b
42342299.348: APIC: 2c
42343299.348: APIC: 2d
42344299.348: APIC: 2e
42345299.348: APIC: 2f
42346299.348: DOMAIN: 0000 child on link 0 PCI: 00:18.0
42347299.348: DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
42348299.348: DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
42349299.348: DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
42350299.348: DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
42351299.348: DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
42352299.348: PCI: 00:18.0
42353299.348: PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0
42354299.348: PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8
42355299.348: PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8
42356299.348: PCI: 00:00.0
42357299.348: PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
42358299.348: PCI: 00:00.1
42359299.349: PCI: 00:00.2
42360299.349: PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
42361299.349: PCI: 00:02.0
42362299.349: PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42363299.349: PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42364299.349: PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42365299.349: PCI: 00:03.0
42366299.349: PCI: 00:04.0
42367299.349: PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42368299.349: PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42369299.349: PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42370299.349: PCI: 00:05.0
42371299.349: PCI: 00:06.0
42372299.349: PCI: 00:07.0
42373299.349: PCI: 00:08.0
42374299.349: PCI: 00:09.0 child on link 0 PCI: 03:00.0
42375299.349: PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42376299.349: PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42377299.349: PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42378299.349: PCI: 03:00.0
42379299.349: PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
42380299.349: PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
42381299.349: PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
42382299.349: PCI: 00:0a.0 child on link 0 PCI: 04:00.0
42383299.349: PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42384299.349: PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42385299.349: PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42386299.349: PCI: 04:00.0
42387299.349: PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
42388299.349: PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
42389299.349: PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
42390299.349: PCI: 00:0b.0
42391299.349: PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42392299.349: PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42393299.349: PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42394299.349: PCI: 00:0c.0
42395299.349: PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42396299.349: PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42397299.349: PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42398299.349: PCI: 00:0d.0 child on link 0 PCI: 07:00.0
42399299.349: PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
42400299.349: PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
42401299.349: PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42402299.349: PCI: 07:00.0
42403299.349: PCI: 07:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
42404299.349: PCI: 07:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
42405299.349: PCI: 07:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
42406299.349: PCI: 07:00.1
42407299.349: PCI: 07:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
42408299.349: PCI: 07:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
42409299.349: PCI: 07:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
42410299.349: PCI: 00:11.0
42411299.349: PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
42412299.349: PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
42413299.349: PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
42414299.349: PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
42415299.349: PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
42416299.349: PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
42417299.349: PCI: 00:12.0
42418299.349: PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
42419299.349: PCI: 00:12.1
42420299.349: PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
42421299.349: PCI: 00:12.2
42422299.349: PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
42423299.349: PCI: 00:13.0
42424299.349: PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
42425299.349: PCI: 00:13.1
42426299.349: PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
42427299.349: PCI: 00:13.2
42428299.349: PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
42429299.350: PCI: 00:14.0 child on link 0 I2C: 01:50
42430299.350: PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
42431299.350: PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
42432299.350: PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
42433299.350: PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
42434299.350: PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
42435299.350: I2C: 01:50
42436299.350: I2C: 01:51
42437299.350: I2C: 01:52
42438299.350: I2C: 01:53
42439299.350: I2C: 01:54
42440299.350: I2C: 01:55
42441299.350: I2C: 01:56
42442299.350: I2C: 01:57
42443299.350: I2C: 01:2f
42444299.350: PCI: 00:14.1
42445299.350: PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
42446299.350: PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
42447299.350: PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
42448299.350: PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
42449299.350: PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
42450299.350: PCI: 00:14.2
42451299.350: PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
42452299.350: PCI: 00:14.3 child on link 0 PNP: 002e.0
42453299.350: PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
42454299.350: PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
42455299.350: PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
42456299.350: PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
42457299.350: PNP: 002e.0
42458299.350: PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
42459299.350: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
42460299.350: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
42461299.350: PNP: 002e.1
42462299.350: PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
42463299.350: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
42464299.350: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
42465299.350: PNP: 002e.2
42466299.350: PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
42467299.350: PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
42468299.350: PNP: 002e.3
42469299.350: PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
42470299.350: PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
42471299.350: PNP: 002e.5
42472299.350: PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
42473299.350: PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
42474299.350: PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
42475299.350: PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
42476299.350: PNP: 002e.106
42477299.350: PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
42478299.350: PNP: 002e.107
42479299.350: PNP: 002e.207
42480299.350: PNP: 002e.307
42481299.350: PNP: 002e.407
42482299.350: PNP: 002e.8
42483299.350: PNP: 002e.108
42484299.350: PNP: 002e.9
42485299.350: PNP: 002e.109
42486299.351: PNP: 002e.209
42487299.351: PNP: 002e.309
42488299.351: PNP: 002e.a
42489299.351: PNP: 002e.b
42490299.351: PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
42491299.351: PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
42492299.351: PNP: 002e.c
42493299.351: PNP: 002e.d
42494299.351: PNP: 002e.f
42495299.351: PNP: 004e.0
42496299.351: PCI: 00:14.4 child on link 0 PCI: 08:01.0
42497299.351: PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
42498299.351: PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
42499299.351: PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
42500299.351: PCI: 08:01.0
42501299.351: PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
42502299.351: PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
42503299.351: PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
42504299.351: PCI: 08:02.0
42505299.351: PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
42506299.351: PCI: 08:03.0
42507299.351: PCI: 00:14.5
42508299.351: PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
42509299.351: PCI: 00:18.1
42510299.351: PCI: 00:18.2
42511299.351: PCI: 00:18.3
42512299.351: PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
42513299.351: PCI: 00:18.4
42514299.351: PCI: 00:18.5
42515299.351: PCI: 00:19.0
42516299.351: PCI: 00:19.1
42517299.351: PCI: 00:19.2
42518299.351: PCI: 00:19.3
42519299.351: PCI: 00:19.4
42520299.351: PCI: 00:19.5
42521299.351: PCI: 00:1a.0
42522299.351: PCI: 00:1a.1
42523299.351: PCI: 00:1a.2
42524299.351: PCI: 00:1a.3
42525299.351: PCI: 00:1a.4
42526299.352: PCI: 00:1a.5
42527299.352: PCI: 00:1b.0
42528299.352: PCI: 00:1b.1
42529299.352: PCI: 00:1b.2
42530299.352: PCI: 00:1b.3
42531299.352: PCI: 00:1b.4
42532299.352: PCI: 00:1b.5
42533299.352: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
42534299.352: PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
42535299.352: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42536299.352: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
42537299.352: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42538299.352: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
42539299.352: PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42540299.352: PCI: 03:00.0 18 * [0x0 - 0x1f] io
42541299.352: PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
42542299.352: PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42543299.352: PCI: 04:00.0 18 * [0x0 - 0x1f] io
42544299.352: PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
42545299.352: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42546299.352: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
42547299.352: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42548299.352: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
42549299.352: PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
42550299.352: PCI: 07:00.0 18 * [0x0 - 0x1f] io
42551299.352: PCI: 07:00.1 18 * [0x20 - 0x3f] io
42552299.352: PCI: 00:0d.0 io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done
42553299.352: PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
42554299.352: PCI: 08:01.0 18 * [0x0 - 0x7f] io
42555299.352: PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
42556299.352: PCI: 00:09.0 1c * [0x0 - 0xfff] io
42557299.352: PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
42558299.352: PCI: 00:0d.0 1c * [0x2000 - 0x2fff] io
42559299.352: PCI: 00:14.4 1c * [0x3000 - 0x3fff] io
42560299.352: PCI: 00:11.0 20 * [0x4000 - 0x400f] io
42561299.352: PCI: 00:14.1 20 * [0x4010 - 0x401f] io
42562299.352: PCI: 00:11.0 10 * [0x4020 - 0x4027] io
42563299.352: PCI: 00:11.0 18 * [0x4028 - 0x402f] io
42564299.352: PCI: 00:14.1 10 * [0x4030 - 0x4037] io
42565299.352: PCI: 00:14.1 18 * [0x4038 - 0x403f] io
42566299.352: PCI: 00:11.0 14 * [0x4040 - 0x4043] io
42567299.352: PCI: 00:11.0 1c * [0x4044 - 0x4047] io
42568299.352: PCI: 00:14.1 14 * [0x4048 - 0x404b] io
42569299.352: PCI: 00:14.1 1c * [0x404c - 0x404f] io
42570299.352: PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done
42571299.352: PCI: 00:18.0 110d8 * [0x0 - 0x4fff] io
42572299.352: DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
42573299.352: DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
42574299.352: PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
42575299.352: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42576299.352: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
42577299.352: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42578299.352: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
42579299.352: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42580299.352: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
42581299.352: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42582299.352: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
42583299.352: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42584299.352: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
42585299.352: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42586299.352: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
42587299.352: PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
42588299.352: PCI: 07:00.0 10 * [0x0 - 0x7ffff] prefmem
42589299.352: PCI: 07:00.1 10 * [0x80000 - 0xfffff] prefmem
42590299.352: PCI: 07:00.0 20 * [0x100000 - 0x103fff] prefmem
42591299.352: PCI: 07:00.1 20 * [0x104000 - 0x107fff] prefmem
42592299.352: PCI: 00:0d.0 prefmem: base: 108000 size: 200000 align: 20 gran: 20 limit: ffffffffffffffff done
42593299.353: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42594299.352: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
42595299.352: PCI: 00:0d.0 24 * [0x0 - 0x1fffff] prefmem
42596299.352: PCI: 00:00.0 fc * [0x200000 - 0x2000ff] prefmem
42597299.352: PCI: 00:18.0 prefmem: base: 200100 size: 300000 align: 20 gran: 20 limit: ffffffff done
42598299.352: PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
42599299.353: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42600299.353: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
42601299.353: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42602299.353: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
42603299.353: PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42604299.353: PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem
42605299.353: PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem
42606299.353: PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
42607299.353: PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42608299.353: PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem
42609299.353: PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem
42610299.353: PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
42611299.353: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42612299.353: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
42613299.353: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42614299.353: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
42615299.353: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42616299.353: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
42617299.353: PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
42618299.353: PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem
42619299.353: PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem
42620299.353: PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem
42621299.353: PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done
42622299.353: PCI: 00:14.4 20 * [0x0 - 0x8fffff] mem
42623299.353: PCI: 00:09.0 20 * [0x900000 - 0x9fffff] mem
42624299.353: PCI: 00:0a.0 20 * [0xa00000 - 0xafffff] mem
42625299.353: PCI: 00:00.2 44 * [0xb00000 - 0xb03fff] mem
42626299.353: PCI: 00:14.2 10 * [0xb04000 - 0xb07fff] mem
42627299.353: PCI: 00:12.0 10 * [0xb08000 - 0xb08fff] mem
42628299.353: PCI: 00:12.1 10 * [0xb09000 - 0xb09fff] mem
42629299.353: PCI: 00:13.0 10 * [0xb0a000 - 0xb0afff] mem
42630299.353: PCI: 00:13.1 10 * [0xb0b000 - 0xb0bfff] mem
42631299.353: PCI: 00:14.5 10 * [0xb0c000 - 0xb0cfff] mem
42632299.353: PCI: 00:11.0 24 * [0xb0d000 - 0xb0d3ff] mem
42633299.353: PCI: 00:12.2 10 * [0xb0e000 - 0xb0e0ff] mem
42634299.353: PCI: 00:13.2 10 * [0xb0f000 - 0xb0f0ff] mem
42635299.353: PCI: 00:14.3 a0 * [0xb10000 - 0xb10000] mem
42636299.353: PCI: 00:18.0 mem: base: b10001 size: c00000 align: 23 gran: 20 limit: ffffffff done
42637299.353: PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem
42638299.353: PCI: 00:18.0 110b8 * [0x4000000 - 0x4bfffff] mem
42639299.353: PCI: 00:18.0 110b0 * [0x4c00000 - 0x4efffff] prefmem
42640299.353: DOMAIN: 0000 mem: base: 4f00000 size: 4f00000 align: 26 gran: 0 limit: ffffffff done
42641299.353: avoid_fixed_resources: DOMAIN: 0000
42642299.353: avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
42643299.353: avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
42644299.353: constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
42645299.353: constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
42646299.353: constrain_resources: DOMAIN: 0000 08 base 4038000000 limit 403fffffff mem (fixed)
42647299.353: constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
42648299.353: constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed)
42649299.353: constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
42650299.353: constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
42651299.353: constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
42652299.353: constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
42653299.353: avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
42654299.353: avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff
42655299.353: Setting resources...
42656299.353: DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
42657299.353: PCI: 00:18.0 110d8 * [0x1000 - 0x5fff] io
42658299.353: DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
42659299.353: PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
42660299.353: PCI: 00:09.0 1c * [0x1000 - 0x1fff] io
42661299.353: PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
42662299.353: PCI: 00:0d.0 1c * [0x3000 - 0x3fff] io
42663299.353: PCI: 00:14.4 1c * [0x4000 - 0x4fff] io
42664299.353: PCI: 00:11.0 20 * [0x5000 - 0x500f] io
42665299.353: PCI: 00:14.1 20 * [0x5010 - 0x501f] io
42666299.353: PCI: 00:11.0 10 * [0x5020 - 0x5027] io
42667299.353: PCI: 00:11.0 18 * [0x5028 - 0x502f] io
42668299.353: PCI: 00:14.1 10 * [0x5030 - 0x5037] io
42669299.353: PCI: 00:14.1 18 * [0x5038 - 0x503f] io
42670299.353: PCI: 00:11.0 14 * [0x5040 - 0x5043] io
42671299.353: PCI: 00:11.0 1c * [0x5044 - 0x5047] io
42672299.353: PCI: 00:14.1 14 * [0x5048 - 0x504b] io
42673299.353: PCI: 00:14.1 1c * [0x504c - 0x504f] io
42674299.353: PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done
42675299.353: PCI: 00:02.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
42676299.353: PCI: 00:02.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
42677299.353: PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
42678299.353: PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
42679299.353: PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
42680299.353: PCI: 03:00.0 18 * [0x1000 - 0x101f] io
42681299.353: PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
42682299.353: PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
42683299.353: PCI: 04:00.0 18 * [0x2000 - 0x201f] io
42684299.353: PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
42685299.353: PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
42686299.353: PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
42687299.353: PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
42688299.353: PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
42689299.353: PCI: 00:0d.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
42690299.353: PCI: 07:00.0 18 * [0x3000 - 0x301f] io
42691299.353: PCI: 07:00.1 18 * [0x3020 - 0x303f] io
42692299.353: PCI: 00:0d.0 io: next_base: 3040 size: 1000 align: 12 gran: 12 done
42693299.353: PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff
42694299.353: PCI: 08:01.0 18 * [0x4000 - 0x407f] io
42695299.353: PCI: 00:14.4 io: next_base: 4080 size: 1000 align: 12 gran: 12 done
42696299.353: DOMAIN: 0000 mem: base:f8000000 size:4f00000 align:26 gran:0 limit:ffffffff
42697299.353: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem
42698299.353: PCI: 00:18.0 110b8 * [0xfc000000 - 0xfcbfffff] mem
42699299.354: PCI: 00:18.0 110b0 * [0xfcc00000 - 0xfcefffff] prefmem
42700299.354: DOMAIN: 0000 mem: next_base: fcf00000 size: 4f00000 align: 26 gran: 0 done
42701299.353: PCI: 00:18.0 prefmem: base:fcc00000 size:300000 align:20 gran:20 limit:fcefffff
42702299.354: PCI: 00:0d.0 24 * [0xfcc00000 - 0xfcdfffff] prefmem
42703299.354: PCI: 00:00.0 fc * [0xfce00000 - 0xfce000ff] prefmem
42704299.354: PCI: 00:18.0 prefmem: next_base: fce00100 size: 300000 align: 20 gran: 20 done
42705299.354: PCI: 00:02.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42706299.354: PCI: 00:02.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42707299.354: PCI: 00:04.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42708299.354: PCI: 00:04.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42709299.354: PCI: 00:09.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42710299.354: PCI: 00:09.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42711299.354: PCI: 00:0a.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42712299.354: PCI: 00:0a.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42713299.354: PCI: 00:0b.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42714299.354: PCI: 00:0b.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42715299.354: PCI: 00:0c.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42716299.354: PCI: 00:0c.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42717299.354: PCI: 00:0d.0 prefmem: base:fcc00000 size:200000 align:20 gran:20 limit:fcdfffff
42718299.354: PCI: 07:00.0 10 * [0xfcc00000 - 0xfcc7ffff] prefmem
42719299.354: PCI: 07:00.1 10 * [0xfcc80000 - 0xfccfffff] prefmem
42720299.354: PCI: 07:00.0 20 * [0xfcd00000 - 0xfcd03fff] prefmem
42721299.354: PCI: 07:00.1 20 * [0xfcd04000 - 0xfcd07fff] prefmem
42722299.354: PCI: 00:0d.0 prefmem: next_base: fcd08000 size: 200000 align: 20 gran: 20 done
42723299.354: PCI: 00:14.4 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
42724299.354: PCI: 00:14.4 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
42725299.354: PCI: 00:18.0 mem: base:fc000000 size:c00000 align:23 gran:20 limit:fcbfffff
42726299.354: PCI: 00:14.4 20 * [0xfc000000 - 0xfc8fffff] mem
42727299.354: PCI: 00:09.0 20 * [0xfc900000 - 0xfc9fffff] mem
42728299.354: PCI: 00:0a.0 20 * [0xfca00000 - 0xfcafffff] mem
42729299.354: PCI: 00:00.2 44 * [0xfcb00000 - 0xfcb03fff] mem
42730299.354: PCI: 00:14.2 10 * [0xfcb04000 - 0xfcb07fff] mem
42731299.354: PCI: 00:12.0 10 * [0xfcb08000 - 0xfcb08fff] mem
42732299.354: PCI: 00:12.1 10 * [0xfcb09000 - 0xfcb09fff] mem
42733299.354: PCI: 00:13.0 10 * [0xfcb0a000 - 0xfcb0afff] mem
42734299.354: PCI: 00:13.1 10 * [0xfcb0b000 - 0xfcb0bfff] mem
42735299.354: PCI: 00:14.5 10 * [0xfcb0c000 - 0xfcb0cfff] mem
42736299.354: PCI: 00:11.0 24 * [0xfcb0d000 - 0xfcb0d3ff] mem
42737299.354: PCI: 00:12.2 10 * [0xfcb0e000 - 0xfcb0e0ff] mem
42738299.354: PCI: 00:13.2 10 * [0xfcb0f000 - 0xfcb0f0ff] mem
42739299.354: PCI: 00:14.3 a0 * [0xfcb10000 - 0xfcb10000] mem
42740299.354: PCI: 00:18.0 mem: next_base: fcb10001 size: c00000 align: 23 gran: 20 done
42741299.354: PCI: 00:02.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
42742299.354: PCI: 00:02.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
42743299.354: PCI: 00:04.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
42744299.354: PCI: 00:04.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
42745299.354: PCI: 00:09.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff
42746299.354: PCI: 03:00.0 10 * [0xfc900000 - 0xfc91ffff] mem
42747299.354: PCI: 03:00.0 1c * [0xfc920000 - 0xfc923fff] mem
42748299.354: PCI: 00:09.0 mem: next_base: fc924000 size: 100000 align: 20 gran: 20 done
42749299.354: PCI: 00:0a.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff
42750299.354: PCI: 04:00.0 10 * [0xfca00000 - 0xfca1ffff] mem
42751299.354: PCI: 04:00.0 1c * [0xfca20000 - 0xfca23fff] mem
42752299.354: PCI: 00:0a.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done
42753299.354: PCI: 00:0b.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
42754299.354: PCI: 00:0b.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
42755299.354: PCI: 00:0c.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
42756299.354: PCI: 00:0c.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
42757299.354: PCI: 00:0d.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
42758299.354: PCI: 00:0d.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
42759299.354: PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff
42760299.354: PCI: 08:01.0 10 * [0xfc000000 - 0xfc7fffff] mem
42761299.354: PCI: 08:01.0 14 * [0xfc800000 - 0xfc81ffff] mem
42762299.354: PCI: 08:02.0 10 * [0xfc820000 - 0xfc820fff] mem
42763299.354: PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done
42764299.354: Root Device assign_resources, bus 0 link: 0
42765299.354: 0: mmio_basek=00300000, basek=00400000, limitk=04100000
42766299.354: 1: mmio_basek=00300000, basek=04100000, limitk=08100000
42767299.354: 2: mmio_basek=00300000, basek=08100000, limitk=0c100000
42768299.354: 3: mmio_basek=00300000, basek=0c100000, limitk=10100000
42769299.354: DOMAIN: 0000 assign_resources, bus 0 link: 0
42770299.354: VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
42771299.354: PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
42772299.354: PCI: 00:18.0 110b0 <- [0x00fcc00000 - 0x00fcefffff] size 0x00300000 gran 0x14 prefmem <node 0 link 1>
42773299.354: PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fcbfffff] size 0x00c00000 gran 0x14 mem <node 0 link 1>
42774299.354: PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1>
42775299.354: PCI: 00:18.0 assign_resources, bus 0 link: 1
42776299.354: PCI: 00:00.0 sr5690_set_resources
42777299.354: sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
42778299.354: PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig>
42779299.354: sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90
42780299.354: PCI: 00:00.0 fc <- [0x00fce00000 - 0x00fce000ff] size 0x00000100 gran 0x08 prefmem
42781299.354: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
42782299.354: CBFS: Locating 'cmos_layout.bin'
42783299.354: CBFS: Found @ offset 2b0c0 size e88
42784299.355: PCI: 00:00.2 44 <- [0x00fcb00000 - 0x00fcb03fff] size 0x00004000 gran 0x0e mem
42785299.355: PCI: 00:02.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 01 io
42786299.355: PCI: 00:02.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 01 prefmem
42787299.355: PCI: 00:02.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 01 mem
42788299.355: PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
42789299.355: PCI: 00:04.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 02 prefmem
42790299.355: PCI: 00:04.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 02 mem
42791299.355: PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
42792299.355: PCI: 00:09.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 03 prefmem
42793299.355: PCI: 00:09.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 03 mem
42794299.355: PCI: 00:09.0 assign_resources, bus 3 link: 0
42795299.355: PCI: 03:00.0 10 <- [0x00fc900000 - 0x00fc91ffff] size 0x00020000 gran 0x11 mem
42796299.355: PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
42797299.355: PCI: 03:00.0 1c <- [0x00fc920000 - 0x00fc923fff] size 0x00004000 gran 0x0e mem
42798299.355: PCI: 00:09.0 assign_resources, bus 3 link: 0
42799299.355: PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
42800299.355: PCI: 00:0a.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 04 prefmem
42801299.355: PCI: 00:0a.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 04 mem
42802299.355: PCI: 00:0a.0 assign_resources, bus 4 link: 0
42803299.355: PCI: 04:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem
42804299.355: PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
42805299.355: PCI: 04:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem
42806299.355: PCI: 00:0a.0 assign_resources, bus 4 link: 0
42807299.355: PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io
42808299.355: PCI: 00:0b.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 05 prefmem
42809299.355: PCI: 00:0b.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 05 mem
42810299.355: PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io
42811299.355: PCI: 00:0c.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 06 prefmem
42812299.355: PCI: 00:0c.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 06 mem
42813299.355: PCI: 00:0d.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 07 io
42814299.355: PCI: 00:0d.0 24 <- [0x00fcc00000 - 0x00fcdfffff] size 0x00200000 gran 0x14 bus 07 prefmem
42815299.355: PCI: 00:0d.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 07 mem
42816299.355: PCI: 00:0d.0 assign_resources, bus 7 link: 0
42817299.355: PCI: 07:00.0 10 <- [0x00fcc00000 - 0x00fcc7ffff] size 0x00080000 gran 0x13 prefmem64
42818299.355: PCI: 07:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
42819299.355: PCI: 07:00.0 20 <- [0x00fcd00000 - 0x00fcd03fff] size 0x00004000 gran 0x0e prefmem64
42820299.355: PCI: 07:00.1 10 <- [0x00fcc80000 - 0x00fccfffff] size 0x00080000 gran 0x13 prefmem64
42821299.355: PCI: 07:00.1 18 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io
42822299.355: PCI: 07:00.1 20 <- [0x00fcd04000 - 0x00fcd07fff] size 0x00004000 gran 0x0e prefmem64
42823299.355: PCI: 00:0d.0 assign_resources, bus 7 link: 0
42824299.355: PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io
42825299.355: PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io
42826299.355: PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io
42827299.355: PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io
42828299.355: PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io
42829299.355: PCI: 00:11.0 24 <- [0x00fcb0d000 - 0x00fcb0d3ff] size 0x00000400 gran 0x0a mem
42830299.355: PCI: 00:12.0 10 <- [0x00fcb08000 - 0x00fcb08fff] size 0x00001000 gran 0x0c mem
42831299.355: PCI: 00:12.1 10 <- [0x00fcb09000 - 0x00fcb09fff] size 0x00001000 gran 0x0c mem
42832299.355: PCI: 00:12.2 10 <- [0x00fcb0e000 - 0x00fcb0e0ff] size 0x00000100 gran 0x08 mem
42833299.355: PCI: 00:13.0 10 <- [0x00fcb0a000 - 0x00fcb0afff] size 0x00001000 gran 0x0c mem
42834299.355: PCI: 00:13.1 10 <- [0x00fcb0b000 - 0x00fcb0bfff] size 0x00001000 gran 0x0c mem
42835299.355: PCI: 00:13.2 10 <- [0x00fcb0f000 - 0x00fcb0f0ff] size 0x00000100 gran 0x08 mem
42836299.355: PCI: 00:14.0 assign_resources, bus 1 link: 0
42837299.355: PCI: 00:14.0 assign_resources, bus 1 link: 0
42838299.355: PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io
42839299.355: PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io
42840299.355: PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io
42841299.355: PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io
42842299.355: PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io
42843299.355: PCI: 00:14.2 10 <- [0x00fcb04000 - 0x00fcb07fff] size 0x00004000 gran 0x0e mem64
42844299.355: PCI: 00:14.3 a0 <- [0x00fcb10000 - 0x00fcb10000] size 0x00000001 gran 0x00 mem
42845299.355: PCI: 00:14.3 assign_resources, bus 0 link: 0
42846299.355: PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
42847299.355: PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
42848299.355: PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
42849299.355: PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
42850299.355: PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
42851299.355: PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
42852299.356: PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
42853299.356: PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
42854299.356: PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
42855299.356: ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
42856299.356: PCI: 00:14.3 assign_resources, bus 0 link: 0
42857299.356: PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io
42858299.356: PCI: 00:14.4 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 08 prefmem
42859299.356: PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem
42860299.356: PCI: 00:14.4 assign_resources, bus 8 link: 0
42861299.356: PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem
42862299.356: PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem
42863299.356: PCI: 08:01.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io
42864299.356: PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem
42865299.356: PCI: 00:14.4 assign_resources, bus 8 link: 0
42866299.356: PCI: 00:14.5 10 <- [0x00fcb0c000 - 0x00fcb0cfff] size 0x00001000 gran 0x0c mem
42867299.356: PCI: 00:18.0 assign_resources, bus 0 link: 1
42868299.356: PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
42869299.356: PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
42870299.356: PCI: 00:1a.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
42871299.356: PCI: 00:1b.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
42872299.356: DOMAIN: 0000 assign_resources, bus 0 link: 0
42873299.356: Root Device assign_resources, bus 0 link: 0
42874299.356: Done setting resources.
42875299.356: Show resources in subtree (Root Device)...After assigning values.
42876299.356: Root Device child on link 0 CPU_CLUSTER: 0
42877299.356: CPU_CLUSTER: 0 child on link 0 APIC: 00
42878299.356: APIC: 00
42879299.356: APIC: 01
42880299.356: APIC: 02
42881299.356: APIC: 03
42882299.356: APIC: 04
42883299.356: APIC: 05
42884299.356: APIC: 06
42885299.356: APIC: 07
42886299.356: APIC: 08
42887299.356: APIC: 09
42888299.356: APIC: 0a
42889299.356: APIC: 0b
42890299.356: APIC: 0c
42891299.356: APIC: 0d
42892299.356: APIC: 0e
42893299.356: APIC: 0f
42894299.356: APIC: 20
42895299.357: APIC: 21
42896299.357: APIC: 22
42897299.357: APIC: 23
42898299.357: APIC: 24
42899299.357: APIC: 25
42900299.357: APIC: 26
42901299.357: APIC: 27
42902299.357: APIC: 28
42903299.357: APIC: 29
42904299.357: APIC: 2a
42905299.357: APIC: 2b
42906299.357: APIC: 2c
42907299.357: APIC: 2d
42908299.357: APIC: 2e
42909299.357: APIC: 2f
42910299.357: DOMAIN: 0000 child on link 0 PCI: 00:18.0
42911299.357: DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
42912299.357: DOMAIN: 0000 resource base f8000000 size 4f00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100
42913299.357: DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
42914299.357: DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
42915299.357: DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
42916299.357: DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
42917299.357: DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
42918299.357: DOMAIN: 0000 resource base 100000000 size f40000000 align 0 gran 0 limit 0 flags e0004200 index 30
42919299.357: DOMAIN: 0000 resource base 1040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 41
42920299.357: DOMAIN: 0000 resource base 2040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 52
42921299.357: DOMAIN: 0000 resource base 3040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 63
42922299.357: PCI: 00:18.0
42923299.357: PCI: 00:18.0 resource base fcc00000 size 300000 align 20 gran 20 limit fcefffff flags 60081200 index 110b0
42924299.357: PCI: 00:18.0 resource base fc000000 size c00000 align 23 gran 20 limit fcbfffff flags 60080200 index 110b8
42925299.357: PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8
42926299.357: PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8
42927299.357: PCI: 00:00.0
42928299.357: PCI: 00:00.0 resource base fce00000 size 100 align 12 gran 8 limit fce000ff flags 60001200 index fc
42929299.357: PCI: 00:00.1
42930299.357: PCI: 00:00.2
42931299.357: PCI: 00:00.2 resource base fcb00000 size 4000 align 14 gran 14 limit fcb03fff flags 70000200 index 44
42932299.357: PCI: 00:02.0
42933299.357: PCI: 00:02.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
42934299.357: PCI: 00:02.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
42935299.357: PCI: 00:02.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
42936299.357: PCI: 00:03.0
42937299.357: PCI: 00:04.0
42938299.357: PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
42939299.357: PCI: 00:04.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
42940299.357: PCI: 00:04.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
42941299.357: PCI: 00:05.0
42942299.357: PCI: 00:06.0
42943299.357: PCI: 00:07.0
42944299.357: PCI: 00:08.0
42945299.357: PCI: 00:09.0 child on link 0 PCI: 03:00.0
42946299.358: PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
42947299.358: PCI: 00:09.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
42948299.358: PCI: 00:09.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20
42949299.358: PCI: 03:00.0
42950299.358: PCI: 03:00.0 resource base fc900000 size 20000 align 17 gran 17 limit fc91ffff flags 60000200 index 10
42951299.358: PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
42952299.358: PCI: 03:00.0 resource base fc920000 size 4000 align 14 gran 14 limit fc923fff flags 60000200 index 1c
42953299.358: PCI: 00:0a.0 child on link 0 PCI: 04:00.0
42954299.358: PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
42955299.358: PCI: 00:0a.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
42956299.358: PCI: 00:0a.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20
42957299.358: PCI: 04:00.0
42958299.358: PCI: 04:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10
42959299.358: PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
42960299.358: PCI: 04:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c
42961299.358: PCI: 00:0b.0
42962299.358: PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
42963299.358: PCI: 00:0b.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
42964299.358: PCI: 00:0b.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
42965299.358: PCI: 00:0c.0
42966299.358: PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
42967299.358: PCI: 00:0c.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
42968299.358: PCI: 00:0c.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
42969299.358: PCI: 00:0d.0 child on link 0 PCI: 07:00.0
42970299.358: PCI: 00:0d.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
42971299.358: PCI: 00:0d.0 resource base fcc00000 size 200000 align 20 gran 20 limit fcdfffff flags 60081202 index 24
42972299.358: PCI: 00:0d.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
42973299.358: PCI: 07:00.0
42974299.358: PCI: 07:00.0 resource base fcc00000 size 80000 align 19 gran 19 limit fcc7ffff flags 60001201 index 10
42975299.358: PCI: 07:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18
42976299.358: PCI: 07:00.0 resource base fcd00000 size 4000 align 14 gran 14 limit fcd03fff flags 60001201 index 20
42977299.358: PCI: 07:00.1
42978299.358: PCI: 07:00.1 resource base fcc80000 size 80000 align 19 gran 19 limit fccfffff flags 60001201 index 10
42979299.358: PCI: 07:00.1 resource base 3020 size 20 align 5 gran 5 limit 303f flags 60000100 index 18
42980299.358: PCI: 07:00.1 resource base fcd04000 size 4000 align 14 gran 14 limit fcd07fff flags 60001201 index 20
42981299.358: PCI: 00:11.0
42982299.358: PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10
42983299.358: PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14
42984299.358: PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18
42985299.358: PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c
42986299.358: PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20
42987299.358: PCI: 00:11.0 resource base fcb0d000 size 400 align 12 gran 10 limit fcb0d3ff flags 60000200 index 24
42988299.358: PCI: 00:12.0
42989299.358: PCI: 00:12.0 resource base fcb08000 size 1000 align 12 gran 12 limit fcb08fff flags 60000200 index 10
42990299.358: PCI: 00:12.1
42991299.358: PCI: 00:12.1 resource base fcb09000 size 1000 align 12 gran 12 limit fcb09fff flags 60000200 index 10
42992299.358: PCI: 00:12.2
42993299.358: PCI: 00:12.2 resource base fcb0e000 size 100 align 12 gran 8 limit fcb0e0ff flags 60000200 index 10
42994299.358: PCI: 00:13.0
42995299.358: PCI: 00:13.0 resource base fcb0a000 size 1000 align 12 gran 12 limit fcb0afff flags 60000200 index 10
42996299.358: PCI: 00:13.1
42997299.358: PCI: 00:13.1 resource base fcb0b000 size 1000 align 12 gran 12 limit fcb0bfff flags 60000200 index 10
42998299.358: PCI: 00:13.2
42999299.358: PCI: 00:13.2 resource base fcb0f000 size 100 align 12 gran 8 limit fcb0f0ff flags 60000200 index 10
43000299.358: PCI: 00:14.0 child on link 0 I2C: 01:50
43001299.358: PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
43002299.358: PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
43003299.358: PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
43004299.358: PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
43005299.358: PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
43006299.358: I2C: 01:50
43007299.358: I2C: 01:51
43008299.358: I2C: 01:52
43009299.358: I2C: 01:53
43010299.358: I2C: 01:54
43011299.358: I2C: 01:55
43012299.358: I2C: 01:56
43013299.358: I2C: 01:57
43014299.358: I2C: 01:2f
43015299.358: PCI: 00:14.1
43016299.359: PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10
43017299.359: PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14
43018299.359: PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18
43019299.359: PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c
43020299.359: PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20
43021299.359: PCI: 00:14.2
43022299.359: PCI: 00:14.2 resource base fcb04000 size 4000 align 14 gran 14 limit fcb07fff flags 60000201 index 10
43023299.359: PCI: 00:14.3 child on link 0 PNP: 002e.0
43024299.359: PCI: 00:14.3 resource base fcb10000 size 1 align 12 gran 0 limit fcb10000 flags 60000200 index a0
43025299.359: PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
43026299.359: PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
43027299.359: PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
43028299.359: PNP: 002e.0
43029299.359: PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
43030299.359: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
43031299.359: PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
43032299.359: PNP: 002e.1
43033299.359: PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
43034299.359: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
43035299.359: PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
43036299.359: PNP: 002e.2
43037299.359: PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
43038299.359: PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
43039299.359: PNP: 002e.3
43040299.359: PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
43041299.359: PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
43042299.359: PNP: 002e.5
43043299.359: PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
43044299.359: PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
43045299.359: PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
43046299.359: PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
43047299.359: PNP: 002e.106
43048299.359: PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
43049299.359: PNP: 002e.107
43050299.359: PNP: 002e.207
43051299.359: PNP: 002e.307
43052299.359: PNP: 002e.407
43053299.359: PNP: 002e.8
43054299.359: PNP: 002e.108
43055299.359: PNP: 002e.9
43056299.359: PNP: 002e.109
43057299.359: PNP: 002e.209
43058299.359: PNP: 002e.309
43059299.359: PNP: 002e.a
43060299.359: PNP: 002e.b
43061299.359: PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
43062299.359: PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
43063299.359: PNP: 002e.c
43064299.359: PNP: 002e.d
43065299.359: PNP: 002e.f
43066299.359: PNP: 004e.0
43067299.359: PCI: 00:14.4 child on link 0 PCI: 08:01.0
43068299.359: PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
43069299.359: PCI: 00:14.4 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
43070299.359: PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20
43071299.359: PCI: 08:01.0
43072299.360: PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10
43073299.359: PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14
43074299.359: PCI: 08:01.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18
43075299.360: PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
43076299.360: PCI: 08:02.0
43077299.360: PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10
43078299.360: PCI: 08:03.0
43079299.360: PCI: 00:14.5
43080299.360: PCI: 00:14.5 resource base fcb0c000 size 1000 align 12 gran 12 limit fcb0cfff flags 60000200 index 10
43081299.360: PCI: 00:18.1
43082299.360: PCI: 00:18.2
43083299.360: PCI: 00:18.3
43084299.360: PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94
43085299.360: PCI: 00:18.4
43086299.360: PCI: 00:18.5
43087299.360: PCI: 00:19.0
43088299.360: PCI: 00:19.1
43089299.360: PCI: 00:19.2
43090299.360: PCI: 00:19.3
43091299.360: PCI: 00:19.4
43092299.360: PCI: 00:19.5
43093299.360: PCI: 00:1a.0
43094299.360: PCI: 00:1a.1
43095299.360: PCI: 00:1a.2
43096299.360: PCI: 00:1a.3
43097299.360: PCI: 00:1a.4
43098299.360: PCI: 00:1a.5
43099299.360: PCI: 00:1b.0
43100299.360: PCI: 00:1b.1
43101299.360: PCI: 00:1b.2
43102299.360: PCI: 00:1b.3
43103299.360: PCI: 00:1b.4
43104299.360: PCI: 00:1b.5
43105299.360: Done allocating resources.
43106299.360: BS: BS_DEV_RESOURCES times (us): entry 0 run 3292465 exit 0
43107299.360: Enabling resources...
43108299.360: PCI: 00:18.0 cmd <- 00
43109299.360: PCI: 00:18.1 subsystem <- 1043/8163
43110299.360: PCI: 00:18.1 cmd <- 00
43111299.360: PCI: 00:18.2 subsystem <- 1043/8163
43112299.360: PCI: 00:18.2 cmd <- 00
43113299.361: PCI: 00:18.3 cmd <- 00
43114299.361: PCI: 00:18.4 cmd <- 00
43115299.361: PCI: 00:18.5 cmd <- 00
43116299.361: PCI: 00:19.0 cmd <- 00
43117299.361: PCI: 00:19.1 subsystem <- 1043/8163
43118299.361: PCI: 00:19.1 cmd <- 00
43119299.361: PCI: 00:19.2 subsystem <- 1043/8163
43120299.361: PCI: 00:19.2 cmd <- 00
43121299.361: PCI: 00:19.3 cmd <- 00
43122299.361: PCI: 00:19.4 cmd <- 00
43123299.361: PCI: 00:19.5 cmd <- 00
43124299.361: PCI: 00:1a.0 cmd <- 00
43125299.361: PCI: 00:1a.1 subsystem <- 1043/8163
43126299.361: PCI: 00:1a.1 cmd <- 00
43127299.361: PCI: 00:1a.2 subsystem <- 1043/8163
43128299.361: PCI: 00:1a.2 cmd <- 00
43129299.361: PCI: 00:1a.3 cmd <- 00
43130299.361: PCI: 00:1a.4 cmd <- 00
43131299.361: PCI: 00:1a.5 cmd <- 00
43132299.361: PCI: 00:1b.0 cmd <- 00
43133299.361: PCI: 00:1b.1 subsystem <- 1043/8163
43134299.361: PCI: 00:1b.1 cmd <- 00
43135299.361: PCI: 00:1b.2 subsystem <- 1043/8163
43136299.361: PCI: 00:1b.2 cmd <- 00
43137299.361: PCI: 00:1b.3 cmd <- 00
43138299.361: PCI: 00:1b.4 cmd <- 00
43139299.361: PCI: 00:1b.5 cmd <- 00
43140299.361: PCI: 00:00.0 subsystem <- 1043/8163
43141299.361: PCI: 00:00.0 cmd <- 02
43142299.361: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
43143299.361: CBFS: Locating 'cmos_layout.bin'
43144299.361: CBFS: Found @ offset 2b0c0 size e88
43145299.362: Initializing IOMMU
43146299.362: PCI: 00:02.0 bridge ctrl <- 0003
43147299.362: PCI: 00:02.0 cmd <- 00
43148299.362: PCI: 00:04.0 bridge ctrl <- 0003
43149299.362: PCI: 00:04.0 cmd <- 00
43150299.362: PCI: 00:09.0 bridge ctrl <- 0003
43151299.362: PCI: 00:09.0 cmd <- 07
43152299.362: PCI: 00:0a.0 bridge ctrl <- 0003
43153299.362: PCI: 00:0a.0 cmd <- 07
43154299.362: PCI: 00:0b.0 bridge ctrl <- 0003
43155299.362: PCI: 00:0b.0 cmd <- 00
43156299.362: PCI: 00:0c.0 bridge ctrl <- 0003
43157299.362: PCI: 00:0c.0 cmd <- 00
43158299.362: PCI: 00:0d.0 bridge ctrl <- 0003
43159299.362: PCI: 00:0d.0 cmd <- 07
43160299.362: PCI: 00:11.0 subsystem <- 1043/8163
43161299.362: PCI: 00:11.0 cmd <- 03
43162299.362: PCI: 00:12.0 subsystem <- 1043/8163
43163299.362: PCI: 00:12.0 cmd <- 02
43164299.362: PCI: 00:12.1 subsystem <- 1043/8163
43165299.362: PCI: 00:12.1 cmd <- 02
43166299.362: PCI: 00:12.2 subsystem <- 1043/8163
43167299.362: PCI: 00:12.2 cmd <- 02
43168299.362: PCI: 00:13.0 subsystem <- 1043/8163
43169299.362: PCI: 00:13.0 cmd <- 02
43170299.362: PCI: 00:13.1 subsystem <- 1043/8163
43171299.362: PCI: 00:13.1 cmd <- 02
43172299.362: PCI: 00:13.2 subsystem <- 1043/8163
43173299.362: PCI: 00:13.2 cmd <- 02
43174299.362: PCI: 00:14.0 subsystem <- 1043/8163
43175299.362: PCI: 00:14.0 cmd <- 403
43176299.362: PCI: 00:14.1 subsystem <- 1043/8163
43177299.362: PCI: 00:14.1 cmd <- 01
43178299.362: PCI: 00:14.2 subsystem <- 1043/8163
43179299.362: PCI: 00:14.2 cmd <- 02
43180299.362: PCI: 00:14.3 subsystem <- 1043/8163
43181299.362: PCI: 00:14.3 cmd <- 0f
43182299.362: sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
43183299.362: sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
43184299.362: sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
43185299.362: sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
43186299.362: sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
43187299.362: PCI: 00:14.4 bridge ctrl <- 000b
43188299.362: PCI: 00:14.4 cmd <- 07
43189299.362: PCI: 00:14.5 subsystem <- 1043/8163
43190299.362: PCI: 00:14.5 cmd <- 02
43191299.362: PCI: 03:00.0 cmd <- 03
43192299.362: PCI: 04:00.0 cmd <- 03
43193299.362: PCI: 07:00.0 cmd <- 03
43194299.362: PCI: 07:00.1 cmd <- 03
43195299.362: PCI: 08:01.0 cmd <- 03
43196299.362: PCI: 08:02.0 subsystem <- 1043/8163
43197299.362: PCI: 08:02.0 cmd <- 02
43198299.362: done.
43199299.362: BS: BS_DEV_ENABLE times (us): entry 0 run 178711 exit 0
43200299.362: Initializing devices...
43201299.362: Root Device init ...
43202299.362: Root Device init finished in 1398 usecs
43203299.362: CPU_CLUSTER: 0 init ...
43204299.363: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
43205299.363: CBFS: Locating 'cmos_layout.bin'
43206299.363: CBFS: Found @ offset 2b0c0 size e88
43207299.363: Enabling probe filter
43208299.368: Enabling ATM mode
43209299.368: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
43210299.368: CBFS: Locating 'cmos_layout.bin'
43211299.368: CBFS: Found @ offset 2b0c0 size e88
43212299.369: start_eip=0x00001000, code_size=0x00000031
43213299.369: CPU1: stack_base 00150000, stack_end 00150ff8
43214299.369: Asserting INIT.
43215299.369: Waiting for send to finish...
43216299.369: +Deasserting INIT.
43217299.369: Waiting for send to finish...
43218299.369: +#startup loops: 1.
43219299.369: Sending STARTUP #1 to 1.
43220299.369: After apic_write.
43221299.369: Initializing CPU #1
43222299.369: Startup point 1.
43223299.369: Waiting for send to finish...
43224299.369: +CPU: vendor AMD device 600f12
43225299.369: After Startup.
43226299.369: CPU: family 15, model 01, stepping 02
43227299.369: CPU2: stack_base 0014f000, stack_end 0014fff8
43228299.370: nodeid = 00, coreid = 01
43229299.369: Asserting INIT.
43230299.370: Enabling cache
43231299.370: Waiting for send to finish...
43232299.370: +Deasserting INIT.
43233299.370: Waiting for send to finish...
43234299.370: +#startup loops: 1.
43235299.370: Sending STARTUP #1 to 2.
43236299.370: After apic_write.
43237299.370: Initializing CPU #2
43238299.370: Startup point 1.
43239299.370: Waiting for send to finish...
43240299.370: +CPU: vendor AMD device 600f12
43241299.370: After Startup.
43242299.370: CPU3: stack_base 0014e000, stack_end 0014eff8
43243299.370: CPU: family 15, model 01, stepping 02
43244299.370: Asserting INIT.
43245299.370: Waiting for send to finish...
43246299.370: +nodeid = 00, coreid = 02
43247299.370: Deasserting INIT.
43248299.370: Waiting for send to finish...
43249299.370: +Enabling cache
43250299.370: #startup loops: 1.
43251299.370: Sending STARTUP #1 to 3.
43252299.370: After apic_write.
43253299.370: CPU ID 0x80000001: 600f12
43254299.370: Startup point 1.
43255299.370: Waiting for send to finish...
43256299.370: +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43257299.370: After Startup.
43258299.370: CPU4: stack_base 0014d000, stack_end 0014dff8
43259299.370: Initializing CPU #3
43260299.370: MTRR: Physical address space:
43261299.370: Asserting INIT.
43262299.370: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
43263299.370: Waiting for send to finish...
43264299.370: +CPU: vendor AMD device 600f12
43265299.370: Deasserting INIT.
43266299.370: 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
43267299.370: Waiting for send to finish...
43268299.370: +CPU: family 15, model 01, stepping 02
43269299.370: 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
43270299.370: #startup loops: 1.
43271299.370: Sending STARTUP #1 to 4.
43272299.370: 0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
43273299.370: After apic_write.
43274299.370: 0x0000000100000000 - 0x0000004040000000 size 0x3f40000000 type 6
43275299.370: Startup point 1.
43276299.370: Waiting for send to finish...
43277299.371: +nodeid = 00, coreid = 03
43278299.371: After Startup.
43279299.371: CPU5: stack_base 0014c000, stack_end 0014cff8
43280299.371: Enabling cache
43281299.371: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43282299.371: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43283299.371: Asserting INIT.
43284299.371: MTRR: Fixed MSR 0x259 0x0000000000000000
43285299.371: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43286299.371: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43287299.371: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43288299.371: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43289299.371: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43290299.371: Waiting for send to finish...
43291299.371: +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43292299.371: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43293299.371: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43294299.371: Deasserting INIT.
43295299.371: Waiting for send to finish...
43296299.371: +Initializing CPU #4
43297299.371: #startup loops: 1.
43298299.371: Sending STARTUP #1 to 5.
43299299.371: MTRR: default type WB/UC MTRR counts: 1/2.
43300299.371: After apic_write.
43301299.371: MTRR: WB selected as default type.
43302299.371: Startup point 1.
43303299.371: Waiting for send to finish...
43304299.371: +MTRR: 0 base 0x00000000c0000000 mask 0x0000ffffc0000000 type 0
43305299.371: After Startup.
43306299.371: CPU6: stack_base 0014b000, stack_end 0014bff8
43307299.371:
43308299.371: MTRR check
43309299.371: Fixed MTRRs : Enabled
43310299.371: Variable MTRRs: Enabled
43311299.371: Asserting INIT.
43312299.371:
43313299.371: Waiting for send to finish...
43314299.371: Setting up local APIC...+ apic_id: 0x02 Deasserting INIT.
43315299.371: done.
43316299.371: Waiting for send to finish...
43317299.371: CPU model: AMD Opteron(tm) Processor 6278
43318299.371: +siblings = 15, #startup loops: 1.
43319299.371: Disabling SMM ASeg memory
43320299.371: Sending STARTUP #1 to 6.
43321299.371:
43322299.371: MTRR check
43323299.371: Fixed MTRRs : Enabled
43324299.371: Variable MTRRs: After apic_write.
43325299.371: Enabled
43326299.371:
43327299.371: Startup point 1.
43328299.371: Waiting for send to finish...
43329299.371: +Setting up local APIC...After Startup.
43330299.371: apic_id: 0x03 done.
43331299.371: CPU7: stack_base 0014a000, stack_end 0014aff8
43332299.371: CPU model: AMD Opteron(tm) Processor 6278
43333299.372: CPU #2 initialized
43334299.372: Asserting INIT.
43335299.372: siblings = 15, Waiting for send to finish...
43336299.372: +Disabling SMM ASeg memory
43337299.372: Deasserting INIT.
43338299.372: CPU #3 initialized
43339299.372: Waiting for send to finish...
43340299.372: +Initializing CPU #5
43341299.372: #startup loops: 1.
43342299.372: Sending STARTUP #1 to 7.
43343299.372: After apic_write.
43344299.372: CPU: vendor AMD device 600f12
43345299.372: Startup point 1.
43346299.372: Waiting for send to finish...
43347299.372: +CPU: vendor AMD device 600f12
43348299.372: After Startup.
43349299.372: CPU8: stack_base 00149000, stack_end 00149ff8
43350299.372: Initializing CPU #6
43351299.372: Asserting INIT.
43352299.372: Waiting for send to finish...
43353299.372: +CPU: vendor AMD device 600f12
43354299.372: Deasserting INIT.
43355299.372: Waiting for send to finish...
43356299.372: +CPU: family 15, model 01, stepping 02
43357299.372: #startup loops: 1.
43358299.372: Sending STARTUP #1 to 8.
43359299.372: After apic_write.
43360299.372: nodeid = 00, coreid = 04
43361299.372: Startup point 1.
43362299.372: Waiting for send to finish...
43363299.372: +CPU: family 15, model 01, stepping 02
43364299.372: After Startup.
43365299.372: CPU9: stack_base 00148000, stack_end 00148ff8
43366299.372: nodeid = 00, coreid = 05
43367299.372: Asserting INIT.
43368299.372: Waiting for send to finish...
43369299.372: +Enabling cache
43370299.372: Deasserting INIT.
43371299.372: Waiting for send to finish...
43372299.372: +CPU: family 15, model 01, stepping 02
43373299.372: #startup loops: 1.
43374299.372: Sending STARTUP #1 to 9.
43375299.372: After apic_write.
43376299.372: Initializing CPU #8
43377299.372: Startup point 1.
43378299.372: Waiting for send to finish...
43379299.372: +Enabling cache
43380299.372: After Startup.
43381299.372: CPU ID 0x80000001: 600f12
43382299.372: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43383299.372: CPU10: stack_base 00147000, stack_end 00147ff8
43384299.372: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43385299.373: Asserting INIT.
43386299.373: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43387299.373: MTRR: Fixed MSR 0x259 0x0000000000000000
43388299.373: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43389299.373: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43390299.373: Waiting for send to finish...
43391299.373: +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43392299.373: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43393299.373: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43394299.373: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43395299.373: Deasserting INIT.
43396299.373: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43397299.373: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43398299.373: Waiting for send to finish...
43399299.373: +nodeid = 00, coreid = 06
43400299.373: #startup loops: 1.
43401299.373: Sending STARTUP #1 to 10.
43402299.373:
43403299.373: MTRR check
43404299.373: Fixed MTRRs : Enabled
43405299.373: Variable MTRRs: Enabled
43406299.373:
43407299.373: After apic_write.
43408299.373: CPU: vendor AMD device 600f12
43409299.373: Startup point 1.
43410299.373: Waiting for send to finish...
43411299.373: Setting up local APIC...+ apic_id: 0x04 After Startup.
43412299.373: done.
43413299.373: CPU11: stack_base 00146000, stack_end 00146ff8
43414299.373: CPU model: AMD Opteron(tm) Processor 6278
43415299.373: Asserting INIT.
43416299.373: siblings = 15, Waiting for send to finish...
43417299.373: Disabling SMM ASeg memory
43418299.373: +
43419299.373: MTRR check
43420299.373: Fixed MTRRs : Enabled
43421299.373: Deasserting INIT.
43422299.373: Variable MTRRs: Enabled
43423299.373:
43424299.373: Waiting for send to finish...
43425299.373: +Setting up local APIC...CPU #4 initialized
43426299.373: #startup loops: 1.
43427299.373: Sending STARTUP #1 to 11.
43428299.373: apic_id: 0x05 done.
43429299.373: After apic_write.
43430299.373: CPU model: AMD Opteron(tm) Processor 6278
43431299.373: Startup point 1.
43432299.373: Waiting for send to finish...
43433299.373: +siblings = 15, After Startup.
43434299.373: Disabling SMM ASeg memory
43435299.373: CPU12: stack_base 00145000, stack_end 00145ff8
43436299.373: CPU #5 initialized
43437299.373: Asserting INIT.
43438299.373: Waiting for send to finish...
43439299.374: +Initializing CPU #10
43440299.374: Deasserting INIT.
43441299.374: CPU: vendor AMD device 600f12
43442299.374: Waiting for send to finish...
43443299.374: +Initializing CPU #7
43444299.374: #startup loops: 1.
43445299.374: Sending STARTUP #1 to 12.
43446299.374: After apic_write.
43447299.374: Enabling cache
43448299.374: Startup point 1.
43449299.374: Waiting for send to finish...
43450299.374: +Initializing CPU #11
43451299.374: After Startup.
43452299.374: CPU13: stack_base 00144000, stack_end 00144ff8
43453299.374: CPU: vendor AMD device 600f12
43454299.374: Asserting INIT.
43455299.374: CPU: family 15, model 01, stepping 02
43456299.374: Waiting for send to finish...
43457299.374: +Initializing CPU #12
43458299.374: Deasserting INIT.
43459299.374: nodeid = 00, coreid = 07
43460299.374: Waiting for send to finish...
43461299.374: +Initializing CPU #9
43462299.374: CPU: family 15, model 01, stepping 02
43463299.374: #startup loops: 1.
43464299.374: Sending STARTUP #1 to 13.
43465299.374: After apic_write.
43466299.374: Enabling cache
43467299.374: Startup point 1.
43468299.374: CPU ID 0x80000001: 600f12
43469299.374: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43470299.374: Waiting for send to finish...
43471299.374: +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43472299.374: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43473299.374: After Startup.
43474299.374: CPU14: stack_base 00143000, stack_end 00143ff8
43475299.374: MTRR: Fixed MSR 0x259 0x0000000000000000
43476299.374: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43477299.374: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43478299.374: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43479299.374: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43480299.374: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43481299.374: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43482299.374: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43483299.374: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43484299.374: Asserting INIT.
43485299.374: Waiting for send to finish...
43486299.374: +nodeid = 01, coreid = 00
43487299.374: Deasserting INIT.
43488299.374:
43489299.374: MTRR check
43490299.374: Waiting for send to finish...
43491299.374: +Fixed MTRRs : #startup loops: 1.
43492299.375: Sending STARTUP #1 to 14.
43493299.375: Enabled
43494299.375: Variable MTRRs: Enabled
43495299.375: After apic_write.
43496299.375:
43497299.375: Initializing CPU #13
43498299.375: Startup point 1.
43499299.375: Waiting for send to finish...
43500299.375: +Setting up local APIC...After Startup.
43501299.375: CPU15: stack_base 00142000, stack_end 00142ff8
43502299.375: apic_id: 0x06 done.
43503299.375: Asserting INIT.
43504299.375: CPU model: AMD Opteron(tm) Processor 6278
43505299.375: Waiting for send to finish...
43506299.375: +siblings = 15, Deasserting INIT.
43507299.375: Disabling SMM ASeg memory
43508299.375: Waiting for send to finish...
43509299.375: CPU #6 initialized
43510299.375: +
43511299.375: MTRR check
43512299.375: #startup loops: 1.
43513299.375: Sending STARTUP #1 to 15.
43514299.375: After apic_write.
43515299.375: Fixed MTRRs : Enabled
43516299.375: Variable MTRRs: Startup point 1.
43517299.375: Enabled
43518299.375: Waiting for send to finish...
43519299.375: +
43520299.375: CPU: family 15, model 01, stepping 02
43521299.375: After Startup.
43522299.375: Setting up local APIC...CPU16: stack_base 00141000, stack_end 00141ff8
43523299.375: apic_id: 0x07 done.
43524299.375: Asserting INIT.
43525299.375: CPU model: AMD Opteron(tm) Processor 6278
43526299.375: Waiting for send to finish...
43527299.375: +siblings = 15, Deasserting INIT.
43528299.375: Disabling SMM ASeg memory
43529299.375: Waiting for send to finish...
43530299.375: +CPU #7 initialized
43531299.375: #startup loops: 1.
43532299.375: Sending STARTUP #1 to 32.
43533299.375: After apic_write.
43534299.375: CPU: vendor AMD device 600f12
43535299.375: Startup point 1.
43536299.375: Waiting for send to finish...
43537299.375: +Initializing CPU #16
43538299.376: After Startup.
43539299.375: CPU17: stack_base 00140000, stack_end 00140ff8
43540299.375: CPU: vendor AMD device 600f12
43541299.376: Asserting INIT.
43542299.376: Initializing CPU #14
43543299.376: Waiting for send to finish...
43544299.376: +CPU: family 15, model 01, stepping 02
43545299.376: Deasserting INIT.
43546299.376: Waiting for send to finish...
43547299.376: +CPU: vendor AMD device 600f12
43548299.376: #startup loops: 1.
43549299.376: Sending STARTUP #1 to 33.
43550299.376: After apic_write.
43551299.376: CPU: family 15, model 01, stepping 02
43552299.376: Startup point 1.
43553299.376: Waiting for send to finish...
43554299.376: +Enabling cache
43555299.376: After Startup.
43556299.376: CPU18: stack_base 0013f000, stack_end 0013fff8
43557299.376: nodeid = 01, coreid = 02
43558299.376: CPU ID 0x80000001: 600f12
43559299.376: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43560299.376: Asserting INIT.
43561299.376: Waiting for send to finish...
43562299.376: +Initializing CPU #15
43563299.376: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43564299.376: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43565299.376: MTRR: Fixed MSR 0x259 0x0000000000000000
43566299.376: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43567299.376: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43568299.376: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43569299.376: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43570299.376: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43571299.376: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43572299.376: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43573299.376: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43574299.376: Deasserting INIT.
43575299.376: nodeid = 02, coreid = 00
43576299.376: Waiting for send to finish...
43577299.376: +CPU: vendor AMD device 600f12
43578299.376: #startup loops: 1.
43579299.376: Sending STARTUP #1 to 34.
43580299.376: After apic_write.
43581299.376: nodeid = 01, coreid = 01
43582299.376: Startup point 1.
43583299.376: Waiting for send to finish...
43584299.376: +Initializing CPU #18
43585299.376:
43586299.376: MTRR check
43587299.376: Fixed MTRRs : Enabled
43588299.376: Variable MTRRs: Enabled
43589299.376:
43590299.376: After Startup.
43591299.377: CPU19: stack_base 0013e000, stack_end 0013eff8
43592299.377: CPU: vendor AMD device 600f12
43593299.377: Setting up local APIC...Asserting INIT.
43594299.377: CPU: family 15, model 01, stepping 02
43595299.377: Waiting for send to finish...
43596299.377: +Enabling cache
43597299.377: Deasserting INIT.
43598299.377: Enabling cache
43599299.377: apic_id: 0x08 done.
43600299.377: Waiting for send to finish...
43601299.377: +nodeid = 02, coreid = 02
43602299.377: CPU ID 0x80000001: 600f12
43603299.377: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43604299.377: CPU: family 15, model 01, stepping 02
43605299.377: CPU ID 0x80000001: 600f12
43606299.377: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43607299.377: #startup loops: 1.
43608299.377: Sending STARTUP #1 to 35.
43609299.377: After apic_write.
43610299.377: CPU: vendor AMD device 600f12
43611299.377: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43612299.377: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43613299.377: MTRR: Fixed MSR 0x259 0x0000000000000000
43614299.377: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43615299.377: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43616299.377: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43617299.377: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43618299.377: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43619299.377: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43620299.377: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43621299.377: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43622299.377: Startup point 1.
43623299.377: Waiting for send to finish...
43624299.377: +Enabling cache
43625299.377: CPU model: AMD Opteron(tm) Processor 6278
43626299.377: Initializing CPU #17
43627299.377: siblings = 15, After Startup.
43628299.377: CPU20: stack_base 0013d000, stack_end 0013dff8
43629299.377: Initializing CPU #19
43630299.377: CPU ID 0x80000001: 600f12
43631299.377: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43632299.377: CPU: vendor AMD device 600f12
43633299.377: CPU: family 15, model 01, stepping 02
43634299.377: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43635299.377: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43636299.377: MTRR: Fixed MSR 0x259 0x0000000000000000
43637299.377: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43638299.377: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43639299.377: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43640299.377: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43641299.377: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43642299.377: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43643299.378: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43644299.378: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43645299.378: Asserting INIT.
43646299.378: CPU: vendor AMD device 600f12
43647299.378: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43648299.378: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43649299.378: MTRR: Fixed MSR 0x259 0x0000000000000000
43650299.378: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43651299.378: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43652299.378: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43653299.378: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43654299.378: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43655299.378: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43656299.378: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43657299.378: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43658299.378: Waiting for send to finish...
43659299.378: +Disabling SMM ASeg memory
43660299.378:
43661299.378: MTRR check
43662299.378: Fixed MTRRs : Enabled
43663299.378: Variable MTRRs: Enabled
43664299.378:
43665299.378: Deasserting INIT.
43666299.378: CPU: family 15, model 01, stepping 02
43667299.378:
43668299.378: MTRR check
43669299.378: Fixed MTRRs : Enabled
43670299.378: Variable MTRRs: Enabled
43671299.378:
43672299.378: Waiting for send to finish...
43673299.378: +nodeid = 02, coreid = 01
43674299.378: Setting up local APIC...#startup loops: 1.
43675299.378: Sending STARTUP #1 to 36.
43676299.378: After apic_write.
43677299.378: Enabling cache
43678299.378:
43679299.378: MTRR check
43680299.378: Fixed MTRRs : Enabled
43681299.378: Variable MTRRs: Enabled
43682299.378:
43683299.378: Startup point 1.
43684299.378: Waiting for send to finish...
43685299.378: +
43686299.378: MTRR check
43687299.378: Fixed MTRRs : Enabled
43688299.378: Variable MTRRs: Enabled
43689299.378:
43690299.378: After Startup.
43691299.378: CPU21: stack_base 0013c000, stack_end 0013cff8
43692299.378: Setting up local APIC...CPU #8 initialized
43693299.378: Asserting INIT.
43694299.378: apic_id: 0x09 done.
43695299.378: Waiting for send to finish...
43696299.378: +Initializing CPU #20
43697299.379: apic_id: 0x22 done.
43698299.379: CPU model: AMD Opteron(tm) Processor 6278
43699299.379: Deasserting INIT.
43700299.379: siblings = 15, Waiting for send to finish...
43701299.379: +Disabling SMM ASeg memory
43702299.379: #startup loops: 1.
43703299.379: Sending STARTUP #1 to 37.
43704299.379: After apic_write.
43705299.379: CPU #9 initialized
43706299.379: Startup point 1.
43707299.379: Waiting for send to finish...
43708299.379: +Initializing CPU #21
43709299.379: CPU model: AMD Opteron(tm) Processor 6278
43710299.379: After Startup.
43711299.379: CPU22: stack_base 0013b000, stack_end 0013bff8
43712299.379: nodeid = 01, coreid = 06
43713299.379: Setting up local APIC...Asserting INIT.
43714299.379: Enabling cache
43715299.379: apic_id: 0x0a done.
43716299.379: Waiting for send to finish...
43717299.379: +Setting up local APIC...Deasserting INIT.
43718299.379: apic_id: 0x20 done.
43719299.379: Waiting for send to finish...
43720299.379: +CPU model: AMD Opteron(tm) Processor 6278
43721299.379: #startup loops: 1.
43722299.379: siblings = 15, Sending STARTUP #1 to 38.
43723299.379: After apic_write.
43724299.379: Disabling SMM ASeg memory
43725299.379: Startup point 1.
43726299.379: Waiting for send to finish...
43727299.379: +CPU #16 initialized
43728299.379: After Startup.
43729299.379:
43730299.379: MTRR check
43731299.379: Fixed MTRRs : Enabled
43732299.379: Variable MTRRs: Enabled
43733299.379:
43734299.379: Initializing CPU #22
43735299.379: siblings = 15, Setting up local APIC...CPU: vendor AMD device 600f12
43736299.379: apic_id: 0x21 done.
43737299.379: CPU23: stack_base 0013a000, stack_end 0013aff8
43738299.379: CPU model: AMD Opteron(tm) Processor 6278
43739299.379: Enabling cache
43740299.379: CPU model: AMD Opteron(tm) Processor 6278
43741299.379: siblings = 15, Asserting INIT.
43742299.380: Disabling SMM ASeg memory
43743299.380: Waiting for send to finish...
43744299.380: +CPU #17 initialized
43745299.380: Deasserting INIT.
43746299.380: CPU: family 15, model 01, stepping 02
43747299.380: Waiting for send to finish...
43748299.380: +CPU: vendor AMD device 600f12
43749299.380: CPU: vendor AMD device 600f12
43750299.380: siblings = 15, #startup loops: 1.
43751299.380: Sending STARTUP #1 to 39.
43752299.380: After apic_write.
43753299.380: CPU: family 15, model 01, stepping 02
43754299.380: CPU ID 0x80000001: 600f12
43755299.380: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43756299.380: Startup point 1.
43757299.380: Waiting for send to finish...
43758299.380: +CPU: family 15, model 01, stepping 02
43759299.380: After Startup.
43760299.380: CPU24: stack_base 00139000, stack_end 00139ff8
43761299.380: CPU: vendor AMD device 600f12
43762299.380: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43763299.380: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43764299.380: MTRR: Fixed MSR 0x259 0x0000000000000000
43765299.380: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43766299.380: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43767299.380: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43768299.380: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43769299.380: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43770299.380: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43771299.380: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43772299.380: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43773299.380: Asserting INIT.
43774299.380: Disabling SMM ASeg memory
43775299.380: Waiting for send to finish...
43776299.380: +CPU: family 15, model 01, stepping 02
43777299.380: Deasserting INIT.
43778299.380: nodeid = 01, coreid = 03
43779299.380:
43780299.380: MTRR check
43781299.380: Fixed MTRRs : Enabled
43782299.380: Variable MTRRs: Enabled
43783299.380:
43784299.380: Waiting for send to finish...
43785299.380: +Disabling SMM ASeg memory
43786299.380: Setting up local APIC...#startup loops: 1.
43787299.380: Sending STARTUP #1 to 40.
43788299.380: After apic_write.
43789299.380: Enabling cache
43790299.380: apic_id: 0x0e
43791299.380: MTRR check
43792299.380: Startup point 1.
43793299.380: Waiting for send to finish...
43794299.381: +Fixed MTRRs : After Startup.
43795299.381: CPU25: stack_base 00138000, stack_end 00138ff8
43796299.381: CPU #10 initialized
43797299.381: Enabled
43798299.381: Variable MTRRs: Enabled
43799299.381:
43800299.381: Asserting INIT.
43801299.381: CPU #18 initialized
43802299.381: Setting up local APIC...nodeid = 02, coreid = 03
43803299.381: apic_id: 0x0b done.
43804299.381: Enabling cache
43805299.381: done.
43806299.381: Waiting for send to finish...
43807299.381: +CPU model: AMD Opteron(tm) Processor 6278
43808299.381: Deasserting INIT.
43809299.381: siblings = 15,
43810299.381: MTRR check
43811299.381: Fixed MTRRs : Enabled
43812299.381: Variable MTRRs: Enabled
43813299.381:
43814299.381: Disabling SMM ASeg memory
43815299.381: Waiting for send to finish...
43816299.381: CPU #11 initialized
43817299.381: Setting up local APIC...+ apic_id: 0x23 done.
43818299.381: #startup loops: 1.
43819299.381: Sending STARTUP #1 to 41.
43820299.381: CPU model: AMD Opteron(tm) Processor 6278
43821299.381: After apic_write.
43822299.381: siblings = 15, Startup point 1.
43823299.381: Waiting for send to finish...
43824299.381: Disabling SMM ASeg memory
43825299.381: +CPU #19 initialized
43826299.381: After Startup.
43827299.381: CPU26: stack_base 00137000, stack_end 00137ff8
43828299.381: nodeid = 01, coreid = 07
43829299.381: CPU model: AMD Opteron(tm) Processor 6278
43830299.381: Asserting INIT.
43831299.381: Enabling cache
43832299.381: Waiting for send to finish...
43833299.381: siblings = 15, +Disabling SMM ASeg memory
43834299.381: Deasserting INIT.
43835299.381:
43836299.381: MTRR check
43837299.381: Fixed MTRRs : Enabled
43838299.381: Variable MTRRs: Enabled
43839299.381:
43840299.381: Waiting for send to finish...
43841299.381: +Setting up local APIC...CPU #14 initialized
43842299.382: #startup loops: 1.
43843299.382: Sending STARTUP #1 to 42.
43844299.382: After apic_write.
43845299.382: apic_id: 0x0f done.
43846299.382: Startup point 1.
43847299.382: Waiting for send to finish...
43848299.382: +CPU model: AMD Opteron(tm) Processor 6278
43849299.382: Initializing CPU #25
43850299.382: siblings = 15, After Startup.
43851299.382: CPU27: stack_base 00136000, stack_end 00136ff8
43852299.382: Disabling SMM ASeg memory
43853299.382: Asserting INIT.
43854299.382: CPU #15 initialized
43855299.382: Waiting for send to finish...
43856299.382: +Initializing CPU #26
43857299.382: Deasserting INIT.
43858299.382: Waiting for send to finish...
43859299.382: +CPU: family 15, model 01, stepping 02
43860299.382: #startup loops: 1.
43861299.382: Sending STARTUP #1 to 43.
43862299.382: After apic_write.
43863299.382: CPU: vendor AMD device 600f12
43864299.382: Startup point 1.
43865299.382: Waiting for send to finish...
43866299.382: +nodeid = 02, coreid = 04
43867299.382: After Startup.
43868299.382: CPU28: stack_base 00135000, stack_end 00135ff8
43869299.382: Initializing CPU #24
43870299.382: Asserting INIT.
43871299.382: Waiting for send to finish...
43872299.382: +Enabling cache
43873299.382: Deasserting INIT.
43874299.382: Waiting for send to finish...
43875299.382: +CPU: family 15, model 01, stepping 02
43876299.382: CPU: vendor AMD device 600f12
43877299.382: #startup loops: 1.
43878299.382: Sending STARTUP #1 to 44.
43879299.382: After apic_write.
43880299.382: CPU: vendor AMD device 600f12
43881299.382: CPU ID 0x80000001: 600f12
43882299.382: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43883299.382: Startup point 1.
43884299.382: Waiting for send to finish...
43885299.382: +Initializing CPU #28
43886299.382: After Startup.
43887299.383: CPU29: stack_base 00134000, stack_end 00134ff8
43888299.383: CPU: vendor AMD device 600f12
43889299.383: Asserting INIT.
43890299.383: Initializing CPU #27
43891299.383: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43892299.383: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43893299.383: MTRR: Fixed MSR 0x259 0x0000000000000000
43894299.383: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43895299.383: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43896299.383: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43897299.383: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43898299.383: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43899299.383: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43900299.383: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43901299.383: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43902299.383: Waiting for send to finish...
43903299.383: +nodeid = 03, coreid = 02
43904299.383: Deasserting INIT.
43905299.383: CPU: family 15, model 01, stepping 02
43906299.383: Waiting for send to finish...
43907299.383: +CPU: family 15, model 01, stepping 02
43908299.383: #startup loops: 1.
43909299.383: Sending STARTUP #1 to 45.
43910299.383: After apic_write.
43911299.383: Initializing CPU #23
43912299.383:
43913299.383: MTRR check
43914299.383: Fixed MTRRs : Enabled
43915299.383: Variable MTRRs: Enabled
43916299.383:
43917299.383: Startup point 1.
43918299.383: Waiting for send to finish...
43919299.383: +nodeid = 02, coreid = 05
43920299.383: After Startup.
43921299.383: CPU30: stack_base 00133000, stack_end 00133ff8
43922299.383: Enabling cache
43923299.383: Asserting INIT.
43924299.383: nodeid = 01, coreid = 05
43925299.383: Setting up local APIC...Waiting for send to finish...
43926299.383: +Enabling cache
43927299.383: CPU ID 0x80000001: 600f12
43928299.383: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43929299.383: Deasserting INIT.
43930299.383: nodeid = 03, coreid = 00
43931299.383: CPU: vendor AMD device 600f12
43932299.383: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43933299.383: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43934299.383: MTRR: Fixed MSR 0x259 0x0000000000000000
43935299.383: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43936299.383: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43937299.383: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43938299.383: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43939299.383: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43940299.384: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43941299.383: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43942299.384: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43943299.384: Waiting for send to finish...
43944299.384: +Enabling cache
43945299.384: #startup loops: 1.
43946299.384: Sending STARTUP #1 to 46.
43947299.384: CPU: family 15, model 01, stepping 02
43948299.384: After apic_write.
43949299.384: nodeid = 01, coreid = 04
43950299.384: Startup point 1.
43951299.384: Waiting for send to finish...
43952299.384: +Enabling cache
43953299.384: CPU ID 0x80000001: 600f12
43954299.384: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43955299.384: After Startup.
43956299.384: CPU31: stack_base 00132000, stack_end 00132ff8
43957299.384: CPU ID 0x80000001: 600f12
43958299.384: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
43959299.384: Initializing CPU #30
43960299.384: Asserting INIT.
43961299.384: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43962299.384: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43963299.384: MTRR: Fixed MSR 0x259 0x0000000000000000
43964299.384: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43965299.384: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43966299.384: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43967299.384: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43968299.384: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43969299.384: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43970299.384: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43971299.384: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43972299.384: Waiting for send to finish...
43973299.384: +CPU: vendor AMD device 600f12
43974299.384: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
43975299.384: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
43976299.384: MTRR: Fixed MSR 0x259 0x0000000000000000
43977299.384: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
43978299.384: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
43979299.384: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
43980299.384: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
43981299.384: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
43982299.384: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
43983299.384: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
43984299.384: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
43985299.384:
43986299.384: MTRR check
43987299.384: Fixed MTRRs : Enabled
43988299.384: Variable MTRRs: Enabled
43989299.384:
43990299.384: Deasserting INIT.
43991299.384: CPU: vendor AMD device 600f12
43992299.384:
43993299.384: MTRR check
43994299.384: Fixed MTRRs : Enabled
43995299.384: Variable MTRRs: Enabled
43996299.384:
43997299.384: Setting up local APIC...nodeid = 02, coreid = 06
43998299.385: apic_id: 0x0c done.
43999299.385: CPU: family 15, model 01, stepping 02
44000299.385: apic_id: 0x24 done.
44001299.385: CPU model: AMD Opteron(tm) Processor 6278
44002299.385: Waiting for send to finish...
44003299.385: +siblings = 15, #startup loops: 1.
44004299.385: Disabling SMM ASeg memory
44005299.385: nodeid = 03, coreid = 06
44006299.385: CPU model: AMD Opteron(tm) Processor 6278
44007299.385: Enabling cache
44008299.385: siblings = 15, Sending STARTUP #1 to 47.
44009299.385: CPU #12 initialized
44010299.385:
44011299.385: MTRR check
44012299.385: Fixed MTRRs : Enabled
44013299.385: Variable MTRRs: Enabled
44014299.385:
44015299.385: CPU ID 0x80000001: 600f12
44016299.385: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
44017299.385: After apic_write.
44018299.385: Setting up local APIC...Enabling cache
44019299.385:
44020299.385: MTRR check
44021299.385: Fixed MTRRs : Enabled
44022299.385: Variable MTRRs: Enabled
44023299.385:
44024299.385: Startup point 1.
44025299.385: Waiting for send to finish...
44026299.385: + apic_id: 0x0d done.
44027299.385: After Startup.
44028299.385: Initializing CPU #0
44029299.385: CPU model: AMD Opteron(tm) Processor 6278
44030299.385: CPU: vendor AMD device 600f12
44031299.385: CPU: family 15, model 01, stepping 02
44032299.385: siblings = 15, nodeid = 00, coreid = 00
44033299.385: Disabling SMM ASeg memory
44034299.385: Enabling cache
44035299.385: CPU #13 initialized
44036299.385: Initializing CPU #31
44037299.385: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
44038299.385: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
44039299.385: MTRR: Fixed MSR 0x259 0x0000000000000000
44040299.385: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
44041299.385: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
44042299.385: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
44043299.385: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
44044299.385: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
44045299.385: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
44046299.385: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
44047299.385: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
44048299.385: CPU ID 0x80000001: 600f12
44049299.385: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
44050299.385: Initializing CPU #29
44051299.386: Setting up local APIC...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
44052299.386: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
44053299.386: MTRR: Fixed MSR 0x259 0x0000000000000000
44054299.386: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
44055299.386: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
44056299.386: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
44057299.386: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
44058299.386: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
44059299.386: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
44060299.386: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
44061299.386: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
44062299.386: CPU: family 15, model 01, stepping 02
44063299.386: Setting up local APIC...CPU: vendor AMD device 600f12
44064299.386: CPU: family 15, model 01, stepping 02
44065299.386: CPU ID 0x80000001: 600f12
44066299.386: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
44067299.386:
44068299.386: MTRR check
44069299.386: Fixed MTRRs : Enabled
44070299.386: Variable MTRRs: Enabled
44071299.386:
44072299.386: nodeid = 03, coreid = 04
44073299.386: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
44074299.386: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
44075299.386: MTRR: Fixed MSR 0x259 0x0000000000000000
44076299.386: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
44077299.386: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
44078299.386: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
44079299.386: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
44080299.386: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
44081299.386: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
44082299.386: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
44083299.386: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
44084299.386: Setting up local APIC...CPU: vendor AMD device 600f12
44085299.386: apic_id: 0x28 done.
44086299.386: apic_id: 0x00 done.
44087299.386: Enabling cache
44088299.386:
44089299.386: MTRR check
44090299.386: Fixed MTRRs : Enabled
44091299.386: Variable MTRRs: Enabled
44092299.386:
44093299.386: CPU model: AMD Opteron(tm) Processor 6278
44094299.386: Disabling SMM ASeg memory
44095299.386: siblings = 15,
44096299.386: MTRR check
44097299.386: Fixed MTRRs : Enabled
44098299.386: Variable MTRRs: Enabled
44099299.386:
44100299.386: Disabling SMM ASeg memory
44101299.386: CPU #20 initialized
44102299.386: CPU #0 initialized
44103299.386: Waiting for 12 CPUS to stop
44104299.386: Setting up local APIC...
44105299.386: MTRR check
44106299.386: Fixed MTRRs : Enabled
44107299.387: Variable MTRRs: apic_id: 0x25 done.
44108299.387: Enabled
44109299.387:
44110299.387: CPU model: AMD Opteron(tm) Processor 6278
44111299.387: Setting up local APIC...siblings = 15, apic_id: 0x01 done.
44112299.387: Disabling SMM ASeg memory
44113299.387: CPU model: AMD Opteron(tm) Processor 6278
44114299.387: CPU #21 initialized
44115299.387: siblings = 15, Waiting for 11 CPUS to stop
44116299.387: Disabling SMM ASeg memory
44117299.387: CPU: family 15, model 01, stepping 02
44118299.387: Setting up local APIC...CPU #1 initialized
44119299.387: nodeid = 03, coreid = 03
44120299.387:
44121299.387: MTRR check
44122299.387: Fixed MTRRs : Enabled
44123299.387: Variable MTRRs: Enabled
44124299.387:
44125299.387: Waiting for 10 CPUS to stop
44126299.387: CPU: family 15, model 01, stepping 02
44127299.387: nodeid = 03, coreid = 01
44128299.387: CPU model: AMD Opteron(tm) Processor 6278
44129299.387: Enabling cache
44130299.387: Setting up local APIC...Enabling cache
44131299.387: CPU: vendor AMD device 600f12
44132299.387: CPU ID 0x80000001: 600f12
44133299.387: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
44134299.387: siblings = 15, CPU: family 15, model 01, stepping 02
44135299.387: apic_id: 0x2a done.
44136299.387: Disabling SMM ASeg memory
44137299.387: Enabling cache
44138299.387:
44139299.387: MTRR check
44140299.387: Fixed MTRRs : Enabled
44141299.387: Variable MTRRs: CPU model: AMD Opteron(tm) Processor 6278
44142299.387: CPU #24 initialized
44143299.387: siblings = 15, Waiting for 9 CPUS to stop
44144299.387: Disabling SMM ASeg memory
44145299.387: Enabled
44146299.387:
44147299.387:
44148299.387: MTRR check
44149299.387: Fixed MTRRs : Enabled
44150299.387: Variable MTRRs: Enabled
44151299.387:
44152299.387: Setting up local APIC...nodeid = 03, coreid = 05
44153299.387: apic_id: 0x2e done.
44154299.388: Setting up local APIC...CPU #26 initialized
44155299.388: apic_id: 0x2b done.
44156299.388: apic_id: 0x29 done.
44157299.388: Waiting for 8 CPUS to stop
44158299.388: CPU model: AMD Opteron(tm) Processor 6278
44159299.388: CPU model: AMD Opteron(tm) Processor 6278
44160299.388: siblings = 15, siblings = 15, Disabling SMM ASeg memory
44161299.388: Disabling SMM ASeg memory
44162299.388: CPU #27 initialized
44163299.388: CPU #25 initialized
44164299.388: Waiting for 7 CPUS to stop
44165299.388: Enabling cache
44166299.388: Waiting for 6 CPUS to stop
44167299.388: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
44168299.388: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
44169299.388: MTRR: Fixed MSR 0x259 0x0000000000000000
44170299.388: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
44171299.388: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
44172299.388: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
44173299.388: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
44174299.388: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
44175299.388: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
44176299.388: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
44177299.388: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
44178299.388: nodeid = 03, coreid = 07
44179299.388: CPU model: AMD Opteron(tm) Processor 6278
44180299.388: CPU: family 15, model 01, stepping 02
44181299.388: apic_id: 0x26 done.
44182299.388:
44183299.388: MTRR check
44184299.388: Fixed MTRRs : Enabled
44185299.388: Variable MTRRs: Enabled
44186299.388:
44187299.388: nodeid = 02, coreid = 07
44188299.388: siblings = 15, Setting up local APIC...Disabling SMM ASeg memory
44189299.388: CPU model: AMD Opteron(tm) Processor 6278
44190299.388: apic_id: 0x2c done.
44191299.388: Enabling cache
44192299.388: siblings = 15, CPU model: AMD Opteron(tm) Processor 6278
44193299.388:
44194299.388: MTRR check
44195299.388: Fixed MTRRs : Enabled
44196299.388: Variable MTRRs: Enabled
44197299.388:
44198299.388: siblings = 15, Enabling cache
44199299.388: Disabling SMM ASeg memory
44200299.388: CPU #30 initialized
44201299.388:
44202299.388: MTRR check
44203299.388: Fixed MTRRs : Enabled
44204299.388: Variable MTRRs: Setting up local APIC...CPU #28 initialized
44205299.389: Waiting for 5 CPUS to stop
44206299.389: Enabled
44207299.389:
44208299.389: apic_id: 0x2f done.
44209299.389: Disabling SMM ASeg memory
44210299.389: CPU model: AMD Opteron(tm) Processor 6278
44211299.389:
44212299.389: MTRR check
44213299.389: Fixed MTRRs : Setting up local APIC...Enabled
44214299.389: Variable MTRRs: Enabled
44215299.389:
44216299.389: siblings = 15, apic_id: 0x2d done.
44217299.389: Disabling SMM ASeg memory
44218299.389: CPU model: AMD Opteron(tm) Processor 6278
44219299.389: CPU #22 initialized
44220299.389: siblings = 15, CPU #31 initialized
44221299.389: Setting up local APIC...Waiting for 4 CPUS to stop
44222299.389: Disabling SMM ASeg memory
44223299.389: apic_id: 0x27 done.
44224299.389: CPU #29 initialized
44225299.389: CPU model: AMD Opteron(tm) Processor 6278
44226299.389: Waiting for 2 CPUS to stop
44227299.389: siblings = 15, Waiting for 1 CPUS to stop
44228299.389: Disabling SMM ASeg memory
44229299.389: CPU #23 initialized
44230299.389: All AP CPUs stopped (20840 loops)
44231299.389: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
44232299.389: CPU1: stack: 00150000 - 00151000, lowest used address 00150de8, stack used: 536 bytes
44233299.389: CPU2: stack: 0014f000 - 00150000, lowest used address 0014fcac, stack used: 852 bytes
44234299.389: CPU3: stack: 0014e000 - 0014f000, lowest used address 0014ede8, stack used: 536 bytes
44235299.389: CPU4: stack: 0014d000 - 0014e000, lowest used address 0014dd08, stack used: 760 bytes
44236299.389: CPU5: stack: 0014c000 - 0014d000, lowest used address 0014cde8, stack used: 536 bytes
44237299.389: CPU6: stack: 0014b000 - 0014c000, lowest used address 0014bd08, stack used: 760 bytes
44238299.389: CPU7: stack: 0014a000 - 0014b000, lowest used address 0014ade8, stack used: 536 bytes
44239299.389: CPU8: stack: 00149000 - 0014a000, lowest used address 00149d08, stack used: 760 bytes
44240299.389: CPU9: stack: 00148000 - 00149000, lowest used address 00148de8, stack used: 536 bytes
44241299.389: CPU10: stack: 00147000 - 00148000, lowest used address 00147d08, stack used: 760 bytes
44242299.389: CPU11: stack: 00146000 - 00147000, lowest used address 00146de8, stack used: 536 bytes
44243299.389: CPU12: stack: 00145000 - 00146000, lowest used address 00145d08, stack used: 760 bytes
44244299.390: CPU13: stack: 00144000 - 00145000, lowest used address 00144de8, stack used: 536 bytes
44245299.390: CPU14: stack: 00143000 - 00144000, lowest used address 00143d08, stack used: 760 bytes
44246299.390: CPU15: stack: 00142000 - 00143000, lowest used address 00142de8, stack used: 536 bytes
44247299.390: CPU16: stack: 00141000 - 00142000, lowest used address 00141d08, stack used: 760 bytes
44248299.390: CPU17: stack: 00140000 - 00141000, lowest used address 00140de8, stack used: 536 bytes
44249299.390: CPU18: stack: 0013f000 - 00140000, lowest used address 0013fd08, stack used: 760 bytes
44250299.390: CPU19: stack: 0013e000 - 0013f000, lowest used address 0013ede8, stack used: 536 bytes
44251299.390: CPU20: stack: 0013d000 - 0013e000, lowest used address 0013dd08, stack used: 760 bytes
44252299.390: CPU21: stack: 0013c000 - 0013d000, lowest used address 0013cde8, stack used: 536 bytes
44253299.390: CPU22: stack: 0013b000 - 0013c000, lowest used address 0013bd08, stack used: 760 bytes
44254299.390: CPU23: stack: 0013a000 - 0013b000, lowest used address 0013ade8, stack used: 536 bytes
44255299.390: CPU24: stack: 00139000 - 0013a000, lowest used address 00139d08, stack used: 760 bytes
44256299.390: CPU25: stack: 00138000 - 00139000, lowest used address 00138de8, stack used: 536 bytes
44257299.390: CPU26: stack: 00137000 - 00138000, lowest used address 00137d08, stack used: 760 bytes
44258299.390: CPU27: stack: 00136000 - 00137000, lowest used address 00136de8, stack used: 536 bytes
44259299.390: CPU28: stack: 00135000 - 00136000, lowest used address 00135d08, stack used: 760 bytes
44260299.390: CPU29: stack: 00134000 - 00135000, lowest used address 00134de8, stack used: 536 bytes
44261299.390: CPU30: stack: 00133000 - 00134000, lowest used address 00133d08, stack used: 760 bytes
44262299.390: CPU31: stack: 00132000 - 00133000, lowest used address 00132de8, stack used: 536 bytes
44263299.390: CPU_CLUSTER: 0 init finished in 2100687 usecs
44264299.390: PCI: 00:18.0 init ...
44265299.390: PCI: 00:18.0 init finished in 1461 usecs
44266299.390: PCI: 00:18.1 init ...
44267299.390: PCI: 00:18.1 init finished in 1462 usecs
44268299.390: PCI: 00:18.2 init ...
44269299.390: PCI: 00:18.2 init finished in 1461 usecs
44270299.390: PCI: 00:18.3 init ...
44271299.390: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44272299.390: CBFS: Locating 'cmos_layout.bin'
44273299.391: CBFS: Found @ offset 2b0c0 size e88
44274299.391: done.
44275299.391: PCI: 00:18.3 init finished in 12592 usecs
44276299.391: PCI: 00:18.4 init ...
44277299.391: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44278299.391: CBFS: Locating 'cmos_layout.bin'
44279299.391: CBFS: Found @ offset 2b0c0 size e88
44280299.392: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44281299.392: CBFS: Locating 'cmos_layout.bin'
44282299.392: CBFS: Found @ offset 2b0c0 size e88
44283299.392: done.
44284299.392: PCI: 00:18.4 init finished in 21323 usecs
44285299.393: PCI: 00:18.5 init ...
44286299.392: NB: Function 5 Northbridge Control.. done.
44287299.393: PCI: 00:18.5 init finished in 4260 usecs
44288299.393: PCI: 00:19.0 init ...
44289299.393: PCI: 00:19.0 init finished in 1462 usecs
44290299.393: PCI: 00:19.1 init ...
44291299.393: PCI: 00:19.1 init finished in 1462 usecs
44292299.393: PCI: 00:19.2 init ...
44293299.393: PCI: 00:19.2 init finished in 1462 usecs
44294299.393: PCI: 00:19.3 init ...
44295299.393: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44296299.393: CBFS: Locating 'cmos_layout.bin'
44297299.393: CBFS: Found @ offset 2b0c0 size e88
44298299.393: done.
44299299.393: PCI: 00:19.3 init finished in 12592 usecs
44300299.393: PCI: 00:19.4 init ...
44301299.393: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44302299.393: CBFS: Locating 'cmos_layout.bin'
44303299.394: CBFS: Found @ offset 2b0c0 size e88
44304299.394: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44305299.394: CBFS: Locating 'cmos_layout.bin'
44306299.394: CBFS: Found @ offset 2b0c0 size e88
44307299.395: done.
44308299.395: PCI: 00:19.4 init finished in 21323 usecs
44309299.395: PCI: 00:19.5 init ...
44310299.395: NB: Function 5 Northbridge Control.. done.
44311299.395: PCI: 00:19.5 init finished in 4261 usecs
44312299.395: PCI: 00:1a.0 init ...
44313299.395: PCI: 00:1a.0 init finished in 1462 usecs
44314299.395: PCI: 00:1a.1 init ...
44315299.395: PCI: 00:1a.1 init finished in 1461 usecs
44316299.395: PCI: 00:1a.2 init ...
44317299.395: PCI: 00:1a.2 init finished in 1462 usecs
44318299.395: PCI: 00:1a.3 init ...
44319299.395: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44320299.395: CBFS: Locating 'cmos_layout.bin'
44321299.395: CBFS: Found @ offset 2b0c0 size e88
44322299.396: done.
44323299.396: PCI: 00:1a.3 init finished in 12593 usecs
44324299.396: PCI: 00:1a.4 init ...
44325299.396: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44326299.396: CBFS: Locating 'cmos_layout.bin'
44327299.396: CBFS: Found @ offset 2b0c0 size e88
44328299.396: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44329299.396: CBFS: Locating 'cmos_layout.bin'
44330299.396: CBFS: Found @ offset 2b0c0 size e88
44331299.397: done.
44332299.397: PCI: 00:1a.4 init finished in 21317 usecs
44333299.397: PCI: 00:1a.5 init ...
44334299.397: NB: Function 5 Northbridge Control.. done.
44335299.397: PCI: 00:1a.5 init finished in 4260 usecs
44336299.397: PCI: 00:1b.0 init ...
44337299.397: PCI: 00:1b.0 init finished in 1462 usecs
44338299.397: PCI: 00:1b.1 init ...
44339299.397: PCI: 00:1b.1 init finished in 1462 usecs
44340299.397: PCI: 00:1b.2 init ...
44341299.397: PCI: 00:1b.2 init finished in 1461 usecs
44342299.397: PCI: 00:1b.3 init ...
44343299.397: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44344299.397: CBFS: Locating 'cmos_layout.bin'
44345299.397: CBFS: Found @ offset 2b0c0 size e88
44346299.398: done.
44347299.398: PCI: 00:1b.3 init finished in 12592 usecs
44348299.398: PCI: 00:1b.4 init ...
44349299.398: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44350299.398: CBFS: Locating 'cmos_layout.bin'
44351299.398: CBFS: Found @ offset 2b0c0 size e88
44352299.399: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44353299.399: CBFS: Locating 'cmos_layout.bin'
44354299.399: CBFS: Found @ offset 2b0c0 size e88
44355299.399: done.
44356299.399: PCI: 00:1b.4 init finished in 21323 usecs
44357299.399: PCI: 00:1b.5 init ...
44358299.399: NB: Function 5 Northbridge Control.. done.
44359299.399: PCI: 00:1b.5 init finished in 4261 usecs
44360299.399: PCI: 00:00.0 init ...
44361299.399: pcie_init in sr5650_ht.c
44362299.399: IOAPIC: Initializing IOAPIC at 0xfce00000
44363299.399: IOAPIC: Bootstrap Processor Local APIC = 0x00
44364299.399: IOAPIC: ID = 0x01
44365299.399: IOAPIC: Dumping registers
44366299.399: reg 0x0000: 0x01000000
44367299.399: reg 0x0001: 0x001f8021
44368299.399: reg 0x0002: 0x00000000
44369299.399: IOAPIC: 32 interrupts
44370299.399: IOAPIC: Enabling interrupts on FSB
44371299.399: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
44372299.399: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
44373299.399: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
44374299.400: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
44375299.399: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
44376299.399: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
44377299.400: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
44378299.400: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
44379299.400: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
44380299.400: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
44381299.400: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
44382299.400: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
44383299.400: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
44384299.400: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
44385299.400: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
44386299.400: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
44387299.400: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
44388299.400: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
44389299.400: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
44390299.400: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
44391299.400: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
44392299.400: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
44393299.400: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
44394299.400: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
44395299.400: IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
44396299.400: IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
44397299.400: IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
44398299.400: IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
44399299.400: IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
44400299.400: IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
44401299.400: IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
44402299.400: IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
44403299.400: PCI: 00:00.0 init finished in 125721 usecs
44404299.400: PCI: 00:11.0 init ...
44405299.400: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44406299.400: CBFS: Locating 'cmos_layout.bin'
44407299.400: CBFS: Found @ offset 2b0c0 size e88
44408299.400: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44409299.400: CBFS: Locating 'cmos_layout.bin'
44410299.401: CBFS: Found @ offset 2b0c0 size e88
44411299.401: rev_id=15
44412299.401: sata_bar0=5020
44413299.401: sata_bar1=5040
44414299.401: sata_bar2=5028
44415299.401: sata_bar3=5044
44416299.401: sata_bar4=5000
44417299.401: sata_bar5=fcb0d000
44418299.401: ide_bar0=5030
44419299.401: ide_bar1=5048
44420299.401: ide_bar2=5038
44421299.401: ide_bar3=504c
44422299.401: Maximum SATA port count supported by silicon: 6
44423299.413: SATA port 0 status = 23
44424299.413: 0x6=a0, 0x7=80
44425299.413: drive detection not yet completed, waiting...
44426299.423: 0x6=0, 0x7=50
44427299.423: drive no longer selected after 10 ms, retrying init
44428299.423: drive detection done after 0 ms
44429299.423: AHCI device 0 is ready after 2 tries
44430299.423: SATA port 1 status = 23
44431299.423: drive detection done after 0 ms
44432299.423: AHCI device 1 is ready after 1 tries
44433299.424: SATA port 2 status = 0
44434299.424: No AHCI SATA drive on Slot2
44435299.423: SATA port 3 status = 23
44436299.423: drive detection done after 0 ms
44437299.424: AHCI device 3 is ready after 1 tries
44438299.424: SATA port 4 status = 0
44439299.424: No AHCI SATA drive on Slot4
44440299.424: SATA port 5 status = 0
44441299.424: No AHCI SATA drive on Slot5
44442299.424: PCI: 00:11.0 init finished in 85673 usecs
44443299.424: PCI: 00:12.0 init ...
44444299.424: PCI: 00:12.0 init finished in 1484 usecs
44445299.424: PCI: 00:12.1 init ...
44446299.424: PCI: 00:12.1 init finished in 1483 usecs
44447299.424: PCI: 00:12.2 init ...
44448299.424: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44449299.424: CBFS: Locating 'cmos_layout.bin'
44450299.424: CBFS: Found @ offset 2b0c0 size e88
44451299.425: usb2_bar0=0xfcb0e000
44452299.425: rpr 6.23, final dword=849e03c8
44453299.425: PCI: 00:12.2 init finished in 13779 usecs
44454299.425: PCI: 00:13.0 init ...
44455299.425: PCI: 00:13.0 init finished in 1484 usecs
44456299.425: PCI: 00:13.1 init ...
44457299.425: PCI: 00:13.1 init finished in 1485 usecs
44458299.425: PCI: 00:13.2 init ...
44459299.425: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44460299.425: CBFS: Locating 'cmos_layout.bin'
44461299.425: CBFS: Found @ offset 2b0c0 size e88
44462299.426: usb2_bar0=0xfcb0f000
44463299.426: rpr 6.23, final dword=849e03c8
44464299.426: PCI: 00:13.2 init finished in 13779 usecs
44465299.426: PCI: 00:14.0 init ...
44466299.426: sm_init().
44467299.426: IOAPIC: Initializing IOAPIC at 0xfec00000
44468299.426: IOAPIC: Bootstrap Processor Local APIC = 0x00
44469299.426: IOAPIC: Dumping registers
44470299.426: reg 0x0000: 0x00000000
44471299.426: reg 0x0001: 0x00178021
44472299.426: reg 0x0002: 0x00000000
44473299.426: IOAPIC: 24 interrupts
44474299.426: IOAPIC: Enabling interrupts on FSB
44475299.426: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
44476299.426: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
44477299.426: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
44478299.426: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
44479299.426: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
44480299.426: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
44481299.426: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
44482299.426: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
44483299.426: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
44484299.426: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
44485299.426: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
44486299.426: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
44487299.426: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
44488299.426: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
44489299.426: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
44490299.426: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
44491299.426: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
44492299.426: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
44493299.426: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
44494299.426: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
44495299.426: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
44496299.426: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
44497299.426: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
44498299.426: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
44499299.426: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44500299.426: CBFS: Locating 'cmos_layout.bin'
44501299.426: CBFS: Found @ offset 2b0c0 size e88
44502299.427: WARNING: No CMOS option 'enable_legacy_usb'.
44503299.427: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44504299.427: CBFS: Locating 'cmos_layout.bin'
44505299.427: CBFS: Found @ offset 2b0c0 size e88
44506299.427: set power "on" after power fail
44507299.427: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44508299.427: CBFS: Locating 'cmos_layout.bin'
44509299.427: CBFS: Found @ offset 2b0c0 size e88
44510299.428: ++++++++++no set NMI+++++
44511299.428: RTC Init
44512299.428: sm_init() end
44513299.428: PCI: 00:14.0 init finished in 132049 usecs
44514299.428: PCI: 00:14.1 init ...
44515299.428: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44516299.428: CBFS: Locating 'cmos_layout.bin'
44517299.428: CBFS: Found @ offset 2b0c0 size e88
44518299.429: PCI: 00:14.1 init finished in 10195 usecs
44519299.429: PCI: 00:14.2 init ...
44520299.429: base = 0xfcb04000
44521299.433: No codec!
44522299.433: PCI: 00:14.2 init finished in 6297 usecs
44523299.433: PCI: 00:14.3 init ...
44524299.433: lpc_init
44525299.433: PCI: 00:14.3 init finished in 2128 usecs
44526299.433: PCI: 00:14.4 init ...
44527299.433: PCI: 00:14.4 init finished in 1480 usecs
44528299.433: PCI: 00:14.5 init ...
44529299.433: PCI: 00:14.5 init finished in 1484 usecs
44530299.433: PCI: 03:00.0 init ...
44531299.433: PCI: 03:00.0 init finished in 1461 usecs
44532299.433: PCI: 04:00.0 init ...
44533299.433: PCI: 04:00.0 init finished in 1462 usecs
44534299.433: PCI: 07:00.0 init ...
44535299.433: PCI: 07:00.0 init finished in 1462 usecs
44536299.433: PCI: 07:00.1 init ...
44537299.433: PCI: 07:00.1 init finished in 1462 usecs
44538299.433: smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
44539299.433: Set SMBUS controller to channel 1
44540299.438: Found 64 pin W83795G Nuvoton H/W Monitor
44541299.721: W83795G/ADG work in Thermal Cruise Mode
44542299.721: Fan<09>CTFS(celsius)<09>TTTI(celsius)
44543299.724: 1<09>80<09>80
44544299.730: 2<09>80<09>80
44545299.735: 3<09>80<09>80
44546299.741: 4<09>80<09>80
44547299.746: 5<09>80<09>80
44548299.752: 6<09>80<09>80
44549299.757: DTS1 current value: 1a
44550299.760: DTS2 current value: 17
44551299.763: DTS3 current value: 0
44552299.766: DTS4 current value: 0
44553299.769: DTS5 current value: 0
44554299.771: DTS6 current value: 0
44555299.774: DTS7 current value: 0
44556299.777: DTS8 current value: 0
44557299.782: Set SMBUS controller to channel 0
44558299.782: I2C: 01:2f init finished in 283828 usecs
44559299.782: PNP: 002e.2 init ...
44560299.782: PNP: 002e.2 init finished in 1399 usecs
44561299.782: PNP: 002e.3 init ...
44562299.782: PNP: 002e.3 init finished in 1399 usecs
44563299.782: PNP: 002e.5 init ...
44564299.782: PNP: 002e.5 init finished in 1415 usecs
44565299.782: PNP: 002e.a init ...
44566299.782: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44567299.782: CBFS: Locating 'cmos_layout.bin'
44568299.782: CBFS: Found @ offset 2b0c0 size e88
44569299.783: set power on after power fail
44570299.783: PNP: 002e.a init finished in 12038 usecs
44571299.783: PNP: 002e.b init ...
44572299.783: PNP: 002e.b init finished in 1399 usecs
44573299.783: PCI: 08:01.0 init ...
44574299.783: ASpeed AST2050: initializing video device
44575299.783: ast_detect_chip: AST 1100 detected
44576299.783: ast_detect_chip: VGA not enabled on entry, requesting chip POST
44577299.783: ast_detect_chip: Analog VGA only
44578299.783: ast_driver_load: dram 800000000 0 16 00800000
44579299.804: ASpeed VGA text mode initialized
44580299.804: PCI: 08:01.0 init finished in 33444 usecs
44581299.804: PCI: 08:02.0 init ...
44582299.804: PCI: 08:02.0 init finished in 1462 usecs
44583299.804: Devices initialized
44584299.804: Show all devs... After init.
44585299.804: Root Device: enabled 1
44586299.804: CPU_CLUSTER: 0: enabled 1
44587299.804: APIC: 00: enabled 1
44588299.804: DOMAIN: 0000: enabled 1
44589299.804: PCI: 00:18.0: enabled 1
44590299.804: PCI: 00:00.0: enabled 1
44591299.804: PCI: 00:00.1: enabled 0
44592299.805: PCI: 00:00.2: enabled 1
44593299.804: PCI: 00:02.0: enabled 1
44594299.805: PCI: 00:03.0: enabled 0
44595299.805: PCI: 00:04.0: enabled 1
44596299.805: PCI: 00:05.0: enabled 0
44597299.805: PCI: 00:06.0: enabled 0
44598299.805: PCI: 00:07.0: enabled 0
44599299.805: PCI: 00:08.0: enabled 0
44600299.805: PCI: 00:09.0: enabled 1
44601299.805: PCI: 00:0a.0: enabled 1
44602299.805: PCI: 00:0b.0: enabled 1
44603299.805: PCI: 00:0c.0: enabled 1
44604299.805: PCI: 00:0d.0: enabled 1
44605299.805: PCI: 00:11.0: enabled 1
44606299.805: PCI: 00:12.0: enabled 1
44607299.805: PCI: 00:12.1: enabled 1
44608299.805: PCI: 00:12.2: enabled 1
44609299.805: PCI: 00:13.0: enabled 1
44610299.805: PCI: 00:13.1: enabled 1
44611299.805: PCI: 00:13.2: enabled 1
44612299.805: PCI: 00:14.0: enabled 1
44613299.805: I2C: 01:50: enabled 1
44614299.805: I2C: 01:51: enabled 1
44615299.805: I2C: 01:52: enabled 1
44616299.805: I2C: 01:53: enabled 1
44617299.805: I2C: 01:54: enabled 1
44618299.805: I2C: 01:55: enabled 1
44619299.805: I2C: 01:56: enabled 1
44620299.805: I2C: 01:57: enabled 1
44621299.805: I2C: 01:2f: enabled 1
44622299.805: PCI: 00:14.1: enabled 1
44623299.805: PCI: 00:14.2: enabled 1
44624299.805: PCI: 00:14.3: enabled 1
44625299.805: PNP: 002e.0: enabled 0
44626299.805: PNP: 002e.1: enabled 0
44627299.805: PNP: 002e.2: enabled 1
44628299.805: PNP: 002e.3: enabled 1
44629299.805: PNP: 002e.5: enabled 1
44630299.805: PNP: 002e.106: enabled 0
44631299.805: PNP: 002e.107: enabled 0
44632299.805: PNP: 002e.207: enabled 0
44633299.805: PNP: 002e.307: enabled 0
44634299.805: PNP: 002e.407: enabled 0
44635299.805: PNP: 002e.8: enabled 0
44636299.805: PNP: 002e.108: enabled 0
44637299.805: PNP: 002e.9: enabled 0
44638299.805: PNP: 002e.109: enabled 0
44639299.805: PNP: 002e.209: enabled 0
44640299.805: PNP: 002e.309: enabled 0
44641299.805: PNP: 002e.a: enabled 1
44642299.805: PNP: 002e.b: enabled 1
44643299.805: PNP: 002e.c: enabled 0
44644299.805: PNP: 002e.d: enabled 0
44645299.805: PNP: 002e.f: enabled 0
44646299.805: PNP: 004e.0: enabled 1
44647299.805: PCI: 00:14.4: enabled 1
44648299.805: PCI: 08:01.0: enabled 1
44649299.805: PCI: 08:02.0: enabled 1
44650299.805: PCI: 08:03.0: enabled 0
44651299.805: PCI: 00:14.5: enabled 1
44652299.805: PCI: 00:18.1: enabled 1
44653299.805: PCI: 00:18.2: enabled 1
44654299.805: PCI: 00:18.3: enabled 1
44655299.805: PCI: 00:18.4: enabled 1
44656299.805: PCI: 00:18.5: enabled 1
44657299.805: PCI: 00:19.0: enabled 1
44658299.805: PCI: 00:19.1: enabled 1
44659299.805: PCI: 00:19.2: enabled 1
44660299.805: PCI: 00:19.3: enabled 1
44661299.805: PCI: 00:19.4: enabled 1
44662299.805: PCI: 00:19.5: enabled 1
44663299.805: PCI: 00:1a.0: enabled 1
44664299.805: PCI: 00:1a.1: enabled 1
44665299.805: PCI: 00:1a.2: enabled 1
44666299.806: PCI: 00:1a.3: enabled 1
44667299.806: PCI: 00:1a.4: enabled 1
44668299.806: PCI: 00:1a.5: enabled 1
44669299.806: PCI: 00:1b.0: enabled 1
44670299.806: PCI: 00:1b.1: enabled 1
44671299.806: PCI: 00:1b.2: enabled 1
44672299.806: PCI: 00:1b.3: enabled 1
44673299.806: PCI: 00:1b.4: enabled 1
44674299.806: PCI: 00:1b.5: enabled 1
44675299.806: APIC: 01: enabled 1
44676299.806: APIC: 02: enabled 1
44677299.806: APIC: 03: enabled 1
44678299.806: APIC: 04: enabled 1
44679299.806: APIC: 05: enabled 1
44680299.806: APIC: 06: enabled 1
44681299.806: APIC: 07: enabled 1
44682299.806: APIC: 08: enabled 1
44683299.806: APIC: 09: enabled 1
44684299.806: APIC: 0a: enabled 1
44685299.806: APIC: 0b: enabled 1
44686299.806: APIC: 0c: enabled 1
44687299.806: APIC: 0d: enabled 1
44688299.806: APIC: 0e: enabled 1
44689299.806: APIC: 0f: enabled 1
44690299.806: APIC: 20: enabled 1
44691299.806: APIC: 21: enabled 1
44692299.806: APIC: 22: enabled 1
44693299.806: APIC: 23: enabled 1
44694299.806: APIC: 24: enabled 1
44695299.806: APIC: 25: enabled 1
44696299.806: APIC: 26: enabled 1
44697299.806: APIC: 27: enabled 1
44698299.806: APIC: 28: enabled 1
44699299.806: APIC: 29: enabled 1
44700299.806: APIC: 2a: enabled 1
44701299.806: APIC: 2b: enabled 1
44702299.806: APIC: 2c: enabled 1
44703299.806: APIC: 2d: enabled 1
44704299.806: APIC: 2e: enabled 1
44705299.806: APIC: 2f: enabled 1
44706299.806: PCI: 03:00.0: enabled 1
44707299.806: PCI: 04:00.0: enabled 1
44708299.806: PCI: 07:00.0: enabled 1
44709299.806: PCI: 07:00.1: enabled 1
44710299.806: BS: BS_DEV_INIT times (us): entry 0 run 3346401 exit 0
44711299.806: Finalize devices...
44712299.806: Devices finalized
44713299.806: BS: BS_POST_DEVICE times (us): entry 0 run 2547 exit 0
44714299.806: BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
44715299.806: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44716299.806: CBFS: Locating 'cmos_layout.bin'
44717299.806: CBFS: Found @ offset 2b0c0 size e88
44718299.807: Writing IRQ routing tables to 0xf0000...done.
44719299.807: Writing IRQ routing tables to 0xb7cbe000...done.
44720299.807: PIRQ table: 48 bytes.
44721299.807: Wrote the mp table end at: 000f0410 - 000f08ac
44722299.807: Wrote the mp table end at: b7cbd010 - b7cbd4ac
44723299.807: MP table: 1196 bytes.
44724299.807: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44725299.807: CBFS: Locating 'fallback/dsdt.aml'
44726299.807: CBFS: Found @ offset 2bf80 size 2608
44727299.807: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44728299.807: CBFS: Locating 'fallback/slic'
44729299.808: CBFS: 'fallback/slic' not found.
44730299.808: ACPI: Writing ACPI tables at b7c99000.
44731299.808: ACPI: * FACS
44732299.808: ACPI: * DSDT
44733299.811: ACPI: * FADT
44734299.811: pm_base: 0x0800
44735299.811: ACPI: added table 1/32, length now 40
44736299.811: ACPI: * SSDT
44737299.811: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44738299.811: CBFS: Locating 'cmos_layout.bin'
44739299.811: CBFS: Found @ offset 2b0c0 size e88
44740299.811: processor_brand=AMD Opteron(tm) Processor 6278
44741299.811: Pstates algorithm ...
44742299.812: Pstate_freq[0] = 2400MHz<09>Pstate_power[0] = 6150mw
44743299.812: Pstate_latency[0] = 5us
44744299.812: Pstate_freq[1] = 2100MHz<09>Pstate_power[1] = 5233mw
44745299.812: Pstate_latency[1] = 5us
44746299.812: Pstate_freq[2] = 1900MHz<09>Pstate_power[2] = 4620mw
44747299.812: Pstate_latency[2] = 5us
44748299.812: Pstate_freq[3] = 1600MHz<09>Pstate_power[3] = 3990mw
44749299.812: Pstate_latency[3] = 5us
44750299.812: Pstate_freq[4] = 1400MHz<09>Pstate_power[4] = 3422mw
44751299.812: Pstate_latency[4] = 5us
44752299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44753299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44754299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44755299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44756299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44757299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44758299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44759299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44760299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44761299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44762299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44763299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44764299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44765299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44766299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44767299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44768299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44769299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44770299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44771299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44772299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44773299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44774299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44775299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44776299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44777299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44778299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44779299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44780299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44781299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44782299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44783299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44784299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44785299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44786299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44787299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44788299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44789299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44790299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44791299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44792299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44793299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44794299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44795299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44796299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44797299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44798299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44799299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44800299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44801299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44802299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44803299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44804299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44805299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44806299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44807299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44808299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44809299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44810299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44811299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44812299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44813299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44814299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44815299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44816299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44817299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44818299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44819299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44820299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44821299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44822299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44823299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
44824299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
44825299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
44826299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
44827299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
44828299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44829299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44830299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44831299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44832299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44833299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44834299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44835299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44836299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44837299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44838299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44839299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44840299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44841299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44842299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44843299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44844299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44845299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44846299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44847299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44848299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44849299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44850299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44851299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44852299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44853299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44854299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44855299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44856299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44857299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44858299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44859299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44860299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44861299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44862299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44863299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44864299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44865299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44866299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44867299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44868299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44869299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44870299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44871299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44872299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44873299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44874299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44875299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44876299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44877299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44878299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44879299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44880299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44881299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44882299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44883299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44884299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44885299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44886299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44887299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44888299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44889299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44890299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44891299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44892299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44893299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44894299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44895299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44896299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44897299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44898299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44899299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44900299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44901299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44902299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44903299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44904299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44905299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44906299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44907299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
44908299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
44909299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
44910299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
44911299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
44912299.813: ACPI: added table 2/32, length now 44
44913299.813: ACPI: * MCFG
44914299.813: ACPI: added table 3/32, length now 48
44915299.813: ACPI: * TCPA
44916299.813: TCPA log created at b7c89000
44917299.813: ACPI: added table 4/32, length now 52
44918299.814: ACPI: * MADT
44919299.814: ACPI: added table 5/32, length now 56
44920299.814: current = b7c9f410
44921299.814: ACPI: * SRAT at b7c9f410
44922299.814: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
44923299.814: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
44924299.814: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
44925299.814: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
44926299.814: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
44927299.814: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
44928299.814: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
44929299.814: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
44930299.814: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
44931299.814: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
44932299.814: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
44933299.814: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
44934299.814: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
44935299.814: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
44936299.814: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
44937299.814: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
44938299.814: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
44939299.814: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
44940299.814: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
44941299.814: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
44942299.814: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
44943299.814: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
44944299.814: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
44945299.814: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
44946299.814: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
44947299.814: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
44948299.814: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
44949299.814: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
44950299.814: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
44951299.814: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
44952299.814: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
44953299.814: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
44954299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
44955299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
44956299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
44957299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
44958299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
44959299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
44960299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
44961299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
44962299.814: ACPI: added table 6/32, length now 60
44963299.814: ACPI: * SLIT at b7c9f730
44964299.814: ACPI: added table 7/32, length now 64
44965299.814: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
44966299.814: CBFS: Locating 'cmos_layout.bin'
44967299.814: CBFS: Found @ offset 2b0c0 size e88
44968299.815: ACPI: * IVRS at b7c9f770
44969299.815: Capability: type 0x01 @ 0xc8
44970299.815: Capability: type 0x05 @ 0xd0
44971299.815: Capability: type 0x10 @ 0xe0
44972299.815: Capability: type 0x01 @ 0xc8
44973299.815: Capability: type 0x05 @ 0xd0
44974299.815: Capability: type 0x10 @ 0xe0
44975299.815: Capability: type 0x01 @ 0x40
44976299.815: Capability: type 0x05 @ 0x50
44977299.815: Capability: type 0x11 @ 0x70
44978299.815: Capability: type 0x10 @ 0xa0
44979299.815: Capability: type 0x01 @ 0x40
44980299.815: Capability: type 0x05 @ 0x50
44981299.815: Capability: type 0x11 @ 0x70
44982299.815: Capability: type 0x10 @ 0xa0
44983299.815: Capability: type 0x01 @ 0x40
44984299.815: Capability: type 0x01 @ 0x44
44985299.815: ACPI: added table 8/32, length now 68
44986299.815: ACPI: * HPET
44987299.815: ACPI: added table 9/32, length now 72
44988299.815: ACPI: * SRAT at b7c9f870
44989299.815: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
44990299.815: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
44991299.815: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
44992299.815: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
44993299.815: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
44994299.815: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
44995299.815: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
44996299.815: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
44997299.815: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
44998299.815: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
44999299.815: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
45000299.815: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
45001299.815: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
45002299.815: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
45003299.815: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
45004299.815: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
45005299.815: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
45006299.815: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
45007299.815: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
45008299.815: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
45009299.815: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
45010299.815: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
45011299.815: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
45012299.815: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
45013299.815: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
45014299.815: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
45015299.815: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
45016299.815: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
45017299.815: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
45018299.815: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
45019299.815: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
45020299.815: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
45021299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
45022299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
45023299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
45024299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
45025299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
45026299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
45027299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
45028299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
45029299.815: ACPI: added table 10/32, length now 76
45030299.815: ACPI: * SLIT at b7c9fb90
45031299.815: ACPI: added table 11/32, length now 80
45032299.815: ACPI: * SRAT at b7c9fbd0
45033299.815: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
45034299.815: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
45035299.815: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
45036299.815: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
45037299.815: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
45038299.815: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
45039299.815: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
45040299.816: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
45041299.816: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
45042299.816: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
45043299.816: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
45044299.816: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
45045299.816: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
45046299.816: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
45047299.816: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
45048299.816: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
45049299.816: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
45050299.816: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
45051299.816: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
45052299.816: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
45053299.816: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
45054299.816: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
45055299.816: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
45056299.816: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
45057299.816: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
45058299.816: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
45059299.816: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
45060299.816: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
45061299.816: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
45062299.816: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
45063299.816: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
45064299.816: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
45065299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
45066299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
45067299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
45068299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
45069299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
45070299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
45071299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
45072299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
45073299.816: ACPI: added table 12/32, length now 84
45074299.816: ACPI: * SLIT at b7c9fef0
45075299.816: ACPI: added table 13/32, length now 88
45076299.816: ACPI: * SRAT at b7c9ff30
45077299.816: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
45078299.816: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
45079299.816: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
45080299.816: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
45081299.816: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
45082299.816: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
45083299.816: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
45084299.816: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
45085299.816: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
45086299.816: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
45087299.816: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
45088299.816: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
45089299.816: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
45090299.816: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
45091299.816: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
45092299.816: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
45093299.816: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
45094299.816: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
45095299.816: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
45096299.816: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
45097299.816: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
45098299.816: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
45099299.816: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
45100299.816: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
45101299.816: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
45102299.816: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
45103299.816: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
45104299.816: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
45105299.816: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
45106299.816: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
45107299.816: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
45108299.816: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
45109299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
45110299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
45111299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
45112299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
45113299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
45114299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
45115299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
45116299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
45117299.816: ACPI: added table 14/32, length now 92
45118299.816: ACPI: * SLIT at b7ca0250
45119299.816: ACPI: added table 15/32, length now 96
45120299.816: ACPI: done.
45121299.816: ACPI tables: 29328 bytes.
45122299.816: smbios_write_tables: b7c88000
45123299.816: Root Device (ASUS KGPE-D16)
45124299.816: CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
45125299.816: APIC: 00 (unknown)
45126299.816: DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
45127299.816: PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
45128299.816: PCI: 00:00.0 (ATI SR5650)
45129299.816: PCI: 00:00.1 (ATI SR5650)
45130299.816: PCI: 00:00.2 (ATI SR5650)
45131299.816: PCI: 00:02.0 (ATI SR5650)
45132299.816: PCI: 00:03.0 (ATI SR5650)
45133299.816: PCI: 00:04.0 (ATI SR5650)
45134299.816: PCI: 00:05.0 (ATI SR5650)
45135299.816: PCI: 00:06.0 (ATI SR5650)
45136299.816: PCI: 00:07.0 (ATI SR5650)
45137299.817: PCI: 00:08.0 (ATI SR5650)
45138299.817: PCI: 00:09.0 (ATI SR5650)
45139299.817: PCI: 00:0a.0 (ATI SR5650)
45140299.817: PCI: 00:0b.0 (ATI SR5650)
45141299.817: PCI: 00:0c.0 (ATI SR5650)
45142299.817: PCI: 00:0d.0 (ATI SR5650)
45143299.817: PCI: 00:11.0 (ATI SP5100)
45144299.817: PCI: 00:12.0 (ATI SP5100)
45145299.817: PCI: 00:12.1 (ATI SP5100)
45146299.817: PCI: 00:12.2 (ATI SP5100)
45147299.817: PCI: 00:13.0 (ATI SP5100)
45148299.817: PCI: 00:13.1 (ATI SP5100)
45149299.817: PCI: 00:13.2 (ATI SP5100)
45150299.817: PCI: 00:14.0 (ATI SP5100)
45151299.817: I2C: 01:50 (unknown)
45152299.817: I2C: 01:51 (unknown)
45153299.817: I2C: 01:52 (unknown)
45154299.817: I2C: 01:53 (unknown)
45155299.817: I2C: 01:54 (unknown)
45156299.817: I2C: 01:55 (unknown)
45157299.817: I2C: 01:56 (unknown)
45158299.817: I2C: 01:57 (unknown)
45159299.817: I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
45160299.817: PCI: 00:14.1 (ATI SP5100)
45161299.817: PCI: 00:14.2 (ATI SP5100)
45162299.817: PCI: 00:14.3 (ATI SP5100)
45163299.817: PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
45164299.817: PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
45165299.817: PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
45166299.817: PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
45167299.817: PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
45168299.817: PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
45169299.817: PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
45170299.817: PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
45171299.817: PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
45172299.817: PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
45173299.817: PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
45174299.817: PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
45175299.817: PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
45176299.817: PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
45177299.817: PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
45178299.817: PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
45179299.817: PNP: 002e.a (WINBOND W83667HG-A Super I/O)
45180299.817: PNP: 002e.b (WINBOND W83667HG-A Super I/O)
45181299.817: PNP: 002e.c (WINBOND W83667HG-A Super I/O)
45182299.817: PNP: 002e.d (WINBOND W83667HG-A Super I/O)
45183299.817: PNP: 002e.f (WINBOND W83667HG-A Super I/O)
45184299.817: PNP: 004e.0 (unknown)
45185299.817: PCI: 00:14.4 (ATI SP5100)
45186299.817: PCI: 08:01.0 (ATI SP5100)
45187299.817: PCI: 08:02.0 (ATI SP5100)
45188299.817: PCI: 08:03.0 (ATI SP5100)
45189299.817: PCI: 00:14.5 (ATI SP5100)
45190299.817: PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
45191299.817: PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
45192299.817: PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
45193299.817: PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
45194299.817: PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
45195299.817: PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
45196299.817: PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
45197299.817: PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
45198299.817: PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
45199299.817: PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
45200299.817: PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
45201299.817: PCI: 00:1a.0 (AMD Family 10h/15h Northbridge)
45202299.817: PCI: 00:1a.1 (AMD Family 10h/15h Northbridge)
45203299.817: PCI: 00:1a.2 (AMD Family 10h/15h Northbridge)
45204299.817: PCI: 00:1a.3 (AMD Family 10h/15h Northbridge)
45205299.817: PCI: 00:1a.4 (AMD Family 10h/15h Northbridge)
45206299.817: PCI: 00:1a.5 (AMD Family 10h/15h Northbridge)
45207299.817: PCI: 00:1b.0 (AMD Family 10h/15h Northbridge)
45208299.817: PCI: 00:1b.1 (AMD Family 10h/15h Northbridge)
45209299.817: PCI: 00:1b.2 (AMD Family 10h/15h Northbridge)
45210299.817: PCI: 00:1b.3 (AMD Family 10h/15h Northbridge)
45211299.817: PCI: 00:1b.4 (AMD Family 10h/15h Northbridge)
45212299.817: PCI: 00:1b.5 (AMD Family 10h/15h Northbridge)
45213299.817: APIC: 01 (unknown)
45214299.817: APIC: 02 (unknown)
45215299.817: APIC: 03 (unknown)
45216299.817: APIC: 04 (unknown)
45217299.817: APIC: 05 (unknown)
45218299.817: APIC: 06 (unknown)
45219299.818: APIC: 07 (unknown)
45220299.818: APIC: 08 (unknown)
45221299.818: APIC: 09 (unknown)
45222299.818: APIC: 0a (unknown)
45223299.818: APIC: 0b (unknown)
45224299.818: APIC: 0c (unknown)
45225299.818: APIC: 0d (unknown)
45226299.818: APIC: 0e (unknown)
45227299.818: APIC: 0f (unknown)
45228299.818: APIC: 20 (unknown)
45229299.818: APIC: 21 (unknown)
45230299.818: APIC: 22 (unknown)
45231299.818: APIC: 23 (unknown)
45232299.818: APIC: 24 (unknown)
45233299.818: APIC: 25 (unknown)
45234299.818: APIC: 26 (unknown)
45235299.818: APIC: 27 (unknown)
45236299.818: APIC: 28 (unknown)
45237299.818: APIC: 29 (unknown)
45238299.818: APIC: 2a (unknown)
45239299.818: APIC: 2b (unknown)
45240299.818: APIC: 2c (unknown)
45241299.818: APIC: 2d (unknown)
45242299.818: APIC: 2e (unknown)
45243299.818: APIC: 2f (unknown)
45244299.818: PCI: 03:00.0 (unknown)
45245299.818: PCI: 04:00.0 (unknown)
45246299.818: PCI: 07:00.0 (unknown)
45247299.818: PCI: 07:00.1 (unknown)
45248299.818: SMBIOS tables: 1819 bytes.
45249299.818: Writing table forward entry at 0x00000500
45250299.818: Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5812
45251299.818: Writing coreboot table at 0xb7cbf000
45252299.818: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45253299.818: CBFS: Locating 'cmos_layout.bin'
45254299.818: CBFS: Found @ offset 2b0c0 size e88
45255299.819: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
45256299.819: 1. 0000000000001000-000000000009ffff: RAM
45257299.819: 2. 00000000000a0000-00000000000bffff: RESERVED
45258299.819: 3. 00000000000c0000-00000000b7c87fff: RAM
45259299.819: 4. 00000000b7c88000-00000000b7ffffff: CONFIGURATION TABLES
45260299.819: 5. 00000000b8000000-00000000bfffffff: RAM
45261299.819: 6. 00000000c0000000-00000000cfffffff: RESERVED
45262299.819: 7. 00000000fcb00000-00000000fcb03fff: RESERVED
45263299.819: 8. 00000000feb00000-00000000feb00fff: RESERVED
45264299.819: 9. 00000000fec00000-00000000fec00fff: RESERVED
45265299.819: 10. 00000000fed00000-00000000fed00fff: RESERVED
45266299.819: 11. 0000000100000000-0000004037ffffff: RAM
45267299.819: 12. 0000004038000000-000000403fffffff: RESERVED
45268299.819: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45269299.819: CBFS: Locating 'cmos_layout.bin'
45270299.820: CBFS: Found @ offset 2b0c0 size e88
45271299.820: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45272299.820: FMAP: Found "FLASH" version 1.1 at 0.
45273299.820: FMAP: base = ff000000 size = 1000000 #areas = 3
45274299.820: Wrote coreboot table at: b7cbf000, 0x1208 bytes, checksum deaf
45275299.820: coreboot table: 4640 bytes.
45276299.820: IMD ROOT 0. b7fff000 00001000
45277299.820: IMD SMALL 1. b7ffe000 00001000
45278299.820: CAR GLOBALS 2. b7ff3000 0000a6c0
45279299.820: CONSOLE 3. b7fd3000 00020000
45280299.820: TIME STAMP 4. b7fd2000 00000400
45281299.820: AMDMEM INFO 5. b7fc8000 000093fc
45282299.820: ACPI RESUME 6. b7cc7000 00301000
45283299.820: COREBOOT 7. b7cbf000 00008000
45284299.820: IRQ TABLE 8. b7cbe000 00001000
45285299.821: SMP TABLE 9. b7cbd000 00001000
45286299.821: ACPI 10. b7c99000 00024000
45287299.821: TCPA LOG 11. b7c89000 00010000
45288299.821: SMBIOS 12. b7c88000 00000800
45289299.821: IMD small region:
45290299.821: IMD ROOT 0. b7ffec00 00000400
45291299.821: ROMSTAGE 1. b7ffebe0 00000004
45292299.821: GDT 2. b7ffe9e0 00000200
45293299.821: Writing AMD DCT configuration to Flash
45294299.823: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45295299.823: CBFS: Locating 'cmos_layout.bin'
45296299.823: CBFS: Found @ offset 2b0c0 size e88
45297299.824: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45298299.824: CBFS: Locating 'cmos_layout.bin'
45299299.824: CBFS: Found @ offset 2b0c0 size e88
45300299.825: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45301299.825: CBFS: Locating 'cmos_layout.bin'
45302299.825: CBFS: Found @ offset 2b0c0 size e88
45303299.825: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45304299.825: CBFS: Locating 'cmos_layout.bin'
45305299.825: CBFS: Found @ offset 2b0c0 size e88
45306299.826: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45307299.826: CBFS: Locating 'cmos_layout.bin'
45308299.826: CBFS: Found @ offset 2b0c0 size e88
45309299.826: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45310299.826: CBFS: Locating 'cmos_layout.bin'
45311299.826: CBFS: Found @ offset 2b0c0 size e88
45312299.827: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45313299.827: CBFS: Locating 'cmos_layout.bin'
45314299.827: CBFS: Found @ offset 2b0c0 size e88
45315299.827: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45316299.827: CBFS: Locating 'cmos_layout.bin'
45317299.827: CBFS: Found @ offset 2b0c0 size e88
45318299.828: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45319299.828: CBFS: Locating 'cmos_layout.bin'
45320299.828: CBFS: Found @ offset 2b0c0 size e88
45321299.828: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45322299.828: CBFS: Locating 'cmos_layout.bin'
45323299.829: CBFS: Found @ offset 2b0c0 size e88
45324299.829: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45325299.829: CBFS: Locating 's3nv'
45326299.829: CBFS: Found @ offset 2fec0 size 10000
45327299.829: Manufacturer: ef
45328299.829: SF: Detected W25Q128 with sector size 0x1000, total 0x1000000
45329299.831: SF: Successfully erased 32768 bytes @ 0x38000
45330300.174: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45331300.174: CBFS: Locating 'cmos_layout.bin'
45332300.174: CBFS: Found @ offset 2b0c0 size e88
45333300.175: BS: BS_WRITE_TABLES times (us): entry 0 run 1989588 exit 0
45334300.175: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
45335300.175: CBFS: Locating 'fallback/payload'
45336300.175: CBFS: Found @ offset 95600 size e920
45337300.175: Loading segment from ROM address 0xff095738
45338300.175: code (compression=1)
45339300.175: New segment dstaddr 0xe4460 memsize 0x1bba0 srcaddr 0xff095770 filesize 0xe8e8
45340300.175: Loading segment from ROM address 0xff095754
45341300.175: Entry Point 0x000ff06e
45342300.175: Bounce Buffer at bfdd1000, 2287584 bytes
45343300.175: Loading Segment: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
45344300.175: lb: [0x0000000000100000, 0x00000000002173f0)
45345300.175: Post relocation: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
45346300.176: using LZMA
45347300.203: [ 0x000e4460, 00100000, 0x00100000) <- ff095770
45348300.203: dest 000e4460, end 00100000, bouncebuffer bfdd1000
45349300.203: Loaded segments
45350300.203: BS: BS_PAYLOAD_LOAD times (us): entry 0 run 68938 exit 0
45351300.203: Jumping to boot code at 000ff06e(b7cbf000)
45352300.203: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
45353300.204: entry = 0x000ff06e
45354300.204: lb_start = 0x00100000
45355300.204: lb_size = 0x001173f0
45356300.204: buffer = 0xbfdd1000
45357300.204: SeaBIOS (version rel-1.10.0-25-g1415d46)
45358300.204: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
45359300.204: Attempting to find coreboot table
45360300.204: Found coreboot table forwarder.
45361300.204: Now attempting to find coreboot memory map
45362300.204: SeaBIOS (version rel-1.10.0-25-g1415d46)
45363300.204: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
45364300.204: Found coreboot cbmem console @ b7fd3000
45365300.204: Found mainboard ASUS KGPE-D16
45366300.204: malloc preinit
45367300.204: Relocating init from 0x000e5980 to 0xbffb4ca0 (size 45728)
45368300.204: malloc init
45369300.204: Found CBFS header at 0xff000138
45370300.204: Add romfile: cbfs master header (size=32)
45371300.204: Add romfile: fallback/romstage (size=174404)
45372300.204: Add romfile: config (size=603)
45373300.204: Add romfile: revision (size=570)
45374300.204: Add romfile: cmos.default (size=256)
45375300.205: Add romfile: cmos_layout.bin (size=3720)
45376300.205: Add romfile: fallback/dsdt.aml (size=9736)
45377300.205: Add romfile: bootorder (size=31)
45378300.205: Add romfile: (size=6168)
45379300.205: Add romfile: s3nv (size=65536)
45380300.205: Add romfile: fallback/ramstage (size=87116)
45381300.205: Add romfile: pci1106,3230.rom (size=27648)
45382300.205: Add romfile: img/coreinfo (size=109556)
45383300.205: Add romfile: img/nvramcui (size=125256)
45384300.205: Add romfile: fallback/payload (size=59680)
45385300.205: Add romfile: img/memtest (size=180268)
45386300.205: Add romfile: microcode_amd.bin (size=12684)
45387300.205: Add romfile: microcode_amd_fam15h.bin (size=7876)
45388300.205: Add romfile: vgaroms/seavgabios.bin (size=27648)
45389300.205: Add romfile: (size=15873240)
45390300.205: Add romfile: bootblock (size=3048)
45391300.205: multiboot: eax=0, ebx=0
45392300.205: init ivt
45393300.205: init bda
45394300.205: Copying romfile 'bootorder' (len 31)
45395300.205: Copying data 31@0xff02e738 to 31@0xbffb3ae0
45396300.205: boot order:
45397300.205: 1: /pci@i0cf8/*@11/drive@3/disk@0
45398300.205: 2:
45399300.205: init bios32
45400300.205: init PMM
45401300.205: init PNPBIOS table
45402300.205: init keyboard
45403300.205: init mouse
45404300.205: init pic
45405300.205: math cp init
45406300.205: PCI probe
45407300.205: PCI device 00:00.0 (vd=1002:5a10 c=0600)
45408300.205: PCI device 00:00.2 (vd=1002:5a23 c=0806)
45409300.205: PCI device 00:02.0 (vd=1002:5a16 c=0604)
45410300.205: PCI device 00:04.0 (vd=1002:5a18 c=0604)
45411300.206: PCI device 00:09.0 (vd=1002:5a1c c=0604)
45412300.205: PCI device 00:0a.0 (vd=1002:5a1d c=0604)
45413300.206: PCI device 00:0b.0 (vd=1002:5a1f c=0604)
45414300.206: PCI device 00:0c.0 (vd=1002:5a20 c=0604)
45415300.206: PCI device 00:0d.0 (vd=1002:5a1e c=0604)
45416300.206: PCI device 00:11.0 (vd=1002:4394 c=0106)
45417300.206: PCI device 00:12.0 (vd=1002:4397 c=0c03)
45418300.206: PCI device 00:12.1 (vd=1002:4398 c=0c03)
45419300.206: PCI device 00:12.2 (vd=1002:4396 c=0c03)
45420300.206: PCI device 00:13.0 (vd=1002:4397 c=0c03)
45421300.206: PCI device 00:13.1 (vd=1002:4398 c=0c03)
45422300.206: PCI device 00:13.2 (vd=1002:4396 c=0c03)
45423300.206: PCI device 00:14.0 (vd=1002:4385 c=0c05)
45424300.206: PCI device 00:14.1 (vd=1002:439c c=0101)
45425300.206: PCI device 00:14.2 (vd=1002:4383 c=0403)
45426300.206: PCI device 00:14.3 (vd=1002:439d c=0601)
45427300.206: PCI device 00:14.4 (vd=1002:4384 c=0604)
45428300.206: PCI device 00:14.5 (vd=1002:4399 c=0c03)
45429300.206: PCI device 00:18.0 (vd=1022:1600 c=0600)
45430300.206: PCI device 00:18.1 (vd=1022:1601 c=0600)
45431300.206: PCI device 00:18.2 (vd=1022:1602 c=0600)
45432300.206: PCI device 00:18.3 (vd=1022:1603 c=0600)
45433300.206: PCI device 00:18.4 (vd=1022:1604 c=0600)
45434300.206: PCI device 00:18.5 (vd=1022:1605 c=0600)
45435300.206: PCI device 00:19.0 (vd=1022:1600 c=0600)
45436300.206: PCI device 00:19.1 (vd=1022:1601 c=0600)
45437300.206: PCI device 00:19.2 (vd=1022:1602 c=0600)
45438300.206: PCI device 00:19.3 (vd=1022:1603 c=0600)
45439300.206: PCI device 00:19.4 (vd=1022:1604 c=0600)
45440300.206: PCI device 00:19.5 (vd=1022:1605 c=0600)
45441300.206: PCI device 00:1a.0 (vd=1022:1600 c=0600)
45442300.206: PCI device 00:1a.1 (vd=1022:1601 c=0600)
45443300.206: PCI device 00:1a.2 (vd=1022:1602 c=0600)
45444300.206: PCI device 00:1a.3 (vd=1022:1603 c=0600)
45445300.206: PCI device 00:1a.4 (vd=1022:1604 c=0600)
45446300.206: PCI device 00:1a.5 (vd=1022:1605 c=0600)
45447300.206: PCI device 00:1b.0 (vd=1022:1600 c=0600)
45448300.206: PCI device 00:1b.1 (vd=1022:1601 c=0600)
45449300.206: PCI device 00:1b.2 (vd=1022:1602 c=0600)
45450300.206: PCI device 00:1b.3 (vd=1022:1603 c=0600)
45451300.206: PCI device 00:1b.4 (vd=1022:1604 c=0600)
45452300.206: PCI device 00:1b.5 (vd=1022:1605 c=0600)
45453300.206: PCI device 03:00.0 (vd=8086:10d3 c=0200)
45454300.206: PCI device 04:00.0 (vd=8086:10d3 c=0200)
45455300.206: PCI device 07:00.0 (vd=8086:10fb c=0200)
45456300.206: PCI device 07:00.1 (vd=8086:10fb c=0200)
45457300.206: PCI device 08:01.0 (vd=1a03:2000 c=0300)
45458300.206: PCI device 08:02.0 (vd=11c1:5811 c=0c00)
45459300.206: Found 52 PCI devices (max PCI bus is 08)
45460300.206: Relocating coreboot bios tables
45461300.206: Copying SMBIOS entry point from 0xb7c88000 to 0x000f0c00
45462300.206: Copying ACPI RSDP from 0xb7c99000 to 0x000f0bd0
45463300.206: Skipping MPTABLE copy due to large size (1196 bytes)
45464300.206: Copying PIR from 0xb7cbe000 to 0x000f0ba0
45465300.208: rsdp=0x000f0bd0
45466300.208: rsdt=0xb7c99030
45467300.208: table(50434146)=0xb7c9b890
45468300.208: pm_tmr_blk=820
45469300.208: Using pmtimer, ioport 0x820
45470300.208: init timer
45471300.208: Scan for VGA option rom
45472300.208: Attempting to init PCI bdf 08:01.0 (vd 1a03:2000)
45473300.208: Copying data 27648@0xff0d5288 to 27648@0x000c0000
45474300.217: Running option rom at c000:0003
45475300.217: Start SeaVGABIOS (version rel-1.10.0-25-g1415d46)
45476300.217: VGABUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
45477300.217: enter vga_post:
45478300.217: a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000
45479300.217: si=00000000 di=00008020 bp=00000000 sp=00006dda cs=f000 ip=cfd0 f=0000
45480300.217: coreboot vga init
45481300.217: Found coreboot table forwarder.
45482300.217: Did not find coreboot framebuffer - assuming EGA text
45483300.217: Attempting to allocate VGA stack via pmm call to f000:d03f
45484300.217: pmm call arg1=0
45485300.217: pmm00: length=20 handle=ffffffff flags=9
45486300.217: VGA stack allocated at ef580
45487300.217: Hooking hardware timer irq (old=f000fea5 new=c0003ed0)
45488300.217: Turning on vga text mode console
45489300.217: set VGA mode 3
45490300.218: SeaBIOS (version rel-1.10.0-25-g1415d46)
45491300.218: init usb
45492300.218: EHCI init on dev 00:12.2 (regs=0xfcb0e020)
45493300.218: /bffb1000\ Start thread
45494300.218: EHCI init on dev 00:13.2 (regs=0xfcb0f020)
45495300.218: /bffb0000\ Start thread
45496300.218: OHCI init on dev 00:12.0 (regs=0xfcb08000)
45497300.218: /bffaf000\ Start thread
45498300.218: OHCI init on dev 00:12.1 (regs=0xfcb09000)
45499300.218: /bffae000\ Start thread
45500300.218: OHCI init on dev 00:13.0 (regs=0xfcb0a000)
45501300.218: /bffad000\ Start thread
45502300.218: /bffac000\ Start thread
45503300.219: \bffac000/ End thread
45504300.219: OHCI init on dev 00:13.1 (regs=0xfcb0b000)
45505300.219: /bffac000\ Start thread
45506300.219: /bffab000\ Start thread
45507300.219: /bffaa000\ Start thread
45508300.219: OHCI init on dev 00:14.5 (regs=0xfcb0c000)
45509300.219: /bffa9000\ Start thread
45510300.219: /bffa8000\ Start thread
45511300.219: /bffa7000\ Start thread
45512300.219: init ps2port
45513300.219: /bffa6000\ Start thread
45514300.222: /bffa5000\ Start thread
45515300.222: /bffa3000\ Start thread
45516300.222: init ahci
45517300.222: AHCI controller at 00:11.0, iobase 0xfcb0d000, irq 0
45518300.222: AHCI: cap 0xf322ff85, ports_impl 0x3f
45519300.222: /bffa2000\ Start thread
45520300.222: |bffa2000| AHCI/0: probing
45521300.222: |bffa2000| AHCI/0: link up
45522300.222: /bffa1000\ Start thread
45523300.222: /bffa0000\ Start thread
45524300.222: /bff9f000\ Start thread
45525300.222: |bff9f000| AHCI/1: probing
45526300.222: |bff9f000| AHCI/1: link up
45527300.222: |bffa2000| AHCI/0: ... finished, status 0x51, ERROR 0x4
45528300.222: /bff9d000\ Start thread
45529300.222: /bff9c000\ Start thread
45530300.222: /bff9b000\ Start thread
45531300.223: /bff9a000\ Start thread
45532300.223: /bff99000\ Start thread
45533300.223: /bff98000\ Start thread
45534300.223: |bff98000| AHCI/2: probing
45535300.223: |bff9f000| AHCI/1: ... finished, status 0x51, ERROR 0x4
45536300.223: |bffa2000| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
45537300.223: |bffa2000| AHCI/0: supported modes: udma 6, multi-dma 2, pio 4
45538300.223: |bffa2000| AHCI/0: Set transfer mode to UDMA-6
45539300.223: /bff97000\ Start thread
45540300.223: /bff96000\ Start thread
45541300.223: /bff95000\ Start thread
45542300.223: /bff94000\ Start thread
45543300.223: |bff9b000| set_address 0xbffb2730
45544300.223: /bff93000\ Start thread
45545300.223: \bff93000/ End thread
45546300.223: \bff9a000/ End thread
45547300.223: \bffa1000/ End thread
45548300.223: \bffa5000/ End thread
45549300.223: \bffa8000/ End thread
45550300.223: \bffab000/ End thread
45551300.223: \bff99000/ End thread
45552300.223: \bffa0000/ End thread
45553300.223: \bffa3000/ End thread
45554300.223: \bffa7000/ End thread
45555300.223: \bffaa000/ End thread
45556300.223: /bffaa000\ Start thread
45557300.223: |bffaa000| AHCI/3: probing
45558300.223: |bffaa000| AHCI/3: link up
45559300.223: |bff98000| AHCI/2: link down
45560300.223: |bff9f000| Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0
45561300.223: |bff9f000| AHCI/1: supported modes: udma 6, multi-dma 2, pio 4
45562300.223: |bff9f000| AHCI/1: Set transfer mode to UDMA-6
45563300.223: /bffa8000\ Start thread
45564300.223: /bffa7000\ Start thread
45565300.223: /bffa5000\ Start thread
45566300.223: \bffa5000/ End thread
45567300.223: \bff96000/ End thread
45568300.223: \bff9d000/ End thread
45569300.223: /bffa5000\ Start thread
45570300.223: \bffa5000/ End thread
45571300.223: \bff95000/ End thread
45572300.223: \bff9c000/ End thread
45573300.223: /bffa5000\ Start thread
45574300.223: \bffa5000/ End thread
45575300.223: \bff94000/ End thread
45576300.223: /bffa5000\ Start thread
45577300.223: |bffa5000| AHCI/4: probing
45578300.223: |bffaa000| AHCI/3: ... finished, status 0x51, ERROR 0x4
45579300.223: \bff98000/ End thread
45580300.223: |bffa2000| AHCI/0: registering: "AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
45581300.223: |bffa2000| Registering bootable: AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0b30)
45582300.223: \bffa2000/ End thread
45583300.223: /bffa3000\ Start thread
45584300.223: /bffa2000\ Start thread
45585300.223: \bffa2000/ End thread
45586300.223: \bffa7000/ End thread
45587300.223: \bff97000/ End thread
45588300.223: /bffa2000\ Start thread
45589300.223: |bffa2000| AHCI/5: probing
45590300.224: |bffa5000| AHCI/4: link down
45591300.224: |bffaa000| Searching bootorder for: /pci@i0cf8/*@11/drive@3/disk@0
45592300.224: |bffaa000| AHCI/3: supported modes: udma 6, multi-dma 2, pio 4
45593300.224: |bffaa000| AHCI/3: Set transfer mode to UDMA-6
45594300.224: |bff9f000| AHCI/1: registering: "AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
45595300.224: |bff9f000| Registering bootable: AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0ae0)
45596300.224: \bff9f000/ End thread
45597300.224: \bffa3000/ End thread
45598300.224: \bffa8000/ End thread
45599300.224: \bffad000/ End thread
45600300.224: \bffae000/ End thread
45601300.224: |bff9b000| config_usb: 0xbffab9b0
45602300.224: \bffb0000/ End thread
45603300.224: \bffb1000/ End thread
45604300.224: init lpt
45605300.224: Found 0 lpt ports
45606300.224: init serial
45607300.224: Found 2 serial ports
45608300.224: Searching bootorder for: /rom@img/memtest
45609300.224: Registering bootable: Payload [memtest] (type:32 prio:9999 data:ff0a4080)
45610300.224: Searching bootorder for: /rom@img/nvramcui
45611300.224: Registering bootable: Payload [nvramcui] (type:32 prio:9999 data:ff076d80)
45612300.224: Searching bootorder for: /rom@img/coreinfo
45613300.224: Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ff05c140)
45614300.224: |bffa2000| AHCI/5: link down
45615300.224: \bffa5000/ End thread
45616300.224: \bffac000/ End thread
45617300.224: |bff9b000| device rev=0110 cls=00 sub=00 proto=00 size=8
45618300.224: \bffa2000/ End thread
45619300.224: |bffaa000| AHCI/3: registering: "AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes)"
45620300.224: |bffaa000| Registering bootable: AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes) (type:2 prio:1 data:f0a90)
45621300.224: \bffaa000/ End thread
45622300.224: \bffa9000/ End thread
45623300.226: |bff9b000| usb_hid_setup 0xbffab9b0
45624300.227: |bff9b000| USB keyboard initialized
45625300.227: \bff9b000/ End thread
45626300.228: \bffaf000/ End thread
45627300.354: |bffa6000| PS2 keyboard initialized
45628300.354: \bffa6000/ End thread
45629300.354: All threads complete.
45630300.354: Scan for option roms
45631300.354: Attempting to init PCI bdf 00:00.0 (vd 1002:5a10)
45632300.354: Attempting to init PCI bdf 00:00.2 (vd 1002:5a23)
45633300.354: Attempting to init PCI bdf 00:02.0 (vd 1002:5a16)
45634300.354: Attempting to init PCI bdf 00:04.0 (vd 1002:5a18)
45635300.354: Attempting to init PCI bdf 00:09.0 (vd 1002:5a1c)
45636300.354: Attempting to init PCI bdf 00:0a.0 (vd 1002:5a1d)
45637300.354: Attempting to init PCI bdf 00:0b.0 (vd 1002:5a1f)
45638300.354: Attempting to init PCI bdf 00:0c.0 (vd 1002:5a20)
45639300.354: Attempting to init PCI bdf 00:0d.0 (vd 1002:5a1e)
45640300.354: Attempting to init PCI bdf 00:14.0 (vd 1002:4385)
45641300.354: Attempting to init PCI bdf 00:14.1 (vd 1002:439c)
45642300.354: Attempting to init PCI bdf 00:14.2 (vd 1002:4383)
45643300.354: Attempting to init PCI bdf 00:14.3 (vd 1002:439d)
45644300.354: Attempting to init PCI bdf 00:14.4 (vd 1002:4384)
45645300.354: Attempting to init PCI bdf 00:18.0 (vd 1022:1600)
45646300.354: Attempting to init PCI bdf 00:18.1 (vd 1022:1601)
45647300.354: Attempting to init PCI bdf 00:18.2 (vd 1022:1602)
45648300.354: Attempting to init PCI bdf 00:18.3 (vd 1022:1603)
45649300.354: Attempting to init PCI bdf 00:18.4 (vd 1022:1604)
45650300.354: Attempting to init PCI bdf 00:18.5 (vd 1022:1605)
45651300.354: Attempting to init PCI bdf 00:19.0 (vd 1022:1600)
45652300.354: Attempting to init PCI bdf 00:19.1 (vd 1022:1601)
45653300.354: Attempting to init PCI bdf 00:19.2 (vd 1022:1602)
45654300.354: Attempting to init PCI bdf 00:19.3 (vd 1022:1603)
45655300.354: Attempting to init PCI bdf 00:19.4 (vd 1022:1604)
45656300.354: Attempting to init PCI bdf 00:19.5 (vd 1022:1605)
45657300.354: Attempting to init PCI bdf 00:1a.0 (vd 1022:1600)
45658300.354: Attempting to init PCI bdf 00:1a.1 (vd 1022:1601)
45659300.354: Attempting to init PCI bdf 00:1a.2 (vd 1022:1602)
45660300.354: Attempting to init PCI bdf 00:1a.3 (vd 1022:1603)
45661300.354: Attempting to init PCI bdf 00:1a.4 (vd 1022:1604)
45662300.354: Attempting to init PCI bdf 00:1a.5 (vd 1022:1605)
45663300.354: Attempting to init PCI bdf 00:1b.0 (vd 1022:1600)
45664300.354: Attempting to init PCI bdf 00:1b.1 (vd 1022:1601)
45665300.354: Attempting to init PCI bdf 00:1b.2 (vd 1022:1602)
45666300.354: Attempting to init PCI bdf 00:1b.3 (vd 1022:1603)
45667300.354: Attempting to init PCI bdf 00:1b.4 (vd 1022:1604)
45668300.354: Attempting to init PCI bdf 00:1b.5 (vd 1022:1605)
45669300.354: Attempting to init PCI bdf 03:00.0 (vd 8086:10d3)
45670300.354: Attempting to init PCI bdf 04:00.0 (vd 8086:10d3)
45671300.354: Attempting to init PCI bdf 07:00.0 (vd 8086:10fb)
45672300.354: Attempting to init PCI bdf 07:00.1 (vd 8086:10fb)
45673300.354: Attempting to init PCI bdf 08:02.0 (vd 11c1:5811)
45674300.354:
45675300.354: Press ESC for boot menu.
45676300.354:
45677300.354: Checking for bootsplash
45678301.390: Select boot device:
45679301.390:
45680301.390: 1. AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiByte
45681301.390: 2. AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
45682301.390: 3. AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
45683301.390: 4. Payload [memtest]
45684301.390: 5. Payload [nvramcui]
45685301.390: 6. Payload [coreinfo]
45686302.793:
45687302.793: Searching bootorder for: HALT
45688302.793: Mapping hd drive 0x000f0a90 to 0
45689302.793: drive 0x000f0a90: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
45690302.793: Mapping hd drive 0x000f0b30 to 1
45691302.793: drive 0x000f0b30: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
45692302.793: Mapping hd drive 0x000f0ae0 to 2
45693302.793: drive 0x000f0ae0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
45694302.793: finalize PMM
45695302.793: malloc finalize
45696302.794: Space available for UMB: c7000-ee800, f0000-f0a90
45697302.794: Returned 245760 bytes of ZoneHigh
45698302.794: e820 map has 13 items:
45699302.794: 0: 0000000000000000 - 000000000009fc00 = 1 RAM
45700302.794: 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
45701302.794: 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
45702302.794: 3: 0000000000100000 - 00000000b7c88000 = 1 RAM
45703302.794: 4: 00000000b7c88000 - 00000000b8000000 = 2 RESERVED
45704302.794: 5: 00000000b8000000 - 00000000bfffc000 = 1 RAM
45705302.794: 6: 00000000bfffc000 - 00000000d0000000 = 2 RESERVED
45706302.794: 7: 00000000fcb00000 - 00000000fcb04000 = 2 RESERVED
45707302.794: 8: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
45708302.794: 9: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
45709302.794: 10: 00000000fed00000 - 00000000fed01000 = 2 RESERVED
45710302.794: 11: 0000000100000000 - 0000004038000000 = 1 RAM
45711302.794: 12: 0000004038000000 - 0000004040000000 = 2 RESERVED
45712302.795: Jump to int19
45713302.795: enter handle_19:
45714302.795: NULL
45715302.795: Booting from Hard Disk...
45716302.808: Booting from 0000:7c00
45717305.206: handle_hwpic1 irq=1