| |
| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| cd01860 |
| SRFTP [46a4] = 41f88200 |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 3 |
| PCI(0, 0, 0)[bc] = 8ea00000 |
| PCI(0, 0, 0)[a8] = 71600000 |
| PCI(0, 0, 0)[ac] = 3 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| Done memory map |
| RCOMP...done |
| COMP2 done |
| COMP1 done |
| FORCE RCOMP and wait 20us...done |
| Done io registers |
| CPE |
| CP5b |
| CP5c |
| OTHP [400c] = 8b4 |
| OTHP [440c] = 8b4 |
| t123: 1767, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| ME: Wrong mode : 2 |
| ME: FWS2: 0x100a0140 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| PASSED! Tell ME that DRAM is ready |
| ME: ME is reporting as disabled, so not waiting for a response. |
| ME: FWS2: 0x100a0140 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: No DID Ack received |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1596 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00600010): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 4096 MB width x8 single rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ 7ffff000 254 entries. |
| IMD: root @ 7fffec00 62 entries. |
| CBMEM entry for DIMM info: 0x7fffe960 |
| POST: 0x3b |
| POST: 0x3c |
| POST: 0x3d |
| TPM initialization. |
| TPM: Init |
| Found TPM SLB9635 TT 1.2 by Infineon |
| TPM: Open |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: OK. |
| POST: 0x3f |
| MTRR Range: Start=ff000000 End=0 (Size 1000000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1b580 |
| CBFS: Checking offset 1e940 |
| CBFS: File @ offset 1e940 size 6a4 |
| CBFS: Unmatched 'payload_config' at 1e940 |
| CBFS: Checking offset 1f040 |
| CBFS: File @ offset 1f040 size ea |
| CBFS: Unmatched 'payload_revision' at 1f040 |
| CBFS: Checking offset 1f180 |
| CBFS: File @ offset 1f180 size d18 |
| CBFS: Unmatched '' at 1f180 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 16ad1 |
| CBFS: Found @ offset 2ff00 size 16ad1 |
| Decompressing stage fallback/ramstage @ 0x7ff93fc0 (276656 bytes) |
| Loading module at 7ff94000 with entry 7ff94000. filesize: 0x31330 memsize: 0x43870 |
| Processing 3057 relocs. Offset value of 0x7fe94000 |
| |
| |
| coreboot-4.6-2553-g1291c44abd-dirty Fri Jan 12 21:13:21 UTC 2018 ramstage starting... |
| POST: 0x39 |
| POST: 0x80 |
| Normal boot. |
| POST: 0x70 |
| BS: BS_PRE_DEVICE times (us): entry 0 run 3 exit 0 |
| POST: 0x71 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4 exit 0 |
| POST: 0x72 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 00ff.1: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 00ff.1: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| POST: 0x24 |
| PCI: 00:00.0 [8086/0154] ops |
| PCI: 00:00.0 [8086/0154] enabled |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| PCI: 00:01.0 subordinate bus PCI Express |
| PCI: 00:01.0 [8086/0151] disabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0166] enabled |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3870 |
| memalign 7ffd3870 |
| PCI: 00:04.0 [8086/0153] enabled |
| PCI: 00:14.0 [8086/0000] ops |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 [8086/1e3a] ops |
| PCI: 00:16.0 [8086/1e3a] disabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0 [8086/1502] enabled |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1e10] enabled |
| PCI: 00:1c.1: Disabling device |
| PCH: Remap PCIe function 2 to 1 |
| PCI: 00:1c.2 [8086/0000] bus ops |
| PCI: 00:1c.2 [8086/1e14] enabled |
| PCH: Remap PCIe function 3 to 1 |
| PCI: 00:1c.3 [8086/0000] bus ops |
| PCI: 00:1c.3 [8086/1e16] enabled |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.4: check set enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfedc21b0 |
| PCH: PCIe map 1c.1 -> 1c.3 |
| PCH: PCIe map 1c.2 -> 1c.1 |
| PCH: PCIe map 1c.3 -> 1c.2 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1e26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1e55] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Found @ offset 1b080 size 4ac |
| PCI: 00:1f.2 [8086/1e01] enabled |
| PCI: 00:1f.3: Disabling device |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.6: Disabling device |
| POST: 0x25 |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3908 |
| memalign 7ffd3908 |
| PCI: pci_scan_bus for bus 01 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 59 usecs |
| PCI: 00:1c.1 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.1 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd392c |
| memalign 7ffd3930 |
| PCI: pci_scan_bus for bus 02 |
| POST: 0x24 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3954 |
| memalign 7ffd3958 |
| PCI: 02:00.0 [197b/2392] enabled |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd39f0 |
| memalign 7ffd39f0 |
| PCI: 02:00.2 [197b/2391] enabled |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3a88 |
| memalign 7ffd3a88 |
| PCI: 02:00.3 [197b/2393] enabled |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3b20 |
| memalign 7ffd3b20 |
| PCI: 02:00.4 [197b/2394] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.0 |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.2 |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.3 |
| Capability: type 0x01 @ 0xa4 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.4 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3bb8 |
| memalign 7ffd3bb8 |
| scan_bus: scanning of bus PCI: 00:1c.1 took 752 usecs |
| PCI: 00:1c.2 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.2 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3c50 |
| memalign 7ffd3c50 |
| PCI: pci_scan_bus for bus 03 |
| POST: 0x24 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3c74 |
| memalign 7ffd3c78 |
| PCI: 03:00.0 [168c/0034] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Failed to enable LTR for dev = PCI: 03:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.2 took 248 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| KBC1126: initialize fan control.KBC1126: fan control initialized. |
| PNP: 00ff.1 disabled |
| memalign Enter, boundary 8, size 2560, free_mem_ptr 7ffd3d10 |
| memalign 7ffd3d10 |
| PNP: 0c31.0 enabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 7619 usecs |
| POST: 0x55 |
| scan_bus: scanning of bus DOMAIN: 0000 took 9125 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 9135 usecs |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 9262 exit 0 |
| POST: 0x73 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. |
| PCI: 00:1c.0 read_resources bus 1 link: 0 |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.1 read_resources bus 2 link: 0 |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| PCI: 00:1c.2 read_resources bus 3 link: 0 |
| PCI: 00:1c.2 read_resources bus 3 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1c.3 |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 |
| PCI: 02:00.2 |
| PCI: 02:00.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 02:00.3 |
| PCI: 02:00.3 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 02:00.4 |
| PCI: 02:00.4 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| NONE |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 |
| NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 |
| PCI: 00:1c.2 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10 |
| PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base fe00 size fc align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PNP: 00ff.1 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:19.0 18 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 20 * [0x1060 - 0x107f] io |
| PCI: 00:1f.2 10 * [0x1080 - 0x1087] io |
| PCI: 00:1f.2 18 * [0x1088 - 0x108f] io |
| PCI: 00:1f.2 14 * [0x1090 - 0x1093] io |
| PCI: 00:1f.2 1c * [0x1094 - 0x1097] io |
| DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.1 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 02:00.0 30 * [0x800000 - 0x80ffff] mem |
| PCI: 02:00.0 10 * [0x810000 - 0x8100ff] mem |
| PCI: 02:00.2 10 * [0x811000 - 0x8110ff] mem |
| PCI: 02:00.3 10 * [0x812000 - 0x8120ff] mem |
| PCI: 02:00.4 10 * [0x813000 - 0x8130ff] mem |
| PCI: 00:1c.1 mem: base: 813100 size: 900000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 03:00.0 10 * [0x0 - 0x7ffff] mem |
| PCI: 03:00.0 30 * [0x80000 - 0x8ffff] mem |
| PCI: 00:1c.2 mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:1c.1 20 * [0x10000000 - 0x108fffff] mem |
| PCI: 00:1c.1 24 * [0x10c00000 - 0x113fffff] prefmem |
| PCI: 00:02.0 10 * [0x11400000 - 0x117fffff] mem |
| PCI: 00:1c.2 20 * [0x11800000 - 0x118fffff] mem |
| PCI: 00:19.0 10 * [0x11900000 - 0x1191ffff] mem |
| PCI: 00:14.0 10 * [0x11920000 - 0x1192ffff] mem |
| PCI: 00:04.0 10 * [0x11930000 - 0x11937fff] mem |
| PCI: 00:1b.0 10 * [0x11938000 - 0x1193bfff] mem |
| PCI: 00:19.0 14 * [0x1193c000 - 0x1193cfff] mem |
| PCI: 00:1f.2 24 * [0x1193d000 - 0x1193d7ff] mem |
| PCI: 00:1a.0 10 * [0x1193e000 - 0x1193e3ff] mem |
| PCI: 00:1d.0 10 * [0x1193f000 - 0x1193f3ff] mem |
| DOMAIN: 0000 mem: base: 1193f400 size: 1193f400 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f8000000 limit fbffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| constrain_resources: PCI: 00:1f.0 10000200 base 0000fe00 limit 0000fefb io (fixed) |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000fdff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:1000 size:1098 align:12 gran:0 limit:fdff |
| PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io |
| PCI: 00:02.0 20 * [0x2000 - 0x203f] io |
| PCI: 00:19.0 18 * [0x2040 - 0x205f] io |
| PCI: 00:1f.2 20 * [0x2060 - 0x207f] io |
| PCI: 00:1f.2 10 * [0x2080 - 0x2087] io |
| PCI: 00:1f.2 18 * [0x2088 - 0x208f] io |
| PCI: 00:1f.2 14 * [0x2090 - 0x2093] io |
| PCI: 00:1f.2 1c * [0x2094 - 0x2097] io |
| DOMAIN: 0000 io: next_base: 2098 size: 1098 align: 12 gran: 0 done |
| PCI: 00:1c.0 io: base:fdff size:0 align:12 gran:12 limit:fdff |
| PCI: 00:1c.0 io: next_base: fdff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.1 io: base:1000 size:1000 align:12 gran:12 limit:1fff |
| NONE 18 * [0x1000 - 0x1fff] io |
| PCI: 00:1c.1 io: next_base: 2000 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1c.2 io: base:fdff size:0 align:12 gran:12 limit:fdff |
| PCI: 00:1c.2 io: next_base: fdff size: 0 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:e0000000 size:1193f400 align:28 gran:0 limit:f7ffffff |
| PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem |
| PCI: 00:1c.1 20 * [0xf0000000 - 0xf08fffff] mem |
| PCI: 00:1c.1 24 * [0xf0c00000 - 0xf13fffff] prefmem |
| PCI: 00:02.0 10 * [0xf1400000 - 0xf17fffff] mem |
| PCI: 00:1c.2 20 * [0xf1800000 - 0xf18fffff] mem |
| PCI: 00:19.0 10 * [0xf1900000 - 0xf191ffff] mem |
| PCI: 00:14.0 10 * [0xf1920000 - 0xf192ffff] mem |
| PCI: 00:04.0 10 * [0xf1930000 - 0xf1937fff] mem |
| PCI: 00:1b.0 10 * [0xf1938000 - 0xf193bfff] mem |
| PCI: 00:19.0 14 * [0xf193c000 - 0xf193cfff] mem |
| PCI: 00:1f.2 24 * [0xf193d000 - 0xf193d7ff] mem |
| PCI: 00:1a.0 10 * [0xf193e000 - 0xf193e3ff] mem |
| PCI: 00:1d.0 10 * [0xf193f000 - 0xf193f3ff] mem |
| DOMAIN: 0000 mem: next_base: f193f400 size: 1193f400 align: 28 gran: 0 done |
| PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.1 prefmem: base:f0c00000 size:800000 align:22 gran:20 limit:f13fffff |
| NONE 14 * [0xf0c00000 - 0xf13fffff] prefmem |
| PCI: 00:1c.1 prefmem: next_base: f1400000 size: 800000 align: 22 gran: 20 done |
| PCI: 00:1c.1 mem: base:f0000000 size:900000 align:22 gran:20 limit:f08fffff |
| NONE 10 * [0xf0000000 - 0xf07fffff] mem |
| PCI: 02:00.0 30 * [0xf0800000 - 0xf080ffff] mem |
| PCI: 02:00.0 10 * [0xf0810000 - 0xf08100ff] mem |
| PCI: 02:00.2 10 * [0xf0811000 - 0xf08110ff] mem |
| PCI: 02:00.3 10 * [0xf0812000 - 0xf08120ff] mem |
| PCI: 02:00.4 10 * [0xf0813000 - 0xf08130ff] mem |
| PCI: 00:1c.1 mem: next_base: f0813100 size: 900000 align: 22 gran: 20 done |
| PCI: 00:1c.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.2 mem: base:f1800000 size:100000 align:20 gran:20 limit:f18fffff |
| PCI: 03:00.0 10 * [0xf1800000 - 0xf187ffff] mem |
| PCI: 03:00.0 30 * [0xf1880000 - 0xf188ffff] mem |
| PCI: 00:1c.2 mem: next_base: f1890000 size: 100000 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x371600000 TOLUD 0x8ea00000 TOM 0x300000000 |
| MEBASE 0x7ffff00000 |
| IGD decoded, subtracting 224M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 10006M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:02.0 10 <- [0x00f1400000 - 0x00f17fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x00f1930000 - 0x00f1937fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:14.0 10 <- [0x00f1920000 - 0x00f192ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:19.0 10 <- [0x00f1900000 - 0x00f191ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00f193c000 - 0x00f193cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 10 <- [0x00f193e000 - 0x00f193e3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00f1938000 - 0x00f193bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:1c.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00f0c00000 - 0x00f13fffff] size 0x00800000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00f0000000 - 0x00f08fffff] size 0x00900000 gran 0x14 bus 02 mem |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 02:00.0 10 <- [0x00f0810000 - 0x00f08100ff] size 0x00000100 gran 0x08 mem |
| PCI: 02:00.0 30 <- [0x00f0800000 - 0x00f080ffff] size 0x00010000 gran 0x10 romem |
| PCI: 02:00.2 10 <- [0x00f0811000 - 0x00f08110ff] size 0x00000100 gran 0x08 mem |
| PCI: 02:00.3 10 <- [0x00f0812000 - 0x00f08120ff] size 0x00000100 gran 0x08 mem |
| PCI: 02:00.4 10 <- [0x00f0813000 - 0x00f08130ff] size 0x00000100 gran 0x08 mem |
| NONE missing set_resources |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.2 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.2 20 <- [0x00f1800000 - 0x00f18fffff] size 0x00100000 gran 0x14 bus 03 mem |
| PCI: 00:1c.2 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x00f1800000 - 0x00f187ffff] size 0x00080000 gran 0x13 mem64 |
| PCI: 03:00.0 30 <- [0x00f1880000 - 0x00f188ffff] size 0x00010000 gran 0x10 romem |
| PCI: 00:1c.2 assign_resources, bus 3 link: 0 |
| PCI: 00:1d.0 10 <- [0x00f193f000 - 0x00f193f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000002080 - 0x0000002087] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000002090 - 0x0000002093] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000002088 - 0x000000208f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000002094 - 0x0000002097] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00f193d000 - 0x00f193d7ff] size 0x00000800 gran 0x0b mem |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 1000 size 1098 align 12 gran 0 limit fdff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base e0000000 size 1193f400 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 271600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base 80000000 size ea00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base f1400000 size 400000 align 22 gran 22 limit f17fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base f1930000 size 8000 align 15 gran 15 limit f1937fff flags 60000201 index 10 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base f1920000 size 10000 align 16 gran 16 limit f192ffff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base f1900000 size 20000 align 17 gran 17 limit f191ffff flags 60000200 index 10 |
| PCI: 00:19.0 resource base f193c000 size 1000 align 12 gran 12 limit f193cfff flags 60000200 index 14 |
| PCI: 00:19.0 resource base 2040 size 20 align 5 gran 5 limit 205f flags 60000100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base f193e000 size 400 align 12 gran 10 limit f193e3ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base f1938000 size 4000 align 14 gran 14 limit f193bfff flags 60000201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base fdff size 0 align 12 gran 12 limit fdff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 00:1c.3 |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.1 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c |
| PCI: 00:1c.1 resource base f0c00000 size 800000 align 22 gran 20 limit f13fffff flags 60081202 index 24 |
| PCI: 00:1c.1 resource base f0000000 size 900000 align 22 gran 20 limit f08fffff flags 60080202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base f0810000 size 100 align 12 gran 8 limit f08100ff flags 60000200 index 10 |
| PCI: 02:00.0 resource base f0800000 size 10000 align 16 gran 16 limit f080ffff flags 60002200 index 30 |
| PCI: 02:00.2 |
| PCI: 02:00.2 resource base f0811000 size 100 align 12 gran 8 limit f08110ff flags 60000200 index 10 |
| PCI: 02:00.3 |
| PCI: 02:00.3 resource base f0812000 size 100 align 12 gran 8 limit f08120ff flags 60000200 index 10 |
| PCI: 02:00.4 |
| PCI: 02:00.4 resource base f0813000 size 100 align 12 gran 8 limit f08130ff flags 60000200 index 10 |
| NONE |
| NONE resource base f0000000 size 800000 align 22 gran 22 limit f07fffff flags 40000200 index 10 |
| NONE resource base f0c00000 size 800000 align 22 gran 22 limit f13fffff flags 40001200 index 14 |
| NONE resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 40000100 index 18 |
| PCI: 00:1c.2 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.2 resource base fdff size 0 align 12 gran 12 limit fdff flags 60080102 index 1c |
| PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:1c.2 resource base f1800000 size 100000 align 20 gran 20 limit f18fffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base f1800000 size 80000 align 19 gran 19 limit f187ffff flags 60000201 index 10 |
| PCI: 03:00.0 resource base f1880000 size 10000 align 16 gran 16 limit f188ffff flags 60002200 index 30 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base f193f000 size 400 align 12 gran 10 limit f193f3ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base fe00 size fc align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PNP: 00ff.1 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 2080 size 8 align 3 gran 3 limit 2087 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 2090 size 4 align 2 gran 2 limit 2093 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 2088 size 8 align 3 gran 3 limit 208f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 2094 size 4 align 2 gran 2 limit 2097 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 2060 size 20 align 5 gran 5 limit 207f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base f193d000 size 800 align 12 gran 11 limit f193d7ff flags 60000200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2747 exit 0 |
| POST: 0x74 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 103c/18f8 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 103c/18f8 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:14.0 subsystem <- 103c/18f8 |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:19.0 subsystem <- 8086/18f8 |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 103c/18f8 |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 103c/18f8 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 103c/18f8 |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 103c/18f8 |
| PCI: 00:1c.1 cmd <- 107 |
| PCI: 00:1c.2 bridge ctrl <- 0003 |
| PCI: 00:1c.2 subsystem <- 103c/18f8 |
| PCI: 00:1c.2 cmd <- 106 |
| PCI: 00:1d.0 subsystem <- 103c/18f8 |
| PCI: 00:1d.0 cmd <- 102 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 103c/18f8 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 103c/18f8 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 02:00.0 cmd <- 06 |
| PCI: 02:00.2 cmd <- 06 |
| PCI: 02:00.3 cmd <- 06 |
| PCI: 02:00.4 cmd <- 06 |
| PCI: 03:00.0 cmd <- 02 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 144 exit 0 |
| read 6000 from 07e4 |
| wrote 00000004 to 0890 |
| read 03040003 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| POST: 0x75 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 1 usecs |
| POST: 0x75 |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 12 relocs. Offset value of 0x00038000 |
| Adjusting 00038002: 0x00000024 -> 0x00038024 |
| Adjusting 0003801d: 0x0000003c -> 0x0003803c |
| Adjusting 00038026: 0x00000024 -> 0x00038024 |
| Adjusting 00038054: 0x00000120 -> 0x00038120 |
| Adjusting 00038066: 0x000001a8 -> 0x000381a8 |
| Adjusting 0003806f: 0x00000100 -> 0x00038100 |
| Adjusting 00038077: 0x00000104 -> 0x00038104 |
| Adjusting 00038081: 0x00000110 -> 0x00038110 |
| Adjusting 0003808a: 0x00000114 -> 0x00038114 |
| Adjusting 000380ab: 0x00000118 -> 0x00038118 |
| Adjusting 000380b2: 0x0000010c -> 0x0003810c |
| Adjusting 000380b8: 0x00000108 -> 0x00038108 |
| SMM Module: stub loaded at 00038000. Will call 7ffadee7(7ffd37e0) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 8001157a. filesize: 0x3658 memsize: 0x7678 |
| Processing 211 relocs. Offset value of 0x80010000 |
| Adjusting 80010592: 0x00002c24 -> 0x80012c24 |
| Adjusting 800105b1: 0x00002c24 -> 0x80012c24 |
| Adjusting 8001066e: 0x00002e6e -> 0x80012e6e |
| Adjusting 80010685: 0x00002c24 -> 0x80012c24 |
| Adjusting 800106fb: 0x00002c34 -> 0x80012c34 |
| Adjusting 8001072e: 0x00002c4f -> 0x80012c4f |
| Adjusting 80010763: 0x00002c58 -> 0x80012c58 |
| Adjusting 800107ba: 0x00002c79 -> 0x80012c79 |
| Adjusting 80010831: 0x00002c8e -> 0x80012c8e |
| Adjusting 80010868: 0x00002cac -> 0x80012cac |
| Adjusting 8001088c: 0x00002ccd -> 0x80012ccd |
| Adjusting 800108a5: 0x00002cf0 -> 0x80012cf0 |
| Adjusting 80010a8c: 0x00003640 -> 0x80013640 |
| Adjusting 80010aa3: 0x00002d1c -> 0x80012d1c |
| Adjusting 80010ab6: 0x00003640 -> 0x80013640 |
| Adjusting 80010ac2: 0x00002eac -> 0x80012eac |
| Adjusting 80010ac7: 0x00002ec9 -> 0x80012ec9 |
| Adjusting 80010acc: 0x00002ecc -> 0x80012ecc |
| Adjusting 80010ad1: 0x00002d28 -> 0x80012d28 |
| Adjusting 80010b04: 0x00003644 -> 0x80013644 |
| Adjusting 80010b1a: 0x00000ae0 -> 0x80010ae0 |
| Adjusting 80010b2e: 0x00003644 -> 0x80013644 |
| Adjusting 80010b40: 0x00003644 -> 0x80013644 |
| Adjusting 80010b53: 0x00002d71 -> 0x80012d71 |
| Adjusting 80010b5c: 0x00002d4c -> 0x80012d4c |
| Adjusting 80011088: 0x00002d96 -> 0x80012d96 |
| Adjusting 800112e2: 0x00003658 -> 0x80013658 |
| Adjusting 80011304: 0x00002d9d -> 0x80012d9d |
| Adjusting 80011331: 0x00002db6 -> 0x80012db6 |
| Adjusting 8001135a: 0x00003650 -> 0x80013650 |
| Adjusting 80011374: 0x000035a0 -> 0x800135a0 |
| Adjusting 80011388: 0x000034b5 -> 0x800134b5 |
| Adjusting 800113a7: 0x000034e6 -> 0x800134e6 |
| Adjusting 800113be: 0x000034f0 -> 0x800134f0 |
| Adjusting 800113d5: 0x000034f5 -> 0x800134f5 |
| Adjusting 800113ec: 0x000034fe -> 0x800134fe |
| Adjusting 80011403: 0x0000350b -> 0x8001350b |
| Adjusting 8001141a: 0x00003517 -> 0x80013517 |
| Adjusting 80011431: 0x00003524 -> 0x80013524 |
| Adjusting 80011448: 0x0000352f -> 0x8001352f |
| Adjusting 8001145f: 0x0000353b -> 0x8001353b |
| Adjusting 80011476: 0x00003545 -> 0x80013545 |
| Adjusting 8001148d: 0x0000354a -> 0x8001354a |
| Adjusting 800114a4: 0x00003552 -> 0x80013552 |
| Adjusting 800114bb: 0x00003559 -> 0x80013559 |
| Adjusting 800114d2: 0x0000355e -> 0x8001355e |
| Adjusting 800114e9: 0x00003564 -> 0x80013564 |
| Adjusting 800114ff: 0x00003569 -> 0x80013569 |
| Adjusting 80011515: 0x00003574 -> 0x80013574 |
| Adjusting 8001152b: 0x00003579 -> 0x80013579 |
| Adjusting 80011541: 0x00003582 -> 0x80013582 |
| Adjusting 80011557: 0x0000358e -> 0x8001358e |
| Adjusting 80011568: 0x000032dc -> 0x800132dc |
| Adjusting 80011584: 0x00003658 -> 0x80013658 |
| Adjusting 80011592: 0x00003658 -> 0x80013658 |
| Adjusting 800115a3: 0x00002dc8 -> 0x80012dc8 |
| Adjusting 800115b7: 0x00003648 -> 0x80013648 |
| Adjusting 800115c2: 0x00003648 -> 0x80013648 |
| Adjusting 800115d5: 0x0000365c -> 0x8001365c |
| Adjusting 800115e1: 0x00002df5 -> 0x80012df5 |
| Adjusting 800115f1: 0x0000364c -> 0x8001364c |
| Adjusting 800115fa: 0x0000364c -> 0x8001364c |
| Adjusting 80011617: 0x0000365c -> 0x8001365c |
| Adjusting 80011620: 0x00003648 -> 0x80013648 |
| Adjusting 80011639: 0x00003660 -> 0x80013660 |
| Adjusting 80011649: 0x00003660 -> 0x80013660 |
| Adjusting 8001166f: 0x00003660 -> 0x80013660 |
| Adjusting 800116d7: 0x00002e00 -> 0x80012e00 |
| Adjusting 800116ea: 0x00002e10 -> 0x80012e10 |
| Adjusting 800117ca: 0x00002e4f -> 0x80012e4f |
| Adjusting 800117f3: 0x00002c10 -> 0x80012c10 |
| Adjusting 8001181d: 0x00002c08 -> 0x80012c08 |
| Adjusting 80011822: 0x00002e83 -> 0x80012e83 |
| Adjusting 80011b17: 0x00003664 -> 0x80013664 |
| Adjusting 80011b46: 0x00003668 -> 0x80013668 |
| Adjusting 80011b59: 0x00003664 -> 0x80013664 |
| Adjusting 80011b7c: 0x00003668 -> 0x80013668 |
| Adjusting 80011bca: 0x00002ee7 -> 0x80012ee7 |
| Adjusting 80011c17: 0x00002ee7 -> 0x80012ee7 |
| Adjusting 80011c61: 0x00003664 -> 0x80013664 |
| Adjusting 80011cf7: 0x00002f03 -> 0x80012f03 |
| Adjusting 80011d85: 0x00002f2b -> 0x80012f2b |
| Adjusting 80011e1a: 0x00003041 -> 0x80013041 |
| Adjusting 80011e5f: 0x00002f93 -> 0x80012f93 |
| Adjusting 80011e70: 0x00002fdb -> 0x80012fdb |
| Adjusting 80011ebc: 0x00002ffb -> 0x80012ffb |
| Adjusting 80011eec: 0x0000301f -> 0x8001301f |
| Adjusting 80011f14: 0x00002f57 -> 0x80012f57 |
| Adjusting 80011f49: 0x00002f75 -> 0x80012f75 |
| Adjusting 80011f5f: 0x00003668 -> 0x80013668 |
| Adjusting 80011fda: 0x0000313c -> 0x8001313c |
| Adjusting 80011fdf: 0x0000307a -> 0x8001307a |
| Adjusting 8001200c: 0x00003082 -> 0x80013082 |
| Adjusting 8001203b: 0x00002f03 -> 0x80012f03 |
| Adjusting 800120ca: 0x00002f2b -> 0x80012f2b |
| Adjusting 800120ec: 0x00003668 -> 0x80013668 |
| Adjusting 80012178: 0x00003041 -> 0x80013041 |
| Adjusting 800121bd: 0x000030cc -> 0x800130cc |
| Adjusting 800121ce: 0x00002fdb -> 0x80012fdb |
| Adjusting 800121ee: 0x00003668 -> 0x80013668 |
| Adjusting 80012222: 0x00003113 -> 0x80013113 |
| Adjusting 80012267: 0x00002f57 -> 0x80012f57 |
| Adjusting 80012292: 0x000030a5 -> 0x800130a5 |
| Adjusting 8001235b: 0x00003650 -> 0x80013650 |
| Adjusting 8001236a: 0x0000314d -> 0x8001314d |
| Adjusting 80012388: 0x00003158 -> 0x80013158 |
| Adjusting 800123a5: 0x00003160 -> 0x80013160 |
| Adjusting 800123bc: 0x00003166 -> 0x80013166 |
| Adjusting 800123d3: 0x0000316e -> 0x8001316e |
| Adjusting 800123ea: 0x00003174 -> 0x80013174 |
| Adjusting 80012401: 0x00003179 -> 0x80013179 |
| Adjusting 80012418: 0x00003181 -> 0x80013181 |
| Adjusting 8001242f: 0x0000318a -> 0x8001318a |
| Adjusting 80012445: 0x0000318e -> 0x8001318e |
| Adjusting 8001245b: 0x00003197 -> 0x80013197 |
| Adjusting 80012471: 0x000031a0 -> 0x800131a0 |
| Adjusting 80012487: 0x00003511 -> 0x80013511 |
| Adjusting 8001249d: 0x000031a6 -> 0x800131a6 |
| Adjusting 800124b3: 0x000031ac -> 0x800131ac |
| Adjusting 800124c9: 0x000031b3 -> 0x800131b3 |
| Adjusting 800124df: 0x000031bc -> 0x800131bc |
| Adjusting 800124f0: 0x000032dc -> 0x800132dc |
| Adjusting 80012561: 0x00003670 -> 0x80013670 |
| Adjusting 80012598: 0x000031cd -> 0x800131cd |
| Adjusting 800125b7: 0x000031db -> 0x800131db |
| Adjusting 800125cd: 0x000031f8 -> 0x800131f8 |
| Adjusting 800125ec: 0x00003205 -> 0x80013205 |
| Adjusting 800125fc: 0x00003212 -> 0x80013212 |
| Adjusting 8001260b: 0x000031c7 -> 0x800131c7 |
| Adjusting 80012616: 0x000031c2 -> 0x800131c2 |
| Adjusting 8001261f: 0x00003223 -> 0x80013223 |
| Adjusting 80012639: 0x00003235 -> 0x80013235 |
| Adjusting 80012656: 0x00003650 -> 0x80013650 |
| Adjusting 8001267e: 0x00003255 -> 0x80013255 |
| Adjusting 8001268f: 0x00003650 -> 0x80013650 |
| Adjusting 800126bc: 0x00003277 -> 0x80013277 |
| Adjusting 800126da: 0x00003266 -> 0x80013266 |
| Adjusting 800126e3: 0x00003650 -> 0x80013650 |
| Adjusting 800126f5: 0x00003288 -> 0x80013288 |
| Adjusting 8001270b: 0x00003650 -> 0x80013650 |
| Adjusting 8001271d: 0x0000329e -> 0x8001329e |
| Adjusting 80012727: 0x00003674 -> 0x80013674 |
| Adjusting 80012731: 0x000032b3 -> 0x800132b3 |
| Adjusting 8001277d: 0x00003674 -> 0x80013674 |
| Adjusting 80012784: 0x000032de -> 0x800132de |
| Adjusting 80012789: 0x00003670 -> 0x80013670 |
| Adjusting 80012794: 0x0000366c -> 0x8001366c |
| Adjusting 8001279e: 0x000032f8 -> 0x800132f8 |
| Adjusting 800127c1: 0x0000366c -> 0x8001366c |
| Adjusting 800127db: 0x00003650 -> 0x80013650 |
| Adjusting 800127ed: 0x00003311 -> 0x80013311 |
| Adjusting 800127ff: 0x00003650 -> 0x80013650 |
| Adjusting 8001283f: 0x00003320 -> 0x80013320 |
| Adjusting 8001285a: 0x00003336 -> 0x80013336 |
| Adjusting 8001286f: 0x00003650 -> 0x80013650 |
| Adjusting 80012881: 0x00003344 -> 0x80013344 |
| Adjusting 80012898: 0x00003650 -> 0x80013650 |
| Adjusting 800128a6: 0x0000335a -> 0x8001335a |
| Adjusting 800128be: 0x0000336a -> 0x8001336a |
| Adjusting 800128d5: 0x00003364 -> 0x80013364 |
| Adjusting 800128ec: 0x0000336f -> 0x8001336f |
| Adjusting 80012903: 0x00003378 -> 0x80013378 |
| Adjusting 8001291e: 0x0000337d -> 0x8001337d |
| Adjusting 80012934: 0x00003385 -> 0x80013385 |
| Adjusting 8001294a: 0x0000338a -> 0x8001338a |
| Adjusting 80012960: 0x0000338e -> 0x8001338e |
| Adjusting 80012971: 0x000032dc -> 0x800132dc |
| Adjusting 8001297e: 0x00003650 -> 0x80013650 |
| Adjusting 8001298f: 0x00003395 -> 0x80013395 |
| Adjusting 800129a4: 0x00003650 -> 0x80013650 |
| Adjusting 800129ce: 0x000033a1 -> 0x800133a1 |
| Adjusting 800129eb: 0x00003650 -> 0x80013650 |
| Adjusting 80012a04: 0x000033b5 -> 0x800133b5 |
| Adjusting 80012a1c: 0x00003594 -> 0x80013594 |
| Adjusting 80012a21: 0x00003670 -> 0x80013670 |
| Adjusting 80012aa5: 0x00003494 -> 0x80013494 |
| Adjusting 80012aac: 0x000033c9 -> 0x800133c9 |
| Adjusting 80012ab8: 0x000033e1 -> 0x800133e1 |
| Adjusting 80012ac4: 0x00003405 -> 0x80013405 |
| Adjusting 80012b1f: 0x00003429 -> 0x80013429 |
| Adjusting 80012b28: 0x0000344e -> 0x8001344e |
| Adjusting 80012b36: 0x00003650 -> 0x80013650 |
| Adjusting 80012b69: 0x00003472 -> 0x80013472 |
| Adjusting 80012b7a: 0x00003650 -> 0x80013650 |
| Adjusting 80012ba7: 0x00003650 -> 0x80013650 |
| Adjusting 80012bbb: 0x000034ac -> 0x800134ac |
| Adjusting 80012bc7: 0x00003670 -> 0x80013670 |
| Adjusting 80012bde: 0x00003650 -> 0x80013650 |
| Adjusting 80012c08: 0x00002bf0 -> 0x80012bf0 |
| Adjusting 80012c10: 0x0000057d -> 0x8001057d |
| Adjusting 80012c14: 0x00002bf0 -> 0x80012bf0 |
| Adjusting 80012c1c: 0x000005ee -> 0x800105ee |
| Adjusting 80012c28: 0x00002d08 -> 0x80012d08 |
| Adjusting 80012d08: 0x000008bd -> 0x800108bd |
| Adjusting 80012d0c: 0x000008c9 -> 0x800108c9 |
| Adjusting 80012d10: 0x000008cc -> 0x800108cc |
| Adjusting 80013494: 0x00002aa9 -> 0x80012aa9 |
| Adjusting 80013498: 0x00002ab5 -> 0x80012ab5 |
| Adjusting 8001349c: 0x00002b66 -> 0x80012b66 |
| Adjusting 800134a0: 0x00002ac1 -> 0x80012ac1 |
| Adjusting 800134a4: 0x00002b1c -> 0x80012b1c |
| Adjusting 800134a8: 0x00002b25 -> 0x80012b25 |
| Adjusting 800135b0: 0x000029b5 -> 0x800129b5 |
| Adjusting 800135b4: 0x0000269f -> 0x8001269f |
| Adjusting 800135c0: 0x00002890 -> 0x80012890 |
| Adjusting 800135c4: 0x00002353 -> 0x80012353 |
| Adjusting 800135c8: 0x0000264f -> 0x8001264f |
| Adjusting 800135cc: 0x0000286d -> 0x8001286d |
| Adjusting 800135d4: 0x000027fc -> 0x800127fc |
| Adjusting 800135d8: 0x000027d9 -> 0x800127d9 |
| Adjusting 800135f4: 0x00002501 -> 0x80012501 |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 12 relocs. Offset value of 0x80008000 |
| Adjusting 80008002: 0x00000024 -> 0x80008024 |
| Adjusting 8000801d: 0x0000003c -> 0x8000803c |
| Adjusting 80008026: 0x00000024 -> 0x80008024 |
| Adjusting 80008054: 0x00000120 -> 0x80008120 |
| Adjusting 80008066: 0x000001a8 -> 0x800081a8 |
| Adjusting 8000806f: 0x00000100 -> 0x80008100 |
| Adjusting 80008077: 0x00000104 -> 0x80008104 |
| Adjusting 80008081: 0x00000110 -> 0x80008110 |
| Adjusting 8000808a: 0x00000114 -> 0x80008114 |
| Adjusting 800080ab: 0x00000118 -> 0x80008118 |
| Adjusting 800080b2: 0x0000010c -> 0x8000810c |
| Adjusting 800080b8: 0x00000108 -> 0x80008108 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: stub loaded at 80008000. Will call 8001157a(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: MCSMI PM1 |
| PM1_STS: WAK PWRBTN |
| GPE0_STS: GPIO15 GPIO13 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 |
| ALT_GP_SMI_STS: GPI15 GPI13 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Found @ offset 14f00 size 5800 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1b |
| CPU: Intel(R) Core(TM) i5-3437U CPU @ 1.90GHz. |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4710 |
| memalign 7ffd4710 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4728 |
| memalign 7ffd4728 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4740 |
| memalign 7ffd4740 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4758 |
| memalign 7ffd4758 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4770 |
| memalign 7ffd4770 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4788 |
| memalign 7ffd4788 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd47a0 |
| memalign 7ffd47a0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd47b8 |
| memalign 7ffd47b8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd47d0 |
| memalign 7ffd47d0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd47e8 |
| memalign 7ffd47e8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4800 |
| memalign 7ffd4800 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4818 |
| memalign 7ffd4818 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4830 |
| memalign 7ffd4830 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4848 |
| memalign 7ffd4848 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4860 |
| memalign 7ffd4860 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4878 |
| memalign 7ffd4878 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4890 |
| memalign 7ffd4890 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd48a8 |
| memalign 7ffd48a8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd48c0 |
| memalign 7ffd48c0 |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000e0000000 size 0x60000000 type 0 |
| 0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1 |
| 0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0 |
| 0x0000000100000000 - 0x0000000371600000 size 0x271600000 type 6 |
| MTRR addr 0x0-0x10 set to 6 type @ 0 |
| MTRR addr 0x10-0x20 set to 6 type @ 1 |
| MTRR addr 0x20-0x30 set to 6 type @ 2 |
| MTRR addr 0x30-0x40 set to 6 type @ 3 |
| MTRR addr 0x40-0x50 set to 6 type @ 4 |
| MTRR addr 0x50-0x60 set to 6 type @ 5 |
| MTRR addr 0x60-0x70 set to 6 type @ 6 |
| MTRR addr 0x70-0x80 set to 6 type @ 7 |
| MTRR addr 0x80-0x84 set to 6 type @ 8 |
| MTRR addr 0x84-0x88 set to 6 type @ 9 |
| MTRR addr 0x88-0x8c set to 6 type @ 10 |
| MTRR addr 0x8c-0x90 set to 6 type @ 11 |
| MTRR addr 0x90-0x94 set to 6 type @ 12 |
| MTRR addr 0x94-0x98 set to 6 type @ 13 |
| MTRR addr 0x98-0x9c set to 6 type @ 14 |
| MTRR addr 0x9c-0xa0 set to 6 type @ 15 |
| MTRR addr 0xa0-0xa4 set to 0 type @ 16 |
| MTRR addr 0xa4-0xa8 set to 0 type @ 17 |
| MTRR addr 0xa8-0xac set to 0 type @ 18 |
| MTRR addr 0xac-0xb0 set to 0 type @ 19 |
| MTRR addr 0xb0-0xb4 set to 0 type @ 20 |
| MTRR addr 0xb4-0xb8 set to 0 type @ 21 |
| MTRR addr 0xb8-0xbc set to 0 type @ 22 |
| MTRR addr 0xbc-0xc0 set to 0 type @ 23 |
| MTRR addr 0xc0-0xc1 set to 6 type @ 24 |
| MTRR addr 0xc1-0xc2 set to 6 type @ 25 |
| MTRR addr 0xc2-0xc3 set to 6 type @ 26 |
| MTRR addr 0xc3-0xc4 set to 6 type @ 27 |
| MTRR addr 0xc4-0xc5 set to 6 type @ 28 |
| MTRR addr 0xc5-0xc6 set to 6 type @ 29 |
| MTRR addr 0xc6-0xc7 set to 6 type @ 30 |
| MTRR addr 0xc7-0xc8 set to 6 type @ 31 |
| MTRR addr 0xc8-0xc9 set to 6 type @ 32 |
| MTRR addr 0xc9-0xca set to 6 type @ 33 |
| MTRR addr 0xca-0xcb set to 6 type @ 34 |
| MTRR addr 0xcb-0xcc set to 6 type @ 35 |
| MTRR addr 0xcc-0xcd set to 6 type @ 36 |
| MTRR addr 0xcd-0xce set to 6 type @ 37 |
| MTRR addr 0xce-0xcf set to 6 type @ 38 |
| MTRR addr 0xcf-0xd0 set to 6 type @ 39 |
| MTRR addr 0xd0-0xd1 set to 6 type @ 40 |
| MTRR addr 0xd1-0xd2 set to 6 type @ 41 |
| MTRR addr 0xd2-0xd3 set to 6 type @ 42 |
| MTRR addr 0xd3-0xd4 set to 6 type @ 43 |
| MTRR addr 0xd4-0xd5 set to 6 type @ 44 |
| MTRR addr 0xd5-0xd6 set to 6 type @ 45 |
| MTRR addr 0xd6-0xd7 set to 6 type @ 46 |
| MTRR addr 0xd7-0xd8 set to 6 type @ 47 |
| MTRR addr 0xd8-0xd9 set to 6 type @ 48 |
| MTRR addr 0xd9-0xda set to 6 type @ 49 |
| MTRR addr 0xda-0xdb set to 6 type @ 50 |
| MTRR addr 0xdb-0xdc set to 6 type @ 51 |
| MTRR addr 0xdc-0xdd set to 6 type @ 52 |
| MTRR addr 0xdd-0xde set to 6 type @ 53 |
| MTRR addr 0xde-0xdf set to 6 type @ 54 |
| MTRR addr 0xdf-0xe0 set to 6 type @ 55 |
| MTRR addr 0xe0-0xe1 set to 6 type @ 56 |
| MTRR addr 0xe1-0xe2 set to 6 type @ 57 |
| MTRR addr 0xe2-0xe3 set to 6 type @ 58 |
| MTRR addr 0xe3-0xe4 set to 6 type @ 59 |
| MTRR addr 0xe4-0xe5 set to 6 type @ 60 |
| MTRR addr 0xe5-0xe6 set to 6 type @ 61 |
| MTRR addr 0xe6-0xe7 set to 6 type @ 62 |
| MTRR addr 0xe7-0xe8 set to 6 type @ 63 |
| MTRR addr 0xe8-0xe9 set to 6 type @ 64 |
| MTRR addr 0xe9-0xea set to 6 type @ 65 |
| MTRR addr 0xea-0xeb set to 6 type @ 66 |
| MTRR addr 0xeb-0xec set to 6 type @ 67 |
| MTRR addr 0xec-0xed set to 6 type @ 68 |
| MTRR addr 0xed-0xee set to 6 type @ 69 |
| MTRR addr 0xee-0xef set to 6 type @ 70 |
| MTRR addr 0xef-0xf0 set to 6 type @ 71 |
| MTRR addr 0xf0-0xf1 set to 6 type @ 72 |
| MTRR addr 0xf1-0xf2 set to 6 type @ 73 |
| MTRR addr 0xf2-0xf3 set to 6 type @ 74 |
| MTRR addr 0xf3-0xf4 set to 6 type @ 75 |
| MTRR addr 0xf4-0xf5 set to 6 type @ 76 |
| MTRR addr 0xf5-0xf6 set to 6 type @ 77 |
| MTRR addr 0xf6-0xf7 set to 6 type @ 78 |
| MTRR addr 0xf7-0xf8 set to 6 type @ 79 |
| MTRR addr 0xf8-0xf9 set to 6 type @ 80 |
| MTRR addr 0xf9-0xfa set to 6 type @ 81 |
| MTRR addr 0xfa-0xfb set to 6 type @ 82 |
| MTRR addr 0xfb-0xfc set to 6 type @ 83 |
| MTRR addr 0xfc-0xfd set to 6 type @ 84 |
| MTRR addr 0xfd-0xfe set to 6 type @ 85 |
| MTRR addr 0xfe-0xff set to 6 type @ 86 |
| MTRR addr 0xff-0x100 set to 6 type @ 87 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/10. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0 |
| MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0 |
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x00 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1900 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 2 cores, 2 threads per core |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd48d8 |
| memalign 7ffd48d8 |
| CPU: 0 has core 1 |
| CPU1: stack_base 7ffcc000, stack_end 7ffccff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4970 |
| CPU: vendor Intel device 306a9 |
| memalign 7ffd4970 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: 0 has core 2 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Found @ offset 14f00 size 5800 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1b |
| CPU: Intel(R) Core(TM) i5-3437U CPU @ 1.90GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x01 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1900 |
| CPU #1 initialized |
| CPU2: stack_base 7ffcb000, stack_end 7ffcbff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4a08 |
| memalign 7ffd4a08 |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Found @ offset 14f00 size 5800 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i5-3437U CPU @ 1.90GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x02 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1900 |
| CPU #2 initialized |
| CPU3: stack_base 7ffca000, stack_end 7ffcaff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Found @ offset 14f00 size 5800 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1b |
| CPU: Intel(R) Core(TM) i5-3437U CPU @ 1.90GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x03 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1900 |
| CPU #3 initialized |
| All AP CPUs stopped (598 loops) |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcda40, stack used: 1472 bytes |
| CPU1: stack: 7ffcc000 - 7ffcd000, lowest used address 7ffccc40, stack used: 960 bytes |
| CPU2: stack: 7ffcb000 - 7ffcc000, lowest used address 7ffcbc40, stack used: 960 bytes |
| CPU3: stack: 7ffca000 - 7ffcb000, lowest used address 7ffcac40, stack used: 960 bytes |
| CPU_CLUSTER: 0 init finished in 105331 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG10. |
| Disabling PEG60. |
| Disabling Device 7. |
| Disabling PEG IO clock. |
| Set BIOS_RESET_CPL |
| CPU TDP: 17 Watts |
| PCI: 00:00.0 init finished in 1020 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 17W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| EDID: |
| 00 ff ff ff ff ff ff 00 30 e4 cf 03 00 00 00 00 |
| 00 16 01 04 90 1a 0e 78 0a 4f 75 98 5b 55 90 27 |
| 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 |
| 01 01 01 01 01 01 3e 1c 56 a0 50 00 16 30 24 28 |
| 35 00 00 90 10 00 00 19 d4 12 56 a0 50 00 16 30 |
| 24 28 35 00 00 90 10 00 00 19 00 00 00 00 00 00 |
| 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 |
| 00 0c 26 ff 0a 3c c8 12 09 1f c8 00 00 00 00 27 |
| Extracted contents: |
| header: 00 ff ff ff ff ff ff 00 |
| serial number: 30 e4 cf 03 00 00 00 00 00 16 |
| version: 01 04 |
| basic params: 90 1a 0e 78 0a |
| chroma info: 4f 75 98 5b 55 90 27 1e 50 54 |
| established: 00 00 00 |
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 |
| descriptor 1: 3e 1c 56 a0 50 00 16 30 24 28 35 00 00 90 10 00 00 19 |
| descriptor 2: d4 12 56 a0 50 00 16 30 24 28 35 00 00 90 10 00 00 19 |
| descriptor 3: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| descriptor 4: 00 00 00 02 00 0c 26 ff 0a 3c c8 12 09 1f c8 00 00 00 |
| extensions: 00 |
| checksum: 27 |
| |
| Manufacturer: LGD Model 3cf Serial Number 0 |
| Made week 0 of 2012 |
| EDID version: 1.4 |
| Digital display |
| 6 bits per primary color channel |
| Digital interface is not defined |
| Maximum image size: 26 cm x 14 cm |
| Gamma: 220% |
| Check DPMS levels |
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2 |
| First detailed timing is preferred timing |
| Established timings supported: |
| Standard timings supported: |
| Detailed timings |
| Hex of detail: 3e1c56a05000163024283500009010000019 |
| Detailed mode (IN HEX): Clock 72300 KHz, 100 mm x 90 mm |
| 0556 057a 05a2 05f6 hborder 0 |
| 0300 0303 0308 0316 vborder 0 |
| -hsync -vsync |
| Did detailed timing |
| Hex of detail: d41256a05000163024283500009010000019 |
| Detailed mode (IN HEX): Clock 48200 KHz, 100 mm x 90 mm |
| 0556 057a 05a2 05f6 hborder 0 |
| 0300 0303 0308 0316 vborder 0 |
| -hsync -vsync |
| Hex of detail: 000000000000000000000000000000000000 |
| Manufacturer-specified data, tag 0 |
| Hex of detail: 00000002000c26ff0a3cc812091fc8000000 |
| Manufacturer-specified data, tag 2 |
| Checksum |
| Checksum: 0x27 (valid) |
| bringing up panel at resolution 1376 x 768 |
| Borders 0 x 0 |
| Blank 160 x 22 |
| Sync 40 x 5 |
| Front porch 36 x 3 |
| Spread spectrum clock |
| Single channel |
| Polarities 1, 1 |
| Data M1=5054136, N1=8388608 |
| Link frequency 270000 kHz |
| Link M1=140392, N1=524288 |
| Pixel N=7, M1=22, M2=8, P1=2 |
| Pixel clock 144489 kHz |
| waiting for panel powerup |
| panel powered up |
| PCI: 00:02.0 init finished in 43131 usecs |
| POST: 0x75 |
| PCI: 00:04.0 init ... |
| PCI: 00:04.0 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 00:14.0 init ... |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 7 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:19.0 init ... |
| PCI: 00:19.0 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 13 usecs |
| POST: 0x75 |
| PCI: 00:1b.0 init ... |
| Azalia: base = f1938000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: verb_size: 16 |
| Azalia: verb loaded. |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 111d76e0 |
| Azalia: verb_size: 44 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 4601 usecs |
| POST: 0x75 |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 8 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1c.1 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 10 usecs |
| POST: 0x75 |
| PCI: 00:1c.2 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.2 init finished in 8 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 13 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Found @ offset 1b080 size 4ac |
| Set power off after power failure. |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Found @ offset 1b080 size 4ac |
| NMI sources enabled. |
| PantherPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 1368 usecs |
| POST: 0x75 |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Found @ offset 1b080 size 4ac |
| SATA: Controller in AHCI mode. |
| ABAR: f193d000 |
| PCI: 00:1f.2 init finished in 409 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 02:00.2 init ... |
| PCI: 02:00.2 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 02:00.3 init ... |
| PCI: 02:00.3 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 02:00.4 init ... |
| PCI: 02:00.4 init finished in 0 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 0 usecs |
| POST: 0x75 |
| POST: 0x75 |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 00ff.1: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:04.0: enabled 1 |
| PCI: 02:00.0: enabled 1 |
| PCI: 02:00.2: enabled 1 |
| PCI: 02:00.3: enabled 1 |
| PCI: 02:00.4: enabled 1 |
| NONE: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| Updating MRC cache data. |
| No MRC cache in cbmem. Can't update flash. |
| BS: BS_DEV_INIT times (us): entry 14 run 156075 exit 1 |
| POST: 0x76 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 371 exit 0 |
| POST: 0x77 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 |
| POST: 0x79 |
| POST: 0x9c |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Found @ offset 1b580 size 334d |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1b580 |
| CBFS: Checking offset 1e940 |
| CBFS: File @ offset 1e940 size 6a4 |
| CBFS: Unmatched 'payload_config' at 1e940 |
| CBFS: Checking offset 1f040 |
| CBFS: File @ offset 1f040 size ea |
| CBFS: Unmatched 'payload_revision' at 1f040 |
| CBFS: Checking offset 1f180 |
| CBFS: File @ offset 1f180 size d18 |
| CBFS: Unmatched '' at 1f180 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 16ad1 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 46a40 |
| CBFS: File @ offset 46a40 size 6c00 |
| CBFS: Unmatched 'vgaroms/seavgabios.bin' at 46a40 |
| CBFS: Checking offset 4d6c0 |
| CBFS: File @ offset 4d6c0 size 228dc |
| CBFS: Unmatched 'img/nvramcui' at 4d6c0 |
| CBFS: Checking offset 70000 |
| CBFS: File @ offset 70000 size 10726 |
| CBFS: Unmatched 'fallback/payload' at 70000 |
| CBFS: Checking offset 80780 |
| CBFS: File @ offset 80780 size 2c02c |
| CBFS: Unmatched 'img/memtest' at 80780 |
| CBFS: Checking offset ac800 |
| CBFS: File @ offset ac800 size f13698 |
| CBFS: Unmatched '' at ac800 |
| CBFS: Checking offset fbfec0 |
| CBFS: File @ offset fbfec0 size fac0 |
| CBFS: Unmatched 'ecfw2.bin' at fbfec0 |
| CBFS: Checking offset fcf9c0 |
| CBFS: File @ offset fcf9c0 size 84d8 |
| CBFS: Unmatched '' at fcf9c0 |
| CBFS: Checking offset fd7ec0 |
| CBFS: File @ offset fd7ec0 size 800 |
| CBFS: Unmatched 'ecfw1.bin' at fd7ec0 |
| CBFS: Checking offset fd8700 |
| CBFS: File @ offset fd8700 size 6bd8 |
| CBFS: Unmatched '' at fd8700 |
| CBFS: Checking offset fdf300 |
| CBFS: File @ offset fdf300 size bb8 |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff13000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| ACPI_PIRQ_GEN: PCI: 00:14.0: pin=1 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=1 pirq=6 |
| ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=1 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=1 pirq=2 |
| ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=3 pirq=4 |
| ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=1 pirq=4 |
| ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=2 |
| ACPI_PIRQ_GEN: PCI: 00:02.0: pin=1 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:04.0: pin=1 pirq=1 |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| Found 1 CPU(s) with 4 core(s) each. |
| PSS: 1901MHz power 17000 control 0x1d00 status 0x1d00 |
| PSS: 1900MHz power 17000 control 0x1300 status 0x1300 |
| PSS: 1600MHz power 13827 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 11798 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 9879 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 8047 control 0xa00 status 0xa00 |
| PSS: 800MHz power 6283 control 0x800 status 0x800 |
| PSS: 1901MHz power 17000 control 0x1d00 status 0x1d00 |
| PSS: 1900MHz power 17000 control 0x1300 status 0x1300 |
| PSS: 1600MHz power 13827 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 11798 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 9879 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 8047 control 0xa00 status 0xa00 |
| PSS: 800MHz power 6283 control 0x800 status 0x800 |
| PSS: 1901MHz power 17000 control 0x1d00 status 0x1d00 |
| PSS: 1900MHz power 17000 control 0x1300 status 0x1300 |
| PSS: 1600MHz power 13827 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 11798 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 9879 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 8047 control 0xa00 status 0xa00 |
| PSS: 800MHz power 6283 control 0x800 status 0x800 |
| PSS: 1901MHz power 17000 control 0x1d00 status 0x1d00 |
| PSS: 1900MHz power 17000 control 0x1300 status 0x1300 |
| PSS: 1600MHz power 13827 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 11798 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 9879 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 8047 control 0xa00 status 0xa00 |
| PSS: 800MHz power 6283 control 0x800 status 0x800 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 7ff02000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff18170 |
| ACPI: * DMAR |
| ACPI: added table 6/32, length now 60 |
| current = 7ff18220 |
| ACPI: * HPET |
| ACPI: added table 7/32, length now 64 |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1b580 |
| CBFS: Checking offset 1e940 |
| CBFS: File @ offset 1e940 size 6a4 |
| CBFS: Unmatched 'payload_config' at 1e940 |
| CBFS: Checking offset 1f040 |
| CBFS: File @ offset 1f040 size ea |
| CBFS: Unmatched 'payload_revision' at 1f040 |
| CBFS: Checking offset 1f180 |
| CBFS: File @ offset 1f180 size d18 |
| CBFS: Unmatched '' at 1f180 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 16ad1 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 46a40 |
| CBFS: File @ offset 46a40 size 6c00 |
| CBFS: Unmatched 'vgaroms/seavgabios.bin' at 46a40 |
| CBFS: Checking offset 4d6c0 |
| CBFS: File @ offset 4d6c0 size 228dc |
| CBFS: Unmatched 'img/nvramcui' at 4d6c0 |
| CBFS: Checking offset 70000 |
| CBFS: File @ offset 70000 size 10726 |
| CBFS: Unmatched 'fallback/payload' at 70000 |
| CBFS: Checking offset 80780 |
| CBFS: File @ offset 80780 size 2c02c |
| CBFS: Unmatched 'img/memtest' at 80780 |
| CBFS: Checking offset ac800 |
| CBFS: File @ offset ac800 size f13698 |
| CBFS: Unmatched '' at ac800 |
| CBFS: Checking offset fbfec0 |
| CBFS: File @ offset fbfec0 size fac0 |
| CBFS: Unmatched 'ecfw2.bin' at fbfec0 |
| CBFS: Checking offset fcf9c0 |
| CBFS: File @ offset fcf9c0 size 84d8 |
| CBFS: Unmatched '' at fcf9c0 |
| CBFS: Checking offset fd7ec0 |
| CBFS: File @ offset fd7ec0 size 800 |
| CBFS: Unmatched 'ecfw1.bin' at fd7ec0 |
| CBFS: Checking offset fd8700 |
| CBFS: File @ offset fd8700 size 6bd8 |
| CBFS: Unmatched '' at fd8700 |
| CBFS: Checking offset fdf300 |
| CBFS: File @ offset fdf300 size bb8 |
| CBFS: 'vbt.bin' not found. |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'pci8086,0166.rom' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1b580 |
| CBFS: Checking offset 1e940 |
| CBFS: File @ offset 1e940 size 6a4 |
| CBFS: Unmatched 'payload_config' at 1e940 |
| CBFS: Checking offset 1f040 |
| CBFS: File @ offset 1f040 size ea |
| CBFS: Unmatched 'payload_revision' at 1f040 |
| CBFS: Checking offset 1f180 |
| CBFS: File @ offset 1f180 size d18 |
| CBFS: Unmatched '' at 1f180 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 16ad1 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 46a40 |
| CBFS: File @ offset 46a40 size 6c00 |
| CBFS: Unmatched 'vgaroms/seavgabios.bin' at 46a40 |
| CBFS: Checking offset 4d6c0 |
| CBFS: File @ offset 4d6c0 size 228dc |
| CBFS: Unmatched 'img/nvramcui' at 4d6c0 |
| CBFS: Checking offset 70000 |
| CBFS: File @ offset 70000 size 10726 |
| CBFS: Unmatched 'fallback/payload' at 70000 |
| CBFS: Checking offset 80780 |
| CBFS: File @ offset 80780 size 2c02c |
| CBFS: Unmatched 'img/memtest' at 80780 |
| CBFS: Checking offset ac800 |
| CBFS: File @ offset ac800 size f13698 |
| CBFS: Unmatched '' at ac800 |
| CBFS: Checking offset fbfec0 |
| CBFS: File @ offset fbfec0 size fac0 |
| CBFS: Unmatched 'ecfw2.bin' at fbfec0 |
| CBFS: Checking offset fcf9c0 |
| CBFS: File @ offset fcf9c0 size 84d8 |
| CBFS: Unmatched '' at fcf9c0 |
| CBFS: Checking offset fd7ec0 |
| CBFS: File @ offset fd7ec0 size 800 |
| CBFS: Unmatched 'ecfw1.bin' at fd7ec0 |
| CBFS: Checking offset fd8700 |
| CBFS: File @ offset fd8700 size 6bd8 |
| CBFS: Unmatched '' at fd8700 |
| CBFS: Checking offset fdf300 |
| CBFS: File @ offset fdf300 size bb8 |
| CBFS: 'pci8086,0166.rom' not found. |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'pci8086,0106.rom' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1b580 |
| CBFS: Checking offset 1e940 |
| CBFS: File @ offset 1e940 size 6a4 |
| CBFS: Unmatched 'payload_config' at 1e940 |
| CBFS: Checking offset 1f040 |
| CBFS: File @ offset 1f040 size ea |
| CBFS: Unmatched 'payload_revision' at 1f040 |
| CBFS: Checking offset 1f180 |
| CBFS: File @ offset 1f180 size d18 |
| CBFS: Unmatched '' at 1f180 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 16ad1 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 46a40 |
| CBFS: File @ offset 46a40 size 6c00 |
| CBFS: Unmatched 'vgaroms/seavgabios.bin' at 46a40 |
| CBFS: Checking offset 4d6c0 |
| CBFS: File @ offset 4d6c0 size 228dc |
| CBFS: Unmatched 'img/nvramcui' at 4d6c0 |
| CBFS: Checking offset 70000 |
| CBFS: File @ offset 70000 size 10726 |
| CBFS: Unmatched 'fallback/payload' at 70000 |
| CBFS: Checking offset 80780 |
| CBFS: File @ offset 80780 size 2c02c |
| CBFS: Unmatched 'img/memtest' at 80780 |
| CBFS: Checking offset ac800 |
| CBFS: File @ offset ac800 size f13698 |
| CBFS: Unmatched '' at ac800 |
| CBFS: Checking offset fbfec0 |
| CBFS: File @ offset fbfec0 size fac0 |
| CBFS: Unmatched 'ecfw2.bin' at fbfec0 |
| CBFS: Checking offset fcf9c0 |
| CBFS: File @ offset fcf9c0 size 84d8 |
| CBFS: Unmatched '' at fcf9c0 |
| CBFS: Checking offset fd7ec0 |
| CBFS: File @ offset fd7ec0 size 800 |
| CBFS: Unmatched 'ecfw1.bin' at fd7ec0 |
| CBFS: Checking offset fd8700 |
| CBFS: File @ offset fd8700 size 6bd8 |
| CBFS: Unmatched '' at fd8700 |
| CBFS: Checking offset fdf300 |
| CBFS: File @ offset fdf300 size bb8 |
| CBFS: 'pci8086,0106.rom' not found. |
| PCI Option ROM loading disabled for PCI: 00:02.0 |
| GMA: locate_vbt_vbios: aa55 8086 0 0 3 |
| GMA: Found valid VBT in legacy area |
| ACPI: done. |
| ACPI tables: 29280 bytes. |
| smbios_write_tables: 7ff01000 |
| Create SMBIOS type 17 |
| Root Device (HP EliteBook Revolve 810 G1) |
| CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| APIC: 00 (unknown) |
| APIC: acac (Intel SandyBridge/IvyBridge CPU) |
| DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PNP: 00ff.1 (SMSC KBC1126 for HP laptops) |
| PNP: 0c31.0 (LPC TPM) |
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:04.0 (unknown) |
| PCI: 02:00.0 (unknown) |
| PCI: 02:00.2 (unknown) |
| PCI: 02:00.3 (unknown) |
| PCI: 02:00.4 (unknown) |
| NONE (unknown) |
| PCI: 03:00.0 (unknown) |
| APIC: 01 (unknown) |
| APIC: 02 (unknown) |
| APIC: 03 (unknown) |
| SMBIOS tables: 552 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum feb |
| Writing coreboot table at 0x7ff37000 |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Found @ offset 1b080 size 4ac |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4aa0 |
| memalign 7ffd4aa0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4ab8 |
| memalign 7ffd4ab8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4ad0 |
| memalign 7ffd4ad0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4ae8 |
| memalign 7ffd4ae8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b00 |
| memalign 7ffd4b00 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b18 |
| memalign 7ffd4b18 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b30 |
| memalign 7ffd4b30 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b48 |
| memalign 7ffd4b48 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b60 |
| memalign 7ffd4b60 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b78 |
| memalign 7ffd4b78 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff00fff: RAM |
| 4. 000000007ff01000-000000007fffffff: CONFIGURATION TABLES |
| 5. 0000000080000000-000000008e9fffff: RESERVED |
| 6. 00000000f8000000-00000000fbffffff: RESERVED |
| 7. 00000000fed40000-00000000fed44fff: RESERVED |
| 8. 00000000fed90000-00000000fed91fff: RESERVED |
| 9. 0000000100000000-00000003715fffff: RAM |
| read e008 from 07e4 |
| wrote 00000004 to 0890 |
| read 03040003 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| read 0080 from 0870 |
| wrote 000c to 0870 |
| read 05030201 from 0878 |
| read 0bd89f20 from 087c |
| read b32d from 0876 |
| read 5006 from 0874 |
| wrote 00000000 to 07e8 |
| wrote 4456 to 0871 |
| read 5481 from 0870 |
| read 5484 from 0870 |
| wrote 0004 to 0870 |
| read 001840ef from 07f0 |
| read 00 from 07f4 |
| wrote 0000 to 0874 |
| SF: Got idcode: ef 40 18 00 00 |
| Manufacturer: ef |
| SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| FMAP: Found "FLASH" version 1.1 at 20000. |
| FMAP: base = ff000000 size = 1000000 #areas = 3 |
| Wrote coreboot table at: 7ff37000, 0x838 bytes, checksum ea96 |
| coreboot table: 2128 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| TIME STAMP 3. 7ffdd000 00000400 |
| ROMSTG STCK 4. 7ffd8000 00005000 |
| RAMSTAGE 5. 7ff93000 00045000 |
| 57a9e100 6. 7ff4f000 00043870 |
| SMM BACKUP 7. 7ff3f000 00010000 |
| COREBOOT 8. 7ff37000 00008000 |
| ACPI 9. 7ff13000 00024000 |
| ACPI GNVS 10. 7ff12000 00001000 |
| TCPA LOG 11. 7ff02000 00010000 |
| SMBIOS 12. 7ff01000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| CAR GLOBALS 1. 7fffeac0 00000140 |
| MEM INFO 2. 7fffe960 00000141 |
| ROMSTAGE 3. 7fffe940 00000004 |
| 57a9e000 4. 7fffe920 00000018 |
| COREBOOTFWD 5. 7fffe8e0 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 6652 exit 0 |
| POST: 0x7a |
| CBFS: 'Master Header Locator' located CBFS at [20100:ffffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14e04 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14f00 |
| CBFS: File @ offset 14f00 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14f00 |
| CBFS: Checking offset 1a780 |
| CBFS: File @ offset 1a780 size 3aa |
| CBFS: Unmatched 'config' at 1a780 |
| CBFS: Checking offset 1ab80 |
| CBFS: File @ offset 1ab80 size 246 |
| CBFS: Unmatched 'revision' at 1ab80 |
| CBFS: Checking offset 1ae00 |
| CBFS: File @ offset 1ae00 size 100 |
| CBFS: Unmatched 'spd.bin' at 1ae00 |
| CBFS: Checking offset 1af40 |
| CBFS: File @ offset 1af40 size 100 |
| CBFS: Unmatched 'cmos.default' at 1af40 |
| CBFS: Checking offset 1b080 |
| CBFS: File @ offset 1b080 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 1b080 |
| CBFS: Checking offset 1b580 |
| CBFS: File @ offset 1b580 size 334d |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1b580 |
| CBFS: Checking offset 1e940 |
| CBFS: File @ offset 1e940 size 6a4 |
| CBFS: Unmatched 'payload_config' at 1e940 |
| CBFS: Checking offset 1f040 |
| CBFS: File @ offset 1f040 size ea |
| CBFS: Unmatched 'payload_revision' at 1f040 |
| CBFS: Checking offset 1f180 |
| CBFS: File @ offset 1f180 size d18 |
| CBFS: Unmatched '' at 1f180 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 16ad1 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 46a40 |
| CBFS: File @ offset 46a40 size 6c00 |
| CBFS: Unmatched 'vgaroms/seavgabios.bin' at 46a40 |
| CBFS: Checking offset 4d6c0 |
| CBFS: File @ offset 4d6c0 size 228dc |
| CBFS: Unmatched 'img/nvramcui' at 4d6c0 |
| CBFS: Checking offset 70000 |
| CBFS: File @ offset 70000 size 10726 |
| CBFS: Found @ offset 70000 size 10726 |
| Loading segment from ROM address 0xff090138 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4b90 |
| memalign 7ffd4b90 |
| New segment dstaddr 0xe0b00 memsize 0x1f500 srcaddr 0xff090170 filesize 0x106ee |
| Loading segment from ROM address 0xff090154 |
| Entry Point 0x000fec22 |
| Payload being loaded at below 1MiB without region being marked as RAM usable. |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4bac |
| memalign 7ffd4bb0 |
| Loading Segment: addr: 0x00000000000e0b00 memsz: 0x000000000001f500 filesz: 0x00000000000106ee |
| lb: [0x000000007ff94000, 0x000000007ffd7870) |
| Post relocation: addr: 0x00000000000e0b00 memsz: 0x000000000001f500 filesz: 0x00000000000106ee |
| using LZMA |
| [ 0x000e0b00, 00100000, 0x00100000) <- ff090170 |
| dest 000e0b00, end 00100000, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 37751 exit 0 |
| POST: 0x7b |
| PCH watchdog disabled |
| Jumping to boot code at 000fec22(7ff37000) |
| POST: 0xf8 |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcd880, stack used: 1920 bytes |
| SeaBIOS (version rel-1.11.0-0-g63451fc) |
| BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU Binutils) 2.28 |
| Found coreboot cbmem console @ 7ffde000 |
| Found mainboard HP EliteBook Revolve 810 G1 |
| Relocating init from 0x000e2140 to 0x7feb4320 (size 52288) |
| Found CBFS header at 0xff020138 |
| multiboot: eax=7ffc4c20, ebx=7ffc4bd4 |
| Found 18 PCI devices (max PCI bus is 03) |
| Copying SMBIOS entry point from 0x7ff01000 to 0x000f66e0 |
| Copying ACPI RSDP from 0x7ff13000 to 0x000f66b0 |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.11.0-0-g63451fc) |
| XHCI init on dev 00:14.0: regs @ 0xf1920000, 8 ports, 32 slots, 32 byte contexts |
| XHCI protocol USB 2.00, 4 ports (offset 1), def 3001 |
| XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 |
| XHCI extcap 0xc1 @ 0xf1928040 |
| XHCI extcap 0xc0 @ 0xf1928070 |
| XHCI extcap 0x1 @ 0xf1928330 |
| EHCI init on dev 00:1a.0 (regs=0xf193e020) |
| EHCI init on dev 00:1d.0 (regs=0xf193f020) |
| AHCI controller at 00:1f.2, iobase 0xf193d000, irq 10 |
| Searching bootorder for: /pci@i0cf8/pci-bridge@1c,1/*@0,2 |
| Found 0 lpt ports |
| Found 0 serial ports |
| Searching bootorder for: /rom@img/memtest |
| Searching bootorder for: /rom@img/nvramcui |
| PS2 keyboard initialized |
| XHCI no devices found |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-5 |
| AHCI/0: registering: "AHCI/0: TOSHIBA THNSNH256GMCT ATA-9 Hard-Disk (238 GiBytes)" |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f6640: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=500118192 |
| Space available for UMB: c7000-eb800, f5f00-f6640 |
| Returned 188416 bytes of ZoneHigh |
| e820 map has 9 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007feef000 = 1 RAM |
| 4: 000000007feef000 - 000000008ea00000 = 2 RESERVED |
| 5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED |
| 6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED |
| 7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED |
| 8: 0000000100000000 - 0000000371600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |