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| coreboot-4.0-7059-g30d0aa9 Sat Oct 18 14:14:58 CEST 2014 starting...
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| Intel ME early init
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| Intel ME firmware is ready
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| Row addr bits : 16
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| Column addr bits : 10
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| Number of ranks : 2
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| DIMM Capacity : 8192 MB
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| CAS latencies : 6 7 8 9 10 11
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| tCKmin : 1.250 ns
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| tAAmin : 13.125 ns
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| tWRmin : 15.000 ns
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| tRCDmin : 13.125 ns
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| tRRDmin : 6.000 ns
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| tRPmin : 13.125 ns
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| tRASmin : 35.000 ns
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| tRCmin : 48.125 ns
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| tRFCmin : 260.000 ns
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| tWTRmin : 7.500 ns
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| tRTPmin : 7.500 ns
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| tFAWmin : 30.000 ns
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| ME: FWS2: 0x39000006
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| ME: Bist in progress: 0x0
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| ME: ICC Status : 0x3
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| ME: Invoke MEBx : 0x0
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| ME: CPU replaced : 0x0
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| ME: MBP ready : 0x0
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| ME: MFS failure : 0x0
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| ME: Warm reset req : 0x0
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| ME: CPU repl valid : 0x0
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| ME: (Reserved) : 0x0
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| ME: FW update req : 0x0
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| ME: (Reserved) : 0x0
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| ME: Current state : 0x0
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| ME: Current PM event: 0x9
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| ME: Progress code : 0x3
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| Waited long enough, or CPU was not replaced, continue...
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| PASSED! Tell ME that DRAM is ready
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| ME: FWS2: 0x390b0006
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| ME: Bist in progress: 0x0
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| ME: ICC Status : 0x3
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| ME: Invoke MEBx : 0x0
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| ME: CPU replaced : 0x0
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| ME: MBP ready : 0x0
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| ME: MFS failure : 0x0
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| ME: Warm reset req : 0x0
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| ME: CPU repl valid : 0x0
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| ME: (Reserved) : 0x0
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| ME: FW update req : 0x0
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| ME: (Reserved) : 0x0
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| ME: Current state : 0xb
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| ME: Current PM event: 0x9
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| ME: Progress code : 0x3
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| ME: Requested BIOS Action: Continue to boot
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| CBFS: loading stage fallback/ramstage @ 0x100000 (393276 bytes), entry @ 0x100000
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| coreboot-4.0-7059-g30d0aa9 Sat Oct 18 14:14:58 CEST 2014 booting...
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| BS: Entering BS_PRE_DEVICE state.
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| CBMEM: recovering 6/254 entries from root @ bffff000
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| Moving GDT to bffda000...ok
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| BS: Exiting BS_PRE_DEVICE state.
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| BS: BS_PRE_DEVICE times (us): entry 26 run 16 exit 0
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| BS: Entering BS_DEV_INIT_CHIPS state.
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| BS: Exiting BS_DEV_INIT_CHIPS state.
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| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 20 exit 0
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| BS: Entering BS_DEV_ENUMERATE state.
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| Enumerating buses...
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| Show all devs...Before device enumeration.
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| Root Device: enabled 1
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| CPU_CLUSTER: 0: enabled 1
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| APIC: 00: enabled 1
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| APIC: acac: enabled 0
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| DOMAIN: 0000: enabled 1
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| PCI: 00:00.0: enabled 1
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| PCI: 00:01.0: enabled 1
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| PCI: 00:02.0: enabled 1
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| PCI: 00:16.0: enabled 1
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| PCI: 00:16.1: enabled 0
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| PCI: 00:16.2: enabled 0
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| PCI: 00:16.3: enabled 0
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| PCI: 00:19.0: enabled 1
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| PCI: 00:1a.0: enabled 1
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| PCI: 00:1b.0: enabled 1
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| PCI: 00:1c.0: enabled 0
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| PCI: 00:1c.1: enabled 1
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| PCI: 00:1c.2: enabled 0
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| PCI: 00:1c.3: enabled 1
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| PCI: 00:1c.4: enabled 1
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| PCI: 00:1c.5: enabled 0
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| PCI: 00:1c.6: enabled 0
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| PCI: 00:1c.7: enabled 0
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| PCI: 00:1d.0: enabled 1
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| PCI: 00:1f.0: enabled 1
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| PNP: 00ff.1: enabled 1
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| PNP: 00ff.2: enabled 1
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| PCI: 00:1f.2: enabled 1
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| PCI: 00:1f.3: enabled 1
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| I2C: 00:54: enabled 1
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| I2C: 00:55: enabled 1
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| I2C: 00:56: enabled 1
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| I2C: 00:57: enabled 1
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| I2C: 00:5c: enabled 1
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| I2C: 00:5d: enabled 1
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| I2C: 00:5e: enabled 1
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| I2C: 00:5f: enabled 1
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| Compare with tree...
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| Root Device: enabled 1
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| CPU_CLUSTER: 0: enabled 1
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| APIC: 00: enabled 1
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| APIC: acac: enabled 0
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| DOMAIN: 0000: enabled 1
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| PCI: 00:00.0: enabled 1
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| PCI: 00:01.0: enabled 1
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| PCI: 00:02.0: enabled 1
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| PCI: 00:16.0: enabled 1
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| PCI: 00:16.1: enabled 0
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| PCI: 00:16.2: enabled 0
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| PCI: 00:16.3: enabled 0
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| PCI: 00:19.0: enabled 1
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| PCI: 00:1a.0: enabled 1
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| PCI: 00:1b.0: enabled 1
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| PCI: 00:1c.0: enabled 0
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| PCI: 00:1c.1: enabled 1
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| PCI: 00:1c.2: enabled 0
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| PCI: 00:1c.3: enabled 1
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| PCI: 00:1c.4: enabled 1
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| PCI: 00:1c.5: enabled 0
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| PCI: 00:1c.6: enabled 0
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| PCI: 00:1c.7: enabled 0
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| PCI: 00:1d.0: enabled 1
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| PCI: 00:1f.0: enabled 1
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| PNP: 00ff.1: enabled 1
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| PNP: 00ff.2: enabled 1
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| PCI: 00:1f.2: enabled 1
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| PCI: 00:1f.3: enabled 1
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| I2C: 00:54: enabled 1
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| I2C: 00:55: enabled 1
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| I2C: 00:56: enabled 1
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| I2C: 00:57: enabled 1
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| I2C: 00:5c: enabled 1
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| I2C: 00:5d: enabled 1
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| I2C: 00:5e: enabled 1
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| I2C: 00:5f: enabled 1
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| scan_static_bus for Root Device
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| CPU_CLUSTER: 0 enabled
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| DOMAIN: 0000 enabled
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| DOMAIN: 0000 scanning...
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| PCI: pci_scan_bus for bus 00
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| PCI: 00:00.0 [8086/0104] ops
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| Normal boot.
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| PCI: 00:00.0 [8086/0104] enabled
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| PCI: Static device PCI: 00:01.0 not found, disabling it.
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| PCI: 00:02.0 [8086/0000] ops
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| PCI: 00:02.0 [8086/0126] enabled
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| PCI: 00:16.0 [8086/1c3a] bus ops
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| PCI: 00:16.0 [8086/1c3a] enabled
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| PCI: 00:16.1: Disabling device
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| PCI: 00:16.1 [8086/1c3b] disabled No operations
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| PCI: 00:16.2: Disabling device
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| PCI: 00:16.2 [8086/1c3c] disabled No operations
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| PCI: 00:16.3: Disabling device
|
| PCI: 00:16.3 [8086/1c3d] disabled No operations
|
| PCI: 00:19.0 [8086/1502] enabled
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| PCI: 00:1a.0 [8086/0000] ops
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| PCI: 00:1a.0 [8086/1c2d] enabled
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| PCI: 00:1b.0 [8086/0000] ops
|
| PCI: 00:1b.0 [8086/1c20] enabled
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| PCH: PCIe Root Port coalescing is enabled
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| PCI: 00:1c.0: Disabling device
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| PCI: 00:1c.0: check set enabled
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| PCH: Remap PCIe function 1 to 0
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| PCI: 00:1c.1 [8086/0000] bus ops
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| PCI: 00:1c.1 [8086/1c12] enabled
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| PCI: 00:1c.2: Disabling device
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| PCH: Remap PCIe function 3 to 0
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| PCI: 00:1c.3 [8086/0000] bus ops
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| PCI: 00:1c.3 [8086/1c16] enabled
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| PCH: Remap PCIe function 4 to 0
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| PCI: 00:1c.4 [8086/0000] bus ops
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| PCI: 00:1c.4 [8086/1c18] enabled
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| PCI: 00:1c.5: Disabling device
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| PCI: 00:1c.6: Disabling device
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| PCI: 00:1c.7: Disabling device
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| PCH: RPFN 0x76543210 -> 0xfed31a0c
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| PCH: PCIe map 1c.0 -> 1c.4
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| PCH: PCIe map 1c.1 -> 1c.0
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| PCH: PCIe map 1c.3 -> 1c.1
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| PCH: PCIe map 1c.4 -> 1c.3
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| PCI: 00:1d.0 [8086/0000] ops
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| PCI: 00:1d.0 [8086/1c26] enabled
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| PCI: 00:1f.0 [8086/0000] bus ops
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| PCI: 00:1f.0 [8086/1c4f] enabled
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| PCI: 00:1f.2 [8086/0000] ops
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| PCI: 00:1f.2 [8086/1c01] enabled
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| PCI: 00:1f.3 [8086/0000] bus ops
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| PCI: 00:1f.3 [8086/1c22] enabled
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| PCI: 00:1f.6 [8086/1c24] enabled
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| scan_static_bus for PCI: 00:16.0
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| scan_static_bus for PCI: 00:16.0 done
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| do_pci_scan_bridge for PCI: 00:1c.0
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| PCI: pci_scan_bus for bus 01
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| PCI: 01:00.0 [8086/4238] enabled
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| PCI: pci_scan_bus returning with max=001
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| Capability: type 0x01 @ 0xc8
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| Capability: type 0x05 @ 0xd0
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| Capability: type 0x10 @ 0xe0
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| Capability: type 0x10 @ 0x40
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| Enabling Common Clock Configuration
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| ASPM: Enabled L0s and L1
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| do_pci_scan_bridge returns max 1
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| do_pci_scan_bridge for PCI: 00:1c.1
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| PCI: pci_scan_bus for bus 02
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| PCI: pci_scan_bus returning with max=002
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| do_pci_scan_bridge returns max 2
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| do_pci_scan_bridge for PCI: 00:1c.3
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| PCI: pci_scan_bus for bus 03
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| PCI: 03:00.0 [1180/e823] enabled
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| PCI: 03:00.1 [1180/e232] enabled
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| PCI: 03:00.2 [1180/e852] enabled
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| PCI: 03:00.3 [1180/e832] enabled
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| PCI: pci_scan_bus returning with max=003
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| Capability: type 0x05 @ 0x50
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| Capability: type 0x01 @ 0x78
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| Capability: type 0x10 @ 0x80
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| Capability: type 0x10 @ 0x40
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| Enabling Common Clock Configuration
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| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
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| Capability: type 0x01 @ 0x78
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| Capability: type 0x10 @ 0x80
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| Capability: type 0x10 @ 0x40
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| Enabling Common Clock Configuration
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| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
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| Capability: type 0x01 @ 0x78
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| Capability: type 0x10 @ 0x80
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| Capability: type 0x10 @ 0x40
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| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
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| Capability: type 0x10 @ 0x80
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| Capability: type 0x10 @ 0x40
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| Enabling Common Clock Configuration
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| ASPM: Enabled L0s and L1
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| do_pci_scan_bridge returns max 3
|
| scan_static_bus for PCI: 00:1f.0
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| PNP: 00ff.1 enabled
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| recv_ec_data: 0x38
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| recv_ec_data: 0x41
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| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x34
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| recv_ec_data: 0x32
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x14
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| recv_ec_data: 0x03
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| recv_ec_data: 0x60
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| recv_ec_data: 0x13
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| EC Firmware ID 8AHT42WW-3.20, Version 6.01D
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| recv_ec_data: 0x70
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| recv_ec_data: 0x10
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| recv_ec_data: 0x70
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| recv_ec_data: 0x70
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| recv_ec_data: 0x00
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| recv_ec_data: 0xa7
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| recv_ec_data: 0xc2
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| recv_ec_data: 0x70
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| PNP: 00ff.2 enabled
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| scan_static_bus for PCI: 00:1f.0 done
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| scan_static_bus for PCI: 00:1f.3
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| smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
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| smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
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| scan_static_bus for PCI: 00:1f.3 done
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| PCI: pci_scan_bus returning with max=003
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| scan_static_bus for Root Device done
|
| done
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| BS: Exiting BS_DEV_ENUMERATE state.
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| BS: BS_DEV_ENUMERATE times (us): entry 0 run 9724 exit 0
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| BS: Entering BS_DEV_RESOURCES state.
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| found VGA at PCI: 00:02.0
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| Setting up VGA for PCI: 00:02.0
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| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
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| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
| Allocating resources...
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| Reading resources...
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| Root Device read_resources bus 0 link: 0
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| CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
| APIC: 00 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0
|
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
| PCI: 00:1c.0 read_resources bus 1 link: 0
|
| PCI: 00:1c.0 read_resources bus 1 link: 0 done
|
| PCI: 00:1c.1 read_resources bus 2 link: 0
|
| PCI: 00:1c.1 read_resources bus 2 link: 0 done
|
| PCI: 00:1c.3 read_resources bus 3 link: 0
|
| PCI: 00:1c.3 read_resources bus 3 link: 0 done
|
| PCI: 00:1f.0 read_resources bus 0 link: 0
|
| PNP: 00ff.1 missing read_resources
|
| PNP: 00ff.2 missing read_resources
|
| PCI: 00:1f.0 read_resources bus 0 link: 0 done
|
| PCI: 00:1f.3 read_resources bus 1 link: 0
|
| PCI: 00:1f.3 read_resources bus 1 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0 done
|
| Root Device read_resources bus 0 link: 0 done
|
| Done reading resources.
|
| Show resources in subtree (Root Device)...After reading.
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| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
|
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
|
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.4
|
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0
|
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.1
|
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.3 child on link 0 PCI: 03:00.0
|
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 03:00.0
|
| PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 03:00.1
|
| PCI: 03:00.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 03:00.2
|
| PCI: 03:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 03:00.3
|
| PCI: 03:00.3 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
|
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.6
|
| PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
|
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:02.0 20 * [0x0 - 0x3f] io
|
| PCI: 00:19.0 18 * [0x40 - 0x5f] io
|
| PCI: 00:1f.2 20 * [0x60 - 0x7f] io
|
| PCI: 00:1f.2 10 * [0x80 - 0x87] io
|
| PCI: 00:1f.2 18 * [0x88 - 0x8f] io
|
| PCI: 00:1f.2 14 * [0x90 - 0x93] io
|
| PCI: 00:1f.2 1c * [0x94 - 0x97] io
|
| DOMAIN: 0000 compute_resources_io: base: 98 size: 98 align: 6 gran: 0 limit: ffff done
|
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
|
| PCI: 00:1c.0 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 03:00.3 10 * [0x0 - 0x7ff] mem
|
| PCI: 03:00.0 10 * [0x800 - 0x8ff] mem
|
| PCI: 03:00.1 10 * [0x900 - 0x9ff] mem
|
| PCI: 03:00.2 10 * [0xa00 - 0xaff] mem
|
| PCI: 00:1c.3 compute_resources_mem: base: b00 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
|
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
|
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem
|
| PCI: 00:1c.3 20 * [0x10500000 - 0x105fffff] mem
|
| PCI: 00:19.0 10 * [0x10600000 - 0x1061ffff] mem
|
| PCI: 00:1b.0 10 * [0x10620000 - 0x10623fff] mem
|
| PCI: 00:19.0 14 * [0x10624000 - 0x10624fff] mem
|
| PCI: 00:1f.6 10 * [0x10625000 - 0x10625fff] mem
|
| PCI: 00:1f.2 24 * [0x10626000 - 0x106267ff] mem
|
| PCI: 00:1a.0 10 * [0x10626800 - 0x10626bff] mem
|
| PCI: 00:1d.0 10 * [0x10626c00 - 0x10626fff] mem
|
| PCI: 00:1f.3 10 * [0x10627000 - 0x106270ff] mem
|
| PCI: 00:16.0 10 * [0x10627100 - 0x1062710f] mem
|
| DOMAIN: 0000 compute_resources_mem: base: 10627110 size: 10627110 align: 28 gran: 0 limit: ffffffff done
|
| avoid_fixed_resources: DOMAIN: 0000
|
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
| constrain_resources: DOMAIN: 0000
|
| constrain_resources: PCI: 00:00.0
|
| constrain_resources: PCI: 00:02.0
|
| constrain_resources: PCI: 00:16.0
|
| constrain_resources: PCI: 00:19.0
|
| constrain_resources: PCI: 00:1a.0
|
| constrain_resources: PCI: 00:1b.0
|
| constrain_resources: PCI: 00:1c.0
|
| constrain_resources: PCI: 01:00.0
|
| constrain_resources: PCI: 00:1c.1
|
| constrain_resources: PCI: 00:1c.3
|
| constrain_resources: PCI: 03:00.0
|
| constrain_resources: PCI: 03:00.1
|
| constrain_resources: PCI: 03:00.2
|
| constrain_resources: PCI: 03:00.3
|
| constrain_resources: PCI: 00:1d.0
|
| constrain_resources: PCI: 00:1f.0
|
| constrain_resources: PNP: 00ff.1
|
| constrain_resources: PNP: 00ff.2
|
| skipping PNP: 00ff.2@60 fixed resource, size=0!
|
| skipping PNP: 00ff.2@62 fixed resource, size=0!
|
| skipping PNP: 00ff.2@64 fixed resource, size=0!
|
| skipping PNP: 00ff.2@66 fixed resource, size=0!
|
| constrain_resources: PCI: 00:1f.2
|
| constrain_resources: PCI: 00:1f.3
|
| constrain_resources: I2C: 01:54
|
| constrain_resources: I2C: 01:55
|
| constrain_resources: I2C: 01:56
|
| constrain_resources: I2C: 01:57
|
| constrain_resources: I2C: 01:5c
|
| constrain_resources: I2C: 01:5d
|
| constrain_resources: I2C: 01:5e
|
| constrain_resources: I2C: 01:5f
|
| constrain_resources: PCI: 00:1f.6
|
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
|
| lim->base 0000167c lim->limit 0000ffff
|
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
|
| lim->base 00000000 lim->limit efffffff
|
| Setting resources...
|
| DOMAIN: 0000 allocate_resources_io: base:167c size:98 align:6 gran:0 limit:ffff
|
| Assigned: PCI: 00:02.0 20 * [0x1800 - 0x183f] io
|
| Assigned: PCI: 00:19.0 18 * [0x1840 - 0x185f] io
|
| Assigned: PCI: 00:1f.2 20 * [0x1860 - 0x187f] io
|
| Assigned: PCI: 00:1f.2 10 * [0x1880 - 0x1887] io
|
| Assigned: PCI: 00:1f.2 18 * [0x1888 - 0x188f] io
|
| Assigned: PCI: 00:1f.2 14 * [0x1890 - 0x1893] io
|
| Assigned: PCI: 00:1f.2 1c * [0x1894 - 0x1897] io
|
| DOMAIN: 0000 allocate_resources_io: next_base: 1898 size: 98 align: 6 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10627110 align:28 gran:0 limit:efffffff
|
| Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
|
| Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
|
| Assigned: PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem
|
| Assigned: PCI: 00:1c.3 20 * [0xe0500000 - 0xe05fffff] mem
|
| Assigned: PCI: 00:19.0 10 * [0xe0600000 - 0xe061ffff] mem
|
| Assigned: PCI: 00:1b.0 10 * [0xe0620000 - 0xe0623fff] mem
|
| Assigned: PCI: 00:19.0 14 * [0xe0624000 - 0xe0624fff] mem
|
| Assigned: PCI: 00:1f.6 10 * [0xe0625000 - 0xe0625fff] mem
|
| Assigned: PCI: 00:1f.2 24 * [0xe0626000 - 0xe06267ff] mem
|
| Assigned: PCI: 00:1a.0 10 * [0xe0626800 - 0xe0626bff] mem
|
| Assigned: PCI: 00:1d.0 10 * [0xe0626c00 - 0xe0626fff] mem
|
| Assigned: PCI: 00:1f.3 10 * [0xe0627000 - 0xe06270ff] mem
|
| Assigned: PCI: 00:16.0 10 * [0xe0627100 - 0xe062710f] mem
|
| DOMAIN: 0000 allocate_resources_mem: next_base: e0627110 size: 10627110 align: 28 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 01:00.0 10 * [0xe0400000 - 0xe0401fff] mem
|
| PCI: 00:1c.0 allocate_resources_mem: next_base: e0402000 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.1 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.3 allocate_resources_mem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 03:00.3 10 * [0xe0500000 - 0xe05007ff] mem
|
| Assigned: PCI: 03:00.0 10 * [0xe0500800 - 0xe05008ff] mem
|
| Assigned: PCI: 03:00.1 10 * [0xe0500900 - 0xe05009ff] mem
|
| Assigned: PCI: 03:00.2 10 * [0xe0500a00 - 0xe0500aff] mem
|
| PCI: 00:1c.3 allocate_resources_mem: next_base: e0500b00 size: 100000 align: 20 gran: 20 done
|
| Root Device assign_resources, bus 0 link: 0
|
| TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000
|
| MEBASE 0x1fe000000
|
| IGD decoded, subtracting 32M UMA and 2M GTT
|
| TSEG base 0xc0000000 size 8M
|
| Available memory below 4GB: 3072M
|
| Available memory above 4GB: 5046M
|
| Adding PCIe config bar base=0xf0000000 size=0x4000000
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
|
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
|
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
|
| PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io
|
| PCI: 00:16.0 10 <- [0x00e0627100 - 0x00e062710f] size 0x00000010 gran 0x04 mem64
|
| PCI: 00:19.0 10 <- [0x00e0600000 - 0x00e061ffff] size 0x00020000 gran 0x11 mem
|
| PCI: 00:19.0 14 <- [0x00e0624000 - 0x00e0624fff] size 0x00001000 gran 0x0c mem
|
| PCI: 00:19.0 18 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1a.0 10 <- [0x00e0626800 - 0x00e0626bff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1b.0 10 <- [0x00e0620000 - 0x00e0623fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
| PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
|
| PCI: 00:1c.0 assign_resources, bus 1 link: 0
|
| PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e0401fff] size 0x00002000 gran 0x0d mem64
|
| PCI: 00:1c.0 assign_resources, bus 1 link: 0
|
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
| PCI: 00:1c.1 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem
|
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
|
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
| PCI: 00:1c.3 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 03 mem
|
| PCI: 00:1c.3 assign_resources, bus 3 link: 0
|
| PCI: 03:00.0 10 <- [0x00e0500800 - 0x00e05008ff] size 0x00000100 gran 0x08 mem
|
| PCI: 03:00.1 10 <- [0x00e0500900 - 0x00e05009ff] size 0x00000100 gran 0x08 mem
|
| PCI: 03:00.2 10 <- [0x00e0500a00 - 0x00e0500aff] size 0x00000100 gran 0x08 mem
|
| PCI: 03:00.3 10 <- [0x00e0500000 - 0x00e05007ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1c.3 assign_resources, bus 3 link: 0
|
| PCI: 00:1d.0 10 <- [0x00e0626c00 - 0x00e0626fff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PNP: 00ff.1 missing set_resources
|
| PNP: 00ff.2 missing set_resources
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PCI: 00:1f.2 10 <- [0x0000001880 - 0x0000001887] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 14 <- [0x0000001890 - 0x0000001893] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 18 <- [0x0000001888 - 0x000000188f] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 1c <- [0x0000001894 - 0x0000001897] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 20 <- [0x0000001860 - 0x000000187f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1f.2 24 <- [0x00e0626000 - 0x00e06267ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1f.3 10 <- [0x00e0627000 - 0x00e06270ff] size 0x00000100 gran 0x08 mem64
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| PCI: 00:1f.6 10 <- [0x00e0625000 - 0x00e0625fff] size 0x00001000 gran 0x0c mem64
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| Root Device assign_resources, bus 0 link: 0
|
| Done setting resources.
|
| Show resources in subtree (Root Device)...After assigning values.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 167c size 98 align 6 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base d0000000 size 10627110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
|
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
|
| DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
|
| DOMAIN: 0000 resource base 100000000 size 13b600000 align 0 gran 0 limit 0 flags e0004200 index 5
|
| DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
|
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
|
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
|
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
|
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10
|
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
|
| PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base e0627100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base e0600000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10
|
| PCI: 00:19.0 resource base e0624000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14
|
| PCI: 00:19.0 resource base 1840 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base e0626800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base e0620000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.4
|
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0
|
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base e0400000 size 2000 align 13 gran 13 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.1
|
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 00:1c.3 child on link 0 PCI: 03:00.0
|
| PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.3 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 03:00.0
|
| PCI: 03:00.0 resource base e0500800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 03:00.1
|
| PCI: 03:00.1 resource base e0500900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 03:00.2
|
| PCI: 03:00.2 resource base e0500a00 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 03:00.3
|
| PCI: 03:00.3 resource base e0500000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base e0626c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 1880 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
|
| PCI: 00:1f.2 resource base 1890 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
|
| PCI: 00:1f.2 resource base 1888 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
|
| PCI: 00:1f.2 resource base 1894 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
|
| PCI: 00:1f.2 resource base 1860 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
|
| PCI: 00:1f.2 resource base e0626000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base e0627000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.6
|
| PCI: 00:1f.6 resource base e0625000 size 1000 align 12 gran 12 limit efffffff flags 60000201 index 10
|
| Done allocating resources.
|
| BS: Exiting BS_DEV_RESOURCES state.
|
| BS: BS_DEV_RESOURCES times (us): entry 0 run 15812 exit 0
|
| BS: Entering BS_DEV_ENABLE state.
|
| Enabling resources...
|
| PCI: 00:00.0 subsystem <- 0000/0000
|
| PCI: 00:00.0 cmd <- 06
|
| PCI: 00:02.0 subsystem <- 0000/0000
|
| PCI: 00:02.0 cmd <- 03
|
| PCI: 00:16.0 subsystem <- 0000/0000
|
| PCI: 00:16.0 cmd <- 02
|
| PCI: 00:19.0 subsystem <- 0000/0000
|
| PCI: 00:19.0 cmd <- 103
|
| PCI: 00:1a.0 subsystem <- 0000/0000
|
| PCI: 00:1a.0 cmd <- 102
|
| PCI: 00:1b.0 subsystem <- 0000/0000
|
| PCI: 00:1b.0 cmd <- 102
|
| PCI: 00:1c.0 bridge ctrl <- 0003
|
| PCI: 00:1c.0 subsystem <- 0000/0000
|
| PCI: 00:1c.0 cmd <- 106
|
| PCI: 00:1c.1 bridge ctrl <- 0003
|
| PCI: 00:1c.1 subsystem <- 0000/0000
|
| PCI: 00:1c.1 cmd <- 100
|
| PCI: 00:1c.3 bridge ctrl <- 0003
|
| PCI: 00:1c.3 subsystem <- 0000/0000
|
| PCI: 00:1c.3 cmd <- 106
|
| PCI: 00:1d.0 subsystem <- 0000/0000
|
| PCI: 00:1d.0 cmd <- 102
|
| pch_decode_init
|
| PCI: 00:1f.0 subsystem <- 0000/0000
|
| PCI: 00:1f.0 cmd <- 107
|
| PCI: 00:1f.2 subsystem <- 0000/0000
|
| PCI: 00:1f.2 cmd <- 03
|
| PCI: 00:1f.3 subsystem <- 0000/0000
|
| PCI: 00:1f.3 cmd <- 103
|
| PCI: 00:1f.6 cmd <- 02
|
| PCI: 01:00.0 cmd <- 02
|
| PCI: 03:00.0 cmd <- 06
|
| PCI: 03:00.1 cmd <- 06
|
| PCI: 03:00.2 cmd <- 06
|
| PCI: 03:00.3 cmd <- 02
|
| done.
|
| BS: Exiting BS_DEV_ENABLE state.
|
| BS: BS_DEV_ENABLE times (us): entry 0 run 778 exit 0
|
| BS: Entering BS_DEV_INIT state.
|
| Initializing devices...
|
| Root Device init
|
| Keyboard init...
|
| Keyboard controller output buffer result timeout
|
| Root Device init 513093 usecs
|
| CPU_CLUSTER: 0 init
|
| start_eip=0x00001000, code_size=0x00000031
|
| Installing SMM handler to 0xc0000000
|
| Installing IED header to 0xc0400000
|
| Initializing SMM handler... ... pmbase = 0x0500
|
|
|
| SMI_STS: INTEL_USB2 MCSMI
|
| PM1_STS:
|
| GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0
|
| ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI5 GPI4 GPI3 GPI1 GPI0
|
| TCO_STS:
|
| ... raise SMI#
|
| Initializing CPU #0
|
| CPU: vendor Intel device 206a7
|
| CPU: family 06, model 2a, stepping 07
|
| Enabling cache
|
| microcode: sig=0x206a7 pf=0x10 revision=0x28
|
| CPU: Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz.
|
| MTRR: Physical address space:
|
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
|
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
|
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
|
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
|
| 0x0000000100000000 - 0x000000023b600000 size 0x13b600000 type 6
|
| MTRR addr 0x0-0x10 set to 6 type @ 0
|
| MTRR addr 0x10-0x20 set to 6 type @ 1
|
| MTRR addr 0x20-0x30 set to 6 type @ 2
|
| MTRR addr 0x30-0x40 set to 6 type @ 3
|
| MTRR addr 0x40-0x50 set to 6 type @ 4
|
| MTRR addr 0x50-0x60 set to 6 type @ 5
|
| MTRR addr 0x60-0x70 set to 6 type @ 6
|
| MTRR addr 0x70-0x80 set to 6 type @ 7
|
| MTRR addr 0x80-0x84 set to 6 type @ 8
|
| MTRR addr 0x84-0x88 set to 6 type @ 9
|
| MTRR addr 0x88-0x8c set to 6 type @ 10
|
| MTRR addr 0x8c-0x90 set to 6 type @ 11
|
| MTRR addr 0x90-0x94 set to 6 type @ 12
|
| MTRR addr 0x94-0x98 set to 6 type @ 13
|
| MTRR addr 0x98-0x9c set to 6 type @ 14
|
| MTRR addr 0x9c-0xa0 set to 6 type @ 15
|
| MTRR addr 0xa0-0xa4 set to 0 type @ 16
|
| MTRR addr 0xa4-0xa8 set to 0 type @ 17
|
| MTRR addr 0xa8-0xac set to 0 type @ 18
|
| MTRR addr 0xac-0xb0 set to 0 type @ 19
|
| MTRR addr 0xb0-0xb4 set to 0 type @ 20
|
| MTRR addr 0xb4-0xb8 set to 0 type @ 21
|
| MTRR addr 0xb8-0xbc set to 0 type @ 22
|
| MTRR addr 0xbc-0xc0 set to 0 type @ 23
|
| MTRR addr 0xc0-0xc1 set to 6 type @ 24
|
| MTRR addr 0xc1-0xc2 set to 6 type @ 25
|
| MTRR addr 0xc2-0xc3 set to 6 type @ 26
|
| MTRR addr 0xc3-0xc4 set to 6 type @ 27
|
| MTRR addr 0xc4-0xc5 set to 6 type @ 28
|
| MTRR addr 0xc5-0xc6 set to 6 type @ 29
|
| MTRR addr 0xc6-0xc7 set to 6 type @ 30
|
| MTRR addr 0xc7-0xc8 set to 6 type @ 31
|
| MTRR addr 0xc8-0xc9 set to 6 type @ 32
|
| MTRR addr 0xc9-0xca set to 6 type @ 33
|
| MTRR addr 0xca-0xcb set to 6 type @ 34
|
| MTRR addr 0xcb-0xcc set to 6 type @ 35
|
| MTRR addr 0xcc-0xcd set to 6 type @ 36
|
| MTRR addr 0xcd-0xce set to 6 type @ 37
|
| MTRR addr 0xce-0xcf set to 6 type @ 38
|
| MTRR addr 0xcf-0xd0 set to 6 type @ 39
|
| MTRR addr 0xd0-0xd1 set to 6 type @ 40
|
| MTRR addr 0xd1-0xd2 set to 6 type @ 41
|
| MTRR addr 0xd2-0xd3 set to 6 type @ 42
|
| MTRR addr 0xd3-0xd4 set to 6 type @ 43
|
| MTRR addr 0xd4-0xd5 set to 6 type @ 44
|
| MTRR addr 0xd5-0xd6 set to 6 type @ 45
|
| MTRR addr 0xd6-0xd7 set to 6 type @ 46
|
| MTRR addr 0xd7-0xd8 set to 6 type @ 47
|
| MTRR addr 0xd8-0xd9 set to 6 type @ 48
|
| MTRR addr 0xd9-0xda set to 6 type @ 49
|
| MTRR addr 0xda-0xdb set to 6 type @ 50
|
| MTRR addr 0xdb-0xdc set to 6 type @ 51
|
| MTRR addr 0xdc-0xdd set to 6 type @ 52
|
| MTRR addr 0xdd-0xde set to 6 type @ 53
|
| MTRR addr 0xde-0xdf set to 6 type @ 54
|
| MTRR addr 0xdf-0xe0 set to 6 type @ 55
|
| MTRR addr 0xe0-0xe1 set to 6 type @ 56
|
| MTRR addr 0xe1-0xe2 set to 6 type @ 57
|
| MTRR addr 0xe2-0xe3 set to 6 type @ 58
|
| MTRR addr 0xe3-0xe4 set to 6 type @ 59
|
| MTRR addr 0xe4-0xe5 set to 6 type @ 60
|
| MTRR addr 0xe5-0xe6 set to 6 type @ 61
|
| MTRR addr 0xe6-0xe7 set to 6 type @ 62
|
| MTRR addr 0xe7-0xe8 set to 6 type @ 63
|
| MTRR addr 0xe8-0xe9 set to 6 type @ 64
|
| MTRR addr 0xe9-0xea set to 6 type @ 65
|
| MTRR addr 0xea-0xeb set to 6 type @ 66
|
| MTRR addr 0xeb-0xec set to 6 type @ 67
|
| MTRR addr 0xec-0xed set to 6 type @ 68
|
| MTRR addr 0xed-0xee set to 6 type @ 69
|
| MTRR addr 0xee-0xef set to 6 type @ 70
|
| MTRR addr 0xef-0xf0 set to 6 type @ 71
|
| MTRR addr 0xf0-0xf1 set to 6 type @ 72
|
| MTRR addr 0xf1-0xf2 set to 6 type @ 73
|
| MTRR addr 0xf2-0xf3 set to 6 type @ 74
|
| MTRR addr 0xf3-0xf4 set to 6 type @ 75
|
| MTRR addr 0xf4-0xf5 set to 6 type @ 76
|
| MTRR addr 0xf5-0xf6 set to 6 type @ 77
|
| MTRR addr 0xf6-0xf7 set to 6 type @ 78
|
| MTRR addr 0xf7-0xf8 set to 6 type @ 79
|
| MTRR addr 0xf8-0xf9 set to 6 type @ 80
|
| MTRR addr 0xf9-0xfa set to 6 type @ 81
|
| MTRR addr 0xfa-0xfb set to 6 type @ 82
|
| MTRR addr 0xfb-0xfc set to 6 type @ 83
|
| MTRR addr 0xfc-0xfd set to 6 type @ 84
|
| MTRR addr 0xfd-0xfe set to 6 type @ 85
|
| MTRR addr 0xfe-0xff set to 6 type @ 86
|
| MTRR addr 0xff-0x100 set to 6 type @ 87
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: default type WB/UC MTRR counts: 3/10.
|
| MTRR: WB selected as default type.
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x00 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2700
|
| Turbo is available but hidden
|
| Turbo has been enabled
|
| CPU: 0 has 2 cores, 2 threads per core
|
| CPU: 0 has core 1
|
| CPU1: stack_base 0015a000, stack_end 0015aff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 1.
|
| After apic_write.
|
| Initializing CPU #1
|
| Startup point 1.
|
| CPU: vendor Intel device 206a7
|
| Waiting for send to finish...
|
| CPU: family 06, model 2a, stepping 07
|
| +Enabling cache
|
| Sending STARTUP #2 to 1.
|
| After apic_write.
|
| microcode: sig=0x206a7 pf=0x10 revision=0x28
|
| CPU: Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| CPU: 0 has core 2
|
| CPU2: stack_base 00159000, stack_end 00159ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 2.
|
| After apic_write.
|
| Initializing CPU #2
|
| CPU: vendor Intel device 206a7
|
| call enable_fixed_mtrr()
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: family 06, model 2a, stepping 07
|
| Enabling cache
|
| microcode: sig=0x206a7 pf=0x10 revision=0x0
|
|
|
| MTRR check
|
| Sending STARTUP #2 to 2.
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| After apic_write.
|
| Setting up local apic... apic_id: 0x01 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2700
|
| CPU #1 initialized
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| CPU: 0 has core 3
|
| CPU3: stack_base 00158000, stack_end 00158ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 3.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Sending STARTUP #2 to 3.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| microcode: updated to revision 0x28 date=2012-04-24
|
| CPU #0 initialized
|
| Waiting for 2 CPUS to stop
|
| Initializing CPU #3
|
| CPU: Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz.
|
| CPU: vendor Intel device 206a7
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| CPU: family 06, model 2a, stepping 07
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| Enabling cache
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| microcode: sig=0x206a7 pf=0x10 revision=0x28
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| CPU: Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz.
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
|
| MTRR check
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x02 done.
|
| Enabling VMX
|
| call enable_fixed_mtrr()
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2700
|
| CPU #2 initialized
|
| Waiting for 1 CPUS to stop
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x03 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2700
|
| CPU #3 initialized
|
| All AP CPUs stopped (5180 loops)
|
| CPU1: stack: 0015a000 - 0015b000, lowest used address 0015ac50, stack used: 944 bytes
|
| CPU2: stack: 00159000 - 0015a000, lowest used address 00159c50, stack used: 944 bytes
|
| CPU3: stack: 00158000 - 00159000, lowest used address 00158c50, stack used: 944 bytes
|
| CPU_CLUSTER: 0 init 78501 usecs
|
| PCI: 00:00.0 init
|
| Set BIOS_RESET_CPL
|
| CPU TDP: 35 Watts
|
| PCI: 00:00.0 init 1010 usecs
|
| PCI: 00:02.0 init
|
| GT Power Management Init
|
| SNB GT2 Power Meter Weights
|
| GT Power Management Init (post VBIOS)
|
| Initializing VGA without OPROM.
|
| EDID:
|
| 00 ff ff ff ff ff ff 00 30 ae b1 40 00 00 00 00
|
| 00 13 01 03 80 23 13 78 ea 43 c5 9c 59 51 96 26
|
| 11 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
|
| 01 01 01 01 01 01 62 2a 40 40 61 84 2a 30 30 20
|
| 35 00 59 c2 10 00 00 19 53 23 40 40 61 84 2a 30
|
| 30 20 35 00 59 c2 10 00 00 19 00 00 00 0f 00 a9
|
| 09 32 a9 09 28 16 09 00 30 e4 00 02 00 00 00 fe
|
| 00 4c 50 31 35 36 57 44 31 2d 54 4c 42 32 00 e2
|
| Extracted contents:
|
| header: 00 ff ff ff ff ff ff 00
|
| serial number: 30 ae b1 40 00 00 00 00 00 13
|
| version: 01 03
|
| basic params: 80 23 13 78 ea
|
| chroma info: 43 c5 9c 59 51 96 26 11 50 54
|
| established: 00 00 00
|
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
| descriptor 1: 62 2a 40 40 61 84 2a 30 30 20 35 00 59 c2 10 00 00 19
|
| descriptor 2: 53 23 40 40 61 84 2a 30 30 20 35 00 59 c2 10 00 00 19
|
| descriptor 3: 00 00 00 0f 00 a9 09 32 a9 09 28 16 09 00 30 e4 00 02
|
| descriptor 4: 00 00 00 fe 00 4c 50 31 35 36 57 44 31 2d 54 4c 42 32
|
| extensions: 00
|
| checksum: e2
|
|
|
| Manufacturer: LEN Model 40b1 Serial Number 0
|
| Made week 0 of 2009
|
| EDID version: 1.3
|
| Digital display
|
| Maximum image size: 35 cm x 19 cm
|
| Gamma: 220%
|
| Check DPMS levels
|
| DPMS levels: Standby Suspend Off
|
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2
|
| First detailed timing is preferred timing
|
| Established timings supported:
|
| Standard timings supported:
|
| Detailed timings
|
| Hex of detail: 622a404061842a303020350059c210000019
|
| Did detailed timing
|
| Detailed mode (IN HEX): Clock 108500 KHz, 159 mm x c2 mm
|
| 0640 0670 0690 0780 hborder 0
|
| 0384 0387 038c 03ae vborder 0
|
| -hsync -vsync
|
| Hex of detail: 5323404061842a303020350059c210000019
|
| Detailed mode (IN HEX): Clock 108500 KHz, 159 mm x c2 mm
|
| 0640 0670 0690 0780 hborder 0
|
| 0384 0387 038c 03ae vborder 0
|
| -hsync -vsync
|
| Hex of detail: 0000000f00a90932a9092816090030e40002
|
| Manufacturer-specified data, tag 15
|
| Hex of detail: 000000fe004c503135365744312d544c4232
|
| ASCII string: LP156WD1-TLB2
|
| Checksum
|
| Checksum: 0xe2 (valid)
|
| WARNING: EDID block does NOT fully conform to EDID 1.3.
|
| Missing name descriptor
|
| Missing monitor ranges
|
| bringing up panel at resolution 1600 x 900
|
| Borders 0 x 0
|
| Blank 320 x 42
|
| Sync 32 x 5
|
| Front porch 48 x 3
|
| Spread spectrum clock
|
| Dual channel
|
| Polarities 1, 1
|
| Data M1=1896174, N1=8388608
|
| Link frequency 270000 kHz
|
| Link M1=210686, N1=524288
|
| Pixel N=9, M1=21, M2=9, P1=2
|
| Pixel clock 108571 kHz
|
| waiting for panel powerup
|
| panel powered up
|
| PCI: 00:02.0 init 28091 usecs
|
| PCI: 00:16.0 init
|
| ME: BIOS path: Normal
|
| ME: Extend SHA-256: 208006c98f970add1ef658ba5ba52ae56cf4018b2151459dfb7e7cc71c29897f
|
| PCI: 00:16.0 init 14 usecs
|
| PCI: 00:19.0 init
|
| PCI: 00:19.0 init 1 usecs
|
| PCI: 00:1a.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1a.0 init 13 usecs
|
| PCI: 00:1b.0 init
|
| Azalia: base = e0620000
|
| Azalia: codec_mask = 09
|
| Azalia: Initializing codec #3
|
| Azalia: codec viddid: 80862805
|
| Azalia: No verb!
|
| Azalia: Initializing codec #0
|
| Azalia: codec viddid: 14f1506e
|
| Azalia: verb_size: 52
|
| Azalia: verb loaded.
|
| PCI: 00:1b.0 init 4305 usecs
|
| PCI: 00:1c.0 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.0 init 8 usecs
|
| PCI: 00:1c.1 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.1 init 8 usecs
|
| PCI: 00:1c.3 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.3 init 10 usecs
|
| PCI: 00:1d.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1d.0 init 12 usecs
|
| PCI: 00:1f.0 init
|
| pch: lpc_init
|
| IOAPIC: Initializing IOAPIC at 0xfec00000
|
| IOAPIC: Bootstrap Processor Local APIC = 0x00
|
| IOAPIC: ID = 0x02
|
| IOAPIC: Dumping registers
|
| reg 0x0000: 0x02000000
|
| reg 0x0001: 0x00170020
|
| reg 0x0002: 0x00170020
|
| Set power on after power failure.
|
| NMI sources enabled.
|
| CougarPoint PM init
|
| rtc_failed = 0x0
|
| RTC Init
|
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
|
| done.
|
| Locking SMM.
|
| PCI: 00:1f.0 init 731 usecs
|
| PCI: 00:1f.2 init
|
| SATA: Initializing...
|
| SATA: Controller in AHCI mode.
|
| ABAR: E0626000
|
| PCI: 00:1f.2 init 278 usecs
|
| PCI: 00:1f.3 init
|
| PCI: 00:1f.3 init 8 usecs
|
| PCI: 00:1f.6 init
|
| PCI: 00:1f.6 init 1 usecs
|
| PCI: 01:00.0 init
|
| PCI: 01:00.0 init 1 usecs
|
| PCI: 03:00.0 init
|
| PCI: 03:00.0 init 1 usecs
|
| PCI: 03:00.1 init
|
| PCI: 03:00.1 init 0 usecs
|
| PCI: 03:00.2 init
|
| PCI: 03:00.2 init 0 usecs
|
| PCI: 03:00.3 init
|
| PCI: 03:00.3 init 0 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
| I2C: 01:54 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
| I2C: 01:55 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
| I2C: 01:56 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
| I2C: 01:57 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
| Locking EEPROM RFID
|
| init EEPROM done
|
| I2C: 01:5c init 25580 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
| I2C: 01:5d init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
| I2C: 01:5e init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
| I2C: 01:5f init 1 usecs
|
| Devices initialized
|
| Show all devs...After init.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.2: enabled 0
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 01:54: enabled 1
|
| I2C: 01:55: enabled 1
|
| I2C: 01:56: enabled 1
|
| I2C: 01:57: enabled 1
|
| I2C: 01:5c: enabled 1
|
| I2C: 01:5d: enabled 1
|
| I2C: 01:5e: enabled 1
|
| I2C: 01:5f: enabled 1
|
| PCI: 00:1f.6: enabled 1
|
| PCI: 01:00.0: enabled 1
|
| PCI: 03:00.0: enabled 1
|
| PCI: 03:00.1: enabled 1
|
| PCI: 03:00.2: enabled 1
|
| PCI: 03:00.3: enabled 1
|
| APIC: 01: enabled 1
|
| APIC: 02: enabled 1
|
| APIC: 03: enabled 1
|
| BS: Exiting BS_DEV_INIT state.
|
| BS: BS_DEV_INIT times (us): entry 0 run 651735 exit 0
|
| BS: Entering BS_POST_DEVICE state.
|
| Finalize devices...
|
| Devices finalized
|
| BS: Exiting BS_POST_DEVICE state.
|
| BS: BS_POST_DEVICE times (us): entry 0 run 2 exit 0
|
| BS: Entering BS_OS_RESUME_CHECK state.
|
| BS: Exiting BS_OS_RESUME_CHECK state.
|
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
|
| BS: Entering BS_WRITE_TABLES state.
|
| Updating MRC cache data.
|
| find_current_mrc_cache_local: picked entry 2 from cache block
|
| SF: Detected M25P64 with page size 10000, total 800000
|
| find_next_mrc_cache: picked next entry from cache block at fffe3000
|
| Finally: write MRC cache update to flash at fffe3000
|
| ACPI: Writing ACPI tables at bffb6000.
|
| ACPI: * FACS
|
| ACPI: * DSDT
|
| ACPI: * IGD OpRegion
|
| GET_VBIOS: aa55 8086 0 3 0
|
| VBIOS not found.
|
| ACPI: * FADT
|
| ACPI: added table 1/32, length now 40
|
| ACPI: * SSDT
|
| Found 1 CPU(s) with 4 core(s) each.
|
| PSS: 2701MHz power 35000 control 0x2200 status 0x2200
|
| PSS: 2700MHz power 35000 control 0x1b00 status 0x1b00
|
| PSS: 2000MHz power 23853 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 18192 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12991 control 0xc00 status 0xc00
|
| PSS: 800MHz power 8236 control 0x800 status 0x800
|
| PSS: 2701MHz power 35000 control 0x2200 status 0x2200
|
| PSS: 2700MHz power 35000 control 0x1b00 status 0x1b00
|
| PSS: 2000MHz power 23853 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 18192 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12991 control 0xc00 status 0xc00
|
| PSS: 800MHz power 8236 control 0x800 status 0x800
|
| PSS: 2701MHz power 35000 control 0x2200 status 0x2200
|
| PSS: 2700MHz power 35000 control 0x1b00 status 0x1b00
|
| PSS: 2000MHz power 23853 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 18192 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12991 control 0xc00 status 0xc00
|
| PSS: 800MHz power 8236 control 0x800 status 0x800
|
| PSS: 2701MHz power 35000 control 0x2200 status 0x2200
|
| PSS: 2700MHz power 35000 control 0x1b00 status 0x1b00
|
| PSS: 2000MHz power 23853 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 18192 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12991 control 0xc00 status 0xc00
|
| PSS: 800MHz power 8236 control 0x800 status 0x800
|
| ACPI: added table 2/32, length now 44
|
| ACPI: * MCFG
|
| ACPI: added table 3/32, length now 48
|
| ACPI: * MADT
|
| ACPI: added table 4/32, length now 52
|
| current = bffbacc0
|
| ACPI: * HPET
|
| ACPI: added table 5/32, length now 56
|
| ACPI: done.
|
| ACPI tables: 19712 bytes.
|
| smbios_write_tables: bffb2000
|
| recv_ec_data: 0x38
|
| recv_ec_data: 0x41
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x34
|
| recv_ec_data: 0x32
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x14
|
| recv_ec_data: 0x03
|
| Root Device (LENOVO 4242W1A)
|
| CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| APIC: 00 (Socket rPGA988B CPU)
|
| APIC: acac (Intel SandyBridge/IvyBridge CPU)
|
| DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:01.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
|
| PNP: 00ff.2 (Lenovo H8 EC)
|
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| I2C: 01:54 (AT24RF08C)
|
| I2C: 01:55 (AT24RF08C)
|
| I2C: 01:56 (AT24RF08C)
|
| I2C: 01:57 (AT24RF08C)
|
| I2C: 01:5c (AT24RF08C)
|
| I2C: 01:5d (AT24RF08C)
|
| I2C: 01:5e (AT24RF08C)
|
| I2C: 01:5f (AT24RF08C)
|
| PCI: 00:1f.6 (unknown)
|
| PCI: 01:00.0 (unknown)
|
| PCI: 03:00.0 (unknown)
|
| PCI: 03:00.1 (unknown)
|
| PCI: 03:00.2 (unknown)
|
| PCI: 03:00.3 (unknown)
|
| APIC: 01 (unknown)
|
| APIC: 02 (unknown)
|
| APIC: 03 (unknown)
|
| SMBIOS tables: 419 bytes.
|
| Writing table forward entry at 0x00000500
|
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9ff3
|
| Table forward entry ends at 0x00000528.
|
| ... aligned to 0x00001000
|
| Writing coreboot table at 0xbfeaa000
|
| rom_table_end = 0xbfeaa000
|
| ... aligned to 0xbfeb0000
|
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
| 1. 0000000000001000-000000000009ffff: RAM
|
| 2. 00000000000a0000-00000000000fffff: RESERVED
|
| 3. 0000000000100000-000000001fffffff: RAM
|
| 4. 0000000020000000-00000000201fffff: RESERVED
|
| 5. 0000000020200000-000000003fffffff: RAM
|
| 6. 0000000040000000-00000000401fffff: RESERVED
|
| 7. 0000000040200000-00000000bfea9fff: RAM
|
| 8. 00000000bfeaa000-00000000bfffffff: CONFIGURATION TABLES
|
| 9. 00000000c0000000-00000000c29fffff: RESERVED
|
| 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
| 11. 0000000100000000-000000023b5fffff: RAM
|
| Wrote coreboot table at: bfeaa000, 0x998 bytes, checksum aa2e
|
| coreboot table: 2480 bytes.
|
| CBMEM ROOT 0. bffff000 00001000
|
| CAR GLOBALS 1. bfffe000 00001000
|
| CONSOLE 2. bffde000 00020000
|
| TIME STAMP 3. bffdd000 00001000
|
| MRC DATA 4. bffdc000 00001000
|
| ROMSTAGE 5. bffdb000 00001000
|
| GDT 6. bffda000 00001000
|
| ACPI 7. bffb6000 00024000
|
| ACPI GNVS 8. bffb5000 00001000
|
| 4f444749 9. bffb3000 00002000
|
| SMBIOS 10. bffb2000 00001000
|
| ACPI RESUME11. bfeb2000 00100000
|
| COREBOOT 12. bfeaa000 00008000
|
| BS: Exiting BS_WRITE_TABLES state.
|
| BS: BS_WRITE_TABLES times (us): entry 5094 run 22564 exit 0
|
| BS: Entering BS_PAYLOAD_LOAD state.
|
| CBFS: located payload @ fff385b8, 55339 bytes.
|
| Loading segment from rom address 0xfff385b8
|
| code (compression=1)
|
| New segment dstaddr 0xe6024 memsize 0x19fdc srcaddr 0xfff385f0 filesize 0xd7f3
|
| (cleaned up) New segment addr 0xe6024 size 0x19fdc offset 0xfff385f0 filesize 0xd7f3
|
| Loading segment from rom address 0xfff385d4
|
| Entry Point 0x000fd56b
|
| Payload being loaded below 1MiB without region being marked as RAM usable.
|
| Bounce Buffer at bfde9000, 786552 bytes
|
| Loading Segment: addr: 0x00000000000e6024 memsz: 0x0000000000019fdc filesz: 0x000000000000d7f3
|
| lb: [0x0000000000100000, 0x000000000016003c)
|
| Post relocation: addr: 0x00000000000e6024 memsz: 0x0000000000019fdc filesz: 0x000000000000d7f3
|
| using LZMA
|
| [ 0x000e6024, 00100000, 0x00100000) <- fff385f0
|
| dest 000e6024, end 00100000, bouncebuffer bfde9000
|
| Loaded segments
|
| BS: Exiting BS_PAYLOAD_LOAD state.
|
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 20677 exit 0
|
| BS: Entering BS_PAYLOAD_BOOT state.
|
| PCH watchdog disabled
|
| Jumping to boot code at 000fd56b
|
| CPU0: stack: 0015b000 - 0015c000, lowest used address 0015ba1c, stack used: 1508 bytes
|
| entry = 0x000fd56b
|
| lb_start = 0x00100000
|
| lb_size = 0x0006003c
|
| buffer = 0xbfde9000
|
| SeaBIOS (version rel-1.7.5-0-ge51488c-20141018_141510-haruhi) |
| Found coreboot cbmem console @ bffde000 |
| Found mainboard LENOVO 4242W1A |
| Relocating init from 0x000e71d9 to 0xbfe5f0c0 (size 44567) |
| Found CBFS header at 0xfffff4c8 |
| CPU Mhz=2694 |
| Found 19 PCI devices (max PCI bus is 03) |
| Copying SMBIOS entry point from 0xbffb2000 to 0x000f1fd0 |
| Copying ACPI RSDP from 0xbffb6000 to 0x000f1fa0 |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.7.5-0-ge51488c-20141018_141510-haruhi) |
| Machine UUID 81db30a9-ab51-cb11-8e4d-d03cefeb1403 |
| EHCI init on dev 00:1a.0 (regs=0xe0626820) |
| EHCI init on dev 00:1d.0 (regs=0xe0626c20) |
| Found 0 lpt ports |
| Found 0 serial ports |
| AHCI controller at 1f.2, iobase e0626000, irq 10 |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: registering: "AHCI/0: Samsung SSD 840 EVO 500GB ATA-9 Hard-Disk (465 GiBytes)" |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| PS2 keyboard initialized |
| All threads complete. |
| Scan for option roms |
| |
| Press F12 for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f1f30: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168 |
| Space available for UMB: c6800-ec800, f0000-f1f30 |
| Returned 253952 bytes of ZoneHigh |
| e820 map has 11 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 0000000020000000 = 1 RAM |
| 4: 0000000020000000 - 0000000020200000 = 2 RESERVED |
| 5: 0000000020200000 - 0000000040000000 = 1 RAM |
| 6: 0000000040000000 - 0000000040200000 = 2 RESERVED |
| 7: 0000000040200000 - 00000000bfea8000 = 1 RAM |
| 8: 00000000bfea8000 - 00000000c2a00000 = 2 RESERVED |
| 9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 10: 0000000100000000 - 000000023b600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |