|
|
|
|
| coreboot-4.0-6885-g396845a-dirty-alterapraxisptyltd Thu Sep 11 19:53:08 AEST 2014 starting...
|
| Setting up static southbridge registers... done.
|
| Disabling Watchdog reboot... done.
|
| Setting up static northbridge registers... done.
|
| Initializing Graphics...
|
| Back from sandybridge_early_initialization()
|
| SMBus controller enabled.
|
| CPU id(306a9): Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz
|
| AES supported, TXT supported, VT supported
|
| PCH type: QM77, device id: 1e55, rev id 4
|
| Intel ME early init
|
| Intel ME firmware is ready
|
| ME: Requested 32MB UMA
|
| Starting native Platform init
|
| Row addr bits : 16
|
| Column addr bits : 10
|
| Number of ranks : 2
|
| DIMM Capacity : 8192 MB
|
| CAS latencies : 5 6 7 8 9 10 11
|
| tCKmin : 1.250 ns
|
| tAAmin : 13.125 ns
|
| tWRmin : 15.000 ns
|
| tRCDmin : 13.125 ns
|
| tRRDmin : 6.000 ns
|
| tRPmin : 13.125 ns
|
| tRASmin : 35.000 ns
|
| tRCmin : 48.125 ns
|
| tRFCmin : 260.000 ns
|
| tWTRmin : 7.500 ns
|
| tRTPmin : 7.500 ns
|
| tFAWmin : 30.000 ns
|
| rankmap[0] = 0x3
|
| PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy...done
|
| MCU frequency is set at : 800 MHz
|
| Selected DRAM frequency: 800 MHz
|
| Minimum CAS latency : 11T
|
| Selected CAS latency : 11T
|
| Selected CWL latency : 8T
|
| Selected tRCD : 11T
|
| Selected tRP : 11T
|
| Selected tRAS : 28T
|
| Selected tWR : 12T
|
| Selected tFAW : 24T
|
| Selected tRRD : 5T
|
| Selected tRTP : 6T
|
| Selected tWTR : 6T
|
| Selected tRFC : 208T
|
| [c14] = 3000000
|
| [320c] = 4024000
|
| [d14] = 0
|
| [330c] = 4000
|
| [4000] = 1c8bbb
|
| [4004] = cc186465
|
| [400c] = a08b4
|
| [4298] = 6cd01860
|
| [42a4] = 41f88200
|
| [4400] = 1c8bbb
|
| [4404] = cc186465
|
| [440c] = a08b4
|
| [4698] = 6cd01860
|
| [46a4] = 41f88200
|
| Done dimm mapping
|
| PCI:[a0] = 0
|
| PCI:[a4] = 2
|
| PCI:[bc] = c2a00000
|
| PCI:[a8] = 3b600000
|
| PCI:[ac] = 2
|
| PCI:[b8] = c0000000
|
| PCI:[b0] = c0a00000
|
| PCI:[b4] = c0800000
|
| PCI:[7c] = 7f
|
| PCI:[70] = fe000000
|
| PCI:[74] = 1
|
| PCI:[78] = fe000c00
|
| Done memory map
|
| RCOMP...done
|
| COMP2 done
|
| COMP1 done
|
| FORCE RCOMP and wait 20us...done
|
| Done io registers
|
| Done jedec reset
|
| Done MRS commands
|
| High adjust 0:0000ffffffffffff
|
| High adjust 1:0000ffffffffffff
|
| High adjust 2:0000ffffffffffff
|
| High adjust 3:0000ffffffffffff
|
| High adjust 4:00000000ffffffff
|
| High adjust 5:0000fffffff |
| |
| *** Log truncated, 2759 characters dropped. *** |
| |
| Relocate MRC DATA from feffa7ac to bffed000 (1040 bytes)
|
| Trying CBFS ramstage loader.
|
| CBFS: loading stage fallback/ramstage @ 0x100000 (393276 bytes), entry @ 0x100000
|
| coreboot-4.0-6885-g396845a-dirty-alterapraxisptyltd Thu Sep 11 19:53:08 AEST 2014 booting...
|
| CBMEM: recovering 5/254 entries from root @ bffff000
|
| Moving GDT to bffeb000...ok
|
| BS: BS_PRE_DEVICE times (us): entry 19 run 0 exit 0
|
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 0
|
| Enumerating buses...
|
| Show all devs...Before device enumeration.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 0
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 0
|
| PNP: 00ff.2: enabled 0
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 00:54: enabled 1
|
| I2C: 00:55: enabled 1
|
| I2C: 00:56: enabled 1
|
| I2C: 00:57: enabled 1
|
| I2C: 00:5c: enabled 1
|
| I2C: 00:5d: enabled 1
|
| I2C: 00:5e: enabled 1
|
| I2C: 00:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 1
|
| Compare with tree...
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 0
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 0
|
| PNP: 00ff.2: enabled 0
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 00:54: enabled 1
|
| I2C: 00:55: enabled 1
|
| I2C: 00:56: enabled 1
|
| I2C: 00:57: enabled 1
|
| I2C: 00:5c: enabled 1
|
| I2C: 00:5d: enabled 1
|
| I2C: 00:5e: enabled 1
|
| I2C: 00:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 1
|
| scan_static_bus for Root Device
|
| CPU_CLUSTER: 0 enabled
|
| DOMAIN: 0000 enabled
|
| DOMAIN: 0000 scanning...
|
| PCI: pci_scan_bus for bus 00
|
| PCI: 00:00.0 [8086/0154] ops
|
| Normal boot.
|
| PCI: 00:00.0 [8086/0154] enabled
|
| PCI: 00:02.0 [8086/0000] ops
|
| PCI: 00:02.0 [8086/0166] enabled
|
| PCI: 00:14.0 [8086/0000] ops
|
| PCI: 00:14.0 [8086/1e31] enabled
|
| PCI: 00:16.0 [8086/1e3a] bus ops
|
| PCI: 00:16.0 [8086/1e3a] enabled
|
| PCI: 00:16.1: Disabling device
|
| PCI: 00:16.1 [8086/1e3b] disabled No operations
|
| PCI: 00:16.2: Disabling device
|
| PCI: 00:16.2 [8086/1e3c] disabled No operations
|
| PCI: 00:16.3: Disabling device
|
| PCI: 00:16.3 [8086/1e3d] disabled No operations
|
| PCI: 00:19.0 [8086/1502] enabled
|
| PCI: 00:1a.0 [8086/0000] ops
|
| PCI: 00:1a.0 [8086/1e2d] enabled
|
| PCI: 00:1b.0 [8086/0000] ops
|
| PCI: 00:1b.0 [8086/1e20] enabled
|
| PCH: PCIe Root Port coalescing is enabled
|
| PCI: 00:1c.0 [8086/0000] bus ops
|
| PCI: 00:1c.0 [8086/1e10] enabled
|
| PCI: 00:1c.1 [8086/0000] bus ops
|
| PCI: 00:1c.1 [8086/1e12] enabled
|
| PCI: 00:1c.2 [8086/0000] bus ops
|
| PCI: 00:1c.2 [8086/1e14] enabled
|
| PCI: 00:1c.3: Disabling device
|
| PCI: 00:1c.4: Disabling device
|
| PCI: 00:1c.4: check set enabled
|
| PCI: 00:1c.5: Disabling device
|
| PCI: 00:1c.6: Disabling device
|
| PCI: 00:1c.7: Disabling device
|
| PCH: RPFN 0x76543210 -> 0xfedcb210
|
| PCI: 00:1d.0 [8086/0000] ops
|
| PCI: 00:1d.0 [8086/1e26] enabled
|
| PCI: 00:1e.0: Disabling device
|
| PCI: 00:1f.0 [8086/0000] bus ops
|
| PCI: 00:1f.0 [8086/1e55] enabled
|
| PCI: 00:1f.2 [8086/0000] ops
|
| PCI: 00:1f.2 [8086/1e01] enabled
|
| PCI: 00:1f.3 [8086/0000] bus ops
|
| PCI: 00:1f.3 [8086/1e22] enabled
|
| PCI: 00:1f.5: Disabling device
|
| PCI: Static device PCI: 00:1f.6 not found, disabling it.
|
| scan_static_bus for PCI: 00:16.0
|
| scan_static_bus for PCI: 00:16.0 done
|
| do_pci_scan_bridge for PCI: 00:1c.0
|
| PCI: pci_scan_bus for bus 01
|
| PCI: 01:00.0 [1180/e823] enabled
|
| PCI: 01:00.1 [1180/e232] enabled
|
| PCI: 01:00.2 [1180/e852] enabled
|
| PCI: 01:00.3 [1180/e832] enabled
|
| PCI: pci_scan_bus returning with max=001
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| do_pci_scan_bridge returns max 1
|
| do_pci_scan_bridge for PCI: 00:1c.1
|
| PCI: pci_scan_bus for bus 02
|
| PCI: 02:00.0 [8086/4238] enabled
|
| PCI: pci_scan_bus returning with max=002
|
| Capability: type 0x01 @ 0xc8
|
| Capability: type 0x05 @ 0xd0
|
| Capability: type 0x10 @ 0xe0
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| do_pci_scan_bridge returns max 2
|
| do_pci_scan_bridge for PCI: 00:1c.2
|
| PCI: pci_scan_bus for bus 03
|
| PCI: pci_scan_bus returning with max=003
|
| do_pci_scan_bridge returns max 3
|
| scan_static_bus for PCI: 00:1f.0
|
| PNP: 00ff.1 disabled
|
| recv_ec_data: 0x47
|
| recv_ec_data: 0x34
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x33
|
| recv_ec_data: 0x38
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x16
|
| recv_ec_data: 0x03
|
| recv_ec_data: 0x20
|
| recv_ec_data: 0x11
|
| EC Firmware ID G4HT38WW-3.22, Version 2.01B
|
| recv_ec_data: 0x40
|
| recv_ec_data: 0x90
|
| recv_ec_data: 0x60
|
| recv_ec_data: 0x70
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0xa7
|
| recv_ec_data: 0xc2
|
| recv_ec_data: 0x70
|
| PNP: 00ff.2 disabled
|
| scan_static_bus for PCI: 00:1f.0 done
|
| scan_static_bus for PCI: 00:1f.3
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
|
| scan_static_bus for PCI: 00:1f.3 done
|
| PCI: pci_scan_bus returning with max=003
|
| scan_static_bus for Root Device done
|
| done
|
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 7976 exit 0
|
| found VGA at PCI: 00:02.0
|
| Setting up VGA for PCI: 00:02.0
|
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
| Allocating resources...
|
| Reading resources...
|
| Root Device read_resources bus 0 link: 0
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
| APIC: 00 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0
|
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
| PCI: 00:1c.0 read_resources bus 1 link: 0
|
| PCI: 00:1c.0 read_resources bus 1 link: 0 done
|
| PCI: 00:1c.1 read_resources bus 2 link: 0
|
| PCI: 00:1c.1 read_resources bus 2 link: 0 done
|
| PCI: 00:1c.2 read_resources bus 3 link: 0
|
| PCI: 00:1c.2 read_resources bus 3 link: 0 done
|
| PCI: 00:1f.0 read_resources bus 0 link: 0
|
| PCI: 00:1f.0 read_resources bus 0 link: 0 done
|
| PCI: 00:1f.3 read_resources bus 1 link: 0
|
| PCI: 00:1f.3 read_resources bus 1 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0 done
|
| Root Device read_resources bus 0 link: 0 done
|
| Done reading resources.
|
| Show resources in subtree (Root Device)...After reading.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
|
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
|
| PCI: 00:14.0
|
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
|
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0
|
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 01:00.1
|
| PCI: 01:00.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 01:00.2
|
| PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 01:00.3
|
| PCI: 01:00.3 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10
|
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0
|
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 02:00.0
|
| PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.3
|
| PCI: 00:1c.4
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
|
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.5
|
| PCI: 00:1f.6
|
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:02.0 20 * [0x0 - 0x3f] io
|
| PCI: 00:19.0 18 * [0x40 - 0x5f] io
|
| PCI: 00:1f.2 20 * [0x60 - 0x7f] io
|
| PCI: 00:1f.2 10 * [0x80 - 0x87] io
|
| PCI: 00:1f.2 18 * [0x88 - 0x8f] io
|
| PCI: 00:1f.2 14 * [0x90 - 0x93] io
|
| PCI: 00:1f.2 1c * [0x94 - 0x97] io
|
| DOMAIN: 0000 compute_resources_io: base: 98 size: 98 align: 6 gran: 0 limit: ffff done
|
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 01:00.3 10 * [0x0 - 0x7ff] mem
|
| PCI: 01:00.0 10 * [0x800 - 0x8ff] mem
|
| PCI: 01:00.1 10 * [0x900 - 0x9ff] mem
|
| PCI: 01:00.2 10 * [0xa00 - 0xaff] mem
|
| PCI: 00:1c.0 compute_resources_mem: base: b00 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 02:00.0 10 * [0x0 - 0x1fff] mem
|
| PCI: 00:1c.1 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
|
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
|
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem
|
| PCI: 00:1c.1 20 * [0x10500000 - 0x105fffff] mem
|
| PCI: 00:19.0 10 * [0x10600000 - 0x1061ffff] mem
|
| PCI: 00:14.0 10 * [0x10620000 - 0x1062ffff] mem
|
| PCI: 00:1b.0 10 * [0x10630000 - 0x10633fff] mem
|
| PCI: 00:19.0 14 * [0x10634000 - 0x10634fff] mem
|
| PCI: 00:1f.2 24 * [0x10635000 - 0x106357ff] mem
|
| PCI: 00:1a.0 10 * [0x10635800 - 0x10635bff] mem
|
| PCI: 00:1d.0 10 * [0x10635c00 - 0x10635fff] mem
|
| PCI: 00:1f.3 10 * [0x10636000 - 0x106360ff] mem
|
| PCI: 00:16.0 10 * [0x10636100 - 0x1063610f] mem
|
| DOMAIN: 0000 compute_resources_mem: base: 10636110 size: 10636110 align: 28 gran: 0 limit: ffffffff done
|
| avoid_fixed_resources: DOMAIN: 0000
|
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
| constrain_resources: DOMAIN: 0000
|
| constrain_resources: PCI: 00:00.0
|
| constrain_resources: PCI: 00:02.0
|
| constrain_resources: PCI: 00:14.0
|
| constrain_resources: PCI: 00:16.0
|
| constrain_resources: PCI: 00:19.0
|
| constrain_resources: PCI: 00:1a.0
|
| constrain_resources: PCI: 00:1b.0
|
| constrain_resources: PCI: 00:1c.0
|
| constrain_resources: PCI: 01:00.0
|
| constrain_resources: PCI: 01:00.1
|
| constrain_resources: PCI: 01:00.2
|
| constrain_resources: PCI: 01:00.3
|
| constrain_resources: PCI: 00:1c.1
|
| constrain_resources: PCI: 02:00.0
|
| constrain_resources: PCI: 00:1c.2
|
| constrain_resources: PCI: 00:1d.0
|
| constrain_resources: PCI: 00:1f.0
|
| constrain_resources: PCI: 00:1f.2
|
| constrain_resources: PCI: 00:1f.3
|
| constrain_resources: I2C: 01:54
|
| constrain_resources: I2C: 01:55
|
| constrain_resources: I2C: 01:56
|
| constrain_resources: I2C: 01:57
|
| constrain_resources: I2C: 01:5c
|
| constrain_resources: I2C: 01:5d
|
| constrain_resources: I2C: 01:5e
|
| constrain_resources: I2C: 01:5f
|
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
|
| lim->base 0000167c lim->limit 0000ffff
|
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
|
| lim->base 00000000 lim->limit efffffff
|
| Setting resources...
|
| DOMAIN: 0000 allocate_resources_io: base:167c size:98 align:6 gran:0 limit:ffff
|
| Assigned: PCI: 00:02.0 20 * [0x1800 - 0x183f] io
|
| Assigned: PCI: 00:19.0 18 * [0x1840 - 0x185f] io
|
| Assigned: PCI: 00:1f.2 20 * [0x1860 - 0x187f] io
|
| Assigned: PCI: 00:1f.2 10 * [0x1880 - 0x1887] io
|
| Assigned: PCI: 00:1f.2 18 * [0x1888 - 0x188f] io
|
| Assigned: PCI: 00:1f.2 14 * [0x1890 - 0x1893] io
|
| Assigned: PCI: 00:1f.2 1c * [0x1894 - 0x1897] io
|
| DOMAIN: 0000 allocate_resources_io: next_base: 1898 size: 98 align: 6 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10636110 align:28 gran:0 limit:efffffff
|
| Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
|
| Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
|
| Assigned: PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem
|
| Assigned: PCI: 00:1c.1 20 * [0xe0500000 - 0xe05fffff] mem
|
| Assigned: PCI: 00:19.0 10 * [0xe0600000 - 0xe061ffff] mem
|
| Assigned: PCI: 00:14.0 10 * [0xe0620000 - 0xe062ffff] mem
|
| Assigned: PCI: 00:1b.0 10 * [0xe0630000 - 0xe0633fff] mem
|
| Assigned: PCI: 00:19.0 14 * [0xe0634000 - 0xe0634fff] mem
|
| Assigned: PCI: 00:1f.2 24 * [0xe0635000 - 0xe06357ff] mem
|
| Assigned: PCI: 00:1a.0 10 * [0xe0635800 - 0xe0635bff] mem
|
| Assigned: PCI: 00:1d.0 10 * [0xe0635c00 - 0xe0635fff] mem
|
| Assigned: PCI: 00:1f.3 10 * [0xe0636000 - 0xe06360ff] mem
|
| Assigned: PCI: 00:16.0 10 * [0xe0636100 - 0xe063610f] mem
|
| DOMAIN: 0000 allocate_resources_mem: next_base: e0636110 size: 10636110 align: 28 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 01:00.3 10 * [0xe0400000 - 0xe04007ff] mem
|
| Assigned: PCI: 01:00.0 10 * [0xe0400800 - 0xe04008ff] mem
|
| Assigned: PCI: 01:00.1 10 * [0xe0400900 - 0xe04009ff] mem
|
| Assigned: PCI: 01:00.2 10 * [0xe0400a00 - 0xe0400aff] mem
|
| PCI: 00:1c.0 allocate_resources_mem: next_base: e0400b00 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_mem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 02:00.0 10 * [0xe0500000 - 0xe0501fff] mem
|
| PCI: 00:1c.1 allocate_resources_mem: next_base: e0502000 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| Root Device assign_resources, bus 0 link: 0
|
| TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000
|
| MEBASE 0x1fe000000
|
| IGD decoded, subtracting 32M UMA and 2M GTT
|
| TSEG base 0xc0000000 size 8M
|
| Available memory below 4GB: 3072M
|
| Available memory above 4GB: 5046M
|
| Adding PCIe config bar base=0xf0000000 size=0x4000000
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
|
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
|
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
|
| PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io
|
| PCI: 00:14.0 10 <- [0x00e0620000 - 0x00e062ffff] size 0x00010000 gran 0x10 mem64
|
| PCI: 00:16.0 10 <- [0x00e0636100 - 0x00e063610f] size 0x00000010 gran 0x04 mem64
|
| PCI: 00:19.0 10 <- [0x00e0600000 - 0x00e061ffff] size 0x00020000 gran 0x11 mem
|
| PCI: 00:19.0 14 <- [0x00e0634000 - 0x00e0634fff] size 0x00001000 gran 0x0c mem
|
| PCI: 00:19.0 18 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1a.0 10 <- [0x00e0635800 - 0x00e0635bff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1b.0 10 <- [0x00e0630000 - 0x00e0633fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
| PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
|
| PCI: 00:1c.0 assign_resources, bus 1 link: 0
|
| PCI: 01:00.0 10 <- [0x00e0400800 - 0x00e04008ff] size 0x00000100 gran 0x08 mem
|
| PCI: 01:00.1 10 <- [0x00e0400900 - 0x00e04009ff] size 0x00000100 gran 0x08 mem
|
| PCI: 01:00.2 10 <- [0x00e0400a00 - 0x00e0400aff] size 0x00000100 gran 0x08 mem
|
| PCI: 01:00.3 10 <- [0x00e0400000 - 0x00e04007ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1c.0 assign_resources, bus 1 link: 0
|
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
| PCI: 00:1c.1 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 02 mem
|
| PCI: 00:1c.1 assign_resources, bus 2 link: 0
|
| PCI: 02:00.0 10 <- [0x00e0500000 - 0x00e0501fff] size 0x00002000 gran 0x0d mem64
|
| PCI: 00:1c.1 assign_resources, bus 2 link: 0
|
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
|
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
| PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
|
| PCI: 00:1d.0 10 <- [0x00e0635c00 - 0x00e0635fff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PCI: 00:1f.2 10 <- [0x0000001880 - 0x0000001887] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 14 <- [0x0000001890 - 0x0000001893] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 18 <- [0x0000001888 - 0x000000188f] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 1c <- [0x0000001894 - 0x0000001897] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 20 <- [0x0000001860 - 0x000000187f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1f.2 24 <- [0x00e0635000 - 0x00e06357ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1f.3 10 <- [0x00e0636000 - 0x00e06360ff] size 0x00000100 gran 0x08 mem64
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| Root Device assign_resources, bus 0 link: 0
|
| Done setting resources.
|
| Show resources in subtree (Root Device)...After assigning values.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 167c size 98 align 6 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base d0000000 size 10636110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
|
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
|
| DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
|
| DOMAIN: 0000 resource base 100000000 size 13b600000 align 0 gran 0 limit 0 flags e0004200 index 5
|
| DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
|
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
|
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
|
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
|
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10
|
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
|
| PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
|
| PCI: 00:14.0
|
| PCI: 00:14.0 resource base e0620000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base e0636100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base e0600000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10
|
| PCI: 00:19.0 resource base e0634000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14
|
| PCI: 00:19.0 resource base 1840 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base e0635800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base e0630000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0
|
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base e0400800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 01:00.1
|
| PCI: 01:00.1 resource base e0400900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 01:00.2
|
| PCI: 01:00.2 resource base e0400a00 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 01:00.3
|
| PCI: 01:00.3 resource base e0400000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10
|
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0
|
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.1 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 02:00.0
|
| PCI: 02:00.0 resource base e0500000 size 2000 align 13 gran 13 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 00:1c.3
|
| PCI: 00:1c.4
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base e0635c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 1880 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
|
| PCI: 00:1f.2 resource base 1890 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
|
| PCI: 00:1f.2 resource base 1888 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
|
| PCI: 00:1f.2 resource base 1894 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
|
| PCI: 00:1f.2 resource base 1860 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
|
| PCI: 00:1f.2 resource base e0635000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base e0636000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.5
|
| PCI: 00:1f.6
|
| Done allocating resources.
|
| BS: BS_DEV_RESOURCES times (us): entry 0 run 11940 exit 0
|
| Enabling resources...
|
| PCI: 00:00.0 subsystem <- 0000/0000
|
| PCI: 00:00.0 cmd <- 06
|
| PCI: 00:02.0 subsystem <- 0000/0000
|
| PCI: 00:02.0 cmd <- 03
|
| PCI: 00:14.0 subsystem <- 0000/0000
|
| PCI: 00:14.0 cmd <- 102
|
| PCI: 00:16.0 subsystem <- 0000/0000
|
| PCI: 00:16.0 cmd <- 02
|
| PCI: 00:19.0 subsystem <- 0000/0000
|
| PCI: 00:19.0 cmd <- 103
|
| PCI: 00:1a.0 subsystem <- 0000/0000
|
| PCI: 00:1a.0 cmd <- 102
|
| PCI: 00:1b.0 subsystem <- 0000/0000
|
| PCI: 00:1b.0 cmd <- 102
|
| PCI: 00:1c.0 bridge ctrl <- 0003
|
| PCI: 00:1c.0 subsystem <- 0000/0000
|
| PCI: 00:1c.0 cmd <- 106
|
| PCI: 00:1c.1 bridge ctrl <- 0003
|
| PCI: 00:1c.1 subsystem <- 0000/0000
|
| PCI: 00:1c.1 cmd <- 106
|
| PCI: 00:1c.2 bridge ctrl <- 0003
|
| PCI: 00:1c.2 subsystem <- 0000/0000
|
| PCI: 00:1c.2 cmd <- 100
|
| PCI: 00:1d.0 subsystem <- 0000/0000
|
| PCI: 00:1d.0 cmd <- 102
|
| pch_decode_init
|
| PCI: 00:1f.0 subsystem <- 0000/0000
|
| PCI: 00:1f.0 cmd <- 107
|
| PCI: 00:1f.2 subsystem <- 0000/0000
|
| PCI: 00:1f.2 cmd <- 03
|
| PCI: 00:1f.3 subsystem <- 0000/0000
|
| PCI: 00:1f.3 cmd <- 103
|
| PCI: 01:00.0 cmd <- 06
|
| PCI: 01:00.1 cmd <- 06
|
| PCI: 01:00.2 cmd <- 06
|
| PCI: 01:00.3 cmd <- 02
|
| PCI: 02:00.0 cmd <- 02
|
| done.
|
| BS: BS_DEV_ENABLE times (us): entry 0 run 628 exit 0
|
| Initializing devices...
|
| Root Device init
|
| Root Device init 11 usecs
|
| CPU_CLUSTER: 0 init
|
| start_eip=0x00001000, code_size=0x00000031
|
| Installing SMM handler to 0xc0000000
|
| Installing IED header to 0xc0400000
|
| Initializing SMM handler... ... pmbase = 0x0500
|
|
|
| SMI_STS: INTEL_USB2 MCSMI PM1
|
| PM1_STS: WAK PWRBTN
|
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW
|
| ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI5 GPI4 GPI3 GPI1 GPI0
|
| TCO_STS:
|
| ... raise SMI#
|
| Initializing CPU #0
|
| CPU: vendor Intel device 306a9
|
| CPU: family 06, model 3a, stepping 09
|
| Enabling cache
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| MTRR: Physical address space:
|
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
|
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
|
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
|
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
|
| 0x0000000100000000 - 0x000000023b600000 size 0x13b600000 type 6
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: default type WB/UC MTRR counts: 3/10.
|
| MTRR: WB selected as default type.
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x00 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2600
|
| Turbo is available but hidden
|
| Turbo has been enabled
|
| CPU: 0 has 4 cores, 2 threads per core
|
| CPU: 0 has core 1
|
| CPU1: stack_base 0015a000, stack_end 0015aff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 1.
|
| After apic_write.
|
| Initializing CPU #1
|
| Startup point 1.
|
| CPU: vendor Intel device 306a9
|
| Waiting for send to finish...
|
| CPU: family 06, model 3a, stepping 09
|
| +Enabling cache
|
| Sending STARTUP #2 to 1.
|
| After apic_write.
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| CPU: 0 has core 2
|
| CPU2: stack_base 00159000, stack_end 00159ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| Deasserting INIT.
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Waiting for send to finish...
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| +MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| #startup loops: 2.
|
| call enable_fixed_mtrr()
|
| Sending STARTUP #1 to 2.
|
| After apic_write.
|
| Initializing CPU #2
|
| CPU: vendor Intel device 306a9
|
| CPU: family 06, model 3a, stepping 09
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| Enabling cache
|
| Startup point 1.
|
| microcode: sig=0x306a9 pf=0x10 revision=0x0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| Waiting for send to finish...
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| microcode: updated to revision 0x17 date=2013-01-09
|
|
|
| MTRR check
|
| +Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x01 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2600
|
| CPU #1 initialized
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| Sending STARTUP #2 to 2.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| CPU: 0 has core 3
|
| CPU3: stack_base 00158000, stack_end 00158ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 3.
|
| After apic_write.
|
| call enable_fixed_mtrr()
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Initializing CPU #3
|
| Sending STARTUP #2 to 3.
|
| After apic_write.
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 306a9
|
| After Startup.
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| CPU: 0 has core 4
|
| CPU4: stack_base 00157000, stack_end 00157ff8
|
| CPU: family 06, model 3a, stepping 09
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| Enabling cache
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x02 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2600
|
| CPU #2 initialized
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 4.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Initializing CPU #4
|
| Sending STARTUP #2 to 4.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 306a9
|
| After Startup.
|
| CPU: 0 has core 5
|
| CPU5: stack_base 00156000, stack_end 00156ff8
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +CPU: family 06, model 3a, stepping 09
|
| call enable_fixed_mtrr()
|
| Enabling cache
|
| microcode: sig=0x306a9 pf=0x10 revision=0x0
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| microcode: updated to revision 0x17 date=2013-01-09
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x03 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2600
|
| CPU #3 initialized
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x258 0x0606060606060606
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 5.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Initializing CPU #5
|
| Sending STARTUP #2 to 5.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 306a9
|
| After Startup.
|
| CPU: 0 has core 6
|
| CPU6: stack_base 00155000, stack_end 00155ff8
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +CPU: family 06, model 3a, stepping 09
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| Enabling cache
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x250 0x0606060606060606
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 6.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Initializing CPU #6
|
| Sending STARTUP #2 to 6.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 306a9
|
| After Startup.
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| CPU: 0 has core 7
|
| CPU7: stack_base 00154000, stack_end 00154ff8
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +CPU: family 06, model 3a, stepping 09
|
| call enable_fixed_mtrr()
|
| Enabling cache
|
| microcode: sig=0x306a9 pf=0x10 revision=0x0
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| microcode: updated to revision 0x17 date=2013-01-09
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 7.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x250 0x0606060606060606
|
| Sending STARTUP #2 to 7.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x258 0x0606060606060606
|
| After Startup.
|
| CPU #0 initialized
|
| Waiting for 4 CPUS to stop
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| Initializing CPU #7
|
|
|
| MTRR check
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Fixed MTRRs : CPU: vendor Intel device 306a9
|
| Enabled
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| Variable MTRRs: call enable_fixed_mtrr()
|
| Enabled
|
|
|
| Setting up local apic...CPU: family 06, model 3a, stepping 09
|
| apic_id: 0x04 MTRR: Fixed MSR 0x269 0x0606060606060606
|
| Enabling cache
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| done.
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| Enabling VMX
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic...MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| apic_id: 0x05 done.
|
| model_x06ax: energy policy set to 6
|
| Enabling VMX
|
| CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz.
|
| model_x06ax: frequency set to 2600
|
| model_x06ax: energy policy set to 6
|
| CPU #4 initialized
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| model_x06ax: frequency set to 2600
|
| Waiting for 3 CPUS to stop
|
| CPU #5 initialized
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| Waiting for 2 CPUS to stop
|
| call enable_fixed_mtrr()
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
|
| MTRR check
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| Fixed MTRRs : MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| Enabled
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| Variable MTRRs: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Enabled
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| Setting up local apic...call enable_fixed_mtrr()
|
| apic_id: 0x06 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| model_x06ax: frequency set to 2600
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| CPU #6 initialized
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| Waiting for 1 CPUS to stop
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x07 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2600
|
| CPU #7 initialized
|
| All AP CPUs stopped (6526 loops)
|
| CPU1: stack: 0015a000 - 0015b000, lowest used address 0015ac50, stack used: 944 bytes
|
| CPU2: stack: 00159000 - 0015a000, lowest used address 00159c50, stack used: 944 bytes
|
| CPU3: stack: 00158000 - 00159000, lowest used address 00158c50, stack used: 944 bytes
|
| CPU4: stack: 00157000 - 00158000, lowest used address 00157c50, stack used: 944 bytes
|
| CPU5: stack: 00156000 - 00157000, lowest used address 00156c50, stack used: 944 bytes
|
| CPU6: stack: 00155000 - 00156000, lowest used address 00155c50, stack used: 944 bytes
|
| CPU7: stack: 00154000 - 00155000, lowest used address 00154c50, stack used: 944 bytes
|
| CPU_CLUSTER: 0 init 228651 usecs
|
| PCI: 00:00.0 init
|
| Set BIOS_RESET_CPL
|
| CPU TDP: 45 Watts
|
| PCI: 00:00.0 init 1008 usecs
|
| PCI: 00:02.0 init
|
| GT Power Management Init
|
| IVB GT2 35W Power Meter Weights
|
| GT Power Management Init (post VBIOS)
|
| Initializing VGA without OPROM.
|
| EDID:
|
| 00 ff ff ff ff ff ff 00 30 ae b2 40 00 00 00 00
|
| 01 13 01 03 80 22 13 78 ea 21 35 ad 50 37 aa 24
|
| 11 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
|
| 01 01 01 01 01 01 4c 36 80 82 70 38 32 40 3c 30
|
| aa 00 58 c1 10 00 00 18 3f 2d 80 82 70 38 32 40
|
| 3c 30 aa 00 58 c1 10 00 00 18 00 00 00 0f 00 d1
|
| 09 32 d1 09 28 1b 19 00 06 af 56 34 00 00 00 fe
|
| 00 42 31 35 36 48 57 30 31 20 56 34 20 0a 00 d6
|
| Extracted contents:
|
| header: 00 ff ff ff ff ff ff 00
|
| serial number: 30 ae b2 40 00 00 00 00 01 13
|
| version: 01 03
|
| basic params: 80 22 13 78 ea
|
| chroma info: 21 35 ad 50 37 aa 24 11 50 54
|
| established: 00 00 00
|
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
| descriptor 1: 4c 36 80 82 70 38 32 40 3c 30 aa 00 58 c1 10 00 00 18
|
| descriptor 2: 3f 2d 80 82 70 38 32 40 3c 30 aa 00 58 c1 10 00 00 18
|
| descriptor 3: 00 00 00 0f 00 d1 09 32 d1 09 28 1b 19 00 06 af 56 34
|
| descriptor 4: 00 00 00 fe 00 42 31 35 36 48 57 30 31 20 56 34 20 0a
|
| extensions: 00
|
| checksum: d6
|
|
|
| Manufacturer: LEN Model 40b2 Serial Number 0
|
| Made week 1 of 2009
|
| EDID version: 1.3
|
| Digital display
|
| Maximum image size: 34 cm x 19 cm
|
| Gamma: 220%
|
| Check DPMS levels
|
| DPMS levels: Standby Suspend Off
|
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2
|
| First detailed timing is preferred timing
|
| Established timings supported:
|
| Standard timings supported:
|
| Detailed timings
|
| Hex of detail: 4c368082703832403c30aa0058c110000018
|
| Did detailed timing
|
| Detailed mode (IN HEX): Clock 139000 KHz, 158 mm x c1 mm
|
| 0780 07bc 07ec 0802 hborder 0
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| 0438 0442 044c 046a vborder 0
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| -hsync -vsync
|
| Hex of detail: 3f2d8082703832403c30aa0058c110000018
|
| Detailed mode (IN HEX): Clock 139000 KHz, 158 mm x c1 mm
|
| 0780 07bc 07ec 0802 hborder 0
|
| 0438 0442 044c 046a vborder 0
|
| -hsync -vsync
|
| Hex of detail: 0000000f00d10932d109281b190006af5634
|
| Manufacturer-specified data, tag 15
|
| Hex of detail: 000000fe004231353648573031205634200a
|
| ASCII string: B156HW01
|
| Checksum
|
| Checksum: 0xd6 (valid)
|
|
|
| Unknown extension block
|
|
|
| EDID block does NOT conform to EDID 1.3!
|
| Missing name descriptor
|
| Missing monitor ranges
|
| Detailed block string not properly terminated
|
| EDID block does not conform at all!
|
| Detailed blocks filled with garbage
|
| bringing up panel at resolution 1920 x 1080
|
| Borders 0 x 0
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| Blank 130 x 50
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| Sync 48 x 10
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| Front porch 60 x 10
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| Spread spectrum clock
|
| Dual channel
|
| Polarities 1, 1
|
| Data M1=9716804, N1=8388608
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| Link frequency 270000 kHz
|
| Link M1=269911, N1=524288
|
| Pixel N=10, M1=14, M2=11, P1=1
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| Pixel clock 138857 kHz
|
| waiting for panel powerup
|
| panel powered up
|
| PCI: 00:02.0 init 32806 usecs
|
| PCI: 00:14.0 init
|
| XHCI: Setting up controller.. done.
|
| PCI: 00:14.0 init 5 usecs
|
| PCI: 00:16.0 init
|
| ME: FW Partition Table : OK
|
| ME: Bringup Loader Failure : NO
|
| ME: Firmware Init Complete : NO
|
| ME: Manufacturing Mode : NO
|
| ME: Boot Options Present : NO
|
| ME: Update In Progress : NO
|
| ME: Current Working State : Normal
|
| ME: Current Operation State : M0 with UMA
|
| ME: Current Operation Mode : Normal
|
| ME: Error Code : No Error
|
| ME: Progress Phase : Host Communication
|
| ME: Power Management Event : Clean Moff->Mx wake
|
| ME: Progress Phase State : Host communication established
|
| ME: BIOS path: Normal
|
| ME: Extend SHA-256: 72ac4092d50568edb998066d81033da5f626bf97fe7f9942d06247dbf59bf8db
|
| ME: MBP item header 00020103
|
| ME: MBP item header 00050102
|
| ME: MBP item header 00020501
|
| ME: MBP item header 00020201
|
| ME: MBP item header 02030101
|
| ME: MBP item header 02060301
|
| ME: MBP item header 02090401
|
| ME: mbp read OK after 1 cycles
|
| ME: found version 8.0.12.1498
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| ME Capability: Full Network manageability : enabled
|
| ME Capability: Regular Network manageability : disabled
|
| ME Capability: Manageability : enabled
|
| ME Capability: Small business technology : disabled
|
| ME Capability: Level III manageability : disabled
|
| ME Capability: IntelR Anti-Theft (AT) : enabled
|
| ME Capability: IntelR Capability Licensing Service (CLS) : enabled
|
| ME Capability: IntelR Power Sharing Technology (MPC) : enabled
|
| ME Capability: ICC Over Clocking : enabled
|
| ME Capability: Protected Audio Video Path (PAVP) : enabled
|
| ME Capability: IPV6 : enabled
|
| ME Capability: KVM Remote Control (KVM) : enabled
|
| ME Capability: Outbreak Containment Heuristic (OCH) : disabled
|
| ME Capability: Virtual LAN (VLAN) : enabled
|
| ME Capability: TLS : enabled
|
| ME Capability: Wireless LAN (WLAN) : enabled
|
| PCI: 00:16.0 init 59 usecs
|
| PCI: 00:19.0 init
|
| PCI: 00:19.0 init 1 usecs
|
| PCI: 00:1a.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1a.0 init 13 usecs
|
| PCI: 00:1b.0 init
|
| Azalia: base = e0630000
|
| Azalia: codec_mask = 09
|
| Azalia: Initializing codec #3
|
| Azalia: codec viddid: 80862806
|
| Azalia: verb_size: 16
|
| Azalia: verb loaded.
|
| Azalia: Initializing codec #0
|
| Azalia: codec viddid: 10ec0269
|
| Azalia: verb_size: 500
|
| Azalia: verb loaded.
|
| PCI: 00:1b.0 init 23599 usecs
|
| PCI: 00:1c.0 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.0 init 10 usecs
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| PCI: 00:1c.1 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.1 init 10 usecs
|
| PCI: 00:1c.2 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.2 init 10 usecs
|
| PCI: 00:1d.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1d.0 init 13 usecs
|
| PCI: 00:1f.0 init
|
| pch: lpc_init
|
| IOAPIC: Initializing IOAPIC at 0xfec00000
|
| IOAPIC: Bootstrap Processor Local APIC = 0x00
|
| IOAPIC: ID = 0x02
|
| IOAPIC: Dumping registers
|
| reg 0x0000: 0x02000000
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| reg 0x0001: 0x00170020
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| reg 0x0002: 0x00170020
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| Set power off after power failure.
|
| NMI sources disabled.
|
| PantherPoint PM init
|
| rtc_failed = 0x0
|
| RTC Init
|
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
|
| done.
|
| Locking SMM.
|
| PCI: 00:1f.0 init 346 usecs
|
| PCI: 00:1f.2 init
|
| SATA: Initializing...
|
| SATA: Controller in AHCI mode.
|
| ABAR: E0635000
|
| PCI: 00:1f.2 init 73 usecs
|
| PCI: 00:1f.3 init
|
| PCI: 00:1f.3 init 7 usecs
|
| PCI: 01:00.0 init
|
| PCI: 01:00.0 init 1 usecs
|
| PCI: 01:00.1 init
|
| PCI: 01:00.1 init 1 usecs
|
| PCI: 01:00.2 init
|
| PCI: 01:00.2 init 0 usecs
|
| PCI: 01:00.3 init
|
| PCI: 01:00.3 init 0 usecs
|
| PCI: 02:00.0 init
|
| PCI: 02:00.0 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
| I2C: 01:54 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
| I2C: 01:55 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
| I2C: 01:56 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
| I2C: 01:57 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
| Locking EEPROM RFID
|
| init EEPROM done
|
| I2C: 01:5c init 24413 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
| I2C: 01:5d init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
| I2C: 01:5e init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
| I2C: 01:5f init 1 usecs
|
| Devices initialized
|
| Show all devs...After init.
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| Root Device: enabled 1
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| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
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| APIC: acac: enabled 0
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| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 0
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 0
|
| PNP: 00ff.2: enabled 0
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 01:54: enabled 1
|
| I2C: 01:55: enabled 1
|
| I2C: 01:56: enabled 1
|
| I2C: 01:57: enabled 1
|
| I2C: 01:5c: enabled 1
|
| I2C: 01:5d: enabled 1
|
| I2C: 01:5e: enabled 1
|
| I2C: 01:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 0
|
| PCI: 01:00.0: enabled 1
|
| PCI: 01:00.1: enabled 1
|
| PCI: 01:00.2: enabled 1
|
| PCI: 01:00.3: enabled 1
|
| PCI: 02:00.0: enabled 1
|
| APIC: 01: enabled 1
|
| APIC: 02: enabled 1
|
| APIC: 03: enabled 1
|
| APIC: 04: enabled 1
|
| APIC: 05: enabled 1
|
| APIC: 06: enabled 1
|
| APIC: 07: enabled 1
|
| BS: BS_DEV_INIT times (us): entry 0 run 311095 exit 0
|
| Finalize devices...
|
| Devices finalized
|
| BS: BS_POST_DEVICE times (us): entry 1 run 1 exit 0
|
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
|
| Updating MRC cache data.
|
| find_current_mrc_cache_local: picked entry 0 from cache block
|
| flash size 0xc00000 bytes
|
| SF: Detected Opaque HW-sequencing with page size 1000, total c00000
|
| find_next_mrc_cache: picked next entry from cache block at fffe1000
|
| Finally: write MRC cache update to flash at fffe1000
|
| SF: Successfully written 1056 bytes @ 0xbe1000
|
| ACPI: Writing ACPI tables at bffdf000.
|
| ACPI: * FACS
|
| ACPI: * DSDT
|
| ACPI: * FADT
|
| ACPI: added table 1/32, length now 40
|
| ACPI: * HPET
|
| ACPI: added table 2/32, length now 44
|
| ACPI: * MADT
|
| ACPI: added table 3/32, length now 48
|
| ACPI: * MCFG
|
| ACPI: added table 4/32, length now 52
|
| ACPI: Patching up global NVS in DSDT at offset 0x00a5 -> 0xbffe2a50
|
| ACPI: * DSDT @ bffdf250 Length 35e9
|
| ACPI: * SSDT
|
| Found 1 CPU(s) with 8 core(s) each.
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| PSS: 2601MHz power 45000 control 0x2400 status 0x2400
|
| PSS: 2600MHz power 45000 control 0x1a00 status 0x1a00
|
| PSS: 2400MHz power 40579 control 0x1800 status 0x1800
|
| PSS: 2200MHz power 36318 control 0x1600 status 0x1600
|
| PSS: 2000MHz power 32251 control 0x1400 status 0x1400
|
| PSS: 1800MHz power 28368 control 0x1200 status 0x1200
|
| PSS: 1600MHz power 24603 control 0x1000 status 0x1000
|
| PSS: 1400MHz power 21014 control 0xe00 status 0xe00
|
| PSS: 1200MHz power 17571 control 0xc00 status 0xc00
|
| ACPI: added table 5/32, length now 56
|
| current = bffe61c0
|
| ACPI: done.
|
| ACPI tables: 29120 bytes.
|
| smbios_write_tables: bffdd000
|
| recv_ec_data: 0x47
|
| recv_ec_data: 0x34
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x33
|
| recv_ec_data: 0x38
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x16
|
| recv_ec_data: 0x03
|
| Root Device (LENOVO 2359CTO)
|
| CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| APIC: 00 (Socket rPGA989 CPU)
|
| APIC: acac (Intel SandyBridge/IvyBridge CPU)
|
| DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:01.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
|
| PNP: 00ff.2 (Lenovo H8 EC)
|
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| I2C: 01:54 (AT24RF08C)
|
| I2C: 01:55 (AT24RF08C)
|
| I2C: 01:56 (AT24RF08C)
|
| I2C: 01:57 (AT24RF08C)
|
| I2C: 01:5c (AT24RF08C)
|
| I2C: 01:5d (AT24RF08C)
|
| I2C: 01:5e (AT24RF08C)
|
| I2C: 01:5f (AT24RF08C)
|
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 01:00.0 (unknown)
|
| PCI: 01:00.1 (unknown)
|
| PCI: 01:00.2 (unknown)
|
| PCI: 01:00.3 (unknown)
|
| PCI: 02:00.0 (unknown)
|
| APIC: 01 (unknown)
|
| APIC: 02 (unknown)
|
| APIC: 03 (unknown)
|
| APIC: 04 (unknown)
|
| APIC: 05 (unknown)
|
| APIC: 06 (unknown)
|
| APIC: 07 (unknown)
|
| SMBIOS tables: 420 bytes.
|
| Writing table forward entry at 0x00000500
|
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum eff0
|
| Table forward entry ends at 0x00000528.
|
| ... aligned to 0x00001000
|
| W |
| 4875 bytes lost |