| coreboot-4.0-5001-g7f68dfd Sat Dec 7 19:11:25 GMT 2013 starting... | |
| Setting up static southbridge registers... done. | |
| Disabling Watchdog reboot... done. | |
| Setting up static northbridge registers... done. | |
| Initializing Graphics... | |
| Back from sandybridge_early_initialization() | |
| SMBus controller enabled. | |
| CPU id(206a7): Intel(R) Celeron(R) CPU 847 @ 1.10GHz | |
| AES NOT supported, TXT NOT supported, VT supported | |
| PCH type: NM70, device id: 1e5f, rev id 4 | |
| Intel ME early init | |
| Intel ME firmware is ready | |
| ME: Requested 16MB UMA | |
| Starting UEFI PEI System Agent | |
| Read scrambler seed 0x00006173 from CMOS 0x98 | |
| Read S3 scrambler seed 0x00007213 from CMOS 0x9c | |
| find_current_mrc_cache_local: No valid MRC cache found. | |
| System Agent: Starting up... | |
| System Agent: Initializing PCH | |
| System Agent: Initializing PCH (SMBUS) | |
| System Agent: Initializing PCH (USB) | |
| System Agent: Initializing PCH (SA Init) | |
| SA PciExpress skipped (pcie_init is 0) | |
| System Agent: Initializing PCH (Me UMA) | |
| System Agent: Initializing Memory | |
| System Agent: Done. | |
| System Agent Version 1.2.2 Build 0 | |
| ME: Sending Init Done with status: 0, UMA base: 0x07f0 | |
| ME: Requested BIOS Action: Continue to boot | |
| ME: FW Partition Table : OK | |
| ME: Bringup Loader Failure : NO | |
| ME: Firmware Init Complete : NO | |
| ME: Manufacturing Mode : NO | |
| ME: Boot Options Present : NO | |
| ME: Update In Progress : NO | |
| ME: Current Working State : Normal | |
| ME: Current Operation State : Bring up | |
| ME: Current Operation Mode : Normal | |
| ME: Error Code : No Error | |
| ME: Progress Phase : BUP Phase | |
| ME: Power Management Event : Pseudo-global reset | |
| ME: Progress Phase State : 0x50 | |
| memcfg DDR3 clock 1333 MHz | |
| memcfg channel assignment: A: 1, B 0, C 2 | |
| memcfg channel[0] config (00600000): | |
| ECC inactive | |
| enhanced interleave mode on | |
| rank interleave on | |
| DIMMA 0 MB width x8 single rank, selected | |
| DIMMB 0 MB width x8 single rank | |
| memcfg channel[1] config (00600008): | |
| ECC inactive | |
| enhanced interleave mode on | |
| rank interleave on | |
| DIMMA 2048 MB width x8 single rank, selected | |
| DIMMB 0 MB width x8 single rank | |
| CBMEM region 7bec0000-7bffffff (cbmem_reinit) | |
| CBMEM region 7bec0000-7bffffff (cbmem_init) | |
| Adding CBMEM entry as no. 1 | |
| Adding CBMEM entry as no. 2 | |
| Adding CBMEM entry as no. 3 | |
| Relocate MRC DATA from ff7e3237 to 7bed0400 (2992 bytes) | |
| Save scrambler seed 0x0000b1e3 to CMOS 0x98 | |
| Save s3 scrambler seed 0x0000ef1a to CMOS 0x9c | |
| CBMEM region 7bec0000-7bffffff (cbmem_reinit) | |
| Loading image. | |
| CBFS: loading stage fallback/coreboot_ram @ 0x100000 (430144 bytes), entry @ 0x100000 | |
| Jumping to image. | |
| coreboot-4.0-5001-g7f68dfd Sat Dec 7 19:11:25 GMT 2013 booting... | |
| Enumerating buses... | |
| Show all devs...Before device enumeration. | |
| Root Device: enabled 1 | |
| CPU_CLUSTER: 0: enabled 1 | |
| APIC: 00: enabled 1 | |
| APIC: acac: enabled 0 | |
| DOMAIN: 0000: enabled 1 | |
| PCI: 00:00.0: enabled 1 | |
| PCI: 00:02.0: enabled 1 | |
| PCI: 00:16.0: enabled 1 | |
| PCI: 00:16.1: enabled 0 | |
| PCI: 00:16.2: enabled 0 | |
| PCI: 00:16.3: enabled 0 | |
| PCI: 00:19.0: enabled 0 | |
| PCI: 00:1a.0: enabled 1 | |
| PCI: 00:1b.0: enabled 1 | |
| PCI: 00:1c.0: enabled 0 | |
| PCI: 00:1c.1: enabled 1 | |
| PCI: 00:1c.2: enabled 1 | |
| PCI: 00:1c.3: enabled 0 | |
| PCI: 00:1c.4: enabled 0 | |
| PCI: 00:1c.5: enabled 0 | |
| PCI: 00:1c.6: enabled 0 | |
| PCI: 00:1c.7: enabled 0 | |
| PCI: 00:1d.0: enabled 1 | |
| PCI: 00:1e.0: enabled 0 | |
| PCI: 00:1f.0: enabled 1 | |
| PNP: 00ff.1: enabled 1 | |
| PCI: 00:1f.2: enabled 1 | |
| PCI: 00:1f.3: enabled 1 | |
| PCI: 00:1f.5: enabled 0 | |
| PCI: 00:1f.6: enabled 1 | |
| Compare with tree... | |
| Root Device: enabled 1 | |
| CPU_CLUSTER: 0: enabled 1 | |
| APIC: 00: enabled 1 | |
| APIC: acac: enabled 0 | |
| DOMAIN: 0000: enabled 1 | |
| PCI: 00:00.0: enabled 1 | |
| PCI: 00:02.0: enabled 1 | |
| PCI: 00:16.0: enabled 1 | |
| PCI: 00:16.1: enabled 0 | |
| PCI: 00:16.2: enabled 0 | |
| PCI: 00:16.3: enabled 0 | |
| PCI: 00:19.0: enabled 0 | |
| PCI: 00:1a.0: enabled 1 | |
| PCI: 00:1b.0: enabled 1 | |
| PCI: 00:1c.0: enabled 0 | |
| PCI: 00:1c.1: enabled 1 | |
| PCI: 00:1c.2: enabled 1 | |
| PCI: 00:1c.3: enabled 0 | |
| PCI: 00:1c.4: enabled 0 | |
| PCI: 00:1c.5: enabled 0 | |
| PCI: 00:1c.6: enabled 0 | |
| PCI: 00:1c.7: enabled 0 | |
| PCI: 00:1d.0: enabled 1 | |
| PCI: 00:1e.0: enabled 0 | |
| PCI: 00:1f.0: enabled 1 | |
| PNP: 00ff.1: enabled 1 | |
| PCI: 00:1f.2: enabled 1 | |
| PCI: 00:1f.3: enabled 1 | |
| PCI: 00:1f.5: enabled 0 | |
| PCI: 00:1f.6: enabled 1 | |
| scan_static_bus for Root Device | |
| CPU_CLUSTER: 0 enabled | |
| DOMAIN: 0000 enabled | |
| DOMAIN: 0000 scanning... | |
| PCI: pci_scan_bus for bus 00 | |
| PCI: 00:00.0 [8086/0104] ops | |
| Normal boot. | |
| PCI: 00:00.0 [8086/0104] enabled | |
| PCI: 00:02.0 [8086/0000] ops | |
| PCI: 00:02.0 [8086/0106] enabled | |
| PCI: 00:16.0 [8086/1e3a] bus ops | |
| PCI: 00:16.0 [8086/1e3a] enabled | |
| PCI: 00:16.1: Disabling device | |
| PCI: 00:16.1 [8086/1e3b] disabled No operations | |
| PCI: 00:16.2: Disabling device | |
| PCI: 00:16.3: Disabling device | |
| PCI: 00:19.0: Disabling device | |
| PCI: 00:1a.0 [8086/0000] ops | |
| PCI: 00:1a.0 [8086/1e2d] enabled | |
| PCI: 00:1b.0 [8086/0000] ops | |
| PCI: 00:1b.0 [8086/1e20] enabled | |
| PCH: PCIe Root Port coalescing is enabled | |
| PCI: 00:1c.0: Disabling device | |
| PCI: 00:1c.0: check set enabled | |
| PCH: Remap PCIe function 1 to 0 | |
| PCI: 00:1c.1 [8086/0000] bus ops | |
| PCI: 00:1c.1 [8086/1e12] enabled | |
| PCH: Remap PCIe function 2 to 0 | |
| PCI: 00:1c.2 [8086/0000] bus ops | |
| PCI: 00:1c.2 [8086/1e14] enabled | |
| PCI: 00:1c.3: Disabling device | |
| PCI: 00:1c.4: Disabling device | |
| PCI: 00:1c.4: check set enabled | |
| PCI: 00:1c.5: Disabling device | |
| PCI: 00:1c.6: Disabling device | |
| PCI: 00:1c.7: Disabling device | |
| PCH: RPFN 0x76543210 -> 0xfedcb10a | |
| PCH: PCIe map 1c.0 -> 1c.2 | |
| PCH: PCIe map 1c.1 -> 1c.0 | |
| PCH: PCIe map 1c.2 -> 1c.1 | |
| PCI: 00:1d.0 [8086/0000] ops | |
| PCI: 00:1d.0 [8086/1e26] enabled | |
| PCI: 00:1e.0: Disabling device | |
| PCI: 00:1f.0 [8086/0000] bus ops | |
| PCI: 00:1f.0 [8086/1e5f] enabled | |
| PCI: 00:1f.2 [8086/0000] ops | |
| PCI: 00:1f.2 [8086/1e01] enabled | |
| PCI: 00:1f.3 [8086/0000] bus ops | |
| PCI: 00:1f.3 [8086/1e22] enabled | |
| PCI: 00:1f.5: Disabling device | |
| PCI: 00:1f.6 [8086/1e24] enabled | |
| scan_static_bus for PCI: 00:16.0 | |
| scan_static_bus for PCI: 00:16.0 done | |
| do_pci_scan_bridge for PCI: 00:1c.0 | |
| PCI: pci_scan_bus for bus 01 | |
| PCI: 01:00.0 [168c/0034] enabled | |
| PCI: pci_scan_bus returning with max=001 | |
| Capability: type 0x01 @ 0x40 | |
| Capability: type 0x05 @ 0x50 | |
| Capability: type 0x10 @ 0x70 | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L0s and L1 | |
| do_pci_scan_bridge returns max 1 | |
| do_pci_scan_bridge for PCI: 00:1c.1 | |
| PCI: pci_scan_bus for bus 02 | |
| PCI: 02:00.0 [14e4/16b5] enabled | |
| PCI: 02:00.1 [14e4/16bc] enabled | |
| PCI: pci_scan_bus returning with max=002 | |
| Capability: type 0x01 @ 0x48 | |
| Capability: type 0x05 @ 0x58 | |
| Capability: type 0x11 @ 0xa0 | |
| Capability: type 0x10 @ 0xac | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L0s and L1 | |
| Capability: type 0x01 @ 0x48 | |
| Capability: type 0x05 @ 0x58 | |
| Capability: type 0x10 @ 0xac | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L0s and L1 | |
| do_pci_scan_bridge returns max 2 | |
| scan_static_bus for PCI: 00:1f.0 | |
| PNP: 00ff.1 enabled | |
| PNP: 00ff.0 enabled | |
| scan_static_bus for PCI: 00:1f.0 done | |
| scan_static_bus for PCI: 00:1f.3 | |
| scan_static_bus for PCI: 00:1f.3 done | |
| PCI: pci_scan_bus returning with max=002 | |
| scan_static_bus for Root Device done | |
| done | |
| found VGA at PCI: 00:02.0 | |
| Setting up VGA for PCI: 00:02.0 | |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 | |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device | |
| Allocating resources... | |
| Reading resources... | |
| Root Device read_resources bus 0 link: 0 | |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 | |
| APIC: 00 missing read_resources | |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done | |
| DOMAIN: 0000 read_resources bus 0 link: 0 | |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. | |
| PCI: 00:1c.0 read_resources bus 1 link: 0 | |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done | |
| PCI: 00:1c.1 read_resources bus 2 link: 0 | |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done | |
| PCI: 00:1f.0 read_resources bus 0 link: 0 | |
| PNP: 00ff.1 missing read_resources | |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done | |
| DOMAIN: 0000 read_resources bus 0 link: 0 done | |
| Root Device read_resources bus 0 link: 0 done | |
| Done reading resources. | |
| Show resources in subtree (Root Device)...After reading. | |
| Root Device child on link 0 CPU_CLUSTER: 0 | |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 | |
| APIC: 00 | |
| APIC: acac | |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 | |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 | |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 | |
| PCI: 00:00.0 | |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf | |
| PCI: 00:02.0 | |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 101201 index 18 | |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 | |
| PCI: 00:16.0 | |
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:16.1 | |
| PCI: 00:16.2 | |
| PCI: 00:16.3 | |
| PCI: 00:19.0 | |
| PCI: 00:1a.0 | |
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 | |
| PCI: 00:1b.0 | |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:1c.2 | |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 | |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c | |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 | |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 | |
| PCI: 01:00.0 | |
| PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 | |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 | |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c | |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 | |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 | |
| PCI: 02:00.0 | |
| PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 10 | |
| PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 18 | |
| PCI: 02:00.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 2200 index 30 | |
| PCI: 02:00.1 | |
| PCI: 02:00.1 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 10 | |
| PCI: 00:1c.3 | |
| PCI: 00:1c.4 | |
| PCI: 00:1c.5 | |
| PCI: 00:1c.6 | |
| PCI: 00:1c.7 | |
| PCI: 00:1d.0 | |
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 | |
| PCI: 00:1e.0 | |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 | |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 | |
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 | |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 | |
| PCI: 00:1f.0 resource base fd60 size 4 align 0 gran 0 limit 0 flags c0040100 index 10000200 | |
| PNP: 00ff.1 | |
| PNP: 00ff.0 | |
| PCI: 00:1f.2 | |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 | |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 | |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 | |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c | |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 | |
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 | |
| PCI: 00:1f.3 | |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 | |
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:1f.5 | |
| PCI: 00:1f.6 | |
| PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 | |
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff | |
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff | |
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done | |
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff | |
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done | |
| PCI: 00:02.0 20 * [0x0 - 0x3f] io | |
| PCI: 00:1f.2 20 * [0x40 - 0x5f] io | |
| PCI: 00:1f.2 10 * [0x60 - 0x67] io | |
| PCI: 00:1f.2 18 * [0x68 - 0x6f] io | |
| PCI: 00:1f.2 14 * [0x70 - 0x73] io | |
| PCI: 00:1f.2 1c * [0x74 - 0x77] io | |
| DOMAIN: 0000 compute_resources_io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done | |
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff | |
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff | |
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done | |
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff | |
| PCI: 01:00.0 10 * [0x0 - 0x7ffff] mem | |
| PCI: 01:00.0 30 * [0x80000 - 0x8ffff] mem | |
| PCI: 00:1c.0 compute_resources_mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done | |
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff | |
| PCI: 02:00.0 10 * [0x0 - 0xffff] prefmem | |
| PCI: 02:00.0 18 * [0x10000 - 0x1ffff] prefmem | |
| PCI: 02:00.1 10 * [0x20000 - 0x2ffff] prefmem | |
| PCI: 00:1c.1 compute_resources_prefmem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done | |
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff | |
| PCI: 02:00.0 30 * [0x0 - 0x7ff] mem | |
| PCI: 00:1c.1 compute_resources_mem: base: 800 size: 100000 align: 20 gran: 20 limit: ffffffff done | |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem | |
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem | |
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem | |
| PCI: 00:1c.1 24 * [0x10500000 - 0x105fffff] prefmem | |
| PCI: 00:1c.1 20 * [0x10600000 - 0x106fffff] mem | |
| PCI: 00:1b.0 10 * [0x10700000 - 0x10703fff] mem | |
| PCI: 00:1f.6 10 * [0x10704000 - 0x10704fff] mem | |
| PCI: 00:1f.2 24 * [0x10705000 - 0x107057ff] mem | |
| PCI: 00:1a.0 10 * [0x10705800 - 0x10705bff] mem | |
| PCI: 00:1d.0 10 * [0x10705c00 - 0x10705fff] mem | |
| PCI: 00:1f.3 10 * [0x10706000 - 0x107060ff] mem | |
| PCI: 00:16.0 10 * [0x10706100 - 0x1070610f] mem | |
| DOMAIN: 0000 compute_resources_mem: base: 10706110 size: 10706110 align: 28 gran: 0 limit: ffffffff done | |
| avoid_fixed_resources: DOMAIN: 0000 | |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff | |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff | |
| constrain_resources: DOMAIN: 0000 | |
| constrain_resources: PCI: 00:00.0 | |
| constrain_resources: PCI: 00:02.0 | |
| constrain_resources: PCI: 00:16.0 | |
| constrain_resources: PCI: 00:1a.0 | |
| constrain_resources: PCI: 00:1b.0 | |
| constrain_resources: PCI: 00:1c.0 | |
| constrain_resources: PCI: 01:00.0 | |
| constrain_resources: PCI: 00:1c.1 | |
| constrain_resources: PCI: 02:00.0 | |
| constrain_resources: PCI: 02:00.1 | |
| constrain_resources: PCI: 00:1d.0 | |
| constrain_resources: PCI: 00:1f.0 | |
| constrain_resources: PNP: 00ff.1 | |
| constrain_resources: PNP: 00ff.0 | |
| constrain_resources: PCI: 00:1f.2 | |
| constrain_resources: PCI: 00:1f.3 | |
| constrain_resources: PCI: 00:1f.6 | |
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff | |
| lim->base 00001000 lim->limit 0000fd5f | |
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff | |
| lim->base 00000000 lim->limit efffffff | |
| Setting resources... | |
| DOMAIN: 0000 allocate_resources_io: base:1000 size:78 align:6 gran:0 limit:fd5f | |
| Assigned: PCI: 00:02.0 20 * [0x1000 - 0x103f] io | |
| Assigned: PCI: 00:1f.2 20 * [0x1040 - 0x105f] io | |
| Assigned: PCI: 00:1f.2 10 * [0x1060 - 0x1067] io | |
| Assigned: PCI: 00:1f.2 18 * [0x1068 - 0x106f] io | |
| Assigned: PCI: 00:1f.2 14 * [0x1070 - 0x1073] io | |
| Assigned: PCI: 00:1f.2 1c * [0x1074 - 0x1077] io | |
| DOMAIN: 0000 allocate_resources_io: next_base: 1078 size: 78 align: 6 gran: 0 done | |
| PCI: 00:1c.0 allocate_resources_io: base:fd5f size:0 align:12 gran:12 limit:fd5f | |
| PCI: 00:1c.0 allocate_resources_io: next_base: fd5f size: 0 align: 12 gran: 12 done | |
| PCI: 00:1c.1 allocate_resources_io: base:fd5f size:0 align:12 gran:12 limit:fd5f | |
| PCI: 00:1c.1 allocate_resources_io: next_base: fd5f size: 0 align: 12 gran: 12 done | |
| DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10706110 align:28 gran:0 limit:efffffff | |
| Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem | |
| Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem | |
| Assigned: PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem | |
| Assigned: PCI: 00:1c.1 24 * [0xe0500000 - 0xe05fffff] prefmem | |
| Assigned: PCI: 00:1c.1 20 * [0xe0600000 - 0xe06fffff] mem | |
| Assigned: PCI: 00:1b.0 10 * [0xe0700000 - 0xe0703fff] mem | |
| Assigned: PCI: 00:1f.6 10 * [0xe0704000 - 0xe0704fff] mem | |
| Assigned: PCI: 00:1f.2 24 * [0xe0705000 - 0xe07057ff] mem | |
| Assigned: PCI: 00:1a.0 10 * [0xe0705800 - 0xe0705bff] mem | |
| Assigned: PCI: 00:1d.0 10 * [0xe0705c00 - 0xe0705fff] mem | |
| Assigned: PCI: 00:1f.3 10 * [0xe0706000 - 0xe07060ff] mem | |
| Assigned: PCI: 00:16.0 10 * [0xe0706100 - 0xe070610f] mem | |
| DOMAIN: 0000 allocate_resources_mem: next_base: e0706110 size: 10706110 align: 28 gran: 0 done | |
| PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff | |
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done | |
| PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff | |
| Assigned: PCI: 01:00.0 10 * [0xe0400000 - 0xe047ffff] mem | |
| Assigned: PCI: 01:00.0 30 * [0xe0480000 - 0xe048ffff] mem | |
| PCI: 00:1c.0 allocate_resources_mem: next_base: e0490000 size: 100000 align: 20 gran: 20 done | |
| PCI: 00:1c.1 allocate_resources_prefmem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff | |
| Assigned: PCI: 02:00.0 10 * [0xe0500000 - 0xe050ffff] prefmem | |
| Assigned: PCI: 02:00.0 18 * [0xe0510000 - 0xe051ffff] prefmem | |
| Assigned: PCI: 02:00.1 10 * [0xe0520000 - 0xe052ffff] prefmem | |
| PCI: 00:1c.1 allocate_resources_prefmem: next_base: e0530000 size: 100000 align: 20 gran: 20 done | |
| PCI: 00:1c.1 allocate_resources_mem: base:e0600000 size:100000 align:20 gran:20 limit:efffffff | |
| Assigned: PCI: 02:00.0 30 * [0xe0600000 - 0xe06007ff] mem | |
| PCI: 00:1c.1 allocate_resources_mem: next_base: e0600800 size: 100000 align: 20 gran: 20 done | |
| Root Device assign_resources, bus 0 link: 0 | |
| TOUUD 0x100600000 TOLUD 0x7ea00000 TOM 0x80000000 | |
| MEBASE 0x7f000000 | |
| IGD decoded, subtracting 32M UMA and 2M GTT | |
| TSEG base 0x7c000000 size 8M | |
| Available memory below 4GB: 1984M | |
| Available memory above 4GB: 6M | |
| Adding PCIe config bar base=0xf0000000 size=0x4000000 | |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 | |
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> | |
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64 | |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 | |
| PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io | |
| PCI: 00:16.0 10 <- [0x00e0706100 - 0x00e070610f] size 0x00000010 gran 0x04 mem64 | |
| PCI: 00:1a.0 10 <- [0x00e0705800 - 0x00e0705bff] size 0x00000400 gran 0x0a mem | |
| PCI: 00:1b.0 10 <- [0x00e0700000 - 0x00e0703fff] size 0x00004000 gran 0x0e mem64 | |
| PCI: 00:1c.0 1c <- [0x000000fd5f - 0x000000fd5e] size 0x00000000 gran 0x0c bus 01 io | |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem | |
| PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem | |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 | |
| PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e047ffff] size 0x00080000 gran 0x13 mem64 | |
| PCI: 01:00.0 30 <- [0x00e0480000 - 0x00e048ffff] size 0x00010000 gran 0x10 romem | |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 | |
| PCI: 00:1c.1 1c <- [0x000000fd5f - 0x000000fd5e] size 0x00000000 gran 0x0c bus 02 io | |
| PCI: 00:1c.1 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 02 prefmem | |
| PCI: 00:1c.1 20 <- [0x00e0600000 - 0x00e06fffff] size 0x00100000 gran 0x14 bus 02 mem | |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 | |
| PCI: 02:00.0 10 <- [0x00e0500000 - 0x00e050ffff] size 0x00010000 gran 0x10 prefmem64 | |
| PCI: 02:00.0 18 <- [0x00e0510000 - 0x00e051ffff] size 0x00010000 gran 0x10 prefmem64 | |
| PCI: 02:00.0 30 <- [0x00e0600000 - 0x00e06007ff] size 0x00000800 gran 0x0b romem | |
| PCI: 02:00.1 10 <- [0x00e0520000 - 0x00e052ffff] size 0x00010000 gran 0x10 prefmem64 | |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 | |
| PCI: 00:1d.0 10 <- [0x00e0705c00 - 0x00e0705fff] size 0x00000400 gran 0x0a mem | |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 | |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 | |
| PCI: 00:1f.2 10 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io | |
| PCI: 00:1f.2 14 <- [0x0000001070 - 0x0000001073] size 0x00000004 gran 0x02 io | |
| PCI: 00:1f.2 18 <- [0x0000001068 - 0x000000106f] size 0x00000008 gran 0x03 io | |
| PCI: 00:1f.2 1c <- [0x0000001074 - 0x0000001077] size 0x00000004 gran 0x02 io | |
| PCI: 00:1f.2 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io | |
| PCI: 00:1f.2 24 <- [0x00e0705000 - 0x00e07057ff] size 0x00000800 gran 0x0b mem | |
| PCI: 00:1f.3 10 <- [0x00e0706000 - 0x00e07060ff] size 0x00000100 gran 0x08 mem64 | |
| PCI: 00:1f.6 10 <- [0x00e0704000 - 0x00e0704fff] size 0x00001000 gran 0x0c mem64 | |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 | |
| CBMEM region 7bec0000-7bffffff (cbmem_late_set_table) | |
| Root Device assign_resources, bus 0 link: 0 | |
| Done setting resources. | |
| Show resources in subtree (Root Device)...After assigning values. | |
| Root Device child on link 0 CPU_CLUSTER: 0 | |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 | |
| APIC: 00 | |
| APIC: acac | |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 | |
| DOMAIN: 0000 resource base 1000 size 78 align 6 gran 0 limit fd5f flags 40040100 index 10000000 | |
| DOMAIN: 0000 resource base d0000000 size 10706110 align 28 gran 0 limit efffffff flags 40040200 index 10000100 | |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 | |
| DOMAIN: 0000 resource base 100000 size 7bf00000 align 0 gran 0 limit 0 flags e0004200 index 4 | |
| DOMAIN: 0000 resource base 100000000 size 600000 align 0 gran 0 limit 0 flags e0004200 index 5 | |
| DOMAIN: 0000 resource base 7c000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 | |
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 | |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8 | |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9 | |
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a | |
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b | |
| PCI: 00:00.0 | |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf | |
| PCI: 00:02.0 | |
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10 | |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60101201 index 18 | |
| PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit fd5f flags 60000100 index 20 | |
| PCI: 00:16.0 | |
| PCI: 00:16.0 resource base e0706100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10 | |
| PCI: 00:16.1 | |
| PCI: 00:16.2 | |
| PCI: 00:16.3 | |
| PCI: 00:19.0 | |
| PCI: 00:1a.0 | |
| PCI: 00:1a.0 resource base e0705800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 | |
| PCI: 00:1b.0 | |
| PCI: 00:1b.0 resource base e0700000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 | |
| PCI: 00:1c.2 | |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 | |
| PCI: 00:1c.0 resource base fd5f size 0 align 12 gran 12 limit fd5f flags 60080102 index 1c | |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 | |
| PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 | |
| PCI: 01:00.0 | |
| PCI: 01:00.0 resource base e0400000 size 80000 align 19 gran 19 limit efffffff flags 60000201 index 10 | |
| PCI: 01:00.0 resource base e0480000 size 10000 align 16 gran 16 limit efffffff flags 60002200 index 30 | |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 | |
| PCI: 00:1c.1 resource base fd5f size 0 align 12 gran 12 limit fd5f flags 60080102 index 1c | |
| PCI: 00:1c.1 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60081202 index 24 | |
| PCI: 00:1c.1 resource base e0600000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 | |
| PCI: 02:00.0 | |
| PCI: 02:00.0 resource base e0500000 size 10000 align 16 gran 16 limit efffffff flags 60001201 index 10 | |
| PCI: 02:00.0 resource base e0510000 size 10000 align 16 gran 16 limit efffffff flags 60001201 index 18 | |
| PCI: 02:00.0 resource base e0600000 size 800 align 11 gran 11 limit efffffff flags 60002200 index 30 | |
| PCI: 02:00.1 | |
| PCI: 02:00.1 resource base e0520000 size 10000 align 16 gran 16 limit efffffff flags 60001201 index 10 | |
| PCI: 00:1c.3 | |
| PCI: 00:1c.4 | |
| PCI: 00:1c.5 | |
| PCI: 00:1c.6 | |
| PCI: 00:1c.7 | |
| PCI: 00:1d.0 | |
| PCI: 00:1d.0 resource base e0705c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 | |
| PCI: 00:1e.0 | |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 | |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 | |
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 | |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 | |
| PCI: 00:1f.0 resource base fd60 size 4 align 0 gran 0 limit 0 flags c0040100 index 10000200 | |
| PNP: 00ff.1 | |
| PNP: 00ff.0 | |
| PCI: 00:1f.2 | |
| PCI: 00:1f.2 resource base 1060 size 8 align 3 gran 3 limit fd5f flags 60000100 index 10 | |
| PCI: 00:1f.2 resource base 1070 size 4 align 2 gran 2 limit fd5f flags 60000100 index 14 | |
| PCI: 00:1f.2 resource base 1068 size 8 align 3 gran 3 limit fd5f flags 60000100 index 18 | |
| PCI: 00:1f.2 resource base 1074 size 4 align 2 gran 2 limit fd5f flags 60000100 index 1c | |
| PCI: 00:1f.2 resource base 1040 size 20 align 5 gran 5 limit fd5f flags 60000100 index 20 | |
| PCI: 00:1f.2 resource base e0705000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24 | |
| PCI: 00:1f.3 | |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 | |
| PCI: 00:1f.3 resource base e0706000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10 | |
| PCI: 00:1f.5 | |
| PCI: 00:1f.6 | |
| PCI: 00:1f.6 resource base e0704000 size 1000 align 12 gran 12 limit efffffff flags 60000201 index 10 | |
| Done allocating resources. | |
| Enabling resources... | |
| PCI: 00:00.0 subsystem <- 0000/0000 | |
| PCI: 00:00.0 cmd <- 06 | |
| PCI: 00:02.0 subsystem <- 0000/0000 | |
| PCI: 00:02.0 cmd <- 03 | |
| PCI: 00:16.0 subsystem <- 0000/0000 | |
| PCI: 00:16.0 cmd <- 02 | |
| PCI: 00:1a.0 subsystem <- 0000/0000 | |
| PCI: 00:1a.0 cmd <- 102 | |
| PCI: 00:1b.0 subsystem <- 0000/0000 | |
| PCI: 00:1b.0 cmd <- 102 | |
| PCI: 00:1c.0 bridge ctrl <- 0003 | |
| PCI: 00:1c.0 subsystem <- 0000/0000 | |
| PCI: 00:1c.0 cmd <- 106 | |
| PCI: 00:1c.1 bridge ctrl <- 0003 | |
| PCI: 00:1c.1 subsystem <- 0000/0000 | |
| PCI: 00:1c.1 cmd <- 106 | |
| PCI: 00:1d.0 subsystem <- 0000/0000 | |
| PCI: 00:1d.0 cmd <- 102 | |
| pch_decode_init | |
| PCI: 00:1f.0 subsystem <- 0000/0000 | |
| PCI: 00:1f.0 cmd <- 107 | |
| PCI: 00:1f.2 subsystem <- 0000/0000 | |
| PCI: 00:1f.2 cmd <- 03 | |
| PCI: 00:1f.3 subsystem <- 0000/0000 | |
| PCI: 00:1f.3 cmd <- 103 | |
| PCI: 00:1f.6 subsystem <- 0000/0000 | |
| PCI: 00:1f.6 cmd <- 02 | |
| PCI: 01:00.0 cmd <- 02 | |
| PCI: 02:00.0 cmd <- 02 | |
| PCI: 02:00.1 cmd <- 06 | |
| done. | |
| Initializing devices... | |
| Root Device init | |
| Parrot EC Init | |
| EC version 0.7.1 | |
| EC Project: KZV1V | |
| Parrot Revision 2 | |
| CPU_CLUSTER: 0 init | |
| start_eip=0x00001000, code_size=0x00000031 | |
| Installing SMM handler to 0x7c000000 | |
| Installing IED header to 0x7c400000 | |
| Initializing SMM handler... ... pmbase = 0x0500 | |
| SMI_STS: | |
| PM1_STS: BM | |
| GPE0_STS: GPIO15 GPIO14 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 | |
| ALT_GP_SMI_STS: GPI15 GPI14 GPI12 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 | |
| TCO_STS: | |
| ... raise SMI# | |
| Initializing CPU #0 | |
| CPU: vendor Intel device 206a7 | |
| CPU: family 06, model 2a, stepping 07 | |
| Enabling cache | |
| microcode: sig=0x206a7 pf=0x10 revision=0x28 | |
| CPU: Intel(R) Celeron(R) CPU 847 @ 1.10GHz. | |
| MTRR: Physical address space: | |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 | |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 | |
| 0x00000000000c0000 - 0x000000007c000000 size 0x7bf40000 type 6 | |
| 0x000000007c000000 - 0x00000000d0000000 size 0x54000000 type 0 | |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 | |
| 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 | |
| 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 | |
| 0x0000000100000000 - 0x0000000100600000 size 0x00600000 type 6 | |
| MTRR: Fixed MSR 0x250 0x0606060606060606 | |
| MTRR: Fixed MSR 0x258 0x0606060606060606 | |
| MTRR: Fixed MSR 0x259 0x0000000000000000 | |
| MTRR: Fixed MSR 0x268 0x0606060606060606 | |
| MTRR: Fixed MSR 0x269 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 | |
| call enable_fixed_mtrr() | |
| MTRR: default type WB/UC MTRR counts: 11/8. | |
| MTRR: UC selected as default type. | |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6 | |
| MTRR: 1 base 0x0000000040000000 mask 0x0000000fe0000000 type 6 | |
| MTRR: 2 base 0x0000000060000000 mask 0x0000000ff0000000 type 6 | |
| MTRR: 3 base 0x0000000070000000 mask 0x0000000ff8000000 type 6 | |
| MTRR: 4 base 0x0000000078000000 mask 0x0000000ffc000000 type 6 | |
| MTRR: 5 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 | |
| MTRR: 6 base 0x00000000ff800000 mask 0x0000000fff800000 type 0 | |
| MTRR: 7 base 0x0000000100000000 mask 0x0000000f00000000 type 6 | |
| MTRR check | |
| Fixed MTRRs : Enabled | |
| Variable MTRRs: Enabled | |
| Setting up local apic... apic_id: 0x00 done. | |
| VMX is locked, so enable_vmx will do nothing | |
| model_x06ax: energy policy set to 6 | |
| model_x06ax: frequency set to 1100 | |
| Turbo is unavailable | |
| CPU: 0 has 2 cores, 1 threads per core | |
| CPU: 0 has core 2 | |
| CPU1: stack_base 00163000, stack_end 00163ff8 | |
| Asserting INIT. | |
| Waiting for send to finish... | |
| +Deasserting INIT. | |
| Waiting for send to finish... | |
| +#startup loops: 2. | |
| Sending STARTUP #1 to 2. | |
| After apic_write. | |
| Initializing CPU #1 | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +CPU: vendor Intel device 206a7 | |
| Sending STARTUP #2 to 2. | |
| After apic_write. | |
| CPU: family 06, model 2a, stepping 07 | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +Enabling cache | |
| After Startup. | |
| CPU #0 initialized | |
| Waiting for 1 CPUS to stop | |
| microcode: sig=0x206a7 pf=0x10 revision=0x0 | |
| microcode: updated to revision 0x28 date=2012-04-24 | |
| CPU: Intel(R) Celeron(R) CPU 847 @ 1.10GHz. | |
| MTRR: Fixed MSR 0x250 0x0606060606060606 | |
| MTRR: Fixed MSR 0x258 0x0606060606060606 | |
| MTRR: Fixed MSR 0x259 0x0000000000000000 | |
| MTRR: Fixed MSR 0x268 0x0606060606060606 | |
| MTRR: Fixed MSR 0x269 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 | |
| call enable_fixed_mtrr() | |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6 | |
| MTRR: 1 base 0x0000000040000000 mask 0x0000000fe0000000 type 6 | |
| MTRR: 2 base 0x0000000060000000 mask 0x0000000ff0000000 type 6 | |
| MTRR: 3 base 0x0000000070000000 mask 0x0000000ff8000000 type 6 | |
| MTRR: 4 base 0x0000000078000000 mask 0x0000000ffc000000 type 6 | |
| MTRR: 5 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 | |
| MTRR: 6 base 0x00000000ff800000 mask 0x0000000fff800000 type 0 | |
| MTRR: 7 base 0x0000000100000000 mask 0x0000000f00000000 type 6 | |
| MTRR check | |
| Fixed MTRRs : Enabled | |
| Variable MTRRs: Enabled | |
| Setting up local apic... apic_id: 0x02 done. | |
| VMX is locked, so enable_vmx will do nothing | |
| model_x06ax: energy policy set to 6 | |
| model_x06ax: frequency set to 1100 | |
| CPU #1 initialized | |
| All AP CPUs stopped (4878 loops) | |
| CPU1: stack: 00163000 - 00164000, lowest used address 00163c5c, stack used: 932 bytes | |
| PCI: 00:00.0 init | |
| Set BIOS_RESET_CPL | |
| CPU TDP: 17 Watts | |
| PCI: 00:02.0 init | |
| GT Power Management Init | |
| SNB GT1 Power Meter Weights | |
| In CBFS, ROM address for PCI: 00:02.0 = fff004f8 | |
| PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 | |
| PCI ROM image, vendor ID 8086, device ID 0106, | |
| PCI ROM image, Class Code 030000, Code Type 00 | |
| Copying VGA ROM Image from fff004f8 to 0xc0000, 0x10000 bytes | |
| Real mode stub @00000600: 867 bytes | |
| Calling Option ROM... | |
| int15_handler: INT15 function 5f34! | |
| ... Option ROM returned. | |
| VBE: Getting information about VESA mode 4117 | |
| VBE: resolution: 1024x768@16 | |
| VBE: framebuffer: d0000000 | |
| VBE: Setting VESA mode 4117 | |
| int15_handler: INT15 function 5f70! | |
| GT Power Management Init (post VBIOS) | |
| PCI: 00:16.0 init | |
| ME: FW Partition Table : OK | |
| ME: Bringup Loader Failure : NO | |
| ME: Firmware Init Complete : NO | |
| ME: Manufacturing Mode : NO | |
| ME: Boot Options Present : NO | |
| ME: Update In Progress : NO | |
| ME: Current Working State : Normal | |
| ME: Current Operation State : M0 with UMA | |
| ME: Current Operation Mode : Normal | |
| ME: Error Code : No Error | |
| ME: Progress Phase : Host Communication | |
| ME: Power Management Event : Pseudo-global reset | |
| ME: Progress Phase State : Host communication established | |
| ME: BIOS path: Normal | |
| ME: Extend SHA-256: ed931a410b99a2c8c57c310a57e40a799876d576bec64a7916a89221ae5c0d31 | |
| ME: MBP item header 00020103 | |
| ME: MBP item header 00050102 | |
| ME: MBP item header 00020501 | |
| ME: MBP item header 00020201 | |
| ME: MBP item header 02030101 | |
| ME: MBP item header 02060301 | |
| ME: MBP item header 02090401 | |
| ME: mbp read OK after 1 cycles | |
| ME: found version 8.0.13.1502 | |
| ME Capability: Full Network manageability : disabled | |
| ME Capability: Regular Network manageability : disabled | |
| ME Capability: Manageability : disabled | |
| ME Capability: Small business technology : disabled | |
| ME Capability: Level III manageability : disabled | |
| ME Capability: IntelR Anti-Theft (AT) : disabled | |
| ME Capability: IntelR Capability Licensing Service (CLS) : enabled | |
| ME Capability: IntelR Power Sharing Technology (MPC) : enabled | |
| ME Capability: ICC Over Clocking : enabled | |
| ME Capability: Protected Audio Video Path (PAVP) : disabled | |
| ME Capability: IPV6 : disabled | |
| ME Capability: KVM Remote Control (KVM) : disabled | |
| ME Capability: Outbreak Containment Heuristic (OCH) : disabled | |
| ME Capability: Virtual LAN (VLAN) : enabled | |
| ME Capability: TLS : disabled | |
| ME Capability: Wireless LAN (WLAN) : disabled | |
| PCI: 00:1a.0 init | |
| EHCI: Setting up controller.. done. | |
| PCI: 00:1b.0 init | |
| Azalia: base = e0700000 | |
| Azalia: codec_mask = 09 | |
| Azalia: Initializing codec #3 | |
| Azalia: codec viddid: 80862806 | |
| Azalia: verb_size: 16 | |
| Azalia: verb loaded. | |
| Azalia: Initializing codec #0 | |
| Azalia: codec viddid: 10ec0269 | |
| Azalia: verb_size: 56 | |
| Azalia: verb loaded. | |
| PCI: 00:1c.0 init | |
| Initializing PCH PCIe bridge. | |
| PCI: 00:1c.1 init | |
| Initializing PCH PCIe bridge. | |
| PCI: 00:1d.0 init | |
| EHCI: Setting up controller.. done. | |
| PCI: 00:1f.0 init | |
| pch: lpc_init | |
| IOAPIC: Initializing IOAPIC at 0xfec00000 | |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 | |
| IOAPIC: ID = 0x02 | |
| IOAPIC: Dumping registers | |
| reg 0x0000: 0x02000000 | |
| reg 0x0001: 0x00170020 | |
| reg 0x0002: 0x00170020 | |
| Set power off after power failure. | |
| NMI sources disabled. | |
| PantherPoint PM init | |
| rtc_failed = 0x0 | |
| RTC Init | |
| i8259_configure_irq_trigger: current interrupts are 0x0 | |
| i8259_configure_irq_trigger: try to set interrupts 0x200 | |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: | |
| done. | |
| Locking SMM. | |
| PCI: 00:1f.2 init | |
| SATA: Initializing... | |
| SATA: Controller in AHCI mode. | |
| ABAR: E0705000 | |
| PCI: 00:1f.3 init | |
| PCI: 00:1f.6 init | |
| CBFS: ERROR: No file header found at 0x7ff9c0 - try next aligned address: 0x7ffa00. | |
| CBFS: WARNING: 'pci8086,1e24.rom' not found. | |
| CBFS: Could not find file 'pci8086,1e24.rom'. | |
| PCI: 01:00.0 init | |
| CBFS: ERROR: No file header found at 0x7ff9c0 - try next aligned address: 0x7ffa00. | |
| CBFS: WARNING: 'pci168c,0034.rom' not found. | |
| CBFS: Could not find file 'pci168c,0034.rom'. | |
| Option ROM address for PCI: 01:00.0 = e0480000 | |
| PCI expansion ROM, signature 0xbeef, INIT size 0x15a00, data ptr 0xbeef | |
| Incorrect expansion ROM header signature beef | |
| PCI: 02:00.0 init | |
| CBFS: ERROR: No file header found at 0x7ff9c0 - try next aligned address: 0x7ffa00. | |
| CBFS: WARNING: 'pci14e4,16b5.rom' not found. | |
| CBFS: Could not find file 'pci14e4,16b5.rom'. | |
| Option ROM address for PCI: 02:00.0 = e0600000 | |
| PCI expansion ROM, signature 0xff04, INIT size 0x0400, data ptr 0xff04 | |
| Incorrect expansion ROM header signature ff04 | |
| PCI: 02:00.1 init | |
| CBFS: ERROR: No file header found at 0x7ff9c0 - try next aligned address: 0x7ffa00. | |
| CBFS: WARNING: 'pci14e4,16bc.rom' not found. | |
| CBFS: Could not find file 'pci14e4,16bc.rom'. | |
| PNP: 00ff.0 init | |
| Compal ENE932: Initializing keyboard. | |
| Keyboard init... | |
| Devices initialized | |
| Show all devs...After init. | |
| Root Device: enabled 1 | |
| CPU_CLUSTER: 0: enabled 1 | |
| APIC: 00: enabled 1 | |
| APIC: acac: enabled 0 | |
| DOMAIN: 0000: enabled 1 | |
| PCI: 00:00.0: enabled 1 | |
| PCI: 00:02.0: enabled 1 | |
| PCI: 00:16.0: enabled 1 | |
| PCI: 00:16.1: enabled 0 | |
| PCI: 00:16.2: enabled 0 | |
| PCI: 00:16.3: enabled 0 | |
| PCI: 00:19.0: enabled 0 | |
| PCI: 00:1a.0: enabled 1 | |
| PCI: 00:1b.0: enabled 1 | |
| PCI: 00:1c.2: enabled 0 | |
| PCI: 00:1c.0: enabled 1 | |
| PCI: 00:1c.1: enabled 1 | |
| PCI: 00:1c.3: enabled 0 | |
| PCI: 00:1c.4: enabled 0 | |
| PCI: 00:1c.5: enabled 0 | |
| PCI: 00:1c.6: enabled 0 | |
| PCI: 00:1c.7: enabled 0 | |
| PCI: 00:1d.0: enabled 1 | |
| PCI: 00:1e.0: enabled 0 | |
| PCI: 00:1f.0: enabled 1 | |
| PNP: 00ff.1: enabled 1 | |
| PCI: 00:1f.2: enabled 1 | |
| PCI: 00:1f.3: enabled 1 | |
| PCI: 00:1f.5: enabled 0 | |
| PCI: 00:1f.6: enabled 1 | |
| PCI: 01:00.0: enabled 1 | |
| PCI: 02:00.0: enabled 1 | |
| PCI: 02:00.1: enabled 1 | |
| PNP: 00ff.0: enabled 1 | |
| APIC: 02: enabled 1 | |
| CBMEM region 7bec0000-7bffffff (cbmem_reinit) | |
| Adding CBMEM entry as no. 4 | |
| Moving GDT to 7bed1000...ok | |
| Finalize devices... | |
| Devices finalized | |
| Updating MRC cache data. | |
| find_current_mrc_cache_local: No valid MRC cache found. | |
| SF: Detected W25Q64 with page size 1000, total 800000 | |
| Need to erase the MRC cache region of 65536 bytes at fff80000 | |
| SF: Successfully erased 65536 bytes @ 0x780000 | |
| Finally: write MRC cache update to flash at fff80000 | |
| CBMEM Base is 7bec0000. | |
| Adding CBMEM entry as no. 5 | |
| ACPI: Writing ACPI tables at 7bed1200. | |
| ACPI: * FACS | |
| ACPI: * DSDT | |
| ACPI: * FADT | |
| ACPI: added table 1/32, length now 40 | |
| ACPI: * HPET | |
| ACPI: added table 2/32, length now 44 | |
| ACPI: * MADT | |
| ACPI: added table 3/32, length now 48 | |
| ACPI: * MCFG | |
| ACPI: added table 4/32, length now 52 | |
| ACPI: Patching up global NVS in DSDT at offset 0x01ab -> 0x7bed48d0 | |
| Adding CBMEM entry as no. 6 | |
| ACPI: * DSDT @ 7bed1450 Length 3293 | |
| ACPI: * SSDT | |
| Found 1 CPU(s) with 2 core(s) each. | |
| PSS: 1100MHz power 17000 control 0xb00 status 0xb00 | |
| PSS: 800MHz power 11938 control 0x800 status 0x800 | |
| PSS: 1100MHz power 17000 control 0xb00 status 0xb00 | |
| PSS: 800MHz power 11938 control 0x800 status 0x800 | |
| ACPI: added table 5/32, length now 56 | |
| current = 7bed5fb0 | |
| ACPI: done. | |
| ACPI tables: 19888 bytes. | |
| Adding CBMEM entry as no. 7 | |
| smbios_write_tables: 7bedc800 | |
| Root Device (Google Parrot) | |
| CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| APIC: 00 (Socket rPGA989 CPU) | |
| APIC: acac (Intel SandyBridge/IvyBridge CPU) | |
| DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PNP: 00ff.1 (COMPAL ENE932 EC) | |
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 01:00.0 (unknown) | |
| PCI: 02:00.0 (unknown) | |
| PCI: 02:00.1 (unknown) | |
| PNP: 00ff.0 (unknown) | |
| APIC: 02 (unknown) | |
| SMBIOS tables: 324 bytes. | |
| Adding CBMEM entry as no. 8 | |
| Adding CBMEM entry as no. 9 | |
| Writing table forward entry at 0x00000500 | |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum b3e0 | |
| Table forward entry ends at 0x00000528. | |
| ... aligned to 0x00001000 | |
| Writing coreboot table at 0x7bfdd000 | |
| rom_table_end = 0x7bfdd000 | |
| ... aligned to 0x7bfe0000 | |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES | |
| 1. 0000000000001000-000000000009ffff: RAM | |
| 2. 00000000000a0000-00000000000fffff: RESERVED | |
| 3. 0000000000100000-000000001fffffff: RAM | |
| 4. 0000000020000000-00000000201fffff: RESERVED | |
| 5. 0000000020200000-000000003fffffff: RAM | |
| 6. 0000000040000000-00000000401fffff: RESERVED | |
| 7. 0000000040200000-000000007bebffff: RAM | |
| 8. 000000007bec0000-000000007bffffff: CONFIGURATION TABLES | |
| 9. 000000007c000000-000000007e9fffff: RESERVED | |
| 10. 00000000f0000000-00000000f3ffffff: RESERVED | |
| 11. 0000000100000000-00000001005fffff: RAM | |
| Wrote coreboot table at: 7bfdd000, 0x26c bytes, checksum c9db | |
| coreboot table: 644 bytes. | |
| Multiboot Information structure has been written. | |
| FREE SPACE 0. 7bfe5000 0001b000 | |
| CAR GLOBALS 1. 7bec0200 00000200 | |
| CONSOLE 2. 7bec0400 00010000 | |
| MRC DATA 3. 7bed0400 00000c00 | |
| GDT 4. 7bed1000 00000200 | |
| ACPI 5. 7bed1200 0000b400 | |
| GNVS PTR 6. 7bedc600 00000200 | |
| SMBIOS 7. 7bedc800 00000800 | |
| ACPI RESUME 8. 7bedd000 00100000 | |
| COREBOOT 9. 7bfdd000 00008000 | |
| Loading segment from rom address 0xfff305f8 | |
| code (compression=1) | |
| New segment dstaddr 0xe6e30 memsize 0x191d0 srcaddr 0xfff30630 filesize 0xcbe8 | |
| (cleaned up) New segment addr 0xe6e30 size 0x191d0 offset 0xfff30630 filesize 0xcbe8 | |
| Loading segment from rom address 0xfff30614 | |
| Entry Point 0x000fc7a8 | |
| Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB | |
| Loading Segment: addr: 0x00000000000e6e30 memsz: 0x00000000000191d0 filesz: 0x000000000000cbe8 | |
| lb: [0x0000000000100000, 0x0000000000169040) | |
| Post relocation: addr: 0x00000000000e6e30 memsz: 0x00000000000191d0 filesz: 0x000000000000cbe8 | |
| using LZMA | |
| [ 0x000e6e30, 00100000, 0x00100000) <- fff30630 | |
| dest 000e6e30, end 00100000, bouncebuffer 7bdedf80 | |
| Loaded segments | |
| int15_handler: INT15 function 5f70! | |
| PCH watchdog disabled | |
| Jumping to boot code at 000fc7a8 | |
| CPU0: stack: 00164000 - 00165000, lowest used address 00164aac, stack used: 1364 bytes | |
| entry = 0x000fc7a8 | |
| lb_start = 0x00100000 | |
| lb_size = 0x00069040 | |
| buffer = 0x7bdedf80 | |