| |
| [NOTE ] coreboot-4.19-1111-g177e135136 Thu Apr 06 15:27:23 UTC 2023 x86_32 bootblock starting (log level: 7)... |
| [INFO ] Timestamp - end of bootblock: 14978699 |
| [INFO ] Timestamp - starting to load romstage: 18229259 |
| [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x0. |
| [DEBUG] FMAP: base = 0xfffc0000 size = 0x40000 #areas = 3 |
| [DEBUG] FMAP: area COREBOOT found @ 200 (261632 bytes) |
| [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x66f8 |
| [INFO ] Timestamp - finished loading romstage: 65719218 |
| [DEBUG] BS: bootblock times (exec / console): total (unknown) / 52 ms |
| [DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xfffc0000, size: 0x00008000 |
| |
| |
| [NOTE ] coreboot-4.19-1111-g177e135136 Thu Apr 06 15:27:23 UTC 2023 x86_32 romstage starting (log level: 7)... |
| [DEBUG] Romstage stack size limited to 0x1000! |
| [DEBUG] SMBus controller enabled |
| [INFO ] Timestamp - before RAM initialization: 96587591 |
| [INFO ] Timestamp - after RAM initialization: 156473676 |
| [DEBUG] CBMEM: |
| [DEBUG] IMD: root @ 0x17fff000 254 entries. |
| [DEBUG] IMD: root @ 0x17ffec00 62 entries. |
| [DEBUG] FMAP: area COREBOOT found @ 200 (261632 bytes) |
| [INFO ] CBFS: Found 'fallback/postcar' @0x1f940 size 0x734c |
| [DEBUG] Loading module at 0x17fd0000 with entry 0x17fd0031. filesize: 0x6c20 memsize: 0xcf30 |
| [DEBUG] Processing 443 relocs. Offset value of 0x15fd0000 |
| [INFO ] Timestamp - end of romstage: 205600672 |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 76 ms |
| |
| |
| [NOTE ] coreboot-4.19-1111-g177e135136 Thu Apr 06 15:27:23 UTC 2023 x86_32 postcar starting (log level: 7)... |
| [INFO ] Timestamp - start of postcar: 222114203 |
| [INFO ] Timestamp - end of postcar: 225381270 |
| [INFO ] Timestamp - starting to load ramstage: 228541830 |
| [DEBUG] FMAP: area COREBOOT found @ 200 (261632 bytes) |
| [INFO ] CBFS: Found 'fallback/ramstage' @0xe040 size 0xf3c2 |
| [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 240053749 |
| [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 294466509 |
| [DEBUG] Loading module at 0x17fa5000 with entry 0x17fa5000. filesize: 0x1e9c0 memsize: 0x295a8 |
| [DEBUG] Processing 2263 relocs. Offset value of 0x13fa5000 |
| [INFO ] Timestamp - finished loading ramstage: 309084587 |
| [DEBUG] BS: postcar times (exec / console): total (unknown) / 74 ms |
| |
| |
| [NOTE ] coreboot-4.19-1111-g177e135136 Thu Apr 06 15:27:23 UTC 2023 x86_32 ramstage starting (log level: 7)... |
| [INFO ] Timestamp - start of ramstage: 325996673 |
| [INFO ] Timestamp - device enumeration: 329324626 |
| [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 5 ms |
| [INFO ] Enumerating buses... |
| [DEBUG] Root Device scanning... |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 0000 enabled |
| [DEBUG] DOMAIN: 0000 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 00 |
| [DEBUG] PCI: 00:00.0 [8086/7190] enabled |
| [DEBUG] PCI: 00:01.0 [8086/7191] enabled |
| [DEBUG] PCI: 00:04.0 [8086/7110] enabled |
| [DEBUG] PCI: 00:04.1 [8086/7111] enabled |
| [DEBUG] PCI: 00:04.2 [8086/7112] enabled |
| [DEBUG] PCI: 00:04.3 [8086/7113] enabled |
| [DEBUG] PCI: 00:0b.0 [1106/3106] enabled |
| [DEBUG] PCI: 00:01.0 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 01 |
| [DEBUG] PCI: 01:00.0 [1002/5960] enabled |
| [DEBUG] PCI: 01:00.1 [1002/5940] enabled |
| [DEBUG] scan_bus: bus PCI: 00:01.0 finished in 12 msecs |
| [DEBUG] PCI: 00:04.0 scanning... |
| [DEBUG] PNP: 03f0.0 enabled |
| [DEBUG] PNP: 03f0.1 enabled |
| [DEBUG] PNP: 03f0.2 enabled |
| [DEBUG] PNP: 03f0.3 enabled |
| [DEBUG] PNP: 03f0.5 enabled |
| [DEBUG] PNP: 03f0.7 enabled |
| [DEBUG] PNP: 03f0.8 enabled |
| [DEBUG] PNP: 03f0.9 enabled |
| [DEBUG] PNP: 03f0.a enabled |
| [DEBUG] scan_bus: bus PCI: 00:04.0 finished in 29 msecs |
| [DEBUG] PCI: 00:04.3 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:04.3 finished in 0 msecs |
| [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 105 msecs |
| [DEBUG] scan_bus: bus Root Device finished in 122 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 137 ms |
| [INFO ] Timestamp - device configuration: 430709562 |
| [DEBUG] found VGA at PCI: 01:00.0 |
| [WARN ] A bridge on the path doesn't support 16-bit VGA decoding!Setting up VGA for PCI: 01:00.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [DEBUG] Setting RAM size to 384 MB |
| [ERROR] PNP: 03f0.8 missing read_resources |
| [ERROR] PNP: 03f0.9 missing read_resources |
| [INFO ] Done reading resources. |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| [DEBUG] PCI: 00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 01:00.0 14 * [0x0 - 0xff] io |
| [DEBUG] PCI: 00:01.0 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem |
| [DEBUG] PCI: 01:00.0 18 * [0x20000 - 0x2ffff] mem |
| [DEBUG] PCI: 01:00.1 14 * [0x30000 - 0x3ffff] mem |
| [DEBUG] PCI: 00:01.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x7ffffff] prefmem |
| [DEBUG] PCI: 01:00.1 10 * [0x8000000 - 0xfffffff] prefmem |
| [DEBUG] PCI: 00:01.0 prefmem: size: 10000000 align: 27 gran: 20 limit: ffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] update_constraints: PCI: 00:04.0 01 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.0 60 base 000003f0 limit 000003f7 io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.1 60 base 00000378 limit 0000037f io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.2 60 base 000003f8 limit 000003ff io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.3 60 base 000002f8 limit 000002ff io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.5 60 base 00000060 limit 00000060 io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.5 62 base 00000064 limit 00000064 io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.7 60 base 00000000 limit 00000000 io (fixed) |
| [DEBUG] update_constraints: PNP: 03f0.7 62 base 00000000 limit 00000001 io (fixed) |
| [DEBUG] update_constraints: PCI: 00:04.3 01 base 0000e400 limit 0000e43f io (fixed) |
| [DEBUG] update_constraints: PCI: 00:04.3 02 base 00000f00 limit 00000f0f io (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 1000, Size: d400, Tag: 100 |
| [INFO ] * Base: e440, Size: 1bc0, Tag: 100 |
| [DEBUG] PCI: 00:01.0 1c * [0x1000 - 0x1fff] limit: 1fff io |
| [DEBUG] PCI: 00:0b.0 10 * [0x2000 - 0x20ff] limit: 20ff io |
| [DEBUG] PCI: 00:04.2 20 * [0x2100 - 0x211f] limit: 211f io |
| [DEBUG] PCI: 00:04.1 20 * [0x2120 - 0x212f] limit: 212f io |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| [DEBUG] update_constraints: DOMAIN: 0000 0a base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] update_constraints: DOMAIN: 0000 0b base 000c0000 limit 17ffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:04.0 02 base ff800000 limit ffffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:04.0 03 base fec00000 limit fec00fff mem (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: a0000, Size: 20000, Tag: 200 |
| [INFO ] * Base: 18000000, Size: e6c00000, Tag: 200 |
| [INFO ] * Base: fec01000, Size: bff000, Tag: 200 |
| [INFO ] * Base: 100000000, Size: f00000000, Tag: 100200 |
| [DEBUG] PCI: 00:00.0 10 * [0x20000000 - 0x2fffffff] limit: 2fffffff prefmem |
| [DEBUG] PCI: 00:01.0 24 * [0x30000000 - 0x3fffffff] limit: 3fffffff prefmem |
| [DEBUG] PCI: 00:01.0 20 * [0x18000000 - 0x180fffff] limit: 180fffff mem |
| [DEBUG] PCI: 00:0b.0 30 * [0xa0000 - 0xaffff] limit: affff mem |
| [DEBUG] PCI: 00:0b.0 14 * [0xb0000 - 0xb00ff] limit: b00ff mem |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| [DEBUG] PCI: 00:01.0 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff |
| [INFO ] PCI: 00:01.0: Resource ranges: |
| [INFO ] * Base: 1000, Size: 1000, Tag: 100 |
| [DEBUG] PCI: 01:00.0 14 * [0x1000 - 0x10ff] limit: 10ff io |
| [DEBUG] PCI: 00:01.0 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done |
| [DEBUG] PCI: 00:01.0 prefmem: base: 30000000 size: 10000000 align: 27 gran: 20 limit: 3fffffff |
| [INFO ] PCI: 00:01.0: Resource ranges: |
| [INFO ] * Base: 30000000, Size: 10000000, Tag: 1200 |
| [DEBUG] PCI: 01:00.0 10 * [0x30000000 - 0x37ffffff] limit: 37ffffff prefmem |
| [DEBUG] PCI: 01:00.1 10 * [0x38000000 - 0x3fffffff] limit: 3fffffff prefmem |
| [DEBUG] PCI: 00:01.0 prefmem: base: 30000000 size: 10000000 align: 27 gran: 20 limit: 3fffffff done |
| [DEBUG] PCI: 00:01.0 mem: base: 18000000 size: 100000 align: 20 gran: 20 limit: 180fffff |
| [INFO ] PCI: 00:01.0: Resource ranges: |
| [INFO ] * Base: 18000000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 01:00.0 30 * [0x18000000 - 0x1801ffff] limit: 1801ffff mem |
| [DEBUG] PCI: 01:00.0 18 * [0x18020000 - 0x1802ffff] limit: 1802ffff mem |
| [DEBUG] PCI: 01:00.1 14 * [0x18030000 - 0x1803ffff] limit: 1803ffff mem |
| [DEBUG] PCI: 00:01.0 mem: base: 18000000 size: 100000 align: 20 gran: 20 limit: 180fffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| [DEBUG] PCI: 00:00.0 10 <- [0x0000000020000000 - 0x000000002fffffff] size 0x10000000 gran 0x1c prefmem |
| [DEBUG] PCI: 00:01.0 1c <- [0x0000000000001000 - 0x0000000000001fff] size 0x00001000 gran 0x0c bus 01 io |
| [DEBUG] PCI: 00:01.0 24 <- [0x0000000030000000 - 0x000000003fffffff] size 0x10000000 gran 0x14 bus 01 prefmem |
| [DEBUG] PCI: 00:01.0 20 <- [0x0000000018000000 - 0x00000000180fffff] size 0x00100000 gran 0x14 bus 01 mem |
| [DEBUG] PCI: 01:00.0 10 <- [0x0000000030000000 - 0x0000000037ffffff] size 0x08000000 gran 0x1b prefmem |
| [DEBUG] PCI: 01:00.0 14 <- [0x0000000000001000 - 0x00000000000010ff] size 0x00000100 gran 0x08 io |
| [DEBUG] PCI: 01:00.0 18 <- [0x0000000018020000 - 0x000000001802ffff] size 0x00010000 gran 0x10 mem |
| [DEBUG] PCI: 01:00.0 30 <- [0x0000000018000000 - 0x000000001801ffff] size 0x00020000 gran 0x11 romem |
| [DEBUG] PCI: 01:00.1 10 <- [0x0000000038000000 - 0x000000003fffffff] size 0x08000000 gran 0x1b prefmem |
| [DEBUG] PCI: 01:00.1 14 <- [0x0000000018030000 - 0x000000001803ffff] size 0x00010000 gran 0x10 mem |
| [DEBUG] PNP: 03f0.0 60 <- [0x00000000000003f0 - 0x00000000000003f7] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 03f0.0 70 <- [0x0000000000000006 - 0x0000000000000006] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 03f0.0 74 <- [0x0000000000000002 - 0x0000000000000002] size 0x00000001 gran 0x00 drq |
| [DEBUG] PNP: 03f0.1 60 <- [0x0000000000000378 - 0x000000000000037f] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 03f0.1 70 <- [0x0000000000000007 - 0x0000000000000007] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 03f0.1 74 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 drq |
| [DEBUG] PNP: 03f0.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 03f0.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 03f0.3 60 <- [0x00000000000002f8 - 0x00000000000002ff] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 03f0.3 70 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 03f0.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 03f0.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 03f0.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 03f0.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 03f0.7 60 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 03f0.7 62 <- [0x0000000000000000 - 0x0000000000000001] size 0x00000002 gran 0x01 io |
| [DEBUG] PNP: 03f0.7 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq |
| [ERROR] PNP: 03f0.a 70 irq size: 0x0000000001 not assigned in devicetree |
| [DEBUG] PCI: 00:04.1 20 <- [0x0000000000002120 - 0x000000000000212f] size 0x00000010 gran 0x04 io |
| [DEBUG] PCI: 00:04.2 20 <- [0x0000000000002100 - 0x000000000000211f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:0b.0 10 <- [0x0000000000002000 - 0x00000000000020ff] size 0x00000100 gran 0x08 io |
| [DEBUG] PCI: 00:0b.0 14 <- [0x00000000000b0000 - 0x00000000000b00ff] size 0x00000100 gran 0x08 mem |
| [DEBUG] PCI: 00:0b.0 30 <- [0x00000000000a0000 - 0x00000000000affff] size 0x00010000 gran 0x10 romem |
| [INFO ] Done setting resources. |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 854 ms |
| [INFO ] Timestamp - device enable: 992637788 |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:01.0 bridge ctrl <- 009b |
| [DEBUG] PCI: 00:01.0 cmd <- 07 |
| [DEBUG] PCI: 00:04.0 cmd <- 07 |
| [DEBUG] PCI: 00:04.1 cmd <- 01 |
| [DEBUG] PCI: 00:04.2 cmd <- 01 |
| [DEBUG] PCI: 00:04.3 cmd <- 01 |
| [DEBUG] PCI: 00:0b.0 cmd <- 83 |
| [DEBUG] PCI: 01:00.0 cmd <- 03 |
| [DEBUG] PCI: 01:00.1 cmd <- 02 |
| [INFO ] done. |
| [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 47 ms |
| [INFO ] Timestamp - device initialization: 1027263393 |
| [INFO ] Initializing devices... |
| [DEBUG] CPU_CLUSTER: 0 init |
| [INFO ] CPU: . |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] CPU: APIC: 00 enabled |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 686 |
| [DEBUG] CPU: family 06, model 08, stepping 06 |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x0000000017ffffff size 0x17f40000 type 6 |
| [DEBUG] 0x0000000018000000 - 0x000000002fffffff size 0x18000000 type 0 |
| [DEBUG] 0x0000000030000000 - 0x0000000037ffffff size 0x08000000 type 1 |
| [DEBUG] 0x0000000038000000 - 0x00000000ffffffff size 0xc8000000 type 0 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 6/3. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000ff0000000 type 6 |
| [DEBUG] MTRR: 1 base 0x0000000010000000 mask 0x0000000ff8000000 type 6 |
| [DEBUG] MTRR: 2 base 0x0000000030000000 mask 0x0000000ff8000000 type 1 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [DEBUG] FMAP: area COREBOOT found @ 200 (261632 bytes) |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x6800 size 0x7800 |
| [DEBUG] microcode: sig=0x686 pf=0x10 revision=0x0 |
| [INFO ] microcode: load microcode patch |
| [INFO ] microcode: updated to revision 0x8 date=2000-05-05 |
| [INFO ] CPU #0 initialized |
| [INFO ] bsp_do_flight_plan done after 208 msecs. |
| [DEBUG] CPU_CLUSTER: 0 init finished in 223 msecs |
| [DEBUG] PCI: 00:00.0 init |
| [DEBUG] PCI: 00:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:04.0 init |
| [DEBUG] RTC Init |
| [DEBUG] PCI: 00:04.0 init finished in 2 msecs |
| [DEBUG] PCI: 00:04.1 init |
| [DEBUG] IDE: Primary IDE interface: on |
| [DEBUG] IDE: Secondary IDE interface: on |
| [DEBUG] IDE: Access to legacy IDE ports: on |
| [DEBUG] IDE: Primary IDE interface, drive 0: UDMA/33: on |
| [DEBUG] IDE: Primary IDE interface, drive 1: UDMA/33: on |
| [DEBUG] IDE: Secondary IDE interface, drive 0: UDMA/33: on |
| [DEBUG] IDE: Secondary IDE interface, drive 1: UDMA/33: on |
| [DEBUG] PCI: 00:04.1 init finished in 36 msecs |
| [DEBUG] PCI: 00:04.2 init |
| [DEBUG] PCI: 00:04.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:0b.0 init |
| [DEBUG] PCI: 00:0b.0 init finished in 0 msecs |
| [DEBUG] PCI: 01:00.0 init |
| [INFO ] Timestamp - Option ROM initialization: 1238061469 |
| [WARN ] CBFS: 'pci1002,5960.rom' not found. |
| [DEBUG] PCI Option ROM loading disabled for PCI: 01:00.0 |
| [DEBUG] PCI: 01:00.0 init finished in 17 msecs |
| [DEBUG] PCI: 01:00.1 init |
| [DEBUG] PCI: 01:00.1 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.0 init |
| [DEBUG] PNP: 03f0.0 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.1 init |
| [DEBUG] PNP: 03f0.1 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.2 init |
| [DEBUG] PNP: 03f0.2 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.3 init |
| [DEBUG] PNP: 03f0.3 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.5 init |
| [DEBUG] PNP: 03f0.5 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.7 init |
| [DEBUG] PNP: 03f0.7 init finished in 0 msecs |
| [DEBUG] PNP: 03f0.a init |
| [DEBUG] PNP: 03f0.a init finished in 0 msecs |
| [INFO ] Devices initialized |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 4 / 407 ms |
| [INFO ] Finalize devices... |
| [INFO ] Devices finalized |
| [INFO ] Timestamp - device setup done: 1303595886 |
| [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 12 ms |
| [INFO ] Timestamp - cbmem post: 1311218766 |
| [DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 5 ms |
| [INFO ] Timestamp - write tables: 1318613751 |
| [INFO ] Copying Interrupt Routing Table to 0x000f0000... done. |
| [INFO ] Copying Interrupt Routing Table to 0x17f9b000... done. |
| [DEBUG] PIRQ table: 128 bytes. |
| [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x1e080 size 0x157a |
| [WARN ] CBFS: 'fallback/slic' not found. |
| [INFO ] ACPI: Writing ACPI tables at 17f77000. |
| [DEBUG] ACPI: * FACS |
| [DEBUG] ACPI: * DSDT |
| [DEBUG] ACPI: * FADT |
| [DEBUG] ACPI: added table 1/32, length now 40 |
| [DEBUG] ACPI: * SSDT |
| [DEBUG] Found 1 CPU(s). |
| [WARN ] CBFS: 'pci1002,5960.rom' not found. |
| [DEBUG] PCI Option ROM loading disabled for PCI: 01:00.0 |
| [WARN ] PCI: 01:00.0: Missing PCI Option ROM |
| [WARN ] CBFS: 'pci1002,5940.rom' not found. |
| [DEBUG] PCI Option ROM loading disabled for PCI: 01:00.1 |
| [WARN ] PCI: 01:00.1: Missing PCI Option ROM |
| [DEBUG] ACPI: added table 2/32, length now 44 |
| [DEBUG] ACPI: * MCFG |
| [DEBUG] ACPI: * MADT |
| [DEBUG] current = 17f789b0 |
| [DEBUG] ACPI: * HPET |
| [DEBUG] ACPI: added table 3/32, length now 48 |
| [WARN ] CBFS: 'pci1002,5960.rom' not found. |
| [DEBUG] PCI Option ROM loading disabled for PCI: 01:00.0 |
| [ERROR] pci_rom_acpi_fill_vfct failed |
| [INFO ] ACPI: done. |
| [DEBUG] ACPI tables: 6640 bytes. |
| [DEBUG] smbios_write_tables: 17f6f000 |
| [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.19-1111-g177e135136' |
| [DEBUG] SMBIOS: Unknown CPU or CPU doesn't support Deterministic Cache CPUID leaf |
| [DEBUG] SMBIOS tables: 359 bytes. |
| [DEBUG] Writing table forward entry at 0x00000500 |
| [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 27e5 |
| [DEBUG] Writing coreboot table at 0x17f9c000 |
| [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| [DEBUG] 1. 0000000000001000-000000000009ffff: RAM |
| [DEBUG] 2. 00000000000c0000-0000000017f6efff: RAM |
| [DEBUG] 3. 0000000017f6f000-0000000017fa4fff: CONFIGURATION TABLES |
| [DEBUG] 4. 0000000017fa5000-0000000017fcefff: RAMSTAGE |
| [DEBUG] 5. 0000000017fcf000-0000000017ffffff: CONFIGURATION TABLES |
| [DEBUG] 6. 00000000fec00000-00000000fec00fff: RESERVED |
| [DEBUG] 7. 00000000ff800000-00000000ffffffff: RESERVED |
| [DEBUG] Wrote coreboot table at: 0x17f9c000, 0x2a8 bytes, checksum 89f9 |
| [DEBUG] coreboot table: 704 bytes. |
| [DEBUG] IMD ROOT 0. 0x17fff000 0x00001000 |
| [DEBUG] IMD SMALL 1. 0x17ffe000 0x00001000 |
| [DEBUG] CONSOLE 2. 0x17fde000 0x00020000 |
| [DEBUG] TIME STAMP 3. 0x17fdd000 0x00000910 |
| [DEBUG] AFTER CAR 4. 0x17fcf000 0x0000e000 |
| [DEBUG] RAMSTAGE 5. 0x17fa4000 0x0002b000 |
| [DEBUG] COREBOOT 6. 0x17f9c000 0x00008000 |
| [DEBUG] IRQ TABLE 7. 0x17f9b000 0x00001000 |
| [DEBUG] ACPI 8. 0x17f77000 0x00024000 |
| [DEBUG] SMBIOS 9. 0x17f6f000 0x00008000 |
| [DEBUG] IMD small region: |
| [DEBUG] IMD ROOT 0. 0x17ffec00 0x00000400 |
| [DEBUG] FMAP 1. 0x17ffeb40 0x000000b6 |
| [DEBUG] ROMSTG STCK 2. 0x17ffeaa0 0x00000088 |
| [INFO ] Timestamp - finalize chips: 1515985189 |
| [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 8 / 300 ms |
| [INFO ] Timestamp - starting to load payload: 1523551807 |
| [INFO ] CBFS: Found 'fallback/payload' @0x26d00 size 0x11bf4 |
| [DEBUG] Checking segment from ROM address 0xfffe6f2c |
| [DEBUG] Checking segment from ROM address 0xfffe6f48 |
| [DEBUG] Loading segment from ROM address 0xfffe6f2c |
| [DEBUG] code (compression=1) |
| [DEBUG] New segment dstaddr 0x000de6c0 memsize 0x21940 srcaddr 0xfffe6f64 filesize 0x11bbc |
| [DEBUG] Loading Segment: addr: 0x000de6c0 memsz: 0x0000000000021940 filesz: 0x0000000000011bbc |
| [DEBUG] using LZMA |
| [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 1557877983 |
| [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 1620009606 |
| [DEBUG] Loading segment from ROM address 0xfffe6f48 |
| [DEBUG] Entry Point 0x000fd28c |
| [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 88 / 76 ms |
| [DEBUG] Jumping to boot code at 0x000fd28c(0x17f9c000) |
| [INFO ] Timestamp - selfboot jump: 1638644688 |
| SeaBIOS (version rel-1.16.1-0-g3208b09) |
| BUILD: gcc: (coreboot toolchain v2023-02-19_17d9d897f0) 11.3.0 binutils: (GNU Binutils) 2.37 |
| Found coreboot cbmem console @ 17fde000 |
| Found mainboard ASUS P2B |
| Relocating init from 0x000dfe20 to 0x16f61a80 (size 54496) |
| Found CBFS header at 0xfffc022c |
| multiboot: eax=17fc32b8, ebx=17fc3284 |
| Found 9 PCI devices (max PCI bus is 01) |
| Copying SMBIOS from 0x17f6f000 to 0x000f61e0 |
| Copying SMBIOS 3.0 from 0x17f6f020 to 0x000f61c0 |
| Copying ACPI RSDP from 0x17f77000 to 0x000f6190 |
| Copying PIR from 0x17f9b000 to 0x000f6110 |
| table(50434146)=0x17f78800 (via xsdt) |
| Using pmtimer, ioport 0xe408 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.16.1-0-g3208b09) |
| UHCI init on dev 00:04.2 (io=2100) |
| ATA controller 1 at 1f0/3f4/0 (irq 14 dev 21) |
| ATA controller 2 at 170/374/0 (irq 15 dev 21) |
| Searching bootorder for: HALT |
| Found 1 lpt ports |
| Found 2 serial ports |
| ata1-0: SDCFXS-064G ATA-0 Hard-Disk (61064 MiBytes) |
| Searching bootorder for: /pci@i0cf8/*@4,1/drive@1/disk@0 |
| Searching bios-geometry for: /pci@i0cf8/*@4,1/drive@1/disk@0 |
| USB keyboard initialized |
| Got ps2 nak (status=51) |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f6090: PCHS=65535/16/63 translation=lba LCHS=1024/255/63 s=125059072 |
| Space available for UMB: cd000-ec800, f5a00-f6090 |
| Returned 16769024 bytes of ZoneHigh |
| e820 map has 7 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 0000000017f6d000 = 1 RAM |
| 4: 0000000017f6d000 - 0000000018000000 = 2 RESERVED |
| 5: 00000000fec00000 - 00000000fec01000 = 2 RESERVED |
| 6: 00000000ff800000 - 0000000100000000 = 2 RESERVED |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |