| |
| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| 6cd01860 |
| SRFTP [46a4] = 41f88200 |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 4 |
| PCI(0, 0, 0)[bc] = 82a00000 |
| PCI(0, 0, 0)[a8] = 7d600000 |
| PCI(0, 0, 0)[ac] = 4 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| Done memory map |
| RCOMP...done |
| COMP2 done |
| COMP1 done |
| FORCE RCOMP and wait 20us...done |
| Done io registers |
| CPE |
| CP5b |
| CP5c |
| OTHP [400c] = 8b4 |
| OTHP [440c] = 8b4 |
| t123: 1767, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| ME: Wrong mode : 2 |
| ME: FWS2: 0x100a0140 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| PASSED! Tell ME that DRAM is ready |
| ME: ME is reporting as disabled, so not waiting for a response. |
| ME: FWS2: 0x100a0140 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: No DID Ack received |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1596 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ 7ffff000 254 entries. |
| IMD: root @ 7fffec00 62 entries. |
| CBMEM entry for DIMM info: 0x7fffe880 |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1bdc0 |
| CBFS: Checking offset 1e600 |
| CBFS: File @ offset 1e600 size 3e1 |
| CBFS: Unmatched 'extensions/99-lockchip.cfg' at 1e600 |
| CBFS: Checking offset 1ea40 |
| CBFS: File @ offset 1ea40 size 1213 |
| CBFS: Unmatched 'grub.cfg' at 1ea40 |
| CBFS: Checking offset 1fcc0 |
| CBFS: File @ offset 1fcc0 size 1d8 |
| CBFS: Unmatched '' at 1fcc0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a672 |
| CBFS: Found @ offset 2ff00 size 1a672 |
| Decompressing stage fallback/ramstage @ 0x7ff8afc0 (313968 bytes) |
| Loading module at 7ff8b000 with entry 7ff8b000. filesize: 0x3a810 memsize: 0x4ca30 |
| Processing 3478 relocs. Offset value of 0x7fe8b000 |
| |
| |
| coreboot-4.6-2128-g690afa1f8c Thu Nov 16 15:27:43 UTC 2017 ramstage starting... |
| Capability: type 0x01 @ 0x50 |
| Capability: type 0x01 @ 0x50 |
| Capability: type 0x0a @ 0x58 |
| usbdebug: Failed hardware init |
| Normal boot. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/0150] ops |
| PCI: 00:00.0 [8086/0150] enabled |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| PCI: 00:01.0 subordinate bus PCI Express |
| PCI: 00:01.0 [8086/0151] enabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0162] enabled |
| PCI: 00:14.0 [8086/0000] ops |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0 [8086/1e3a] ops |
| PCI: 00:16.0 [8086/1e3a] enabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0: Disabling device |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1e10] enabled |
| PCI: 00:1c.1: Disabling device |
| PCI: 00:1c.2: Disabling device |
| PCI: 00:1c.3: Disabling device |
| PCI: 00:1c.4 [8086/0000] bus ops |
| PCI: 00:1c.4 [8086/1e18] enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfed4ba90 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1e26] enabled |
| Capability: type 0x0d @ 0x50 |
| Capability: type 0x0d @ 0x50 |
| PCI: 00:1e.0 [8086/244e] enabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1e49] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Found @ offset 1b880 size 4cc |
| PCI: 00:1f.2 [8086/1e00] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1e22] enabled |
| PCI: 00:1f.4: Disabling device |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:01.0 scanning... |
| do_pci_scan_bridge for PCI: 00:01.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3a30 |
| memalign 7ffd3a30 |
| PCI: pci_scan_bus for bus 01 |
| scan_bus: scanning of bus PCI: 00:01.0 took 19 usecs |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3a54 |
| memalign 7ffd3a58 |
| PCI: pci_scan_bus for bus 02 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 55 usecs |
| PCI: 00:1c.4 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.4 |
| PCI: pci_scan_bus for bus 03 |
| PCI: 03:00.0 [10ec/8168] enabled |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Failed to enable LTR for dev = PCI: 03:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.4 took 223 usecs |
| PCI: 00:1e.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1e.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3a7c |
| memalign 7ffd3a80 |
| PCI: pci_scan_bus for bus 04 |
| scan_bus: scanning of bus PCI: 00:1e.0 took 48 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| memalign Enter, boundary 8, size 2560, free_mem_ptr 7ffd3aa4 |
| memalign 7ffd3aa8 |
| PNP: 002e.0 disabled |
| PNP: 002e.1 enabled |
| PNP: 002e.2 enabled |
| PNP: 002e.3 enabled |
| PNP: 002e.4 enabled |
| PNP: 002e.5 enabled |
| PNP: 002e.6 enabled |
| PNP: 002e.7 disabled |
| PNP: 002e.a disabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 195 usecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 5 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 945 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 954 usecs |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 1081 exit 0 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. |
| PCI: 00:01.0 read_resources bus 1 link: 0 |
| PCI: 00:01.0 read_resources bus 1 link: 0 done |
| PCI: 00:1a.0 EHCI BAR hook registered |
| PCI: 00:1c.0 read_resources bus 2 link: 0 |
| PCI: 00:1c.0 read_resources bus 2 link: 0 done |
| PCI: 00:1c.4 read_resources bus 3 link: 0 |
| PCI: 00:1c.4 read_resources bus 3 link: 0 done |
| More than one caller of pci_ehci_read_resources from PCI: 00:1d.0 |
| PCI: 00:1e.0 read_resources bus 4 link: 0 |
| PCI: 00:1e.0 read_resources bus 4 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1c.1 |
| PCI: 00:1c.2 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1f.0 child on link 0 PNP: 002e.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PNP: 002e.0 |
| PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| PNP: 002e.1 |
| PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.2 |
| PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.3 |
| PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60 |
| PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 |
| PNP: 002e.4 |
| PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags c0000100 index 62 |
| PNP: 002e.5 |
| PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 |
| PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 |
| PNP: 002e.6 |
| PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.7 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.a |
| PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1f.4 |
| PCI: 00:1f.5 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 03:00.0 10 * [0x0 - 0xff] io |
| PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:1f.2 20 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 10 * [0x1060 - 0x1067] io |
| PCI: 00:1f.2 18 * [0x1068 - 0x106f] io |
| PCI: 00:1f.2 14 * [0x1070 - 0x1073] io |
| PCI: 00:1f.2 1c * [0x1074 - 0x1077] io |
| DOMAIN: 0000 io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem |
| PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem |
| PCI: 00:1c.4 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem |
| PCI: 00:1c.4 24 * [0x10400000 - 0x104fffff] prefmem |
| PCI: 00:14.0 10 * [0x10500000 - 0x1050ffff] mem |
| PCI: 00:1b.0 10 * [0x10510000 - 0x10513fff] mem |
| PCI: 00:1f.2 24 * [0x10514000 - 0x105147ff] mem |
| PCI: 00:1a.0 10 * [0x10515000 - 0x105153ff] mem |
| PCI: 00:1d.0 10 * [0x10516000 - 0x105163ff] mem |
| PCI: 00:1f.3 10 * [0x10517000 - 0x105170ff] mem |
| PCI: 00:16.0 10 * [0x10518000 - 0x1051800f] mem |
| DOMAIN: 0000 mem: base: 10518010 size: 10518010 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f8000000 limit fbffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:1000 size:1078 align:12 gran:0 limit:ffff |
| PCI: 00:1c.4 1c * [0x1000 - 0x1fff] io |
| PCI: 00:02.0 20 * [0x2000 - 0x203f] io |
| PCI: 00:1f.2 20 * [0x2040 - 0x205f] io |
| PCI: 00:1f.2 10 * [0x2060 - 0x2067] io |
| PCI: 00:1f.2 18 * [0x2068 - 0x206f] io |
| PCI: 00:1f.2 14 * [0x2070 - 0x2073] io |
| PCI: 00:1f.2 1c * [0x2074 - 0x2077] io |
| DOMAIN: 0000 io: next_base: 2078 size: 1078 align: 12 gran: 0 done |
| PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.4 io: base:1000 size:1000 align:12 gran:12 limit:1fff |
| PCI: 03:00.0 10 * [0x1000 - 0x10ff] io |
| PCI: 00:1c.4 io: next_base: 1100 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1e.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1e.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:e0000000 size:10518010 align:28 gran:0 limit:f7ffffff |
| PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem |
| PCI: 00:02.0 10 * [0xf0000000 - 0xf03fffff] mem |
| PCI: 00:1c.4 24 * [0xf0400000 - 0xf04fffff] prefmem |
| PCI: 00:14.0 10 * [0xf0500000 - 0xf050ffff] mem |
| PCI: 00:1b.0 10 * [0xf0510000 - 0xf0513fff] mem |
| PCI: 00:1f.2 24 * [0xf0514000 - 0xf05147ff] mem |
| PCI: 00:1a.0 10 * [0xf0515000 - 0xf05153ff] mem |
| PCI: 00:1d.0 10 * [0xf0516000 - 0xf05163ff] mem |
| PCI: 00:1f.3 10 * [0xf0517000 - 0xf05170ff] mem |
| PCI: 00:16.0 10 * [0xf0518000 - 0xf051800f] mem |
| DOMAIN: 0000 mem: next_base: f0518010 size: 10518010 align: 28 gran: 0 done |
| PCI: 00:01.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:01.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:01.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:01.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.4 prefmem: base:f0400000 size:100000 align:20 gran:20 limit:f04fffff |
| PCI: 03:00.0 20 * [0xf0400000 - 0xf0403fff] prefmem |
| PCI: 03:00.0 18 * [0xf0404000 - 0xf0404fff] prefmem |
| PCI: 00:1c.4 prefmem: next_base: f0405000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.4 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.4 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1e.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1e.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1e.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1e.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x47d600000 TOLUD 0x82a00000 TOM 0x400000000 |
| MEBASE 0x7ffff00000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 14294M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:01.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:01.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io |
| PCI: 00:14.0 10 <- [0x00f0500000 - 0x00f050ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:16.0 10 <- [0x00f0518000 - 0x00f051800f] size 0x00000010 gran 0x04 mem64 |
| PCI: 00:1a.0 EHCI Debug Port hook triggered |
| PCI: 00:1a.0 10 <- [0x00f0515000 - 0x00f05153ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 10 <- [0x00f0515000 - 0x00f05153ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 EHCI Debug Port relocated |
| PCI: 00:1b.0 10 <- [0x00f0510000 - 0x00f0513fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem |
| PCI: 00:1c.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io |
| PCI: 00:1c.4 24 <- [0x00f0400000 - 0x00f04fffff] size 0x00100000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.4 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io |
| PCI: 03:00.0 18 <- [0x00f0404000 - 0x00f0404fff] size 0x00001000 gran 0x0c prefmem64 |
| PCI: 03:00.0 20 <- [0x00f0400000 - 0x00f0403fff] size 0x00004000 gran 0x0e prefmem64 |
| PCI: 00:1c.4 assign_resources, bus 3 link: 0 |
| PCI: 00:1d.0 10 <- [0x00f0516000 - 0x00f05163ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| PCI: 00:1e.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1e.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq |
| PNP: 002e.3 60 <- [0x0000000378 - 0x000000037b] size 0x00000004 gran 0x02 io |
| PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq |
| PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq |
| PNP: 002e.4 60 <- [0x0000000a30 - 0x0000000a37] size 0x00000008 gran 0x03 io |
| PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq |
| PNP: 002e.4 62 <- [0x0000000a20 - 0x0000000a27] size 0x00000008 gran 0x03 io |
| PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io |
| PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq |
| PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io |
| PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00f0514000 - 0x00f05147ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00f0517000 - 0x00f05170ff] size 0x00000100 gran 0x08 mem64 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 1000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base e0000000 size 10518010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 37d600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:01.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:01.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base f0000000 size 400000 align 22 gran 22 limit f03fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 20 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base f0500000 size 10000 align 16 gran 16 limit f050ffff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base f0518000 size 10 align 12 gran 4 limit f051800f flags 60000201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base f0515000 size 400 align 12 gran 10 limit f05153ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base f0510000 size 4000 align 14 gran 14 limit f0513fff flags 60000201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 00:1c.1 |
| PCI: 00:1c.2 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.4 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c |
| PCI: 00:1c.4 resource base f0400000 size 100000 align 20 gran 20 limit f04fffff flags 60081202 index 24 |
| PCI: 00:1c.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10 |
| PCI: 03:00.0 resource base f0404000 size 1000 align 12 gran 12 limit f0404fff flags 60001201 index 18 |
| PCI: 03:00.0 resource base f0400000 size 4000 align 14 gran 14 limit f0403fff flags 60001201 index 20 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base f0516000 size 400 align 12 gran 10 limit f05163ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 00:1f.0 child on link 0 PNP: 002e.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PNP: 002e.0 |
| PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| PNP: 002e.1 |
| PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.2 |
| PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.3 |
| PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags e0000100 index 60 |
| PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 |
| PNP: 002e.4 |
| PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags e0000100 index 62 |
| PNP: 002e.5 |
| PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 |
| PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 |
| PNP: 002e.6 |
| PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.7 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.a |
| PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 2070 size 4 align 2 gran 2 limit 2073 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 2074 size 4 align 2 gran 2 limit 2077 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 2040 size 20 align 5 gran 5 limit 205f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base f0514000 size 800 align 12 gran 11 limit f05147ff flags 60000200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base f0517000 size 100 align 12 gran 8 limit f05170ff flags 60000201 index 10 |
| PCI: 00:1f.4 |
| PCI: 00:1f.5 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2465 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 1458/5000 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:01.0 bridge ctrl <- 0003 |
| PCI: 00:01.0 cmd <- 00 |
| PCI: 00:02.0 subsystem <- 1458/d000 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:14.0 subsystem <- 1458/5007 |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:16.0 subsystem <- 1458/5000 |
| PCI: 00:16.0 cmd <- 02 |
| PCI: 00:1a.0 subsystem <- 1458/5006 |
| PCI: 00:1a.0 cmd <- 106 |
| PCI: 00:1b.0 subsystem <- 1458/a002 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 1458/5000 |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.4 bridge ctrl <- 0003 |
| PCI: 00:1c.4 subsystem <- 1458/5000 |
| PCI: 00:1c.4 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 1458/5006 |
| PCI: 00:1d.0 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0003 |
| PCI: 00:1e.0 cmd <- 100 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 1458/5001 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 1458/b005 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 1458/5001 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 03:00.0 subsystem <- 1458/e000 |
| PCI: 03:00.0 cmd <- 103 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 227 exit 0 |
| read 6000 from 07e4 |
| wrote 00000004 to 0890 |
| read 02040003 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 3 usecs |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 12 relocs. Offset value of 0x00038000 |
| Adjusting 00038002: 0x00000024 -> 0x00038024 |
| Adjusting 0003801d: 0x0000003c -> 0x0003803c |
| Adjusting 00038026: 0x00000024 -> 0x00038024 |
| Adjusting 00038054: 0x00000120 -> 0x00038120 |
| Adjusting 00038066: 0x000001a8 -> 0x000381a8 |
| Adjusting 0003806f: 0x00000100 -> 0x00038100 |
| Adjusting 00038077: 0x00000104 -> 0x00038104 |
| Adjusting 00038081: 0x00000110 -> 0x00038110 |
| Adjusting 0003808a: 0x00000114 -> 0x00038114 |
| Adjusting 000380ab: 0x00000118 -> 0x00038118 |
| Adjusting 000380b2: 0x0000010c -> 0x0003810c |
| Adjusting 000380b8: 0x00000108 -> 0x00038108 |
| SMM Module: stub loaded at 00038000. Will call 7ffac118(7ffd39c0) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 8001156d. filesize: 0x3658 memsize: 0x7678 |
| Processing 211 relocs. Offset value of 0x80010000 |
| Adjusting 80010592: 0x00002c2c -> 0x80012c2c |
| Adjusting 800105b1: 0x00002c2c -> 0x80012c2c |
| Adjusting 8001066e: 0x00002e76 -> 0x80012e76 |
| Adjusting 80010685: 0x00002c2c -> 0x80012c2c |
| Adjusting 800106fb: 0x00002c3c -> 0x80012c3c |
| Adjusting 8001072e: 0x00002c57 -> 0x80012c57 |
| Adjusting 80010763: 0x00002c60 -> 0x80012c60 |
| Adjusting 800107ba: 0x00002c81 -> 0x80012c81 |
| Adjusting 80010831: 0x00002c96 -> 0x80012c96 |
| Adjusting 80010868: 0x00002cb4 -> 0x80012cb4 |
| Adjusting 8001088c: 0x00002cd5 -> 0x80012cd5 |
| Adjusting 800108a5: 0x00002cf8 -> 0x80012cf8 |
| Adjusting 80010a7f: 0x00003640 -> 0x80013640 |
| Adjusting 80010a96: 0x00002d24 -> 0x80012d24 |
| Adjusting 80010aa9: 0x00003640 -> 0x80013640 |
| Adjusting 80010ab5: 0x00002eb4 -> 0x80012eb4 |
| Adjusting 80010aba: 0x00002ed1 -> 0x80012ed1 |
| Adjusting 80010abf: 0x00002ed4 -> 0x80012ed4 |
| Adjusting 80010ac4: 0x00002d30 -> 0x80012d30 |
| Adjusting 80010af7: 0x00003644 -> 0x80013644 |
| Adjusting 80010b0d: 0x00000ad3 -> 0x80010ad3 |
| Adjusting 80010b21: 0x00003644 -> 0x80013644 |
| Adjusting 80010b33: 0x00003644 -> 0x80013644 |
| Adjusting 80010b46: 0x00002d79 -> 0x80012d79 |
| Adjusting 80010b4f: 0x00002d54 -> 0x80012d54 |
| Adjusting 8001107b: 0x00002d9e -> 0x80012d9e |
| Adjusting 800112d5: 0x00003658 -> 0x80013658 |
| Adjusting 800112f7: 0x00002da5 -> 0x80012da5 |
| Adjusting 80011324: 0x00002dbe -> 0x80012dbe |
| Adjusting 8001134d: 0x00003650 -> 0x80013650 |
| Adjusting 80011367: 0x000035a0 -> 0x800135a0 |
| Adjusting 8001137b: 0x000034b9 -> 0x800134b9 |
| Adjusting 8001139a: 0x000034ea -> 0x800134ea |
| Adjusting 800113b1: 0x000034f4 -> 0x800134f4 |
| Adjusting 800113c8: 0x000034f9 -> 0x800134f9 |
| Adjusting 800113df: 0x00003502 -> 0x80013502 |
| Adjusting 800113f6: 0x0000350f -> 0x8001350f |
| Adjusting 8001140d: 0x0000351b -> 0x8001351b |
| Adjusting 80011424: 0x00003528 -> 0x80013528 |
| Adjusting 8001143b: 0x00003533 -> 0x80013533 |
| Adjusting 80011452: 0x0000353f -> 0x8001353f |
| Adjusting 80011469: 0x00003549 -> 0x80013549 |
| Adjusting 80011480: 0x0000354e -> 0x8001354e |
| Adjusting 80011497: 0x00003556 -> 0x80013556 |
| Adjusting 800114ae: 0x0000355d -> 0x8001355d |
| Adjusting 800114c5: 0x00003562 -> 0x80013562 |
| Adjusting 800114dc: 0x00003568 -> 0x80013568 |
| Adjusting 800114f2: 0x0000356d -> 0x8001356d |
| Adjusting 80011508: 0x00003578 -> 0x80013578 |
| Adjusting 8001151e: 0x0000357d -> 0x8001357d |
| Adjusting 80011534: 0x00003586 -> 0x80013586 |
| Adjusting 8001154a: 0x00003592 -> 0x80013592 |
| Adjusting 8001155b: 0x000032e0 -> 0x800132e0 |
| Adjusting 80011577: 0x00003658 -> 0x80013658 |
| Adjusting 80011585: 0x00003658 -> 0x80013658 |
| Adjusting 80011596: 0x00002dd0 -> 0x80012dd0 |
| Adjusting 800115aa: 0x00003648 -> 0x80013648 |
| Adjusting 800115b5: 0x00003648 -> 0x80013648 |
| Adjusting 800115c8: 0x0000365c -> 0x8001365c |
| Adjusting 800115d4: 0x00002dfd -> 0x80012dfd |
| Adjusting 800115e4: 0x0000364c -> 0x8001364c |
| Adjusting 800115ed: 0x0000364c -> 0x8001364c |
| Adjusting 8001160a: 0x0000365c -> 0x8001365c |
| Adjusting 80011613: 0x00003648 -> 0x80013648 |
| Adjusting 8001162c: 0x00003660 -> 0x80013660 |
| Adjusting 8001163c: 0x00003660 -> 0x80013660 |
| Adjusting 80011662: 0x00003660 -> 0x80013660 |
| Adjusting 800116ca: 0x00002e08 -> 0x80012e08 |
| Adjusting 800116dd: 0x00002e18 -> 0x80012e18 |
| Adjusting 8001171d: 0x00002e57 -> 0x80012e57 |
| Adjusting 80011800: 0x00002c18 -> 0x80012c18 |
| Adjusting 8001182a: 0x00002c10 -> 0x80012c10 |
| Adjusting 8001182f: 0x00002e8b -> 0x80012e8b |
| Adjusting 80011b24: 0x00003664 -> 0x80013664 |
| Adjusting 80011b53: 0x00003668 -> 0x80013668 |
| Adjusting 80011b66: 0x00003664 -> 0x80013664 |
| Adjusting 80011b89: 0x00003668 -> 0x80013668 |
| Adjusting 80011bd7: 0x00002ee9 -> 0x80012ee9 |
| Adjusting 80011c24: 0x00002ee9 -> 0x80012ee9 |
| Adjusting 80011c6e: 0x00003664 -> 0x80013664 |
| Adjusting 80011d04: 0x00002f05 -> 0x80012f05 |
| Adjusting 80011d92: 0x00002f2d -> 0x80012f2d |
| Adjusting 80011e27: 0x00003043 -> 0x80013043 |
| Adjusting 80011e6c: 0x00002f95 -> 0x80012f95 |
| Adjusting 80011e7d: 0x00002fdd -> 0x80012fdd |
| Adjusting 80011ec9: 0x00002ffd -> 0x80012ffd |
| Adjusting 80011ef9: 0x00003021 -> 0x80013021 |
| Adjusting 80011f21: 0x00002f59 -> 0x80012f59 |
| Adjusting 80011f56: 0x00002f77 -> 0x80012f77 |
| Adjusting 80011f6c: 0x00003668 -> 0x80013668 |
| Adjusting 80011fe7: 0x00003140 -> 0x80013140 |
| Adjusting 80011fec: 0x0000307c -> 0x8001307c |
| Adjusting 80012019: 0x00003084 -> 0x80013084 |
| Adjusting 80012048: 0x00002f05 -> 0x80012f05 |
| Adjusting 800120d7: 0x00002f2d -> 0x80012f2d |
| Adjusting 800120f9: 0x00003668 -> 0x80013668 |
| Adjusting 80012185: 0x00003043 -> 0x80013043 |
| Adjusting 800121ca: 0x000030ce -> 0x800130ce |
| Adjusting 800121db: 0x00002fdd -> 0x80012fdd |
| Adjusting 800121fb: 0x00003668 -> 0x80013668 |
| Adjusting 8001222f: 0x00003115 -> 0x80013115 |
| Adjusting 80012274: 0x00002f59 -> 0x80012f59 |
| Adjusting 8001229f: 0x000030a7 -> 0x800130a7 |
| Adjusting 80012368: 0x00003650 -> 0x80013650 |
| Adjusting 80012377: 0x00003151 -> 0x80013151 |
| Adjusting 80012395: 0x0000315c -> 0x8001315c |
| Adjusting 800123b2: 0x00003164 -> 0x80013164 |
| Adjusting 800123c9: 0x0000316a -> 0x8001316a |
| Adjusting 800123e0: 0x00003172 -> 0x80013172 |
| Adjusting 800123f7: 0x00003178 -> 0x80013178 |
| Adjusting 8001240e: 0x0000317d -> 0x8001317d |
| Adjusting 80012425: 0x00003185 -> 0x80013185 |
| Adjusting 8001243c: 0x0000318e -> 0x8001318e |
| Adjusting 80012452: 0x00003192 -> 0x80013192 |
| Adjusting 80012468: 0x0000319b -> 0x8001319b |
| Adjusting 8001247e: 0x000031a4 -> 0x800131a4 |
| Adjusting 80012494: 0x00003515 -> 0x80013515 |
| Adjusting 800124aa: 0x000031aa -> 0x800131aa |
| Adjusting 800124c0: 0x000031b0 -> 0x800131b0 |
| Adjusting 800124d6: 0x000031b7 -> 0x800131b7 |
| Adjusting 800124ec: 0x000031c0 -> 0x800131c0 |
| Adjusting 800124fd: 0x000032e0 -> 0x800132e0 |
| Adjusting 8001256e: 0x00003670 -> 0x80013670 |
| Adjusting 800125a5: 0x000031d1 -> 0x800131d1 |
| Adjusting 800125c4: 0x000031df -> 0x800131df |
| Adjusting 800125da: 0x000031fc -> 0x800131fc |
| Adjusting 800125f9: 0x00003209 -> 0x80013209 |
| Adjusting 80012609: 0x00003216 -> 0x80013216 |
| Adjusting 80012618: 0x000031cb -> 0x800131cb |
| Adjusting 80012623: 0x000031c6 -> 0x800131c6 |
| Adjusting 8001262c: 0x00003227 -> 0x80013227 |
| Adjusting 80012646: 0x00003239 -> 0x80013239 |
| Adjusting 80012663: 0x00003650 -> 0x80013650 |
| Adjusting 8001268b: 0x00003259 -> 0x80013259 |
| Adjusting 8001269c: 0x00003650 -> 0x80013650 |
| Adjusting 800126c9: 0x0000327b -> 0x8001327b |
| Adjusting 800126e7: 0x0000326a -> 0x8001326a |
| Adjusting 800126f0: 0x00003650 -> 0x80013650 |
| Adjusting 80012702: 0x0000328c -> 0x8001328c |
| Adjusting 80012718: 0x00003650 -> 0x80013650 |
| Adjusting 8001272a: 0x000032a2 -> 0x800132a2 |
| Adjusting 80012734: 0x00003674 -> 0x80013674 |
| Adjusting 8001273e: 0x000032b7 -> 0x800132b7 |
| Adjusting 8001278a: 0x00003674 -> 0x80013674 |
| Adjusting 80012791: 0x000032e2 -> 0x800132e2 |
| Adjusting 80012796: 0x00003670 -> 0x80013670 |
| Adjusting 800127a1: 0x0000366c -> 0x8001366c |
| Adjusting 800127ab: 0x000032fc -> 0x800132fc |
| Adjusting 800127ce: 0x0000366c -> 0x8001366c |
| Adjusting 800127e8: 0x00003650 -> 0x80013650 |
| Adjusting 800127fa: 0x00003315 -> 0x80013315 |
| Adjusting 8001280c: 0x00003650 -> 0x80013650 |
| Adjusting 8001284c: 0x00003324 -> 0x80013324 |
| Adjusting 80012867: 0x0000333a -> 0x8001333a |
| Adjusting 8001287c: 0x00003650 -> 0x80013650 |
| Adjusting 8001288e: 0x00003348 -> 0x80013348 |
| Adjusting 800128a5: 0x00003650 -> 0x80013650 |
| Adjusting 800128b3: 0x0000335e -> 0x8001335e |
| Adjusting 800128cb: 0x0000336e -> 0x8001336e |
| Adjusting 800128e2: 0x00003368 -> 0x80013368 |
| Adjusting 800128f9: 0x00003373 -> 0x80013373 |
| Adjusting 80012910: 0x0000337c -> 0x8001337c |
| Adjusting 8001292b: 0x00003381 -> 0x80013381 |
| Adjusting 80012941: 0x00003389 -> 0x80013389 |
| Adjusting 80012957: 0x0000338e -> 0x8001338e |
| Adjusting 8001296d: 0x00003392 -> 0x80013392 |
| Adjusting 8001297e: 0x000032e0 -> 0x800132e0 |
| Adjusting 8001298b: 0x00003650 -> 0x80013650 |
| Adjusting 8001299c: 0x00003399 -> 0x80013399 |
| Adjusting 800129b1: 0x00003650 -> 0x80013650 |
| Adjusting 800129da: 0x000033a5 -> 0x800133a5 |
| Adjusting 800129f7: 0x00003650 -> 0x80013650 |
| Adjusting 80012a10: 0x000033b9 -> 0x800133b9 |
| Adjusting 80012a28: 0x00003598 -> 0x80013598 |
| Adjusting 80012a2d: 0x00003670 -> 0x80013670 |
| Adjusting 80012ab1: 0x00003498 -> 0x80013498 |
| Adjusting 80012ab8: 0x000033cd -> 0x800133cd |
| Adjusting 80012ac4: 0x000033e5 -> 0x800133e5 |
| Adjusting 80012ad0: 0x00003409 -> 0x80013409 |
| Adjusting 80012b25: 0x0000342d -> 0x8001342d |
| Adjusting 80012b2e: 0x00003452 -> 0x80013452 |
| Adjusting 80012b3c: 0x00003650 -> 0x80013650 |
| Adjusting 80012b6f: 0x00003476 -> 0x80013476 |
| Adjusting 80012b80: 0x00003650 -> 0x80013650 |
| Adjusting 80012bac: 0x00003650 -> 0x80013650 |
| Adjusting 80012bc0: 0x000034b0 -> 0x800134b0 |
| Adjusting 80012bcc: 0x00003670 -> 0x80013670 |
| Adjusting 80012be3: 0x00003650 -> 0x80013650 |
| Adjusting 80012c10: 0x00002bf8 -> 0x80012bf8 |
| Adjusting 80012c18: 0x0000057d -> 0x8001057d |
| Adjusting 80012c1c: 0x00002bf8 -> 0x80012bf8 |
| Adjusting 80012c24: 0x000005ee -> 0x800105ee |
| Adjusting 80012c30: 0x00002d10 -> 0x80012d10 |
| Adjusting 80012d10: 0x000008ee -> 0x800108ee |
| Adjusting 80012d14: 0x000008fa -> 0x800108fa |
| Adjusting 80012d18: 0x000008fd -> 0x800108fd |
| Adjusting 80013498: 0x00002ab5 -> 0x80012ab5 |
| Adjusting 8001349c: 0x00002ac1 -> 0x80012ac1 |
| Adjusting 800134a0: 0x00002b6c -> 0x80012b6c |
| Adjusting 800134a4: 0x00002acd -> 0x80012acd |
| Adjusting 800134a8: 0x00002b22 -> 0x80012b22 |
| Adjusting 800134ac: 0x00002b2b -> 0x80012b2b |
| Adjusting 800135b0: 0x000029c2 -> 0x800129c2 |
| Adjusting 800135b4: 0x000026ac -> 0x800126ac |
| Adjusting 800135c0: 0x0000289d -> 0x8001289d |
| Adjusting 800135c4: 0x00002360 -> 0x80012360 |
| Adjusting 800135c8: 0x0000265c -> 0x8001265c |
| Adjusting 800135cc: 0x0000287a -> 0x8001287a |
| Adjusting 800135d4: 0x00002809 -> 0x80012809 |
| Adjusting 800135d8: 0x000027e6 -> 0x800127e6 |
| Adjusting 800135f4: 0x0000250e -> 0x8001250e |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 12 relocs. Offset value of 0x80008000 |
| Adjusting 80008002: 0x00000024 -> 0x80008024 |
| Adjusting 8000801d: 0x0000003c -> 0x8000803c |
| Adjusting 80008026: 0x00000024 -> 0x80008024 |
| Adjusting 80008054: 0x00000120 -> 0x80008120 |
| Adjusting 80008066: 0x000001a8 -> 0x800081a8 |
| Adjusting 8000806f: 0x00000100 -> 0x80008100 |
| Adjusting 80008077: 0x00000104 -> 0x80008104 |
| Adjusting 80008081: 0x00000110 -> 0x80008110 |
| Adjusting 8000808a: 0x00000114 -> 0x80008114 |
| Adjusting 800080ab: 0x00000118 -> 0x80008118 |
| Adjusting 800080b2: 0x0000010c -> 0x8000810c |
| Adjusting 800080b8: 0x00000108 -> 0x80008108 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at 80006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd |
| SMM Module: stub loaded at 80008000. Will call 8001156d(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: PM1 |
| PM1_STS: WAK PWRBTN TMROF |
| GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 |
| ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd44a8 |
| memalign 7ffd44a8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd44c0 |
| memalign 7ffd44c0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd44d8 |
| memalign 7ffd44d8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd44f0 |
| memalign 7ffd44f0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4508 |
| memalign 7ffd4508 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4520 |
| memalign 7ffd4520 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4538 |
| memalign 7ffd4538 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4550 |
| memalign 7ffd4550 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4568 |
| memalign 7ffd4568 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4580 |
| memalign 7ffd4580 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4598 |
| memalign 7ffd4598 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45b0 |
| memalign 7ffd45b0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45c8 |
| memalign 7ffd45c8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45e0 |
| memalign 7ffd45e0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45f8 |
| memalign 7ffd45f8 |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000e0000000 size 0x60000000 type 0 |
| 0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1 |
| 0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0 |
| 0x0000000100000000 - 0x000000047d600000 size 0x37d600000 type 6 |
| MTRR addr 0x0-0x10 set to 6 type @ 0 |
| MTRR addr 0x10-0x20 set to 6 type @ 1 |
| MTRR addr 0x20-0x30 set to 6 type @ 2 |
| MTRR addr 0x30-0x40 set to 6 type @ 3 |
| MTRR addr 0x40-0x50 set to 6 type @ 4 |
| MTRR addr 0x50-0x60 set to 6 type @ 5 |
| MTRR addr 0x60-0x70 set to 6 type @ 6 |
| MTRR addr 0x70-0x80 set to 6 type @ 7 |
| MTRR addr 0x80-0x84 set to 6 type @ 8 |
| MTRR addr 0x84-0x88 set to 6 type @ 9 |
| MTRR addr 0x88-0x8c set to 6 type @ 10 |
| MTRR addr 0x8c-0x90 set to 6 type @ 11 |
| MTRR addr 0x90-0x94 set to 6 type @ 12 |
| MTRR addr 0x94-0x98 set to 6 type @ 13 |
| MTRR addr 0x98-0x9c set to 6 type @ 14 |
| MTRR addr 0x9c-0xa0 set to 6 type @ 15 |
| MTRR addr 0xa0-0xa4 set to 0 type @ 16 |
| MTRR addr 0xa4-0xa8 set to 0 type @ 17 |
| MTRR addr 0xa8-0xac set to 0 type @ 18 |
| MTRR addr 0xac-0xb0 set to 0 type @ 19 |
| MTRR addr 0xb0-0xb4 set to 0 type @ 20 |
| MTRR addr 0xb4-0xb8 set to 0 type @ 21 |
| MTRR addr 0xb8-0xbc set to 0 type @ 22 |
| MTRR addr 0xbc-0xc0 set to 0 type @ 23 |
| MTRR addr 0xc0-0xc1 set to 6 type @ 24 |
| MTRR addr 0xc1-0xc2 set to 6 type @ 25 |
| MTRR addr 0xc2-0xc3 set to 6 type @ 26 |
| MTRR addr 0xc3-0xc4 set to 6 type @ 27 |
| MTRR addr 0xc4-0xc5 set to 6 type @ 28 |
| MTRR addr 0xc5-0xc6 set to 6 type @ 29 |
| MTRR addr 0xc6-0xc7 set to 6 type @ 30 |
| MTRR addr 0xc7-0xc8 set to 6 type @ 31 |
| MTRR addr 0xc8-0xc9 set to 6 type @ 32 |
| MTRR addr 0xc9-0xca set to 6 type @ 33 |
| MTRR addr 0xca-0xcb set to 6 type @ 34 |
| MTRR addr 0xcb-0xcc set to 6 type @ 35 |
| MTRR addr 0xcc-0xcd set to 6 type @ 36 |
| MTRR addr 0xcd-0xce set to 6 type @ 37 |
| MTRR addr 0xce-0xcf set to 6 type @ 38 |
| MTRR addr 0xcf-0xd0 set to 6 type @ 39 |
| MTRR addr 0xd0-0xd1 set to 6 type @ 40 |
| MTRR addr 0xd1-0xd2 set to 6 type @ 41 |
| MTRR addr 0xd2-0xd3 set to 6 type @ 42 |
| MTRR addr 0xd3-0xd4 set to 6 type @ 43 |
| MTRR addr 0xd4-0xd5 set to 6 type @ 44 |
| MTRR addr 0xd5-0xd6 set to 6 type @ 45 |
| MTRR addr 0xd6-0xd7 set to 6 type @ 46 |
| MTRR addr 0xd7-0xd8 set to 6 type @ 47 |
| MTRR addr 0xd8-0xd9 set to 6 type @ 48 |
| MTRR addr 0xd9-0xda set to 6 type @ 49 |
| MTRR addr 0xda-0xdb set to 6 type @ 50 |
| MTRR addr 0xdb-0xdc set to 6 type @ 51 |
| MTRR addr 0xdc-0xdd set to 6 type @ 52 |
| MTRR addr 0xdd-0xde set to 6 type @ 53 |
| MTRR addr 0xde-0xdf set to 6 type @ 54 |
| MTRR addr 0xdf-0xe0 set to 6 type @ 55 |
| MTRR addr 0xe0-0xe1 set to 6 type @ 56 |
| MTRR addr 0xe1-0xe2 set to 6 type @ 57 |
| MTRR addr 0xe2-0xe3 set to 6 type @ 58 |
| MTRR addr 0xe3-0xe4 set to 6 type @ 59 |
| MTRR addr 0xe4-0xe5 set to 6 type @ 60 |
| MTRR addr 0xe5-0xe6 set to 6 type @ 61 |
| MTRR addr 0xe6-0xe7 set to 6 type @ 62 |
| MTRR addr 0xe7-0xe8 set to 6 type @ 63 |
| MTRR addr 0xe8-0xe9 set to 6 type @ 64 |
| MTRR addr 0xe9-0xea set to 6 type @ 65 |
| MTRR addr 0xea-0xeb set to 6 type @ 66 |
| MTRR addr 0xeb-0xec set to 6 type @ 67 |
| MTRR addr 0xec-0xed set to 6 type @ 68 |
| MTRR addr 0xed-0xee set to 6 type @ 69 |
| MTRR addr 0xee-0xef set to 6 type @ 70 |
| MTRR addr 0xef-0xf0 set to 6 type @ 71 |
| MTRR addr 0xf0-0xf1 set to 6 type @ 72 |
| MTRR addr 0xf1-0xf2 set to 6 type @ 73 |
| MTRR addr 0xf2-0xf3 set to 6 type @ 74 |
| MTRR addr 0xf3-0xf4 set to 6 type @ 75 |
| MTRR addr 0xf4-0xf5 set to 6 type @ 76 |
| MTRR addr 0xf5-0xf6 set to 6 type @ 77 |
| MTRR addr 0xf6-0xf7 set to 6 type @ 78 |
| MTRR addr 0xf7-0xf8 set to 6 type @ 79 |
| MTRR addr 0xf8-0xf9 set to 6 type @ 80 |
| MTRR addr 0xf9-0xfa set to 6 type @ 81 |
| MTRR addr 0xfa-0xfb set to 6 type @ 82 |
| MTRR addr 0xfb-0xfc set to 6 type @ 83 |
| MTRR addr 0xfc-0xfd set to 6 type @ 84 |
| MTRR addr 0xfd-0xfe set to 6 type @ 85 |
| MTRR addr 0xfe-0xff set to 6 type @ 86 |
| MTRR addr 0xff-0x100 set to 6 type @ 87 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/8. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0 |
| MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0 |
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x00 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 4 cores, 2 threads per core |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4610 |
| memalign 7ffd4610 |
| CPU: 0 has core 1 |
| CPU1: stack_base 7ffcc000, stack_end 7ffccff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd46a8 |
| CPU: vendor Intel device 306a9 |
| memalign 7ffd46a8 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: 0 has core 2 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x01 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #1 initialized |
| CPU2: stack_base 7ffcb000, stack_end 7ffcbff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4740 |
| memalign 7ffd4740 |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x02 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #2 initialized |
| CPU3: stack_base 7ffca000, stack_end 7ffcaff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd47d8 |
| memalign 7ffd47d8 |
| CPU: 0 has core 4 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x03 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #3 initialized |
| CPU4: stack_base 7ffc9000, stack_end 7ffc9ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 4. |
| After apic_write. |
| In relocation handler: cpu 4 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 4. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4870 |
| memalign 7ffd4870 |
| CPU: 0 has core 5 |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x04 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #4 initialized |
| CPU5: stack_base 7ffc8000, stack_end 7ffc8ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 5. |
| After apic_write. |
| In relocation handler: cpu 5 |
| New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 5. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4908 |
| memalign 7ffd4908 |
| CPU: 0 has core 6 |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x05 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #5 initialized |
| CPU6: stack_base 7ffc7000, stack_end 7ffc7ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 6. |
| After apic_write. |
| In relocation handler: cpu 6 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 6. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd49a0 |
| memalign 7ffd49a0 |
| CPU: 0 has core 7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x06 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #6 initialized |
| CPU7: stack_base 7ffc6000, stack_end 7ffc6ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 7. |
| After apic_write. |
| In relocation handler: cpu 7 |
| New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 7. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #7 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Found @ offset 15900 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x07 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #7 initialized |
| All AP CPUs stopped (534 loops) |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcda70, stack used: 1424 bytes |
| CPU1: stack: 7ffcc000 - 7ffcd000, lowest used address 7ffccc00, stack used: 1024 bytes |
| CPU2: stack: 7ffcb000 - 7ffcc000, lowest used address 7ffcbc00, stack used: 1024 bytes |
| CPU3: stack: 7ffca000 - 7ffcb000, lowest used address 7ffcac00, stack used: 1024 bytes |
| CPU4: stack: 7ffc9000 - 7ffca000, lowest used address 7ffc9c00, stack used: 1024 bytes |
| CPU5: stack: 7ffc8000 - 7ffc9000, lowest used address 7ffc8c00, stack used: 1024 bytes |
| CPU6: stack: 7ffc7000 - 7ffc8000, lowest used address 7ffc7c00, stack used: 1024 bytes |
| CPU7: stack: 7ffc6000 - 7ffc7000, lowest used address 7ffc6c00, stack used: 1024 bytes |
| CPU_CLUSTER: 0 init finished in 252933 usecs |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling Device 4. |
| Disabling PEG60. |
| Disabling Device 7. |
| Set BIOS_RESET_CPL |
| CPU TDP: 77 Watts |
| PCI: 00:00.0 init finished in 1014 usecs |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| [0.258180] HW.GFX.GMA.Initialize |
| [0.258184] HW.GFX.GMA.Registers.Read: 0x80862805 <- 0x000e5020:PCH_AUD_VID_DID |
| [0.258186] HW.GFX.GMA.Panel.Setup_PP_Sequencer |
| [0.258188] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS |
| [0.258191] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.258193] HW.GFX.GMA.Registers.Read: 0x00186904 <- 0x000c7210:PCH_PP_DIVISOR |
| [0.258194] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS |
| [0.258196] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS |
| [0.258197] HW.GFX.GMA.Registers.Write: 0x48340001 -> 0x000c7208:PCH_PP_ON_DELAYS |
| [0.258199] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS |
| [0.258201] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.258202] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.258204] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR |
| [0.258206] HW.GFX.GMA.Registers.Read: 0x00186904 <- 0x000c7210:PCH_PP_DIVISOR |
| [0.258207] HW.GFX.GMA.Registers.Write: 0x00186904 -> 0x000c7210:PCH_PP_DIVISOR |
| [0.258209] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL |
| [0.258211] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL |
| [0.258212] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL |
| [0.258214] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A |
| [0.258215] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x00064000:DDI_BUF_CTL_A |
| [0.258216] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB |
| [0.258218] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB |
| [0.258219] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B |
| [0.258220] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4100:PCH_DP_B |
| [0.258221] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL |
| [0.258223] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL |
| [0.258224] HW.GFX.GMA.Registers.Write: 0x00000013 -> 0x000c4030:SHOTPLUG_CTL |
| [0.258226] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC |
| [0.258228] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000e1150:PCH_HDMIC |
| [0.258229] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C |
| [0.258231] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000e4200:PCH_DP_C |
| [0.258232] HW.GFX.GMA.Registers.Unset_Mask: 0x00031303 !S SHOTPLUG_CTL |
| [0.258234] HW.GFX.GMA.Registers.Read: 0x00000010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.258235] HW.GFX.GMA.Registers.Write: 0x00000010 -> 0x000c4030:SHOTPLUG_CTL |
| [0.258237] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID |
| [0.258239] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000e1160:PCH_HDMID |
| [0.258240] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D |
| [0.258242] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000e4300:PCH_DP_D |
| [0.258243] HW.GFX.GMA.Registers.Unset_Mask: 0x00130303 !S SHOTPLUG_CTL |
| [0.258245] HW.GFX.GMA.Registers.Read: 0x00000010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.258246] HW.GFX.GMA.Registers.Write: 0x00000010 -> 0x000c4030:SHOTPLUG_CTL |
| [0.258349] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S VGACNTRL |
| [0.258351] HW.GFX.GMA.Registers.Read: 0x00002900 <- 0x00041000:VGACNTRL |
| [0.258352] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:VGACNTRL |
| [0.258353] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL |
| [0.258356] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.258359] HW.GFX.GMA.Registers.Set_Mask: 0x00004000 .S PCH_DREF_CONTROL |
| [0.258361] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.258362] HW.GFX.GMA.Registers.Write: 0x00005402 -> 0x000c6200:PCH_DREF_CONTROL |
| [0.258365] HW.GFX.GMA.Registers.Read: 0x00005402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.258387] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ |
| [0.258389] HW.GFX.GMA.Registers.Read: 0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ |
| [0.258390] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ |
| [0.258392] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.258393] HW.GFX.GMA.I2C.I2C_Read |
| [0.258393] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.258394] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.258397] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 |
| [0.258398] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 |
| [0.258400] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.258402] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.258404] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.258406] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.258949] HW.GFX.GMA.Registers.Read: 0x00008a04 <- 0x000c5108:PCH_GMBUS2 |
| [0.258951] HW.GFX.GMA.Registers.Read: 0xffffff00 <- 0x000c510c:PCH_GMBUS3 |
| [0.258952] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.259237] HW.GFX.GMA.Registers.Read: 0x00008a08 <- 0x000c5108:PCH_GMBUS2 |
| [0.259239] HW.GFX.GMA.Registers.Read: 0x00ffffff <- 0x000c510c:PCH_GMBUS3 |
| [0.259240] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.259520] HW.GFX.GMA.Registers.Read: 0x00008a0c <- 0x000c5108:PCH_GMBUS2 |
| [0.259522] HW.GFX.GMA.Registers.Read: 0xa0a4ac10 <- 0x000c510c:PCH_GMBUS3 |
| [0.259523] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.259798] HW.GFX.GMA.Registers.Read: 0x00008a10 <- 0x000c5108:PCH_GMBUS2 |
| [0.259800] HW.GFX.GMA.Registers.Read: 0x3854394c <- 0x000c510c:PCH_GMBUS3 |
| [0.259801] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.260080] HW.GFX.GMA.Registers.Read: 0x00008a14 <- 0x000c5108:PCH_GMBUS2 |
| [0.260082] HW.GFX.GMA.Registers.Read: 0x03011a02 <- 0x000c510c:PCH_GMBUS3 |
| [0.260083] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.260360] HW.GFX.GMA.Registers.Read: 0x00008a18 <- 0x000c5108:PCH_GMBUS2 |
| [0.260362] HW.GFX.GMA.Registers.Read: 0x781e3580 <- 0x000c510c:PCH_GMBUS3 |
| [0.260363] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.260645] HW.GFX.GMA.Registers.Read: 0x00008a1c <- 0x000c5108:PCH_GMBUS2 |
| [0.260647] HW.GFX.GMA.Registers.Read: 0xa7757eee <- 0x000c510c:PCH_GMBUS3 |
| [0.260648] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.260930] HW.GFX.GMA.Registers.Read: 0x00008a20 <- 0x000c5108:PCH_GMBUS2 |
| [0.260932] HW.GFX.GMA.Registers.Read: 0x279c5255 <- 0x000c510c:PCH_GMBUS3 |
| [0.260933] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.261210] HW.GFX.GMA.Registers.Read: 0x00008a24 <- 0x000c5108:PCH_GMBUS2 |
| [0.261212] HW.GFX.GMA.Registers.Read: 0xa554500f <- 0x000c510c:PCH_GMBUS3 |
| [0.261213] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.261498] HW.GFX.GMA.Registers.Read: 0x00008a28 <- 0x000c5108:PCH_GMBUS2 |
| [0.261500] HW.GFX.GMA.Registers.Read: 0x4f71004b <- 0x000c510c:PCH_GMBUS3 |
| [0.261501] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.261781] HW.GFX.GMA.Registers.Read: 0x00008a2c <- 0x000c5108:PCH_GMBUS2 |
| [0.261783] HW.GFX.GMA.Registers.Read: 0xc0a98081 <- 0x000c510c:PCH_GMBUS3 |
| [0.261784] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.262063] HW.GFX.GMA.Registers.Read: 0x00008a30 <- 0x000c5108:PCH_GMBUS2 |
| [0.262065] HW.GFX.GMA.Registers.Read: 0xc0d140a9 <- 0x000c510c:PCH_GMBUS3 |
| [0.262066] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.262348] HW.GFX.GMA.Registers.Read: 0x00008a34 <- 0x000c5108:PCH_GMBUS2 |
| [0.262350] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x000c510c:PCH_GMBUS3 |
| [0.262351] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.262631] HW.GFX.GMA.Registers.Read: 0x00008a38 <- 0x000c5108:PCH_GMBUS2 |
| [0.262633] HW.GFX.GMA.Registers.Read: 0x3a020101 <- 0x000c510c:PCH_GMBUS3 |
| [0.262634] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.262909] HW.GFX.GMA.Registers.Read: 0x00008a3c <- 0x000c5108:PCH_GMBUS2 |
| [0.262911] HW.GFX.GMA.Registers.Read: 0x38711880 <- 0x000c510c:PCH_GMBUS3 |
| [0.262912] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.263189] HW.GFX.GMA.Registers.Read: 0x00008a40 <- 0x000c5108:PCH_GMBUS2 |
| [0.263191] HW.GFX.GMA.Registers.Read: 0x2c58402d <- 0x000c510c:PCH_GMBUS3 |
| [0.263192] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.263474] HW.GFX.GMA.Registers.Read: 0x00008a44 <- 0x000c5108:PCH_GMBUS2 |
| [0.263476] HW.GFX.GMA.Registers.Read: 0x280f0045 <- 0x000c510c:PCH_GMBUS3 |
| [0.263477] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.263754] HW.GFX.GMA.Registers.Read: 0x00008a48 <- 0x000c5108:PCH_GMBUS2 |
| [0.263756] HW.GFX.GMA.Registers.Read: 0x1e000021 <- 0x000c510c:PCH_GMBUS3 |
| [0.263757] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264041] HW.GFX.GMA.Registers.Read: 0x00008a4c <- 0x000c5108:PCH_GMBUS2 |
| [0.264043] HW.GFX.GMA.Registers.Read: 0xff000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.264044] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264326] HW.GFX.GMA.Registers.Read: 0x00008a50 <- 0x000c5108:PCH_GMBUS2 |
| [0.264328] HW.GFX.GMA.Registers.Read: 0x57433400 <- 0x000c510c:PCH_GMBUS3 |
| [0.264329] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264614] HW.GFX.GMA.Registers.Read: 0x00008a54 <- 0x000c5108:PCH_GMBUS2 |
| [0.264616] HW.GFX.GMA.Registers.Read: 0x31363758 <- 0x000c510c:PCH_GMBUS3 |
| [0.264617] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264899] HW.GFX.GMA.Registers.Read: 0x00008a58 <- 0x000c5108:PCH_GMBUS2 |
| [0.264901] HW.GFX.GMA.Registers.Read: 0x39543835 <- 0x000c510c:PCH_GMBUS3 |
| [0.264902] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265181] HW.GFX.GMA.Registers.Read: 0x00008a5c <- 0x000c5108:PCH_GMBUS2 |
| [0.265183] HW.GFX.GMA.Registers.Read: 0x00000a4c <- 0x000c510c:PCH_GMBUS3 |
| [0.265184] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265466] HW.GFX.GMA.Registers.Read: 0x00008a60 <- 0x000c5108:PCH_GMBUS2 |
| [0.265468] HW.GFX.GMA.Registers.Read: 0x4400fc00 <- 0x000c510c:PCH_GMBUS3 |
| [0.265469] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265746] HW.GFX.GMA.Registers.Read: 0x00008a64 <- 0x000c5108:PCH_GMBUS2 |
| [0.265748] HW.GFX.GMA.Registers.Read: 0x204c4c45 <- 0x000c510c:PCH_GMBUS3 |
| [0.265749] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266025] HW.GFX.GMA.Registers.Read: 0x00008a68 <- 0x000c5108:PCH_GMBUS2 |
| [0.266027] HW.GFX.GMA.Registers.Read: 0x31343255 <- 0x000c510c:PCH_GMBUS3 |
| [0.266028] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266314] HW.GFX.GMA.Registers.Read: 0x00008a6c <- 0x000c5108:PCH_GMBUS2 |
| [0.266316] HW.GFX.GMA.Registers.Read: 0x200a4834 <- 0x000c510c:PCH_GMBUS3 |
| [0.266317] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266599] HW.GFX.GMA.Registers.Read: 0x00008a70 <- 0x000c5108:PCH_GMBUS2 |
| [0.266601] HW.GFX.GMA.Registers.Read: 0xfd000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.266602] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266881] HW.GFX.GMA.Registers.Read: 0x00008a74 <- 0x000c5108:PCH_GMBUS2 |
| [0.266883] HW.GFX.GMA.Registers.Read: 0x1e4c3800 <- 0x000c510c:PCH_GMBUS3 |
| [0.266884] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267166] HW.GFX.GMA.Registers.Read: 0x00008a78 <- 0x000c5108:PCH_GMBUS2 |
| [0.267168] HW.GFX.GMA.Registers.Read: 0x0a001153 <- 0x000c510c:PCH_GMBUS3 |
| [0.267169] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267445] HW.GFX.GMA.Registers.Read: 0x00008a7c <- 0x000c5108:PCH_GMBUS2 |
| [0.267447] HW.GFX.GMA.Registers.Read: 0x20202020 <- 0x000c510c:PCH_GMBUS3 |
| [0.267448] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267726] HW.GFX.GMA.Registers.Read: 0x0000ca80 <- 0x000c5108:PCH_GMBUS2 |
| [0.267728] HW.GFX.GMA.Registers.Read: 0x72012020 <- 0x000c510c:PCH_GMBUS3 |
| [0.267729] HW.GFX.GMA.Registers.Wait: 0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2 |
| [0.267731] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.267733] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 |
| [0.267755] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.267756] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.267758] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.267760] EDID+0x0000: 00 ff ff ff ff ff ff 00 10 ac a4 a0 4c 39 54 38 |
| [0.267762] EDID+0x0010: 02 1a 01 03 80 35 1e 78 ee 7e 75 a7 55 52 9c 27 |
| [0.267764] EDID+0x0020: 0f 50 54 a5 4b 00 71 4f 81 80 a9 c0 a9 40 d1 c0 |
| [0.267766] EDID+0x0030: 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c |
| [0.267768] EDID+0x0040: 45 00 0f 28 21 00 00 1e 00 00 00 ff 00 34 43 57 |
| [0.267770] EDID+0x0050: 58 37 36 31 35 38 54 39 4c 0a 00 00 00 fc 00 44 |
| [0.267772] EDID+0x0060: 45 4c 4c 20 55 32 34 31 34 48 0a 20 00 00 00 fd |
| [0.267774] EDID+0x0070: 00 38 4c 1e 53 11 00 0a 20 20 20 20 20 20 01 72 |
| [0.267776] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.267777] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.267779] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.267780] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 |
| [0.267782] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.267784] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.267785] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.267787] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268298] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268299] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.268301] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268302] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 |
| [0.268304] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.268306] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268307] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268309] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268821] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268822] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.268824] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268825] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 |
| [0.268827] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.268829] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268830] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.268832] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.269342] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.269343] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.269343] HW.GFX.GMA.I2C.I2C_Read |
| [0.269344] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.269344] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.269348] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 |
| [0.269349] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0 |
| [0.269351] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.269353] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.269355] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.269357] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.269463] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.269464] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.269464] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.269467] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| |
| [0.269469] CONFIG => |
| [0.269469] (Primary => |
| [0.269470] (Port => HDMI1 , |
| [0.269470] Framebuffer => |
| [0.269471] (Width => 1920, |
| [0.269471] Height => 1080, |
| [0.269472] Stride => 1920, |
| [0.269472] Offset => 0x00000000, |
| [0.269473] BPC => 8), |
| [0.269473] Mode => |
| [0.269474] (Dotclock => 148500000, |
| [0.269475] H_Visible => 1920, |
| [0.269476] H_Sync_Begin => 2008, |
| [0.269477] H_Sync_End => 2052, |
| [0.269478] H_Total => 2200, |
| [0.269479] V_Visible => 1080, |
| [0.269480] V_Sync_Begin => 1084, |
| [0.269481] V_Sync_End => 1089, |
| [0.269482] V_Total => 1125, |
| [0.269483] H_Sync_Active_High => True, |
| [0.269483] V_Sync_Active_High => True, |
| [0.269484] BPC => 5)), |
| [0.269485] Secondary => |
| [0.269485] (Port => Disabled, |
| [0.269486] Framebuffer => |
| [0.269486] (Width => 1, |
| [0.269487] Height => 1, |
| [0.269487] Stride => 1, |
| [0.269488] Offset => 0x00000000, |
| [0.269488] BPC => 8), |
| [0.269489] Mode => |
| [0.269489] (Dotclock => 24000000, |
| [0.269490] H_Visible => 1, |
| [0.269490] H_Sync_Begin => 1, |
| [0.269491] H_Sync_End => 1, |
| [0.269491] H_Total => 1, |
| [0.269492] V_Visible => 1, |
| [0.269492] V_Sync_Begin => 1, |
| [0.269493] V_Sync_End => 1, |
| [0.269493] V_Total => 1, |
| [0.269494] H_Sync_Active_High => False, |
| [0.269495] V_Sync_Active_High => False, |
| [0.269495] BPC => 5)), |
| [0.269496] Tertiary => |
| [0.269496] (Port => Disabled, |
| [0.269497] Framebuffer => |
| [0.269497] (Width => 1, |
| [0.269498] Height => 1, |
| [0.269498] Stride => 1, |
| [0.269499] Offset => 0x00000000, |
| [0.269499] BPC => 8), |
| [0.269500] Mode => |
| [0.269500] (Dotclock => 24000000, |
| [0.269501] H_Visible => 1, |
| [0.269501] H_Sync_Begin => 1, |
| [0.269502] H_Sync_End => 1, |
| [0.269502] H_Total => 1, |
| [0.269503] V_Visible => 1, |
| [0.269503] V_Sync_Begin => 1, |
| [0.269504] V_Sync_End => 1, |
| [0.269504] V_Total => 1, |
| [0.269505] H_Sync_Active_High => False, |
| [0.269506] V_Sync_Active_High => False, |
| [0.269506] BPC => 5))); |
| |
| [0.270891] Trying to enable port HDMI1 |
| [0.270892] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting |
| [0.270893] HW.GFX.GMA.PLLs.Alloc |
| [0.270893] HW.GFX.GMA.PLLs.On |
| [0.270949] Valid clock found. |
| [0.270949] Best/Target/Delta: 148500000/148500000/0. |
| [0.270951] HW.GFX.GMA.PLLs.Program_DPLL |
| [0.270951] HW.GFX.GMA.Registers.Write: 0x00021007 -> 0x000c6040:PCH_FPA0 |
| [0.270954] HW.GFX.GMA.Registers.Write: 0x00021007 -> 0x000c6044:PCH_FPA1 |
| [0.270956] HW.GFX.GMA.Registers.Write: 0x44020002 -> 0x000c6014:PCH_DPLL_A |
| [0.270958] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DPLL_A |
| [0.270960] HW.GFX.GMA.Registers.Read: 0x44020002 <- 0x000c6014:PCH_DPLL_A |
| [0.270961] HW.GFX.GMA.Registers.Write: 0xc4020002 -> 0x000c6014:PCH_DPLL_A |
| [0.270964] HW.GFX.GMA.Registers.Read: 0xc4020002 <- 0x000c6014:PCH_DPLL_A |
| [0.271117] HW.GFX.GMA.Connectors.Pre_On |
| [0.271118] HW.GFX.GMA.Connectors.FDI.Pre_On |
| [0.271119] HW.GFX.GMA.Registers.Write: 0x00200090 -> 0x000f0010:FDI_RX_MISC_A |
| [0.271121] HW.GFX.GMA.Registers.Write: 0x7e000000 -> 0x000f0030:FDI_RXA_TUSIZE1 |
| [0.271123] HW.GFX.GMA.Registers.Unset_Mask: 0x00000700 !S FDI_RXA_IMR |
| [0.271125] HW.GFX.GMA.Registers.Read: 0x00000fff <- 0x000f0018:FDI_RXA_IMR |
| [0.271126] HW.GFX.GMA.Registers.Write: 0x000008ff -> 0x000f0018:FDI_RXA_IMR |
| [0.271129] HW.GFX.GMA.Registers.Read: 0x000008ff <- 0x000f0018:FDI_RXA_IMR |
| [0.271130] HW.GFX.GMA.Registers.Write: 0x00000700 -> 0x000f0014:FDI_RXA_IIR |
| [0.271132] HW.GFX.GMA.Registers.Write: 0x00082840 -> 0x000f000c:FDI_RXA_CTL |
| [0.271135] HW.GFX.GMA.Registers.Read: 0x00082840 <- 0x000f000c:FDI_RXA_CTL |
| [0.271357] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S FDI_RXA_CTL |
| [0.271359] HW.GFX.GMA.Registers.Read: 0x00082840 <- 0x000f000c:FDI_RXA_CTL |
| [0.271360] HW.GFX.GMA.Registers.Write: 0x00082850 -> 0x000f000c:FDI_RXA_CTL |
| [0.271362] HW.GFX.GMA.Registers.Write: 0x000c4800 -> 0x00060100:FDI_TX_CTL_A |
| [0.271364] HW.GFX.GMA.Registers.Read: 0x000c4800 <- 0x00060100:FDI_TX_CTL_A |
| [0.271466] HW.GFX.GMA.Pipe_Setup.On |
| [0.271467] HW.GFX.GMA.Transcoder.Setup |
| [0.271467] HW.GFX.GMA.Transcoder.Setup_Link |
| [0.271468] HW.GFX.GMA.DP_Info.Calculate_M_N |
| [0.271469] HW.GFX.GMA.Registers.Write: 0x7e699999 -> 0x00060030:PIPEA_DATA_M1 |
| [0.271470] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x00060034:PIPEA_DATA_N1 |
| [0.271471] HW.GFX.GMA.Registers.Write: 0x0008cccc -> 0x00060040:PIPEA_LINK_M1 |
| [0.271472] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x00060044:PIPEA_LINK_N1 |
| [0.271473] HW.GFX.GMA.Registers.Write: 0x0897077f -> 0x00060000:HTOTAL_A |
| [0.271474] HW.GFX.GMA.Registers.Write: 0x0897077f -> 0x00060004:HBLANK_A |
| [0.271475] HW.GFX.GMA.Registers.Write: 0x080307d7 -> 0x00060008:HSYNC_A |
| [0.271476] HW.GFX.GMA.Registers.Write: 0x04640437 -> 0x0006000c:VTOTAL_A |
| [0.271477] HW.GFX.GMA.Registers.Write: 0x04640437 -> 0x00060010:VBLANK_A |
| [0.271478] HW.GFX.GMA.Registers.Write: 0x0440043b -> 0x00060014:VSYNC_A |
| [0.271479] HW.GFX.GMA.Pipe_Setup.Setup_Display |
| [0.271479] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane |
| [0.271481] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DSPACNTR |
| [0.271482] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070180:DSPACNTR |
| [0.271483] HW.GFX.GMA.Registers.Write: 0x98004000 -> 0x00070180:DSPACNTR |
| [0.271484] HW.GFX.GMA.Registers.Write: 0x00001e00 -> 0x00070188:DSPASTRIDE |
| [0.271485] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF |
| [0.271486] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070184:DSPALINOFF |
| [0.271487] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF |
| [0.271488] HW.GFX.GMA.Registers.Write: 0x077f0437 -> 0x0006001c:PIPEASRC |
| [0.271489] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00070008:PIPEACONF |
| [0.271490] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00070008:PIPEACONF |
| [0.271491] HW.GFX.GMA.Connectors.Post_On |
| [0.271491] HW.GFX.GMA.Connectors.FDI.Post_On |
| [0.271492] HW.GFX.GMA.Connectors.FDI.Auto_Training |
| [0.271493] HW.GFX.GMA.Registers.Unset_And_Set_Mask: FDI_TX_CTL_A |
| [0.271494] HW.GFX.GMA.Registers.Read: 0x000c4800 <- 0x00060100:FDI_TX_CTL_A |
| [0.271495] HW.GFX.GMA.Registers.Write: 0x800c4c00 -> 0x00060100:FDI_TX_CTL_A |
| [0.271496] HW.GFX.GMA.Registers.Read: 0x800c4c00 <- 0x00060100:FDI_TX_CTL_A |
| [0.271497] HW.GFX.GMA.Registers.Set_Mask: 0x80000400 .S FDI_RXA_CTL |
| [0.271499] HW.GFX.GMA.Registers.Read: 0x00082850 <- 0x000f000c:FDI_RXA_CTL |
| [0.271500] HW.GFX.GMA.Registers.Write: 0x80082c50 -> 0x000f000c:FDI_RXA_CTL |
| [0.271503] HW.GFX.GMA.Registers.Read: 0x80082c50 <- 0x000f000c:FDI_RXA_CTL |
| [0.271510] HW.GFX.GMA.Registers.Is_Set_Mask: FDI_TX_CTL_A |
| [0.271511] HW.GFX.GMA.Registers.Read: 0x800c4c02 <- 0x00060100:FDI_TX_CTL_A |
| [0.271512] HW.GFX.GMA.Registers.Set_Mask: 0x0c000000 .S FDI_RXA_CTL |
| [0.271514] HW.GFX.GMA.Registers.Read: 0x80082c50 <- 0x000f000c:FDI_RXA_CTL |
| [0.271515] HW.GFX.GMA.Registers.Write: 0x8c082c50 -> 0x000f000c:FDI_RXA_CTL |
| [0.271517] HW.GFX.GMA.PCH.Transcoder.On |
| [0.271517] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DPLL_SEL |
| [0.271519] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7000:PCH_DPLL_SEL |
| [0.271520] HW.GFX.GMA.Registers.Write: 0x00000008 -> 0x000c7000:PCH_DPLL_SEL |
| [0.271522] HW.GFX.GMA.Registers.Write: 0x0897077f -> 0x000e0000:TRANS_HTOTAL_A |
| [0.271524] HW.GFX.GMA.Registers.Write: 0x0897077f -> 0x000e0004:TRANS_HBLANK_A |
| [0.271526] HW.GFX.GMA.Registers.Write: 0x080307d7 -> 0x000e0008:TRANS_HSYNC_A |
| [0.271528] HW.GFX.GMA.Registers.Write: 0x04640437 -> 0x000e000c:TRANS_VTOTAL_A |
| [0.271530] HW.GFX.GMA.Registers.Write: 0x04640437 -> 0x000e0010:TRANS_VBLANK_A |
| [0.271532] HW.GFX.GMA.Registers.Write: 0x0440043b -> 0x000e0014:TRANS_VSYNC_A |
| [0.271534] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S TRANSA_CHICKEN2 |
| [0.271536] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000f0064:TRANSA_CHICKEN2 |
| [0.271537] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0064:TRANSA_CHICKEN2 |
| [0.271539] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0008:TRANSACONF |
| [0.271541] HW.GFX.GMA.PCH.HDMI.On |
| [0.271541] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_HDMIB |
| [0.271544] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB |
| [0.271545] HW.GFX.GMA.Registers.Write: 0x8000081c -> 0x000e1140:PCH_HDMIB |
| [0.271547] Enabled port HDMI1 |
| PCI: 00:02.0 init finished in 13773 usecs |
| PCI: 00:14.0 init ... |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 6 usecs |
| PCI: 00:16.0 init ... |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| intel_me_path: mbp is not ready! |
| ME: BIOS path: Error |
| PCI: 00:16.0 init finished in 21 usecs |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 12 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: base = f0510000 |
| Azalia: codec_mask = 0c |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: No verb! |
| Azalia: Initializing codec #2 |
| Azalia: codec viddid: 10ec0887 |
| Azalia: verb_size: 56 |
| PCI: 00:1b.0 init finished in 4178 usecs |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 10 usecs |
| PCI: 00:1c.4 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.4 init finished in 8 usecs |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 12 usecs |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Found @ offset 1b880 size 4cc |
| Set power on after power failure. |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Found @ offset 1b880 size 4cc |
| NMI sources enabled. |
| PantherPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 1372 usecs |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Found @ offset 1b880 size 4cc |
| SATA: Controller in AHCI mode. |
| ABAR: f0514000 |
| PCI: 00:1f.2 init finished in 448 usecs |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 0 usecs |
| PNP: 002e.1 init ... |
| PNP: 002e.1 init finished in 0 usecs |
| PNP: 002e.2 init ... |
| PNP: 002e.2 init finished in 0 usecs |
| PNP: 002e.3 init ... |
| PNP: 002e.3 init finished in 0 usecs |
| PNP: 002e.4 init ... |
| Unsupported thermal mode 0x0 on TMPIN1 |
| Unsupported thermal mode 0x0 on TMPIN2 |
| Unsupported thermal mode 0x0 on TMPIN3 |
| PNP: 002e.4 init finished in 22 usecs |
| PNP: 002e.5 init ... |
| PNP: 002e.5 init finished in 28 usecs |
| PNP: 002e.6 init ... |
| PNP: 002e.6 init finished in 0 usecs |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| Updating MRC cache data. |
| No MRC cache in cbmem. Can't update flash. |
| BS: BS_DEV_INIT times (us): entry 12 run 273993 exit 1 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 380 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Found @ offset 1bdc0 size 27e7 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1bdc0 |
| CBFS: Checking offset 1e600 |
| CBFS: File @ offset 1e600 size 3e1 |
| CBFS: Unmatched 'extensions/99-lockchip.cfg' at 1e600 |
| CBFS: Checking offset 1ea40 |
| CBFS: File @ offset 1ea40 size 1213 |
| CBFS: Unmatched 'grub.cfg' at 1ea40 |
| CBFS: Checking offset 1fcc0 |
| CBFS: File @ offset 1fcc0 size 1d8 |
| CBFS: Unmatched '' at 1fcc0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a672 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a5c0 |
| CBFS: File @ offset 4a5c0 size 2291c |
| CBFS: Unmatched 'img/nvramcui' at 4a5c0 |
| CBFS: Checking offset 6cf40 |
| CBFS: File @ offset 6cf40 size 8df23 |
| CBFS: Unmatched 'fallback/payload' at 6cf40 |
| CBFS: Checking offset faec0 |
| CBFS: File @ offset faec0 size 2c02c |
| CBFS: Unmatched 'img/memtest' at faec0 |
| CBFS: Checking offset 126f40 |
| CBFS: File @ offset 126f40 size 11ea |
| CBFS: Unmatched 'grubtest.cfg' at 126f40 |
| CBFS: Checking offset 128180 |
| CBFS: File @ offset 128180 size 6b7158 |
| CBFS: Unmatched '' at 128180 |
| CBFS: Checking offset 7df300 |
| CBFS: File @ offset 7df300 size bb8 |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff01000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 7fef0000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff06460 |
| ACPI: * DMAR |
| ACPI: added table 6/32, length now 60 |
| current = 7ff06510 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1bdc0 |
| CBFS: Checking offset 1e600 |
| CBFS: File @ offset 1e600 size 3e1 |
| CBFS: Unmatched 'extensions/99-lockchip.cfg' at 1e600 |
| CBFS: Checking offset 1ea40 |
| CBFS: File @ offset 1ea40 size 1213 |
| CBFS: Unmatched 'grub.cfg' at 1ea40 |
| CBFS: Checking offset 1fcc0 |
| CBFS: File @ offset 1fcc0 size 1d8 |
| CBFS: Unmatched '' at 1fcc0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a672 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a5c0 |
| CBFS: File @ offset 4a5c0 size 2291c |
| CBFS: Unmatched 'img/nvramcui' at 4a5c0 |
| CBFS: Checking offset 6cf40 |
| CBFS: File @ offset 6cf40 size 8df23 |
| CBFS: Unmatched 'fallback/payload' at 6cf40 |
| CBFS: Checking offset faec0 |
| CBFS: File @ offset faec0 size 2c02c |
| CBFS: Unmatched 'img/memtest' at faec0 |
| CBFS: Checking offset 126f40 |
| CBFS: File @ offset 126f40 size 11ea |
| CBFS: Unmatched 'grubtest.cfg' at 126f40 |
| CBFS: Checking offset 128180 |
| CBFS: File @ offset 128180 size 6b7158 |
| CBFS: Unmatched '' at 128180 |
| CBFS: Checking offset 7df300 |
| CBFS: File @ offset 7df300 size bb8 |
| CBFS: 'vbt.bin' not found. |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'pci8086,0162.rom' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1bdc0 |
| CBFS: Checking offset 1e600 |
| CBFS: File @ offset 1e600 size 3e1 |
| CBFS: Unmatched 'extensions/99-lockchip.cfg' at 1e600 |
| CBFS: Checking offset 1ea40 |
| CBFS: File @ offset 1ea40 size 1213 |
| CBFS: Unmatched 'grub.cfg' at 1ea40 |
| CBFS: Checking offset 1fcc0 |
| CBFS: File @ offset 1fcc0 size 1d8 |
| CBFS: Unmatched '' at 1fcc0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a672 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a5c0 |
| CBFS: File @ offset 4a5c0 size 2291c |
| CBFS: Unmatched 'img/nvramcui' at 4a5c0 |
| CBFS: Checking offset 6cf40 |
| CBFS: File @ offset 6cf40 size 8df23 |
| CBFS: Unmatched 'fallback/payload' at 6cf40 |
| CBFS: Checking offset faec0 |
| CBFS: File @ offset faec0 size 2c02c |
| CBFS: Unmatched 'img/memtest' at faec0 |
| CBFS: Checking offset 126f40 |
| CBFS: File @ offset 126f40 size 11ea |
| CBFS: Unmatched 'grubtest.cfg' at 126f40 |
| CBFS: Checking offset 128180 |
| CBFS: File @ offset 128180 size 6b7158 |
| CBFS: Unmatched '' at 128180 |
| CBFS: Checking offset 7df300 |
| CBFS: File @ offset 7df300 size bb8 |
| CBFS: 'pci8086,0162.rom' not found. |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'pci8086,0106.rom' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1bdc0 |
| CBFS: Checking offset 1e600 |
| CBFS: File @ offset 1e600 size 3e1 |
| CBFS: Unmatched 'extensions/99-lockchip.cfg' at 1e600 |
| CBFS: Checking offset 1ea40 |
| CBFS: File @ offset 1ea40 size 1213 |
| CBFS: Unmatched 'grub.cfg' at 1ea40 |
| CBFS: Checking offset 1fcc0 |
| CBFS: File @ offset 1fcc0 size 1d8 |
| CBFS: Unmatched '' at 1fcc0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a672 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a5c0 |
| CBFS: File @ offset 4a5c0 size 2291c |
| CBFS: Unmatched 'img/nvramcui' at 4a5c0 |
| CBFS: Checking offset 6cf40 |
| CBFS: File @ offset 6cf40 size 8df23 |
| CBFS: Unmatched 'fallback/payload' at 6cf40 |
| CBFS: Checking offset faec0 |
| CBFS: File @ offset faec0 size 2c02c |
| CBFS: Unmatched 'img/memtest' at faec0 |
| CBFS: Checking offset 126f40 |
| CBFS: File @ offset 126f40 size 11ea |
| CBFS: Unmatched 'grubtest.cfg' at 126f40 |
| CBFS: Checking offset 128180 |
| CBFS: File @ offset 128180 size 6b7158 |
| CBFS: Unmatched '' at 128180 |
| CBFS: Checking offset 7df300 |
| CBFS: File @ offset 7df300 size bb8 |
| CBFS: 'pci8086,0106.rom' not found. |
| PCI Option ROM loading disabled for PCI: 00:02.0 |
| GMA: locate_vbt_vbios: 220c 4229 85 99 98 |
| GMA: VBT couldn't be found |
| ACPI: * HPET |
| ACPI: added table 7/32, length now 64 |
| ACPI: done. |
| ACPI tables: 21840 bytes. |
| smbios_write_tables: 7feef000 |
| Create SMBIOS type 17 |
| Root Device (GIGABYTE GA-B75M-D3V) |
| CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| APIC: 00 (unknown) |
| APIC: acac (Intel SandyBridge/IvyBridge CPU) |
| DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 03:00.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PNP: 002e.0 (ITE IT8728F Super I/O) |
| PNP: 002e.1 (ITE IT8728F Super I/O) |
| PNP: 002e.2 (ITE IT8728F Super I/O) |
| PNP: 002e.3 (ITE IT8728F Super I/O) |
| PNP: 002e.4 (ITE IT8728F Super I/O) |
| PNP: 002e.5 (ITE IT8728F Super I/O) |
| PNP: 002e.6 (ITE IT8728F Super I/O) |
| PNP: 002e.7 (ITE IT8728F Super I/O) |
| PNP: 002e.a (ITE IT8728F Super I/O) |
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| APIC: 01 (unknown) |
| APIC: 02 (unknown) |
| APIC: 03 (unknown) |
| APIC: 04 (unknown) |
| APIC: 05 (unknown) |
| APIC: 06 (unknown) |
| APIC: 07 (unknown) |
| SMBIOS tables: 550 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 2fec |
| Writing coreboot table at 0x7ff25000 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Found @ offset 1b880 size 4cc |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4a38 |
| memalign 7ffd4a38 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4a50 |
| memalign 7ffd4a50 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4a68 |
| memalign 7ffd4a68 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4a80 |
| memalign 7ffd4a80 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4a98 |
| memalign 7ffd4a98 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4ab0 |
| memalign 7ffd4ab0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4ac8 |
| memalign 7ffd4ac8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4ae0 |
| memalign 7ffd4ae0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4af8 |
| memalign 7ffd4af8 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007feeefff: RAM |
| 4. 000000007feef000-000000007fffffff: CONFIGURATION TABLES |
| 5. 0000000080000000-00000000829fffff: RESERVED |
| 6. 00000000f8000000-00000000fbffffff: RESERVED |
| 7. 00000000fed90000-00000000fed91fff: RESERVED |
| 8. 0000000100000000-000000047d5fffff: RAM |
| read e008 from 07e4 |
| wrote 00000004 to 0890 |
| read 02040003 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| read 0080 from 0870 |
| wrote 000c to 0870 |
| read 05030201 from 0878 |
| read 0bd89f20 from 087c |
| read b32d from 0876 |
| read 5006 from 0874 |
| wrote 00000000 to 07e8 |
| wrote 4456 to 0871 |
| read 5481 from 0870 |
| read 5484 from 0870 |
| wrote 0004 to 0870 |
| read c21720c2 from 07f0 |
| read 20 from 07f4 |
| wrote 0000 to 0874 |
| SF: Got idcode: c2 20 17 c2 20 |
| Manufacturer: c2 |
| SF: Detected MX25L6405D with sector size 0x1000, total 0x800000 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| FMAP: Found "FLASH" version 1.1 at 20000. |
| FMAP: base = ff800000 size = 800000 #areas = 3 |
| Wrote coreboot table at: 7ff25000, 0x888 bytes, checksum dcef |
| coreboot table: 2208 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| TIME STAMP 3. 7ffdd000 00000400 |
| ROMSTG STCK 4. 7ffd8000 00005000 |
| RAMSTAGE 5. 7ff8a000 0004e000 |
| 57a9e100 6. 7ff3d000 0004ca30 |
| SMM BACKUP 7. 7ff2d000 00010000 |
| COREBOOT 8. 7ff25000 00008000 |
| ACPI 9. 7ff01000 00024000 |
| ACPI GNVS 10. 7ff00000 00001000 |
| TCPA LOG 11. 7fef0000 00010000 |
| SMBIOS 12. 7feef000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| CAR GLOBALS 1. 7fffea40 000001c0 |
| USBDEBUG 2. 7fffe9e0 00000058 |
| MEM INFO 3. 7fffe880 00000141 |
| ROMSTAGE 4. 7fffe860 00000004 |
| 57a9e000 5. 7fffe840 00000018 |
| COREBOOTFWD 6. 7fffe800 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 6840 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 157e4 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 15900 |
| CBFS: File @ offset 15900 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 15900 |
| CBFS: Checking offset 1b180 |
| CBFS: File @ offset 1b180 size 308 |
| CBFS: Unmatched 'config' at 1b180 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 240 |
| CBFS: Unmatched 'revision' at 1b4c0 |
| CBFS: Checking offset 1b740 |
| CBFS: File @ offset 1b740 size 100 |
| CBFS: Unmatched 'cmos.default' at 1b740 |
| CBFS: Checking offset 1b880 |
| CBFS: File @ offset 1b880 size 4cc |
| CBFS: Unmatched 'cmos_layout.bin' at 1b880 |
| CBFS: Checking offset 1bdc0 |
| CBFS: File @ offset 1bdc0 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1bdc0 |
| CBFS: Checking offset 1e600 |
| CBFS: File @ offset 1e600 size 3e1 |
| CBFS: Unmatched 'extensions/99-lockchip.cfg' at 1e600 |
| CBFS: Checking offset 1ea40 |
| CBFS: File @ offset 1ea40 size 1213 |
| CBFS: Unmatched 'grub.cfg' at 1ea40 |
| CBFS: Checking offset 1fcc0 |
| CBFS: File @ offset 1fcc0 size 1d8 |
| CBFS: Unmatched '' at 1fcc0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a672 |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a5c0 |
| CBFS: File @ offset 4a5c0 size 2291c |
| CBFS: Unmatched 'img/nvramcui' at 4a5c0 |
| CBFS: Checking offset 6cf40 |
| CBFS: File @ offset 6cf40 size 8df23 |
| CBFS: Found @ offset 6cf40 size 8df23 |
| Loading segment from ROM address 0xff88d078 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4b10 |
| memalign 7ffd4b10 |
| New segment dstaddr 0x8200 memsize 0x17824 srcaddr 0xff88d0cc filesize 0x83b7 |
| Loading segment from ROM address 0xff88d094 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4b2c |
| memalign 7ffd4b30 |
| New segment dstaddr 0x100000 memsize 0x2059e0 srcaddr 0xff895483 filesize 0x85b18 |
| Loading segment from ROM address 0xff88d0b0 |
| Entry Point 0x00008200 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b4c |
| memalign 7ffd4b50 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b68 |
| memalign 7ffd4b68 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b80 |
| memalign 7ffd4b80 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| lb: [0x000000007ff8b000, 0x000000007ffd7a30) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| using LZMA |
| [ 0x00008200, 00017feb, 0x0001fa24) <- ff88d0cc |
| Clearing Segment: addr: 0x0000000000017feb memsz: 0x0000000000007a39 |
| dest 00008200, end 0001fa24, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000002059e0 filesz: 0x0000000000085b18 |
| lb: [0x000000007ff8b000, 0x000000007ffd7a30) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x00000000002059e0 filesz: 0x0000000000085b18 |
| using LZMA |
| [ 0x00100000, 003059e0, 0x003059e0) <- ff895483 |
| dest 00100000, end 003059e0, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 180002 exit 0 |
| PCH watchdog disabled |
| Jumping to boot code at 00008200(7ff25000) |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcd880, stack used: 1920 bytes |
| error: file `/background.jpg' not found. |
|
error: file `/dejavusansmono.pf2' not found. |
|
error: file `/boot/grub/layouts/usqwerty.gkb' not found. |
|
GNU GRUB version 2.02-2 |
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+----------------------------------------------------------------------------+||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
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Press enter to boot the selected OS, `e' to edit the commands |
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before booting or `c' for a command-line. ESC to return |
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previous menu. *Load Operating System (incl. fully encrypted disks) [o] ? Search ISOLINUX menu (AHCI) [a] ? Search ISOLINUX menu (USB) [u] ? Search ISOLINUX menu (CD/DVD) [d] ? Load test configuration (grubtest.cfg) inside of CBFS [t] ? Search for GRUB2 configuration on external media [s] ? Poweroff [p] ? Reboot [r] ? ? ? ? The highlighted entry will be executed automatically in 1s. The highlighted entry will be executed automatically in 0s. error: file `/boot/grub/fonts/unicode.pf2' not found. |
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