| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| ing SandyBridge RAM training (1). |
| Trying CAS 9, tCK 384. |
| Found compatible clock, CAS pair. |
| Selected DRAM frequency: 666 MHz |
| Selected CAS latency : 9T |
| PLL busy... done in 50 us |
| MCU frequency is set at : 666 MHz |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 1 |
| PCI(0, 0, 0)[bc] = c2a00000 |
| PCI(0, 0, 0)[a8] = 3b600000 |
| PCI(0, 0, 0)[ac] = 1 |
| PCI(0, 0, 0)[b8] = c0000000 |
| PCI(0, 0, 0)[b0] = c0a00000 |
| PCI(0, 0, 0)[b4] = c0800000 |
| PCI(0, 0, 0)[7c] = 7f |
| PCI(0, 0, 0)[70] = fe000000 |
| PCI(0, 0, 0)[74] = 0 |
| PCI(0, 0, 0)[78] = fe000c00 |
| Done memory map |
| Done io registers |
| t123: 1912, 9120, 500 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : YES |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Normal |
| ME: Current Operation State : M0 without UMA |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : Policy Module |
| ME: Power Management Event : Non-power cycle reset |
| ME: Progress Phase State : Entery into Policy Module |
| ME: FWS2: 0x3900012e |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x3 |
| ME: Invoke MEBx : 0x1 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x1 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x0 |
| ME: Current PM event: 0x9 |
| ME: Progress code : 0x3 |
| PASSED! Tell ME that DRAM is ready |
| ME: FWS2: 0x390b012e |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x3 |
| ME: Invoke MEBx : 0x1 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x1 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xb |
| ME: Current PM event: 0x9 |
| ME: Progress code : 0x3 |
| ME: Requested BIOS Action: Continue to boot |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Normal |
| ME: Current Operation State : M0 without UMA |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : Policy Module |
| ME: Power Management Event : Non-power cycle reset |
| ME: Progress Phase State : Received DRAM Init Done |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1330 MHz |
| memcfg channel assignment: A: 1, B 0, C 2 |
| memcfg channel[0] config (00000000): |
| ECC inactive |
| enhanced interleave mode off |
| rank interleave off |
| DIMMA 0 MB width x8 single rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00620010): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 4096 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ bffff000 254 entries. |
| IMD: root @ bfffec00 62 entries. |
| External stage cache: |
| IMD: root @ c03ff000 254 entries. |
| IMD: root @ c03fec00 62 entries. |
| CBMEM entry for DIMM info: 0xbfffea40 |
| MTRR Range: Start=ff000000 End=0 (Size 1000000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=bf800000 End=c0000000 (Size 800000) |
| MTRR Range: Start=c0000000 End=c0800000 (Size 800000) |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Found @ offset dbc0 size 451c |
| Decompressing stage fallback/postcar @ 0xbffcefc0 (34256 bytes) |
| Loading module at bffcf000 with entry bffcf000. filesize: 0x42d0 memsize: 0x8590 |
| Processing 124 relocs. Offset value of 0xbdfcf000 |
| |
| |
| coreboot-4.9-6-gb21539d Wed Jul 17 16:33:51 UTC 2019 postcar starting... |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 87840 size 19331 |
| Decompressing stage fallback/ramstage @ 0xbff87fc0 (283192 bytes) |
| Loading module at bff88000 with entry bff88000. filesize: 0x359d0 memsize: 0x451f8 |
| Processing 3465 relocs. Offset value of 0xbf188000 |
| |
| |
| coreboot-4.9-6-gb21539d Wed Jul 17 16:33:51 UTC 2019 ramstage starting... |
| Normal boot. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:04.0: enabled 0 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 1 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:04.0: enabled 0 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 1 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/0104] ops |
| PCI: 00:00.0 [8086/0104] enabled |
| PCI: 00:01.0 [8086/0000] bus ops |
| PCI: 00:01.0 [8086/0101] disabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0116] enabled |
| PCI: 00:04.0 [8086/0103] disabled |
| PCI: 00:14.0 [8086/0000] ops |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 [8086/1e3a] ops |
| PCI: 00:16.0 [8086/1e3a] disabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0: Disabling device |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1e10] enabled |
| PCI: 00:1c.1 [8086/0000] bus ops |
| PCI: 00:1c.1 [8086/1e12] enabled |
| PCI: 00:1c.2 [8086/0000] bus ops |
| PCI: 00:1c.2 [8086/1e14] enabled |
| PCI: 00:1c.3: Disabling device |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.4: check set enabled |
| PCH: Remap PCIe function 5 to 3 |
| PCI: 00:1c.5 [8086/0000] bus ops |
| PCI: 00:1c.5 [8086/1e1a] enabled |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.6 [8086/0000] bus ops |
| PCI: 00:1c.6 [8086/1e1c] disabled |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfe3cd210 |
| PCH: PCIe map 1c.3 -> 1c.5 |
| PCH: PCIe map 1c.5 -> 1c.3 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1e26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1e.0 [8086/2448] bus ops |
| PCI: 00:1e.0 [8086/2448] disabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1e57] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| PCI: 00:1f.2 [8086/1e01] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1e22] enabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1e09] disabled No operations |
| PCI: 00:1f.6: Disabling device |
| PCI: 00:1f.6 [8086/1e24] disabled No operations |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| PCI: pci_scan_bus for bus 01 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 53 usecs |
| PCI: 00:1c.1 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.1 |
| PCI: pci_scan_bus for bus 02 |
| PCI: 02:00.0 [168c/0034] enabled |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Failed to enable LTR for dev = PCI: 02:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.1 took 236 usecs |
| PCI: 00:1c.2 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.2 |
| PCI: pci_scan_bus for bus 03 |
| PCI: 03:00.0 [10ec/5209] enabled |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled None |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Failed to enable LTR for dev = PCI: 03:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.2 took 220 usecs |
| PCI: 00:1c.3 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.3 |
| PCI: pci_scan_bus for bus 04 |
| PCI: 04:00.0 [10ec/8168] enabled |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Failed to enable LTR for dev = PCI: 04:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.3 took 223 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| PNP: 0c31.0 enabled |
| Clearing EC output queue... |
| EC output queue has been cleared. |
| recv_ec_data: 0x47 |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x31 |
| recv_ec_data: 0x39 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x20 |
| recv_ec_data: 0x10 |
| EC Firmware ID G8HT19WW-0.0, Version 2.01A |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| recv_ec_data: 0x70 |
| recv_ec_data: 0x10 |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| H8: BDC detection not implemented. Assuming BDC installed |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| recv_ec_data: 0x70 |
| H8: WWAN installed |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| recv_ec_data: 0x70 |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| recv_ec_data: 0xfa |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| recv_ec_data: 0xa6 |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| No CMOS option 'first_battery'. |
| recv_ec_data: 0xa6 |
| recv_ec_data: 0x70 |
| PNP: 00ff.1 enabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 35865 usecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 33 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 37177 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 37189 usecs |
| done |
| FMAP: area RW_MRC_CACHE found @ b10000 (65536 bytes) |
| MRC: No data in cbmem for 'RW_MRC_CACHE'. |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 37362 exit 5 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PCI: 00:1c.0 read_resources bus 1 link: 0 |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.1 read_resources bus 2 link: 0 |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| PCI: 00:1c.2 read_resources bus 3 link: 0 |
| PCI: 00:1c.2 read_resources bus 3 link: 0 done |
| PCI: 00:1c.3 read_resources bus 4 link: 0 |
| PCI: 00:1c.3 read_resources bus 4 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PNP: 00ff.1 missing read_resources |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| PCI: 00:1f.3 read_resources bus 1 link: 0 |
| PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10 |
| PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 |
| PCI: 00:1c.2 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.4 |
| PCI: 00:1c.3 child on link 0 PCI: 04:00.0 |
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 04:00.0 |
| PCI: 04:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 04:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 0c31.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1610 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.1 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.1 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.1 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 04:00.0 10 * [0x0 - 0xff] io |
| PCI: 00:1c.3 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.3 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:1f.2 20 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 10 * [0x1060 - 0x1067] io |
| PCI: 00:1f.2 18 * [0x1068 - 0x106f] io |
| PCI: 00:1f.2 14 * [0x1070 - 0x1073] io |
| PCI: 00:1f.2 1c * [0x1074 - 0x1077] io |
| DOMAIN: 0000 io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 02:00.0 10 * [0x0 - 0x7ffff] mem |
| PCI: 02:00.0 30 * [0x80000 - 0x8ffff] mem |
| PCI: 00:1c.1 mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 03:00.0 10 * [0x0 - 0xfff] mem |
| PCI: 00:1c.2 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 04:00.0 20 * [0x0 - 0x3fff] prefmem |
| PCI: 04:00.0 18 * [0x4000 - 0x4fff] prefmem |
| PCI: 00:1c.3 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem |
| PCI: 00:1c.1 20 * [0x10400000 - 0x104fffff] mem |
| PCI: 00:1c.2 20 * [0x10500000 - 0x105fffff] mem |
| PCI: 00:1c.3 24 * [0x10600000 - 0x106fffff] prefmem |
| PCI: 00:14.0 10 * [0x10700000 - 0x1070ffff] mem |
| PCI: 00:1b.0 10 * [0x10710000 - 0x10713fff] mem |
| PCI: 00:1f.2 24 * [0x10714000 - 0x107147ff] mem |
| PCI: 00:1a.0 10 * [0x10715000 - 0x107153ff] mem |
| PCI: 00:1d.0 10 * [0x10716000 - 0x107163ff] mem |
| PCI: 00:1f.3 10 * [0x10717000 - 0x107170ff] mem |
| DOMAIN: 0000 mem: base: 10717100 size: 10717100 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| constrain_resources: PCI: 00:1f.0 10000200 base 00001610 limit 0000168b io (fixed) |
| skipping PNP: 00ff.1@60 fixed resource, size=0! |
| skipping PNP: 00ff.1@62 fixed resource, size=0! |
| skipping PNP: 00ff.1@64 fixed resource, size=0! |
| skipping PNP: 00ff.1@66 fixed resource, size=0! |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000168c limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:168c size:1078 align:12 gran:0 limit:ffff |
| PCI: 00:1c.3 1c * [0x2000 - 0x2fff] io |
| PCI: 00:02.0 20 * [0x3000 - 0x303f] io |
| PCI: 00:1f.2 20 * [0x3040 - 0x305f] io |
| PCI: 00:1f.2 10 * [0x3060 - 0x3067] io |
| PCI: 00:1f.2 18 * [0x3068 - 0x306f] io |
| PCI: 00:1f.2 14 * [0x3070 - 0x3073] io |
| PCI: 00:1f.2 1c * [0x3074 - 0x3077] io |
| DOMAIN: 0000 io: next_base: 3078 size: 1078 align: 12 gran: 0 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.2 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.2 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.3 io: base:2000 size:1000 align:12 gran:12 limit:2fff |
| PCI: 04:00.0 10 * [0x2000 - 0x20ff] io |
| PCI: 00:1c.3 io: next_base: 2100 size: 1000 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:d0000000 size:10717100 align:28 gran:0 limit:efffffff |
| PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem |
| PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem |
| PCI: 00:1c.1 20 * [0xe0400000 - 0xe04fffff] mem |
| PCI: 00:1c.2 20 * [0xe0500000 - 0xe05fffff] mem |
| PCI: 00:1c.3 24 * [0xe0600000 - 0xe06fffff] prefmem |
| PCI: 00:14.0 10 * [0xe0700000 - 0xe070ffff] mem |
| PCI: 00:1b.0 10 * [0xe0710000 - 0xe0713fff] mem |
| PCI: 00:1f.2 24 * [0xe0714000 - 0xe07147ff] mem |
| PCI: 00:1a.0 10 * [0xe0715000 - 0xe07153ff] mem |
| PCI: 00:1d.0 10 * [0xe0716000 - 0xe07163ff] mem |
| PCI: 00:1f.3 10 * [0xe0717000 - 0xe07170ff] mem |
| DOMAIN: 0000 mem: next_base: e0717100 size: 10717100 align: 28 gran: 0 done |
| PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.1 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.1 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.1 mem: base:e0400000 size:100000 align:20 gran:20 limit:e04fffff |
| PCI: 02:00.0 10 * [0xe0400000 - 0xe047ffff] mem |
| PCI: 02:00.0 30 * [0xe0480000 - 0xe048ffff] mem |
| PCI: 00:1c.1 mem: next_base: e0490000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.2 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.2 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.2 mem: base:e0500000 size:100000 align:20 gran:20 limit:e05fffff |
| PCI: 03:00.0 10 * [0xe0500000 - 0xe0500fff] mem |
| PCI: 00:1c.2 mem: next_base: e0501000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.3 prefmem: base:e0600000 size:100000 align:20 gran:20 limit:e06fffff |
| PCI: 04:00.0 20 * [0xe0600000 - 0xe0603fff] prefmem |
| PCI: 04:00.0 18 * [0xe0604000 - 0xe0604fff] prefmem |
| PCI: 00:1c.3 prefmem: next_base: e0605000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.3 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.3 mem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x13b600000 TOLUD 0xc2a00000 TOM 0x100000000 |
| MEBASE 0xfe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0xc0000000 size 8M |
| Available memory below 4GB: 3072M |
| Available memory above 4GB: 950M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io |
| PCI: 00:14.0 10 <- [0x00e0700000 - 0x00e070ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:1a.0 10 <- [0x00e0715000 - 0x00e07153ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00e0710000 - 0x00e0713fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 02:00.0 10 <- [0x00e0400000 - 0x00e047ffff] size 0x00080000 gran 0x13 mem64 |
| PCI: 02:00.0 30 <- [0x00e0480000 - 0x00e048ffff] size 0x00010000 gran 0x10 romem |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.2 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 03 mem |
| PCI: 00:1c.2 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x00e0500000 - 0x00e0500fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:1c.2 assign_resources, bus 3 link: 0 |
| PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io |
| PCI: 00:1c.3 24 <- [0x00e0600000 - 0x00e06fffff] size 0x00100000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem |
| PCI: 00:1c.3 assign_resources, bus 4 link: 0 |
| PCI: 04:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io |
| PCI: 04:00.0 18 <- [0x00e0604000 - 0x00e0604fff] size 0x00001000 gran 0x0c prefmem64 |
| PCI: 04:00.0 20 <- [0x00e0600000 - 0x00e0603fff] size 0x00004000 gran 0x0e prefmem64 |
| PCI: 00:1c.3 assign_resources, bus 4 link: 0 |
| PCI: 00:1d.0 10 <- [0x00e0716000 - 0x00e07163ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 00ff.1 missing set_resources |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00e0714000 - 0x00e07147ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00e0717000 - 0x00e07170ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 168c size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base d0000000 size 10717100 align 28 gran 0 limit efffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 3b600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index 9 |
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit e03fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base e0700000 size 10000 align 16 gran 16 limit e070ffff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base e0715000 size 400 align 12 gran 10 limit e07153ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base e0710000 size 4000 align 14 gran 14 limit e0713fff flags 60000201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.1 resource base e0400000 size 100000 align 20 gran 20 limit e04fffff flags 60080202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base e0400000 size 80000 align 19 gran 19 limit e047ffff flags 60000201 index 10 |
| PCI: 02:00.0 resource base e0480000 size 10000 align 16 gran 16 limit e048ffff flags 60002200 index 30 |
| PCI: 00:1c.2 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.2 resource base e0500000 size 100000 align 20 gran 20 limit e05fffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base e0500000 size 1000 align 12 gran 12 limit e0500fff flags 60000200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.4 |
| PCI: 00:1c.3 child on link 0 PCI: 04:00.0 |
| PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c |
| PCI: 00:1c.3 resource base e0600000 size 100000 align 20 gran 20 limit e06fffff flags 60081202 index 24 |
| PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 |
| PCI: 04:00.0 |
| PCI: 04:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 10 |
| PCI: 04:00.0 resource base e0604000 size 1000 align 12 gran 12 limit e0604fff flags 60001201 index 18 |
| PCI: 04:00.0 resource base e0600000 size 4000 align 14 gran 14 limit e0603fff flags 60001201 index 20 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base e0716000 size 400 align 12 gran 10 limit e07163ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 0c31.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1610 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.1 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.1 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.1 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base e0714000 size 800 align 12 gran 11 limit e07147ff flags 60000200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base e0717000 size 100 align 12 gran 8 limit e07170ff flags 60000201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2818 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 17aa/21fe |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 17aa/21fe |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:14.0 subsystem <- 17aa/21fe |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:1a.0 subsystem <- 17aa/21fe |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 17aa/21fe |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 17aa/21fe |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 17aa/21fe |
| PCI: 00:1c.1 cmd <- 106 |
| PCI: 00:1c.2 bridge ctrl <- 0003 |
| PCI: 00:1c.2 subsystem <- 17aa/21fe |
| PCI: 00:1c.2 cmd <- 106 |
| PCI: 00:1c.3 bridge ctrl <- 0003 |
| PCI: 00:1c.3 subsystem <- 17aa/21fe |
| PCI: 00:1c.3 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 17aa/21fe |
| PCI: 00:1d.0 cmd <- 102 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 17aa/21fe |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 17aa/21fe |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 17aa/21fe |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 02:00.0 cmd <- 02 |
| PCI: 03:00.0 cmd <- 02 |
| PCI: 04:00.0 cmd <- 03 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 151 exit 0 |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x801 |
| TPM: Continue self test |
| TPM: command 0x53 returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=0, nvlocked=0 |
| TPM: setup succeeded |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 1 usecs |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call bffa4d2e(bffc90c0) |
| Installing SMM handler to 0xc0000000 |
| Loading module at c0010000 with entry c0010497. filesize: 0x1b90 memsize: 0x5bb8 |
| Processing 60 relocs. Offset value of 0xc0010000 |
| Loading module at c0008000 with entry c0008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0xc0008000 |
| SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at c0007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd |
| SMM Module: stub loaded at c0008000. Will call c0010497(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: MCSMI |
| PM1_STS: |
| PM1_EN: 0 |
| GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 TCO_SCI |
| ALT_GP_SMI_STS: GPI15 GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| Enabling cache |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 80 size 6400 |
| microcode: sig=0x206a7 pf=0x10 revision=0x2d |
| CPU: Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x206a7 |
| CPU: AES NOT supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 |
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000013b600000 size 0x3b600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 3/4. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x00 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1400 |
| Turbo is unavailable |
| CPU: 0 has 2 cores, 2 threads per core |
| CPU: 0 has core 1 |
| CPU1: stack_base bffc0000, stack_end bffc0ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| CPU: 0 has core 2 |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| Enabling cache |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 80 size 6400 |
| microcode: sig=0x206a7 pf=0x10 revision=0x2d |
| CPU: Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x206a7 |
| CPU: AES NOT supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x01 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1400 |
| CPU #1 initialized |
| CPU2: stack_base bffbf000, stack_end bffbfff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| Enabling cache |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 80 size 6400 |
| microcode: sig=0x206a7 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x2d date=2018-02-07 |
| CPU: Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x206a7 |
| CPU: AES NOT supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x02 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1400 |
| CPU #2 initialized |
| CPU3: stack_base bffbe000, stack_end bffbeff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #3 |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| Enabling cache |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 80 size 6400 |
| microcode: sig=0x206a7 pf=0x10 revision=0x2d |
| CPU: Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x206a7 |
| CPU: AES NOT supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x03 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 1400 |
| CPU #3 initialized |
| All AP CPUs stopped (563 loops) |
| CPU0: stack: bffc1000 - bffc2000, lowest used address bffc1a90, stack used: 1392 bytes |
| CPU1: stack: bffc0000 - bffc1000, lowest used address bffc0c80, stack used: 896 bytes |
| CPU2: stack: bffbf000 - bffc0000, lowest used address bffbfc80, stack used: 896 bytes |
| CPU3: stack: bffbe000 - bffbf000, lowest used address bffbec80, stack used: 896 bytes |
| CPU_CLUSTER: 0 init finished in 67464 usecs |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG10. |
| Disabling Device 4. |
| Disabling PEG60. |
| Disabling Device 7. |
| Disabling PEG IO clock. |
| Set BIOS_RESET_CPL |
| CPU TDP: 17 Watts |
| PCI: 00:00.0 init finished in 1021 usecs |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| SNB GT2 Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| EDID: |
| 00 ff ff ff ff ff ff 00 06 af 5c 31 00 00 00 00 |
| 00 14 01 03 80 1a 0e 78 0a 99 85 95 55 56 92 28 |
| 22 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 |
| 01 01 01 01 01 01 12 1b 56 5a 50 00 19 30 30 20 |
| 36 00 00 90 10 00 00 18 00 00 00 0f 00 00 00 00 |
| 00 00 00 00 00 00 00 00 00 20 00 00 00 fe 00 41 |
| 55 4f 0a 20 20 20 20 20 20 20 20 20 00 00 00 fe |
| 00 42 31 31 36 58 57 30 33 20 56 31 20 0a 00 e9 |
| Extracted contents: |
| header: 00 ff ff ff ff ff ff 00 |
| serial number: 06 af 5c 31 00 00 00 00 00 14 |
| version: 01 03 |
| basic params: 80 1a 0e 78 0a |
| chroma info: 99 85 95 55 56 92 28 22 50 54 |
| established: 00 00 00 |
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 |
| descriptor 1: 12 1b 56 5a 50 00 19 30 30 20 36 00 00 90 10 00 00 18 |
| descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 |
| descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20 |
| descriptor 4: 00 00 00 fe 00 42 31 31 36 58 57 30 33 20 56 31 20 0a |
| extensions: 00 |
| checksum: e9 |
| |
| Manufacturer: AUO Model 315c Serial Number 0 |
| Made week 0 of 2010 |
| EDID version: 1.3 |
| Digital display |
| Maximum image size: 26 cm x 14 cm |
| Gamma: 220% |
| Check DPMS levels |
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2 |
| First detailed timing is preferred timing |
| Established timings supported: |
| Standard timings supported: |
| Detailed timings |
| Hex of detail: 121b565a5000193030203600009010000018 |
| Detailed mode (IN HEX): Clock 69300 KHz, 100 mm x 90 mm |
| 0556 0586 05a6 05b0 hborder 0 |
| 0300 0303 0309 0319 vborder 0 |
| -hsync -vsync |
| Did detailed timing |
| Hex of detail: 0000000f0000000000000000000000000020 |
| Manufacturer-specified data, tag 15 |
| Hex of detail: 000000fe0041554f0a202020202020202020 |
| ASCII string: AUO |
| Hex of detail: 000000fe004231313658573033205631200a |
| ASCII string: B116XW03 V1 |
| Checksum |
| Checksum: 0xe9 (valid) |
| WARNING: EDID block does NOT fully conform to EDID 1.3. |
| Missing name descriptor |
| Missing monitor ranges |
| bringing up panel at resolution 1376 x 768 |
| Borders 0 x 0 |
| Blank 90 x 25 |
| Sync 32 x 6 |
| Front porch 48 x 3 |
| Spread spectrum clock |
| Single channel |
| Polarities 1, 1 |
| Data M1=1211105, N1=8388608 |
| Link frequency 270000 kHz |
| Link M1=134567, N1=524288 |
| Pixel N=6, M1=18, M2=7, P1=2 |
| Pixel clock 138571 kHz |
| waiting for panel powerup |
| panel powered up |
| PCI: 00:02.0 init finished in 30373 usecs |
| PCI: 00:14.0 init ... |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 8 usecs |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 14 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: base = e0710000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: verb_size: 16 |
| Azalia: verb loaded. |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 10ec0269 |
| Azalia: verb_size: 44 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 4851 usecs |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 9 usecs |
| PCI: 00:1c.1 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 9 usecs |
| PCI: 00:1c.2 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.2 init finished in 9 usecs |
| PCI: 00:1c.3 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.3 init finished in 9 usecs |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 14 usecs |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| PCH: detected HM77, device id: 0x1e57, rev id 0x4 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| Set power off after power failure. |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| NMI sources disabled. |
| PantherPoint PM init |
| RTC: failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 1222 usecs |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| FMAP: area COREBOOT found @ b20000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| SATA: Controller in AHCI mode. |
| ABAR: e0714000 |
| PCI: 00:1f.2 init finished in 311 usecs |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 1 usecs |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 1 usecs |
| PCI: 04:00.0 init ... |
| PCI: 04:00.0 init finished in 0 usecs |
| PNP: 00ff.1 init ... |
| Keyboard init... |
| Keyboard controller output buffer result timeout |
| PS/2 keyboard initialized on primary channel |
| PNP: 00ff.1 init finished in 541520 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ... |
| I2C: 01:54 init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ... |
| I2C: 01:55 init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ... |
| I2C: 01:56 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ... |
| I2C: 01:57 init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ... |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 27566 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ... |
| I2C: 01:5d init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ... |
| I2C: 01:5e init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ... |
| I2C: 01:5f init finished in 1 usecs |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:04.0: enabled 0 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| I2C: 01:54: enabled 1 |
| I2C: 01:55: enabled 1 |
| I2C: 01:56: enabled 1 |
| I2C: 01:57: enabled 1 |
| I2C: 01:5c: enabled 1 |
| I2C: 01:5d: enabled 1 |
| I2C: 01:5e: enabled 1 |
| I2C: 01:5f: enabled 1 |
| PCI: 02:00.0: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PCI: 04:00.0: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 140902 run 674611 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 56 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 12140 size 35e4 |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at bff4b000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 4 core(s) each. |
| PSS: 1400MHz power 17000 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 14233 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 11579 control 0xa00 status 0xa00 |
| PSS: 800MHz power 9046 control 0x800 status 0x800 |
| PSS: 1400MHz power 17000 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 14233 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 11579 control 0xa00 status 0xa00 |
| PSS: 800MHz power 9046 control 0x800 status 0x800 |
| PSS: 1400MHz power 17000 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 14233 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 11579 control 0xa00 status 0xa00 |
| PSS: 800MHz power 9046 control 0x800 status 0x800 |
| PSS: 1400MHz power 17000 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 14233 control 0xc00 status 0xc00 |
| PSS: 1000MHz power 11579 control 0xa00 status 0xa00 |
| PSS: 800MHz power 9046 control 0x800 status 0x800 |
| Generating ACPI PIRQ entries |
| ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=7 |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: * H8 |
| H8: BDC detection not implemented. Assuming BDC installed |
| H8: WWAN installed |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at bff3a000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = bff50250 |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'vbt.bin' |
| CBFS: 'vbt.bin' not found. |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'pci8086,0116.rom' |
| CBFS: 'pci8086,0116.rom' not found. |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'pci8086,0106.rom' |
| CBFS: 'pci8086,0106.rom' not found. |
| PCI Option ROM loading disabled for PCI: 00:02.0 |
| GMA: locate_vbt_vbios: aa55 8086 0 0 3 |
| GMA: Found valid VBT in legacy area |
| ACPI: * HPET |
| ACPI: added table 6/32, length now 60 |
| ACPI: done. |
| ACPI tables: 29328 bytes. |
| smbios_write_tables: bff39000 |
| recv_ec_data: 0x47 |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x31 |
| recv_ec_data: 0x39 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x00 |
| Create SMBIOS type 17 |
| SMBIOS tables: 530 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4fe7 |
| Writing coreboot table at 0xbff6f000 |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset d540 size 61c |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000001fffffff: RAM |
| 4. 0000000020000000-00000000201fffff: RESERVED |
| 5. 0000000020200000-000000003fffffff: RAM |
| 6. 0000000040000000-00000000401fffff: RESERVED |
| 7. 0000000040200000-00000000bff38fff: RAM |
| 8. 00000000bff39000-00000000bff87fff: CONFIGURATION TABLES |
| 9. 00000000bff88000-00000000bffcdfff: RAMSTAGE |
| 10. 00000000bffce000-00000000bfffffff: CONFIGURATION TABLES |
| 11. 00000000c0000000-00000000c29fffff: RESERVED |
| 12. 00000000f0000000-00000000f3ffffff: RESERVED |
| 13. 00000000fed40000-00000000fed44fff: RESERVED |
| 14. 0000000100000000-000000013b5fffff: RAM |
| flash size 0xc00000 bytes |
| SF: Detected Opaque HW-sequencing with sector size 0x1000, total 0xc00000 |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| Wrote coreboot table at: bff6f000, 0x9a4 bytes, checksum 7fe7 |
| coreboot table: 2492 bytes. |
| IMD ROOT 0. bffff000 00001000 |
| IMD SMALL 1. bfffe000 00001000 |
| CONSOLE 2. bffde000 00020000 |
| TIME STAMP 3. bffdd000 00000910 |
| ROMSTG STCK 4. bffd8000 00005000 |
| AFTER CAR 5. bffce000 0000a000 |
| RAMSTAGE 6. bff87000 00047000 |
| SMM BACKUP 7. bff77000 00010000 |
| COREBOOT 8. bff6f000 00008000 |
| ACPI 9. bff4b000 00024000 |
| ACPI GNVS 10. bff4a000 00001000 |
| TCPA TCGLOG11. bff3a000 00010000 |
| SMBIOS 12. bff39000 00000800 |
| IMD small region: |
| IMD ROOT 0. bfffec00 00000400 |
| MEM INFO 1. bfffea40 000001a9 |
| ROMSTAGE 2. bfffea20 00000004 |
| COREBOOTFWD 3. bfffe9e0 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 23382 exit 0 |
| CBFS @ b20000 size e0000 |
| CBFS: 'Master Header Locator' located CBFS at [b20000:c00000) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 15780 size 10a96 |
| Checking segment from ROM address 0xfff357b8 |
| Payload being loaded at below 1MiB without region being marked as RAM usable. |
| Checking segment from ROM address 0xfff357d4 |
| Loading segment from ROM address 0xfff357b8 |
| code (compression=1) |
| New segment dstaddr 0x000e0660 memsize 0x1f9a0 srcaddr 0xfff357f0 filesize 0x10a5e |
| Loading Segment: addr: 0x000e0660 memsz: 0x000000000001f9a0 filesz: 0x0000000000010a5e |
| using LZMA |
| [ 0x000e0660, 00100000, 0x00100000) <- fff357f0 |
| Loading segment from ROM address 0xfff357d4 |
| Entry Point 0x000ff809 |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 43161 exit 0 |
| PCH: watchdog disabled |
| Jumping to boot code at 000ff809(bff6f000) |
| CPU0: stack: bffc1000 - bffc2000, lowest used address bffc1a60, stack used: 1440 bytes |
| SeaBIOS (version rel-1.12.0-0-ga698c89) |
| BUILD: gcc: (Ubuntu 5.4.0-6ubuntu1~16.04.11) 5.4.0 20160609 binutils: (GNU Binutils for Ubuntu) 2.26.1 |
| Found coreboot cbmem console @ bffde000 |
| Found mainboard LENOVO ThinkPad X131e |
| Relocating init from 0x000e1ca0 to 0xbfeec120 (size 52704) |
| Found CBFS header at 0xfff20038 |
| multiboot: eax=bffbd1c0, ebx=bffbd174 |
| Found 16 PCI devices (max PCI bus is 04) |
| Copying SMBIOS entry point from 0xbff39000 to 0x000f66c0 |
| Copying ACPI RSDP from 0xbff4b000 to 0x000f6690 |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.12.0-0-ga698c89) |
| Machine UUID 6d166001-5144-11cb-a3cb-ff41e268145a |
| XHCI init on dev 00:14.0: regs @ 0xe0700000, 8 ports, 32 slots, 32 byte contexts |
| XHCI protocol USB 2.00, 4 ports (offset 1), def 3001 |
| XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 |
| XHCI extcap 0xc1 @ 0xe0708040 |
| XHCI extcap 0xc0 @ 0xe0708070 |
| XHCI extcap 0x1 @ 0xe0708330 |
| EHCI init on dev 00:1a.0 (regs=0xe0715020) |
| EHCI init on dev 00:1d.0 (regs=0xe0716020) |
| AHCI controller at 00:1f.2, iobase 0xe0714000, irq 10 |
| Found 0 lpt ports |
| Found 0 serial ports |
| Searching bootorder for: /rom@img/memtest |
| Searching bootorder for: /rom@img/nvramcui |
| Searching bootorder for: /rom@img/tint |
| Searching bootorder for: /rom@img/coreinfo |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-6 |
| AHCI/0: registering: "AHCI/0: Samsung SSD 850 EVO 120GB ATA-9 Hard-Disk (111 GiBytes)" |
| XHCI no devices found |
| USB keyboard initialized |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (1 ports used) |
| PS2 keyboard initialized |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f6620: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 |
| Space available for UMB: c7000-ed000, f5ee0-f6620 |
| Returned 184320 bytes of ZoneHigh |
| e820 map has 12 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 0000000020000000 = 1 RAM |
| 4: 0000000020000000 - 0000000020200000 = 2 RESERVED |
| 5: 0000000020200000 - 0000000040000000 = 1 RAM |
| 6: 0000000040000000 - 0000000040200000 = 2 RESERVED |
| 7: 0000000040200000 - 00000000bff26000 = 1 RAM |
| 8: 00000000bff26000 - 00000000c2a00000 = 2 RESERVED |
| 9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 10: 00000000fed40000 - 00000000fed45000 = 2 RESERVED |
| 11: 0000000100000000 - 000000013b600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |