| |
| |
| coreboot-4.2-619-gd890b45 Sat Dec 26 19:53:49 UTC 2015 romstage starting... |
| Setting up static southbridge registers... done. |
| Disabling Watchdog reboot... done. |
| Setting up static northbridge registers... done. |
| Initializing Graphics... |
| Back from sandybridge_early_initialization() |
| POST: 0x38 |
| SMBus controller enabled. |
| POST: 0x39 |
| POST: 0x3a |
| CPU id(306a9): Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz |
| AES supported, TXT supported, VT supported |
| PCH type: B75, device id: 1e49, rev id 4 |
| Intel ME early init |
| Intel ME firmware is ready |
| ME: Requested 32MB UMA |
| Starting native Platform init |
| Row addr bits : 16 |
| Column addr bits : 10 |
| Number of ranks : 1 |
| DIMM Capacity : 4096 MB |
| CAS latencies : 5 6 7 8 9 10 11 |
| tCKmin : 1.250 ns |
| tAAmin : 13.125 ns |
| tWRmin : 15.000 ns |
| tRCDmin : 13.125 ns |
| tRRDmin : 6.000 ns |
| tRPmin : 13.125 ns |
| tRASmin : 35.000 ns |
| tRCmin : 48.125 ns |
| tRFCmin : 260.000 ns |
| tWTRmin : 7.500 ns |
| tRTPmin : 7.500 ns |
| tFAWmin : 30.000 ns |
| rankmap[0] = 0x1 |
| Row addr bits : 16 |
| Column addr bits : 10 |
| Number of ranks : 1 |
| DIMM Capacity : 4096 MB |
| CAS latencies : 5 6 7 8 9 10 11 |
| tCKmin : 1.250 ns |
| tAAmin : 13.125 ns |
| tWRmin : 15.000 ns |
| tRCDmin : 13.125 ns |
| tRRDmin : 6.000 ns |
| tRPmin : 13.125 ns |
| tRASmin : 35.000 ns |
| tRCmin : 48.125 ns |
| tRFCmin : 260.000 ns |
| tWTRmin : 7.500 ns |
| tRTPmin : 7.500 ns |
| tFAWmin : 30.000 ns |
| rankmap[1] = 0x1 |
| PLL busy...done |
| MCU frequency is set at : 800 MHz |
| Selected DRAM frequency: 800 MHz |
| Minimum CAS latency : 11T |
| Selected CAS latency : 11T |
| Selected CWL latency : 8T |
| Selected tRCD : 11T |
| Selected tRP : 11T |
| Selected tRAS : 28T |
| Selected tWR : 12T |
| Selected tFAW : 24T |
| Selected tRRD : 5T |
| Selected tRTP : 6T |
| Selected tWTR : 6T |
| Selected tRFC : 208T |
| [c14] = 1000000 |
| [320c] = 24000 |
| [d14] = 1000000 |
| [330c] = 24000 |
| [4000] = 1c8bbb |
| [4004] = cc186465 |
| [400c] = a08b4 |
| [4298] = 6cd01860 |
| [42a4] = 41f88200 |
| [4400] = 1c8bbb |
| [4404] = cc186465 |
| [440c] = a08b4 |
| [4698] = 6cd01860 |
| [46a4] = 41f88200 |
| Done dimm mapping |
| PCI:[a0] = 0 |
| PCI:[a4] = 2 |
| PCI:[bc] = c2a00000 |
| PCI:[a8] = 3b600000 |
| PCI:[ac] = 2 |
| PCI:[b8] = c0000000 |
| PCI:[b0] = c0a00000 |
| PCI:[b4] = c0800000 |
| PCI:[7c] = 7f |
| PCI:[70] = fe000000 |
| PCI:[74] = 1 |
| PCI:[78] = fe000c00 |
| Done memory map |
| RCOMP...done |
| COMP2 done |
| COMP1 done |
| FORCE RCOMP and wait 20us...done |
| Done io registers |
| Done jedec reset |
| Done MRS commands |
| High adjust 0:0000ffffffffffff |
| High adjust 1:00000000ffffffff |
| High adjust 2:00000000ffffffff |
| High adjust 3:00000000ffffffff |
| High adjust 4:00000000ffffffff |
| High adjust 5:00000000ffffffff |
| High adjust 6:00000000ffffffff |
| High adjust 7:00000000ffffffff |
| High adjust 0:0000fffffff |
| |
| *** Log truncated, 2653 characters dropped. *** |
| |
| Relocate MRC DATA from feffa79c to bffdd000 (1040 bytes) |
| POST: 0x3c |
| POST: 0x3d |
| POST: 0x3f |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 740100 size 108ab |
| |
| |
| coreboot-4.2-619-gd890b45 Sat Dec 26 19:53:49 UTC 2015 ramstage starting... |
| POST: 0x39 |
| Moving GDT to bfffe8a0...ok |
| POST: 0x80 |
| Normal boot. |
| POST: 0x70 |
| BS: BS_PRE_DEVICE times (us): entry 0 run 1054 exit 0 |
| POST: 0x71 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1054 exit 0 |
| POST: 0x72 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| POST: 0x24 |
| PCI: 00:00.0 [8086/0150] ops |
| Normal boot. |
| PCI: 00:00.0 [8086/0150] enabled |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| PCI: 00:01.0 subordinate bus PCI Express |
| PCI: 00:01.0 [8086/0151] enabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0162] enabled |
| PCI: 00:14.0 [8086/0000] ops |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0 [8086/1e3a] ops |
| PCI: 00:16.0 [8086/1e3a] enabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.1 [8086/1e3b] disabled No operations |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.2 [8086/1e3c] disabled No operations |
| PCI: 00:16.3: Disabling device |
| PCI: 00:16.3 [8086/1e3d] disabled No operations |
| PCI: 00:19.0: Disabling device |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1e10] enabled |
| PCI: 00:1c.1: Disabling device |
| PCI: 00:1c.2: Disabling device |
| PCI: 00:1c.3: Disabling device |
| PCI: 00:1c.4 [8086/0000] bus ops |
| PCI: 00:1c.4 [8086/1e18] enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfed4ba90 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1e26] enabled |
| Capability: type 0x0d @ 0x50 |
| Capability: type 0x0d @ 0x50 |
| PCI: 00:1e.0 [8086/244e] enabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1e49] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| PCI: 00:1f.2 [8086/1e00] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1e22] enabled |
| PCI: 00:1f.4: Disabling device |
| PCI: 00:1f.5: Disabling device |
| POST: 0x25 |
| PCI: 00:01.0 scanning... |
| do_pci_scan_bridge for PCI: 00:01.0 |
| PCI: pci_scan_bus for bus 01 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: scanning of bus PCI: 00:01.0 took 11259 usecs |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| PCI: pci_scan_bus for bus 02 |
| POST: 0x24 |
| PCI: 02:00.0 [1106/3432] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xc4 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled None |
| scan_bus: scanning of bus PCI: 00:1c.0 took 29765 usecs |
| PCI: 00:1c.4 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.4 |
| PCI: pci_scan_bus for bus 03 |
| POST: 0x24 |
| PCI: 03:00.0 [10ec/8168] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| scan_bus: scanning of bus PCI: 00:1c.4 took 29605 usecs |
| PCI: 00:1e.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1e.0 |
| PCI: pci_scan_bus for bus 04 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: scanning of bus PCI: 00:1e.0 took 11287 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| PNP: 002e.0 disabled |
| PNP: 002e.1 enabled |
| PNP: 002e.2 enabled |
| PNP: 002e.3 enabled |
| PNP: 002e.4 enabled |
| PNP: 002e.5 enabled |
| PNP: 002e.6 enabled |
| PNP: 002e.7 disabled |
| PNP: 002e.a disabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 25006 usecs |
| PCI: 00:1f.3 scanning... |
| scan_smbus for PCI: 00:1f.3 |
| scan_smbus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 7748 usecs |
| POST: 0x55 |
| scan_bus: scanning of bus DOMAIN: 0000 took 306736 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 324480 usecs |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 522632 exit 0 |
| POST: 0x73 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PCI: 00:01.0 read_resources bus 1 link: 0 |
| PCI: 00:01.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.0 read_resources bus 2 link: 0 |
| PCI: 00:1c.0 read_resources bus 2 link: 0 done |
| PCI: 00:1c.4 read_resources bus 3 link: 0 |
| PCI: 00:1c.4 read_resources bus 3 link: 0 done |
| PCI: 00:1e.0 read_resources bus 4 link: 0 |
| PCI: 00:1e.0 read_resources bus 4 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| PCI: 00:1c.1 |
| PCI: 00:1c.2 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1f.0 child on link 0 PNP: 002e.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PNP: 002e.0 |
| PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| PNP: 002e.1 |
| PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.2 |
| PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.3 |
| PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60 |
| PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 |
| PNP: 002e.4 |
| PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags c0000100 index 62 |
| PNP: 002e.5 |
| PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 |
| PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 |
| PNP: 002e.6 |
| PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.7 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.a |
| PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1f.4 |
| PCI: 00:1f.5 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 03:00.0 10 * [0x0 - 0xff] io |
| PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:1f.2 20 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 10 * [0x1060 - 0x1067] io |
| PCI: 00:1f.2 18 * [0x1068 - 0x106f] io |
| PCI: 00:1f.2 14 * [0x1070 - 0x1073] io |
| PCI: 00:1f.2 1c * [0x1074 - 0x1077] io |
| DOMAIN: 0000 io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 02:00.0 10 * [0x0 - 0xfff] mem |
| PCI: 00:1c.0 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem |
| PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem |
| PCI: 00:1c.4 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem |
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem |
| PCI: 00:1c.4 24 * [0x10500000 - 0x105fffff] prefmem |
| PCI: 00:14.0 10 * [0x10600000 - 0x1060ffff] mem |
| PCI: 00:1b.0 10 * [0x10610000 - 0x10613fff] mem |
| PCI: 00:1f.2 24 * [0x10614000 - 0x106147ff] mem |
| PCI: 00:1a.0 10 * [0x10615000 - 0x106153ff] mem |
| PCI: 00:1d.0 10 * [0x10616000 - 0x106163ff] mem |
| PCI: 00:1f.3 10 * [0x10617000 - 0x106170ff] mem |
| PCI: 00:16.0 10 * [0x10618000 - 0x1061800f] mem |
| DOMAIN: 0000 mem: base: 10618010 size: 10618010 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 cf base f0000000 limit f3ffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:1000 size:1078 align:12 gran:0 limit:ffff |
| PCI: 00:1c.4 1c * [0x1000 - 0x1fff] io |
| PCI: 00:02.0 20 * [0x2000 - 0x203f] io |
| PCI: 00:1f.2 20 * [0x2040 - 0x205f] io |
| PCI: 00:1f.2 10 * [0x2060 - 0x2067] io |
| PCI: 00:1f.2 18 * [0x2068 - 0x206f] io |
| PCI: 00:1f.2 14 * [0x2070 - 0x2073] io |
| PCI: 00:1f.2 1c * [0x2074 - 0x2077] io |
| DOMAIN: 0000 io: next_base: 2078 size: 1078 align: 12 gran: 0 done |
| PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.4 io: base:1000 size:1000 align:12 gran:12 limit:1fff |
| PCI: 03:00.0 10 * [0x1000 - 0x10ff] io |
| PCI: 00:1c.4 io: next_base: 1100 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1e.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1e.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:d0000000 size:10618010 align:28 gran:0 limit:efffffff |
| PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem |
| PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem |
| PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem |
| PCI: 00:1c.4 24 * [0xe0500000 - 0xe05fffff] prefmem |
| PCI: 00:14.0 10 * [0xe0600000 - 0xe060ffff] mem |
| PCI: 00:1b.0 10 * [0xe0610000 - 0xe0613fff] mem |
| PCI: 00:1f.2 24 * [0xe0614000 - 0xe06147ff] mem |
| PCI: 00:1a.0 10 * [0xe0615000 - 0xe06153ff] mem |
| PCI: 00:1d.0 10 * [0xe0616000 - 0xe06163ff] mem |
| PCI: 00:1f.3 10 * [0xe0617000 - 0xe06170ff] mem |
| PCI: 00:16.0 10 * [0xe0618000 - 0xe061800f] mem |
| DOMAIN: 0000 mem: next_base: e0618010 size: 10618010 align: 28 gran: 0 done |
| PCI: 00:01.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:01.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:01.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:01.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:e0400000 size:100000 align:20 gran:20 limit:e04fffff |
| PCI: 02:00.0 10 * [0xe0400000 - 0xe0400fff] mem |
| PCI: 00:1c.0 mem: next_base: e0401000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.4 prefmem: base:e0500000 size:100000 align:20 gran:20 limit:e05fffff |
| PCI: 03:00.0 20 * [0xe0500000 - 0xe0503fff] prefmem |
| PCI: 03:00.0 18 * [0xe0504000 - 0xe0504fff] prefmem |
| PCI: 00:1c.4 prefmem: next_base: e0505000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.4 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.4 mem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1e.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1e.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1e.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1e.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000 |
| MEBASE 0x1fe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0xc0000000 size 8M |
| Available memory below 4GB: 3072M |
| Available memory above 4GB: 5046M |
| Adding PCIe config bar base=0xf0000000 size=0x4000000 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> |
| PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:01.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:01.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io |
| PCI: 00:14.0 10 <- [0x00e0600000 - 0x00e060ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:16.0 10 <- [0x00e0618000 - 0x00e061800f] size 0x00000010 gran 0x04 mem64 |
| PCI: 00:1a.0 10 <- [0x00e0615000 - 0x00e06153ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00e0610000 - 0x00e0613fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| PCI: 02:00.0 10 <- [0x00e0400000 - 0x00e0400fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io |
| PCI: 00:1c.4 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.4 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.4 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io |
| PCI: 03:00.0 18 <- [0x00e0504000 - 0x00e0504fff] size 0x00001000 gran 0x0c prefmem64 |
| PCI: 03:00.0 20 <- [0x00e0500000 - 0x00e0503fff] size 0x00004000 gran 0x0e prefmem64 |
| PCI: 00:1c.4 assign_resources, bus 3 link: 0 |
| PCI: 00:1d.0 10 <- [0x00e0616000 - 0x00e06163ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1e.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq |
| PNP: 002e.3 60 <- [0x0000000378 - 0x000000037b] size 0x00000004 gran 0x02 io |
| PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq |
| PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq |
| PNP: 002e.4 60 <- [0x0000000a30 - 0x0000000a37] size 0x00000008 gran 0x03 io |
| PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq |
| PNP: 002e.4 62 <- [0x0000000a20 - 0x0000000a27] size 0x00000008 gran 0x03 io |
| PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io |
| PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq |
| PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io |
| PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00e0614000 - 0x00e06147ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00e0617000 - 0x00e06170ff] size 0x00000100 gran 0x08 mem64 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 1000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base d0000000 size 10618010 align 28 gran 0 limit efffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 13b600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9 |
| DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:01.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:01.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit e03fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 20 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base e0600000 size 10000 align 16 gran 16 limit e060ffff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base e0618000 size 10 align 12 gran 4 limit e061800f flags 60000201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base e0615000 size 400 align 12 gran 10 limit e06153ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base e0610000 size 4000 align 14 gran 14 limit e0613fff flags 60000201 index 10 |
| PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit e04fffff flags 60080202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base e0400000 size 1000 align 12 gran 12 limit e0400fff flags 60000200 index 10 |
| PCI: 00:1c.1 |
| PCI: 00:1c.2 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.4 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c |
| PCI: 00:1c.4 resource base e0500000 size 100000 align 20 gran 20 limit e05fffff flags 60081202 index 24 |
| PCI: 00:1c.4 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10 |
| PCI: 03:00.0 resource base e0504000 size 1000 align 12 gran 12 limit e0504fff flags 60001201 index 18 |
| PCI: 03:00.0 resource base e0500000 size 4000 align 14 gran 14 limit e0503fff flags 60001201 index 20 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base e0616000 size 400 align 12 gran 10 limit e06163ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 |
| PCI: 00:1f.0 child on link 0 PNP: 002e.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PNP: 002e.0 |
| PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| PNP: 002e.1 |
| PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.2 |
| PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.3 |
| PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags e0000100 index 60 |
| PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 |
| PNP: 002e.4 |
| PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags e0000100 index 62 |
| PNP: 002e.5 |
| PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 |
| PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 |
| PNP: 002e.6 |
| PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.7 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.a |
| PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 2070 size 4 align 2 gran 2 limit 2073 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 2074 size 4 align 2 gran 2 limit 2077 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 2040 size 20 align 5 gran 5 limit 205f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base e0614000 size 800 align 12 gran 11 limit e06147ff flags 60000200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base e0617000 size 100 align 12 gran 8 limit e06170ff flags 60000201 index 10 |
| PCI: 00:1f.4 |
| PCI: 00:1f.5 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2299218 exit 0 |
| POST: 0x74 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 1458/5000 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:01.0 bridge ctrl <- 0003 |
| PCI: 00:01.0 cmd <- 00 |
| PCI: 00:02.0 subsystem <- 1458/d000 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:14.0 subsystem <- 1458/5007 |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:16.0 subsystem <- 1458/5000 |
| PCI: 00:16.0 cmd <- 02 |
| PCI: 00:1a.0 subsystem <- 1458/5006 |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 1458/a002 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 1458/5000 |
| PCI: 00:1c.0 cmd <- 106 |
| PCI: 00:1c.4 bridge ctrl <- 0003 |
| PCI: 00:1c.4 subsystem <- 1458/5000 |
| PCI: 00:1c.4 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 1458/5006 |
| PCI: 00:1d.0 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0003 |
| PCI: 00:1e.0 cmd <- 100 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 1458/5001 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 1458/b005 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 1458/5001 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 02:00.0 cmd <- 02 |
| PCI: 03:00.0 subsystem <- 1458/e000 |
| PCI: 03:00.0 cmd <- 103 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 93275 exit 0 |
| POST: 0x75 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 1921 usecs |
| POST: 0x75 |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160 |
| Processing 10 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 00113e0a(001316a0) |
| Installing SMM handler to 0xc0000000 |
| Loading module at c0010000 with entry c001010c. filesize: 0xed0 memsize: 0x4ef0 |
| Processing 50 relocs. Offset value of 0xc0010000 |
| Loading module at c0008000 with entry c0008000. filesize: 0x160 memsize: 0x160 |
| Processing 10 relocs. Offset value of 0xc0008000 |
| SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at c0007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at c0007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at c0006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at c0006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at c0006400 rel16 0x1bfd |
| SMM Module: stub loaded at c0008000. Will call c001010c(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: PM1 |
| PM1_STS: PRBTNOR PWRBTN TMROF |
| GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 TCO_SCI |
| ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 |
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000023b600000 size 0x13b600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| MTRR: default type WB/UC MTRR counts: 3/10. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x00 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 4 cores, 2 threads per core |
| CPU: 0 has core 1 |
| CPU1: stack_base 0012b000, stack_end 0012bff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00 |
| Startup point 1. |
| Waiting for send to finish... |
| +Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| CPU: 0 has core 2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x01 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #1 initialized |
| CPU2: stack_base 0012a000, stack_end 0012aff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x02 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #2 initialized |
| CPU3: stack_base 00129000, stack_end 00129ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 4 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x03 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #3 initialized |
| CPU4: stack_base 00128000, stack_end 00128ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 4. |
| After apic_write. |
| In relocation handler: cpu 4 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0xbffff000 IEDBASE=0xc0400000 @ 0003fc00 |
| Sending STARTUP #2 to 4. |
| After apic_write. |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 5 |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x04 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #4 initialized |
| CPU5: stack_base 00127000, stack_end 00127ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 5. |
| After apic_write. |
| In relocation handler: cpu 5 |
| New SMBASE=0xbfffec00 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 5. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 6 |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x05 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #5 initialized |
| CPU6: stack_base 00126000, stack_end 00126ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 6. |
| After apic_write. |
| In relocation handler: cpu 6 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0xbfffe800 IEDBASE=0xc0400000 @ 0003fc00 |
| Sending STARTUP #2 to 6. |
| After apic_write. |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x06 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #6 initialized |
| CPU7: stack_base 00125000, stack_end 00125ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 7. |
| After apic_write. |
| In relocation handler: cpu 7 |
| New SMBASE=0xbfffe400 IEDBASE=0xc0400000 @ 0003fc00 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 7. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #7 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 700180 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local apic... apic_id: 0x07 done. |
| POST: 0x9b |
| Enabling VMX |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 3400 |
| CPU #7 initialized |
| All AP CPUs stopped (213381 loops) |
| CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cacc, stack used: 1332 bytes |
| CPU1: stack: 0012b000 - 0012c000, lowest used address 0012bc78, stack used: 904 bytes |
| CPU2: stack: 0012a000 - 0012b000, lowest used address 0012ac78, stack used: 904 bytes |
| CPU3: stack: 00129000 - 0012a000, lowest used address 00129c78, stack used: 904 bytes |
| CPU4: stack: 00128000 - 00129000, lowest used address 00128c78, stack used: 904 bytes |
| CPU5: stack: 00127000 - 00128000, lowest used address 00127c78, stack used: 904 bytes |
| CPU6: stack: 00126000 - 00127000, lowest used address 00126c78, stack used: 904 bytes |
| CPU7: stack: 00125000 - 00126000, lowest used address 00125c78, stack used: 904 bytes |
| CPU_CLUSTER: 0 init finished in 24301122 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG60. |
| Set BIOS_RESET_CPL |
| CPU TDP: 77 Watts |
| PCI: 00:00.0 init finished in 11130 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| PCI: 00:02.0 init finished in 10919 usecs |
| POST: 0x75 |
| PCI: 00:14.0 init ... |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 5241 usecs |
| POST: 0x75 |
| PCI: 00:16.0 init ... |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : YES |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Normal |
| ME: Current Operation State : M0 with UMA |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : Host Communication |
| ME: Power Management Event : Moff->Mx wake after an error |
| ME: Progress Phase State : Host communication established |
| ME: BIOS path: Normal |
| ME: Extend SHA-256: f0b1b87824433f0a421ddc0cf152d1cd3d2b5e3ce7a373b3333a70ce98dd821d |
| ME: MBP item header 00020103 |
| ME: MBP item header 00050102 |
| ME: MBP item header 00020501 |
| ME: MBP item header 00020201 |
| ME: MBP item header 02030101 |
| ME: MBP item header 02060301 |
| ME: MBP item header 02090401 |
| ME: mbp read OK after 1 cycles |
| ME: found version 8.1.30.1350 |
| ME Capability: Full Network manageability : disabled |
| ME Capability: Regular Network manageability : disabled |
| ME Capability: Manageability : enabled |
| ME Capability: Small business technology : enabled |
| ME Capability: Level III manageability : disabled |
| ME Capability: IntelR Anti-Theft (AT) : enabled |
| ME Capability: IntelR Capability Licensing Service (CLS) : enabled |
| ME Capability: IntelR Power Sharing Technology (MPC) : enabled |
| ME Capability: ICC Over Clocking : enabled |
| ME Capability: Protected Audio Video Path (PAVP) : enabled |
| ME Capability: IPV6 : disabled |
| ME Capability: KVM Remote Control (KVM) : disabled |
| ME Capability: Outbreak Containment Heuristic (OCH) : disabled |
| ME Capability: Virtual LAN (VLAN) : enabled |
| ME Capability: TLS : enabled |
| ME Capability: Wireless LAN (WLAN) : disabled |
| PCI: 00:16.0 init finished in 177781 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 5248 usecs |
| POST: 0x75 |
| PCI: 00:1b.0 init ... |
| Azalia: base = e0610000 |
| Azalia: codec_mask = 0c |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: No verb! |
| Azalia: Initializing codec #2 |
| Azalia: codec viddid: 10ec0887 |
| Azalia: No verb! |
| PCI: 00:1b.0 init finished in 22535 usecs |
| POST: 0x75 |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 4710 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1c.4 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.4 init finished in 4710 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 5248 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| Set power off after power failure. |
| NMI sources disabled. |
| PantherPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 39221 usecs |
| POST: 0x75 |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| SATA: Controller in AHCI mode. |
| ABAR: e0614000 |
| PCI: 00:1f.2 init finished in 8264 usecs |
| POST: 0x75 |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 2012 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 2007 usecs |
| POST: 0x75 |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 2005 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PNP: 002e.1 init ... |
| PNP: 002e.1 init finished in 1919 usecs |
| POST: 0x75 |
| PNP: 002e.2 init ... |
| PNP: 002e.2 init finished in 1919 usecs |
| POST: 0x75 |
| PNP: 002e.3 init ... |
| PNP: 002e.3 init finished in 1919 usecs |
| POST: 0x75 |
| PNP: 002e.4 init ... |
| ITE IT8728F Super I/O HWM: Initializing Hardware Monitor.. |
| ITE IT8728F Super I/O HWM: Base Address at 0xa35 |
| PNP: 002e.4 init finished in 11494 usecs |
| POST: 0x75 |
| PNP: 002e.5 init ... |
| PNP: 002e.5 init finished in 1947 usecs |
| POST: 0x75 |
| PNP: 002e.6 init ... |
| PNP: 002e.6 init finished in 1918 usecs |
| POST: 0x75 |
| POST: 0x75 |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 02:00.0: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 5 run 24867283 exit 0 |
| POST: 0x76 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 6295 exit 0 |
| POST: 0x77 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1054 exit 0 |
| Updating MRC cache data. |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'mrc.cache' |
| CBFS: Found @ offset 7300c0 size 10000 |
| find_current_mrc_cache_local: picked entry 4 from cache block |
| SF: Detected W25Q64 with sector size 0x1000, total 0x800000 |
| find_next_mrc_cache: picked next entry from cache block at fff35100 |
| Finally: write MRC cache update to flash at fff35100 |
| POST: 0x79 |
| POST: 0x9c |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 706580 size 261c |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at bfeb9000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * IGD OpRegion |
| GET_VBIOS: 87b4 1a1b 29 fe b0 |
| VBIOS not found. |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| PSS: 3401MHz power 77000 control 0x2700 status 0x2700 |
| PSS: 3400MHz power 77000 control 0x2200 status 0x2200 |
| PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00 |
| PSS: 2400MHz power 48259 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 38348 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 29132 control 0x1000 status 0x1000 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: * TCPA |
| TCPA log created at bfea6000 |
| ACPI: added table 3/32, length now 48 |
| ACPI: * MADT |
| ACPI: added table 4/32, length now 52 |
| current = bfebe200 |
| ACPI: * DMAR |
| ACPI: added table 5/32, length now 56 |
| current = bfebe2b0 |
| ACPI: * HPET |
| ACPI: added table 6/32, length now 60 |
| ACPI: done. |
| ACPI tables: 21232 bytes. |
| smbios_write_tables: bfea5000 |
| Root Device (GIGABYTE GA-B75M-D3H) |
| CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| APIC: 00 (unknown) |
| APIC: acac (Intel SandyBridge/IvyBridge CPU) |
| DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 03:00.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PNP: 002e.0 (ITE IT8728F Super I/O) |
| PNP: 002e.1 (ITE IT8728F Super I/O) |
| PNP: 002e.2 (ITE IT8728F Super I/O) |
| PNP: 002e.3 (ITE IT8728F Super I/O) |
| PNP: 002e.4 (ITE IT8728F Super I/O) |
| PNP: 002e.5 (ITE IT8728F Super I/O) |
| PNP: 002e.6 (ITE IT8728F Super I/O) |
| PNP: 002e.7 (ITE IT8728F Super I/O) |
| PNP: 002e.a (ITE IT8728F Super I/O) |
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 02:00.0 (unknown) |
| APIC: 01 (unknown) |
| APIC: 02 (unknown) |
| APIC: 03 (unknown) |
| APIC: 04 (unknown) |
| APIC: 05 (unknown) |
| APIC: 06 (unknown) |
| APIC: 07 (unknown) |
| SMBIOS tables: 355 bytes. |
| POST: 0x9e |
| POST: 0x9d |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6ff4 |
| Table forward entry ends at 0x00000528. |
| ... aligned to 0x00001000 |
| Writing coreboot table at 0xbfe9d000 |
| rom_table_end = 0xbfe9d000 |
| ... aligned to 0xbfea0000 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-00000000bfe9cfff: RAM |
| 4. 00000000bfe9d000-00000000bfffffff: CONFIGURATION TABLES |
| 5. 00000000c0000000-00000000c29fffff: RESERVED |
| 6. 00000000f0000000-00000000f3ffffff: RESERVED |
| 7. 00000000fed90000-00000000fed91fff: RESERVED |
| 8. 0000000100000000-000000023b5fffff: RAM |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| No FMAP found at 0 offset. |
| Wrote coreboot table at: bfe9d000, 0x2f0 bytes, checksum 925f |
| coreboot table: 776 bytes. |
| IMD ROOT 0. bffff000 00001000 |
| IMD SMALL 1. bfffe000 00001000 |
| CONSOLE 2. bffde000 00020000 |
| MRC DATA 3. bffdd000 00000420 |
| ACPI RESUME 4. bfedd000 00100000 |
| ACPI 5. bfeb9000 00024000 |
| ACPI GNVS 6. bfeb8000 00001000 |
| 4f444749 7. bfeb6000 00002000 |
| TCPA LOG 8. bfea6000 00010000 |
| SMBIOS 9. bfea5000 00000800 |
| COREBOOT 10. bfe9d000 00008000 |
| IMD small region: |
| IMD ROOT 0. bfffec00 00000400 |
| CAR GLOBALS 1. bfffeac0 00000140 |
| ROMSTAGE 2. bfffeaa0 00000004 |
| GDT 3. bfffe8a0 00000200 |
| BS: BS_WRITE_TABLES times (us): entry 2093317 run 4791474 exit 0 |
| POST: 0x7a |
| CBFS: 'Master Header Locator' located CBFS at [0:7fffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 721180 size ed70 |
| Loading segment from rom address 0xfff211b8 |
| code (compression=1) |
| New segment dstaddr 0xe44a4 memsize 0x1bb5c srcaddr 0xfff211f0 filesize 0xed38 |
| Loading segment from rom address 0xfff211d4 |
| Entry Point 0x000ff06e |
| Payload being loaded below 1MiB without region being marked as RAM usable. |
| Bounce Buffer at bfe32000, 437792 bytes |
| Loading Segment: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38 |
| lb: [0x0000000000100000, 0x0000000000135710) |
| Post relocation: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38 |
| using LZMA |
| [ 0x000e44a4, 00100000, 0x00100000) <- fff211f0 |
| dest 000e44a4, end 00100000, bouncebuffer bfe32000 |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2147231 exit 0 |
| POST: 0x7b |
| PCH watchdog disabled |
| Jumping to boot code at 000ff06e(bfe9d000) |
| POST: 0xf8 |
| CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cacc, stack used: 1332 bytes |
| entry = 0x000ff06e |
| lb_start = 0x00100000 |
| lb_size = 0x00035710 |
| buffer = 0xbfe32000 |
| SeaBIOS (version rel-1.9.0-0-g01a84be) |
| BUILD: gcc: (coreboot toolchain v1.31 June 17th, 2015) 4.9.2 binutils: (GNU Binutils) 2.25 |
| Found coreboot cbmem console @ bffde000 |
| Found mainboard GIGABYTE GA-B75M-D3H |
| Relocating init from 0x000e58b0 to 0xbfe51ed0 (size 45216) |
| Found CBFS header at 0xfff00138 |
| multiboot: eax=0, ebx=0 |
| Found 16 PCI devices (max PCI bus is 04) |
| Copying SMBIOS entry point from 0xbfea5000 to 0x000f0930 |
| Copying ACPI RSDP from 0xbfeb9000 to 0x000f0900 |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| XHCI init on dev 00:14.0: regs @ 0xe0600000, 8 ports, 32 slots, 32 byte contexts |
| XHCI protocol USB 2.00, 4 ports (offset 1), def 3001 |
| XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 |
| XHCI extcap 0xc1 @ e0608040 |
| XHCI extcap 0xc0 @ e0608070 |
| XHCI extcap 0x1 @ e0608330 |
| XHCI init on dev 02:00.0: regs @ 0xe0400000, 5 ports, 16 slots, 32 byte contexts |
| XHCI extcap 0x1 @ e04000a0 |
| XHCI protocol USB 2.00, 1 ports (offset 1), def 6 |
| XHCI protocol USB 3.00, 4 ports (offset 2), def 0 |
| Found 0 lpt ports |
| Found 1 serial ports |
| AHCI controller at 1f.2, iobase e0614000, irq 10 |
| EHCI init on dev 00:1a.0 (regs=0xe0615020) |
| EHCI init on dev 00:1d.0 (regs=0xe0616020) |
| Got ps2 nak (status=51) |
| XHCI port #1: 0x40200e03, powered, enabled, pls 0, speed 3 [High] |
| XHCI no devices found |
| Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@3/*@0/*@0,0 |
| Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@3 |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@3/disk@0 |
| AHCI/3: registering: "DVD/CD [AHCI/3: ASUS BC-12B1ST ATAPI-8 DVD/CD]" |
| USB mouse initialized |
| USB keyboard initialized |
| Initialized USB HUB (0 ports used) |
| XHCI no devices found |
| Initialized USB HUB (2 ports used) |
| USB MSC vendor='SanDisk' product='Extreme' rev='0001' type=0 removable=0 |
| USB MSC blksize=512 sectors=31277232 |
| Initialized USB HUB (1 ports used) |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f08b0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=31277232 |
| Space available for UMB: c0000-ee000, f0000-f0830 |
| Returned 53248 bytes of ZoneHigh |
| e820 map has 8 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 00000000bfe6a000 = 1 RAM |
| 4: 00000000bfe6a000 - 00000000c2a00000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED |
| 7: 0000000100000000 - 000000023b600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from DVD/CD... |
| Device reports MEDIUM NOT PRESENT |
| scsi_is_ready returned -1 |
| Boot failed: Could not read from CDROM (code 0003) |
| enter handle_18: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |