| coreboot-4.0-5457-gca4f4b8 Son Feb 9 22:25:37 CET 2014 starting... | |
| Setting up static southbridge registers... done. | |
| Disabling Watchdog reboot... done. | |
| Setting up static northbridge registers... done. | |
| Initializing Graphics... | |
| Back from sandybridge_early_initialization() | |
| SMBus controller enabled. | |
| CPU id(306a9): Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz | |
| AES supported, TXT supported, VT supported | |
| PCH type: QM77, device id: 1e55, rev id 4 | |
| Intel ME early init | |
| Intel ME firmware is ready | |
| ME: Requested 32MB UMA | |
| Starting UEFI PEI System Agent | |
| Read scrambler seed 0x0000465d from CMOS 0x70 | |
| Read S3 scrambler seed 0x0000e2e2 from CMOS 0x74 | |
| CBFS: ERROR: No file header found at 0xbff480 - try next aligned address: 0xbff4c0. | |
| CBFS: ERROR: No file header found at 0xbff4c0 - try next aligned address: 0xbff500. | |
| CBFS: WARNING: 'mrc.cache' not found. | |
| CBFS: Could not find file 'mrc.cache'. | |
| find_current_mrc_cache: could not find MRC cache area | |
| System Agent: Starting up... | |
| System Agent: Initializing PCH | |
| System Agent: Initializing PCH (SMBUS) | |
| System Agent: Initializing PCH (USB) | |
| System Agent: Initializing PCH (SA Init) | |
| SA PciExpress skipped (pcie_init is 0) | |
| System Agent: Initializing PCH (Me UMA) | |
| System Agent: Initializing Memory | |
| System Agent: Done. | |
| System Agent Version 1.6.0 Build 0 | |
| ME: FW Partition Table : OK | |
| ME: Bringup Loader Failure : NO | |
| ME: Firmware Init Complete : NO | |
| ME: Manufacturing Mode : NO | |
| ME: Boot Options Present : NO | |
| ME: Update In Progress : NO | |
| ME: Current Working State : Normal | |
| ME: Current Operation State : Bring up | |
| ME: Current Operation Mode : Normal | |
| ME: Error Code : No Error | |
| ME: Progress Phase : BUP Phase | |
| ME: Power Management Event : Clean Moff->Mx wake | |
| ME: Progress Phase State : 0x50 | |
| memcfg DDR3 clock 1600 MHz | |
| memcfg channel assignment: A: 0, B 1, C 2 | |
| memcfg channel[0] config (00620020): | |
| ECC inactive | |
| enhanced interleave mode on | |
| rank interleave on | |
| DIMMA 8192 MB width x8 dual rank, selected | |
| DIMMB 0 MB width x8 single rank | |
| memcfg channel[1] config (00620020): | |
| ECC inactive | |
| enhanced interleave mode on | |
| rank interleave on | |
| DIMMA 8192 MB width x8 dual rank, selected | |
| DIMMB 0 MB width x8 single rank | |
| CBMEM region aced0000-acffffff (cbmem_check_toc) | |
| CBMEM region aced0000-acffffff (cbmem_initialize_empty) | |
| Adding CBMEM entry as no. 1 | |
| Adding CBMEM entry as no. 2 | |
| Adding CBMEM entry as no. 3 | |
| Adding CBMEM entry as no. 4 | |
| Relocate MRC DATA from ff7e3237 to acee0600 (2992 bytes) | |
| Save scrambler seed 0x00008f5f to CMOS 0x70 | |
| Save s3 scrambler seed 0x0000597e to CMOS 0x74 | |
| Loading image. | |
| CBFS: loading stage fallback/coreboot_ram @ 0x100000 (569400 bytes), entry @ 0x100000 | |
| Jumping to image. | |
| coreboot-4.0-5457-gca4f4b8 Son Feb 9 22:25:37 CET 2014 booting... | |
| BS: Entering BS_PRE_DEVICE state. | |
| BS: Exiting BS_PRE_DEVICE state. | |
| BS: Entering BS_DEV_INIT_CHIPS state. | |
| BS: Exiting BS_DEV_INIT_CHIPS state. | |
| BS: Entering BS_DEV_ENUMERATE state. | |
| Enumerating buses... | |
| Show all devs...Before device enumeration. | |
| Root Device: enabled 1 | |
| CPU_CLUSTER: 0: enabled 1 | |
| APIC: 00: enabled 1 | |
| APIC: acac: enabled 0 | |
| DOMAIN: 0000: enabled 1 | |
| PCI: 00:00.0: enabled 1 | |
| PCI: 00:01.0: enabled 0 | |
| PCI: 00:02.0: enabled 1 | |
| PCI: 00:14.0: enabled 1 | |
| PCI: 00:16.0: enabled 1 | |
| PCI: 00:16.1: enabled 0 | |
| PCI: 00:16.2: enabled 0 | |
| PCI: 00:16.3: enabled 0 | |
| PCI: 00:19.0: enabled 1 | |
| PCI: 00:1a.0: enabled 1 | |
| PCI: 00:1b.0: enabled 1 | |
| PCI: 00:1c.0: enabled 1 | |
| PCI: 00:1c.1: enabled 1 | |
| PCI: 00:1c.2: enabled 1 | |
| PCI: 00:1c.3: enabled 0 | |
| PCI: 00:1c.4: enabled 0 | |
| PCI: 00:1c.5: enabled 0 | |
| PCI: 00:1c.6: enabled 0 | |
| PCI: 00:1c.7: enabled 0 | |
| PCI: 00:1d.0: enabled 1 | |
| PCI: 00:1e.0: enabled 0 | |
| PCI: 00:1f.0: enabled 1 | |
| PNP: 00ff.1: enabled 1 | |
| PNP: 00ff.2: enabled 1 | |
| PCI: 00:1f.2: enabled 1 | |
| PCI: 00:1f.3: enabled 1 | |
| I2C: 00:54: enabled 1 | |
| I2C: 00:55: enabled 1 | |
| I2C: 00:56: enabled 1 | |
| I2C: 00:57: enabled 1 | |
| I2C: 00:5c: enabled 1 | |
| I2C: 00:5d: enabled 1 | |
| I2C: 00:5e: enabled 1 | |
| I2C: 00:5f: enabled 1 | |
| PCI: 00:1f.5: enabled 0 | |
| PCI: 00:1f.6: enabled 1 | |
| Compare with tree... | |
| Root Device: enabled 1 | |
| CPU_CLUSTER: 0: enabled 1 | |
| APIC: 00: enabled 1 | |
| APIC: acac: enabled 0 | |
| DOMAIN: 0000: enabled 1 | |
| PCI: 00:00.0: enabled 1 | |
| PCI: 00:01.0: enabled 0 | |
| PCI: 00:02.0: enabled 1 | |
| PCI: 00:14.0: enabled 1 | |
| PCI: 00:16.0: enabled 1 | |
| PCI: 00:16.1: enabled 0 | |
| PCI: 00:16.2: enabled 0 | |
| PCI: 00:16.3: enabled 0 | |
| PCI: 00:19.0: enabled 1 | |
| PCI: 00:1a.0: enabled 1 | |
| PCI: 00:1b.0: enabled 1 | |
| PCI: 00:1c.0: enabled 1 | |
| PCI: 00:1c.1: enabled 1 | |
| PCI: 00:1c.2: enabled 1 | |
| PCI: 00:1c.3: enabled 0 | |
| PCI: 00:1c.4: enabled 0 | |
| PCI: 00:1c.5: enabled 0 | |
| PCI: 00:1c.6: enabled 0 | |
| PCI: 00:1c.7: enabled 0 | |
| PCI: 00:1d.0: enabled 1 | |
| PCI: 00:1e.0: enabled 0 | |
| PCI: 00:1f.0: enabled 1 | |
| PNP: 00ff.1: enabled 1 | |
| PNP: 00ff.2: enabled 1 | |
| PCI: 00:1f.2: enabled 1 | |
| PCI: 00:1f.3: enabled 1 | |
| I2C: 00:54: enabled 1 | |
| I2C: 00:55: enabled 1 | |
| I2C: 00:56: enabled 1 | |
| I2C: 00:57: enabled 1 | |
| I2C: 00:5c: enabled 1 | |
| I2C: 00:5d: enabled 1 | |
| I2C: 00:5e: enabled 1 | |
| I2C: 00:5f: enabled 1 | |
| PCI: 00:1f.5: enabled 0 | |
| PCI: 00:1f.6: enabled 1 | |
| scan_static_bus for Root Device | |
| CPU_CLUSTER: 0 enabled | |
| DOMAIN: 0000 enabled | |
| DOMAIN: 0000 scanning... | |
| PCI: pci_scan_bus for bus 00 | |
| PCI: 00:00.0 [8086/0154] ops | |
| Normal boot. | |
| PCI: 00:00.0 [8086/0154] enabled | |
| PCI: 00:02.0 [8086/0000] ops | |
| PCI: 00:02.0 [8086/0166] enabled | |
| PCI: 00:14.0 [8086/0000] ops | |
| PCI: 00:14.0 [8086/1e31] enabled | |
| PCI: 00:16.0 [8086/1e3a] bus ops | |
| PCI: 00:16.0 [8086/1e3a] enabled | |
| PCI: 00:16.1: Disabling device | |
| PCI: 00:16.1 [8086/1e3b] disabled No operations | |
| PCI: 00:16.2: Disabling device | |
| PCI: 00:16.2 [8086/1e3c] disabled No operations | |
| PCI: 00:16.3: Disabling device | |
| PCI: 00:16.3 [8086/1e3d] disabled No operations | |
| PCI: 00:19.0 [8086/1502] enabled | |
| PCI: 00:1a.0 [8086/0000] ops | |
| PCI: 00:1a.0 [8086/1e2d] enabled | |
| PCI: 00:1b.0 [8086/0000] ops | |
| PCI: 00:1b.0 [8086/1e20] enabled | |
| PCH: PCIe Root Port coalescing is enabled | |
| PCI: 00:1c.0 [8086/0000] bus ops | |
| PCI: 00:1c.0 [8086/1e10] enabled | |
| PCI: 00:1c.1 [8086/0000] bus ops | |
| PCI: 00:1c.1 [8086/1e12] enabled | |
| PCI: 00:1c.2 [8086/0000] bus ops | |
| PCI: 00:1c.2 [8086/1e14] enabled | |
| PCI: 00:1c.3: Disabling device | |
| PCI: 00:1c.4: Disabling device | |
| PCI: 00:1c.4: check set enabled | |
| PCI: 00:1c.5: Disabling device | |
| PCI: 00:1c.6: Disabling device | |
| PCI: 00:1c.7: Disabling device | |
| PCH: RPFN 0x76543210 -> 0xfedcb210 | |
| PCI: 00:1d.0 [8086/0000] ops | |
| PCI: 00:1d.0 [8086/1e26] enabled | |
| PCI: 00:1e.0: Disabling device | |
| PCI: 00:1f.0 [8086/0000] bus ops | |
| PCI: 00:1f.0 [8086/1e55] enabled | |
| PCI: 00:1f.2 [8086/0000] ops | |
| PCI: 00:1f.2 [8086/1e01] enabled | |
| PCI: 00:1f.3 [8086/0000] bus ops | |
| PCI: 00:1f.3 [8086/1e22] enabled | |
| PCI: 00:1f.5: Disabling device | |
| PCI: Static device PCI: 00:1f.6 not found, disabling it. | |
| scan_static_bus for PCI: 00:16.0 | |
| scan_static_bus for PCI: 00:16.0 done | |
| do_pci_scan_bridge for PCI: 00:1c.0 | |
| PCI: pci_scan_bus for bus 01 | |
| PCI: 01:00.0 [1180/e823] enabled | |
| PCI: 01:00.1 [1180/e232] enabled | |
| PCI: 01:00.2 [1180/e852] enabled | |
| PCI: pci_scan_bus returning with max=001 | |
| Capability: type 0x05 @ 0x50 | |
| Capability: type 0x01 @ 0x78 | |
| Capability: type 0x10 @ 0x80 | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L0s and L1 | |
| Capability: type 0x05 @ 0x50 | |
| Capability: type 0x01 @ 0x78 | |
| Capability: type 0x10 @ 0x80 | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L0s and L1 | |
| Capability: type 0x05 @ 0x50 | |
| Capability: type 0x01 @ 0x78 | |
| Capability: type 0x10 @ 0x80 | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L0s and L1 | |
| do_pci_scan_bridge returns max 1 | |
| do_pci_scan_bridge for PCI: 00:1c.1 | |
| PCI: pci_scan_bus for bus 02 | |
| PCI: 02:00.0 [8086/0085] enabled | |
| PCI: pci_scan_bus returning with max=002 | |
| Capability: type 0x01 @ 0xc8 | |
| Capability: type 0x05 @ 0xd0 | |
| Capability: type 0x10 @ 0xe0 | |
| Capability: type 0x10 @ 0x40 | |
| Enabling Common Clock Configuration | |
| ASPM: Enabled L1 | |
| do_pci_scan_bridge returns max 2 | |
| do_pci_scan_bridge for PCI: 00:1c.2 | |
| PCI: pci_scan_bus for bus 03 | |
| PCI: pci_scan_bus returning with max=003 | |
| do_pci_scan_bridge returns max 3 | |
| scan_static_bus for PCI: 00:1f.0 | |
| PNP: 00ff.1 enabled | |
| recv_ec_data: 0x47 | |
| recv_ec_data: 0x32 | |
| recv_ec_data: 0x48 | |
| recv_ec_data: 0x54 | |
| recv_ec_data: 0x33 | |
| recv_ec_data: 0x31 | |
| recv_ec_data: 0x57 | |
| recv_ec_data: 0x57 | |
| recv_ec_data: 0x16 | |
| recv_ec_data: 0x03 | |
| recv_ec_data: 0x00 | |
| recv_ec_data: 0x11 | |
| EC Firmware ID G2HT31WW-3.22, Version 0.01B | |
| recv_ec_data: 0x00 | |
| recv_ec_data: 0x90 | |
| recv_ec_data: 0x20 | |
| recv_ec_data: 0x30 | |
| recv_ec_data: 0x00 | |
| recv_ec_data: 0xa6 | |
| recv_ec_data: 0xe0 | |
| recv_ec_data: 0x70 | |
| PNP: 00ff.2 enabled | |
| scan_static_bus for PCI: 00:1f.0 done | |
| scan_static_bus for PCI: 00:1f.3 | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled | |
| scan_static_bus for PCI: 00:1f.3 done | |
| PCI: pci_scan_bus returning with max=003 | |
| scan_static_bus for Root Device done | |
| done | |
| BS: Exiting BS_DEV_ENUMERATE state. | |
| BS: Entering BS_DEV_RESOURCES state. | |
| found VGA at PCI: 00:02.0 | |
| Setting up VGA for PCI: 00:02.0 | |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 | |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device | |
| Allocating resources... | |
| Reading resources... | |
| Root Device read_resources bus 0 link: 0 | |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 | |
| APIC: 00 missing read_resources | |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done | |
| DOMAIN: 0000 read_resources bus 0 link: 0 | |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. | |
| PCI: 00:1c.0 read_resources bus 1 link: 0 | |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done | |
| PCI: 00:1c.1 read_resources bus 2 link: 0 | |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done | |
| PCI: 00:1c.2 read_resources bus 3 link: 0 | |
| PCI: 00:1c.2 read_resources bus 3 link: 0 done | |
| PCI: 00:1f.0 read_resources bus 0 link: 0 | |
| PNP: 00ff.1 missing read_resources | |
| PNP: 00ff.2 missing read_resources | |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done | |
| PCI: 00:1f.3 read_resources bus 1 link: 0 | |
| PCI: 00:1f.3 read_resources bus 1 link: 0 done | |
| DOMAIN: 0000 read_resources bus 0 link: 0 done | |
| Root Device read_resources bus 0 link: 0 done | |
| Done reading resources. | |
| Show resources in subtree (Root Device)...After reading. | |
| Root Device child on link 0 CPU_CLUSTER: 0 | |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 | |
| APIC: 00 | |
| APIC: acac | |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 | |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 | |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 | |
| PCI: 00:00.0 | |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf | |
| PCI: 00:01.0 | |
| PCI: 00:02.0 | |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 | |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 | |
| PCI: 00:14.0 | |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:16.0 | |
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:16.1 | |
| PCI: 00:16.2 | |
| PCI: 00:16.3 | |
| PCI: 00:19.0 | |
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 | |
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 | |
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 | |
| PCI: 00:1a.0 | |
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 | |
| PCI: 00:1b.0 | |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 | |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c | |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 | |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 | |
| PCI: 01:00.0 | |
| PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 | |
| PCI: 01:00.1 | |
| PCI: 01:00.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 | |
| PCI: 01:00.2 | |
| PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 | |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 | |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c | |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 | |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 | |
| PCI: 02:00.0 | |
| PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 | |
| PCI: 00:1c.2 | |
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c | |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 | |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 | |
| PCI: 00:1c.3 | |
| PCI: 00:1c.4 | |
| PCI: 00:1c.5 | |
| PCI: 00:1c.6 | |
| PCI: 00:1c.7 | |
| PCI: 00:1d.0 | |
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 | |
| PCI: 00:1e.0 | |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 | |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 | |
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 | |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 | |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 | |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 | |
| PNP: 00ff.1 | |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 | |
| PNP: 00ff.2 | |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 | |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 | |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 | |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 | |
| PCI: 00:1f.2 | |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 | |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 | |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 | |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c | |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 | |
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 | |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 | |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 | |
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10 | |
| I2C: 01:54 | |
| I2C: 01:55 | |
| I2C: 01:56 | |
| I2C: 01:57 | |
| I2C: 01:5c | |
| I2C: 01:5d | |
| I2C: 01:5e | |
| I2C: 01:5f | |
| PCI: 00:1f.5 | |
| PCI: 00:1f.6 | |
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff | |
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff | |
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done | |
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff | |
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done | |
| PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff | |
| PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done | |
| PCI: 00:02.0 20 * [0x0 - 0x3f] io | |
| PCI: 00:19.0 18 * [0x40 - 0x5f] io | |
| PCI: 00:1f.2 20 * [0x60 - 0x7f] io | |
| PCI: 00:1f.2 10 * [0x80 - 0x87] io | |
| PCI: 00:1f.2 18 * [0x88 - 0x8f] io | |
| PCI: 00:1f.2 14 * [0x90 - 0x93] io | |
| PCI: 00:1f.2 1c * [0x94 - 0x97] io | |
| DOMAIN: 0000 compute_resources_io: base: 98 size: 98 align: 6 gran: 0 limit: ffff done | |
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff | |
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff | |
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done | |
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff | |
| PCI: 01:00.0 10 * [0x0 - 0xff] mem | |
| PCI: 01:00.1 10 * [0x100 - 0x1ff] mem | |
| PCI: 01:00.2 10 * [0x200 - 0x2ff] mem | |
| PCI: 00:1c.0 compute_resources_mem: base: 300 size: 100000 align: 20 gran: 20 limit: ffffffff done | |
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff | |
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done | |
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff | |
| PCI: 02:00.0 10 * [0x0 - 0x1fff] mem | |
| PCI: 00:1c.1 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done | |
| PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff | |
| PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done | |
| PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff | |
| PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done | |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem | |
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem | |
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem | |
| PCI: 00:1c.1 20 * [0x10500000 - 0x105fffff] mem | |
| PCI: 00:19.0 10 * [0x10600000 - 0x1061ffff] mem | |
| PCI: 00:14.0 10 * [0x10620000 - 0x1062ffff] mem | |
| PCI: 00:1b.0 10 * [0x10630000 - 0x10633fff] mem | |
| PCI: 00:19.0 14 * [0x10634000 - 0x10634fff] mem | |
| PCI: 00:1f.2 24 * [0x10635000 - 0x106357ff] mem | |
| PCI: 00:1a.0 10 * [0x10635800 - 0x10635bff] mem | |
| PCI: 00:1d.0 10 * [0x10635c00 - 0x10635fff] mem | |
| PCI: 00:1f.3 10 * [0x10636000 - 0x106360ff] mem | |
| PCI: 00:16.0 10 * [0x10636100 - 0x1063610f] mem | |
| DOMAIN: 0000 compute_resources_mem: base: 10636110 size: 10636110 align: 28 gran: 0 limit: ffffffff done | |
| avoid_fixed_resources: DOMAIN: 0000 | |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff | |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff | |
| constrain_resources: DOMAIN: 0000 | |
| constrain_resources: PCI: 00:00.0 | |
| constrain_resources: PCI: 00:02.0 | |
| constrain_resources: PCI: 00:14.0 | |
| constrain_resources: PCI: 00:16.0 | |
| constrain_resources: PCI: 00:19.0 | |
| constrain_resources: PCI: 00:1a.0 | |
| constrain_resources: PCI: 00:1b.0 | |
| constrain_resources: PCI: 00:1c.0 | |
| constrain_resources: PCI: 01:00.0 | |
| constrain_resources: PCI: 01:00.1 | |
| constrain_resources: PCI: 01:00.2 | |
| constrain_resources: PCI: 00:1c.1 | |
| constrain_resources: PCI: 02:00.0 | |
| constrain_resources: PCI: 00:1c.2 | |
| constrain_resources: PCI: 00:1d.0 | |
| constrain_resources: PCI: 00:1f.0 | |
| constrain_resources: PNP: 00ff.1 | |
| constrain_resources: PNP: 00ff.2 | |
| skipping PNP: 00ff.2@60 fixed resource, size=0! | |
| skipping PNP: 00ff.2@62 fixed resource, size=0! | |
| skipping PNP: 00ff.2@64 fixed resource, size=0! | |
| skipping PNP: 00ff.2@66 fixed resource, size=0! | |
| constrain_resources: PCI: 00:1f.2 | |
| constrain_resources: PCI: 00:1f.3 | |
| constrain_resources: I2C: 01:54 | |
| constrain_resources: I2C: 01:55 | |
| constrain_resources: I2C: 01:56 | |
| constrain_resources: I2C: 01:57 | |
| constrain_resources: I2C: 01:5c | |
| constrain_resources: I2C: 01:5d | |
| constrain_resources: I2C: 01:5e | |
| constrain_resources: I2C: 01:5f | |
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff | |
| lim->base 0000167c lim->limit 0000ffff | |
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff | |
| lim->base 00000000 lim->limit efffffff | |
| Setting resources... | |
| DOMAIN: 0000 allocate_resources_io: base:167c size:98 align:6 gran:0 limit:ffff | |
| Assigned: PCI: 00:02.0 20 * [0x1800 - 0x183f] io | |
| Assigned: PCI: 00:19.0 18 * [0x1840 - 0x185f] io | |
| Assigned: PCI: 00:1f.2 20 * [0x1860 - 0x187f] io | |
| Assigned: PCI: 00:1f.2 10 * [0x1880 - 0x1887] io | |
| Assigned: PCI: 00:1f.2 18 * [0x1888 - 0x188f] io | |
| Assigned: PCI: 00:1f.2 14 * [0x1890 - 0x1893] io | |
| Assigned: PCI: 00:1f.2 1c * [0x1894 - 0x1897] io | |
| DOMAIN: 0000 allocate_resources_io: next_base: 1898 size: 98 align: 6 gran: 0 done | |
| PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff | |
| PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done | |
| PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff | |
| PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done | |
| PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff | |
| PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done | |
| DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10636110 align:28 gran:0 limit:efffffff | |
| Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem | |
| Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem | |
| Assigned: PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem | |
| Assigned: PCI: 00:1c.1 20 * [0xe0500000 - 0xe05fffff] mem | |
| Assigned: PCI: 00:19.0 10 * [0xe0600000 - 0xe061ffff] mem | |
| Assigned: PCI: 00:14.0 10 * [0xe0620000 - 0xe062ffff] mem | |
| Assigned: PCI: 00:1b.0 10 * [0xe0630000 - 0xe0633fff] mem | |
| Assigned: PCI: 00:19.0 14 * [0xe0634000 - 0xe0634fff] mem | |
| Assigned: PCI: 00:1f.2 24 * [0xe0635000 - 0xe06357ff] mem | |
| Assigned: PCI: 00:1a.0 10 * [0xe0635800 - 0xe0635bff] mem | |
| Assigned: PCI: 00:1d.0 10 * [0xe0635c00 - 0xe0635fff] mem | |
| Assigned: PCI: 00:1f.3 10 * [0xe0636000 - 0xe06360ff] mem | |
| Assigned: PCI: 00:16.0 10 * [0xe0636100 - 0xe063610f] mem | |
| DOMAIN: 0000 allocate_resources_mem: next_base: e0636110 size: 10636110 align: 28 gran: 0 done | |
| PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff | |
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done | |
| PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff | |
| Assigned: PCI: 01:00.0 10 * [0xe0400000 - 0xe04000ff] mem | |
| Assigned: PCI: 01:00.1 10 * [0xe0400100 - 0xe04001ff] mem | |
| Assigned: PCI: 01:00.2 10 * [0xe0400200 - 0xe04002ff] mem | |
| PCI: 00:1c.0 allocate_resources_mem: next_base: e0400300 size: 100000 align: 20 gran: 20 done | |
| PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff | |
| PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done | |
| PCI: 00:1c.1 allocate_resources_mem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff | |
| Assigned: PCI: 02:00.0 10 * [0xe0500000 - 0xe0501fff] mem | |
| PCI: 00:1c.1 allocate_resources_mem: next_base: e0502000 size: 100000 align: 20 gran: 20 done | |
| PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff | |
| PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done | |
| PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff | |
| PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done | |
| Root Device assign_resources, bus 0 link: 0 | |
| TOUUD 0x44e600000 TOLUD 0xafa00000 TOM 0x400000000 | |
| MEBASE 0x3fe000000 | |
| IGD decoded, subtracting 32M UMA and 2M GTT | |
| TSEG base 0xad000000 size 8M | |
| Available memory below 4GB: 2768M | |
| Available memory above 4GB: 13542M | |
| Adding PCIe config bar base=0xf0000000 size=0x4000000 | |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 | |
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> | |
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64 | |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 | |
| PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io | |
| PCI: 00:14.0 10 <- [0x00e0620000 - 0x00e062ffff] size 0x00010000 gran 0x10 mem64 | |
| PCI: 00:16.0 10 <- [0x00e0636100 - 0x00e063610f] size 0x00000010 gran 0x04 mem64 | |
| PCI: 00:19.0 10 <- [0x00e0600000 - 0x00e061ffff] size 0x00020000 gran 0x11 mem | |
| PCI: 00:19.0 14 <- [0x00e0634000 - 0x00e0634fff] size 0x00001000 gran 0x0c mem | |
| PCI: 00:19.0 18 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io | |
| PCI: 00:1a.0 10 <- [0x00e0635800 - 0x00e0635bff] size 0x00000400 gran 0x0a mem | |
| PCI: 00:1b.0 10 <- [0x00e0630000 - 0x00e0633fff] size 0x00004000 gran 0x0e mem64 | |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io | |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem | |
| PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem | |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 | |
| PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e04000ff] size 0x00000100 gran 0x08 mem | |
| PCI: 01:00.1 10 <- [0x00e0400100 - 0x00e04001ff] size 0x00000100 gran 0x08 mem | |
| PCI: 01:00.2 10 <- [0x00e0400200 - 0x00e04002ff] size 0x00000100 gran 0x08 mem | |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 | |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io | |
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem | |
| PCI: 00:1c.1 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 02 mem | |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 | |
| PCI: 02:00.0 10 <- [0x00e0500000 - 0x00e0501fff] size 0x00002000 gran 0x0d mem64 | |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 | |
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io | |
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem | |
| PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem | |
| PCI: 00:1d.0 10 <- [0x00e0635c00 - 0x00e0635fff] size 0x00000400 gran 0x0a mem | |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 | |
| PNP: 00ff.1 missing set_resources | |
| PNP: 00ff.2 missing set_resources | |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 | |
| PCI: 00:1f.2 10 <- [0x0000001880 - 0x0000001887] size 0x00000008 gran 0x03 io | |
| PCI: 00:1f.2 14 <- [0x0000001890 - 0x0000001893] size 0x00000004 gran 0x02 io | |
| PCI: 00:1f.2 18 <- [0x0000001888 - 0x000000188f] size 0x00000008 gran 0x03 io | |
| PCI: 00:1f.2 1c <- [0x0000001894 - 0x0000001897] size 0x00000004 gran 0x02 io | |
| PCI: 00:1f.2 20 <- [0x0000001860 - 0x000000187f] size 0x00000020 gran 0x05 io | |
| PCI: 00:1f.2 24 <- [0x00e0635000 - 0x00e06357ff] size 0x00000800 gran 0x0b mem | |
| PCI: 00:1f.3 10 <- [0x00e0636000 - 0x00e06360ff] size 0x00000100 gran 0x08 mem64 | |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 | |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 | |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 | |
| CBMEM region aced0000-acffffff (cbmem_late_set_table) | |
| Root Device assign_resources, bus 0 link: 0 | |
| Done setting resources. | |
| Show resources in subtree (Root Device)...After assigning values. | |
| Root Device child on link 0 CPU_CLUSTER: 0 | |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 | |
| APIC: 00 | |
| APIC: acac | |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 | |
| DOMAIN: 0000 resource base 167c size 98 align 6 gran 0 limit ffff flags 40040100 index 10000000 | |
| DOMAIN: 0000 resource base d0000000 size 10636110 align 28 gran 0 limit efffffff flags 40040200 index 10000100 | |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 | |
| DOMAIN: 0000 resource base 100000 size acf00000 align 0 gran 0 limit 0 flags e0004200 index 4 | |
| DOMAIN: 0000 resource base 100000000 size 34e600000 align 0 gran 0 limit 0 flags e0004200 index 5 | |
| DOMAIN: 0000 resource base ad000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 | |
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 | |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8 | |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9 | |
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a | |
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b | |
| PCI: 00:00.0 | |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf | |
| PCI: 00:01.0 | |
| PCI: 00:02.0 | |
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10 | |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 | |
| PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit ffff flags 60000100 index 20 | |
| PCI: 00:14.0 | |
| PCI: 00:14.0 resource base e0620000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 | |
| PCI: 00:16.0 | |
| PCI: 00:16.0 resource base e0636100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10 | |
| PCI: 00:16.1 | |
| PCI: 00:16.2 | |
| PCI: 00:16.3 | |
| PCI: 00:19.0 | |
| PCI: 00:19.0 resource base e0600000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 | |
| PCI: 00:19.0 resource base e0634000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14 | |
| PCI: 00:19.0 resource base 1840 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 | |
| PCI: 00:1a.0 | |
| PCI: 00:1a.0 resource base e0635800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 | |
| PCI: 00:1b.0 | |
| PCI: 00:1b.0 resource base e0630000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 | |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 | |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c | |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 | |
| PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 | |
| PCI: 01:00.0 | |
| PCI: 01:00.0 resource base e0400000 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 | |
| PCI: 01:00.1 | |
| PCI: 01:00.1 resource base e0400100 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 | |
| PCI: 01:00.2 | |
| PCI: 01:00.2 resource base e0400200 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 | |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 | |
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c | |
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 | |
| PCI: 00:1c.1 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 | |
| PCI: 02:00.0 | |
| PCI: 02:00.0 resource base e0500000 size 2000 align 13 gran 13 limit efffffff flags 60000201 index 10 | |
| PCI: 00:1c.2 | |
| PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c | |
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 | |
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 | |
| PCI: 00:1c.3 | |
| PCI: 00:1c.4 | |
| PCI: 00:1c.5 | |
| PCI: 00:1c.6 | |
| PCI: 00:1c.7 | |
| PCI: 00:1d.0 | |
| PCI: 00:1d.0 resource base e0635c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 | |
| PCI: 00:1e.0 | |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 | |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 | |
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 | |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 | |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 | |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 | |
| PNP: 00ff.1 | |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 | |
| PNP: 00ff.2 | |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 | |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 | |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 | |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 | |
| PCI: 00:1f.2 | |
| PCI: 00:1f.2 resource base 1880 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 | |
| PCI: 00:1f.2 resource base 1890 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 | |
| PCI: 00:1f.2 resource base 1888 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 | |
| PCI: 00:1f.2 resource base 1894 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c | |
| PCI: 00:1f.2 resource base 1860 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 | |
| PCI: 00:1f.2 resource base e0635000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24 | |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 | |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 | |
| PCI: 00:1f.3 resource base e0636000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10 | |
| I2C: 01:54 | |
| I2C: 01:55 | |
| I2C: 01:56 | |
| I2C: 01:57 | |
| I2C: 01:5c | |
| I2C: 01:5d | |
| I2C: 01:5e | |
| I2C: 01:5f | |
| PCI: 00:1f.5 | |
| PCI: 00:1f.6 | |
| Done allocating resources. | |
| BS: Exiting BS_DEV_RESOURCES state. | |
| BS: Entering BS_DEV_ENABLE state. | |
| Enabling resources... | |
| PCI: 00:00.0 subsystem <- 0000/0000 | |
| PCI: 00:00.0 cmd <- 06 | |
| PCI: 00:02.0 subsystem <- 0000/0000 | |
| PCI: 00:02.0 cmd <- 03 | |
| PCI: 00:14.0 subsystem <- 0000/0000 | |
| PCI: 00:14.0 cmd <- 102 | |
| PCI: 00:16.0 subsystem <- 0000/0000 | |
| PCI: 00:16.0 cmd <- 02 | |
| PCI: 00:19.0 subsystem <- 0000/0000 | |
| PCI: 00:19.0 cmd <- 103 | |
| PCI: 00:1a.0 subsystem <- 0000/0000 | |
| PCI: 00:1a.0 cmd <- 102 | |
| PCI: 00:1b.0 subsystem <- 0000/0000 | |
| PCI: 00:1b.0 cmd <- 102 | |
| PCI: 00:1c.0 bridge ctrl <- 0003 | |
| PCI: 00:1c.0 subsystem <- 0000/0000 | |
| PCI: 00:1c.0 cmd <- 106 | |
| PCI: 00:1c.1 bridge ctrl <- 0003 | |
| PCI: 00:1c.1 subsystem <- 0000/0000 | |
| PCI: 00:1c.1 cmd <- 106 | |
| PCI: 00:1c.2 bridge ctrl <- 0003 | |
| PCI: 00:1c.2 subsystem <- 0000/0000 | |
| PCI: 00:1c.2 cmd <- 100 | |
| PCI: 00:1d.0 subsystem <- 0000/0000 | |
| PCI: 00:1d.0 cmd <- 102 | |
| pch_decode_init | |
| PCI: 00:1f.0 subsystem <- 0000/0000 | |
| PCI: 00:1f.0 cmd <- 107 | |
| PCI: 00:1f.2 subsystem <- 0000/0000 | |
| PCI: 00:1f.2 cmd <- 03 | |
| PCI: 00:1f.3 subsystem <- 0000/0000 | |
| PCI: 00:1f.3 cmd <- 103 | |
| PCI: 01:00.0 cmd <- 06 | |
| PCI: 01:00.1 cmd <- 06 | |
| PCI: 01:00.2 cmd <- 06 | |
| PCI: 02:00.0 cmd <- 02 | |
| done. | |
| BS: Exiting BS_DEV_ENABLE state. | |
| BS: Entering BS_DEV_INIT state. | |
| Initializing devices... | |
| Root Device init | |
| Keyboard init... | |
| Keyboard controller output buffer result timeout | |
| Keyboard controller output buffer result timeout | |
| Keyboard controller output buffer result timeout | |
| Keyboard reset failed ACK: 0xaa | |
| CPU_CLUSTER: 0 init | |
| start_eip=0x00001000, code_size=0x00000031 | |
| Installing SMM handler to 0xad000000 | |
| Installing IED header to 0xad400000 | |
| Initializing SMM handler... ... pmbase = 0x0500 | |
| SMI_STS: MCSMI PM1 | |
| PM1_STS: WAK PWRBTN BM TMROF | |
| GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW | |
| ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 | |
| TCO_STS: | |
| ... raise SMI# | |
| Initializing CPU #0 | |
| CPU: vendor Intel device 306a9 | |
| CPU: family 06, model 3a, stepping 09 | |
| Enabling cache | |
| microcode: sig=0x306a9 pf=0x10 revision=0x17 | |
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz. | |
| MTRR: Physical address space: | |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 | |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 | |
| 0x00000000000c0000 - 0x00000000ad000000 size 0xacf40000 type 6 | |
| 0x00000000ad000000 - 0x00000000d0000000 size 0x23000000 type 0 | |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 | |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 | |
| 0x0000000100000000 - 0x000000044e600000 size 0x34e600000 type 6 | |
| MTRR addr 0x0-0x10 set to 6 type @ 0 | |
| MTRR addr 0x10-0x20 set to 6 type @ 1 | |
| MTRR addr 0x20-0x30 set to 6 type @ 2 | |
| MTRR addr 0x30-0x40 set to 6 type @ 3 | |
| MTRR addr 0x40-0x50 set to 6 type @ 4 | |
| MTRR addr 0x50-0x60 set to 6 type @ 5 | |
| MTRR addr 0x60-0x70 set to 6 type @ 6 | |
| MTRR addr 0x70-0x80 set to 6 type @ 7 | |
| MTRR addr 0x80-0x84 set to 6 type @ 8 | |
| MTRR addr 0x84-0x88 set to 6 type @ 9 | |
| MTRR addr 0x88-0x8c set to 6 type @ 10 | |
| MTRR addr 0x8c-0x90 set to 6 type @ 11 | |
| MTRR addr 0x90-0x94 set to 6 type @ 12 | |
| MTRR addr 0x94-0x98 set to 6 type @ 13 | |
| MTRR addr 0x98-0x9c set to 6 type @ 14 | |
| MTRR addr 0x9c-0xa0 set to 6 type @ 15 | |
| MTRR addr 0xa0-0xa4 set to 0 type @ 16 | |
| MTRR addr 0xa4-0xa8 set to 0 type @ 17 | |
| MTRR addr 0xa8-0xac set to 0 type @ 18 | |
| MTRR addr 0xac-0xb0 set to 0 type @ 19 | |
| MTRR addr 0xb0-0xb4 set to 0 type @ 20 | |
| MTRR addr 0xb4-0xb8 set to 0 type @ 21 | |
| MTRR addr 0xb8-0xbc set to 0 type @ 22 | |
| MTRR addr 0xbc-0xc0 set to 0 type @ 23 | |
| MTRR addr 0xc0-0xc1 set to 6 type @ 24 | |
| MTRR addr 0xc1-0xc2 set to 6 type @ 25 | |
| MTRR addr 0xc2-0xc3 set to 6 type @ 26 | |
| MTRR addr 0xc3-0xc4 set to 6 type @ 27 | |
| MTRR addr 0xc4-0xc5 set to 6 type @ 28 | |
| MTRR addr 0xc5-0xc6 set to 6 type @ 29 | |
| MTRR addr 0xc6-0xc7 set to 6 type @ 30 | |
| MTRR addr 0xc7-0xc8 set to 6 type @ 31 | |
| MTRR addr 0xc8-0xc9 set to 6 type @ 32 | |
| MTRR addr 0xc9-0xca set to 6 type @ 33 | |
| MTRR addr 0xca-0xcb set to 6 type @ 34 | |
| MTRR addr 0xcb-0xcc set to 6 type @ 35 | |
| MTRR addr 0xcc-0xcd set to 6 type @ 36 | |
| MTRR addr 0xcd-0xce set to 6 type @ 37 | |
| MTRR addr 0xce-0xcf set to 6 type @ 38 | |
| MTRR addr 0xcf-0xd0 set to 6 type @ 39 | |
| MTRR addr 0xd0-0xd1 set to 6 type @ 40 | |
| MTRR addr 0xd1-0xd2 set to 6 type @ 41 | |
| MTRR addr 0xd2-0xd3 set to 6 type @ 42 | |
| MTRR addr 0xd3-0xd4 set to 6 type @ 43 | |
| MTRR addr 0xd4-0xd5 set to 6 type @ 44 | |
| MTRR addr 0xd5-0xd6 set to 6 type @ 45 | |
| MTRR addr 0xd6-0xd7 set to 6 type @ 46 | |
| MTRR addr 0xd7-0xd8 set to 6 type @ 47 | |
| MTRR addr 0xd8-0xd9 set to 6 type @ 48 | |
| MTRR addr 0xd9-0xda set to 6 type @ 49 | |
| MTRR addr 0xda-0xdb set to 6 type @ 50 | |
| MTRR addr 0xdb-0xdc set to 6 type @ 51 | |
| MTRR addr 0xdc-0xdd set to 6 type @ 52 | |
| MTRR addr 0xdd-0xde set to 6 type @ 53 | |
| MTRR addr 0xde-0xdf set to 6 type @ 54 | |
| MTRR addr 0xdf-0xe0 set to 6 type @ 55 | |
| MTRR addr 0xe0-0xe1 set to 6 type @ 56 | |
| MTRR addr 0xe1-0xe2 set to 6 type @ 57 | |
| MTRR addr 0xe2-0xe3 set to 6 type @ 58 | |
| MTRR addr 0xe3-0xe4 set to 6 type @ 59 | |
| MTRR addr 0xe4-0xe5 set to 6 type @ 60 | |
| MTRR addr 0xe5-0xe6 set to 6 type @ 61 | |
| MTRR addr 0xe6-0xe7 set to 6 type @ 62 | |
| MTRR addr 0xe7-0xe8 set to 6 type @ 63 | |
| MTRR addr 0xe8-0xe9 set to 6 type @ 64 | |
| MTRR addr 0xe9-0xea set to 6 type @ 65 | |
| MTRR addr 0xea-0xeb set to 6 type @ 66 | |
| MTRR addr 0xeb-0xec set to 6 type @ 67 | |
| MTRR addr 0xec-0xed set to 6 type @ 68 | |
| MTRR addr 0xed-0xee set to 6 type @ 69 | |
| MTRR addr 0xee-0xef set to 6 type @ 70 | |
| MTRR addr 0xef-0xf0 set to 6 type @ 71 | |
| MTRR addr 0xf0-0xf1 set to 6 type @ 72 | |
| MTRR addr 0xf1-0xf2 set to 6 type @ 73 | |
| MTRR addr 0xf2-0xf3 set to 6 type @ 74 | |
| MTRR addr 0xf3-0xf4 set to 6 type @ 75 | |
| MTRR addr 0xf4-0xf5 set to 6 type @ 76 | |
| MTRR addr 0xf5-0xf6 set to 6 type @ 77 | |
| MTRR addr 0xf6-0xf7 set to 6 type @ 78 | |
| MTRR addr 0xf7-0xf8 set to 6 type @ 79 | |
| MTRR addr 0xf8-0xf9 set to 6 type @ 80 | |
| MTRR addr 0xf9-0xfa set to 6 type @ 81 | |
| MTRR addr 0xfa-0xfb set to 6 type @ 82 | |
| MTRR addr 0xfb-0xfc set to 6 type @ 83 | |
| MTRR addr 0xfc-0xfd set to 6 type @ 84 | |
| MTRR addr 0xfd-0xfe set to 6 type @ 85 | |
| MTRR addr 0xfe-0xff set to 6 type @ 86 | |
| MTRR addr 0xff-0x100 set to 6 type @ 87 | |
| MTRR: Fixed MSR 0x250 0x0606060606060606 | |
| MTRR: Fixed MSR 0x258 0x0606060606060606 | |
| MTRR: Fixed MSR 0x259 0x0000000000000000 | |
| MTRR: Fixed MSR 0x268 0x0606060606060606 | |
| MTRR: Fixed MSR 0x269 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 | |
| call enable_fixed_mtrr() | |
| MTRR: default type WB/UC MTRR counts: 6/13. | |
| MTRR: WB selected as default type. | |
| MTRR: 0 base 0x00000000ad000000 mask 0x0000000fff000000 type 0 | |
| MTRR: 1 base 0x00000000ae000000 mask 0x0000000ffe000000 type 0 | |
| MTRR: 2 base 0x00000000b0000000 mask 0x0000000ff0000000 type 0 | |
| MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 | |
| MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 | |
| MTRR: 5 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 | |
| MTRR check | |
| Fixed MTRRs : Enabled | |
| Variable MTRRs: Enabled | |
| Setting up local apic... apic_id: 0x00 done. | |
| Enabling VMX | |
| model_x06ax: energy policy set to 6 | |
| model_x06ax: frequency set to 2800 | |
| Turbo is available but hidden | |
| Turbo has been enabled | |
| CPU: 0 has 2 cores, 2 threads per core | |
| CPU: 0 has core 1 | |
| CPU1: stack_base 00185000, stack_end 00185ff8 | |
| Asserting INIT. | |
| Waiting for send to finish... | |
| +Deasserting INIT. | |
| Waiting for send to finish... | |
| +#startup loops: 2. | |
| Sending STARTUP #1 to 1. | |
| After apic_write. | |
| Initializing CPU #1 | |
| Startup point 1. | |
| CPU: vendor Intel device 306a9 | |
| Waiting for send to finish... | |
| CPU: family 06, model 3a, stepping 09 | |
| +Enabling cache | |
| Sending STARTUP #2 to 1. | |
| After apic_write. | |
| microcode: sig=0x306a9 pf=0x10 revision=0x17 | |
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz. | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +After Startup. | |
| MTRR: Fixed MSR 0x250 0x0606060606060606 | |
| CPU: 0 has core 2 | |
| MTRR: Fixed MSR 0x258 0x0606060606060606 | |
| CPU2: stack_base 00184000, stack_end 00184ff8 | |
| MTRR: Fixed MSR 0x259 0x0000000000000000 | |
| MTRR: Fixed MSR 0x268 0x0606060606060606 | |
| MTRR: Fixed MSR 0x269 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 | |
| Asserting INIT. | |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 | |
| Waiting for send to finish... | |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 | |
| +MTRR: Fixed MSR 0x26f 0x0606060606060606 | |
| call enable_fixed_mtrr() | |
| MTRR: 0 base 0x00000000ad000000 mask 0x0000000fff000000 type 0 | |
| MTRR: 1 base 0x00000000ae000000 mask 0x0000000ffe000000 type 0 | |
| MTRR: 2 base 0x00000000b0000000 mask 0x0000000ff0000000 type 0 | |
| MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 | |
| Deasserting INIT. | |
| MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 | |
| Waiting for send to finish... | |
| MTRR: 5 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 | |
| + | |
| MTRR check | |
| Fixed MTRRs : Enabled | |
| Variable MTRRs: Enabled | |
| Setting up local apic... apic_id: 0x01 done. | |
| Enabling VMX | |
| model_x06ax: energy policy set to 6 | |
| model_x06ax: frequency set to 2800 | |
| CPU #1 initialized | |
| #startup loops: 2. | |
| Sending STARTUP #1 to 2. | |
| After apic_write. | |
| Initializing CPU #2 | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +CPU: vendor Intel device 306a9 | |
| Sending STARTUP #2 to 2. | |
| After apic_write. | |
| CPU: family 06, model 3a, stepping 09 | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +Enabling cache | |
| After Startup. | |
| CPU: 0 has core 3 | |
| CPU3: stack_base 00183000, stack_end 00183ff8 | |
| Asserting INIT. | |
| Waiting for send to finish... | |
| +microcode: sig=0x306a9 pf=0x10 revision=0x0 | |
| microcode: updated to revision 0x17 date=2013-01-09 | |
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz. | |
| MTRR: Fixed MSR 0x250 0x0606060606060606 | |
| MTRR: Fixed MSR 0x258 0x0606060606060606 | |
| Deasserting INIT. | |
| Waiting for send to finish... | |
| +MTRR: Fixed MSR 0x259 0x0000000000000000 | |
| #startup loops: 2. | |
| Sending STARTUP #1 to 3. | |
| After apic_write. | |
| MTRR: Fixed MSR 0x268 0x0606060606060606 | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +Initializing CPU #3 | |
| Sending STARTUP #2 to 3. | |
| After apic_write. | |
| MTRR: Fixed MSR 0x269 0x0606060606060606 | |
| Startup point 1. | |
| Waiting for send to finish... | |
| +CPU: vendor Intel device 306a9 | |
| After Startup. | |
| CPU #0 initialized | |
| Waiting for 2 CPUS to stop | |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 | |
| CPU: family 06, model 3a, stepping 09 | |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 | |
| Enabling cache | |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 | |
| microcode: sig=0x306a9 pf=0x10 revision=0x17 | |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 | |
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz. | |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 | |
| MTRR: Fixed MSR 0x250 0x0606060606060606 | |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 | |
| MTRR: Fixed MSR 0x258 0x0606060606060606 | |
| call enable_fixed_mtrr() | |
| MTRR: Fixed MSR 0x259 0x0000000000000000 | |
| MTRR: 0 base 0x00000000ad000000 mask 0x0000000fff000000 type 0 | |
| MTRR: Fixed MSR 0x268 0x0606060606060606 | |
| MTRR: 1 base 0x00000000ae000000 mask 0x0000000ffe000000 type 0 | |
| MTRR: Fixed MSR 0x269 0x0606060606060606 | |
| MTRR: 2 base 0x00000000b0000000 mask 0x0000000ff0000000 type 0 | |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 | |
| MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 | |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 | |
| MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 | |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 | |
| MTRR: 5 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 | |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 | |
| MTRR check | |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 | |
| Fixed MTRRs : MTRR: Fixed MSR 0x26f 0x0606060606060606 | |
| Enabled | |
| call enable_fixed_mtrr() | |
| Variable MTRRs: Enabled | |
| Setting up local apic... apic_id: 0x02 MTRR: 0 base 0x00000000ad000000 mask 0x0000000fff000000 type 0 | |
| done. | |
| MTRR: 1 base 0x00000000ae000000 mask 0x0000000ffe000000 type 0 | |
| Enabling VMX | |
| MTRR: 2 base 0x00000000b0000000 mask 0x0000000ff0000000 type 0 | |
| model_x06ax: energy policy set to 6 | |
| MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 | |
| model_x06ax: frequency set to 2800 | |
| MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 | |
| CPU #2 initialized | |
| MTRR: 5 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 | |
| Waiting for 1 CPUS to stop | |
| MTRR check | |
| Fixed MTRRs : Enabled | |
| Variable MTRRs: Enabled | |
| Setting up local apic... apic_id: 0x03 done. | |
| Enabling VMX | |
| model_x06ax: energy policy set to 6 | |
| model_x06ax: frequency set to 2800 | |
| CPU #3 initialized | |
| All AP CPUs stopped (6877 loops) | |
| CPU1: stack: 00185000 - 00186000, lowest used address 00185c9c, stack used: 868 bytes | |
| CPU2: stack: 00184000 - 00185000, lowest used address 00184c9c, stack used: 868 bytes | |
| CPU3: stack: 00183000 - 00184000, lowest used address 00183c9c, stack used: 868 bytes | |
| PCI: 00:00.0 init | |
| Set BIOS_RESET_CPL | |
| CPU TDP: 35 Watts | |
| PCI: 00:02.0 init | |
| GT Power Management Init | |
| IVB GT2 25W-35W Power Meter Weights | |
| In CBFS, ROM address for PCI: 00:02.0 = fff00778 | |
| PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 | |
| PCI ROM image, vendor ID 8086, device ID 0106, | |
| PCI ROM image, Class Code 030000, Code Type 00 | |
| Copying VGA ROM Image from fff00778 to 0xc0000, 0x10000 bytes | |
| int15_handler: INT15 function 5fac! | |
| Unknown INT15 function 5fac! | |
| int15_handler: INT15 function 5f40! | |
| Unknown INT15 function 5f40! | |
| int15_handler: INT15 function 5f35! | |
| GT Power Management Init (post VBIOS) | |
| PCI: 00:14.0 init | |
| XHCI: Setting up controller.. done. | |
| PCI: 00:16.0 init | |
| ME: FW Partition Table : OK | |
| ME: Bringup Loader Failure : NO | |
| ME: Firmware Init Complete : NO | |
| ME: Manufacturing Mode : NO | |
| ME: Boot Options Present : NO | |
| ME: Update In Progress : NO | |
| ME: Current Working State : Normal | |
| ME: Current Operation State : M0 with UMA | |
| ME: Current Operation Mode : Normal | |
| ME: Error Code : No Error | |
| ME: Progress Phase : Host Communication | |
| ME: Power Management Event : Clean Moff->Mx wake | |
| ME: Progress Phase State : Host communication established | |
| ME: BIOS path: Normal | |
| ME: Extend SHA-256: e4296030ae179336fc242e1a495f7121e9bea777ff01a32141277ff3e64e84b8 | |
| ME: MBP item header 00020103 | |
| ME: MBP item header 00050102 | |
| ME: MBP item header 00020501 | |
| ME: MBP item header 00020201 | |
| ME: MBP item header 00020104 | |
| ME: unknown mbp item id 0x104!!! | |
| PCI: 00:19.0 init | |
| PCI: 00:1a.0 init | |
| EHCI: Setting up controller.. done. | |
| PCI: 00:1b.0 init | |
| Azalia: base = e0630000 | |
| Azalia: codec_mask = 09 | |
| Azalia: Initializing codec #3 | |
| Azalia: codec viddid: 80862806 | |
| Azalia: verb_size: 16 | |
| Azalia: verb loaded. | |
| Azalia: Initializing codec #0 | |
| Azalia: codec viddid: 10ec0269 | |
| Azalia: verb_size: 500 | |
| Azalia: verb loaded. | |
| PCI: 00:1c.0 init | |
| Initializing PCH PCIe bridge. | |
| PCI: 00:1c.1 init | |
| Initializing PCH PCIe bridge. | |
| PCI: 00:1c.2 init | |
| Initializing PCH PCIe bridge. | |
| PCI: 00:1d.0 init | |
| EHCI: Setting up controller.. done. | |
| PCI: 00:1f.0 init | |
| pch: lpc_init | |
| IOAPIC: Initializing IOAPIC at 0xfec00000 | |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 | |
| IOAPIC: ID = 0x02 | |
| IOAPIC: Dumping registers | |
| reg 0x0000: 0x02000000 | |
| reg 0x0001: 0x00170020 | |
| reg 0x0002: 0x00170020 | |
| Set power off after power failure. | |
| NMI sources disabled. | |
| PantherPoint PM init | |
| rtc_failed = 0x0 | |
| RTC Init | |
| i8259_configure_irq_trigger: current interrupts are 0x0 | |
| i8259_configure_irq_trigger: try to set interrupts 0x200 | |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: | |
| done. | |
| Locking SMM. | |
| PCI: 00:1f.2 init | |
| SATA: Initializing... | |
| SATA: Controller in AHCI mode. | |
| ABAR: E0635000 | |
| PCI: 00:1f.3 init | |
| PCI: 01:00.0 init | |
| PCI: 01:00.1 init | |
| PCI: 01:00.2 init | |
| PCI: 02:00.0 init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init | |
| Locking EEPROM RFID | |
| init EEPROM done | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init | |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init | |
| Devices initialized | |
| Show all devs...After init. | |
| Root Device: enabled 1 | |
| CPU_CLUSTER: 0: enabled 1 | |
| APIC: 00: enabled 1 | |
| APIC: acac: enabled 0 | |
| DOMAIN: 0000: enabled 1 | |
| PCI: 00:00.0: enabled 1 | |
| PCI: 00:01.0: enabled 0 | |
| PCI: 00:02.0: enabled 1 | |
| PCI: 00:14.0: enabled 1 | |
| PCI: 00:16.0: enabled 1 | |
| PCI: 00:16.1: enabled 0 | |
| PCI: 00:16.2: enabled 0 | |
| PCI: 00:16.3: enabled 0 | |
| PCI: 00:19.0: enabled 1 | |
| PCI: 00:1a.0: enabled 1 | |
| PCI: 00:1b.0: enabled 1 | |
| PCI: 00:1c.0: enabled 1 | |
| PCI: 00:1c.1: enabled 1 | |
| PCI: 00:1c.2: enabled 1 | |
| PCI: 00:1c.3: enabled 0 | |
| PCI: 00:1c.4: enabled 0 | |
| PCI: 00:1c.5: enabled 0 | |
| PCI: 00:1c.6: enabled 0 | |
| PCI: 00:1c.7: enabled 0 | |
| PCI: 00:1d.0: enabled 1 | |
| PCI: 00:1e.0: enabled 0 | |
| PCI: 00:1f.0: enabled 1 | |
| PNP: 00ff.1: enabled 1 | |
| PNP: 00ff.2: enabled 1 | |
| PCI: 00:1f.2: enabled 1 | |
| PCI: 00:1f.3: enabled 1 | |
| I2C: 01:54: enabled 1 | |
| I2C: 01:55: enabled 1 | |
| I2C: 01:56: enabled 1 | |
| I2C: 01:57: enabled 1 | |
| I2C: 01:5c: enabled 1 | |
| I2C: 01:5d: enabled 1 | |
| I2C: 01:5e: enabled 1 | |
| I2C: 01:5f: enabled 1 | |
| PCI: 00:1f.5: enabled 0 | |
| PCI: 00:1f.6: enabled 0 | |
| PCI: 01:00.0: enabled 1 | |
| PCI: 01:00.1: enabled 1 | |
| PCI: 01:00.2: enabled 1 | |
| PCI: 02:00.0: enabled 1 | |
| APIC: 01: enabled 1 | |
| APIC: 02: enabled 1 | |
| APIC: 03: enabled 1 | |
| BS: Exiting BS_DEV_INIT state. | |
| BS: Entering BS_POST_DEVICE state. | |
| CBMEM region aced0000-acffffff (cbmem_check_toc) | |
| Adding CBMEM entry as no. 5 | |
| Moving GDT to acee1200...ok | |
| Finalize devices... | |
| Devices finalized | |
| BS: Exiting BS_POST_DEVICE state. | |
| BS: Entering BS_OS_RESUME_CHECK state. | |
| BS: Exiting BS_OS_RESUME_CHECK state. | |
| BS: Entering BS_WRITE_TABLES state. | |
| Updating MRC cache data. | |
| CBFS: ERROR: No file header found at 0xbff480 - try next aligned address: 0xbff4c0. | |
| CBFS: ERROR: No file header found at 0xbff4c0 - try next aligned address: 0xbff500. | |
| CBFS: WARNING: 'mrc.cache' not found. | |
| CBFS: Could not find file 'mrc.cache'. | |
| update_mrc_cache: could not find MRC cache area | |
| Adding CBMEM entry as no. 6 | |
| ACPI: Writing ACPI tables at acee1400. | |
| ACPI: * FACS | |
| ACPI: * DSDT | |
| ACPI: * FADT | |
| ACPI: added table 1/32, length now 40 | |
| ACPI: * HPET | |
| ACPI: added table 2/32, length now 44 | |
| ACPI: * MADT | |
| ACPI: added table 3/32, length now 48 | |
| ACPI: * MCFG | |
| ACPI: added table 4/32, length now 52 | |
| ACPI: Patching up global NVS in DSDT at offset 0x00a5 -> 0xacee4d60 | |
| Adding CBMEM entry as no. 7 | |
| ACPI: * DSDT @ acee1650 Length 351a | |
| ACPI: * SSDT | |
| Found 1 CPU(s) with 4 core(s) each. | |
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300 | |
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00 | |
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800 | |
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400 | |
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000 | |
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00 | |
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300 | |
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00 | |
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800 | |
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400 | |
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000 | |
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00 | |
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300 | |
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00 | |
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800 | |
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400 | |
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000 | |
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00 | |
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300 | |
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00 | |
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800 | |
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400 | |
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000 | |
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00 | |
| ACPI: added table 5/32, length now 56 | |
| current = acee6e50 | |
| ACPI: done. | |
| ACPI tables: 23120 bytes. | |
| Adding CBMEM entry as no. 8 | |
| smbios_write_tables: aceeca00 | |
| Root Device (LENOVO 2325TLU) | |
| CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| APIC: 00 (Socket rPGA989 CPU) | |
| APIC: acac (Intel SandyBridge/IvyBridge CPU) | |
| DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:01.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) | |
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7) | |
| PNP: 00ff.2 (Lenovo H8 EC) | |
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| I2C: 01:54 (AT24RF08C) | |
| I2C: 01:55 (AT24RF08C) | |
| I2C: 01:56 (AT24RF08C) | |
| I2C: 01:57 (AT24RF08C) | |
| I2C: 01:5c (AT24RF08C) | |
| I2C: 01:5d (AT24RF08C) | |
| I2C: 01:5e (AT24RF08C) | |
| I2C: 01:5f (AT24RF08C) | |
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) | |
| PCI: 01:00.0 (unknown) | |
| PCI: 01:00.1 (unknown) | |
| PCI: 01:00.2 (unknown) | |
| PCI: 02:00.0 (unknown) | |
| APIC: 01 (unknown) | |
| APIC: 02 (unknown) | |
| APIC: 03 (unknown) | |
| SMBIOS tables: 312 bytes. | |
| Adding CBMEM entry as no. 9 | |
| Adding CBMEM entry as no. 10 | |
| Writing table forward entry at 0x00000500 | |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 80df | |
| Table forward entry ends at 0x00000528. | |
| ... aligned to 0x00001000 | |
| Writing coreboot table at 0xacfed200 | |
| rom_table_end = 0xacfed200 | |
| ... aligned to 0xacff0000 | |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES | |
| 1. 0000000000001000-000000000009ffff: RAM | |
| 2. 00000000000a0000-00000000000fffff: RESERVED | |
| 3. 0000000000100000-000000001fffffff: RAM | |
| 4. 0000000020000000-00000000201fffff: RESERVED | |
| 5. 0000000020200000-000000003fffffff: RAM | |
| 6. 0000000040000000-00000000401fffff: RESERVED | |
| 7. 0000000040200000-00000000acecffff: RAM | |
| 8. 00000000aced0000-00000000acffffff: CONFIGURATION TABLES | |
| 9. 00000000ad000000-00000000af9fffff: RESERVED | |
| 10. 00000000f0000000-00000000f3ffffff: RESERVED | |
| 11. 0000000100000000-000000044e5fffff: RAM | |
| Wrote coreboot table at: acfed200, 0x954 bytes, checksum dbd8 | |
| coreboot table: 2412 bytes. | |
| FREE SPACE 0. acff5200 0000ae00 | |
| CAR GLOBALS 1. aced0200 00000200 | |
| CONSOLE 2. aced0400 00010000 | |
| TIME STAMP 3. acee0400 00000200 | |
| MRC DATA 4. acee0600 00000c00 | |
| GDT 5. acee1200 00000200 | |
| ACPI 6. acee1400 0000b400 | |
| GNVS PTR 7. aceec800 00000200 | |
| SMBIOS 8. aceeca00 00000800 | |
| ACPI RESUME 9. aceed200 00100000 | |
| COREBOOT 10. acfed200 00008000 | |
| BS: Exiting BS_WRITE_TABLES state. | |
| BS: Entering BS_PAYLOAD_LOAD state. | |
| Loading segment from rom address 0xfff38338 | |
| code (compression=1) | |
| New segment dstaddr 0x8200 memsize 0x17f34 srcaddr 0xfff3838c filesize 0x8495 | |
| (cleaned up) New segment addr 0x8200 size 0x17f34 offset 0xfff3838c filesize 0x8495 | |
| Loading segment from rom address 0xfff38354 | |
| code (compression=1) | |
| New segment dstaddr 0x100000 memsize 0xc0a90 srcaddr 0xfff40821 filesize 0x3be26 | |
| (cleaned up) New segment addr 0x100000 size 0xc0a90 offset 0xfff40821 filesize 0x3be26 | |
| Loading segment from rom address 0xfff38370 | |
| Entry Point 0x00008200 | |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017f34 filesz: 0x0000000000008495 | |
| lb: [0x0000000000100000, 0x000000000018b038) | |
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017f34 filesz: 0x0000000000008495 | |
| using LZMA | |
| [ 0x00008200, 000187fb, 0x00020134) <- fff3838c | |
| Clearing Segment: addr: 0x00000000000187fb memsz: 0x0000000000007939 | |
| dest 00008200, end 00020134, bouncebuffer acd84538 | |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000c0a90 filesz: 0x000000000003be26 | |
| lb: [0x0000000000100000, 0x000000000018b038) | |
| segment: [0x0000000000100000, 0x000000000013be26, 0x00000000001c0a90) | |
| bounce: [0x00000000acd84538, 0x00000000acdc035e, 0x00000000ace44fc8) | |
| Post relocation: addr: 0x00000000acd84538 memsz: 0x00000000000c0a90 filesz: 0x000000000003be26 | |
| using LZMA | |
| [ 0xacd84538, ace44fc8, 0xace44fc8) <- fff40821 | |
| dest acd84538, end ace44fc8, bouncebuffer acd84538 | |
| move suffix around: from ace0f570, to 18b038, amount: 35a58 | |
| Loaded segments | |
| BS: Exiting BS_PAYLOAD_LOAD state. | |
| BS: Entering BS_PAYLOAD_BOOT state. | |
| PCH watchdog disabled | |
| Jumping to boot code at 00008200 | |
| CPU0: stack: 00186000 - 00187000, lowest used address 00186898, stack used: 1896 bytes | |
| entry = 0x00008200 | |
| lb_start = 0x00100000 | |
| lb_size = 0x0008b038 | |
| buffer = 0xacd84538 | |
| error: terminal `console' isn't found. | |
| GNU GRUB version 2.02~beta2 | |
| +----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. | |
| Press enter to boot the selected OS, `e' to edit the commands | |
| before booting or `c' for a command-line. *Debian GNU/Linux Advanced options for Debian GNU/Linux Debian GNU/Linux, with Xen hypervisor Advanced options for Debian GNU/Linux (with Xen hypervisor) Memory test (memtest86+) Memory test (memtest86+, serial console 115200) Memory test (memtest86+, experimental multiboot) Memory test (memtest86+, serial console 115200, experimental multiboot) GRUB Invaders Install Debian Sid SeaBIOS OFW v The highlighted entry will be executed automatically in 5s. error: file `/boot/grub/i386-coreboot/all_video.mod' not found. | |
| Loading Linux 3.12-1-amd64 ... | |
| Loading initial ramdisk ... | |
| Press any key to continue... | |