| CPU: ID 0x30673, Processor Type 0x0, Family 0x6, Model 0x37, Stepping 0x3 |
| Northbridge: 8086:0f00 (Bay Trail) |
| Southbridge: 8086:0f1c (Bay Trail) |
| IGD: 8086:0f31 (unknown) |
| |
| ===================== SHARED MSRs (All Cores) ===================== |
| MSR 0x00000000 = 0x00000000:0x00000000 (IA32_P5_MC_ADDR) |
| MSR 0x00000001 = 0x00000000:0x00000000 (IA32_P5_MC_TYPE) |
| MSR 0x00000017 = 0x0000000C:0x90040A37 (IA32_PLATFORM_ID) |
| MSR 0x0000002A = 0x00000000:0x40080000 (MSR_EBC_HARD_POWERON) |
| MSR 0x000000CD = 0x00000000:0x00000002 (MSR_FSB_FREQ) |
| MSR 0x000000E2 = 0x00000000:0x000E0008 (MSR_PKG_CST_CONFIG_CONTROL) |
| MSR 0x000000E4 = 0x00000000:0x00000000 (MSR_PMG_IO_CAPTURE_BASE) |
| MSR 0x0000011E = 0x00000000:0x7E28010F (BBL_CR_CTL3) |
| MSR 0x00000198 = 0x00006E00:0x00000A37 (IA32_PERF_STATUS) |
| MSR 0x000001A2 = 0x00000000:0x006E0000 (MSR_TEMPERATURE_TARGET) |
| MSR 0x000001A6 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_0) |
| MSR 0x000001A7 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_1) |
| MSR 0x000001AD = 0x00000000:0x00000000 (MSR_TURBO_RATIO_LIMIT) |
| MSR 0x000003FA = 0x0000016F:0x6961C9A0 (MSR_PKG_C6_RESIDENCY) |
| MSR 0x00000400 = 0x00000000:0x0000003F (IA32_MC0_CTL) |
| MSR 0x00000401 = 0x00000000:0x00000000 (IA32_MC0_STATUS) |
| MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR) |
| MSR 0x00000404 = 0x00000000:0x00000001 (IA32_MC1_CTL) |
| MSR 0x00000405 = 0x00000000:0x00000000 (IA32_MC1_STATUS) |
| MSR 0x00000408 = 0x00000000:0x00000003 (IA32_MC2_CTL) |
| MSR 0x00000409 = 0x00000000:0x00000000 (IA32_MC2_STATUS) |
| MSR 0x0000040A = 0x00000000:0x00000000 (IA32_MC2_ADDR) |
| MSR 0x00000414 = 0x00000000:0x00000007 (MSR_MC5_CTL) |
| MSR 0x00000415 = 0x00000000:0x00000000 (MSR_MC5_STATUS) |
| MSR 0x00000416 = 0x00000000:0x00000000 (MSR_MC5_ADDR) |
| |
| ====================== UNIQUE MSRs (core 0) ====================== |
| MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE) |
| MSR 0x00000010 = 0x0000043A:0x56EE9FC8 (IA32_TIME_STAMP_COUNTER) |
| MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE) |
| MSR 0x00000034 = 0x00000000:0x00000001 (MSR_SMI_COUNT) |
| MSR 0x0000003A = 0x00000000:0x00000000 (IA32_FEATURE_CONTROL) |
| MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP) |
| MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP) |
| MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP) |
| MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP) |
| MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP) |
| MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP) |
| MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP) |
| MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP) |
| MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP) |
| MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP) |
| MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP) |
| MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP) |
| MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP) |
| MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP) |
| MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP) |
| MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP) |
| MSR 0x0000008B = 0x00000322:0x00000000 (IA32_BIOS_SIGN_ID) |
| MSR 0x000000C1 = 0x00000000:0x0000FFFF (IA32_PMC0) |
| MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1) |
| MSR 0x000000E7 = 0x00000161:0xB54162E4 (IA32_MPERF) |
| MSR 0x000000E8 = 0x0000015C:0xE176C62A (IA32_APERF) |
| MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP) |
| MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS) |
| MSR 0x00000175 = 0x00000000:0x00000000 (IA32_SYSENTER_ESP) |
| MSR 0x00000176 = 0xFFFFFFFF:0x81770170 (IA32_SYSENTER_EIP) |
| MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0) |
| MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1) |
| MSR 0x00000199 = 0x00000000:0x00000A37 (IA32_PERF_CONTROL) |
| MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION) |
| MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| MSR 0x0000019C = 0x00000000:0x88430000 (IA32_THERM_STATUS) |
| MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES) |
| MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS) |
| MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS) |
| MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL) |
| MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP) |
| MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP) |
| MSR 0x000001F2 = 0x00000000:0x7B000006 (IA32_SMRR_PHYSBASE) |
| MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK) |
| MSR 0x00000200 = 0x00000000:0xFF800005 (IA32_MTRR_PHYSBASE0) |
| MSR 0x00000201 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK0) |
| MSR 0x00000202 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE1) |
| MSR 0x00000203 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK1) |
| MSR 0x00000204 = 0x00000000:0x7B000000 (IA32_MTRR_PHYSBASE2) |
| MSR 0x00000205 = 0x0000000F:0xFF000800 (IA32_MTRR_PHYSMASK2) |
| MSR 0x00000206 = 0x00000000:0x7C000000 (IA32_MTRR_PHYSBASE3) |
| MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3) |
| MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| MSR 0x00000268 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C0000) |
| MSR 0x00000269 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C8000) |
| MSR 0x0000026A = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D0000) |
| MSR 0x0000026B = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D8000) |
| MSR 0x0000026C = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E0000) |
| MSR 0x0000026D = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E8000) |
| MSR 0x0000026E = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F0000) |
| MSR 0x0000026F = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F8000) |
| MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT) |
| MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0) |
| MSR 0x0000030A = 0x000000FD:0x8EE5C5A9 (IA32_FIXED_CTR1) |
| MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2) |
| MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES) |
| MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL) |
| MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS) |
| MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL) |
| MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL) |
| MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE) |
| MSR 0x000003FD = 0x000002A2:0x51835540 (MSR_CORE_C6_RESIDENCY) |
| MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL) |
| MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS) |
| MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR) |
| MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL) |
| MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS) |
| MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR) |
| MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC) |
| MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS) |
| MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS) |
| MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS) |
| MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS) |
| MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC) |
| MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0) |
| MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1) |
| MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0) |
| MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1) |
| MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM) |
| MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2) |
| MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM) |
| MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS) |
| MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS) |
| MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS) |
| MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS) |
| MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC) |
| MSR 0x000004C1 = 0x00000000:0x0000FFFF (IA32_A_PMC0) |
| MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1) |
| MSR 0x00000600 = 0xFFFF8800:0x77759D00 (IA32_DS_AREA) |
| MSR 0x00000660 = 0x00000022:0x2504EC0E (MSR_CORE_C1_RESIDENCY) |
| MSR 0x000006E0 = 0x0000043A:0x6AEA6C22 (IA32_TSC_DEADLINE) |
| |
| ====================== UNIQUE MSRs (core 1) ====================== |
| MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE) |
| MSR 0x00000010 = 0x0000043A:0x56FE7786 (IA32_TIME_STAMP_COUNTER) |
| MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE) |
| MSR 0x00000034 = 0x00000000:0x00000001 (MSR_SMI_COUNT) |
| MSR 0x0000003A = 0x00000000:0x00000000 (IA32_FEATURE_CONTROL) |
| MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP) |
| MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP) |
| MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP) |
| MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP) |
| MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP) |
| MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP) |
| MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP) |
| MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP) |
| MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP) |
| MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP) |
| MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP) |
| MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP) |
| MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP) |
| MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP) |
| MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP) |
| MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP) |
| MSR 0x0000008B = 0x00000322:0x00000000 (IA32_BIOS_SIGN_ID) |
| MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0) |
| MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1) |
| MSR 0x000000E7 = 0x00000140:0xC034957A (IA32_MPERF) |
| MSR 0x000000E8 = 0x0000013E:0x15022F66 (IA32_APERF) |
| MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP) |
| MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS) |
| MSR 0x00000175 = 0x00000000:0x00000000 (IA32_SYSENTER_ESP) |
| MSR 0x00000176 = 0xFFFFFFFF:0x81770170 (IA32_SYSENTER_EIP) |
| MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0) |
| MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1) |
| MSR 0x00000199 = 0x00000000:0x00000A37 (IA32_PERF_CONTROL) |
| MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION) |
| MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| MSR 0x0000019C = 0x00000000:0x88400000 (IA32_THERM_STATUS) |
| MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES) |
| MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS) |
| MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS) |
| MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL) |
| MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP) |
| MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP) |
| MSR 0x000001F2 = 0x00000000:0x7B000006 (IA32_SMRR_PHYSBASE) |
| MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK) |
| MSR 0x00000200 = 0x00000000:0xFF800005 (IA32_MTRR_PHYSBASE0) |
| MSR 0x00000201 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK0) |
| MSR 0x00000202 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE1) |
| MSR 0x00000203 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK1) |
| MSR 0x00000204 = 0x00000000:0x7B000000 (IA32_MTRR_PHYSBASE2) |
| MSR 0x00000205 = 0x0000000F:0xFF000800 (IA32_MTRR_PHYSMASK2) |
| MSR 0x00000206 = 0x00000000:0x7C000000 (IA32_MTRR_PHYSBASE3) |
| MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3) |
| MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| MSR 0x00000268 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C0000) |
| MSR 0x00000269 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C8000) |
| MSR 0x0000026A = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D0000) |
| MSR 0x0000026B = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D8000) |
| MSR 0x0000026C = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E0000) |
| MSR 0x0000026D = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E8000) |
| MSR 0x0000026E = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F0000) |
| MSR 0x0000026F = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F8000) |
| MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT) |
| MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0) |
| MSR 0x0000030A = 0x000000FF:0x428BF952 (IA32_FIXED_CTR1) |
| MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2) |
| MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES) |
| MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL) |
| MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS) |
| MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL) |
| MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL) |
| MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE) |
| MSR 0x000003FD = 0x000002BE:0x22A41FE0 (MSR_CORE_C6_RESIDENCY) |
| MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL) |
| MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS) |
| MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR) |
| MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL) |
| MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS) |
| MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR) |
| MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC) |
| MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS) |
| MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS) |
| MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS) |
| MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS) |
| MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC) |
| MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0) |
| MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1) |
| MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0) |
| MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1) |
| MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM) |
| MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2) |
| MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM) |
| MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS) |
| MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS) |
| MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS) |
| MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS) |
| MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC) |
| MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0) |
| MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1) |
| MSR 0x00000600 = 0xFFFF8800:0x77759D80 (IA32_DS_AREA) |
| MSR 0x00000660 = 0x00000024:0xF0B4342A (MSR_CORE_C1_RESIDENCY) |
| MSR 0x000006E0 = 0x0000043A:0x5739E64A (IA32_TSC_DEADLINE) |
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