| coreboot-4.0-6942-g4177db5 Wed Sep 24 13:25:54 CST 2014 booting...
|
| BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
|
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
|
| Enumerating buses...
|
| Show all devs...Before device enumeration.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 1
|
| PCI: 00:01.1: enabled 1
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:02.1: enabled 1
|
| PCI: 00:02.2: enabled 1
|
| PCI: 00:02.3: enabled 1
|
| PCI: 00:02.4: enabled 1
|
| PCI: 00:02.5: enabled 1
|
| PCI: 00:10.0: enabled 1
|
| PCI: 00:11.0: enabled 1
|
| PCI: 00:12.0: enabled 1
|
| PCI: 00:12.2: enabled 1
|
| PCI: 00:13.0: enabled 1
|
| PCI: 00:13.2: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| I2C: 00:50: enabled 1
|
| I2C: 00:51: enabled 1
|
| PCI: 00:14.2: enabled 1
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| PCI: 00:14.3: enabled 1
|
| PCI: 00:14.7: enabled 1
|
| PCI: 00:18.0: enabled 1
|
| PCI: 00:18.1: enabled 1
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| PCI: 00:18.2: enabled 1
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| PCI: 00:18.3: enabled 1
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| PCI: 00:18.4: enabled 1
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| PCI: 00:18.5: enabled 1
|
| Compare with tree...
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| Root Device: enabled 1
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| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
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| DOMAIN: 0000: enabled 1
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| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 1
|
| PCI: 00:01.1: enabled 1
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| PCI: 00:02.0: enabled 1
|
| PCI: 00:02.1: enabled 1
|
| PCI: 00:02.2: enabled 1
|
| PCI: 00:02.3: enabled 1
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| PCI: 00:02.4: enabled 1
|
| PCI: 00:02.5: enabled 1
|
| PCI: 00:10.0: enabled 1
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| PCI: 00:11.0: enabled 1
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| PCI: 00:12.0: enabled 1
|
| PCI: 00:12.2: enabled 1
|
| PCI: 00:13.0: enabled 1
|
| PCI: 00:13.2: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| I2C: 00:50: enabled 1
|
| I2C: 00:51: enabled 1
|
| PCI: 00:14.2: enabled 1
|
| PCI: 00:14.3: enabled 1
|
| PCI: 00:14.7: enabled 1
|
| PCI: 00:18.0: enabled 1
|
| PCI: 00:18.1: enabled 1
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| PCI: 00:18.2: enabled 1
|
| PCI: 00:18.3: enabled 1
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| PCI: 00:18.4: enabled 1
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| PCI: 00:18.5: enabled 1
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| Mainboard DB-FT3b Enable.
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| scan_static_bus for Root Device
|
| setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
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| setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000001
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| setup_uma_memory: system memory size 4GB, topmem2 size 4592MB, topmem size 3584MB
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| setup_uma_memory: uma size 0x20000000, memory start 0xc0000000
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| CPU_CLUSTER: 0 enabled
|
| DOMAIN: 0000 enabled
|
| CPU_CLUSTER: 0 scanning...
|
| MullinsPI Debug: Grabbing the AMD Topology Information.
|
| MullinsPI Debug: AMD Topology Number of Modules (@0x00252ed4) is 1
|
| MullinsPI Debug: AMD Topology Number of IOAPICs (@0xffe5f1c8) is 3
|
| PCI: 00:18.5 family16h, core_max=0x8, core_nums=0x7, siblings=0x3
|
| node 0x0 core 0x0 apicid=0x0
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| CPU: APIC: 00 enabled
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| node 0x0 core 0x1 apicid=0x1
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| CPU: APIC: 01 enabled
|
| node 0x0 core 0x2 apicid=0x2
|
| CPU: APIC: 02 enabled
|
| node 0x0 core 0x3 apicid=0x3
|
| CPU: APIC: 03 enabled
|
| DOMAIN: 0000 scanning...
|
| PCI: pci_scan_bus for bus 00
|
| PCI: 00:00.0 [1022/1566] ops
|
| PCI: 00:00.0 [1022/1566] enabled
|
| PCI: 00:01.0 [1002/9855] enabled
|
| PCI: 00:01.1 [1002/9840] enabled
|
| PCI: 00:02.0 [1022/156b] enabled
|
| PCI: Static device PCI: 00:02.1 not found, disabling it.
|
| PCI: Static device PCI: 00:02.2 not found, disabling it.
|
| Capability: type 0x01 @ 0x50
|
| Capability: type 0x10 @ 0x58
|
| Capability: type 0x05 @ 0xa0
|
| Capability: type 0x0d @ 0xb0
|
| Capability: type 0x08 @ 0xb8
|
| Capability: type 0x01 @ 0x50
|
| Capability: type 0x10 @ 0x58
|
| PCI: 00:02.3 subordinate bus PCI Express
|
| PCI: 00:02.3 [1022/1439] enabled
|
| PCI: Static device PCI: 00:02.4 not found, disabling it.
|
| PCI: Static device PCI: 00:02.5 not found, disabling it.
|
| PCI: 00:08.0 [1022/1537] enabled
|
| hudson_enable()
|
| PCI: 00:10.0 [1022/7814] enabled
|
| hudson_enable()
|
| PCI: 00:11.0 [1022/7800] ops
|
| PCI: 00:11.0 [1022/7800] enabled
|
| hudson_enable()
|
| PCI: 00:12.0 [1022/7808] ops
|
| PCI: 00:12.0 [1022/7808] enabled
|
| hudson_enable()
|
| PCI: 00:13.0 [1022/7808] ops
|
| PCI: 00:13.0 [1022/7808] enabled
|
| hudson_enable()
|
| PCI: 00:14.0 [1022/780b] bus ops
|
| PCI: 00:14.0 [1022/780b] enabled
|
| hudson_enable()
|
| PCI: 00:14.2 [1022/780d] ops
|
| PCI: 00:14.2 [1022/780d] enabled
|
| hudson_enable()
|
| PCI: 00:14.3 [1022/780e] bus ops
|
| PCI: 00:14.3 [1022/780e] enabled
|
| hudson_enable()
|
| PCI: 00:14.7 [1022/7813] ops
|
| PCI: 00:14.7 [1022/7813] enabled
|
| PCI: 00:18.0 [1022/1580] enabled
|
| PCI: 00:18.1 [1022/1581] enabled
|
| PCI: 00:18.2 [1022/1582] enabled
|
| PCI: 00:18.3 [1022/1583] enabled
|
| PCI: 00:18.4 [1022/1584] enabled
|
| PCI: 00:18.5 [1022/1585] enabled
|
| PCI: Left over static devices:
|
| PCI: 00:12.2
|
| PCI: 00:13.2
|
| PCI: Check your devicetree.cb.
|
| do_pci_scan_bridge for PCI: 00:02.3
|
| PCI: pci_scan_bus for bus 01
|
| PCI: 01:00.0 [10ec/8168] enabled
|
| PCI: 01:00.1 [10ec/816a] enabled
|
| PCI: 01:00.2 [10ec/816b] enabled
|
| PCI: 01:00.3 [10ec/816c] enabled
|
| PCI: pci_scan_bus returning with max=001
|
| Capability: type 0x01 @ 0x40
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x10 @ 0x70
|
| Capability: type 0x01 @ 0x50
|
| Capability: type 0x10 @ 0x58
|
| Capability: type 0x01 @ 0x40
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x10 @ 0x70
|
| Capability: type 0x01 @ 0x50
|
| Capability: type 0x10 @ 0x58
|
| Capability: type 0x01 @ 0x40
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x10 @ 0x70
|
| Capability: type 0x01 @ 0x50
|
| Capability: type 0x10 @ 0x58
|
| Capability: type 0x01 @ 0x40
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x10 @ 0x70
|
| Capability: type 0x01 @ 0x50
|
| Capability: type 0x10 @ 0x58
|
| do_pci_scan_bridge returns max 1
|
| scan_static_bus for PCI: 00:14.0
|
| smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
|
| smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
|
| scan_static_bus for PCI: 00:14.0 done
|
| scan_static_bus for PCI: 00:14.3
|
| scan_static_bus for PCI: 00:14.3 done
|
| PCI: pci_scan_bus returning with max=001
|
| scan_static_bus for Root Device done
|
| done
|
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 7898 exit 0
|
| found VGA at PCI: 00:01.0
|
| Setting up VGA for PCI: 00:01.0
|
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
| Allocating resources...
|
| Reading resources...
|
| Root Device read_resources bus 0 link: 0
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
| APIC: 00 missing read_resources
|
| APIC: 01 missing read_resources
|
| APIC: 02 missing read_resources
|
| APIC: 03 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
| fx_devs=0x1
|
| DOMAIN: 0000 read_resources bus 0 link: 0
|
| PCI: 00:02.3 read_resources bus 1 link: 0
|
| PCI: 00:02.3 read_resources bus 1 link: 0 done
|
| PCI: 00:14.0 read_resources bus 1 link: 0
|
| I2C: 01:50 missing read_resources
|
| I2C: 01:51 missing read_resources
|
| PCI: 00:14.0 read_resources bus 1 link: 0 done
|
| PCI: 00:18.0 read_resources bus 0 link: 0
|
| PCI: 00:18.0 read_resources bus 0 link: 0 done
|
| PCI: 00:18.0 read_resources bus 0 link: 1
|
| PCI: 00:18.0 read_resources bus 0 link: 1 done
|
| PCI: 00:18.0 read_resources bus 0 link: 2
|
| PCI: 00:18.0 read_resources bus 0 link: 2 done
|
| PCI: 00:18.0 read_resources bus 0 link: 3
|
| PCI: 00:18.0 read_resources bus 0 link: 3 done
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| DOMAIN: 0000 read_resources bus 0 link: 0 done
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| Root Device read_resources bus 0 link: 0 done
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| Done reading resources.
|
| Show resources in subtree (Root Device)...After reading.
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| Root Device child on link 0 CPU_CLUSTER: 0
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| CPU_CLUSTER: 0 child on link 0 APIC: 00
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| CPU_CLUSTER: 0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
|
| APIC: 00
|
| APIC: 01
|
| APIC: 02
|
| APIC: 03
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:01.0
|
| PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 10
|
| PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18
|
| PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20
|
| PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24
|
| PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
|
| PCI: 00:01.1
|
| PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:02.0
|
| PCI: 00:02.1
|
| PCI: 00:02.2
|
| PCI: 00:02.3 child on link 0 PCI: 01:00.0
|
| PCI: 00:02.3 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
|
| PCI: 00:02.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:02.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
|
| PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
|
| PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
|
| PCI: 01:00.1
|
| PCI: 01:00.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
|
| PCI: 01:00.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
|
| PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
|
| PCI: 01:00.2
|
| PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
|
| PCI: 01:00.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
|
| PCI: 01:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
|
| PCI: 01:00.3
|
| PCI: 01:00.3 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
|
| PCI: 01:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 18
|
| PCI: 01:00.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
|
| PCI: 00:02.4
|
| PCI: 00:02.5
|
| PCI: 00:08.0
|
| PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10
|
| PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
|
| PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
|
| PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20
|
| PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24
|
| PCI: 00:10.0
|
| PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:11.0
|
| PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
| PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
| PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
| PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
| PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
|
| PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
|
| PCI: 00:12.0
|
| PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 00:13.0
|
| PCI: 00:13.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 00:14.0 child on link 0 I2C: 01:50
|
| I2C: 01:50
|
| I2C: 01:51
|
| PCI: 00:14.2
|
| PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:14.3
|
| PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
|
| PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:14.7
|
| PCI: 00:14.7 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:18.0
|
| PCI: 00:18.1
|
| PCI: 00:18.2
|
| PCI: 00:18.3
|
| PCI: 00:18.4
|
| PCI: 00:18.5
|
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
| PCI: 00:02.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
|
| PCI: 01:00.0 10 * [0x0 - 0xff] io
|
| PCI: 01:00.1 10 * [0x400 - 0x4ff] io
|
| PCI: 01:00.2 10 * [0x800 - 0x8ff] io
|
| PCI: 01:00.3 10 * [0xc00 - 0xcff] io
|
| PCI: 00:02.3 compute_resources_io: base: d00 size: 1000 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:02.3 1c * [0x0 - 0xfff] io
|
| PCI: 00:01.0 20 * [0x1000 - 0x10ff] io
|
| PCI: 00:11.0 20 * [0x1400 - 0x140f] io
|
| PCI: 00:11.0 10 * [0x1410 - 0x1417] io
|
| PCI: 00:11.0 18 * [0x1418 - 0x141f] io
|
| PCI: 00:11.0 14 * [0x1420 - 0x1423] io
|
| PCI: 00:11.0 1c * [0x1424 - 0x1427] io
|
| DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
|
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
| PCI: 00:02.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 01:00.0 20 * [0x0 - 0x3fff] prefmem
|
| PCI: 00:02.3 compute_resources_prefmem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:02.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 01:00.1 20 * [0x0 - 0x3fff] mem
|
| PCI: 01:00.2 20 * [0x4000 - 0x7fff] mem
|
| PCI: 01:00.3 20 * [0x8000 - 0xbfff] mem
|
| PCI: 01:00.0 18 * [0xc000 - 0xcfff] mem
|
| PCI: 01:00.1 18 * [0xd000 - 0xdfff] mem
|
| PCI: 01:00.2 18 * [0xe000 - 0xefff] mem
|
| PCI: 01:00.3 18 * [0xf000 - 0xf0ff] mem
|
| PCI: 00:02.3 compute_resources_mem: base: f100 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
|
| PCI: 00:01.0 18 * [0x10000000 - 0x107fffff] prefmem
|
| PCI: 00:02.3 24 * [0x10800000 - 0x108fffff] prefmem
|
| PCI: 00:02.3 20 * [0x10900000 - 0x109fffff] mem
|
| PCI: 00:08.0 18 * [0x10a00000 - 0x10afffff] mem
|
| PCI: 00:08.0 20 * [0x10b00000 - 0x10bfffff] mem
|
| PCI: 00:01.0 24 * [0x10c00000 - 0x10c3ffff] mem
|
| PCI: 00:01.0 30 * [0x10c40000 - 0x10c5ffff] mem
|
| PCI: 00:08.0 10 * [0x10c60000 - 0x10c7ffff] prefmem
|
| PCI: 00:01.1 10 * [0x10c80000 - 0x10c83fff] mem
|
| PCI: 00:14.2 10 * [0x10c84000 - 0x10c87fff] mem
|
| PCI: 00:08.0 24 * [0x10c88000 - 0x10c89fff] mem
|
| PCI: 00:10.0 10 * [0x10c8a000 - 0x10c8bfff] mem
|
| PCI: 00:08.0 1c * [0x10c8c000 - 0x10c8cfff] mem
|
| PCI: 00:11.0 24 * [0x10c8d000 - 0x10c8d3ff] mem
|
| PCI: 00:12.0 10 * [0x10c8d400 - 0x10c8d4ff] mem
|
| PCI: 00:13.0 10 * [0x10c8d500 - 0x10c8d5ff] mem
|
| PCI: 00:14.7 10 * [0x10c8d600 - 0x10c8d6ff] mem
|
| DOMAIN: 0000 compute_resources_mem: base: 10c8d700 size: 10c8d700 align: 28 gran: 0 limit: ffffffff done
|
| avoid_fixed_resources: DOMAIN: 0000
|
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
| constrain_resources: DOMAIN: 0000
|
| constrain_resources: PCI: 00:00.0
|
| constrain_resources: PCI: 00:01.0
|
| constrain_resources: PCI: 00:01.1
|
| constrain_resources: PCI: 00:02.0
|
| constrain_resources: PCI: 00:02.3
|
| constrain_resources: PCI: 01:00.0
|
| constrain_resources: PCI: 01:00.1
|
| constrain_resources: PCI: 01:00.2
|
| constrain_resources: PCI: 01:00.3
|
| constrain_resources: PCI: 00:08.0
|
| constrain_resources: PCI: 00:10.0
|
| constrain_resources: PCI: 00:11.0
|
| constrain_resources: PCI: 00:12.0
|
| constrain_resources: PCI: 00:13.0
|
| constrain_resources: PCI: 00:14.0
|
| constrain_resources: I2C: 01:50
|
| constrain_resources: I2C: 01:51
|
| constrain_resources: PCI: 00:14.2
|
| constrain_resources: PCI: 00:14.3
|
| constrain_resources: PCI: 00:14.7
|
| constrain_resources: PCI: 00:18.0
|
| constrain_resources: PCI: 00:18.1
|
| constrain_resources: PCI: 00:18.2
|
| constrain_resources: PCI: 00:18.3
|
| constrain_resources: PCI: 00:18.4
|
| constrain_resources: PCI: 00:18.5
|
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
|
| lim->base 00001000 lim->limit 0000ffff
|
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
|
| lim->base 00000000 lim->limit febfffff
|
| Setting resources...
|
| DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0 limit:ffff
|
| Assigned: PCI: 00:02.3 1c * [0x1000 - 0x1fff] io
|
| Assigned: PCI: 00:01.0 20 * [0x2000 - 0x20ff] io
|
| Assigned: PCI: 00:11.0 20 * [0x2400 - 0x240f] io
|
| Assigned: PCI: 00:11.0 10 * [0x2410 - 0x2417] io
|
| Assigned: PCI: 00:11.0 18 * [0x2418 - 0x241f] io
|
| Assigned: PCI: 00:11.0 14 * [0x2420 - 0x2423] io
|
| Assigned: PCI: 00:11.0 1c * [0x2424 - 0x2427] io
|
| DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align: 12 gran: 0 done
|
| PCI: 00:02.3 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
|
| Assigned: PCI: 01:00.0 10 * [0x1000 - 0x10ff] io
|
| Assigned: PCI: 01:00.1 10 * [0x1400 - 0x14ff] io
|
| Assigned: PCI: 01:00.2 10 * [0x1800 - 0x18ff] io
|
| Assigned: PCI: 01:00.3 10 * [0x1c00 - 0x1cff] io
|
| PCI: 00:02.3 allocate_resources_io: next_base: 1d00 size: 1000 align: 12 gran: 12 done
|
| DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10c8d700 align:28 gran:0 limit:febfffff
|
| Assigned: PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
|
| Assigned: PCI: 00:01.0 18 * [0xf0000000 - 0xf07fffff] prefmem
|
| Assigned: PCI: 00:02.3 24 * [0xf0800000 - 0xf08fffff] prefmem
|
| Assigned: PCI: 00:02.3 20 * [0xf0900000 - 0xf09fffff] mem
|
| Assigned: PCI: 00:08.0 18 * [0xf0a00000 - 0xf0afffff] mem
|
| Assigned: PCI: 00:08.0 20 * [0xf0b00000 - 0xf0bfffff] mem
|
| Assigned: PCI: 00:01.0 24 * [0xf0c00000 - 0xf0c3ffff] mem
|
| Assigned: PCI: 00:01.0 30 * [0xf0c40000 - 0xf0c5ffff] mem
|
| Assigned: PCI: 00:08.0 10 * [0xf0c60000 - 0xf0c7ffff] prefmem
|
| Assigned: PCI: 00:01.1 10 * [0xf0c80000 - 0xf0c83fff] mem
|
| Assigned: PCI: 00:14.2 10 * [0xf0c84000 - 0xf0c87fff] mem
|
| Assigned: PCI: 00:08.0 24 * [0xf0c88000 - 0xf0c89fff] mem
|
| Assigned: PCI: 00:10.0 10 * [0xf0c8a000 - 0xf0c8bfff] mem
|
| Assigned: PCI: 00:08.0 1c * [0xf0c8c000 - 0xf0c8cfff] mem
|
| Assigned: PCI: 00:11.0 24 * [0xf0c8d000 - 0xf0c8d3ff] mem
|
| Assigned: PCI: 00:12.0 10 * [0xf0c8d400 - 0xf0c8d4ff] mem
|
| Assigned: PCI: 00:13.0 10 * [0xf0c8d500 - 0xf0c8d5ff] mem
|
| Assigned: PCI: 00:14.7 10 * [0xf0c8d600 - 0xf0c8d6ff] mem
|
| DOMAIN: 0000 allocate_resources_mem: next_base: f0c8d700 size: 10c8d700 align: 28 gran: 0 done
|
| PCI: 00:02.3 allocate_resources_prefmem: base:f0800000 size:100000 align:20 gran:20 limit:febfffff
|
| Assigned: PCI: 01:00.0 20 * [0xf0800000 - 0xf0803fff] prefmem
|
| PCI: 00:02.3 allocate_resources_prefmem: next_base: f0804000 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:02.3 allocate_resources_mem: base:f0900000 size:100000 align:20 gran:20 limit:febfffff
|
| Assigned: PCI: 01:00.1 20 * [0xf0900000 - 0xf0903fff] mem
|
| Assigned: PCI: 01:00.2 20 * [0xf0904000 - 0xf0907fff] mem
|
| Assigned: PCI: 01:00.3 20 * [0xf0908000 - 0xf090bfff] mem
|
| Assigned: PCI: 01:00.0 18 * [0xf090c000 - 0xf090cfff] mem
|
| Assigned: PCI: 01:00.1 18 * [0xf090d000 - 0xf090dfff] mem
|
| Assigned: PCI: 01:00.2 18 * [0xf090e000 - 0xf090efff] mem
|
| Assigned: PCI: 01:00.3 18 * [0xf090f000 - 0xf090f0ff] mem
|
| PCI: 00:02.3 allocate_resources_mem: next_base: f090f100 size: 100000 align: 20 gran: 20 done
|
| Root Device assign_resources, bus 0 link: 0
|
| CPU_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem <mmconfig>
|
| CPU_CLUSTER: 0 assign_resources, bus 0 link: 0
|
| CPU_CLUSTER: 0 assign_resources, bus 0 link: 0
|
| node 0: mmio_basek=00380000, basek=00400000, limitk=00460000
|
| CBMEM region bffc0000-bfffffff (cbmem_late_set_table)
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
|
| PCI: 00:01.0 18 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem64
|
| PCI: 00:01.0 20 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
|
| PCI: 00:01.0 24 <- [0x00f0c00000 - 0x00f0c3ffff] size 0x00040000 gran 0x12 mem
|
| PCI: 00:01.0 30 <- [0x00f0c40000 - 0x00f0c5ffff] size 0x00020000 gran 0x11 romem
|
| PCI: 00:01.1 10 <- [0x00f0c80000 - 0x00f0c83fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:02.3 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
|
| PCI: 00:02.3 24 <- [0x00f0800000 - 0x00f08fffff] size 0x00100000 gran 0x14 bus 01 prefmem
|
| PCI: 00:02.3 20 <- [0x00f0900000 - 0x00f09fffff] size 0x00100000 gran 0x14 bus 01 mem
|
| PCI: 00:02.3 assign_resources, bus 1 link: 0
|
| PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
|
| PCI: 01:00.0 18 <- [0x00f090c000 - 0x00f090cfff] size 0x00001000 gran 0x0c mem64
|
| PCI: 01:00.0 20 <- [0x00f0800000 - 0x00f0803fff] size 0x00004000 gran 0x0e prefmem64
|
| PCI: 01:00.1 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
|
| PCI: 01:00.1 18 <- [0x00f090d000 - 0x00f090dfff] size 0x00001000 gran 0x0c mem64
|
| PCI: 01:00.1 20 <- [0x00f0900000 - 0x00f0903fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 01:00.2 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
|
| PCI: 01:00.2 18 <- [0x00f090e000 - 0x00f090efff] size 0x00001000 gran 0x0c mem64
|
| PCI: 01:00.2 20 <- [0x00f0904000 - 0x00f0907fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 01:00.3 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io
|
| PCI: 01:00.3 18 <- [0x00f090f000 - 0x00f090f0ff] size 0x00000100 gran 0x08 mem64
|
| PCI: 01:00.3 20 <- [0x00f0908000 - 0x00f090bfff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:02.3 assign_resources, bus 1 link: 0
|
| PCI: 00:08.0 10 <- [0x00f0c60000 - 0x00f0c7ffff] size 0x00020000 gran 0x11 prefmem64
|
| PCI: 00:08.0 18 <- [0x00f0a00000 - 0x00f0afffff] size 0x00100000 gran 0x14 mem
|
| PCI: 00:08.0 1c <- [0x00f0c8c000 - 0x00f0c8cfff] size 0x00001000 gran 0x0c mem
|
| PCI: 00:08.0 20 <- [0x00f0b00000 - 0x00f0bfffff] size 0x00100000 gran 0x14 mem
|
| PCI: 00:08.0 24 <- [0x00f0c88000 - 0x00f0c89fff] size 0x00002000 gran 0x0d mem
|
| PCI: 00:10.0 10 <- [0x00f0c8a000 - 0x00f0c8bfff] size 0x00002000 gran 0x0d mem64
|
| PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
|
| PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
|
| PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
|
| PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
|
| PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
|
| PCI: 00:11.0 24 <- [0x00f0c8d000 - 0x00f0c8d3ff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:12.0 10 <- [0x00f0c8d400 - 0x00f0c8d4ff] size 0x00000100 gran 0x08 mem
|
| PCI: 00:13.0 10 <- [0x00f0c8d500 - 0x00f0c8d5ff] size 0x00000100 gran 0x08 mem
|
| PCI: 00:14.2 10 <- [0x00f0c84000 - 0x00f0c87fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:14.7 10 <- [0x00f0c8d600 - 0x00f0c8d6ff] size 0x00000100 gran 0x08 mem64
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| Root Device assign_resources, bus 0 link: 0
|
| Done setting resources.
|
| Show resources in subtree (Root Device)...After assigning values.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| CPU_CLUSTER: 0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
|
| APIC: 00
|
| APIC: 01
|
| APIC: 02
|
| APIC: 03
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base e0000000 size 10c8d700 align 28 gran 0 limit febfffff flags 40040200 index 10000100
|
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
|
| DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0 flags e0004200 index 20
|
| DOMAIN: 0000 resource base 100000000 size 1f000000 align 0 gran 0 limit 0 flags e0004200 index 30
|
| DOMAIN: 0000 resource base c0000000 size 20000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| PCI: 00:00.0
|
| PCI: 00:01.0
|
| PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001201 index 10
|
| PCI: 00:01.0 resource base f0000000 size 800000 align 23 gran 23 limit febfffff flags 60001201 index 18
|
| PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 20
|
| PCI: 00:01.0 resource base f0c00000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 24
|
| PCI: 00:01.0 resource base f0c40000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
|
| PCI: 00:01.1
|
| PCI: 00:01.1 resource base f0c80000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10
|
| PCI: 00:02.0
|
| PCI: 00:02.1
|
| PCI: 00:02.2
|
| PCI: 00:02.3 child on link 0 PCI: 01:00.0
|
| PCI: 00:02.3 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:02.3 resource base f0800000 size 100000 align 20 gran 20 limit febfffff flags 60081202 index 24
|
| PCI: 00:02.3 resource base f0900000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
|
| PCI: 01:00.0 resource base f090c000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18
|
| PCI: 01:00.0 resource base f0800000 size 4000 align 14 gran 14 limit febfffff flags 60001201 index 20
|
| PCI: 01:00.1
|
| PCI: 01:00.1 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
|
| PCI: 01:00.1 resource base f090d000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18
|
| PCI: 01:00.1 resource base f0900000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 20
|
| PCI: 01:00.2
|
| PCI: 01:00.2 resource base 1800 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
|
| PCI: 01:00.2 resource base f090e000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18
|
| PCI: 01:00.2 resource base f0904000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 20
|
| PCI: 01:00.3
|
| PCI: 01:00.3 resource base 1c00 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
|
| PCI: 01:00.3 resource base f090f000 size 100 align 8 gran 8 limit febfffff flags 60000201 index 18
|
| PCI: 01:00.3 resource base f0908000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 20
|
| PCI: 00:02.4
|
| PCI: 00:02.5
|
| PCI: 00:08.0
|
| PCI: 00:08.0 resource base f0c60000 size 20000 align 17 gran 17 limit febfffff flags 60001201 index 10
|
| PCI: 00:08.0 resource base f0a00000 size 100000 align 20 gran 20 limit febfffff flags 60000200 index 18
|
| PCI: 00:08.0 resource base f0c8c000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 1c
|
| PCI: 00:08.0 resource base f0b00000 size 100000 align 20 gran 20 limit febfffff flags 60000200 index 20
|
| PCI: 00:08.0 resource base f0c88000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 24
|
| PCI: 00:10.0
|
| PCI: 00:10.0 resource base f0c8a000 size 2000 align 13 gran 13 limit febfffff flags 60000201 index 10
|
| PCI: 00:11.0
|
| PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
|
| PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
|
| PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
|
| PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
|
| PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
|
| PCI: 00:11.0 resource base f0c8d000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24
|
| PCI: 00:12.0
|
| PCI: 00:12.0 resource base f0c8d400 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
|
| PCI: 00:13.0
|
| PCI: 00:13.0 resource base f0c8d500 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
|
| PCI: 00:14.0 child on link 0 I2C: 01:50
|
| I2C: 01:50
|
| I2C: 01:51
|
| PCI: 00:14.2
|
| PCI: 00:14.2 resource base f0c84000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10
|
| PCI: 00:14.3
|
| PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
|
| PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:14.7
|
| PCI: 00:14.7 resource base f0c8d600 size 100 align 8 gran 8 limit febfffff flags 60000201 index 10
|
| PCI: 00:18.0
|
| PCI: 00:18.1
|
| PCI: 00:18.2
|
| PCI: 00:18.3
|
| PCI: 00:18.4
|
| PCI: 00:18.5
|
| Done allocating resources.
|
| BS: BS_DEV_RESOURCES times (us): entry 0 run 29573 exit 0
|
| Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
|
| 'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
|
| Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist
|
| Enabling resources...
|
| agesawrapper_amdinitmid() entry
|
| agesawrapper_amdinitmid() returned AGESA_SUCCESS
|
| ader - leaving domain_enable_resources.
|
| PCI: 00:00.0 cmd <- 04
|
| PCI: 00:01.0 subsystem <- 1022/1410
|
| PCI: 00:01.0 cmd <- 07
|
| PCI: 00:01.1 subsystem <- 1022/1410
|
| PCI: 00:01.1 cmd <- 02
|
| PCI: 00:02.0 subsystem <- 1022/1410
|
| PCI: 00:02.0 cmd <- 00
|
| PCI: 00:02.3 bridge ctrl <- 0003
|
| PCI: 00:02.3 cmd <- 07
|
| PCI: 00:08.0 cmd <- 06
|
| PCI: 00:10.0 subsystem <- 1022/1410
|
| PCI: 00:10.0 cmd <- 02
|
| PCI: 00:11.0 cmd <- 07
|
| PCI: 00:12.0 subsystem <- 1022/1410
|
| PCI: 00:12.0 cmd <- 02
|
| PCI: 00:13.0 subsystem <- 1022/1410
|
| PCI: 00:13.0 cmd <- 02
|
| PCI: 00:14.0 subsystem <- 1022/1410
|
| PCI: 00:14.0 cmd <- 403
|
| PCI: 00:14.2 subsystem <- 1022/1410
|
| PCI: 00:14.2 cmd <- ffff
|
| PCI: 00:14.3 subsystem <- 1022/1410
|
| PCI: 00:14.3 cmd <- 0f
|
| PCI: 00:14.7 cmd <- 06
|
| PCI: 00:18.0 subsystem <- 1022/1410
|
| PCI: 00:18.0 cmd <- 00
|
| PCI: 00:18.1 subsystem <- 1022/1410
|
| PCI: 00:18.1 cmd <- 00
|
| PCI: 00:18.2 subsystem <- 1022/1410
|
| PCI: 00:18.2 cmd <- 00
|
| PCI: 00:18.3 subsystem <- 1022/1410
|
| PCI: 00:18.3 cmd <- 00
|
| PCI: 00:18.4 subsystem <- 1022/1410
|
| PCI: 00:18.4 cmd <- 00
|
| PCI: 00:18.5 subsystem <- 1022/1410
|
| PCI: 00:18.5 cmd <- 00
|
| PCI: 01:00.0 cmd <- 03
|
| PCI: 01:00.1 cmd <- 03
|
| PCI: 01:00.2 cmd <- 03
|
| PCI: 01:00.3 cmd <- 03
|
| done.
|
| BS: BS_DEV_ENABLE times (us): entry 277 run 2665276 exit 0
|
| Initializing devices...
|
| Root Device init
|
| Root Device init 65 usecs
|
| CPU_CLUSTER: 0 init
|
| start_eip=0x00001000, code_size=0x00000031
|
| Initializing CPU #0
|
| CPU: vendor AMD device 730f00
|
| CPU: family 16, model 30, stepping 00
|
| Model 16 Init.
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Enabling cache
|
| Setting up local apic... apic_id: 0x00 done.
|
| siblings = 03, CPU #0 initialized
|
| CPU1: stack_base 00251000, stack_end 00251ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 1.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Sending STARTUP #2 to 1.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| Initializing CPU #1
|
| CPU: vendor AMD device 730f00
|
| CPU: family 16, model 30, stepping 00
|
| Model 16 Init.
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Enabling cache
|
| Setting up local apic... apic_id: 0x01 done.
|
| siblings = 03, CPU #1 initialized
|
| CPU2: stack_base 00250000, stack_end 00250ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 2.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Sending STARTUP #2 to 2.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| Initializing CPU #2
|
| CPU: vendor AMD device 730f00
|
| CPU: family 16, model 30, stepping 00
|
| Model 16 Init.
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Enabling cache
|
| Setting up local apic... apic_id: 0x02 done.
|
| siblings = 03, CPU #2 initialized
|
| CPU3: stack_base 0024f000, stack_end 0024fff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 3.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Sending STARTUP #2 to 3.
|
| After apic_write.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| Initializing CPU #3
|
| Waiting for 1 CPUS to stop
|
| CPU: vendor AMD device 730f00
|
| CPU: family 16, model 30, stepping 00
|
| Model 16 Init.
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Enabling cache
|
| Setting up local apic... apic_id: 0x03 done.
|
| siblings = 03, CPU #3 initialized
|
| All AP CPUs stopped (130 loops)
|
| CPU1: stack: 00251000 - 00252000, lowest used address 00251dc8, stack used: 568 bytes
|
| CPU2: stack: 00250000 - 00251000, lowest used address 00250dc8, stack used: 568 bytes
|
| CPU3: stack: 0024f000 - 00250000, lowest used address 0024fdc8, stack used: 568 bytes
|
| CPU_CLUSTER: 0 init 41566 usecs
|
| PCI: 00:00.0 init
|
| PCI: 00:00.0 init 25 usecs
|
| PCI: 00:01.0 init
|
| Mapping PCI device 10029855 to 10029850
|
| In CBFS, ROM address for PCI: 00:01.0 = ff800778
|
| PCI expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c4
|
| PCI ROM image, vendor ID 1002, device ID 9850,
|
| PCI ROM image, Class Code 030000, Code Type 00
|
| Copying VGA ROM Image from ff800778 to 0xc0000, 0xec00 bytes
|
| Real mode stub @00000600: 867 bytes
|
| Calling Option ROM...
|
| ... Option ROM returned.
|
| VGA Option ROM was run
|
| PCI: 00:01.0 init 28301 usecs
|
| PCI: 00:01.1 init
|
| PCI: 00:01.1 init 24 usecs
|
| PCI: 00:02.0 init
|
| PCI: 00:02.0 init 24 usecs
|
| PCI: 00:08.0 init
|
| PCI: 00:08.0 init 24 usecs
|
| PCI: 00:10.0 init
|
| PCI: 00:10.0 init 24 usecs
|
| PCI: 00:11.0 init
|
| PCI: 00:11.0 init 24 usecs
|
| PCI: 00:12.0 init
|
| PCI: 00:12.0 init 24 usecs
|
| PCI: 00:13.0 init
|
| PCI: 00:13.0 init 24 usecs
|
| PCI: 00:14.0 init
|
| IOAPIC: Initializing IOAPIC at 0xfec00000
|
| IOAPIC: Bootstrap Processor Local APIC = 0x00
|
| IOAPIC: ID = 0x04
|
| IOAPIC: Dumping registers
|
| reg 0x0000: 0x04000000
|
| reg 0x0001: 0x00178021
|
| reg 0x0002: 0x04000000
|
| IOAPIC: 24 interrupts
|
| IOAPIC: Enabling interrupts on FSB
|
| IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
|
| IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
|
| IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
|
| IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
|
| IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
|
| IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
|
| IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
|
| IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
|
| PCI: 00:14.0 init 1961 usecs
|
| PCI: 00:14.2 init
|
| PCI: 00:14.2 init 24 usecs
|
| PCI: 00:14.3 init
|
| RTC Init
|
| PCI: 00:14.3 init 55 usecs
|
| PCI: 00:14.7 init
|
| PCI: 00:14.7 init 26 usecs
|
| PCI: 00:18.0 init
|
| PCI: 00:18.0 init 24 usecs
|
| PCI: 00:18.1 init
|
| PCI: 00:18.1 init 24 usecs
|
| PCI: 00:18.2 init
|
| PCI: 00:18.2 init 24 usecs
|
| PCI: 00:18.3 init
|
| PCI: 00:18.3 init 24 usecs
|
| PCI: 00:18.4 init
|
| PCI: 00:18.4 init 24 usecs
|
| PCI: 00:18.5 init
|
| PCI: 00:18.5 init 24 usecs
|
| PCI: 01:00.0 init
|
| PCI: 01:00.0 init 24 usecs
|
| PCI: 01:00.1 init
|
| PCI: 01:00.1 init 24 usecs
|
| PCI: 01:00.2 init
|
| PCI: 01:00.2 init 24 usecs
|
| PCI: 01:00.3 init
|
| PCI: 01:00.3 init 24 usecs
|
| Devices initialized
|
| Show all devs...After init.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 1
|
| PCI: 00:01.1: enabled 1
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:02.1: enabled 0
|
| PCI: 00:02.2: enabled 0
|
| PCI: 00:02.3: enabled 1
|
| PCI: 00:02.4: enabled 0
|
| PCI: 00:02.5: enabled 0
|
| PCI: 00:10.0: enabled 1
|
| PCI: 00:11.0: enabled 1
|
| PCI: 00:12.0: enabled 1
|
| PCI: 00:12.2: enabled 1
|
| PCI: 00:13.0: enabled 1
|
| PCI: 00:13.2: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| I2C: 01:50: enabled 1
|
| I2C: 01:51: enabled 1
|
| PCI: 00:14.2: enabled 1
|
| PCI: 00:14.3: enabled 1
|
| PCI: 00:14.7: enabled 1
|
| PCI: 00:18.0: enabled 1
|
| PCI: 00:18.1: enabled 1
|
| PCI: 00:18.2: enabled 1
|
| PCI: 00:18.3: enabled 1
|
| PCI: 00:18.4: enabled 1
|
| PCI: 00:18.5: enabled 1
|
| APIC: 01: enabled 1
|
| APIC: 02: enabled 1
|
| APIC: 03: enabled 1
|
| PCI: 00:08.0: enabled 1
|
| PCI: 01:00.0: enabled 1
|
| PCI: 01:00.1: enabled 1
|
| PCI: 01:00.2: enabled 1
|
| PCI: 01:00.3: enabled 1
|
| BS: BS_DEV_INIT times (us): entry 0 run 74888 exit 0
|
| CBMEM region bffc0000-bfffffff (cbmem_check_toc)
|
| CBMEM region bffc0000-bfffffff (cbmem_initialize_empty)
|
| Adding CBMEM entry as no. 1
|
| Moving GDT to bffc0200...ok
|
| Adding CBMEM entry as no. 2
|
| Finalize devices...
|
| Devices finalized
|
| agesawrapper_amdinitlate() entry
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00a, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = 1180000, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = 1080000, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = 1040000, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a008, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00f, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a00e, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
|
|
| EventLog: EventClass = 2, EventInfo = 8040100.
|
| Param1 = a010, Param2 = 0.
|
| Param3 = 0, Param4 = 0.
|
| ASSERTION FAILED: file 'src/mainboard/amd/olivehillplus/agesawrapper.c', line 369
|
| DmiTable:1001129f, AcpiPstatein: 1001011b, AcpiSrat:0,AcpiSlit:0, Mce:10011123, Cmc:100111e5,Alib:10012431, AcpiIvrs:0 in agesawrapper_amdinitlate
|
| agesawrapper_amdinitlate() returned AGESA_ERROR
|
| BS: BS_POST_DEVICE times (us): entry 256 run 53 exit 14584
|
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
|
| Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
|
| Adding CBMEM entry as no. 3
|
| Writing IRQ routing tables to 0xbffe0400...write_pirq_routing_table done.
|
| PIRQ table: 48 bytes.
|
| Wrote the mp table end at: 000f0410 - 000f05cc
|
| Adding CBMEM entry as no. 4
|
| Wrote the mp table end at: bffe1410 - bffe15cc
|
| MP table: 460 bytes.
|
| Adding CBMEM entry as no. 5
|
| ACPI: Writing ACPI tables at bffe2400...
|
| ACPI: * DSDT at bffe24c8
|
| ACPI: * DSDT @ bffe24c8 Length 167a
|
| ACPI: * FACS at bffe3b48
|
| ACPI: * FADT at bffe3b88
|
| pm_base: 0x0800
|
| ACPI: added table 1/32, length now 40
|
| ACPI: * HPET at bffe3c80
|
| ACPI: added table 2/32, length now 44
|
| ACPI: * MADT at bffe3cb8
|
| ACPI: added table 3/32, length now 48
|
| ACPI: added table 4/32, length now 52
|
| ACPI: * IVRS at bffe3f08
|
| AGESA IVRS table NULL. Skipping.
|
| ACPI: * SRAT at bffe3f08
|
| AGESA SRAT table NULL. Skipping.
|
| ACPI: * SLIT at bffe3f08
|
| AGESA SLIT table NULL. Skipping.
|
| ACPI: * AGESA ALIB SSDT at bffe3f10
|
| ACPI: added table 5/32, length now 56
|
| ACPI: * SSDT at bffe8790
|
| ACPI: added table 6/32, length now 60
|
| ACPI: * SSDT for PState at bffe8db4
|
| ACPI: * SSDT
|
| ACPI: added table 7/32, length now 64
|
| ACPI: done.
|
| ACPI tables: 27129 bytes.
|
| Adding CBMEM entry as no. 6
|
| smbios_write_tables: bffed800
|
| Root Device (AMD DB-FT3b)
|
| CPU_CLUSTER: 0 (AMD FAM16 Root Complex)
|
| APIC: 00 (AMD CPU Family 16h)
|
| DOMAIN: 0000 (AMD FAM16 Root Complex)
|
| PCI: 00:00.0 (AMD FAM16 Northbridge)
|
| PCI: 00:01.0 (AMD FAM16 Northbridge)
|
| PCI: 00:01.1 (AMD FAM16 Northbridge)
|
| PCI: 00:02.0 (AMD FAM16 Northbridge)
|
| PCI: 00:02.1 (AMD FAM16 Northbridge)
|
| PCI: 00:02.2 (AMD FAM16 Northbridge)
|
| PCI: 00:02.3 (AMD FAM16 Northbridge)
|
| PCI: 00:02.4 (AMD FAM16 Northbridge)
|
| PCI: 00:02.5 (AMD FAM16 Northbridge)
|
| PCI: 00:10.0 (ATI HUDSON)
|
| PCI: 00:11.0 (ATI HUDSON)
|
| PCI: 00:12.0 (ATI HUDSON)
|
| PCI: 00:12.2 (ATI HUDSON)
|
| PCI: 00:13.0 (ATI HUDSON)
|
| PCI: 00:13.2 (ATI HUDSON)
|
| PCI: 00:14.0 (ATI HUDSON)
|
| I2C: 01:50 (unknown)
|
| I2C: 01:51 (unknown)
|
| PCI: 00:14.2 (ATI HUDSON)
|
| PCI: 00:14.3 (ATI HUDSON)
|
| PCI: 00:14.7 (ATI HUDSON)
|
| PCI: 00:18.0 (AMD FAM16 Northbridge)
|
| PCI: 00:18.1 (AMD FAM16 Northbridge)
|
| PCI: 00:18.2 (AMD FAM16 Northbridge)
|
| PCI: 00:18.3 (AMD FAM16 Northbridge)
|
| PCI: 00:18.4 (AMD FAM16 Northbridge)
|
| PCI: 00:18.5 (AMD FAM16 Northbridge)
|
| APIC: 01 (unknown)
|
| APIC: 02 (unknown)
|
| APIC: 03 (unknown)
|
| PCI: 00:08.0 (unknown)
|
| PCI: 01:00.0 (unknown)
|
| PCI: 01:00.1 (unknown)
|
| PCI: 01:00.2 (unknown)
|
| PCI: 01:00.3 (unknown)
|
| SMBIOS tables: 333 bytes.
|
| Adding CBMEM entry as no. 7
|
| Writing table forward entry at 0x00000500
|
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5fdf
|
| Table forward entry ends at 0x00000528.
|
| ... aligned to 0x00001000
|
| Writing coreboot table at 0xbffee000
|
| rom_table_end = 0xbffee000
|
| ... aligned to 0xbfff0000
|
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
| 1. 0000000000001000-000000000009ffff: RAM
|
| 2. 00000000000c0000-00000000bffbffff: RAM
|
| 3. 00000000bffc0000-00000000bfffffff: CONFIGURATION TABLES
|
| 4. 00000000c0000000-00000000dfffffff: RESERVED
|
| 5. 00000000f8000000-00000000fbffffff: RESERVED
|
| 6. 0000000100000000-000000011effffff: RAM
|
| Wrote coreboot table at: bffee000, 0x174 bytes, checksum 63bd
|
| coreboot table: 396 bytes.
|
| FREE SPACE 0. bfff6000 0000a000
|
| GDT 1. bffc0200 00000200
|
| CONSOLE 2. bffc0400 00020000
|
| IRQ TABLE 3. bffe0400 00001000
|
| SMP TABLE 4. bffe1400 00001000
|
| ACPI 5. bffe2400 0000b400
|
| SMBIOS 6. bffed800 00000800
|
| COREBOOT 7. bffee000 00008000
|
| BS: BS_WRITE_TABLES times (us): entry 0 run 4867 exit 0
|
| CBFS: located payload @ ff83ea78, 56173 bytes.
|
| Loading segment from rom address 0xff83ea78
|
| code (compression=1)
|
| New segment dstaddr 0xe5c18 memsize 0x1a3e8 srcaddr 0xff83eab0 filesize 0xdb35
|
| (cleaned up) New segment addr 0xe5c18 size 0x1a3e8 offset 0xff83eab0 filesize 0xdb35
|
| Loading segment from rom address 0xff83ea94
|
| Entry Point 0x000fd58c
|
| Bounce Buffer at bfd99000, 2252888 bytes
|
| Loading Segment: addr: 0x00000000000e5c18 memsz: 0x000000000001a3e8 filesz: 0x000000000000db35
|
| lb: [0x0000000000200000, 0x000000000031302c)
|
| Post relocation: addr: 0x00000000000e5c18 memsz: 0x000000000001a3e8 filesz: 0x000000000000db35
|
| using LZMA
|
| [ 0x000e5c18, 00100000, 0x00100000) <- ff83eab0
|
| dest 000e5c18, end 00100000, bouncebuffer bfd99000
|
| Loaded segments
|
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 16495 exit 0
|
| Jumping to boot code at 000fd58c
|
| CPU0: stack: 00252000 - 00253000, lowest used address 002525e8, stack used: 2584 bytes
|
| entry = 0x000fd58c
|
| lb_start = 0x00200000
|
| lb_size = 0x0011302c
|
| buffer = 0xbfd99000
|
| SeaBIOS (version rel-1.7.5-42-g275672e-dirty-20140818_154755-toonie.localdomain) |
| Found coreboot cbmem console @ bffc0400 |
| Found mainboard AMD DB-FT3b |
| Relocating init from 0x000e6de0 to 0xbff750c0 (size 44672) |
| Found CBFS header at 0xfffffc50 |
| CPU Mhz=1198 |
| Found 23 PCI devices (max PCI bus is 01) |
| Copying PIR from 0xbffe0400 to 0x000f1c30 |
| Copying MPTABLE from 0xbffe1400/bffe1410 to 0x000f1a60 |
| Copying ACPI RSDP from 0xbffe2400 to 0x000f1a40 |
| Copying SMBIOS entry point from 0xbffed800 to 0x000f1a20 |
| Using pmtimer, ioport 0x818 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.7.5-42-g275672e-dirty-20140818_154755-toonie.localdomain) |
| XHCI init on dev 00:10.0: regs @ 0xf0c8a000, 4 ports, 32 slots, 32 byte contexts |
| XHCI extcap 0x1 @ f0c8a500 |
| XHCI protocol USB 3.00, 2 ports (offset 1), def 0 |
| XHCI protocol USB 2.00, 2 ports (offset 3), def 10 |
| XHCI extcap 0xa @ f0c8a540 |
| WARNING - Timeout at i8042_flush:71! |
| EHCI init on dev 00:12.0 (regs=0xf0c8d420) |
| Found 0 lpt ports |
| Found 0 serial ports |
| ATA controller 1 at 2410/2420/0 (irq 0 dev 88) |
| EHCI init on dev 00:13.0 (regs=0xf0c8d520) |
| ATA controller 2 at 2418/2424/0 (irq 0 dev 88) |
| ata0-0: ST3750525AS ATA-8 Hard-Disk (698 GiBytes) |
| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0 |
| XHCI no devices found |
| USB keyboard initialized |
| Initialized USB HUB (1 ports used) |
| Initialized USB HUB (0 ports used) |
| All threads complete. |
| Scan for option roms |
| |
| Press F12 for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f19d0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1465149168 |
| Space available for UMB: cf000-ef000, f0000-f19d0 |
| Returned 253952 bytes of ZoneHigh |
| e820 map has 7 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 00000000bffbe000 = 1 RAM |
| 4: 00000000bffbe000 - 00000000e0000000 = 2 RESERVED |
| 5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED |
| 6: 0000000100000000 - 000000011f000000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |