| 0x75 |
| PCI: 00:1c.4 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.4 init finished in 8 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 13 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| Set power on after power failure. |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| NMI sources enabled. |
| PantherPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 1466 usecs |
| POST: 0x75 |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| SATA: Controller in AHCI mode. |
| ABAR: f0614000 |
| PCI: 00:1f.2 init finished in 452 usecs |
| POST: 0x75 |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 0 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PNP: 002e.1 init ... |
| PNP: 002e.1 init finished in 0 usecs |
| POST: 0x75 |
| PNP: 002e.2 init ... |
| PNP: 002e.2 init finished in 0 usecs |
| POST: 0x75 |
| PNP: 002e.3 init ... |
| PNP: 002e.3 init finished in 0 usecs |
| POST: 0x75 |
| PNP: 002e.4 init ... |
| Unsupported thermal mode 0x0 on TMPIN1 |
| Unsupported thermal mode 0x0 on TMPIN2 |
| Unsupported thermal mode 0x0 on TMPIN3 |
| PNP: 002e.4 init finished in 24 usecs |
| POST: 0x75 |
| PNP: 002e.5 init ... |
| PNP: 002e.5 init finished in 28 usecs |
| POST: 0x75 |
| PNP: 002e.6 init ... |
| PNP: 002e.6 init finished in 0 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 02:00.0: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 12 run 276233 exit 0 |
| POST: 0x76 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 6 exit 0 |
| POST: 0x77 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 |
| Updating MRC cache data. |
| No MRC cache in cbmem. Can't update flash. |
| POST: 0x79 |
| POST: 0x9c |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Unmatched 'cmos_layout.bin' at 1c680 |
| CBFS: Checking offset 1cc80 |
| CBFS: File @ offset 1cc80 size 27e7 |
| CBFS: Found @ offset 1cc80 size 27e7 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Unmatched 'cmos_layout.bin' at 1c680 |
| CBFS: Checking offset 1cc80 |
| CBFS: File @ offset 1cc80 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1cc80 |
| CBFS: Checking offset 1f4c0 |
| CBFS: File @ offset 1f4c0 size 9d8 |
| CBFS: Unmatched '' at 1f4c0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a41f |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a380 |
| CBFS: File @ offset 4a380 size 2275c |
| CBFS: Unmatched 'img/nvramcui' at 4a380 |
| CBFS: Checking offset 6cb40 |
| CBFS: File @ offset 6cb40 size 8de72 |
| CBFS: Unmatched 'fallback/payload' at 6cb40 |
| CBFS: Checking offset faa00 |
| CBFS: File @ offset faa00 size 2c02c |
| CBFS: Unmatched 'img/memtest' at faa00 |
| CBFS: Checking offset 126a80 |
| CBFS: File @ offset 126a80 size 11f2 |
| CBFS: Unmatched 'grub.cfg' at 126a80 |
| CBFS: Checking offset 127cc0 |
| CBFS: File @ offset 127cc0 size 11ea |
| CBFS: Unmatched 'grubtest.cfg' at 127cc0 |
| CBFS: Checking offset 128f00 |
| CBFS: File @ offset 128f00 size 6b5f18 |
| CBFS: Unmatched '' at 128f00 |
| CBFS: Checking offset 7dee40 |
| CBFS: File @ offset 7dee40 size 1068 |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff13000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| PSS: 2501MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2500MHz power 45000 control 0x1900 status 0x1900 |
| PSS: 2200MHz power 38253 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 33948 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 29840 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 25920 control 0x1000 status 0x1000 |
| lpc_tpm: Read reg 0xf00 returns 0x1a15d1 |
| lpc_tpm: Read reg 0xc returns 0x0 |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: * TCPA |
| TCPA log created at 7ff02000 |
| ACPI: added table 3/32, length now 48 |
| ACPI: * MADT |
| ACPI: added table 4/32, length now 52 |
| current = 7ff185a0 |
| ACPI: * DMAR |
| ACPI: added table 5/32, length now 56 |
| current = 7ff18650 |
| GET_VBIOS: f31f 373 fb c2 52 |
| VBIOS not found. |
| ACPI: * HPET |
| ACPI: added table 6/32, length now 60 |
| ACPI: done. |
| ACPI tables: 22160 bytes. |
| smbios_write_tables: 7ff01000 |
| Create SMBIOS type 17 |
| Root Device (GIGABYTE GA-B75M-D3H) |
| CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| APIC: 00 (unknown) |
| APIC: acac (Intel SandyBridge/IvyBridge CPU) |
| DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge) |
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 03:00.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PNP: 002e.0 (ITE IT8728F Super I/O) |
| PNP: 002e.1 (ITE IT8728F Super I/O) |
| PNP: 002e.2 (ITE IT8728F Super I/O) |
| PNP: 002e.3 (ITE IT8728F Super I/O) |
| PNP: 002e.4 (ITE IT8728F Super I/O) |
| PNP: 002e.5 (ITE IT8728F Super I/O) |
| PNP: 002e.6 (ITE IT8728F Super I/O) |
| PNP: 002e.7 (ITE IT8728F Super I/O) |
| PNP: 002e.a (ITE IT8728F Super I/O) |
| PNP: 0c31.0 (LPC TPM) |
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) |
| PCI: 02:00.0 (unknown) |
| APIC: 01 (unknown) |
| APIC: 02 (unknown) |
| APIC: 03 (unknown) |
| APIC: 04 (unknown) |
| APIC: 05 (unknown) |
| APIC: 06 (unknown) |
| APIC: 07 (unknown) |
| SMBIOS tables: 767 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum feb |
| Writing coreboot table at 0x7ff37000 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b20 |
| memalign 7ffd4b20 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b38 |
| memalign 7ffd4b38 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b50 |
| memalign 7ffd4b50 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b68 |
| memalign 7ffd4b68 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b80 |
| memalign 7ffd4b80 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4b98 |
| memalign 7ffd4b98 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4bb0 |
| memalign 7ffd4bb0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4bc8 |
| memalign 7ffd4bc8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4be0 |
| memalign 7ffd4be0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4bf8 |
| memalign 7ffd4bf8 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff00fff: RAM |
| 4. 000000007ff01000-000000007fffffff: CONFIGURATION TABLES |
| 5. 0000000080000000-00000000829fffff: RESERVED |
| 6. 00000000f8000000-00000000fbffffff: RESERVED |
| 7. 00000000fed40000-00000000fed44fff: RESERVED |
| 8. 00000000fed90000-00000000fed91fff: RESERVED |
| 9. 0000000100000000-000000087b5fffff: RAM |
| read 6008 from 07e4 |
| wrote 00000004 to 0890 |
| read 02040003 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| read 0080 from 0870 |
| wrote 000c to 0870 |
| wrote 9f to 0878 |
| read 0000 from 0876 |
| wrote 0000 to 0876 |
| read 0000 from 0874 |
| wrote 00000000 to 07e8 |
| wrote 4402 to 0871 |
| read 0081 from 0870 |
| read 0084 from 0870 |
| wrote 0004 to 0870 |
| read c21720c2 from 07f0 |
| read 20 from 07f4 |
| wrote 0000 to 0874 |
| SF: Got idcode: c2 20 17 c2 20 |
| Manufacturer: c2 |
| SF: Detected MX25L6405D with sector size 0x1000, total 0x800000 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| FMAP: Found "FLASH" version 1.1 at 20000. |
| FMAP: base = ff800000 size = 800000 #areas = 3 |
| Wrote coreboot table at: 7ff37000, 0x950 bytes, checksum 2498 |
| coreboot table: 2408 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| TIME STAMP 3. 7ffdd000 00000400 |
| ROMSTG STCK 4. 7ffd8000 00005000 |
| RAMSTAGE 5. 7ff8b000 0004d000 |
| 57a9e100 6. 7ff3f000 0004ba50 |
| COREBOOT 7. 7ff37000 00008000 |
| ACPI 8. 7ff13000 00024000 |
| ACPI GNVS 9. 7ff12000 00001000 |
| TCPA LOG 10. 7ff02000 00010000 |
| SMBIOS 11. 7ff01000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| CAR GLOBALS 1. 7fffea40 000001c0 |
| USBDEBUG 2. 7fffe9e0 00000058 |
| MEM INFO 3. 7fffe880 00000141 |
| ROMSTAGE 4. 7fffe860 00000004 |
| 57a9e000 5. 7fffe840 00000010 |
| BS: BS_WRITE_TABLES times (us): entry 2 run 5357 exit 0 |
| POST: 0x7a |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Unmatched 'cmos_layout.bin' at 1c680 |
| CBFS: Checking offset 1cc80 |
| CBFS: File @ offset 1cc80 size 27e7 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 1cc80 |
| CBFS: Checking offset 1f4c0 |
| CBFS: File @ offset 1f4c0 size 9d8 |
| CBFS: Unmatched '' at 1f4c0 |
| CBFS: Checking offset 1fec0 |
| CBFS: File @ offset 1fec0 size 10000 |
| CBFS: Unmatched 'mrc.cache' at 1fec0 |
| CBFS: Checking offset 2ff00 |
| CBFS: File @ offset 2ff00 size 1a41f |
| CBFS: Unmatched 'fallback/ramstage' at 2ff00 |
| CBFS: Checking offset 4a380 |
| CBFS: File @ offset 4a380 size 2275c |
| CBFS: Unmatched 'img/nvramcui' at 4a380 |
| CBFS: Checking offset 6cb40 |
| CBFS: File @ offset 6cb40 size 8de72 |
| CBFS: Found @ offset 6cb40 size 8de72 |
| Loading segment from ROM address 0xff88cc78 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4c10 |
| memalign 7ffd4c10 |
| New segment dstaddr 0x8200 memsize 0x17824 srcaddr 0xff88cccc filesize 0x83b7 |
| Loading segment from ROM address 0xff88cc94 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4c2c |
| memalign 7ffd4c30 |
| New segment dstaddr 0x100000 memsize 0x205710 srcaddr 0xff895083 filesize 0x85a67 |
| Loading segment from ROM address 0xff88ccb0 |
| Entry Point 0x00008200 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c4c |
| memalign 7ffd4c50 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c68 |
| memalign 7ffd4c68 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c80 |
| memalign 7ffd4c80 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| lb: [0x000000007ff8c000, 0x000000007ffd7a50) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| using LZMA |
| [ 0x00008200, 00017feb, 0x0001fa24) <- ff88cccc |
| Clearing Segment: addr: 0x0000000000017feb memsz: 0x0000000000007a39 |
| dest 00008200, end 0001fa24, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000205710 filesz: 0x0000000000085a67 |
| lb: [0x000000007ff8c000, 0x000000007ffd7a50) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000205710 filesz: 0x0000000000085a67 |
| using LZMA |
| [ 0x00100000, 00305710, 0x00305710) <- ff895083 |
| dest 00100000, end 00305710, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 269733 exit 0 |
| POST: 0x7b |
| PCH watchdog disabled |
| Jumping to boot code at 00008200(7ff37000) |
| POST: 0xf8 |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcd880, stack used: 1920 bytes |
| 6cb40 size 8de72 |
| CBFS: Found @ offset 6cb40 size 8de72 |
| Loading segment from ROM address 0xff88cc78 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4c10 |
| memalign 7ffd4c10 |
| New segment dstaddr 0x8200 memsize 0x17824 srcaddr 0xff88cccc filesize 0x83b7 |
| Loading segment from ROM address 0xff88cc94 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4c2c |
| memalign 7ffd4c30 |
| New segment dstaddr 0x100000 memsize 0x205710 srcaddr 0xff895083 filesize 0x85a67 |
| Loading segment from ROM address 0xff88ccb0 |
| Entry Point 0x00008200 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c4c |
| memalign 7ffd4c50 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c68 |
| memalign 7ffd4c68 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c80 |
| memalign 7ffd4c80 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| lb: [0x000000007ff8c000, 0x000000007ffd7a50) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| using LZMA |
| [ 0x00008200, 00017feb, 0x0001fa24) <- ff88cccc |
| Clearing Segment: addr: 0x0000000000017feb memsz: 0x0000000000007a39 |
| dest 00008200, end 0001fa24, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000205710 filesz: 0x0000000000085a67 |
| lb: [0x000000007ff8c000, 0x000000007ffd7a50) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000205710 filesz: 0x0000000000085a67 |
| using LZMA |
| [ 0x00100000, 00305710, 0x00305710) <- ff895083 |
| dest 00100000, end 00305710, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 270202 exit 0 |
| POST: 0x7b |
| PCH watchdog disabled |
| Jumping to boot code at 00008200(7ff37000) |
| POST: 0xf8 |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcd880, stack used: 1920 bytes |
| img/nvramcui' at 4a380 |
| CBFS: Checking offset 6cb40 |
| CBFS: File @ offset 6cb40 size 8de72 |
| CBFS: Found @ offset 6cb40 size 8de72 |
| Loading segment from ROM address 0xff88cc78 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4c10 |
| memalign 7ffd4c10 |
| New segment dstaddr 0x8200 memsize 0x17824 srcaddr 0xff88cccc filesize 0x83b7 |
| Loading segment from ROM address 0xff88cc94 |
| code (compression=1) |
| memalign Enter, boundary 8, size 28, free_mem_ptr 7ffd4c2c |
| memalign 7ffd4c30 |
| New segment dstaddr 0x100000 memsize 0x205710 srcaddr 0xff895083 filesize 0x85a67 |
| Loading segment from ROM address 0xff88ccb0 |
| Entry Point 0x00008200 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c4c |
| memalign 7ffd4c50 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c68 |
| memalign 7ffd4c68 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4c80 |
| memalign 7ffd4c80 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| lb: [0x000000007ff8c000, 0x000000007ffd7a50) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017824 filesz: 0x00000000000083b7 |
| using LZMA |
| [ 0x00008200, 00017feb, 0x0001fa24) <- ff88cccc |
| Clearing Segment: addr: 0x0000000000017feb memsz: 0x0000000000007a39 |
| dest 00008200, end 0001fa24, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000205710 filesz: 0x0000000000085a67 |
| lb: [0x000000007ff8c000, 0x000000007ffd7a50) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000205710 filesz: 0x0000000000085a67 |
| using LZMA |
| [ 0x00100000, 00305710, 0x00305710) <- ff895083 |
| dest 00100000, end 00305710, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 269528 exit 0 |
| POST: 0x7b |
| PCH watchdog disabled |
| Jumping to boot code at 00008200(7ff37000) |
| POST: 0xf8 |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcd880, stack used: 1920 bytes |
| error: file `/background.jpg' not found. |
|
error: file `/dejavusansmono.pf2' not found. |
|
error: file `/boot/grub/layouts/usqwerty.gkb' not found. |
|
GNU GRUB version 2.02-1 |
|
|
|
+----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
|
Press enter to boot the selected OS, `e' to edit the co |
| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| 8b4 |
| REFI [4298] = 6cd01860 |
| SRFTP [42a4] = 41f88200 |
| DBP [4400] = 1c8bbb |
| RAP [4404] = cc186465 |
| OTHP [440c] = a08b4 |
| OTHP [440c] = 8b4 |
| REFI [4698] = 6cd01860 |
| SRFTP [46a4] = 41f88200 |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 8 |
| PCI(0, 0, 0)[bc] = 82a00000 |
| PCI(0, 0, 0)[a8] = 7b600000 |
| PCI(0, 0, 0)[ac] = 8 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| PCI(0, 0, 0)[7c] = 7f |
| PCI(0, 0, 0)[70] = fe000000 |
| PCI(0, 0, 0)[74] = 7 |
| PCI(0, 0, 0)[78] = fe000c00 |
| Done memory map |
| RCOMP...done |
| COMP2 done |
| COMP1 done |
| FORCE RCOMP and wait 20us...done |
| Done io registers |
| CPE |
| CP5b |
| CP5c |
| OTHP [400c] = 8b4 |
| OTHP [440c] = 8b4 |
| t123: 1767, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Waiting for DID BIOS message |
| ME: FWS2: 0x101f015a |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x1 |
| ME: CPU replaced : 0x1 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x1f |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| Full training required |
| PASSED! Tell ME that DRAM is ready |
| ME: FWS2: 0x102c015a |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x1 |
| ME: CPU replaced : 0x1 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x2c |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: Continue to boot |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : 0x2c |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1596 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00662020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 8192 MB width x8 dual rank |
| memcfg channel[1] config (00662020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 8192 MB width x8 dual rank |
| CBMEM entry for DIMM info: 0x7fffe880 |
| POST: 0x3b |
| POST: 0x3c |
| POST: 0x3d |
| TPM initialization. |
| TPM: Init |
| lpc_tpm: Read reg 0xf00 returns 0xffffffff |
| tis_probe: No TPM device found |
| POST: 0x3f |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| Jumping to image. |
| Capability: type 0x01 @ 0x50 |
| Capability: type 0x0a @ 0x58 |
| |
| |
| coreboot-4.6-824-g41114650d0 Sun Jul 23 20:34:11 UTC 2017 ramstage starting... |
| POST: 0x39 |
| POST: 0x80 |
| S3 Resume. |
| POST: 0x70 |
| BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 |
| POST: 0x71 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 |
| POST: 0x72 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| POST: 0x24 |
| PCI: 00:00.0 [8086/0150] ops |
| PCI: 00:00.0 [8086/0150] enabled |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| PCI: 00:01.0 subordinate bus PCI Express |
| PCI: 00:01.0 [8086/0151] enabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0162] enabled |
| PCI: 00:14.0 [8086/0000] ops |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0 [8086/1e3a] ops |
| PCI: 00:16.0 [8086/1e3a] enabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0: Disabling device |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1e10] enabled |
| PCI: 00:1c.1: Disabling device |
| PCI: 00:1c.2: Disabling device |
| PCI: 00:1c.3: Disabling device |
| PCI: 00:1c.4 [8086/0000] bus ops |
| PCI: 00:1c.4 [8086/1e18] enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfed4ba90 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1e26] enabled |
| Capability: type 0x0d @ 0x50 |
| Capability: type 0x0d @ 0x50 |
| PCI: 00:1e.0 [8086/244e] enabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1e49] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| PCI: 00:1f.2 [8086/1e00] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1e22] enabled |
| PCI: 00:1f.4: Disabling device |
| PCI: 00:1f.5: Disabling device |
| POST: 0x25 |
| PCI: 00:01.0 scanning... |
| do_pci_scan_bridge for PCI: 00:01.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3a50 |
| memalign 7ffd3a50 |
| PCI: pci_scan_bus for bus 01 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: scanning of bus PCI: 00:01.0 took 21 usecs |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3a74 |
| memalign 7ffd3a78 |
| PCI: pci_scan_bus for bus 02 |
| POST: 0x24 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd3a9c |
| memalign 7ffd3aa0 |
| PCI: 02:00.0 [168c/002a] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x60 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled L1 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 211 usecs |
| PCI: 00:1c.4 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.4 |
| PCI: pci_scan_bus for bus 03 |
| POST: 0x24 |
| PCI: 03:00.0 [10ec/8168] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Capability: type 0x01 @ 0x40 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x10 @ 0x70 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| scan_bus: scanning of bus PCI: 00:1c.4 took 207 usecs |
| PCI: 00:1e.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1e.0 |
| memalign Enter, boundary 8, size 36, free_mem_ptr 7ffd3b38 |
| memalign 7ffd3b38 |
| PCI: pci_scan_bus for bus 04 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: scanning of bus PCI: 00:1e.0 took 50 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| memalign Enter, boundary 8, size 2560, free_mem_ptr 7ffd3b5c |
| memalign 7ffd3b60 |
| PNP: 002e.0 disabled |
| PNP: 002e.1 enabled |
| PNP: 002e.2 enabled |
| PNP: 002e.3 enabled |
| PNP: 002e.4 enabled |
| PNP: 002e.5 enabled |
| PNP: 002e.6 enabled |
| PNP: 002e.7 disabled |
| PNP: 002e.a disabled |
| PNP: 0c31.0 enabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 199 usecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 5 usecs |
| POST: 0x55 |
| scan_bus: scanning of bus DOMAIN: 0000 took 1023 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 1032 usecs |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 1166 exit 0 |
| POST: 0x73 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. |
| PCI: 00:01.0 read_resources bus 1 link: 0 |
| PCI: 00:01.0 read_resources bus 1 link: 0 done |
| PCI: 00:1a.0 EHCI BAR hook registered |
| PCI: 00:1c.0 read_resources bus 2 link: 0 |
| PCI: 00:1c.0 read_resources bus 2 link: 0 done |
| PCI: 00:1c.4 read_resources bus 3 link: 0 |
| PCI: 00:1c.4 read_resources bus 3 link: 0 done |
| More than one caller of pci_ehci_read_resources from PCI: 00:1d.0 |
| PCI: 00:1e.0 read_resources bus 4 link: 0 |
| PCI: 00:1e.0 read_resources bus 4 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.1 |
| PCI: 00:1c.2 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1f.0 child on link 0 PNP: 002e.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PNP: 002e.0 |
| PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| PNP: 002e.1 |
| PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.2 |
| PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.3 |
| PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60 |
| PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 |
| PNP: 002e.4 |
| PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags c0000100 index 60 |
| PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags c0000100 index 62 |
| PNP: 002e.5 |
| PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 |
| PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 |
| PNP: 002e.6 |
| PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| PNP: 002e.7 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.a |
| PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1f.4 |
| PCI: 00:1f.5 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 03:00.0 10 * [0x0 - 0xff] io |
| PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:1f.2 20 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 10 * [0x1060 - 0x1067] io |
| PCI: 00:1f.2 18 * [0x1068 - 0x106f] io |
| PCI: 00:1f.2 14 * [0x1070 - 0x1073] io |
| PCI: 00:1f.2 1c * [0x1074 - 0x1077] io |
| DOMAIN: 0000 io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 02:00.0 10 * [0x0 - 0xffff] mem |
| PCI: 00:1c.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem |
| PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem |
| PCI: 00:1c.4 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem |
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem |
| PCI: 00:1c.4 24 * [0x10500000 - 0x105fffff] prefmem |
| PCI: 00:14.0 10 * [0x10600000 - 0x1060ffff] mem |
| PCI: 00:1b.0 10 * [0x10610000 - 0x10613fff] mem |
| PCI: 00:1f.2 24 * [0x10614000 - 0x106147ff] mem |
| PCI: 00:1a.0 10 * [0x10615000 - 0x106153ff] mem |
| PCI: 00:1d.0 10 * [0x10616000 - 0x106163ff] mem |
| PCI: 00:1f.3 10 * [0x10617000 - 0x106170ff] mem |
| PCI: 00:16.0 10 * [0x10618000 - 0x1061800f] mem |
| DOMAIN: 0000 mem: base: 10618010 size: 10618010 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f8000000 limit fbffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:1000 size:1078 align:12 gran:0 limit:ffff |
| PCI: 00:1c.4 1c * [0x1000 - 0x1fff] io |
| PCI: 00:02.0 20 * [0x2000 - 0x203f] io |
| PCI: 00:1f.2 20 * [0x2040 - 0x205f] io |
| PCI: 00:1f.2 10 * [0x2060 - 0x2067] io |
| PCI: 00:1f.2 18 * [0x2068 - 0x206f] io |
| PCI: 00:1f.2 14 * [0x2070 - 0x2073] io |
| PCI: 00:1f.2 1c * [0x2074 - 0x2077] io |
| DOMAIN: 0000 io: next_base: 2078 size: 1078 align: 12 gran: 0 done |
| PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.4 io: base:1000 size:1000 align:12 gran:12 limit:1fff |
| PCI: 03:00.0 10 * [0x1000 - 0x10ff] io |
| PCI: 00:1c.4 io: next_base: 1100 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1e.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1e.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:e0000000 size:10618010 align:28 gran:0 limit:f7ffffff |
| PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem |
| PCI: 00:02.0 10 * [0xf0000000 - 0xf03fffff] mem |
| PCI: 00:1c.0 20 * [0xf0400000 - 0xf04fffff] mem |
| PCI: 00:1c.4 24 * [0xf0500000 - 0xf05fffff] prefmem |
| PCI: 00:14.0 10 * [0xf0600000 - 0xf060ffff] mem |
| PCI: 00:1b.0 10 * [0xf0610000 - 0xf0613fff] mem |
| PCI: 00:1f.2 24 * [0xf0614000 - 0xf06147ff] mem |
| PCI: 00:1a.0 10 * [0xf0615000 - 0xf06153ff] mem |
| PCI: 00:1d.0 10 * [0xf0616000 - 0xf06163ff] mem |
| PCI: 00:1f.3 10 * [0xf0617000 - 0xf06170ff] mem |
| PCI: 00:16.0 10 * [0xf0618000 - 0xf061800f] mem |
| DOMAIN: 0000 mem: next_base: f0618010 size: 10618010 align: 28 gran: 0 done |
| PCI: 00:01.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:01.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:01.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:01.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:f0400000 size:100000 align:20 gran:20 limit:f04fffff |
| PCI: 02:00.0 10 * [0xf0400000 - 0xf040ffff] mem |
| PCI: 00:1c.0 mem: next_base: f0410000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.4 prefmem: base:f0500000 size:100000 align:20 gran:20 limit:f05fffff |
| PCI: 03:00.0 20 * [0xf0500000 - 0xf0503fff] prefmem |
| PCI: 03:00.0 18 * [0xf0504000 - 0xf0504fff] prefmem |
| PCI: 00:1c.4 prefmem: next_base: f0505000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.4 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1c.4 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1e.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1e.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1e.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff |
| PCI: 00:1e.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x87b600000 TOLUD 0x82a00000 TOM 0x800000000 |
| MEBASE 0x7fe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 30646M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:01.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:01.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io |
| PCI: 00:14.0 10 <- [0x00f0600000 - 0x00f060ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:16.0 10 <- [0x00f0618000 - 0x00f061800f] size 0x00000010 gran 0x04 mem64 |
| PCI: 00:1a.0 EHCI Debug Port hook triggered |
| PCI: 00:1a.0 10 <- [0x00f0615000 - 0x00f06153ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 10 <- [0x00f0615000 - 0x00f06153ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 EHCI Debug Port relocated |
| PCI: 00:1b.0 10 <- [0x00f0610000 - 0x00f0613fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.0 20 <- [0x00f0400000 - 0x00f04fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| PCI: 02:00.0 10 <- [0x00f0400000 - 0x00f040ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io |
| PCI: 00:1c.4 24 <- [0x00f0500000 - 0x00f05fffff] size 0x00100000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.4 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io |
| PCI: 03:00.0 18 <- [0x00f0504000 - 0x00f0504fff] size 0x00001000 gran 0x0c prefmem64 |
| PCI: 03:00.0 20 <- [0x00f0500000 - 0x00f0503fff] size 0x00004000 gran 0x0e prefmem64 |
| PCI: 00:1c.4 assign_resources, bus 3 link: 0 |
| PCI: 00:1d.0 10 <- [0x00f0616000 - 0x00f06163ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| PCI: 00:1e.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1e.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq |
| PNP: 002e.3 60 <- [0x0000000378 - 0x000000037b] size 0x00000004 gran 0x02 io |
| PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq |
| PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq |
| PNP: 002e.4 60 <- [0x0000000a30 - 0x0000000a37] size 0x00000008 gran 0x03 io |
| PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq |
| PNP: 002e.4 62 <- [0x0000000a20 - 0x0000000a27] size 0x00000008 gran 0x03 io |
| PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io |
| PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq |
| PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io |
| PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00f0614000 - 0x00f06147ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00f0617000 - 0x00f06170ff] size 0x00000100 gran 0x08 mem64 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 1000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base e0000000 size 10618010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 77b600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:01.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:01.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base f0000000 size 400000 align 22 gran 22 limit f03fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 20 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base f0600000 size 10000 align 16 gran 16 limit f060ffff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base f0618000 size 10 align 12 gran 4 limit f061800f flags 60000201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base f0615000 size 400 align 12 gran 10 limit f06153ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base f0610000 size 4000 align 14 gran 14 limit f0613fff flags 60000201 index 10 |
| PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base f0400000 size 100000 align 20 gran 20 limit f04fffff flags 60080202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base f0400000 size 10000 align 16 gran 16 limit f040ffff flags 60000201 index 10 |
| PCI: 00:1c.1 |
| PCI: 00:1c.2 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.4 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c |
| PCI: 00:1c.4 resource base f0500000 size 100000 align 20 gran 20 limit f05fffff flags 60081202 index 24 |
| PCI: 00:1c.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10 |
| PCI: 03:00.0 resource base f0504000 size 1000 align 12 gran 12 limit f0504fff flags 60001201 index 18 |
| PCI: 03:00.0 resource base f0500000 size 4000 align 14 gran 14 limit f0503fff flags 60001201 index 20 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base f0616000 size 400 align 12 gran 10 limit f06163ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 |
| PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 |
| PCI: 00:1f.0 child on link 0 PNP: 002e.0 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PNP: 002e.0 |
| PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| PNP: 002e.1 |
| PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.2 |
| PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.3 |
| PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags e0000100 index 60 |
| PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 |
| PNP: 002e.4 |
| PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags e0000100 index 60 |
| PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags e0000100 index 62 |
| PNP: 002e.5 |
| PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 |
| PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 |
| PNP: 002e.6 |
| PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| PNP: 002e.7 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 |
| PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 |
| PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 002e.a |
| PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 |
| PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 2070 size 4 align 2 gran 2 limit 2073 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 2074 size 4 align 2 gran 2 limit 2077 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 2040 size 20 align 5 gran 5 limit 205f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base f0614000 size 800 align 12 gran 11 limit f06147ff flags 60000200 index 24 |
| PCI: 00:1f.3 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base f0617000 size 100 align 12 gran 8 limit f06170ff flags 60000201 index 10 |
| PCI: 00:1f.4 |
| PCI: 00:1f.5 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2635 exit 0 |
| POST: 0x74 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 1458/5000 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:01.0 bridge ctrl <- 0003 |
| PCI: 00:01.0 cmd <- 00 |
| PCI: 00:02.0 subsystem <- 1458/d000 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:14.0 subsystem <- 1458/5007 |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:16.0 subsystem <- 1458/5000 |
| PCI: 00:16.0 cmd <- 02 |
| PCI: 00:1a.0 subsystem <- 1458/5006 |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 1458/a002 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 1458/5000 |
| PCI: 00:1c.0 cmd <- 106 |
| PCI: 00:1c.4 bridge ctrl <- 0003 |
| PCI: 00:1c.4 subsystem <- 1458/5000 |
| PCI: 00:1c.4 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 1458/5006 |
| PCI: 00:1d.0 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0003 |
| PCI: 00:1e.0 cmd <- 100 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 1458/5001 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 1458/b005 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 1458/5001 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 02:00.0 cmd <- 02 |
| PCI: 03:00.0 subsystem <- 1458/e000 |
| PCI: 03:00.0 cmd <- 103 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 234 exit 0 |
| read 6000 from 07e4 |
| wrote 00000004 to 0890 |
| read 02040003 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| POST: 0x75 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 3 usecs |
| POST: 0x75 |
| CPU_CLUSTER: 0 init ... |
| memalign Enter, boundary 8, size 49, free_mem_ptr 7ffd4560 |
| memalign 7ffd4560 |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 12 relocs. Offset value of 0x00038000 |
| Adjusting 00038002: 0x00000024 -> 0x00038024 |
| Adjusting 0003801d: 0x0000003c -> 0x0003803c |
| Adjusting 00038026: 0x00000024 -> 0x00038024 |
| Adjusting 00038054: 0x00000120 -> 0x00038120 |
| Adjusting 00038066: 0x000001a8 -> 0x000381a8 |
| Adjusting 0003806f: 0x00000100 -> 0x00038100 |
| Adjusting 00038077: 0x00000104 -> 0x00038104 |
| Adjusting 00038081: 0x00000110 -> 0x00038110 |
| Adjusting 0003808a: 0x00000114 -> 0x00038114 |
| Adjusting 000380ab: 0x00000118 -> 0x00038118 |
| Adjusting 000380b2: 0x0000010c -> 0x0003810c |
| Adjusting 000380b8: 0x00000108 -> 0x00038108 |
| SMM Module: stub loaded at 00038000. Will call 7ffac7ce(7ffd39c0) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 8001156d. filesize: 0x3658 memsize: 0x7678 |
| Processing 211 relocs. Offset value of 0x80010000 |
| Adjusting 80010592: 0x00002c24 -> 0x80012c24 |
| Adjusting 800105b1: 0x00002c24 -> 0x80012c24 |
| Adjusting 8001066e: 0x00002e6e -> 0x80012e6e |
| Adjusting 80010685: 0x00002c24 -> 0x80012c24 |
| Adjusting 800106fb: 0x00002c34 -> 0x80012c34 |
| Adjusting 8001072e: 0x00002c4f -> 0x80012c4f |
| Adjusting 80010763: 0x00002c58 -> 0x80012c58 |
| Adjusting 800107ba: 0x00002c79 -> 0x80012c79 |
| Adjusting 80010831: 0x00002c8e -> 0x80012c8e |
| Adjusting 80010868: 0x00002cac -> 0x80012cac |
| Adjusting 8001088c: 0x00002ccd -> 0x80012ccd |
| Adjusting 800108a5: 0x00002cf0 -> 0x80012cf0 |
| Adjusting 80010a7f: 0x00003640 -> 0x80013640 |
| Adjusting 80010a96: 0x00002d1c -> 0x80012d1c |
| Adjusting 80010aa9: 0x00003640 -> 0x80013640 |
| Adjusting 80010ab5: 0x00002eac -> 0x80012eac |
| Adjusting 80010aba: 0x00002ec9 -> 0x80012ec9 |
| Adjusting 80010abf: 0x00002ecc -> 0x80012ecc |
| Adjusting 80010ac4: 0x00002d28 -> 0x80012d28 |
| Adjusting 80010af7: 0x00003644 -> 0x80013644 |
| Adjusting 80010b0d: 0x00000ad3 -> 0x80010ad3 |
| Adjusting 80010b21: 0x00003644 -> 0x80013644 |
| Adjusting 80010b33: 0x00003644 -> 0x80013644 |
| Adjusting 80010b46: 0x00002d71 -> 0x80012d71 |
| Adjusting 80010b4f: 0x00002d4c -> 0x80012d4c |
| Adjusting 8001107b: 0x00002d96 -> 0x80012d96 |
| Adjusting 800112d5: 0x00003658 -> 0x80013658 |
| Adjusting 800112f7: 0x00002d9d -> 0x80012d9d |
| Adjusting 80011324: 0x00002db6 -> 0x80012db6 |
| Adjusting 8001134d: 0x00003650 -> 0x80013650 |
| Adjusting 80011367: 0x000035a0 -> 0x800135a0 |
| Adjusting 8001137b: 0x000034b1 -> 0x800134b1 |
| Adjusting 8001139a: 0x000034e2 -> 0x800134e2 |
| Adjusting 800113b1: 0x000034ec -> 0x800134ec |
| Adjusting 800113c8: 0x000034f1 -> 0x800134f1 |
| Adjusting 800113df: 0x000034fa -> 0x800134fa |
| Adjusting 800113f6: 0x00003507 -> 0x80013507 |
| Adjusting 8001140d: 0x00003513 -> 0x80013513 |
| Adjusting 80011424: 0x00003520 -> 0x80013520 |
| Adjusting 8001143b: 0x0000352b -> 0x8001352b |
| Adjusting 80011452: 0x00003537 -> 0x80013537 |
| Adjusting 80011469: 0x00003541 -> 0x80013541 |
| Adjusting 80011480: 0x00003546 -> 0x80013546 |
| Adjusting 80011497: 0x0000354e -> 0x8001354e |
| Adjusting 800114ae: 0x00003555 -> 0x80013555 |
| Adjusting 800114c5: 0x0000355a -> 0x8001355a |
| Adjusting 800114dc: 0x00003560 -> 0x80013560 |
| Adjusting 800114f2: 0x00003565 -> 0x80013565 |
| Adjusting 80011508: 0x00003570 -> 0x80013570 |
| Adjusting 8001151e: 0x00003575 -> 0x80013575 |
| Adjusting 80011534: 0x0000357e -> 0x8001357e |
| Adjusting 8001154a: 0x0000358a -> 0x8001358a |
| Adjusting 8001155b: 0x000032d8 -> 0x800132d8 |
| Adjusting 80011577: 0x00003658 -> 0x80013658 |
| Adjusting 80011585: 0x00003658 -> 0x80013658 |
| Adjusting 80011596: 0x00002dc8 -> 0x80012dc8 |
| Adjusting 800115aa: 0x00003648 -> 0x80013648 |
| Adjusting 800115b5: 0x00003648 -> 0x80013648 |
| Adjusting 800115c8: 0x0000365c -> 0x8001365c |
| Adjusting 800115d4: 0x00002df5 -> 0x80012df5 |
| Adjusting 800115e4: 0x0000364c -> 0x8001364c |
| Adjusting 800115ed: 0x0000364c -> 0x8001364c |
| Adjusting 8001160a: 0x0000365c -> 0x8001365c |
| Adjusting 80011613: 0x00003648 -> 0x80013648 |
| Adjusting 8001162c: 0x00003660 -> 0x80013660 |
| Adjusting 8001163c: 0x00003660 -> 0x80013660 |
| Adjusting 80011662: 0x00003660 -> 0x80013660 |
| Adjusting 800116ca: 0x00002e00 -> 0x80012e00 |
| Adjusting 800116dd: 0x00002e10 -> 0x80012e10 |
| Adjusting 8001171d: 0x00002e4f -> 0x80012e4f |
| Adjusting 80011800: 0x00002c10 -> 0x80012c10 |
| Adjusting 8001182a: 0x00002c08 -> 0x80012c08 |
| Adjusting 8001182f: 0x00002e83 -> 0x80012e83 |
| Adjusting 80011b24: 0x00003664 -> 0x80013664 |
| Adjusting 80011b53: 0x00003668 -> 0x80013668 |
| Adjusting 80011b66: 0x00003664 -> 0x80013664 |
| Adjusting 80011b89: 0x00003668 -> 0x80013668 |
| Adjusting 80011bd7: 0x00002ee0 -> 0x80012ee0 |
| Adjusting 80011c24: 0x00002ee0 -> 0x80012ee0 |
| Adjusting 80011c6e: 0x00003664 -> 0x80013664 |
| Adjusting 80011d04: 0x00002efc -> 0x80012efc |
| Adjusting 80011d92: 0x00002f24 -> 0x80012f24 |
| Adjusting 80011e27: 0x0000303a -> 0x8001303a |
| Adjusting 80011e6c: 0x00002f8c -> 0x80012f8c |
| Adjusting 80011e7d: 0x00002fd4 -> 0x80012fd4 |
| Adjusting 80011ec9: 0x00002ff4 -> 0x80012ff4 |
| Adjusting 80011ef9: 0x00003018 -> 0x80013018 |
| Adjusting 80011f21: 0x00002f50 -> 0x80012f50 |
| Adjusting 80011f56: 0x00002f6e -> 0x80012f6e |
| Adjusting 80011f6c: 0x00003668 -> 0x80013668 |
| Adjusting 80011fe7: 0x00003138 -> 0x80013138 |
| Adjusting 80011fec: 0x00003073 -> 0x80013073 |
| Adjusting 80012019: 0x0000307b -> 0x8001307b |
| Adjusting 80012048: 0x00002efc -> 0x80012efc |
| Adjusting 800120d7: 0x00002f24 -> 0x80012f24 |
| Adjusting 800120f9: 0x00003668 -> 0x80013668 |
| Adjusting 80012185: 0x0000303a -> 0x8001303a |
| Adjusting 800121ca: 0x000030c5 -> 0x800130c5 |
| Adjusting 800121db: 0x00002fd4 -> 0x80012fd4 |
| Adjusting 800121fb: 0x00003668 -> 0x80013668 |
| Adjusting 8001222f: 0x0000310c -> 0x8001310c |
| Adjusting 80012274: 0x00002f50 -> 0x80012f50 |
| Adjusting 8001229f: 0x0000309e -> 0x8001309e |
| Adjusting 80012368: 0x00003650 -> 0x80013650 |
| Adjusting 80012377: 0x00003149 -> 0x80013149 |
| Adjusting 80012395: 0x00003154 -> 0x80013154 |
| Adjusting 800123b2: 0x0000315c -> 0x8001315c |
| Adjusting 800123c9: 0x00003162 -> 0x80013162 |
| Adjusting 800123e0: 0x0000316a -> 0x8001316a |
| Adjusting 800123f7: 0x00003170 -> 0x80013170 |
| Adjusting 8001240e: 0x00003175 -> 0x80013175 |
| Adjusting 80012425: 0x0000317d -> 0x8001317d |
| Adjusting 8001243c: 0x00003186 -> 0x80013186 |
| Adjusting 80012452: 0x0000318a -> 0x8001318a |
| Adjusting 80012468: 0x00003193 -> 0x80013193 |
| Adjusting 8001247e: 0x0000319c -> 0x8001319c |
| Adjusting 80012494: 0x0000350d -> 0x8001350d |
| Adjusting 800124aa: 0x000031a2 -> 0x800131a2 |
| Adjusting 800124c0: 0x000031a8 -> 0x800131a8 |
| Adjusting 800124d6: 0x000031af -> 0x800131af |
| Adjusting 800124ec: 0x000031b8 -> 0x800131b8 |
| Adjusting 800124fd: 0x000032d8 -> 0x800132d8 |
| Adjusting 8001256e: 0x00003670 -> 0x80013670 |
| Adjusting 800125a5: 0x000031c9 -> 0x800131c9 |
| Adjusting 800125c4: 0x000031d7 -> 0x800131d7 |
| Adjusting 800125da: 0x000031f4 -> 0x800131f4 |
| Adjusting 800125f9: 0x00003201 -> 0x80013201 |
| Adjusting 80012609: 0x0000320e -> 0x8001320e |
| Adjusting 80012618: 0x000031c3 -> 0x800131c3 |
| Adjusting 80012623: 0x000031be -> 0x800131be |
| Adjusting 8001262c: 0x0000321f -> 0x8001321f |
| Adjusting 80012646: 0x00003231 -> 0x80013231 |
| Adjusting 80012663: 0x00003650 -> 0x80013650 |
| Adjusting 8001268b: 0x00003251 -> 0x80013251 |
| Adjusting 8001269c: 0x00003650 -> 0x80013650 |
| Adjusting 800126c9: 0x00003273 -> 0x80013273 |
| Adjusting 800126e7: 0x00003262 -> 0x80013262 |
| Adjusting 800126f0: 0x00003650 -> 0x80013650 |
| Adjusting 80012702: 0x00003284 -> 0x80013284 |
| Adjusting 80012718: 0x00003650 -> 0x80013650 |
| Adjusting 8001272a: 0x0000329a -> 0x8001329a |
| Adjusting 80012734: 0x00003674 -> 0x80013674 |
| Adjusting 8001273e: 0x000032af -> 0x800132af |
| Adjusting 8001277d: 0x0000366c -> 0x8001366c |
| Adjusting 80012787: 0x000032da -> 0x800132da |
| Adjusting 800127aa: 0x0000366c -> 0x8001366c |
| Adjusting 800127cb: 0x00003674 -> 0x80013674 |
| Adjusting 800127d2: 0x000032f3 -> 0x800132f3 |
| Adjusting 800127d7: 0x00003670 -> 0x80013670 |
| Adjusting 800127e2: 0x00003650 -> 0x80013650 |
| Adjusting 800127f4: 0x0000330d -> 0x8001330d |
| Adjusting 80012806: 0x00003650 -> 0x80013650 |
| Adjusting 80012846: 0x0000331c -> 0x8001331c |
| Adjusting 80012861: 0x00003332 -> 0x80013332 |
| Adjusting 80012876: 0x00003650 -> 0x80013650 |
| Adjusting 80012888: 0x00003340 -> 0x80013340 |
| Adjusting 8001289f: 0x00003650 -> 0x80013650 |
| Adjusting 800128ad: 0x00003356 -> 0x80013356 |
| Adjusting 800128c5: 0x00003366 -> 0x80013366 |
| Adjusting 800128dc: 0x00003360 -> 0x80013360 |
| Adjusting 800128f3: 0x0000336b -> 0x8001336b |
| Adjusting 8001290a: 0x00003374 -> 0x80013374 |
| Adjusting 80012925: 0x00003379 -> 0x80013379 |
| Adjusting 8001293b: 0x00003381 -> 0x80013381 |
| Adjusting 80012951: 0x00003386 -> 0x80013386 |
| Adjusting 80012967: 0x0000338a -> 0x8001338a |
| Adjusting 80012978: 0x000032d8 -> 0x800132d8 |
| Adjusting 80012985: 0x00003650 -> 0x80013650 |
| Adjusting 80012996: 0x00003391 -> 0x80013391 |
| Adjusting 800129ab: 0x00003650 -> 0x80013650 |
| Adjusting 800129d4: 0x0000339d -> 0x8001339d |
| Adjusting 800129f1: 0x00003650 -> 0x80013650 |
| Adjusting 80012a0a: 0x000033b1 -> 0x800133b1 |
| Adjusting 80012a22: 0x00003590 -> 0x80013590 |
| Adjusting 80012a27: 0x00003670 -> 0x80013670 |
| Adjusting 80012aab: 0x00003490 -> 0x80013490 |
| Adjusting 80012ab2: 0x000033c5 -> 0x800133c5 |
| Adjusting 80012abe: 0x000033dd -> 0x800133dd |
| Adjusting 80012aca: 0x00003401 -> 0x80013401 |
| Adjusting 80012b1f: 0x00003425 -> 0x80013425 |
| Adjusting 80012b28: 0x0000344a -> 0x8001344a |
| Adjusting 80012b36: 0x00003650 -> 0x80013650 |
| Adjusting 80012b69: 0x0000346e -> 0x8001346e |
| Adjusting 80012b7a: 0x00003650 -> 0x80013650 |
| Adjusting 80012ba6: 0x00003650 -> 0x80013650 |
| Adjusting 80012bba: 0x000034a8 -> 0x800134a8 |
| Adjusting 80012bc6: 0x00003670 -> 0x80013670 |
| Adjusting 80012bdd: 0x00003650 -> 0x80013650 |
| Adjusting 80012c08: 0x00002bf0 -> 0x80012bf0 |
| Adjusting 80012c10: 0x0000057d -> 0x8001057d |
| Adjusting 80012c14: 0x00002bf0 -> 0x80012bf0 |
| Adjusting 80012c1c: 0x000005ee -> 0x800105ee |
| Adjusting 80012c28: 0x00002d08 -> 0x80012d08 |
| Adjusting 80012d08: 0x000008ee -> 0x800108ee |
| Adjusting 80012d0c: 0x000008fa -> 0x800108fa |
| Adjusting 80012d10: 0x000008fd -> 0x800108fd |
| Adjusting 80013490: 0x00002aaf -> 0x80012aaf |
| Adjusting 80013494: 0x00002abb -> 0x80012abb |
| Adjusting 80013498: 0x00002b66 -> 0x80012b66 |
| Adjusting 8001349c: 0x00002ac7 -> 0x80012ac7 |
| Adjusting 800134a0: 0x00002b1c -> 0x80012b1c |
| Adjusting 800134a4: 0x00002b25 -> 0x80012b25 |
| Adjusting 800135b0: 0x000029bc -> 0x800129bc |
| Adjusting 800135b4: 0x000026ac -> 0x800126ac |
| Adjusting 800135c0: 0x00002897 -> 0x80012897 |
| Adjusting 800135c4: 0x00002360 -> 0x80012360 |
| Adjusting 800135c8: 0x0000265c -> 0x8001265c |
| Adjusting 800135cc: 0x00002874 -> 0x80012874 |
| Adjusting 800135d4: 0x00002803 -> 0x80012803 |
| Adjusting 800135d8: 0x000027e0 -> 0x800127e0 |
| Adjusting 800135f4: 0x0000250e -> 0x8001250e |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 12 relocs. Offset value of 0x80008000 |
| Adjusting 80008002: 0x00000024 -> 0x80008024 |
| Adjusting 8000801d: 0x0000003c -> 0x8000803c |
| Adjusting 80008026: 0x00000024 -> 0x80008024 |
| Adjusting 80008054: 0x00000120 -> 0x80008120 |
| Adjusting 80008066: 0x000001a8 -> 0x800081a8 |
| Adjusting 8000806f: 0x00000100 -> 0x80008100 |
| Adjusting 80008077: 0x00000104 -> 0x80008104 |
| Adjusting 80008081: 0x00000110 -> 0x80008110 |
| Adjusting 8000808a: 0x00000114 -> 0x80008114 |
| Adjusting 800080ab: 0x00000118 -> 0x80008118 |
| Adjusting 800080b2: 0x0000010c -> 0x8000810c |
| Adjusting 800080b8: 0x00000108 -> 0x80008108 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at 80006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd |
| SMM Module: stub loaded at 80008000. Will call 8001156d(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: PM1 |
| PM1_STS: WAK PWRBTN TMROF |
| GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 |
| ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4591 |
| memalign 7ffd4598 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45b0 |
| memalign 7ffd45b0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45c8 |
| memalign 7ffd45c8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45e0 |
| memalign 7ffd45e0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd45f8 |
| memalign 7ffd45f8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4610 |
| memalign 7ffd4610 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4628 |
| memalign 7ffd4628 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4640 |
| memalign 7ffd4640 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4658 |
| memalign 7ffd4658 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4670 |
| memalign 7ffd4670 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4688 |
| memalign 7ffd4688 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd46a0 |
| memalign 7ffd46a0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd46b8 |
| memalign 7ffd46b8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd46d0 |
| memalign 7ffd46d0 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd46e8 |
| memalign 7ffd46e8 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4700 |
| memalign 7ffd4700 |
| memalign Enter, boundary 8, size 24, free_mem_ptr 7ffd4718 |
| memalign 7ffd4718 |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000e0000000 size 0x60000000 type 0 |
| 0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1 |
| 0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0 |
| 0x0000000100000000 - 0x000000087b600000 size 0x77b600000 type 6 |
| MTRR addr 0x0-0x10 set to 6 type @ 0 |
| MTRR addr 0x10-0x20 set to 6 type @ 1 |
| MTRR addr 0x20-0x30 set to 6 type @ 2 |
| MTRR addr 0x30-0x40 set to 6 type @ 3 |
| MTRR addr 0x40-0x50 set to 6 type @ 4 |
| MTRR addr 0x50-0x60 set to 6 type @ 5 |
| MTRR addr 0x60-0x70 set to 6 type @ 6 |
| MTRR addr 0x70-0x80 set to 6 type @ 7 |
| MTRR addr 0x80-0x84 set to 6 type @ 8 |
| MTRR addr 0x84-0x88 set to 6 type @ 9 |
| MTRR addr 0x88-0x8c set to 6 type @ 10 |
| MTRR addr 0x8c-0x90 set to 6 type @ 11 |
| MTRR addr 0x90-0x94 set to 6 type @ 12 |
| MTRR addr 0x94-0x98 set to 6 type @ 13 |
| MTRR addr 0x98-0x9c set to 6 type @ 14 |
| MTRR addr 0x9c-0xa0 set to 6 type @ 15 |
| MTRR addr 0xa0-0xa4 set to 0 type @ 16 |
| MTRR addr 0xa4-0xa8 set to 0 type @ 17 |
| MTRR addr 0xa8-0xac set to 0 type @ 18 |
| MTRR addr 0xac-0xb0 set to 0 type @ 19 |
| MTRR addr 0xb0-0xb4 set to 0 type @ 20 |
| MTRR addr 0xb4-0xb8 set to 0 type @ 21 |
| MTRR addr 0xb8-0xbc set to 0 type @ 22 |
| MTRR addr 0xbc-0xc0 set to 0 type @ 23 |
| MTRR addr 0xc0-0xc1 set to 6 type @ 24 |
| MTRR addr 0xc1-0xc2 set to 6 type @ 25 |
| MTRR addr 0xc2-0xc3 set to 6 type @ 26 |
| MTRR addr 0xc3-0xc4 set to 6 type @ 27 |
| MTRR addr 0xc4-0xc5 set to 6 type @ 28 |
| MTRR addr 0xc5-0xc6 set to 6 type @ 29 |
| MTRR addr 0xc6-0xc7 set to 6 type @ 30 |
| MTRR addr 0xc7-0xc8 set to 6 type @ 31 |
| MTRR addr 0xc8-0xc9 set to 6 type @ 32 |
| MTRR addr 0xc9-0xca set to 6 type @ 33 |
| MTRR addr 0xca-0xcb set to 6 type @ 34 |
| MTRR addr 0xcb-0xcc set to 6 type @ 35 |
| MTRR addr 0xcc-0xcd set to 6 type @ 36 |
| MTRR addr 0xcd-0xce set to 6 type @ 37 |
| MTRR addr 0xce-0xcf set to 6 type @ 38 |
| MTRR addr 0xcf-0xd0 set to 6 type @ 39 |
| MTRR addr 0xd0-0xd1 set to 6 type @ 40 |
| MTRR addr 0xd1-0xd2 set to 6 type @ 41 |
| MTRR addr 0xd2-0xd3 set to 6 type @ 42 |
| MTRR addr 0xd3-0xd4 set to 6 type @ 43 |
| MTRR addr 0xd4-0xd5 set to 6 type @ 44 |
| MTRR addr 0xd5-0xd6 set to 6 type @ 45 |
| MTRR addr 0xd6-0xd7 set to 6 type @ 46 |
| MTRR addr 0xd7-0xd8 set to 6 type @ 47 |
| MTRR addr 0xd8-0xd9 set to 6 type @ 48 |
| MTRR addr 0xd9-0xda set to 6 type @ 49 |
| MTRR addr 0xda-0xdb set to 6 type @ 50 |
| MTRR addr 0xdb-0xdc set to 6 type @ 51 |
| MTRR addr 0xdc-0xdd set to 6 type @ 52 |
| MTRR addr 0xdd-0xde set to 6 type @ 53 |
| MTRR addr 0xde-0xdf set to 6 type @ 54 |
| MTRR addr 0xdf-0xe0 set to 6 type @ 55 |
| MTRR addr 0xe0-0xe1 set to 6 type @ 56 |
| MTRR addr 0xe1-0xe2 set to 6 type @ 57 |
| MTRR addr 0xe2-0xe3 set to 6 type @ 58 |
| MTRR addr 0xe3-0xe4 set to 6 type @ 59 |
| MTRR addr 0xe4-0xe5 set to 6 type @ 60 |
| MTRR addr 0xe5-0xe6 set to 6 type @ 61 |
| MTRR addr 0xe6-0xe7 set to 6 type @ 62 |
| MTRR addr 0xe7-0xe8 set to 6 type @ 63 |
| MTRR addr 0xe8-0xe9 set to 6 type @ 64 |
| MTRR addr 0xe9-0xea set to 6 type @ 65 |
| MTRR addr 0xea-0xeb set to 6 type @ 66 |
| MTRR addr 0xeb-0xec set to 6 type @ 67 |
| MTRR addr 0xec-0xed set to 6 type @ 68 |
| MTRR addr 0xed-0xee set to 6 type @ 69 |
| MTRR addr 0xee-0xef set to 6 type @ 70 |
| MTRR addr 0xef-0xf0 set to 6 type @ 71 |
| MTRR addr 0xf0-0xf1 set to 6 type @ 72 |
| MTRR addr 0xf1-0xf2 set to 6 type @ 73 |
| MTRR addr 0xf2-0xf3 set to 6 type @ 74 |
| MTRR addr 0xf3-0xf4 set to 6 type @ 75 |
| MTRR addr 0xf4-0xf5 set to 6 type @ 76 |
| MTRR addr 0xf5-0xf6 set to 6 type @ 77 |
| MTRR addr 0xf6-0xf7 set to 6 type @ 78 |
| MTRR addr 0xf7-0xf8 set to 6 type @ 79 |
| MTRR addr 0xf8-0xf9 set to 6 type @ 80 |
| MTRR addr 0xf9-0xfa set to 6 type @ 81 |
| MTRR addr 0xfa-0xfb set to 6 type @ 82 |
| MTRR addr 0xfb-0xfc set to 6 type @ 83 |
| MTRR addr 0xfc-0xfd set to 6 type @ 84 |
| MTRR addr 0xfd-0xfe set to 6 type @ 85 |
| MTRR addr 0xfe-0xff set to 6 type @ 86 |
| MTRR addr 0xff-0x100 set to 6 type @ 87 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/12. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0 |
| MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0 |
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x00 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 4 cores, 2 threads per core |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4730 |
| memalign 7ffd4730 |
| CPU: 0 has core 1 |
| CPU1: stack_base 7ffcc000, stack_end 7ffccff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd47c8 |
| CPU: vendor Intel device 306a9 |
| memalign 7ffd47c8 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: 0 has core 2 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x01 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #1 initialized |
| CPU2: stack_base 7ffcb000, stack_end 7ffcbff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4860 |
| memalign 7ffd4860 |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x02 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #2 initialized |
| CPU3: stack_base 7ffca000, stack_end 7ffcaff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd48f8 |
| memalign 7ffd48f8 |
| CPU: 0 has core 4 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x03 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #3 initialized |
| CPU4: stack_base 7ffc9000, stack_end 7ffc9ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 4. |
| After apic_write. |
| In relocation handler: cpu 4 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 4. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4990 |
| memalign 7ffd4990 |
| CPU: 0 has core 5 |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x04 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #4 initialized |
| CPU5: stack_base 7ffc8000, stack_end 7ffc8ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 5. |
| After apic_write. |
| In relocation handler: cpu 5 |
| New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 5. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4a28 |
| memalign 7ffd4a28 |
| CPU: 0 has core 6 |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x05 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #5 initialized |
| CPU6: stack_base 7ffc7000, stack_end 7ffc7ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 6. |
| After apic_write. |
| In relocation handler: cpu 6 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 6. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| memalign Enter, boundary 8, size 152, free_mem_ptr 7ffd4ac0 |
| memalign 7ffd4ac0 |
| CPU: 0 has core 7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x0 |
| microcode: updated to revision 0x1b date=2014-05-29 |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x06 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #6 initialized |
| CPU7: stack_base 7ffc6000, stack_end 7ffc6ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 7. |
| After apic_write. |
| In relocation handler: cpu 7 |
| New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 7. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #7 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Found @ offset 16640 size 5800 |
| microcode: sig=0x306a9 pf=0x2 revision=0x1b |
| CPU: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz. |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| Setting up local APIC... apic_id: 0x07 done. |
| POST: 0x9b |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| CPU #7 initialized |
| All AP CPUs stopped (577 loops) |
| CPU0: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcd9e0, stack used: 1568 bytes |
| CPU1: stack: 7ffcc000 - 7ffcd000, lowest used address 7ffccc00, stack used: 1024 bytes |
| CPU2: stack: 7ffcb000 - 7ffcc000, lowest used address 7ffcbc00, stack used: 1024 bytes |
| CPU3: stack: 7ffca000 - 7ffcb000, lowest used address 7ffcac00, stack used: 1024 bytes |
| CPU4: stack: 7ffc9000 - 7ffca000, lowest used address 7ffc9c00, stack used: 1024 bytes |
| CPU5: stack: 7ffc8000 - 7ffc9000, lowest used address 7ffc8c00, stack used: 1024 bytes |
| CPU6: stack: 7ffc7000 - 7ffc8000, lowest used address 7ffc7c00, stack used: 1024 bytes |
| CPU7: stack: 7ffc6000 - 7ffc7000, lowest used address 7ffc6c00, stack used: 1024 bytes |
| CPU_CLUSTER: 0 init finished in 257801 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling Device 4. |
| Disabling PEG60. |
| Disabling Device 7. |
| Set BIOS_RESET_CPL |
| CPU TDP: 45 Watts |
| PCI: 00:00.0 init finished in 1015 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| [0.263316] HW.GFX.GMA.Initialize |
| [0.263320] HW.GFX.GMA.Registers.Read: 0x80862805 <- 0x000e5020:PCH_AUD_VID_DID |
| [0.263323] HW.GFX.GMA.Panel.Setup_PP_Sequencer |
| [0.263325] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS |
| [0.263329] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.263332] HW.GFX.GMA.Registers.Read: 0x00186904 <- 0x000c7210:PCH_PP_DIVISOR |
| [0.263334] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS |
| [0.263337] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS |
| [0.263339] HW.GFX.GMA.Registers.Write: 0x48340001 -> 0x000c7208:PCH_PP_ON_DELAYS |
| [0.263342] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS |
| [0.263345] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.263347] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.263350] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR |
| [0.263352] HW.GFX.GMA.Registers.Read: 0x00186904 <- 0x000c7210:PCH_PP_DIVISOR |
| [0.263354] HW.GFX.GMA.Registers.Write: 0x00186904 -> 0x000c7210:PCH_PP_DIVISOR |
| [0.263357] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL |
| [0.263359] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL |
| [0.263361] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL |
| [0.263364] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A |
| [0.263366] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x00064000:DDI_BUF_CTL_A |
| [0.263368] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB |
| [0.263370] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB |
| [0.263372] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B |
| [0.263374] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4100:PCH_DP_B |
| [0.263376] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL |
| [0.263378] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL |
| [0.263380] HW.GFX.GMA.Registers.Write: 0x00000013 -> 0x000c4030:SHOTPLUG_CTL |
| [0.263382] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC |
| [0.263384] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000e1150:PCH_HDMIC |
| [0.263386] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C |
| [0.263388] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000e4200:PCH_DP_C |
| [0.263390] HW.GFX.GMA.Registers.Unset_Mask: 0x00031303 !S SHOTPLUG_CTL |
| [0.263393] HW.GFX.GMA.Registers.Read: 0x00000010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.263395] HW.GFX.GMA.Registers.Write: 0x00000010 -> 0x000c4030:SHOTPLUG_CTL |
| [0.263397] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID |
| [0.263399] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1160:PCH_HDMID |
| [0.263401] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D |
| [0.263403] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4300:PCH_DP_D |
| [0.263405] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL |
| [0.263407] HW.GFX.GMA.Registers.Read: 0x00000010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.263409] HW.GFX.GMA.Registers.Write: 0x00130010 -> 0x000c4030:SHOTPLUG_CTL |
| [0.263513] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S VGACNTRL |
| [0.263515] HW.GFX.GMA.Registers.Read: 0x00002900 <- 0x00041000:VGACNTRL |
| [0.263517] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:VGACNTRL |
| [0.263519] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL |
| [0.263523] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.263527] HW.GFX.GMA.Registers.Set_Mask: 0x00004000 .S PCH_DREF_CONTROL |
| [0.263530] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.263532] HW.GFX.GMA.Registers.Write: 0x00005402 -> 0x000c6200:PCH_DREF_CONTROL |
| [0.263536] HW.GFX.GMA.Registers.Read: 0x00005402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.263559] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ |
| [0.263562] HW.GFX.GMA.Registers.Read: 0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ |
| [0.263564] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ |
| [0.263567] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.263568] HW.GFX.GMA.I2C.I2C_Read |
| [0.263569] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.263570] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.263573] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 |
| [0.263575] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 |
| [0.263578] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.263581] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.263583] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.263586] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.263686] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.263688] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.263689] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.263692] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.263695] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.263696] HW.GFX.GMA.I2C.I2C_Read |
| [0.263697] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.263698] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.263701] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.263703] HW.GFX.GMA.I2C.Reset_GMBUS |
| [0.263704] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.263707] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.263710] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.263713] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2 |
| [0.263715] HW.GFX.GMA.Registers.Write: 0x00000006 -> 0x000c5100:PCH_GMBUS0 |
| [0.263718] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.263721] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.263724] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.263727] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264253] HW.GFX.GMA.Registers.Read: 0x00008a04 <- 0x000c5108:PCH_GMBUS2 |
| [0.264256] HW.GFX.GMA.Registers.Read: 0xffffff00 <- 0x000c510c:PCH_GMBUS3 |
| [0.264258] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264531] HW.GFX.GMA.Registers.Read: 0x00008a08 <- 0x000c5108:PCH_GMBUS2 |
| [0.264533] HW.GFX.GMA.Registers.Read: 0x00ffffff <- 0x000c510c:PCH_GMBUS3 |
| [0.264535] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.264813] HW.GFX.GMA.Registers.Read: 0x00008a0c <- 0x000c5108:PCH_GMBUS2 |
| [0.264816] HW.GFX.GMA.Registers.Read: 0x00006c50 <- 0x000c510c:PCH_GMBUS3 |
| [0.264818] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265092] HW.GFX.GMA.Registers.Read: 0x00008a10 <- 0x000c5108:PCH_GMBUS2 |
| [0.265095] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.265097] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265370] HW.GFX.GMA.Registers.Read: 0x00008a14 <- 0x000c5108:PCH_GMBUS2 |
| [0.265373] HW.GFX.GMA.Registers.Read: 0x03011432 <- 0x000c510c:PCH_GMBUS3 |
| [0.265375] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265649] HW.GFX.GMA.Registers.Read: 0x00008a18 <- 0x000c5108:PCH_GMBUS2 |
| [0.265652] HW.GFX.GMA.Registers.Read: 0x782e5281 <- 0x000c510c:PCH_GMBUS3 |
| [0.265654] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.265928] HW.GFX.GMA.Registers.Read: 0x00008a1c <- 0x000c5108:PCH_GMBUS2 |
| [0.265931] HW.GFX.GMA.Registers.Read: 0xa3b0d90b <- 0x000c510c:PCH_GMBUS3 |
| [0.265933] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266206] HW.GFX.GMA.Registers.Read: 0x00008a20 <- 0x000c5108:PCH_GMBUS2 |
| [0.266209] HW.GFX.GMA.Registers.Read: 0x259c4957 <- 0x000c510c:PCH_GMBUS3 |
| [0.266211] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266487] HW.GFX.GMA.Registers.Read: 0x00008a24 <- 0x000c5108:PCH_GMBUS2 |
| [0.266490] HW.GFX.GMA.Registers.Read: 0xa94b4911 <- 0x000c510c:PCH_GMBUS3 |
| [0.266492] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.266766] HW.GFX.GMA.Registers.Read: 0x00008a28 <- 0x000c5108:PCH_GMBUS2 |
| [0.266769] HW.GFX.GMA.Registers.Read: 0x009500cf <- 0x000c510c:PCH_GMBUS3 |
| [0.266771] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267044] HW.GFX.GMA.Registers.Read: 0x00008a2c <- 0x000c5108:PCH_GMBUS2 |
| [0.267047] HW.GFX.GMA.Registers.Read: 0xc08100b3 <- 0x000c510c:PCH_GMBUS3 |
| [0.267049] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267322] HW.GFX.GMA.Registers.Read: 0x00008a30 <- 0x000c5108:PCH_GMBUS2 |
| [0.267325] HW.GFX.GMA.Registers.Read: 0x40810081 <- 0x000c510c:PCH_GMBUS3 |
| [0.267327] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267602] HW.GFX.GMA.Registers.Read: 0x00008a34 <- 0x000c5108:PCH_GMBUS2 |
| [0.267604] HW.GFX.GMA.Registers.Read: 0x40a98081 <- 0x000c510c:PCH_GMBUS3 |
| [0.267606] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.267880] HW.GFX.GMA.Registers.Read: 0x00008a38 <- 0x000c5108:PCH_GMBUS2 |
| [0.267883] HW.GFX.GMA.Registers.Read: 0x211bc0d1 <- 0x000c510c:PCH_GMBUS3 |
| [0.267885] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.268158] HW.GFX.GMA.Registers.Read: 0x00008a3c <- 0x000c5108:PCH_GMBUS2 |
| [0.268161] HW.GFX.GMA.Registers.Read: 0x0051a050 <- 0x000c510c:PCH_GMBUS3 |
| [0.268163] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.268437] HW.GFX.GMA.Registers.Read: 0x00008a40 <- 0x000c5108:PCH_GMBUS2 |
| [0.268439] HW.GFX.GMA.Registers.Read: 0x8848301e <- 0x000c510c:PCH_GMBUS3 |
| [0.268441] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.268715] HW.GFX.GMA.Registers.Read: 0x00008a44 <- 0x000c5108:PCH_GMBUS2 |
| [0.268718] HW.GFX.GMA.Registers.Read: 0x00000035 <- 0x000c510c:PCH_GMBUS3 |
| [0.268720] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.268994] HW.GFX.GMA.Registers.Read: 0x00008a48 <- 0x000c5108:PCH_GMBUS2 |
| [0.268997] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.268999] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.269272] HW.GFX.GMA.Registers.Read: 0x00008a4c <- 0x000c5108:PCH_GMBUS2 |
| [0.269275] HW.GFX.GMA.Registers.Read: 0x80001f0e <- 0x000c510c:PCH_GMBUS3 |
| [0.269277] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.269550] HW.GFX.GMA.Registers.Read: 0x00008a50 <- 0x000c5108:PCH_GMBUS2 |
| [0.269553] HW.GFX.GMA.Registers.Read: 0x301e0051 <- 0x000c510c:PCH_GMBUS3 |
| [0.269555] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.269829] HW.GFX.GMA.Registers.Read: 0x00008a54 <- 0x000c5108:PCH_GMBUS2 |
| [0.269832] HW.GFX.GMA.Registers.Read: 0x00378040 <- 0x000c510c:PCH_GMBUS3 |
| [0.269834] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.270106] HW.GFX.GMA.Registers.Read: 0x00008a58 <- 0x000c5108:PCH_GMBUS2 |
| [0.270109] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.270111] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.270384] HW.GFX.GMA.Registers.Read: 0x00008a5c <- 0x000c5108:PCH_GMBUS2 |
| [0.270386] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.270388] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.270665] HW.GFX.GMA.Registers.Read: 0x00008a60 <- 0x000c5108:PCH_GMBUS2 |
| [0.270668] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.270670] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.270943] HW.GFX.GMA.Registers.Read: 0x00008a64 <- 0x000c5108:PCH_GMBUS2 |
| [0.270946] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.270948] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.271223] HW.GFX.GMA.Registers.Read: 0x00008a68 <- 0x000c5108:PCH_GMBUS2 |
| [0.271226] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.271228] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.271503] HW.GFX.GMA.Registers.Read: 0x00008a6c <- 0x000c5108:PCH_GMBUS2 |
| [0.271506] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.271508] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.271782] HW.GFX.GMA.Registers.Read: 0x00008a70 <- 0x000c5108:PCH_GMBUS2 |
| [0.271785] HW.GFX.GMA.Registers.Read: 0xfc000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.271787] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.272060] HW.GFX.GMA.Registers.Read: 0x00008a74 <- 0x000c5108:PCH_GMBUS2 |
| [0.272063] HW.GFX.GMA.Registers.Read: 0x4c435400 <- 0x000c510c:PCH_GMBUS3 |
| [0.272065] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.272339] HW.GFX.GMA.Registers.Read: 0x00008a78 <- 0x000c5108:PCH_GMBUS2 |
| [0.272341] HW.GFX.GMA.Registers.Read: 0x3831534d <- 0x000c510c:PCH_GMBUS3 |
| [0.272343] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.272617] HW.GFX.GMA.Registers.Read: 0x00008a7c <- 0x000c5108:PCH_GMBUS2 |
| [0.272620] HW.GFX.GMA.Registers.Read: 0x20200a31 <- 0x000c510c:PCH_GMBUS3 |
| [0.272622] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.272896] HW.GFX.GMA.Registers.Read: 0x0000ca80 <- 0x000c5108:PCH_GMBUS2 |
| [0.272899] HW.GFX.GMA.Registers.Read: 0xd5012020 <- 0x000c510c:PCH_GMBUS3 |
| [0.272901] HW.GFX.GMA.Registers.Wait: 0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2 |
| [0.272904] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.272907] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 |
| [0.272928] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.272929] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.272932] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.272935] EDID+0x0000: 00 ff ff ff ff ff ff 00 50 6c 00 00 00 00 00 00 |
| [0.272938] EDID+0x0010: 32 14 01 03 81 52 2e 78 0b d9 b0 a3 57 49 9c 25 |
| [0.272941] EDID+0x0020: 11 49 4b a9 cf 00 95 00 b3 00 81 c0 81 00 81 40 |
| [0.272944] EDID+0x0030: 81 80 a9 40 d1 c0 1b 21 50 a0 51 00 1e 30 48 88 |
| [0.272947] EDID+0x0040: 35 00 00 00 00 00 00 00 0e 1f 00 80 51 00 1e 30 |
| [0.272949] EDID+0x0050: 40 80 37 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| [0.272951] EDID+0x0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc |
| [0.272953] EDID+0x0070: 00 54 43 4c 4d 53 31 38 31 0a 20 20 20 20 01 d5 |
| [0.272956] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.272957] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.272959] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.272961] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 |
| [0.272964] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.272967] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.272969] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.272972] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273466] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273468] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.273470] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273472] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 |
| [0.273475] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.273477] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273479] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273482] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273976] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273978] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.273980] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273982] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 |
| [0.273985] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.273987] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273989] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.273992] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.274487] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.274489] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.274490] HW.GFX.GMA.I2C.I2C_Read |
| [0.274491] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.274492] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.274496] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 |
| [0.274498] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0 |
| [0.274501] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.274504] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.274507] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.274510] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.274610] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.274612] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.274613] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.274615] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| |
| [0.274617] CONFIG => |
| [0.274617] (Primary => |
| [0.274618] (Port => HDMI3 , |
| [0.274619] Framebuffer => |
| [0.274619] (Width => 1360, |
| [0.274621] Height => 768, |
| [0.274622] Stride => 1408, |
| [0.274623] Offset => 0x00000000, |
| [0.274624] BPC => 8), |
| [0.274625] Mode => |
| [0.274625] (Dotclock => 84750000, |
| [0.274627] H_Visible => 1360, |
| [0.274628] H_Sync_Begin => 1432, |
| [0.274629] H_Sync_End => 1568, |
| [0.274630] H_Total => 1776, |
| [0.274631] V_Visible => 768, |
| [0.274632] V_Sync_Begin => 771, |
| [0.274633] V_Sync_End => 776, |
| [0.274634] V_Total => 798, |
| [0.274635] H_Sync_Active_High => False, |
| [0.274636] V_Sync_Active_High => False, |
| [0.274637] BPC => 5)), |
| [0.274638] Secondary => |
| [0.274638] (Port => Disabled, |
| [0.274640] Framebuffer => |
| [0.274640] (Width => 1, |
| [0.274642] Height => 1, |
| [0.274643] Stride => 1, |
| [0.274644] Offset => 0x00000000, |
| [0.274645] BPC => 8), |
| [0.274646] Mode => |
| [0.274646] (Dotclock => 24000000, |
| [0.274648] H_Visible => 1, |
| [0.274649] H_Sync_Begin => 1, |
| [0.274650] H_Sync_End => 1, |
| [0.274651] H_Total => 1, |
| [0.274652] V_Visible => 1, |
| [0.274653] V_Sync_Begin => 1, |
| [0.274654] V_Sync_End => 1, |
| [0.274655] V_Total => 1, |
| [0.274656] H_Sync_Active_High => False, |
| [0.274657] V_Sync_Active_High => False, |
| [0.274658] BPC => 5)), |
| [0.274659] Tertiary => |
| [0.274659] (Port => Disabled, |
| [0.274660] Framebuffer => |
| [0.274661] (Width => 1, |
| [0.274662] Height => 1, |
| [0.274663] Stride => 1, |
| [0.274664] Offset => 0x00000000, |
| [0.274665] BPC => 8), |
| [0.274666] Mode => |
| [0.274666] (Dotclock => 24000000, |
| [0.274668] H_Visible => 1, |
| [0.274669] H_Sync_Begin => 1, |
| [0.274670] H_Sync_End => 1, |
| [0.274671] H_Total => 1, |
| [0.274672] V_Visible => 1, |
| [0.274673] V_Sync_Begin => 1, |
| [0.274674] V_Sync_End => 1, |
| [0.274675] V_Total => 1, |
| [0.274676] H_Sync_Active_High => False, |
| [0.274677] V_Sync_Active_High => False, |
| [0.274678] BPC => 5))); |
| |
| [0.275319] Trying to enable port HDMI3 |
| [0.275320] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting |
| [0.275321] HW.GFX.GMA.PLLs.Alloc |
| [0.275322] HW.GFX.GMA.PLLs.On |
| [0.275402] Valid clock found. |
| [0.275403] Best/Target/Delta: 84750000/84750000/0. |
| [0.275405] HW.GFX.GMA.PLLs.Program_DPLL |
| [0.275406] HW.GFX.GMA.Registers.Write: 0x00021306 -> 0x000c6040:PCH_FPA0 |
| [0.275409] HW.GFX.GMA.Registers.Write: 0x00021306 -> 0x000c6044:PCH_FPA1 |
| [0.275412] HW.GFX.GMA.Registers.Write: 0x44080008 -> 0x000c6014:PCH_DPLL_A |
| [0.275415] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DPLL_A |
| [0.275417] HW.GFX.GMA.Registers.Read: 0x44080008 <- 0x000c6014:PCH_DPLL_A |
| [0.275419] HW.GFX.GMA.Registers.Write: 0xc4080008 -> 0x000c6014:PCH_DPLL_A |
| [0.275423] HW.GFX.GMA.Registers.Read: 0xc4080008 <- 0x000c6014:PCH_DPLL_A |
| [0.275577] HW.GFX.GMA.Connectors.Pre_On |
| [0.275578] HW.GFX.GMA.Connectors.FDI.Pre_On |
| [0.275579] HW.GFX.GMA.Registers.Write: 0x00200090 -> 0x000f0010:FDI_RX_MISC_A |
| [0.275582] HW.GFX.GMA.Registers.Write: 0x7e000000 -> 0x000f0030:FDI_RXA_TUSIZE1 |
| [0.275585] HW.GFX.GMA.Registers.Unset_Mask: 0x00000700 !S FDI_RXA_IMR |
| [0.275588] HW.GFX.GMA.Registers.Read: 0x00000fff <- 0x000f0018:FDI_RXA_IMR |
| [0.275590] HW.GFX.GMA.Registers.Write: 0x000008ff -> 0x000f0018:FDI_RXA_IMR |
| [0.275593] HW.GFX.GMA.Registers.Read: 0x000008ff <- 0x000f0018:FDI_RXA_IMR |
| [0.275595] HW.GFX.GMA.Registers.Write: 0x00000700 -> 0x000f0014:FDI_RXA_IIR |
| [0.275598] HW.GFX.GMA.Registers.Write: 0x00002840 -> 0x000f000c:FDI_RXA_CTL |
| [0.275601] HW.GFX.GMA.Registers.Read: 0x00002840 <- 0x000f000c:FDI_RXA_CTL |
| [0.275824] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S FDI_RXA_CTL |
| [0.275827] HW.GFX.GMA.Registers.Read: 0x00002840 <- 0x000f000c:FDI_RXA_CTL |
| [0.275829] HW.GFX.GMA.Registers.Write: 0x00002850 -> 0x000f000c:FDI_RXA_CTL |
| [0.275832] HW.GFX.GMA.Registers.Write: 0x00044800 -> 0x00060100:FDI_TX_CTL_A |
| [0.275834] HW.GFX.GMA.Registers.Read: 0x00044800 <- 0x00060100:FDI_TX_CTL_A |
| [0.275937] HW.GFX.GMA.Pipe_Setup.On |
| [0.275938] HW.GFX.GMA.Transcoder.Setup |
| [0.275939] HW.GFX.GMA.Transcoder.Setup_Link |
| [0.275940] HW.GFX.GMA.DP_Info.Calculate_M_N |
| [0.275941] HW.GFX.GMA.Registers.Write: 0x7e788888 -> 0x00060030:PIPEA_DATA_M1 |
| [0.275943] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x00060034:PIPEA_DATA_N1 |
| [0.275945] HW.GFX.GMA.Registers.Write: 0x000505b0 -> 0x00060040:PIPEA_LINK_M1 |
| [0.275947] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x00060044:PIPEA_LINK_N1 |
| [0.275949] HW.GFX.GMA.Registers.Write: 0x06ef054f -> 0x00060000:HTOTAL_A |
| [0.275951] HW.GFX.GMA.Registers.Write: 0x06ef054f -> 0x00060004:HBLANK_A |
| [0.275953] HW.GFX.GMA.Registers.Write: 0x061f0597 -> 0x00060008:HSYNC_A |
| [0.275955] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x0006000c:VTOTAL_A |
| [0.275957] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x00060010:VBLANK_A |
| [0.275959] HW.GFX.GMA.Registers.Write: 0x03070302 -> 0x00060014:VSYNC_A |
| [0.275961] HW.GFX.GMA.Pipe_Setup.Setup_Display |
| [0.275962] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane |
| [0.275963] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DSPACNTR |
| [0.275964] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070180:DSPACNTR |
| [0.275966] HW.GFX.GMA.Registers.Write: 0x98004000 -> 0x00070180:DSPACNTR |
| [0.275968] HW.GFX.GMA.Registers.Write: 0x00001600 -> 0x00070188:DSPASTRIDE |
| [0.275970] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF |
| [0.275972] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070184:DSPALINOFF |
| [0.275974] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF |
| [0.275976] HW.GFX.GMA.Registers.Write: 0x054f02ff -> 0x0006001c:PIPEASRC |
| [0.275978] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00070008:PIPEACONF |
| [0.275980] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00070008:PIPEACONF |
| [0.275982] HW.GFX.GMA.Connectors.Post_On |
| [0.275983] HW.GFX.GMA.Connectors.FDI.Post_On |
| [0.275984] HW.GFX.GMA.Connectors.FDI.Auto_Training |
| [0.275985] HW.GFX.GMA.Registers.Unset_And_Set_Mask: FDI_TX_CTL_A |
| [0.275986] HW.GFX.GMA.Registers.Read: 0x00044800 <- 0x00060100:FDI_TX_CTL_A |
| [0.275988] HW.GFX.GMA.Registers.Write: 0x80044c00 -> 0x00060100:FDI_TX_CTL_A |
| [0.275990] HW.GFX.GMA.Registers.Read: 0x80044c00 <- 0x00060100:FDI_TX_CTL_A |
| [0.275992] HW.GFX.GMA.Registers.Set_Mask: 0x80000400 .S FDI_RXA_CTL |
| [0.275995] HW.GFX.GMA.Registers.Read: 0x00002850 <- 0x000f000c:FDI_RXA_CTL |
| [0.275997] HW.GFX.GMA.Registers.Write: 0x80002c50 -> 0x000f000c:FDI_RXA_CTL |
| [0.276001] HW.GFX.GMA.Registers.Read: 0x80002c50 <- 0x000f000c:FDI_RXA_CTL |
| [0.276009] HW.GFX.GMA.Registers.Is_Set_Mask: FDI_TX_CTL_A |
| [0.276010] HW.GFX.GMA.Registers.Read: 0x80044c02 <- 0x00060100:FDI_TX_CTL_A |
| [0.276012] HW.GFX.GMA.Registers.Set_Mask: 0x0c000000 .S FDI_RXA_CTL |
| [0.276015] HW.GFX.GMA.Registers.Read: 0x80002c50 <- 0x000f000c:FDI_RXA_CTL |
| [0.276017] HW.GFX.GMA.Registers.Write: 0x8c002c50 -> 0x000f000c:FDI_RXA_CTL |
| [0.276019] HW.GFX.GMA.PCH.Transcoder.On |
| [0.276020] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DPLL_SEL |
| [0.276022] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7000:PCH_DPLL_SEL |
| [0.276024] HW.GFX.GMA.Registers.Write: 0x00000008 -> 0x000c7000:PCH_DPLL_SEL |
| [0.276027] HW.GFX.GMA.Registers.Write: 0x06ef054f -> 0x000e0000:TRANS_HTOTAL_A |
| [0.276030] HW.GFX.GMA.Registers.Write: 0x06ef054f -> 0x000e0004:TRANS_HBLANK_A |
| [0.276033] HW.GFX.GMA.Registers.Write: 0x061f0597 -> 0x000e0008:TRANS_HSYNC_A |
| [0.276036] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x000e000c:TRANS_VTOTAL_A |
| [0.276039] HW.GFX.GMA.Registers.Write: 0x031d02ff -> 0x000e0010:TRANS_VBLANK_A |
| [0.276042] HW.GFX.GMA.Registers.Write: 0x03070302 -> 0x000e0014:TRANS_VSYNC_A |
| [0.276045] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S TRANSA_CHICKEN2 |
| [0.276048] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000f0064:TRANSA_CHICKEN2 |
| [0.276050] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0064:TRANSA_CHICKEN2 |
| [0.276053] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0008:TRANSACONF |
| [0.276056] HW.GFX.GMA.PCH.HDMI.On |
| [0.276057] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_HDMID |
| [0.276059] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1160:PCH_HDMID |
| [0.276061] HW.GFX.GMA.Registers.Write: 0x80000804 -> 0x000e1160:PCH_HDMID |
| [0.276064] Enabled port HDMI3 |
| Error: GNVS or ASLB not set. |
| PCI: 00:02.0 init finished in 13149 usecs |
| POST: 0x75 |
| PCI: 00:14.0 init ... |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 7 usecs |
| POST: 0x75 |
| PCI: 00:16.0 init ... |
| ME: BIOS path: S3 Wake |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 init finished in 11 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 13 usecs |
| POST: 0x75 |
| PCI: 00:1b.0 init ... |
| Azalia: base = f0610000 |
| Azalia: codec_mask = 0c |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: No verb! |
| Azalia: Initializing codec #2 |
| Azalia: codec viddid: 10ec0887 |
| Azalia: No verb! |
| PCI: 00:1b.0 init finished in 2109 usecs |
| POST: 0x75 |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 9 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1c.4 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.4 init finished in 8 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 13 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| Set power on after power failure. |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| NMI sources enabled. |
| PantherPoint PM init |
| rtc_failed = 0x0 |
| Enabling BIOS updates outside of SMM... pch_spi_init |
| PCI: 00:1f.0 init finished in 915 usecs |
| POST: 0x75 |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| CBFS: 'Master Header Locator' located CBFS at [20100:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 16544 |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 16640 |
| CBFS: File @ offset 16640 size 5800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 16640 |
| CBFS: Checking offset 1bec0 |
| CBFS: File @ offset 1bec0 size 396 |
| CBFS: Unmatched 'config' at 1bec0 |
| CBFS: Checking offset 1c2c0 |
| CBFS: File @ offset 1c2c0 size 23f |
| CBFS: Unmatched 'revision' at 1c2c0 |
| CBFS: Checking offset 1c540 |
| CBFS: File @ offset 1c540 size 100 |
| CBFS: Unmatched 'cmos.default' at 1c540 |
| CBFS: Checking offset 1c680 |
| CBFS: File @ offset 1c680 size 5b0 |
| CBFS: Found @ offset 1c680 size 5b0 |
| SATA: Controller in AHCI mode. |
| ABAR: f0614000 |
| PCI: 00:1f.2 init finished in 453 usecs |
| POST: 0x75 |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 0 usecs |
| POST: 0x75 |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 0 usecs |
| POST: 0x75 |
| POST: 0x75 |
| PNP: 002e.1 init ... |
| PNP: 002e.1 init finished in 0 usecs |
| POST: 0x75 |
| PNP: 002e.2 init ... |
| PNP: 002e.2 init finished in 0 usecs |
| POST: 0x75 |
| PNP: 002e.3 init ... |
| PNP: 002e.3 init finished in 0 usecs |
| POST: 0x75 |
| PNP: 002e.4 init ... |
| Unsupported thermal mode 0x0 on TMPIN1 |
| Unsupported thermal mode 0x0 on TMPIN2 |
| Unsupported thermal mode 0x0 on TMPIN3 |
| PNP: 002e.4 init finished in 24 usecs |
| POST: 0x75 |
| PNP: 002e.5 init ... |
| PNP: 002e.5 init finished in 30 usecs |
| POST: 0x75 |
| PNP: 002e.6 init ... |
| PNP: 002e.6 init finished in 0 usecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 0 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 0 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 1 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 002e.0: enabled 0 |
| PNP: 002e.1: enabled 1 |
| PNP: 002e.2: enabled 1 |
| PNP: 002e.3: enabled 1 |
| PNP: 002e.4: enabled 1 |
| PNP: 002e.5: enabled 1 |
| PNP: 002e.6: enabled 1 |
| PNP: 002e.7: enabled 0 |
| PNP: 002e.a: enabled 0 |
| PNP: 0c31.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.4: enabled 0 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 02:00.0: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 12 run 275771 exit 0 |
| POST: 0x76 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 395 exit 0 |
| POST: 0x77 |
| Trying to find the wakeup vector... |
| Looking on 000f0000 for valid checksum |
| Checksum 1 passed |
| Checksum 2 passed all OK |
| RSDP found at 000f0000 |
| RSDT found at 7ff13030 ends at 7ff1306c |
| FADT found at 7ff15a80 |
| FACS found at 7ff13240 |
| OS waking vector is 0009a1d0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 16 exit 0 |
| POST: 0x78 |
| POST: 0xfd |
| |