| diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h |
| index 248b4d5ef1..3abc877a19 100644 |
| --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h |
| +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h |
| @@ -207,10 +207,6 @@ typedef struct { |
| UINT8 RevisionId; ///< The PCI revision id of this memory controller. |
| UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. |
| CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. |
| - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings |
| - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings |
| - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings |
| - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings |
| } CONTROLLER_INFO; |
| |
| typedef struct { |
| @@ -228,6 +224,7 @@ typedef struct { |
| UINT8 ErrorCorrectionType; |
| |
| SiMrcVersion Version; |
| + UINT32 FreqMax; |
| BOOLEAN EccSupport; |
| UINT8 MemoryProfile; |
| UINT32 TotalPhysicalMemorySize; |