| |
| [NOTE ] coreboot-24.02-107-gff2d86351533-dirty Fri Mar 01 18:46:30 UTC 2024 x86_32 bootblock starting (log level: 7)... |
| [DEBUG] CPU: Intel(R) Core(TM) i5-7400 CPU @ 3.00GHz |
| [DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f3 |
| [DEBUG] CPU: AES supported, TXT NOT supported, VT supported |
| [DEBUG] MCH: device id 591f (rev 05) is Kabylake DT |
| [DEBUG] PCH: device id a2c8 (rev 00) is B250 |
| [DEBUG] IGD: device id 5912 (rev 04) is Kaby Lake DT GT2 |
| [INFO ] PMC: Using default GPE route. |
| [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x650000. |
| [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 5 |
| [DEBUG] FMAP: area COREBOOT found @ 650200 (1768960 bytes) |
| [INFO ] CBFS: mcache @0xfef04e00 built for 15 files, used 0x35c of 0x4000 bytes |
| [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xd2f0 in mcache @0xfef04e2c |
| [DEBUG] BS: bootblock times (exec / console): total (unknown) / 82 ms |
| |
| |
| [NOTE ] coreboot-24.02-107-gff2d86351533-dirty Fri Mar 01 18:46:30 UTC 2024 x86_32 romstage starting (log level: 7)... |
| [DEBUG] pm1_sts: 0000 pm1_en: 4000 pm1_cnt: 00000000 |
| [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 |
| [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 |
| [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 |
| [DEBUG] gpe0_sts[3]: 00002040 gpe0_en[3]: 00000000 |
| [DEBUG] TCO_STS: 0000 0000 |
| [DEBUG] GEN_PMCON: e0a40200 00001240 |
| [DEBUG] GBLRST_CAUSE: 00000000 00000000 |
| [DEBUG] prev_sleep_state 0 (S0) |
| [DEBUG] FMAP: area COREBOOT found @ 650200 (1768960 bytes) |
| [INFO ] CBFS: Found 'fspm.bin' @0x67dc0 size 0x63000 in mcache @0xfef05004 |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes) |
| [INFO ] No memory dimm at address A2 |
| [INFO ] No memory dimm at address A6 |
| [DEBUG] SPD @ 0x50 |
| [INFO ] SPD: module type is DDR4 |
| [INFO ] SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb |
| [INFO ] SPD: device width 8 bits, bus width 64 bits |
| [INFO ] SPD: module size is 8192 MB (per channel) |
| [DEBUG] SPD @ 0x52 |
| [INFO ] SPD: module type is DDR4 |
| [INFO ] SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb |
| [INFO ] SPD: device width 8 bits, bus width 64 bits |
| [INFO ] SPD: module size is 8192 MB (per channel) |
| [DEBUG] CBMEM: |
| [DEBUG] IMD: root @ 0x7afff000 254 entries. |
| [DEBUG] IMD: root @ 0x7affec00 62 entries. |
| [DEBUG] External stage cache: |
| [DEBUG] IMD: root @ 0x7b3ff000 254 entries. |
| [DEBUG] IMD: root @ 0x7b3fec00 62 entries. |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes) |
| [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000 |
| [DEBUG] MRC: 'RW_MRC_CACHE' does not need update. |
| [DEBUG] 2 DIMMs found |
| [DEBUG] SMM Memory Map |
| [DEBUG] SMRAM : 0x7b000000 0x800000 |
| [DEBUG] Subregion 0: 0x7b000000 0x200000 |
| [DEBUG] Subregion 1: 0x7b200000 0x200000 |
| [DEBUG] Subregion 2: 0x7b400000 0x400000 |
| [DEBUG] top_of_ram = 0x7b000000 |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/postcar' @0xef300 size 0x5cb8 in mcache @0xfef050a8 |
| [DEBUG] Loading module at 0x7abcf000 with entry 0x7abcf031. filesize: 0x5908 memsize: 0xbc58 |
| [DEBUG] Processing 220 relocs. Offset value of 0x78bcf000 |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 229 ms |
| |
| |
| [NOTE ] coreboot-24.02-107-gff2d86351533-dirty Fri Mar 01 18:46:30 UTC 2024 x86_32 postcar starting (log level: 7)... |
| [DEBUG] Normal boot |
| [DEBUG] FMAP: area COREBOOT found @ 650200 (1768960 bytes) |
| [INFO ] CBFS: Found 'fallback/ramstage' @0x42940 size 0x210aa in mcache @0x7abdd10c |
| [DEBUG] Loading module at 0x7aa7a000 with entry 0x7aa7a000. filesize: 0x442a0 memsize: 0x153850 |
| [DEBUG] Processing 4962 relocs. Offset value of 0x76a7a000 |
| [DEBUG] BS: postcar times (exec / console): total (unknown) / 44 ms |
| |
| |
| [NOTE ] coreboot-24.02-107-gff2d86351533-dirty Fri Mar 01 18:46:30 UTC 2024 x86_32 ramstage starting (log level: 7)... |
| [DEBUG] Normal boot |
| [DEBUG] microcode: sig=0x906e9 pf=0x2 revision=0xf3 |
| [DEBUG] FMAP: area COREBOOT found @ 650200 (1768960 bytes) |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xd400 size 0x35400 in mcache @0x7abdd0ac |
| [DEBUG] Skip microcode update |
| [INFO ] CBFS: Found 'fsps.bin' @0xcae00 size 0x23ff2 in mcache @0x7abdd244 |
| [DEBUG] Detected 4 core, 4 thread CPU. |
| [DEBUG] Setting up SMI for CPU |
| [DEBUG] IED base = 0x7b400000 |
| [DEBUG] IED size = 0x00400000 |
| [INFO ] Will perform SMM setup. |
| [INFO ] CPU: Intel(R) Core(TM) i5-7400 CPU @ 3.00GHz. |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] CPU: APIC: 00 enabled |
| [DEBUG] CPU: APIC: 01 enabled |
| [DEBUG] CPU: APIC: 02 enabled |
| [DEBUG] CPU: APIC: 03 enabled |
| [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 |
| [DEBUG] Processing 16 relocs. Offset value of 0x00030000 |
| [DEBUG] Attempting to start 3 APs |
| [DEBUG] Waiting for 10ms after sending INIT. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [INFO ] LAPIC 0x6 in XAPIC mode. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [INFO ] LAPIC 0x2 in XAPIC mode. |
| [INFO ] AP: slot 3 apic_id 6, MCU rev: 0x000000f3 |
| [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x000000f3 |
| [INFO ] LAPIC 0x4 in XAPIC mode. |
| [INFO ] AP: slot 2 apic_id 4, MCU rev: 0x000000f3 |
| [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0 |
| [DEBUG] Processing 9 relocs. Offset value of 0x00038000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x7b002000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 |
| [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7aa9d112 |
| [DEBUG] Installing permanent SMM handler to 0x7b000000 |
| [DEBUG] HANDLER [0x7b1fd000-0x7b1ff700] |
| |
| [DEBUG] CPU 0 |
| [DEBUG] ss0 [0x7b1fcc00-0x7b1fd000] |
| [DEBUG] stub0 [0x7b1f5000-0x7b1f51a0] |
| |
| [DEBUG] CPU 1 |
| [DEBUG] ss1 [0x7b1fc800-0x7b1fcc00] |
| [DEBUG] stub1 [0x7b1f4c00-0x7b1f4da0] |
| |
| [DEBUG] CPU 2 |
| [DEBUG] ss2 [0x7b1fc400-0x7b1fc800] |
| [DEBUG] stub2 [0x7b1f4800-0x7b1f49a0] |
| |
| [DEBUG] CPU 3 |
| [DEBUG] ss3 [0x7b1fc000-0x7b1fc400] |
| [DEBUG] stub3 [0x7b1f4400-0x7b1f45a0] |
| |
| [DEBUG] stacks [0x7b000000-0x7b002000] |
| [DEBUG] Loading module at 0x7b1fd000 with entry 0x7b1fda0d. filesize: 0x2648 memsize: 0x2700 |
| [DEBUG] Processing 164 relocs. Offset value of 0x7b1fd000 |
| [DEBUG] Loading module at 0x7b1f5000 with entry 0x7b1f5000. filesize: 0x1a0 memsize: 0x1a0 |
| [DEBUG] Processing 9 relocs. Offset value of 0x7b1f5000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x7b002000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000 |
| [DEBUG] SMM Module: placing smm entry code at 7b1f4c00, cpu # 0x1 |
| [DEBUG] SMM Module: placing smm entry code at 7b1f4800, cpu # 0x2 |
| [DEBUG] SMM Module: placing smm entry code at 7b1f4400, cpu # 0x3 |
| [DEBUG] SMM Module: stub loaded at 7b1f5000. Will call 0x7b1fda0d |
| [DEBUG] Clearing SMI status registers |
| [DEBUG] GPE0 STD STS: PME_B0 TCO_SCI |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ed000, cpu = 0 |
| [DEBUG] In relocation handler: CPU 0 |
| [DEBUG] New SMBASE=0x7b1ed000 IEDBASE=0x7b400000 |
| [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec800, cpu = 2 |
| [DEBUG] In relocation handler: CPU 2 |
| [DEBUG] New SMBASE=0x7b1ec800 IEDBASE=0x7b400000 |
| [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec400, cpu = 3 |
| [DEBUG] In relocation handler: CPU 3 |
| [DEBUG] New SMBASE=0x7b1ec400 IEDBASE=0x7b400000 |
| [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ecc00, cpu = 1 |
| [DEBUG] In relocation handler: CPU 1 |
| [DEBUG] New SMBASE=0x7b1ecc00 IEDBASE=0x7b400000 |
| [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 906e9 |
| [DEBUG] CPU: family 06, model 9e, stepping 09 |
| [DEBUG] Clearing out pending MCEs |
| [DEBUG] cpu: energy policy set to 6 |
| [INFO ] Turbo is available but hidden |
| [INFO ] Turbo is available and visible |
| [DEBUG] Skip microcode update |
| [INFO ] CPU #0 initialized |
| [INFO ] Initializing CPU #2 |
| [INFO ] Initializing CPU #1 |
| [DEBUG] CPU: vendor Intel device 906e9 |
| [DEBUG] CPU: family 06, model 9e, stepping 09 |
| [DEBUG] CPU: vendor Intel device 906e9 |
| [DEBUG] CPU: family 06, model 9e, stepping 09 |
| [DEBUG] Clearing out pending MCEs |
| [INFO ] Initializing CPU #3 |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] CPU: vendor Intel device 906e9 |
| [DEBUG] CPU: family 06, model 9e, stepping 09 |
| [DEBUG] Skip microcode update |
| [INFO ] CPU #2 initialized |
| [DEBUG] Clearing out pending MCEs |
| [DEBUG] Clearing out pending MCEs |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] Skip microcode update |
| [INFO ] CPU #1 initialized |
| [DEBUG] Skip microcode update |
| [INFO ] CPU #3 initialized |
| [INFO ] bsp_do_flight_plan done after 427 msecs. |
| [DEBUG] CPU: frequency set to 3500 MHz |
| [DEBUG] Enabling SMIs. |
| [DEBUG] Locking SMM. |
| [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL already locked |
| [DEBUG] IA32_FEATURE_CONTROL already locked |
| [DEBUG] IA32_FEATURE_CONTROL already locked |
| [DEBUG] IA32_FEATURE_CONTROL already locked |
| [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 226 / 379 ms |
| [DEBUG] WEAK: src/soc/intel/skylake/chip.c/mainboard_silicon_init_params called |
| [INFO ] FSPS returned 0 |
| [INFO ] ITSS IRQ Polarities Before: |
| [INFO ] IPC0: 0x00ff4000 |
| [INFO ] IPC1: 0x00000007 |
| [INFO ] IPC2: 0x00000000 |
| [INFO ] IPC3: 0x00000000 |
| [INFO ] ITSS IRQ Polarities After: |
| [INFO ] IPC0: 0x00ff4000 |
| [INFO ] IPC1: 0x00080007 |
| [INFO ] IPC2: 0x00000000 |
| [INFO ] IPC3: 0x00000000 |
| [INFO ] Found PCIe Root Port #5 at PCI: 00:1c.0. |
| [INFO ] Found PCIe Root Port #7 at PCI: 00:1c.6. |
| [INFO ] Found PCIe Root Port #8 at PCI: 00:1c.7. |
| [INFO ] Found PCIe Root Port #21 at PCI: 00:1b.0. |
| [INFO ] Remapping PCIe Root Port #21 from PCI: 00:00:1b.4 to new function number 0. |
| [INFO ] Remapping PCIe Root Port #5 from PCI: 00:00:1c.4 to new function number 0. |
| [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:00:1d.2) which was enabled in devicetree, removing and disabling. |
| [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 286 / 98 ms |
| [INFO ] Enumerating buses... |
| [DEBUG] Root Device scanning... |
| [DEBUG] DOMAIN: 00000000 enabled |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 00000000 scanning... |
| [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 |
| [DEBUG] PCI: 00:00:00.0 [8086/591f] enabled |
| [INFO ] PCI: Static device PCI: 00:00:01.0 not found, disabling it. |
| [DEBUG] PCI: 00:00:02.0 [8086/5912] enabled |
| [DEBUG] PCI: 00:00:14.0 [8086/a2af] enabled |
| [DEBUG] PCI: 00:00:14.2 [8086/a2b1] enabled |
| [DEBUG] PCI: 00:00:16.0 [8086/a2ba] enabled |
| [DEBUG] PCI: 00:00:17.0 [8086/a282] enabled |
| [DEBUG] PCI: 00:00:1b.0 [8086/a2eb] enabled |
| [DEBUG] PCI: 00:00:1c.0 [8086/a294] enabled |
| [DEBUG] PCI: 00:00:1c.6 [8086/a296] enabled |
| [DEBUG] PCI: 00:00:1c.7 [8086/a297] enabled |
| [DEBUG] PCI: 00:00:1f.0 [8086/a2c8] enabled |
| [DEBUG] PCI: 00:00:1f.1 [8086/a2a0] enabled |
| [DEBUG] PCI: 00:00:1f.2 [8086/a2a1] enabled |
| [DEBUG] PCI: 00:00:1f.3 [8086/a2f0] enabled |
| [DEBUG] PCI: 00:00:1f.4 [8086/a2a3] enabled |
| [DEBUG] PCI: 00:00:1f.6 [8086/15b8] enabled |
| [DEBUG] GPIO: 0 enabled |
| [WARN ] PCI: Leftover static devices: |
| [WARN ] PCI: 00:00:01.0 |
| [WARN ] PCI: 00:00:01.1 |
| [WARN ] PCI: 00:00:01.2 |
| [WARN ] PCI: 00:00:04.0 |
| [WARN ] PCI: 00:00:05.0 |
| [WARN ] PCI: 00:00:07.0 |
| [WARN ] PCI: 00:00:08.0 |
| [WARN ] PCI: 00:00:13.0 |
| [WARN ] PCI: 00:00:14.1 |
| [WARN ] PCI: 00:00:14.3 |
| [WARN ] PCI: 00:00:15.0 |
| [WARN ] PCI: 00:00:15.1 |
| [WARN ] PCI: 00:00:15.2 |
| [WARN ] PCI: 00:00:15.3 |
| [WARN ] PCI: 00:00:16.1 |
| [WARN ] PCI: 00:00:16.2 |
| [WARN ] PCI: 00:00:16.3 |
| [WARN ] PCI: 00:00:16.4 |
| [WARN ] PCI: 00:00:19.0 |
| [WARN ] PCI: 00:00:19.1 |
| [WARN ] PCI: 00:00:19.2 |
| [WARN ] PCI: 00:00:1e.0 |
| [WARN ] PCI: 00:00:1e.1 |
| [WARN ] PCI: 00:00:1e.2 |
| [WARN ] PCI: 00:00:1e.3 |
| [WARN ] PCI: 00:00:1e.4 |
| [WARN ] PCI: 00:00:1e.5 |
| [WARN ] PCI: 00:00:1e.6 |
| [WARN ] PCI: 00:00:1f.5 |
| [WARN ] PCI: 00:00:1f.7 |
| [WARN ] PCI: Check your devicetree.cb. |
| [DEBUG] PCI: 00:00:02.0 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs |
| [DEBUG] PCI: 00:00:14.0 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs |
| [DEBUG] PCI: 00:00:1b.0 scanning... |
| [DEBUG] PCI: pci_scan_bus for segment group 00 bus 01 |
| [DEBUG] PCI: 00:01:00.0 [144d/a808] enabled |
| [INFO ] PCIe: Common Clock Configuration already enabled |
| [INFO ] L1 Sub-State supported from root port 27 |
| [INFO ] L1 Sub-State Support = 0xf |
| [INFO ] CommonModeRestoreTime = 0x28 |
| [INFO ] Power On Value = 0x16, Power On Scale = 0x0 |
| [INFO ] ASPM: Enabled L1 |
| [INFO ] PCI: 00:01:00.0: Enabled LTR |
| [INFO ] PCI: 00:01:00.0: Programmed LTR max latencies |
| [INFO ] PCI: 00:00:1b.0: Setting Max_Payload_Size to 128 for devices under this root port |
| [DEBUG] scan_bus: bus PCI: 00:00:1b.0 finished in 59 msecs |
| [DEBUG] PCI: 00:00:1c.0 scanning... |
| [DEBUG] PCI: pci_scan_bus for segment group 00 bus 02 |
| [DEBUG] PCI: 00:02:00.0 [10ec/8168] enabled |
| [INFO ] PCIe: Common Clock Configuration already enabled |
| [INFO ] ASPM: Enabled L1 |
| [INFO ] PCI: 00:02:00.0: Enabled LTR |
| [INFO ] PCI: 00:02:00.0: Programmed LTR max latencies |
| [INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port |
| [DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 40 msecs |
| [DEBUG] PCI: 00:00:1c.6 scanning... |
| [DEBUG] PCI: pci_scan_bus for segment group 00 bus 03 |
| [DEBUG] PCI: 00:03:00.0 [8086/f1a5] enabled |
| [INFO ] PCIe: Common Clock Configuration already enabled |
| [INFO ] L1 Sub-State supported from root port 28 |
| [INFO ] L1 Sub-State Support = 0xf |
| [INFO ] CommonModeRestoreTime = 0x28 |
| [INFO ] Power On Value = 0x16, Power On Scale = 0x0 |
| [INFO ] ASPM: Enabled L1 |
| [INFO ] PCI: 00:03:00.0: Enabled LTR |
| [INFO ] PCI: 00:03:00.0: Programmed LTR max latencies |
| [INFO ] PCI: 00:00:1c.6: Setting Max_Payload_Size to 128 for devices under this root port |
| [DEBUG] scan_bus: bus PCI: 00:00:1c.6 finished in 59 msecs |
| [DEBUG] PCI: 00:00:1c.7 scanning... |
| [DEBUG] PCI: pci_scan_bus for segment group 00 bus 04 |
| [DEBUG] PCI: 00:04:00.0 [10ec/8168] enabled |
| [INFO ] PCIe: Common Clock Configuration already enabled |
| [INFO ] L1 Sub-State supported from root port 28 |
| [INFO ] L1 Sub-State Support = 0xf |
| [INFO ] CommonModeRestoreTime = 0x96 |
| [INFO ] Power On Value = 0xf, Power On Scale = 0x1 |
| [INFO ] ASPM: Enabled L1 |
| [INFO ] PCI: 00:04:00.0: Enabled LTR |
| [INFO ] PCI: 00:04:00.0: Programmed LTR max latencies |
| [INFO ] PCI: 00:00:1c.7: Setting Max_Payload_Size to 128 for devices under this root port |
| [DEBUG] scan_bus: bus PCI: 00:00:1c.7 finished in 59 msecs |
| [DEBUG] PCI: 00:00:1f.0 scanning... |
| [DEBUG] PNP: 002e.0 disabled |
| [DEBUG] PNP: 002e.1 enabled |
| [DEBUG] PNP: 002e.2 disabled |
| [DEBUG] PNP: 002e.3 disabled |
| [DEBUG] PNP: 002e.4 enabled |
| [DEBUG] PNP: 002e.5 enabled |
| [DEBUG] PNP: 002e.6 enabled |
| [DEBUG] PNP: 002e.7 enabled |
| [DEBUG] PNP: 002e.8 enabled |
| [DEBUG] PNP: 002e.a disabled |
| [DEBUG] PNP: 0c31.0 enabled |
| [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 38 msecs |
| [DEBUG] PCI: 00:00:1f.2 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs |
| [DEBUG] PCI: 00:00:1f.3 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs |
| [DEBUG] PCI: 00:00:1f.4 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 0 msecs |
| [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 567 msecs |
| [DEBUG] scan_bus: bus Root Device finished in 585 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 600 ms |
| [INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE' |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes) |
| [INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'. |
| [DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 18 ms |
| [DEBUG] found VGA at PCI: 00:00:02.0 |
| [DEBUG] Setting up VGA for PCI: 00:00:02.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000 |
| [DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000 |
| [DEBUG] SA MMIO resource: DMIBAR -> base = 0xfed18000, size = 0x00001000 |
| [DEBUG] SA MMIO resource: EPBAR -> base = 0xfed19000, size = 0x00001000 |
| [DEBUG] SA MMIO resource: GDXCBAR -> base = 0xfed84000, size = 0x00001000 |
| [DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 |
| [DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000 |
| [DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000 |
| [INFO ] Available memory above 4GB: 14320M |
| [INFO ] Done reading resources. |
| [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === |
| [DEBUG] PCI: 00:00:1b.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:00:1b.0 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:00:1b.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0x3fff] mem |
| [DEBUG] PCI: 00:00:1b.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:00:1b.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:00:1b.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0xff] io |
| [DEBUG] PCI: 00:00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 00:02:00.0 18 * [0x0 - 0xfff] mem |
| [DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:02:00.0 20 * [0x0 - 0x3fff] prefmem |
| [DEBUG] PCI: 00:00:1c.0 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:00:1c.6 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:00:1c.6 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:00:1c.6 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 00:03:00.0 10 * [0x0 - 0x3fff] mem |
| [DEBUG] PCI: 00:00:1c.6 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:00:1c.7 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:04:00.0 10 * [0x0 - 0xff] io |
| [DEBUG] PCI: 00:00:1c.7 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:00:1c.7 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 00:04:00.0 20 * [0x0 - 0x3fff] mem |
| [DEBUG] PCI: 00:04:00.0 18 * [0x4000 - 0x4fff] mem |
| [DEBUG] PCI: 00:00:1c.7 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000080 limit 0000008f io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 000003f8 limit 000003ff io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.4 60 base 00000a30 limit 00000a37 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.4 62 base 00000230 limit 00000237 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.7 60 base 00000000 limit 00000000 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.7 62 base 00000a00 limit 00000a07 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.7 64 base 00000000 limit 00000007 io (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 002e.8 60 base 00000270 limit 00000277 io (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 40 base 00001800 limit 000018ff io (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed) |
| [INFO ] DOMAIN: 00000000: Resource ranges: |
| [INFO ] * Base: 1000, Size: 800, Tag: 100 |
| [INFO ] * Base: 1900, Size: d6a0, Tag: 100 |
| [INFO ] * Base: efc0, Size: 1040, Tag: 100 |
| [DEBUG] PCI: 00:00:1c.0 1c * [0x2000 - 0x2fff] limit: 2fff io |
| [DEBUG] PCI: 00:00:1c.7 1c * [0x3000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:00:02.0 20 * [0x1000 - 0x103f] limit: 103f io |
| [DEBUG] PCI: 00:00:17.0 20 * [0x1040 - 0x105f] limit: 105f io |
| [DEBUG] PCI: 00:00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io |
| [DEBUG] PCI: 00:00:17.0 1c * [0x1068 - 0x106b] limit: 106b io |
| [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff |
| [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base e0000000 limit efffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed10000 limit fed17fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base fed18000 limit fed18fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed19000 limit fed19fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed84000 limit fed84fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed91000 limit fed91fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 000c0000 limit 7affffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 7b000000 limit 7fffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 100000000 limit 47effffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 000a0000 limit 000bffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000c0000 limit 000fffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 48 base fe000000 limit fe00ffff mem (fixed) |
| [INFO ] DOMAIN: 00000000: Resource ranges: |
| [INFO ] * Base: 80000000, Size: 60000000, Tag: 200 |
| [INFO ] * Base: 47f000000, Size: 7b81000000, Tag: 200 |
| [DEBUG] PCI: 00:00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem |
| [DEBUG] PCI: 00:00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem |
| [DEBUG] PCI: 00:00:1b.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem |
| [DEBUG] PCI: 00:00:1c.0 24 * [0x91100000 - 0x911fffff] limit: 911fffff prefmem |
| [DEBUG] PCI: 00:00:1c.0 20 * [0x91200000 - 0x912fffff] limit: 912fffff mem |
| [DEBUG] PCI: 00:00:1c.6 20 * [0x91300000 - 0x913fffff] limit: 913fffff mem |
| [DEBUG] PCI: 00:00:1c.7 20 * [0x91400000 - 0x914fffff] limit: 914fffff mem |
| [DEBUG] PCI: 00:00:1f.6 10 * [0x91500000 - 0x9151ffff] limit: 9151ffff mem |
| [DEBUG] PCI: 00:00:14.0 10 * [0x91520000 - 0x9152ffff] limit: 9152ffff mem |
| [DEBUG] PCI: 00:00:1f.3 20 * [0x91530000 - 0x9153ffff] limit: 9153ffff mem |
| [DEBUG] PCI: 00:00:1f.2 10 * [0x91540000 - 0x91543fff] limit: 91543fff mem |
| [DEBUG] PCI: 00:00:1f.3 10 * [0x91544000 - 0x91547fff] limit: 91547fff mem |
| [DEBUG] PCI: 00:00:17.0 10 * [0x91548000 - 0x91549fff] limit: 91549fff mem |
| [DEBUG] PCI: 00:00:14.2 10 * [0x9154a000 - 0x9154afff] limit: 9154afff mem |
| [DEBUG] PCI: 00:00:16.0 10 * [0x9154b000 - 0x9154bfff] limit: 9154bfff mem |
| [DEBUG] PCI: 00:00:17.0 24 * [0x9154c000 - 0x9154c7ff] limit: 9154c7ff mem |
| [DEBUG] PCI: 00:00:17.0 14 * [0x9154d000 - 0x9154d0ff] limit: 9154d0ff mem |
| [DEBUG] PCI: 00:00:1f.4 10 * [0x9154e000 - 0x9154e0ff] limit: 9154e0ff mem |
| [DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff done |
| [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done |
| [DEBUG] PCI: 00:01:00.0 10 * [0x91000000 - 0x91003fff] limit: 91003fff mem |
| [DEBUG] PCI: 00:02:00.0 10 * [0x2000 - 0x20ff] limit: 20ff io |
| [DEBUG] PCI: 00:02:00.0 20 * [0x91100000 - 0x91103fff] limit: 91103fff prefmem |
| [DEBUG] PCI: 00:02:00.0 18 * [0x91200000 - 0x91200fff] limit: 91200fff mem |
| [DEBUG] PCI: 00:03:00.0 10 * [0x91300000 - 0x91303fff] limit: 91303fff mem |
| [DEBUG] PCI: 00:04:00.0 10 * [0x3000 - 0x30ff] limit: 30ff io |
| [DEBUG] PCI: 00:04:00.0 18 * [0x91404000 - 0x91404fff] limit: 91404fff mem |
| [DEBUG] PCI: 00:04:00.0 20 * [0x91400000 - 0x91403fff] limit: 91403fff mem |
| [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === |
| [DEBUG] PCI: 00:00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64 |
| [DEBUG] PCI: 00:00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64 |
| [DEBUG] PCI: 00:00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io |
| [DEBUG] PCI: 00:00:14.0 10 <- [0x0000000091520000 - 0x000000009152ffff] size 0x00010000 gran 0x10 mem64 |
| [DEBUG] PCI: 00:00:14.2 10 <- [0x000000009154a000 - 0x000000009154afff] size 0x00001000 gran 0x0c mem64 |
| [DEBUG] PCI: 00:00:16.0 10 <- [0x000000009154b000 - 0x000000009154bfff] size 0x00001000 gran 0x0c mem64 |
| [DEBUG] PCI: 00:00:17.0 10 <- [0x0000000091548000 - 0x0000000091549fff] size 0x00002000 gran 0x0d mem |
| [DEBUG] PCI: 00:00:17.0 14 <- [0x000000009154d000 - 0x000000009154d0ff] size 0x00000100 gran 0x08 mem |
| [DEBUG] PCI: 00:00:17.0 18 <- [0x0000000000001060 - 0x0000000000001067] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:00:17.0 1c <- [0x0000000000001068 - 0x000000000000106b] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:00:17.0 20 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:00:17.0 24 <- [0x000000009154c000 - 0x000000009154c7ff] size 0x00000800 gran 0x0b mem |
| [DEBUG] PCI: 00:00:1b.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio |
| [DEBUG] PCI: 00:00:1b.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem |
| [DEBUG] PCI: 00:00:1b.0 20 <- [0x0000000091000000 - 0x00000000910fffff] size 0x00100000 gran 0x14 seg 00 bumem |
| [DEBUG] PCI: 00:01:00.0 10 <- [0x0000000091000000 - 0x0000000091003fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:00:1c.0 1c <- [0x0000000000002000 - 0x0000000000002fff] size 0x00001000 gran 0x0c seg 00 buio |
| [DEBUG] PCI: 00:00:1c.0 24 <- [0x0000000091100000 - 0x00000000911fffff] size 0x00100000 gran 0x14 seg 00 buprefmem |
| [DEBUG] PCI: 00:00:1c.0 20 <- [0x0000000091200000 - 0x00000000912fffff] size 0x00100000 gran 0x14 seg 00 bumem |
| [DEBUG] PCI: 00:02:00.0 10 <- [0x0000000000002000 - 0x00000000000020ff] size 0x00000100 gran 0x08 io |
| [DEBUG] PCI: 00:02:00.0 18 <- [0x0000000091200000 - 0x0000000091200fff] size 0x00001000 gran 0x0c mem64 |
| [DEBUG] PCI: 00:02:00.0 20 <- [0x0000000091100000 - 0x0000000091103fff] size 0x00004000 gran 0x0e prefmem64 |
| [DEBUG] PCI: 00:00:1c.6 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio |
| [DEBUG] PCI: 00:00:1c.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem |
| [DEBUG] PCI: 00:00:1c.6 20 <- [0x0000000091300000 - 0x00000000913fffff] size 0x00100000 gran 0x14 seg 00 bumem |
| [DEBUG] PCI: 00:03:00.0 10 <- [0x0000000091300000 - 0x0000000091303fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:00:1c.7 1c <- [0x0000000000003000 - 0x0000000000003fff] size 0x00001000 gran 0x0c seg 00 buio |
| [DEBUG] PCI: 00:00:1c.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem |
| [DEBUG] PCI: 00:00:1c.7 20 <- [0x0000000091400000 - 0x00000000914fffff] size 0x00100000 gran 0x14 seg 00 bumem |
| [DEBUG] PCI: 00:04:00.0 10 <- [0x0000000000003000 - 0x00000000000030ff] size 0x00000100 gran 0x08 io |
| [DEBUG] PCI: 00:04:00.0 18 <- [0x0000000091404000 - 0x0000000091404fff] size 0x00001000 gran 0x0c mem64 |
| [DEBUG] PCI: 00:04:00.0 20 <- [0x0000000091400000 - 0x0000000091403fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PNP: 002e.1 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.1 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.1 f1 <- [0x0000000000000050 - 0x000000000000004f] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.4 60 <- [0x0000000000000a30 - 0x0000000000000a37] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.4 62 <- [0x0000000000000230 - 0x0000000000000237] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.4 70 <- [0x0000000000000009 - 0x0000000000000009] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.4 f0 <- [0x0000000000000040 - 0x000000000000003f] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.5 71 <- [0x0000000000000002 - 0x0000000000000001] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.5 f0 <- [0x0000000000000048 - 0x0000000000000047] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.6 70 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.6 71 <- [0x0000000000000002 - 0x0000000000000001] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 25 <- [0x0000000000000011 - 0x0000000000000010] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 26 <- [0x0000000000000004 - 0x0000000000000003] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 28 <- [0x0000000000000081 - 0x0000000000000080] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 2a <- [0x000000000000000d - 0x000000000000000c] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 2c <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 60 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 002e.7 62 <- [0x0000000000000a00 - 0x0000000000000a07] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.7 64 <- [0x0000000000000000 - 0x0000000000000007] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.7 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 71 <- [0x0000000000000009 - 0x0000000000000008] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 72 <- [0x0000000000000020 - 0x000000000000001f] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 73 <- [0x0000000000000038 - 0x0000000000000037] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 b8 <- [0x0000000000000011 - 0x0000000000000010] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 bc <- [0x00000000000000c0 - 0x00000000000000bf] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 bd <- [0x0000000000000003 - 0x0000000000000002] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 c0 <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 c1 <- [0x0000000000000004 - 0x0000000000000003] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 c3 <- [0x0000000000000041 - 0x0000000000000040] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 c8 <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 c9 <- [0x0000000000000004 - 0x0000000000000003] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 cb <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 e9 <- [0x0000000000000007 - 0x0000000000000006] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 f0 <- [0x0000000000000010 - 0x000000000000000f] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 f4 <- [0x000000000000000c - 0x000000000000000b] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 f6 <- [0x000000000000000e - 0x000000000000000d] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 f8 <- [0x0000000000000008 - 0x0000000000000007] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 f9 <- [0x0000000000000002 - 0x0000000000000001] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 fc <- [0x000000000000007c - 0x000000000000007b] size 0x00000000 gran 0x00 irq |
| [DEBUG] PNP: 002e.8 60 <- [0x0000000000000270 - 0x0000000000000277] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.8 70 <- [0x0000000000000008 - 0x0000000000000008] size 0x00000001 gran 0x00 irq |
| [DEBUG] LPC: enabling default decode range LPC_IOE_COMA_EN |
| [DEBUG] LPC: Opened IO window LGIR1: base a30 size 8 |
| [DEBUG] LPC: Opened IO window LGIR2: base 230 size 8 |
| [DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64 |
| [DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64 |
| [ERROR] LPC IO decode base 0! |
| [DEBUG] LPC: Opened IO window LGIR3: base a00 size 8 |
| [ERROR] LPC IO decode base 0! |
| [ERROR] LPC: Cannot open IO window: 270 size 8 |
| [ERROR] No more IO windows |
| [DEBUG] PCI: 00:00:1f.2 10 <- [0x0000000091540000 - 0x0000000091543fff] size 0x00004000 gran 0x0e mem |
| [DEBUG] PCI: 00:00:1f.3 10 <- [0x0000000091544000 - 0x0000000091547fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:00:1f.3 20 <- [0x0000000091530000 - 0x000000009153ffff] size 0x00010000 gran 0x10 mem64 |
| [DEBUG] PCI: 00:00:1f.4 10 <- [0x000000009154e000 - 0x000000009154e0ff] size 0x00000100 gran 0x08 mem64 |
| [DEBUG] PCI: 00:00:1f.6 10 <- [0x0000000091500000 - 0x000000009151ffff] size 0x00020000 gran 0x11 mem |
| [INFO ] Done setting resources. |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1886 ms |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00:00.0 subsystem <- 8086/591f |
| [DEBUG] PCI: 00:00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:00:02.0 subsystem <- 8086/5912 |
| [DEBUG] PCI: 00:00:02.0 cmd <- 03 |
| [DEBUG] PCI: 00:00:14.0 subsystem <- 8086/a2af |
| [DEBUG] PCI: 00:00:14.0 cmd <- 02 |
| [DEBUG] PCI: 00:00:14.2 subsystem <- 8086/a2b1 |
| [DEBUG] PCI: 00:00:14.2 cmd <- 02 |
| [DEBUG] PCI: 00:00:16.0 subsystem <- 8086/a2ba |
| [DEBUG] PCI: 00:00:16.0 cmd <- 02 |
| [DEBUG] PCI: 00:00:17.0 subsystem <- 8086/a282 |
| [DEBUG] PCI: 00:00:17.0 cmd <- 03 |
| [DEBUG] PCI: 00:00:1b.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:00:1b.0 subsystem <- 8086/a2eb |
| [DEBUG] PCI: 00:00:1b.0 cmd <- 06 |
| [DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:00:1c.0 subsystem <- 8086/a294 |
| [DEBUG] PCI: 00:00:1c.0 cmd <- 07 |
| [DEBUG] PCI: 00:00:1c.6 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:00:1c.6 subsystem <- 8086/a296 |
| [DEBUG] PCI: 00:00:1c.6 cmd <- 06 |
| [DEBUG] PCI: 00:00:1c.7 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:00:1c.7 subsystem <- 8086/a297 |
| [DEBUG] PCI: 00:00:1c.7 cmd <- 07 |
| [DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/a2c8 |
| [DEBUG] PCI: 00:00:1f.0 cmd <- 07 |
| [DEBUG] PCI: 00:00:1f.2 subsystem <- 8086/a2a1 |
| [DEBUG] PCI: 00:00:1f.2 cmd <- 06 |
| [DEBUG] PCI: 00:00:1f.3 subsystem <- 8086/a2f0 |
| [DEBUG] PCI: 00:00:1f.3 cmd <- 02 |
| [DEBUG] PCI: 00:00:1f.4 subsystem <- 8086/a2a3 |
| [DEBUG] PCI: 00:00:1f.4 cmd <- 03 |
| [DEBUG] PCI: 00:00:1f.6 subsystem <- 8086/15b8 |
| [DEBUG] PCI: 00:00:1f.6 cmd <- 02 |
| [DEBUG] PCI: 00:01:00.0 cmd <- 02 |
| [DEBUG] PCI: 00:02:00.0 cmd <- 03 |
| [DEBUG] PCI: 00:03:00.0 cmd <- 02 |
| [DEBUG] PCI: 00:04:00.0 cmd <- 03 |
| [INFO ] done. |
| [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 1 / 181 ms |
| [DEBUG] ME: Version: 11.8.50.3425 |
| [DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 11 / 4 ms |
| [INFO ] Initializing devices... |
| [DEBUG] PCI: 00:00:00.0 init |
| [INFO ] CPU TDP = 65 Watts |
| [INFO ] CPU PL1 = 65 Watts |
| [INFO ] CPU PL2 = 81 Watts |
| [DEBUG] PCI: 00:00:00.0 init finished in 11 msecs |
| [DEBUG] PCI: 00:00:02.0 init |
| [INFO ] CBFS: Found 'vbt.bin' @0xeee40 size 0x48e in mcache @0x7abdd278 |
| [INFO ] Found a VBT of 6144 bytes |
| [INFO ] GMA: Found VBT in CBFS |
| [INFO ] GMA: Found valid VBT in CBFS |
| [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 |
| [INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000 |
| [DEBUG] PCI: 00:00:02.0 init finished in 254 msecs |
| [DEBUG] PCI: 00:00:14.0 init |
| [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:00:14.2 init |
| [DEBUG] PCI: 00:00:14.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:00:16.0 init |
| [DEBUG] PCI: 00:00:16.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:00:1b.0 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:00:1b.0 init finished in 4 msecs |
| [DEBUG] PCI: 00:00:1c.0 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs |
| [DEBUG] PCI: 00:00:1c.6 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:00:1c.6 init finished in 4 msecs |
| [DEBUG] PCI: 00:00:1c.7 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:00:1c.7 init finished in 4 msecs |
| [DEBUG] PCI: 00:00:1f.0 init |
| [DEBUG] IOAPIC: Initializing IOAPIC at fec00000 |
| [DEBUG] IOAPIC: ID = 0x00 |
| [DEBUG] IOAPIC: 120 interrupts |
| [DEBUG] IOAPIC: Clearing IOAPIC at fec00000 |
| [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| [DEBUG] PCI: 00:00:1f.0 init finished in 23 msecs |
| [DEBUG] PCI: 00:00:1f.2 init |
| [DEBUG] RTC Init |
| [INFO ] Set power on after power failure. |
| [INFO ] PMC: Using default GPE route. |
| [DEBUG] apm_control: Disabling ACPI. |
| [DEBUG] APMC done. |
| [DEBUG] Disabling Deep S3 |
| [DEBUG] Disabling Deep S3 |
| [DEBUG] Disabling Deep S4 |
| [DEBUG] Disabling Deep S4 |
| [DEBUG] Disabling Deep S5 |
| [DEBUG] Disabling Deep S5 |
| [DEBUG] PCI: 00:00:1f.2 init finished in 38 msecs |
| [DEBUG] PCI: 00:00:1f.3 init |
| [DEBUG] azalia_audio: base = 0x91544000 |
| [DEBUG] azalia_audio: codec_mask = 01 |
| [DEBUG] azalia_audio: Initializing codec #0 |
| [DEBUG] azalia_audio: codec viddid: 10ec0662 |
| [DEBUG] azalia_audio: verb_size: 48 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] PCI: 00:00:1f.3 init finished in 32 msecs |
| [DEBUG] PCI: 00:00:1f.4 init |
| [DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs |
| [DEBUG] PCI: 00:00:1f.6 init |
| [DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs |
| [DEBUG] PCI: 00:01:00.0 init |
| [DEBUG] PCI: 00:01:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:02:00.0 init |
| [DEBUG] PCI: 00:02:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:03:00.0 init |
| [DEBUG] PCI: 00:03:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:04:00.0 init |
| [DEBUG] PCI: 00:04:00.0 init finished in 0 msecs |
| [DEBUG] PNP: 002e.1 init |
| [DEBUG] PNP: 002e.1 init finished in 0 msecs |
| [DEBUG] PNP: 002e.4 init |
| [WARN ] Unsupported thermal mode 0x0 on TMPIN2 |
| [DEBUG] PNP: 002e.4 init finished in 5 msecs |
| [DEBUG] PNP: 002e.5 init |
| [DEBUG] PNP: 002e.5 init finished in 0 msecs |
| [DEBUG] PNP: 002e.6 init |
| [DEBUG] PNP: 002e.6 init finished in 0 msecs |
| [DEBUG] PNP: 002e.7 init |
| [DEBUG] PNP: 002e.7 init finished in 0 msecs |
| [DEBUG] PNP: 002e.8 init |
| [DEBUG] PNP: 002e.8 init finished in 0 msecs |
| [INFO ] Devices initialized |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 228 / 375 ms |
| [DEBUG] FMAP: area SMMSTORE found @ 610000 (262144 bytes) |
| [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000 |
| [DEBUG] smm store: 4 # blocks with size 0x10000 |
| [INFO ] SMMSTORE: Setting up SMI handler |
| [INFO ] Found TPM 2.0 SLB9670 TT 2.0 (0x001b) by Infineon (0x15d1) |
| [INFO ] tlcl_send_startup: Startup return code is 0x0 |
| [INFO ] TPM: setup succeeded |
| [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 7 / 40 ms |
| [INFO ] Finalize devices... |
| [DEBUG] PCI: 00:00:02.0 final |
| [DEBUG] PCI: 00:00:16.0 final |
| [DEBUG] PCI: 00:00:17.0 final |
| [DEBUG] PCI: 00:00:1f.2 final |
| [DEBUG] PCI: 00:00:1f.4 final |
| [INFO ] Devices finalized |
| [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 25 ms |
| [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x64e40 size 0x2aaa in mcache @0x7abdd1d8 |
| [WARN ] CBFS: 'fallback/slic' not found. |
| [INFO ] ACPI: Writing ACPI tables at 7a9fb000. |
| [DEBUG] ACPI: * FACS |
| [DEBUG] SCI is IRQ 9, GSI 9 |
| [DEBUG] ACPI: * FACP |
| [DEBUG] ACPI: added table 1/32, length now 44 |
| [DEBUG] PCI space above 4GB MMIO is at 0x47f000000, len = 0x7b81000000 |
| [DEBUG] Found 1 CPU(s) with 4/4 physical/logical core(s) each. |
| [DEBUG] PSS: 3001MHz power 65000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 3000MHz power 65000 control 0x1e00 status 0x1e00 |
| [DEBUG] PSS: 2800MHz power 59250 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 48464 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 38484 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 29344 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1200MHz power 20930 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 800MHz power 13226 control 0x800 status 0x800 |
| [DEBUG] PSS: 3001MHz power 65000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 3000MHz power 65000 control 0x1e00 status 0x1e00 |
| [DEBUG] PSS: 2800MHz power 59250 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 48464 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 38484 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 29344 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1200MHz power 20930 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 800MHz power 13226 control 0x800 status 0x800 |
| [DEBUG] PSS: 3001MHz power 65000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 3000MHz power 65000 control 0x1e00 status 0x1e00 |
| [DEBUG] PSS: 2800MHz power 59250 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 48464 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 38484 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 29344 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1200MHz power 20930 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 800MHz power 13226 control 0x800 status 0x800 |
| [DEBUG] PSS: 3001MHz power 65000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 3000MHz power 65000 control 0x1e00 status 0x1e00 |
| [DEBUG] PSS: 2800MHz power 59250 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 48464 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 38484 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 29344 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1200MHz power 20930 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 800MHz power 13226 control 0x800 status 0x800 |
| [DEBUG] Empty min sleep state array returned |
| [INFO ] Returning default LPI constraint package |
| [INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in |
| [DEBUG] PPI: Pending OS request: 0x0 (0x0) |
| [DEBUG] PPI: OS response: CMD 0xaea7cdbf = 0x0 |
| [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0 |
| [DEBUG] ACPI: * SSDT |
| [DEBUG] ACPI: added table 2/32, length now 52 |
| [DEBUG] ACPI: * MCFG |
| [DEBUG] ACPI: added table 3/32, length now 60 |
| [DEBUG] TPM2 log created at 0x7a9eb000 |
| [DEBUG] ACPI: * TPM2 |
| [DEBUG] ACPI: added table 4/32, length now 68 |
| [DEBUG] ACPI: * LPIT |
| [DEBUG] ACPI: added table 5/32, length now 76 |
| [DEBUG] IOAPIC: 120 interrupts |
| [DEBUG] SCI is IRQ 9, GSI 9 |
| [DEBUG] ACPI: * APIC |
| [DEBUG] ACPI: added table 6/32, length now 84 |
| [DEBUG] ACPI: * SPCR |
| [DEBUG] ACPI: added table 7/32, length now 92 |
| [DEBUG] current = 7a9ff320 |
| [DEBUG] ACPI: * DMAR |
| [DEBUG] ACPI: added table 8/32, length now 100 |
| [DEBUG] acpi_write_dbg2_pci_uart: Device not found |
| [DEBUG] ACPI: * HPET |
| [DEBUG] ACPI: added table 9/32, length now 108 |
| [INFO ] ACPI: done. |
| [DEBUG] ACPI tables: 17392 bytes. |
| [DEBUG] smbios_write_tables: 7a9e3000 |
| [WARN ] EEPROM not found |
| [WARN ] EEPROM not found |
| [WARN ] EEPROM not found |
| [WARN ] EEPROM not found |
| [WARN ] EEPROM not found |
| [WARN ] EEPROM not found |
| [WARN ] EEPROM not found |
| [INFO ] Create SMBIOS type 16 |
| [INFO ] Create SMBIOS type 17 |
| [INFO ] Create SMBIOS type 20 |
| [DEBUG] SMBIOS tables: 1005 bytes. |
| [DEBUG] Writing table forward entry at 0x00000500 |
| [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 953c |
| [DEBUG] Writing coreboot table at 0x7aa1f000 |
| [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| [DEBUG] 1. 0000000000001000-000000000009ffff: RAM |
| [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED |
| [DEBUG] 3. 0000000000100000-000000007a9e2fff: RAM |
| [DEBUG] 4. 000000007a9e3000-000000007aa79fff: CONFIGURATION TABLES |
| [DEBUG] 5. 000000007aa7a000-000000007abcdfff: RAMSTAGE |
| [DEBUG] 6. 000000007abce000-000000007affffff: CONFIGURATION TABLES |
| [DEBUG] 7. 000000007b000000-000000007fffffff: RESERVED |
| [DEBUG] 8. 00000000e0000000-00000000efffffff: RESERVED |
| [DEBUG] 9. 00000000fd000000-00000000fe00ffff: RESERVED |
| [DEBUG] 10. 00000000fed10000-00000000fed19fff: RESERVED |
| [DEBUG] 11. 00000000fed40000-00000000fed44fff: RESERVED |
| [DEBUG] 12. 00000000fed80000-00000000fed84fff: RESERVED |
| [DEBUG] 13. 00000000fed90000-00000000fed91fff: RESERVED |
| [DEBUG] 14. 0000000100000000-000000047effffff: RAM |
| [DEBUG] Wrote coreboot table at: 0x7aa1f000, 0x534 bytes, checksum 17f3 |
| [DEBUG] coreboot table: 1356 bytes. |
| [DEBUG] IMD ROOT 0. 0x7afff000 0x00001000 |
| [DEBUG] IMD SMALL 1. 0x7affe000 0x00001000 |
| [DEBUG] FSP MEMORY 2. 0x7abfe000 0x00400000 |
| [DEBUG] CONSOLE 3. 0x7abde000 0x00020000 |
| [DEBUG] RO MCACHE 4. 0x7abdd000 0x0000035c |
| [DEBUG] TIME STAMP 5. 0x7abdc000 0x00000910 |
| [DEBUG] MEM INFO 6. 0x7abdb000 0x00000f48 |
| [DEBUG] AFTER CAR 7. 0x7abce000 0x0000d000 |
| [DEBUG] RAMSTAGE 8. 0x7aa79000 0x00155000 |
| [DEBUG] REFCODE 9. 0x7aa4b000 0x0002e000 |
| [DEBUG] SMM BACKUP 10. 0x7aa3b000 0x00010000 |
| [DEBUG] IGD OPREGION11. 0x7aa37000 0x00003161 |
| [DEBUG] SMM COMBUFFER12. 0x7aa27000 0x00010000 |
| [DEBUG] COREBOOT 13. 0x7aa1f000 0x00008000 |
| [DEBUG] ACPI 14. 0x7a9fb000 0x00024000 |
| [DEBUG] TPM2 TCGLOG15. 0x7a9eb000 0x00010000 |
| [DEBUG] SMBIOS 16. 0x7a9e3000 0x00008000 |
| [DEBUG] IMD small region: |
| [DEBUG] IMD ROOT 0. 0x7affec00 0x00000400 |
| [DEBUG] FSP RUNTIME 1. 0x7affebe0 0x00000004 |
| [DEBUG] FMAP 2. 0x7affeac0 0x0000010a |
| [DEBUG] POWER STATE 3. 0x7affea80 0x00000040 |
| [DEBUG] FSPM VERSION 4. 0x7affea60 0x00000004 |
| [DEBUG] ROMSTAGE 5. 0x7affea40 0x00000004 |
| [DEBUG] ROMSTG STCK 6. 0x7affe980 0x000000a8 |
| [DEBUG] ACPI GNVS 7. 0x7affe940 0x00000038 |
| [DEBUG] TPM PPI 8. 0x7affe7e0 0x0000015a |
| [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 2 / 683 ms |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6 |
| [DEBUG] 0x000000007b000000 - 0x000000007fffffff size 0x05000000 type 0 |
| [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1 |
| [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0 |
| [DEBUG] 0x0000000100000000 - 0x000000047effffff size 0x37f000000 type 6 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 6/7. |
| [DEBUG] MTRR: WB selected as default type. |
| [DEBUG] MTRR: 0 base 0x000000007b000000 mask 0x0000007fff000000 type 0 |
| [DEBUG] MTRR: 1 base 0x000000007c000000 mask 0x0000007ffc000000 type 0 |
| [DEBUG] MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1 |
| [DEBUG] MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0 |
| [DEBUG] MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0 |
| [DEBUG] MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 |
| [INFO ] LAPIC 0x6 in XAPIC mode. |
| [INFO ] LAPIC 0x2 in XAPIC mode. |
| [INFO ] LAPIC 0x4 in XAPIC mode. |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] apic_id 0x6 setup mtrr for CPU physical address size: 39 bits |
| [DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits |
| [DEBUG] apic_id 0x4 setup mtrr for CPU physical address size: 39 bits |
| [DEBUG] MTRR: TEMPORARY Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6 |
| [DEBUG] 0x000000007b000000 - 0x00000000ff7fffff size 0x84800000 type 0 |
| [DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5 |
| [DEBUG] 0x0000000100000000 - 0x000000047effffff size 0x37f000000 type 6 |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 11/7. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 |
| [DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0 |
| [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0 |
| [DEBUG] MTRR: 3 base 0x00000000ff800000 mask 0x0000007fff800000 type 5 |
| [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 |
| [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007e00000000 type 6 |
| [DEBUG] MTRR: 6 base 0x0000000400000000 mask 0x0000007f80000000 type 6 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [DEBUG] BS: BS_WRITE_TABLES exit times (exec / console): 190 / 320 ms |
| [INFO ] CBFS: Found 'fallback/payload' @0xf5000 size 0x7ae0c in mcache @0x7abdd2ec |
| [DEBUG] Checking segment from ROM address 0xfff4522c |
| [DEBUG] Checking segment from ROM address 0xfff45248 |
| [DEBUG] Loading segment from ROM address 0xfff4522c |
| [DEBUG] code (compression=1) |
| [DEBUG] New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xfff45264 filesize 0x7add4 |
| [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x000000000007add4 |
| [DEBUG] using LZMA |
| [DEBUG] Loading segment from ROM address 0xfff45248 |
| [DEBUG] Entry Point 0x008016a8 |
| [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 53 / 61 ms |
| [DEBUG] Finalizing chipset. |
| [DEBUG] ME: Host Firmware Status Register 1 : 0x90000245 |
| [DEBUG] ME: Host Firmware Status Register 2 : 0x66000106 |
| [DEBUG] ME: Host Firmware Status Register 3 : 0x00000020 |
| [DEBUG] ME: Host Firmware Status Register 4 : 0x00084004 |
| [DEBUG] ME: Host Firmware Status Register 5 : 0x00000000 |
| [DEBUG] ME: Host Firmware Status Register 6 : 0x40000000 |
| [DEBUG] ME: FW Partition Table : OK |
| [DEBUG] ME: Bringup Loader Failure : NO |
| [DEBUG] ME: Firmware Init Complete : YES |
| [DEBUG] ME: Manufacturing Mode : NO |
| [DEBUG] ME: Boot Options Present : NO |
| [DEBUG] ME: Update In Progress : NO |
| [DEBUG] ME: D3 Support : NO |
| [DEBUG] ME: D0i3 Support : YES |
| [DEBUG] ME: Low Power State Enabled : NO |
| [DEBUG] ME: CPU Replaced : NO |
| [DEBUG] ME: CPU Replacement Valid : YES |
| [DEBUG] ME: Current Working State : Normal |
| [DEBUG] ME: Current Operation State : M0 with UMA |
| [DEBUG] ME: Current Operation Mode : Normal |
| [DEBUG] ME: Error Code : No Error |
| [DEBUG] ME: Progress Phase : Host Communication |
| [DEBUG] ME: Power Management Event : Pseudo-global reset |
| [DEBUG] ME: Progress Phase State : Host communication established |
| [DEBUG] ME: Power Down Mitigation : NO |
| [DEBUG] ME: Firmware SKU : Consumer |
| [DEBUG] ME: FPF status : fused |
| [DEBUG] apm_control: Finalizing SMM. |
| [DEBUG] APMC done. |
| [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 5 / 155 ms |
| [DEBUG] mp_park_aps done after 0 msecs. |
| [DEBUG] Jumping to boot code at 0x008016a8(0x7aa1f000) |