| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| mainboard supports Dual Channel Operation. |
| [DEBUG] Reading SPD using i2c block operation. |
| [DEBUG] DDR II Channel 0 Socket 0: x8DDS |
| [DEBUG] DIMM 0 side 0 = 512 MB |
| [DEBUG] DIMM 0 side 1 = 512 MB |
| [DEBUG] DDR II Channel 0 Socket 1: N/A |
| [DEBUG] Reading SPD using i2c block operation. |
| [DEBUG] DDR II Channel 1 Socket 0: x8DDS |
| [DEBUG] DIMM 2 side 0 = 512 MB |
| [DEBUG] DIMM 2 side 1 = 512 MB |
| [DEBUG] DDR II Channel 1 Socket 1: N/A |
| [DEBUG] Memory will be driven at 667MT with CAS=5 clocks |
| [DEBUG] tRAS = 15 cycles |
| [DEBUG] tRP = 5 cycles |
| [DEBUG] tRCD = 5 cycles |
| [DEBUG] tWR = 5 cycles |
| [DEBUG] tRFC = 35 cycles |
| [DEBUG] Refresh: 7.8us |
| [DEBUG] Setting Graphics Frequency... |
| [DEBUG] FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz |
| [DEBUG] Setting Memory Frequency... CLKCFG = 0x00010043, ok (unchanged) |
| [DEBUG] Setting mode of operation for memory channels...Dual Channel Interleaved. |
| [DEBUG] Programming Clock Crossing...MEM=667 FSB=667... ok |
| [DEBUG] Setting RAM size... |
| [DEBUG] C0DRB = 0x20202010 |
| [DEBUG] C1DRB = 0x20202010 |
| [DEBUG] TOLUD = 0x0080 |
| [DEBUG] Setting row attributes... |
| [DEBUG] C0DRA = 0x0033 |
| [DEBUG] C1DRA = 0x0033 |
| [DEBUG] one dimm per channel config.. |
| [DEBUG] Initializing System Memory IO... |
| [DEBUG] Programming Dual Channel RCOMP |
| [DEBUG] Table Index: 18 |
| [DEBUG] Programming DLL Timings... |
| [DEBUG] Enabling System Memory IO... |
| [DEBUG] jedec enable sequence: bank 0 |
| [DEBUG] jedec enable sequence: bank 1 |
| [DEBUG] bankaddr from bank size of rank 0 |
| [DEBUG] jedec enable sequence: bank 4 |
| [DEBUG] jedec enable sequence: bank 5 |
| [DEBUG] bankaddr from bank size of rank 4 |
| [SPEW ] receive_enable_autoconfig() for channel 0 |
| [SPEW ] find_strobes_low() |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x5 |
| [SPEW ] set_receive_enable() medium=0x1, coarse=0x5 |
| [SPEW ] find_strobes_edge() |
| [SPEW ] set_receive_enable() medium=0x1, coarse=0x5 |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x5 |
| [SPEW ] add_quarter_clock() mediumcoarse=17 fine=12 |
| [SPEW ] find_preamble() |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x4 |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x3 |
| [SPEW ] add_quarter_clock() mediumcoarse=0f fine=92 |
| [SPEW ] set_receive_enable() medium=0x1, coarse=0x4 |
| [SPEW ] normalize() |
| [SPEW ] receive_enable_autoconfig() for channel 1 |
| [SPEW ] find_strobes_low() |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x5 |
| [SPEW ] set_receive_enable() medium=0x1, coarse=0x5 |
| [SPEW ] find_strobes_edge() |
| [SPEW ] set_receive_enable() medium=0x1, coarse=0x5 |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x5 |
| [SPEW ] set_receive_enable() medium=0x1, coarse=0x5 |
| [SPEW ] add_quarter_clock() mediumcoarse=15 fine=f2 |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x5 |
| [SPEW ] find_preamble() |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x4 |
| [SPEW ] set_receive_enable() medium=0x3, coarse=0x3 |
| [SPEW ] add_quarter_clock() mediumcoarse=0f fine=72 |
| [SPEW ] normalize() |
| [SPEW ] set_receive_enable() medium=0x0, coarse=0x4 |
| [DEBUG] RAM initialization finished. |
| [DEBUG] Setting up Egress Port RCRB |
| [DEBUG] Loading port arbitration table ...ok |
| [DEBUG] Wait for VC1 negotiation ...ok |
| [DEBUG] Setting up DMI RCRB |
| [DEBUG] Wait for VC1 negotiation ...done.. |
| [DEBUG] Internal graphics: enabled |
| [DEBUG] Waiting for DMI hardware...ok |
| [DEBUG] Enabling PCI Express x16 Link |
| [DEBUG] SLOTSTS: 0048 |
| [DEBUG] PCIe link training ... Detected PCIe device 1002:7149 |
| [DEBUG] PCIe x16 link training succeeded. |
| [DEBUG] PCIe device class: 030000 |
| [DEBUG] PCIe device is VGA. Disabling IGD. |
| [DEBUG] Setting up Root Complex Topology |
| [DEBUG] CBMEM: |
| [DEBUG] IMD: root @ 0x7fbff000 254 entries. |
| [DEBUG] IMD: root @ 0x7fbfec00 62 entries. |
| [DEBUG] External stage cache: |
| [DEBUG] IMD: root @ 0x7ffff000 254 entries. |
| [DEBUG] IMD: root @ 0x7fffec00 62 entries. |
| [DEBUG] SMM Memory Map |
| [DEBUG] SMRAM : 0x7fe00000 0x200000 |
| [DEBUG] Subregion 0: 0x7fe00000 0x100000 |
| [DEBUG] Subregion 1: 0x7ff00000 0x100000 |
| [DEBUG] Subregion 2: 0x80000000 0x0 |
| [DEBUG] MTRR Range: Start=7f400000 End=7f800000 (Size 400000) |
| [DEBUG] MTRR Range: Start=7f800000 End=7fc00000 (Size 400000) |
| [DEBUG] MTRR Range: Start=7fe00000 End=80000000 (Size 200000) |
| [DEBUG] MTRR Range: Start=ffe00000 End=0 (Size 200000) |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/postcar' @0x4ec80 size 0x54a4 in mcache @0xfefc3040 |
| [DEBUG] Loading module at 0x7fbd0000 with entry 0x7fbd0031. filesize: 0x50a8 memsize: 0xa3d8 |
| [DEBUG] Processing 239 relocs. Offset value of 0x7dbd0000 |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 30 ms |
| |
| |
| [NOTE ] coreboot-4.16-536-g662353ac3e Wed Apr 6 23:42:56 UTC 2022 postcar starting (log level: 8)... |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/ramstage' @0x24ec0 size 0x15d2a in mcache @0x7fbdd0dc |
| [DEBUG] Loading module at 0x7fb94000 with entry 0x7fb94000. filesize: 0x2bb10 memsize: 0x3a270 |
| [DEBUG] Processing 3268 relocs. Offset value of 0x7bb94000 |
| [DEBUG] BS: postcar times (exec / console): total (unknown) / 2 ms |
| |
| |
| [NOTE ] coreboot-4.16-536-g662353ac3e Wed Apr 6 23:42:56 UTC 2022 ramstage starting (log level: 8)... |
| [DEBUG] Normal boot |
| [INFO ] Enumerating buses... |
| [SPEW ] Show all devs... Before device enumeration. |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] APIC: 00: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 1 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:02.1: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 1 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1d.1: enabled 1 |
| [SPEW ] PCI: 00:1d.2: enabled 1 |
| [SPEW ] PCI: 00:1d.3: enabled 1 |
| [SPEW ] PCI: 00:1d.7: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 1 |
| [SPEW ] PCI: 00:1e.2: enabled 0 |
| [SPEW ] PCI: 00:1e.3: enabled 0 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.1: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PNP: 00ff.1: enabled 1 |
| [SPEW ] PNP: 00ff.2: enabled 1 |
| [SPEW ] PNP: 164e.2: enabled 1 |
| [SPEW ] PNP: 164e.3: enabled 0 |
| [SPEW ] PNP: 164e.7: enabled 1 |
| [SPEW ] PNP: 164e.19: enabled 1 |
| [SPEW ] PNP: 002e.0: enabled 0 |
| [SPEW ] PNP: 002e.1: enabled 1 |
| [SPEW ] PNP: 002e.2: enabled 0 |
| [SPEW ] PNP: 002e.3: enabled 1 |
| [SPEW ] PNP: 002e.7: enabled 1 |
| [SPEW ] PNP: 002e.a: enabled 0 |
| [SPEW ] I2C: 00:69: enabled 1 |
| [SPEW ] I2C: 00:54: enabled 1 |
| [SPEW ] I2C: 00:55: enabled 1 |
| [SPEW ] I2C: 00:56: enabled 1 |
| [SPEW ] I2C: 00:57: enabled 1 |
| [SPEW ] I2C: 00:5c: enabled 1 |
| [SPEW ] I2C: 00:5d: enabled 1 |
| [SPEW ] I2C: 00:5e: enabled 1 |
| [SPEW ] I2C: 00:5f: enabled 1 |
| [SPEW ] Compare with tree... |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] APIC: 00: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:02.1: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 1 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1d.1: enabled 1 |
| [SPEW ] PCI: 00:1d.2: enabled 1 |
| [SPEW ] PCI: 00:1d.3: enabled 1 |
| [SPEW ] PCI: 00:1d.7: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:1e.2: enabled 0 |
| [SPEW ] PCI: 00:1e.3: enabled 0 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PNP: 00ff.1: enabled 1 |
| [SPEW ] PNP: 00ff.2: enabled 1 |
| [SPEW ] PNP: 164e.2: enabled 1 |
| [SPEW ] PNP: 164e.3: enabled 0 |
| [SPEW ] PNP: 164e.7: enabled 1 |
| [SPEW ] PNP: 164e.19: enabled 1 |
| [SPEW ] PNP: 002e.0: enabled 0 |
| [SPEW ] PNP: 002e.1: enabled 1 |
| [SPEW ] PNP: 002e.2: enabled 0 |
| [SPEW ] PNP: 002e.3: enabled 1 |
| [SPEW ] PNP: 002e.7: enabled 1 |
| [SPEW ] PNP: 002e.a: enabled 0 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] I2C: 00:69: enabled 1 |
| [SPEW ] I2C: 00:54: enabled 1 |
| [SPEW ] I2C: 00:55: enabled 1 |
| [SPEW ] I2C: 00:56: enabled 1 |
| [SPEW ] I2C: 00:57: enabled 1 |
| [SPEW ] I2C: 00:5c: enabled 1 |
| [SPEW ] I2C: 00:5d: enabled 1 |
| [SPEW ] I2C: 00:5e: enabled 1 |
| [SPEW ] I2C: 00:5f: enabled 1 |
| [SPEW ] PCI: 00:1f.1: enabled 1 |
| [DEBUG] Root Device scanning... |
| [SPEW ] scan_static_bus for Root Device |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 0000 enabled |
| [DEBUG] DOMAIN: 0000 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 00 |
| [SPEW ] PCI: 00:00.0 [8086/0000] ops |
| [DEBUG] PCI: 00:00.0 [8086/27a0] enabled |
| [DEBUG] PCI: 00:01.0 subordinate bus PCI Express |
| [DEBUG] PCI: 00:01.0 [8086/27a1] enabled |
| [INFO ] PCI: Static device PCI: 00:02.0 not found, disabling it. |
| [INFO ] PCI: Static device PCI: 00:02.1 not found, disabling it. |
| [SPEW ] PCI: 00:1b.0 [8086/27d8] ops |
| [DEBUG] PCI: 00:1b.0 [8086/27d8] enabled |
| [SPEW ] PCI: 00:1c.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.0 [8086/27d0] enabled |
| [SPEW ] PCI: 00:1c.1 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.1 [8086/27d2] enabled |
| [SPEW ] PCI: 00:1c.2 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.2 [8086/27d4] enabled |
| [SPEW ] PCI: 00:1c.3 [8086/0000] bus ops |
| [SPEW ] ICH: RPFN 0x00543210 -> 0x00543210 |
| [DEBUG] PCI: 00:1c.3 [8086/27d6] enabled |
| [DEBUG] PCI: 00:1c.4: Disabling device |
| [DEBUG] PCI: 00:1c.5: Disabling device |
| [SPEW ] PCI: 00:1d.0 [8086/27c8] ops |
| [DEBUG] PCI: 00:1d.0 [8086/27c8] enabled |
| [SPEW ] PCI: 00:1d.1 [8086/27c9] ops |
| [DEBUG] PCI: 00:1d.1 [8086/27c9] enabled |
| [SPEW ] PCI: 00:1d.2 [8086/27ca] ops |
| [DEBUG] PCI: 00:1d.2 [8086/27ca] enabled |
| [SPEW ] PCI: 00:1d.3 [8086/27cb] ops |
| [DEBUG] PCI: 00:1d.3 [8086/27cb] enabled |
| [SPEW ] PCI: 00:1d.7 [8086/27cc] ops |
| [DEBUG] PCI: 00:1d.7 [8086/27cc] enabled |
| [SPEW ] PCI: 00:1e.0 [8086/2448] bus ops |
| [DEBUG] PCI: 00:1e.0 [8086/2448] enabled |
| [DEBUG] PCI: 00:1e.2: Disabling device |
| [SPEW ] PCI: 00:1e.2 [8086/27de] ops |
| [DEBUG] PCI: 00:1e.2: Disabling device |
| [DEBUG] PCI: 00:1e.2 [8086/27de] disabled |
| [DEBUG] PCI: 00:1e.3: Disabling device |
| [SPEW ] PCI: 00:1e.3 [8086/27dd] ops |
| [DEBUG] PCI: 00:1e.3: Disabling device |
| [DEBUG] PCI: 00:1e.3 [8086/27dd] disabled |
| [SPEW ] PCI: 00:1f.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1f.0 [8086/27b9] enabled |
| [SPEW ] PCI: 00:1f.1 [8086/27df] ops |
| [DEBUG] PCI: 00:1f.1 [8086/27df] enabled |
| [DEBUG] Set SATA mode early |
| [SPEW ] PCI: 00:1f.2 [8086/0000] ops |
| [DEBUG] Set SATA mode early |
| [DEBUG] PCI: 00:1f.2 [8086/27c5] enabled |
| [SPEW ] PCI: 00:1f.3 [8086/27da] bus ops |
| [DEBUG] PCI: 00:1f.3 [8086/27da] enabled |
| [WARN ] PCI: Leftover static devices: |
| [WARN ] PCI: 00:02.0 |
| [WARN ] PCI: 00:02.1 |
| [WARN ] PCI: 00:1c.4 |
| [WARN ] PCI: 00:1c.5 |
| [WARN ] PCI: Check your devicetree.cb. |
| [DEBUG] PCI: 00:01.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:01.0 |
| [DEBUG] PCI: 00:01.0: No LTR support |
| [DEBUG] PCI: pci_scan_bus for bus 01 |
| [DEBUG] PCI: 01:00.0 [1002/7149] enabled |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 01:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:01.0 finished in 1 msecs |
| [DEBUG] PCI: 00:1c.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.0 |
| [DEBUG] PCI: pci_scan_bus for bus 02 |
| [DEBUG] PCI: 02:00.0 [8086/109a] enabled |
| [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.1 |
| [DEBUG] PCI: pci_scan_bus for bus 03 |
| [DEBUG] PCI: 03:00.0 [8086/4227] enabled |
| [DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.2 |
| [DEBUG] PCI: pci_scan_bus for bus 04 |
| [DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.3 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.3 |
| [DEBUG] PCI: pci_scan_bus for bus 05 |
| [DEBUG] scan_bus: bus PCI: 00:1c.3 finished in 0 msecs |
| [DEBUG] PCI: 00:1e.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1e.0 |
| [DEBUG] PCI: pci_scan_bus for bus 06 |
| [SPEW ] PCI: 06:00.0 [104c/ac56] ops |
| [DEBUG] PCI: 06:00.0 [104c/ac56] enabled |
| [DEBUG] scan_bus: bus PCI: 00:1e.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 scanning... |
| [SPEW ] scan_static_bus for PCI: 00:1f.0 |
| [INFO ] PMH7: ID 03 Revision 02 |
| [DEBUG] PNP: 00ff.1 enabled |
| [SPEW ] Clearing EC output queue... |
| [SPEW ] EC output queue has been cleared. |
| [SPEW ] recv_ec_data: 0x37 |
| [SPEW ] recv_ec_data: 0x39 |
| [SPEW ] recv_ec_data: 0x48 |
| [SPEW ] recv_ec_data: 0x54 |
| [SPEW ] recv_ec_data: 0x35 |
| [SPEW ] recv_ec_data: 0x30 |
| [SPEW ] recv_ec_data: 0x57 |
| [SPEW ] recv_ec_data: 0x57 |
| [SPEW ] recv_ec_data: 0x04 |
| [SPEW ] recv_ec_data: 0x03 |
| [SPEW ] recv_ec_data: 0x70 |
| [SPEW ] recv_ec_data: 0x10 |
| [INFO ] H8: EC Firmware ID 79HT50WW-3.4, Version 7.01A |
| [DEBUG] No CMOS option 'usb_always_on'. |
| [SPEW ] recv_ec_data: 0x00 |
| [SPEW ] recv_ec_data: 0x20 |
| [SPEW ] recv_ec_data: 0x10 |
| [INFO ] H8: BDC not installed |
| [SPEW ] recv_ec_data: 0x20 |
| [INFO ] H8: WWAN detection not implemented. Assuming WWAN installed |
| [SPEW ] recv_ec_data: 0x20 |
| [DEBUG] No CMOS option 'fn_ctrl_swap'. |
| [SPEW ] recv_ec_data: 0x00 |
| [SPEW ] recv_ec_data: 0xa6 |
| [SPEW ] recv_ec_data: 0xa6 |
| [SPEW ] recv_ec_data: 0x60 |
| [DEBUG] PNP: 00ff.2 enabled |
| [DEBUG] PNP: 164e.2 enabled |
| [DEBUG] PNP: 164e.3 disabled |
| [DEBUG] PNP: 164e.7 enabled |
| [DEBUG] PNP: 164e.19 enabled |
| [DEBUG] PNP: 002e.0 disabled |
| [DEBUG] PNP: 002e.1 enabled |
| [DEBUG] PNP: 002e.2 disabled |
| [DEBUG] PNP: 002e.3 enabled |
| [DEBUG] PNP: 002e.7 enabled |
| [DEBUG] PNP: 002e.a disabled |
| [SPEW ] scan_static_bus for PCI: 00:1f.0 done |
| [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 17 msecs |
| [DEBUG] PCI: 00:1f.3 scanning... |
| [SPEW ] scan_generic_bus for PCI: 00:1f.3 |
| [DEBUG] I2C: 01:69 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->scan_generic_bus for PCI: 00:1f.3 done |
| [DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 2 msecs |
| [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 41 msecs |
| [SPEW ] scan_static_bus for Root Device done |
| [DEBUG] scan_bus: bus Root Device finished in 42 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 51 ms |
| [DEBUG] found VGA at PCI: 01:00.0 |
| [DEBUG] Setting up VGA for PCI: 01:00.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [SPEW ] Root Device read_resources bus 0 link: 0 |
| [SPEW ] CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| [SPEW ] CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| [DEBUG] pci_tolm: 0xffffffff |
| [SPEW ] Top of Low Used DRAM: 0x80000000 |
| [DEBUG] TSEG decoded, subtracting 2M |
| [DEBUG] Unused RAM between cbmem_top and TOM: 0x800K |
| [INFO ] Available memory: 2093056K (2044M) |
| [SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 |
| [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| [SPEW ] PCI: 00:01.0 read_resources bus 1 link: 0 |
| [SPEW ] PCI: 00:01.0 read_resources bus 1 link: 0 done |
| [SPEW ] PCI: 00:1c.0 read_resources bus 2 link: 0 |
| [SPEW ] PCI: 00:1c.0 read_resources bus 2 link: 0 done |
| [SPEW ] PCI: 00:1c.1 read_resources bus 3 link: 0 |
| [SPEW ] PCI: 00:1c.1 read_resources bus 3 link: 0 done |
| [SPEW ] PCI: 00:1c.2 read_resources bus 4 link: 0 |
| [SPEW ] PCI: 00:1c.2 read_resources bus 4 link: 0 done |
| [SPEW ] PCI: 00:1c.3 read_resources bus 5 link: 0 |
| [SPEW ] PCI: 00:1c.3 read_resources bus 5 link: 0 done |
| [SPEW ] PCI: 00:1e.0 read_resources bus 6 link: 0 |
| [SPEW ] PCI: 00:1e.0 read_resources bus 6 link: 0 done |
| [SPEW ] PCI: 00:1f.0 read_resources bus 0 link: 0 |
| [ERROR] PNP: 00ff.1 missing read_resources |
| [ERROR] PNP: 00ff.2 missing read_resources |
| [SPEW ] PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| [SPEW ] PCI: 00:1f.3 read_resources bus 1 link: 0 |
| [SPEW ] PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| [SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 done |
| [SPEW ] Root Device read_resources bus 0 link: 0 done |
| [INFO ] Done reading resources. |
| [SPEW ] Show resources in subtree (Root Device)...After reading. |
| [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 |
| [DEBUG] CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| [DEBUG] APIC: 00 |
| [DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100 |
| [SPEW ] DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| [SPEW ] DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| [SPEW ] DOMAIN: 0000 resource base 7fe00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| [SPEW ] DOMAIN: 0000 resource base 7fc00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| [SPEW ] DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8 |
| [SPEW ] DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9 |
| [DEBUG] PCI: 00:00.0 |
| [SPEW ] PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 48 |
| [DEBUG] PCI: 00:01.0 child on link 0 PCI: 01:00.0 |
| [SPEW ] PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 01:00.0 |
| [SPEW ] PCI: 01:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10 |
| [SPEW ] PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 |
| [SPEW ] PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18 |
| [SPEW ] PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 |
| [DEBUG] PCI: 00:1b.0 |
| [SPEW ] PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 02:00.0 |
| [SPEW ] PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| [SPEW ] PCI: 02:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| [DEBUG] PCI: 00:1c.1 child on link 0 PCI: 03:00.0 |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 03:00.0 |
| [SPEW ] PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1c.2 |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 00:1c.3 |
| [SPEW ] PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 00:1d.0 |
| [SPEW ] PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.1 |
| [SPEW ] PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.2 |
| [SPEW ] PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.3 |
| [SPEW ] PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.7 |
| [SPEW ] PCI: 00:1d.7 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1e.0 child on link 0 PCI: 06:00.0 |
| [SPEW ] PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 06:00.0 |
| [SPEW ] PCI: 06:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| [SPEW ] PCI: 06:00.0 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 2c |
| [SPEW ] PCI: 06:00.0 resource base 0 size 1000 align 2 gran 2 limit ffff flags 100 index 34 |
| [SPEW ] PCI: 06:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c |
| [SPEW ] PCI: 06:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 |
| [DEBUG] PCI: 00:1e.2 |
| [DEBUG] PCI: 00:1e.3 |
| [DEBUG] PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| [SPEW ] PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| [SPEW ] PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| [SPEW ] PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| [SPEW ] PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| [SPEW ] PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| [SPEW ] PCI: 00:1f.0 resource base 1680 size 1c align 0 gran 0 limit 0 flags c0040100 index 10000400 |
| [DEBUG] PNP: 00ff.1 |
| [SPEW ] PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| [DEBUG] PNP: 00ff.2 |
| [SPEW ] PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| [SPEW ] PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| [SPEW ] PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| [SPEW ] PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| [DEBUG] PNP: 164e.2 |
| [SPEW ] PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [SPEW ] PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| [SPEW ] PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 |
| [DEBUG] PNP: 164e.3 |
| [SPEW ] PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 164e.7 |
| [SPEW ] PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 |
| [SPEW ] PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 164e.19 |
| [SPEW ] PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 |
| [SPEW ] PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 002e.0 |
| [DEBUG] PNP: 002e.1 |
| [SPEW ] PNP: 002e.1 resource base 3bc size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| [SPEW ] PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| [DEBUG] PNP: 002e.2 |
| [SPEW ] PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| [DEBUG] PNP: 002e.3 |
| [SPEW ] PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| [DEBUG] PNP: 002e.7 |
| [SPEW ] PNP: 002e.7 resource base 1620 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 |
| [SPEW ] PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 002e.a |
| [DEBUG] PCI: 00:1f.1 |
| [SPEW ] PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| [SPEW ] PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| [SPEW ] PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| [SPEW ] PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| [SPEW ] PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1f.2 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24 |
| [DEBUG] PCI: 00:1f.3 child on link 0 I2C: 01:69 |
| [SPEW ] PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| [DEBUG] I2C: 01:69 |
| [DEBUG] I2C: 01:54 |
| [DEBUG] I2C: 01:55 |
| [DEBUG] I2C: 01:56 |
| [DEBUG] I2C: 01:57 |
| [DEBUG] I2C: 01:5c |
| [DEBUG] I2C: 01:5d |
| [DEBUG] I2C: 01:5e |
| [DEBUG] I2C: 01:5f |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| [DEBUG] PCI: 00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 01:00.0 14 * [0x0 - 0xff] io |
| [DEBUG] PCI: 00:01.0 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem |
| [DEBUG] PCI: 01:00.0 18 * [0x20000 - 0x2ffff] mem |
| [DEBUG] PCI: 00:01.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x7ffffff] prefmem |
| [DEBUG] PCI: 00:01.0 prefmem: size: 8000000 align: 27 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 02:00.0 18 * [0x0 - 0x1f] io |
| [DEBUG] PCI: 00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 02:00.0 10 * [0x0 - 0x1ffff] mem |
| [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 03:00.0 10 * [0x0 - 0xfff] mem |
| [DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 06:00.0 2c * [0x0 - 0xfff] io |
| [DEBUG] PCI: 06:00.0 34 * [0x1000 - 0x1fff] io |
| [DEBUG] PCI: 00:1e.0 io: size: 2000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1e.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 06:00.0 24 * [0x0 - 0x1ffffff] mem |
| [DEBUG] PCI: 06:00.0 10 * [0x2000000 - 0x2000fff] mem |
| [DEBUG] PCI: 00:1e.0 mem: size: 2100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 06:00.0 1c * [0x0 - 0x1ffffff] prefmem |
| [DEBUG] PCI: 00:1e.0 prefmem: size: 2000000 align: 20 gran: 20 limit: ffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000400 base 00001680 limit 0000169b io (fixed) |
| [DEBUG] update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) |
| [DEBUG] update_constraints: PNP: 164e.2 60 base 000002f8 limit 000002ff io (fixed) |
| [DEBUG] update_constraints: PNP: 164e.3 60 base 000003f8 limit 000003ff io (fixed) |
| [DEBUG] update_constraints: PNP: 164e.7 60 base 00001680 limit 0000168f io (fixed) |
| [DEBUG] update_constraints: PNP: 164e.19 60 base 0000164c limit 0000164d io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.1 60 base 000003bc limit 000003c3 io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.2 60 base 000002f8 limit 000002ff io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.3 60 base 000003f8 limit 000003ff io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.7 60 base 00001620 limit 0000162f io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 1000, Size: 5e0, Tag: 100 |
| [INFO ] * Base: 15f0, Size: 10, Tag: 100 |
| [INFO ] * Base: 167c, Size: 4, Tag: 100 |
| [INFO ] * Base: 169c, Size: e964, Tag: 100 |
| [DEBUG] PCI: 00:1e.0 1c * [0x2000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:01.0 1c * [0x4000 - 0x4fff] limit: 4fff io |
| [DEBUG] PCI: 00:1c.0 1c * [0x5000 - 0x5fff] limit: 5fff io |
| [DEBUG] PCI: 00:1d.0 20 * [0x1000 - 0x101f] limit: 101f io |
| [DEBUG] PCI: 00:1d.1 20 * [0x1020 - 0x103f] limit: 103f io |
| [DEBUG] PCI: 00:1d.2 20 * [0x1040 - 0x105f] limit: 105f io |
| [DEBUG] PCI: 00:1d.3 20 * [0x1060 - 0x107f] limit: 107f io |
| [DEBUG] PCI: 00:1f.2 20 * [0x1080 - 0x109f] limit: 109f io |
| [DEBUG] PCI: 00:1f.1 20 * [0x10a0 - 0x10af] limit: 10af io |
| [DEBUG] PCI: 00:1f.1 10 * [0x10b0 - 0x10b7] limit: 10b7 io |
| [DEBUG] PCI: 00:1f.1 18 * [0x10b8 - 0x10bf] limit: 10bf io |
| [DEBUG] PCI: 00:1f.2 10 * [0x10c0 - 0x10c7] limit: 10c7 io |
| [DEBUG] PCI: 00:1f.2 18 * [0x10c8 - 0x10cf] limit: 10cf io |
| [DEBUG] PCI: 00:1f.1 14 * [0x10d0 - 0x10d3] limit: 10d3 io |
| [DEBUG] PCI: 00:1f.1 1c * [0x10d4 - 0x10d7] limit: 10d7 io |
| [DEBUG] PCI: 00:1f.2 14 * [0x10d8 - 0x10db] limit: 10db io |
| [DEBUG] PCI: 00:1f.2 1c * [0x10dc - 0x10df] limit: 10df io |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| [DEBUG] update_constraints: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] update_constraints: DOMAIN: 0000 04 base 00100000 limit 7fffffff mem (fixed) |
| [DEBUG] update_constraints: DOMAIN: 0000 06 base 7fe00000 limit 7fffffff mem (fixed) |
| [DEBUG] update_constraints: DOMAIN: 0000 07 base 7fc00000 limit 7fdfffff mem (fixed) |
| [DEBUG] update_constraints: DOMAIN: 0000 08 base 000a0000 limit 000bffff mem (fixed) |
| [DEBUG] update_constraints: DOMAIN: 0000 09 base 000c0000 limit 000fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 48 base f0000000 limit f3ffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 80000000, Size: 70000000, Tag: 200 |
| [INFO ] * Base: f4000000, Size: ac00000, Tag: 200 |
| [INFO ] * Base: fec01000, Size: bff000, Tag: 200 |
| [INFO ] * Base: 100000000, Size: f00000000, Tag: 100200 |
| [DEBUG] PCI: 00:01.0 24 * [0x80000000 - 0x87ffffff] limit: 87ffffff prefmem |
| [DEBUG] PCI: 00:1e.0 20 * [0x88000000 - 0x8a0fffff] limit: 8a0fffff mem |
| [DEBUG] PCI: 00:1e.0 24 * [0x8a100000 - 0x8c0fffff] limit: 8c0fffff prefmem |
| [DEBUG] PCI: 00:01.0 20 * [0x8c100000 - 0x8c1fffff] limit: 8c1fffff mem |
| [DEBUG] PCI: 00:1c.0 20 * [0x8c200000 - 0x8c2fffff] limit: 8c2fffff mem |
| [DEBUG] PCI: 00:1c.1 20 * [0x8c300000 - 0x8c3fffff] limit: 8c3fffff mem |
| [DEBUG] PCI: 00:1b.0 10 * [0x8c400000 - 0x8c403fff] limit: 8c403fff mem |
| [DEBUG] PCI: 00:1d.7 10 * [0x8c404000 - 0x8c4043ff] limit: 8c4043ff mem |
| [DEBUG] PCI: 00:1f.2 24 * [0x8c405000 - 0x8c4053ff] limit: 8c4053ff mem |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| [DEBUG] PCI: 00:01.0 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff |
| [INFO ] PCI: 00:01.0: Resource ranges: |
| [INFO ] * Base: 4000, Size: 1000, Tag: 100 |
| [DEBUG] PCI: 01:00.0 14 * [0x4000 - 0x40ff] limit: 40ff io |
| [DEBUG] PCI: 00:01.0 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff done |
| [DEBUG] PCI: 00:01.0 prefmem: base: 80000000 size: 8000000 align: 27 gran: 20 limit: 87ffffff |
| [INFO ] PCI: 00:01.0: Resource ranges: |
| [INFO ] * Base: 80000000, Size: 8000000, Tag: 1200 |
| [DEBUG] PCI: 01:00.0 10 * [0x80000000 - 0x87ffffff] limit: 87ffffff prefmem |
| [DEBUG] PCI: 00:01.0 prefmem: base: 80000000 size: 8000000 align: 27 gran: 20 limit: 87ffffff done |
| [DEBUG] PCI: 00:01.0 mem: base: 8c100000 size: 100000 align: 20 gran: 20 limit: 8c1fffff |
| [INFO ] PCI: 00:01.0: Resource ranges: |
| [INFO ] * Base: 8c100000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 01:00.0 30 * [0x8c100000 - 0x8c11ffff] limit: 8c11ffff mem |
| [DEBUG] PCI: 01:00.0 18 * [0x8c120000 - 0x8c12ffff] limit: 8c12ffff mem |
| [DEBUG] PCI: 00:01.0 mem: base: 8c100000 size: 100000 align: 20 gran: 20 limit: 8c1fffff done |
| [DEBUG] PCI: 00:1c.0 io: base: 5000 size: 1000 align: 12 gran: 12 limit: 5fff |
| [INFO ] PCI: 00:1c.0: Resource ranges: |
| [INFO ] * Base: 5000, Size: 1000, Tag: 100 |
| [DEBUG] PCI: 02:00.0 18 * [0x5000 - 0x501f] limit: 501f io |
| [DEBUG] PCI: 00:1c.0 io: base: 5000 size: 1000 align: 12 gran: 12 limit: 5fff done |
| [DEBUG] PCI: 00:1c.0 mem: base: 8c200000 size: 100000 align: 20 gran: 20 limit: 8c2fffff |
| [INFO ] PCI: 00:1c.0: Resource ranges: |
| [INFO ] * Base: 8c200000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 02:00.0 10 * [0x8c200000 - 0x8c21ffff] limit: 8c21ffff mem |
| [DEBUG] PCI: 00:1c.0 mem: base: 8c200000 size: 100000 align: 20 gran: 20 limit: 8c2fffff done |
| [DEBUG] PCI: 00:1c.1 mem: base: 8c300000 size: 100000 align: 20 gran: 20 limit: 8c3fffff |
| [INFO ] PCI: 00:1c.1: Resource ranges: |
| [INFO ] * Base: 8c300000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 03:00.0 10 * [0x8c300000 - 0x8c300fff] limit: 8c300fff mem |
| [DEBUG] PCI: 00:1c.1 mem: base: 8c300000 size: 100000 align: 20 gran: 20 limit: 8c3fffff done |
| [DEBUG] PCI: 00:1e.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff |
| [INFO ] PCI: 00:1e.0: Resource ranges: |
| [INFO ] * Base: 2000, Size: 2000, Tag: 100 |
| [DEBUG] PCI: 06:00.0 2c * [0x2000 - 0x2fff] limit: 2fff io |
| [DEBUG] PCI: 06:00.0 34 * [0x3000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:1e.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done |
| [DEBUG] PCI: 00:1e.0 prefmem: base: 8a100000 size: 2000000 align: 20 gran: 20 limit: 8c0fffff |
| [INFO ] PCI: 00:1e.0: Resource ranges: |
| [INFO ] * Base: 8a100000, Size: 2000000, Tag: 1200 |
| [DEBUG] PCI: 06:00.0 1c * [0x8a100000 - 0x8c0fffff] limit: 8c0fffff prefmem |
| [DEBUG] PCI: 00:1e.0 prefmem: base: 8a100000 size: 2000000 align: 20 gran: 20 limit: 8c0fffff done |
| [DEBUG] PCI: 00:1e.0 mem: base: 88000000 size: 2100000 align: 20 gran: 20 limit: 8a0fffff |
| [INFO ] PCI: 00:1e.0: Resource ranges: |
| [INFO ] * Base: 88000000, Size: 2100000, Tag: 200 |
| [DEBUG] PCI: 06:00.0 24 * [0x88000000 - 0x89ffffff] limit: 89ffffff mem |
| [DEBUG] PCI: 06:00.0 10 * [0x8a000000 - 0x8a000fff] limit: 8a000fff mem |
| [DEBUG] PCI: 00:1e.0 mem: base: 88000000 size: 2100000 align: 20 gran: 20 limit: 8a0fffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| [SPEW ] Root Device assign_resources, bus 0 link: 0 |
| [DEBUG] DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 04 <- [0x0000100000 - 0x007fffffff] size 0x7ff00000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 06 <- [0x007fe00000 - 0x007fffffff] size 0x00200000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 07 <- [0x007fc00000 - 0x007fdfffff] size 0x00200000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 08 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 09 <- [0x00000c0000 - 0x00000fffff] size 0x00040000 gran 0x00 mem |
| [SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| [DEBUG] PCI: 00:01.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io |
| [DEBUG] PCI: 00:01.0 24 <- [0x0080000000 - 0x0087ffffff] size 0x08000000 gran 0x14 bus 01 prefmem |
| [DEBUG] PCI: 00:01.0 20 <- [0x008c100000 - 0x008c1fffff] size 0x00100000 gran 0x14 bus 01 mem |
| [SPEW ] PCI: 00:01.0 assign_resources, bus 1 link: 0 |
| [DEBUG] PCI: 01:00.0 10 <- [0x0080000000 - 0x0087ffffff] size 0x08000000 gran 0x1b prefmem |
| [DEBUG] PCI: 01:00.0 14 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io |
| [DEBUG] PCI: 01:00.0 18 <- [0x008c120000 - 0x008c12ffff] size 0x00010000 gran 0x10 mem |
| [DEBUG] PCI: 01:00.0 30 <- [0x008c100000 - 0x008c11ffff] size 0x00020000 gran 0x11 romem |
| [SPEW ] PCI: 00:01.0 assign_resources, bus 1 link: 0 done |
| [DEBUG] PCI: 00:1b.0 10 <- [0x008c400000 - 0x008c403fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:1c.0 1c <- [0x0000005000 - 0x0000005fff] size 0x00001000 gran 0x0c bus 02 io |
| [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| [DEBUG] PCI: 00:1c.0 20 <- [0x008c200000 - 0x008c2fffff] size 0x00100000 gran 0x14 bus 02 mem |
| [SPEW ] PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| [DEBUG] PCI: 02:00.0 10 <- [0x008c200000 - 0x008c21ffff] size 0x00020000 gran 0x11 mem |
| [DEBUG] PCI: 02:00.0 18 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io |
| [SPEW ] PCI: 00:1c.0 assign_resources, bus 2 link: 0 done |
| [DEBUG] PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| [DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| [DEBUG] PCI: 00:1c.1 20 <- [0x008c300000 - 0x008c3fffff] size 0x00100000 gran 0x14 bus 03 mem |
| [SPEW ] PCI: 00:1c.1 assign_resources, bus 3 link: 0 |
| [DEBUG] PCI: 03:00.0 10 <- [0x008c300000 - 0x008c300fff] size 0x00001000 gran 0x0c mem |
| [SPEW ] PCI: 00:1c.1 assign_resources, bus 3 link: 0 done |
| [DEBUG] PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| [DEBUG] PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| [DEBUG] PCI: 00:1c.2 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 04 mem |
| [DEBUG] PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io |
| [DEBUG] PCI: 00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem |
| [DEBUG] PCI: 00:1c.3 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 05 mem |
| [DEBUG] PCI: 00:1d.0 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.1 20 <- [0x0000001020 - 0x000000103f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.2 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.3 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.7 10 <- [0x008c404000 - 0x008c4043ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 06 io |
| [DEBUG] PCI: 00:1e.0 24 <- [0x008a100000 - 0x008c0fffff] size 0x02000000 gran 0x14 bus 06 prefmem |
| [DEBUG] PCI: 00:1e.0 20 <- [0x0088000000 - 0x008a0fffff] size 0x02100000 gran 0x14 bus 06 mem |
| [SPEW ] PCI: 00:1e.0 assign_resources, bus 6 link: 0 |
| [DEBUG] PCI: 06:00.0 10 <- [0x008a000000 - 0x008a000fff] size 0x00001000 gran 0x0c mem |
| [DEBUG] PCI: 06:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io |
| [DEBUG] PCI: 06:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io |
| [DEBUG] PCI: 06:00.0 1c <- [0x008a100000 - 0x008c0fffff] size 0x02000000 gran 0x0c prefmem |
| [DEBUG] PCI: 06:00.0 24 <- [0x0088000000 - 0x0089ffffff] size 0x02000000 gran 0x0c mem |
| [SPEW ] PCI: 00:1e.0 assign_resources, bus 6 link: 0 done |
| [SPEW ] PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| [ERROR] PNP: 00ff.1 missing set_resources |
| [ERROR] PNP: 00ff.2 missing set_resources |
| [DEBUG] PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io |
| [ERROR] PNP: 164e.2 70 irq size: 0x0000000001 not assigned in devicetree |
| [ERROR] PNP: 164e.2 74 drq size: 0x0000000001 not assigned in devicetree |
| [ERROR] PNP: 164e.2 75 drq size: 0x0000000001 not assigned in devicetree |
| [DEBUG] PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io |
| [ERROR] PNP: 164e.7 70 irq size: 0x0000000001 not assigned in devicetree |
| [DEBUG] PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io |
| [ERROR] PNP: 164e.19 70 irq size: 0x0000000001 not assigned in devicetree |
| [DEBUG] PNP: 002e.1 60 <- [0x00000003bc - 0x00000003c3] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq |
| [ERROR] PNP: 002e.1 74 drq size: 0x0000000001 not assigned in devicetree |
| [DEBUG] PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io |
| [ERROR] PNP: 002e.7 70 irq size: 0x0000000001 not assigned in devicetree |
| [SPEW ] PCI: 00:1f.0 assign_resources, bus 0 link: 0 done |
| [DEBUG] PCI: 00:1f.1 10 <- [0x00000010b0 - 0x00000010b7] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.1 14 <- [0x00000010d0 - 0x00000010d3] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.1 18 <- [0x00000010b8 - 0x00000010bf] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.1 1c <- [0x00000010d4 - 0x00000010d7] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.1 20 <- [0x00000010a0 - 0x00000010af] size 0x00000010 gran 0x04 io |
| [DEBUG] PCI: 00:1f.2 10 <- [0x00000010c0 - 0x00000010c7] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 14 <- [0x00000010d8 - 0x00000010db] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 18 <- [0x00000010c8 - 0x00000010cf] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 1c <- [0x00000010dc - 0x00000010df] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 20 <- [0x0000001080 - 0x000000109f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1f.2 24 <- [0x008c405000 - 0x008c4053ff] size 0x00000400 gran 0x0a mem |
| [SPEW ] PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| [SPEW ] PCI: 00:1f.3 assign_resources, bus 1 link: 0 done |
| [SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 done |
| [SPEW ] Root Device assign_resources, bus 0 link: 0 done |
| [INFO ] Done setting resources. |
| [SPEW ] Show resources in subtree (Root Device)...After assigning values. |
| [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 |
| [DEBUG] CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| [DEBUG] APIC: 00 |
| [DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100 |
| [SPEW ] DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| [SPEW ] DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| [SPEW ] DOMAIN: 0000 resource base 7fe00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| [SPEW ] DOMAIN: 0000 resource base 7fc00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| [SPEW ] DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8 |
| [SPEW ] DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9 |
| [DEBUG] PCI: 00:00.0 |
| [SPEW ] PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 48 |
| [DEBUG] PCI: 00:01.0 child on link 0 PCI: 01:00.0 |
| [SPEW ] PCI: 00:01.0 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c |
| [SPEW ] PCI: 00:01.0 resource base 80000000 size 8000000 align 27 gran 20 limit 87ffffff flags 60081202 index 24 |
| [SPEW ] PCI: 00:01.0 resource base 8c100000 size 100000 align 20 gran 20 limit 8c1fffff flags 60080202 index 20 |
| [DEBUG] PCI: 01:00.0 |
| [SPEW ] PCI: 01:00.0 resource base 80000000 size 8000000 align 27 gran 27 limit 87ffffff flags 60001200 index 10 |
| [SPEW ] PCI: 01:00.0 resource base 4000 size 100 align 8 gran 8 limit 40ff flags 60000100 index 14 |
| [SPEW ] PCI: 01:00.0 resource base 8c120000 size 10000 align 16 gran 16 limit 8c12ffff flags 60000200 index 18 |
| [SPEW ] PCI: 01:00.0 resource base 8c100000 size 20000 align 17 gran 17 limit 8c11ffff flags 60002200 index 30 |
| [DEBUG] PCI: 00:1b.0 |
| [SPEW ] PCI: 00:1b.0 resource base 8c400000 size 4000 align 14 gran 14 limit 8c403fff flags 60000201 index 10 |
| [DEBUG] PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| [SPEW ] PCI: 00:1c.0 resource base 5000 size 1000 align 12 gran 12 limit 5fff flags 60080102 index 1c |
| [SPEW ] PCI: 00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.0 resource base 8c200000 size 100000 align 20 gran 20 limit 8c2fffff flags 60080202 index 20 |
| [DEBUG] PCI: 02:00.0 |
| [SPEW ] PCI: 02:00.0 resource base 8c200000 size 20000 align 17 gran 17 limit 8c21ffff flags 60000200 index 10 |
| [SPEW ] PCI: 02:00.0 resource base 5000 size 20 align 5 gran 5 limit 501f flags 60000100 index 18 |
| [DEBUG] PCI: 00:1c.1 child on link 0 PCI: 03:00.0 |
| [SPEW ] PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.1 resource base 8c300000 size 100000 align 20 gran 20 limit 8c3fffff flags 60080202 index 20 |
| [DEBUG] PCI: 03:00.0 |
| [SPEW ] PCI: 03:00.0 resource base 8c300000 size 1000 align 12 gran 12 limit 8c300fff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1c.2 |
| [SPEW ] PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.2 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| [DEBUG] PCI: 00:1c.3 |
| [SPEW ] PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.3 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.3 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| [DEBUG] PCI: 00:1d.0 |
| [SPEW ] PCI: 00:1d.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.1 |
| [SPEW ] PCI: 00:1d.1 resource base 1020 size 20 align 5 gran 5 limit 103f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.2 |
| [SPEW ] PCI: 00:1d.2 resource base 1040 size 20 align 5 gran 5 limit 105f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.3 |
| [SPEW ] PCI: 00:1d.3 resource base 1060 size 20 align 5 gran 5 limit 107f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.7 |
| [SPEW ] PCI: 00:1d.7 resource base 8c404000 size 400 align 12 gran 10 limit 8c4043ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1e.0 child on link 0 PCI: 06:00.0 |
| [SPEW ] PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit 3fff flags 60080102 index 1c |
| [SPEW ] PCI: 00:1e.0 resource base 8a100000 size 2000000 align 20 gran 20 limit 8c0fffff flags 60081202 index 24 |
| [SPEW ] PCI: 00:1e.0 resource base 88000000 size 2100000 align 20 gran 20 limit 8a0fffff flags 60080202 index 20 |
| [DEBUG] PCI: 06:00.0 |
| [SPEW ] PCI: 06:00.0 resource base 8a000000 size 1000 align 12 gran 12 limit 8a000fff flags 60000200 index 10 |
| [SPEW ] PCI: 06:00.0 resource base 2000 size 1000 align 2 gran 2 limit 2fff flags 60000100 index 2c |
| [SPEW ] PCI: 06:00.0 resource base 3000 size 1000 align 2 gran 2 limit 3fff flags 60000100 index 34 |
| [SPEW ] PCI: 06:00.0 resource base 8a100000 size 2000000 align 12 gran 12 limit 8c0fffff flags 60001200 index 1c |
| [SPEW ] PCI: 06:00.0 resource base 88000000 size 2000000 align 12 gran 12 limit 89ffffff flags 60000200 index 24 |
| [DEBUG] PCI: 00:1e.2 |
| [DEBUG] PCI: 00:1e.3 |
| [DEBUG] PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| [SPEW ] PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| [SPEW ] PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| [SPEW ] PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| [SPEW ] PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| [SPEW ] PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| [SPEW ] PCI: 00:1f.0 resource base 1680 size 1c align 0 gran 0 limit 0 flags c0040100 index 10000400 |
| [DEBUG] PNP: 00ff.1 |
| [SPEW ] PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| [DEBUG] PNP: 00ff.2 |
| [SPEW ] PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| [SPEW ] PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| [SPEW ] PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| [SPEW ] PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| [DEBUG] PNP: 164e.2 |
| [SPEW ] PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 |
| [SPEW ] PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [SPEW ] PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| [SPEW ] PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 |
| [DEBUG] PNP: 164e.3 |
| [SPEW ] PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 164e.7 |
| [SPEW ] PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 |
| [SPEW ] PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 164e.19 |
| [SPEW ] PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 |
| [SPEW ] PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 002e.0 |
| [DEBUG] PNP: 002e.1 |
| [SPEW ] PNP: 002e.1 resource base 3bc size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 |
| [SPEW ] PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| [SPEW ] PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 |
| [DEBUG] PNP: 002e.2 |
| [SPEW ] PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 |
| [SPEW ] PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 |
| [DEBUG] PNP: 002e.3 |
| [SPEW ] PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 |
| [SPEW ] PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 |
| [DEBUG] PNP: 002e.7 |
| [SPEW ] PNP: 002e.7 resource base 1620 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 |
| [SPEW ] PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [DEBUG] PNP: 002e.a |
| [DEBUG] PCI: 00:1f.1 |
| [SPEW ] PCI: 00:1f.1 resource base 10b0 size 8 align 3 gran 3 limit 10b7 flags 60000100 index 10 |
| [SPEW ] PCI: 00:1f.1 resource base 10d0 size 4 align 2 gran 2 limit 10d3 flags 60000100 index 14 |
| [SPEW ] PCI: 00:1f.1 resource base 10b8 size 8 align 3 gran 3 limit 10bf flags 60000100 index 18 |
| [SPEW ] PCI: 00:1f.1 resource base 10d4 size 4 align 2 gran 2 limit 10d7 flags 60000100 index 1c |
| [SPEW ] PCI: 00:1f.1 resource base 10a0 size 10 align 4 gran 4 limit 10af flags 60000100 index 20 |
| [DEBUG] PCI: 00:1f.2 |
| [SPEW ] PCI: 00:1f.2 resource base 10c0 size 8 align 3 gran 3 limit 10c7 flags 60000100 index 10 |
| [SPEW ] PCI: 00:1f.2 resource base 10d8 size 4 align 2 gran 2 limit 10db flags 60000100 index 14 |
| [SPEW ] PCI: 00:1f.2 resource base 10c8 size 8 align 3 gran 3 limit 10cf flags 60000100 index 18 |
| [SPEW ] PCI: 00:1f.2 resource base 10dc size 4 align 2 gran 2 limit 10df flags 60000100 index 1c |
| [SPEW ] PCI: 00:1f.2 resource base 1080 size 20 align 5 gran 5 limit 109f flags 60000100 index 20 |
| [SPEW ] PCI: 00:1f.2 resource base 8c405000 size 400 align 12 gran 10 limit 8c4053ff flags 60000200 index 24 |
| [DEBUG] PCI: 00:1f.3 child on link 0 I2C: 01:69 |
| [SPEW ] PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| [DEBUG] I2C: 01:69 |
| [DEBUG] I2C: 01:54 |
| [DEBUG] I2C: 01:55 |
| [DEBUG] I2C: 01:56 |
| [DEBUG] I2C: 01:57 |
| [DEBUG] I2C: 01:5c |
| [DEBUG] I2C: 01:5d |
| [DEBUG] I2C: 01:5e |
| [DEBUG] I2C: 01:5f |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 196 ms |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00.0 subsystem <- 17aa/2015 |
| [DEBUG] PCI: 00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:01.0 bridge ctrl <- 001b |
| [DEBUG] PCI: 00:01.0 cmd <- 07 |
| [DEBUG] PCI: 00:1b.0 subsystem <- 17aa/2010 |
| [DEBUG] PCI: 00:1b.0 cmd <- 102 |
| [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.0 subsystem <- 17aa/2001 |
| [DEBUG] PCI: 00:1c.0 cmd <- 107 |
| [DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.1 subsystem <- 8086/27d2 |
| [DEBUG] PCI: 00:1c.1 cmd <- 106 |
| [DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.2 subsystem <- 8086/27d4 |
| [DEBUG] PCI: 00:1c.2 cmd <- 100 |
| [DEBUG] PCI: 00:1c.3 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.3 subsystem <- 8086/27d6 |
| [DEBUG] PCI: 00:1c.3 cmd <- 100 |
| [DEBUG] PCI: 00:1d.0 subsystem <- 17aa/200a |
| [DEBUG] PCI: 00:1d.0 cmd <- 01 |
| [DEBUG] PCI: 00:1d.1 subsystem <- 17aa/200a |
| [DEBUG] PCI: 00:1d.1 cmd <- 01 |
| [DEBUG] PCI: 00:1d.2 subsystem <- 17aa/200a |
| [DEBUG] PCI: 00:1d.2 cmd <- 01 |
| [DEBUG] PCI: 00:1d.3 subsystem <- 17aa/200a |
| [DEBUG] PCI: 00:1d.3 cmd <- 01 |
| [DEBUG] PCI: 00:1d.7 subsystem <- 17aa/200b |
| [DEBUG] PCI: 00:1d.7 cmd <- 102 |
| [DEBUG] PCI: 00:1e.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1e.0 subsystem <- 8086/2448 |
| [DEBUG] PCI: 00:1e.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.0 subsystem <- 8086/27b9 |
| [DEBUG] PCI: 00:1f.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.1 subsystem <- 17aa/200c |
| [DEBUG] PCI: 00:1f.1 cmd <- 01 |
| [DEBUG] PCI: 00:1f.2 subsystem <- 17aa/200d |
| [DEBUG] PCI: 00:1f.2 cmd <- 03 |
| [DEBUG] PCI: 00:1f.3 subsystem <- 8086/27da |
| [DEBUG] PCI: 00:1f.3 cmd <- 101 |
| [DEBUG] PCI: 01:00.0 subsystem <- 17aa/20a4 |
| [DEBUG] PCI: 01:00.0 cmd <- 03 |
| [DEBUG] PCI: 02:00.0 cmd <- 03 |
| [DEBUG] PCI: 03:00.0 cmd <- 02 |
| [DEBUG] PCI: 06:00.0 bridge ctrl <- 0143 |
| [DEBUG] PCI: 06:00.0 subsystem <- 17aa/2012 |
| [DEBUG] PCI: 06:00.0 cmd <- 03 |
| [INFO ] done. |
| [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 10 ms |
| [INFO ] Initializing devices... |
| [DEBUG] Root Device init |
| [SPEW ] recv_ec_data: 0x00 |
| [DEBUG] Root Device init finished in 0 msecs |
| [DEBUG] CPU_CLUSTER: 0 init |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xce80 size 0x18000 in mcache @0x7fbdd0ac |
| [DEBUG] microcode: sig=0x6f6 pf=0x20 revision=0x0 |
| [INFO ] microcode: updated to revision 0xd1 date=2010-10-01 |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007fc00000 size 0x7fb40000 type 6 |
| [DEBUG] 0x000000007fc00000 - 0x0000000080000000 size 0x00400000 type 0 |
| [DEBUG] 0x0000000080000000 - 0x0000000088000000 size 0x08000000 type 1 |
| [DEBUG] 0x0000000088000000 - 0x0000000100000000 size 0x78000000 type 0 |
| [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [SPEW ] call enable_fixed_mtrr() |
| [DEBUG] CPU physical address size: 36 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 6/3. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 1 base 0x000000007fc00000 mask 0x0000000fffc00000 type 0 |
| [DEBUG] MTRR: 2 base 0x0000000080000000 mask 0x0000000ff8000000 type 1 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [DEBUG] CPU has 2 cores. |
| [DEBUG] Setting up SMI for CPU |
| [INFO ] Will perform SMM setup. |
| [INFO ] CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 |
| [DEBUG] Processing 18 relocs. Offset value of 0x00030000 |
| [DEBUG] Attempting to start 1 APs |
| [DEBUG] Waiting for 10ms after sending INIT. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [INFO ] LAPIC 0x1 in XAPIC mode. |
| [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x000000d1 |
| [SPEW ] smm_setup_relocation_handler: enter |
| [SPEW ] smm_setup_relocation_handler: exit |
| [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0 |
| [DEBUG] Processing 11 relocs. Offset value of 0x00038000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x7fe00800 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 |
| [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7fba7fb0 |
| [DEBUG] Installing permanent SMM handler to 0x7fe00000 |
| [DEBUG] smm_load_module: total_smm_space_needed 6648, available -> 100000 |
| [DEBUG] Loading module at 0x7fefb000 with entry 0x7fefb839. filesize: 0x1a08 memsize: 0x5a48 |
| [DEBUG] Processing 75 relocs. Offset value of 0x7fefb000 |
| [DEBUG] smm_load_module: smram_start: 0x7fe00000 |
| [DEBUG] smm_load_module: smram_end: 7ff00000 |
| [DEBUG] smm_load_module: handler start 0x7fefb839 |
| [DEBUG] smm_load_module: handler_size 6890 |
| [DEBUG] smm_load_module: fxsave_area 0x7feffc00 |
| [DEBUG] smm_load_module: fxsave_size 400 |
| [DEBUG] smm_load_module: CONFIG_MSEG_SIZE 0x0 |
| [DEBUG] smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0 |
| [DEBUG] smm_load_module: handler_mod_params.smbase = 0x7fe00000 |
| [DEBUG] smm_load_module: per_cpu_save_state_size = 0x400 |
| [DEBUG] smm_load_module: num_cpus = 0x2 |
| [DEBUG] smm_load_module: cbmemc = 0x7fbde000, cbmemc_size = 0x20000 |
| [DEBUG] smm_load_module: total_save_state_size = 0x800 |
| [DEBUG] smm_load_module: cpu0 entry: 7feeb000 |
| [DEBUG] smm_create_map: cpus allowed in one segment 30 |
| [DEBUG] smm_create_map: min # of segments needed 1 |
| [DEBUG] CPU 0x0 |
| [DEBUG] smbase 7feeb000 entry 7fef3000 |
| [DEBUG] ss_start 7fefac00 code_end 7fef31e0 |
| [DEBUG] CPU 0x1 |
| [DEBUG] smbase 7feeac00 entry 7fef2c00 |
| [DEBUG] ss_start 7fefa800 code_end 7fef2de0 |
| [DEBUG] Loading module at 0x7fef3000 with entry 0x7fef3000. filesize: 0x1e0 memsize: 0x1e0 |
| [DEBUG] Processing 11 relocs. Offset value of 0x7fef3000 |
| [INFO ] smm_place_entry_code: smbase 7feeac00, stack_top 7fe00800 |
| [DEBUG] SMM Module: placing smm entry code at 7fef2c00, cpu # 0x1 |
| [DEBUG] smm_place_entry_code: copying from 7fef3000 to 7fef2c00 0x1e0 bytes |
| [DEBUG] smm_module_setup_stub: stack_top = 0x7fe00800 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x100000 |
| [DEBUG] SMM Module: stub loaded at 7fef3000. Will call 0x7fefb839 |
| [DEBUG] Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7feeb000, cpu = 0 |
| [DEBUG] In relocation handler: cpu 0 |
| [DEBUG] New SMBASE=0x7feeb000 |
| [SPEW ] SMM revision: 0x00030100 |
| [DEBUG] Relocation complete. |
| [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL already locked |
| [DEBUG] IA32_FEATURE_CONTROL already locked |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7feeac00, cpu = 1 |
| [DEBUG] In relocation handler: cpu 1 |
| [DEBUG] New SMBASE=0x7feeac00 |
| [SPEW ] SMM revision: 0x00030100 |
| [DEBUG] Relocation complete. |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 6f6 |
| [DEBUG] CPU: family 06, model 0f, stepping 06 |
| [INFO ] CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| [INFO ] CPU #0 initialized |
| [INFO ] Initializing CPU #1 |
| [DEBUG] CPU: vendor Intel device 6f6 |
| [DEBUG] CPU: family 06, model 0f, stepping 06 |
| [INFO ] CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| [INFO ] CPU #1 initialized |
| [DEBUG] CPU 1 going down... |
| [INFO ] bsp_do_flight_plan done after 24 msecs. |
| [DEBUG] Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| [DEBUG] SMI_STS: |
| [SPEW ] PM1_STS: |
| [SPEW ] PM1_EN: 0 |
| [DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO1 GPIO0 |
| [DEBUG] ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| [DEBUG] TCO_STS: |
| [DEBUG] Locking SMM. |
| [DEBUG] CPU_CLUSTER: 0 init finished in 55 msecs |
| [DEBUG] PCI: 00:1b.0 init |
| [DEBUG] Azalia: codec type: Azalia |
| [DEBUG] Azalia: base = 8c400000 |
| [DEBUG] Azalia: codec_mask = 03 |
| [DEBUG] azalia_audio: Initializing codec #1 |
| [DEBUG] azalia_audio: codec viddid: 14f12bfa |
| [DEBUG] azalia_audio: No verb! |
| [DEBUG] azalia_audio: Initializing codec #0 |
| [DEBUG] azalia_audio: codec viddid: 11d41981 |
| [DEBUG] azalia_audio: verb_size: 44 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] PCI: 00:1b.0 init finished in 6 msecs |
| [DEBUG] PCI: 00:1c.0 init |
| [DEBUG] Initializing ICH7 PCIe bridge. |
| [DEBUG] PCI: 00:1c.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 init |
| [DEBUG] Initializing ICH7 PCIe bridge. |
| [DEBUG] PCI: 00:1c.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 init |
| [DEBUG] Initializing ICH7 PCIe bridge. |
| [DEBUG] PCI: 00:1c.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.3 init |
| [DEBUG] Initializing ICH7 PCIe bridge. |
| [DEBUG] PCI: 00:1c.3 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.0 init |
| [DEBUG] UHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.1 init |
| [DEBUG] UHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.2 init |
| [DEBUG] UHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.3 init |
| [DEBUG] UHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.3 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.7 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.7 init finished in 0 msecs |
| [DEBUG] PCI: 00:1e.0 init |
| [DEBUG] PCI: 00:1e.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 init |
| [DEBUG] i82801gx: lpc_init |
| [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 |
| [DEBUG] IOAPIC: ID = 0x02 |
| [SPEW ] IOAPIC: Dumping registers |
| [SPEW ] reg 0x0000: 0x02000000 |
| [SPEW ] reg 0x0001: 0x00170020 |
| [SPEW ] reg 0x0002: 0x00170020 |
| [DEBUG] IOAPIC: 24 interrupts |
| [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 |
| [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000 |
| [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00000700 |
| [DEBUG] No CMOS option 'power_on_after_fail'. |
| [INFO ] Set power on after power failure. |
| [INFO ] NMI sources enabled. |
| [DEBUG] rtc_failed = 0x0 |
| [DEBUG] RTC Init |
| [DEBUG] apm_control: Disabling ACPI. |
| [DEBUG] APMC done. |
| [DEBUG] PCI: 00:1f.0 init finished in 11 msecs |
| [DEBUG] PCI: 00:1f.1 init |
| [DEBUG] i82801gx_ide: initializing... IDE0 |
| [DEBUG] PCI: 00:1f.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.2 init |
| [DEBUG] i82801gx_sata: initializing... |
| [DEBUG] SATA controller in AHCI mode. |
| [DEBUG] PCI: 00:1f.2 init finished in 0 msecs |
| [DEBUG] PCI: 01:00.0 init |
| [INFO ] CBFS: Found 'pci1002,7149.rom' @0x3ec40 size 0x10000 in mcache @0x7fbdd214 |
| [DEBUG] In CBFS, ROM address for PCI: 01:00.0 = 0xffe3ee6c |
| [SPEW ] PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x0238 |
| [SPEW ] PCI ROM image, vendor ID 1002, device ID 7149, |
| [SPEW ] PCI ROM image, Class Code 030000, Code Type 00 |
| [DEBUG] Copying VGA ROM Image from 0xffe3ee6c to 0xc0000, 0xfe00 bytes |
| [SPEW ] Real mode stub @0x00000600: 889 bytes |
| [DEBUG] Calling Option ROM... |
| [DEBUG] intel_vga_int15_handler: AX=5f08 BX=ff2d CX=0000 DX=4000 |
| [DEBUG] Unknown INT15 function 5f08! |
| [DEBUG] int15 call returned error. |
| [DEBUG] intel_vga_int15_handler: AX=5f08 BX=0002 CX=8980 DX=4000 |
| [DEBUG] Unknown INT15 function 5f08! |
| [DEBUG] int15 call returned error. |
| [DEBUG] intel_vga_int15_handler: AX=5f08 BX=0005 CX=8913 DX=4000 |
| [DEBUG] Unknown INT15 function 5f08! |
| [DEBUG] int15 call returned error. |
| [DEBUG] intel_vga_int15_handler: AX=5f08 BX=0101 CX=0000 DX=0980 |
| [DEBUG] Unknown INT15 function 5f08! |
| [DEBUG] int15 call returned error. |
| [DEBUG] ... Option ROM returned. |
| [DEBUG] VGA Option ROM was run |
| [DEBUG] PCI: 01:00.0 init finished in 217 msecs |
| [DEBUG] PCI: 02:00.0 init |
| [DEBUG] PCI: 02:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 03:00.0 init |
| [DEBUG] PCI: 03:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 06:00.0 init |
| [INFO ] Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller |
| [DEBUG] PCI: 06:00.0 init finished in 0 msecs |
| [DEBUG] PNP: 00ff.2 init |
| [DEBUG] PNP: 00ff.2 init finished in 0 msecs |
| [DEBUG] PNP: 164e.2 init |
| [DEBUG] PNP: 164e.2 init finished in 0 msecs |
| [DEBUG] PNP: 164e.7 init |
| [DEBUG] PNP: 164e.7 init finished in 0 msecs |
| [DEBUG] PNP: 164e.19 init |
| [DEBUG] PNP: 164e.19 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:69 init |
| [DEBUG] Changing 12 of the 12 ck505 config bytes. |
| [DEBUG] I2C: 01:69 init finished in 26 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| [DEBUG] I2C: 01:54 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| [DEBUG] I2C: 01:55 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| [DEBUG] I2C: 01:56 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| [DEBUG] I2C: 01:57 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| [DEBUG] Locking EEPROM RFID |
| [DEBUG] init EEPROM done |
| [DEBUG] I2C: 01:5c init finished in 21 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| [DEBUG] I2C: 01:5d init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| [DEBUG] I2C: 01:5e init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| [DEBUG] I2C: 01:5f init finished in 0 msecs |
| [INFO ] Devices initialized |
| [SPEW ] Show all devs... After init. |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] APIC: 00: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 1 |
| [SPEW ] PCI: 00:02.0: enabled 0 |
| [SPEW ] PCI: 00:02.1: enabled 0 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 1 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1d.1: enabled 1 |
| [SPEW ] PCI: 00:1d.2: enabled 1 |
| [SPEW ] PCI: 00:1d.3: enabled 1 |
| [SPEW ] PCI: 00:1d.7: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 1 |
| [SPEW ] PCI: 00:1e.2: enabled 0 |
| [SPEW ] PCI: 00:1e.3: enabled 0 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.1: enabled 1 |
| [SPEW ] PCI: 01:00.0: enabled 1 |
| [SPEW ] PCI: 06:00.0: enabled 1 |
| [SPEW ] PNP: 00ff.1: enabled 1 |
| [SPEW ] PNP: 00ff.2: enabled 1 |
| [SPEW ] PNP: 164e.2: enabled 1 |
| [SPEW ] PNP: 164e.3: enabled 0 |
| [SPEW ] PNP: 164e.7: enabled 1 |
| [SPEW ] PNP: 164e.19: enabled 1 |
| [SPEW ] PNP: 002e.0: enabled 0 |
| [SPEW ] PNP: 002e.1: enabled 1 |
| [SPEW ] PNP: 002e.2: enabled 0 |
| [SPEW ] PNP: 002e.3: enabled 1 |
| [SPEW ] PNP: 002e.7: enabled 1 |
| [SPEW ] PNP: 002e.a: enabled 0 |
| [SPEW ] I2C: 01:69: enabled 1 |
| [SPEW ] I2C: 01:54: enabled 1 |
| [SPEW ] I2C: 01:55: enabled 1 |
| [SPEW ] I2C: 01:56: enabled 1 |
| [SPEW ] I2C: 01:57: enabled 1 |
| [SPEW ] I2C: 01:5c: enabled 1 |
| [SPEW ] I2C: 01:5d: enabled 1 |
| [SPEW ] I2C: 01:5e: enabled 1 |
| [SPEW ] I2C: 01:5f: enabled 1 |
| [SPEW ] PCI: 02:00.0: enabled 1 |
| [SPEW ] PCI: 03:00.0: enabled 1 |
| [SPEW ] APIC: 01: enabled 1 |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 290 / 75 ms |
| [INFO ] Finalize devices... |
| [DEBUG] PCI: 00:1f.0 final |
| [INFO ] Devices finalized |
| [SPEW ] PCI srcbusirq = 0x4 from dev = 0x1 and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x8 from dev = 0x2 and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x6c from dev = 0x1b and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x70 from dev = 0x1c and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x71 from dev = 0x1c and pirq = 1 |
| [SPEW ] PCI srcbusirq = 0x72 from dev = 0x1c and pirq = 2 |
| [SPEW ] PCI srcbusirq = 0x73 from dev = 0x1c and pirq = 3 |
| [SPEW ] PCI srcbusirq = 0x74 from dev = 0x1d and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x75 from dev = 0x1d and pirq = 1 |
| [SPEW ] PCI srcbusirq = 0x76 from dev = 0x1d and pirq = 2 |
| [SPEW ] PCI srcbusirq = 0x77 from dev = 0x1d and pirq = 3 |
| [SPEW ] PCI srcbusirq = 0x7c from dev = 0x1f and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x7d from dev = 0x1f and pirq = 1 |
| [SPEW ] PCI srcbusirq = 0x7e from dev = 0x1f and pirq = 2 |
| [SPEW ] PCI srcbusirq = 0x0 from dev = 0x0 and pirq = 0 |
| [DEBUG] Wrote the mp table end at: 0x000f0010 - 0x000f01bc |
| [SPEW ] PCI srcbusirq = 0x4 from dev = 0x1 and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x8 from dev = 0x2 and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x6c from dev = 0x1b and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x70 from dev = 0x1c and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x71 from dev = 0x1c and pirq = 1 |
| [SPEW ] PCI srcbusirq = 0x72 from dev = 0x1c and pirq = 2 |
| [SPEW ] PCI srcbusirq = 0x73 from dev = 0x1c and pirq = 3 |
| [SPEW ] PCI srcbusirq = 0x74 from dev = 0x1d and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x75 from dev = 0x1d and pirq = 1 |
| [SPEW ] PCI srcbusirq = 0x76 from dev = 0x1d and pirq = 2 |
| [SPEW ] PCI srcbusirq = 0x77 from dev = 0x1d and pirq = 3 |
| [SPEW ] PCI srcbusirq = 0x7c from dev = 0x1f and pirq = 0 |
| [SPEW ] PCI srcbusirq = 0x7d from dev = 0x1f and pirq = 1 |
| [SPEW ] PCI srcbusirq = 0x7e from dev = 0x1f and pirq = 2 |
| [SPEW ] PCI srcbusirq = 0x0 from dev = 0x0 and pirq = 0 |
| [DEBUG] Wrote the mp table end at: 0x7fb7a010 - 0x7fb7a1bc |
| [DEBUG] MP table: 444 bytes. |
| [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3b2c0 size 0x314e in mcache @0x7fbdd198 |
| [WARN ] CBFS: 'fallback/slic' not found. |
| [INFO ] ACPI: Writing ACPI tables at 7fb56000. |
| [DEBUG] ACPI: * FACS |
| [DEBUG] ACPI: * DSDT |
| [DEBUG] ACPI: * FADT |
| [DEBUG] ACPI: added table 1/32, length now 40 |
| [DEBUG] ACPI: * SSDT |
| [DEBUG] Found 1 CPU(s) with 2 core(s) each. |
| [DEBUG] clocks between 1000 and 2000 MHz. |
| [DEBUG] adding 4 P-States between busratio 6 and c, incl. P0 |
| [DEBUG] PSS: 2000MHz power 35000 control 0xc2a status 0xc2a |
| [DEBUG] PSS: 1666MHz power 31666 control 0xa21 status 0xa21 |
| [DEBUG] PSS: 1333MHz power 28333 control 0x81a status 0x81a |
| [DEBUG] PSS: 1000MHz power 25000 control 0x613 status 0x613 |
| [DEBUG] clocks between 1000 and 2000 MHz. |
| [DEBUG] adding 4 P-States between busratio 6 and c, incl. P0 |
| [DEBUG] PSS: 2000MHz power 35000 control 0xc2a status 0xc2a |
| [DEBUG] PSS: 1666MHz power 31666 control 0xa21 status 0xa21 |
| [DEBUG] PSS: 1333MHz power 28333 control 0x81a status 0x81a |
| [DEBUG] PSS: 1000MHz power 25000 control 0x613 status 0x613 |
| [DEBUG] Generating ACPI PIRQ entries |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:01.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=1 pirq=1 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=4 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=5 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=6 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=7 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.1: pin=1 pirq=1 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.2: pin=2 pirq=2 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.3: pin=3 pirq=3 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1f.1: pin=2 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=0 pirq=7 |
| [INFO ] CBFS: Found 'pci1002,7149.rom' @0x3ec40 size 0x10000 in mcache @0x7fbdd214 |
| [DEBUG] In CBFS, ROM address for PCI: 01:00.0 = 0xffe3ee6c |
| [SPEW ] PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x0238 |
| [SPEW ] PCI ROM image, vendor ID 1002, device ID 7149, |
| [SPEW ] PCI ROM image, Class Code 030000, Code Type 00 |
| [ERROR] PCI: 01:00.0: Missing ACPI scope |
| [INFO ] ACPI: * H8 |
| [INFO ] H8: BDC not installed |
| [INFO ] H8: WWAN detection not implemented. Assuming WWAN installed |
| [DEBUG] ACPI: added table 2/32, length now 44 |
| [DEBUG] ACPI: * MCFG |
| [DEBUG] ACPI: added table 3/32, length now 48 |
| [DEBUG] ACPI: * MADT |
| [DEBUG] ACPI: added table 4/32, length now 52 |
| [DEBUG] current = 7fb59cd0 |
| [DEBUG] ACPI: * HPET |
| [DEBUG] ACPI: added table 5/32, length now 56 |
| [DEBUG] Copying initialized VBIOS image from 0x000c0000 |
| [DEBUG] ACPI: * VFCT at 7fb59d10 |
| [DEBUG] ACPI: added table 6/32, length now 60 |
| [INFO ] ACPI: done. |
| [DEBUG] ACPI tables: 80768 bytes. |
| [DEBUG] smbios_write_tables: 7fb55000 |
| [SPEW ] recv_ec_data: 0x37 |
| [SPEW ] recv_ec_data: 0x39 |
| [SPEW ] recv_ec_data: 0x48 |
| [SPEW ] recv_ec_data: 0x54 |
| [SPEW ] recv_ec_data: 0x35 |
| [SPEW ] recv_ec_data: 0x30 |
| [SPEW ] recv_ec_data: 0x57 |
| [SPEW ] recv_ec_data: 0x57 |
| [SPEW ] recv_ec_data: 0x04 |
| [SPEW ] recv_ec_data: 0x03 |
| [DEBUG] SMBIOS tables: 652 bytes. |
| [DEBUG] Writing table forward entry at 0x00000500 |
| [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d026 |
| [DEBUG] Writing coreboot table at 0x7fb7b000 |
| [INFO ] CBFS: Found 'cmos_layout.bin' @0x3e580 size 0x680 in mcache @0x7fbdd1ec |
| [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| [DEBUG] 1. 0000000000001000-000000000009ffff: RAM |
| [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED |
| [DEBUG] 3. 0000000000100000-000000007fb54fff: RAM |
| [DEBUG] 4. 000000007fb55000-000000007fb93fff: CONFIGURATION TABLES |
| [DEBUG] 5. 000000007fb94000-000000007fbcefff: RAMSTAGE |
| [DEBUG] 6. 000000007fbcf000-000000007fbfffff: CONFIGURATION TABLES |
| [DEBUG] 7. 000000007fc00000-000000007fffffff: RESERVED |
| [DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| [INFO ] Manufacturer: c2 |
| [INFO ] SF: Detected c2 2015 with sector size 0x1000, total 0x200000 |
| [DEBUG] Wrote coreboot table at: 0x7fb7b000, 0xa08 bytes, checksum f804 |
| [DEBUG] coreboot table: 2592 bytes. |
| [DEBUG] IMD ROOT 0. 0x7fbff000 0x00001000 |
| [DEBUG] IMD SMALL 1. 0x7fbfe000 0x00001000 |
| [DEBUG] CONSOLE 2. 0x7fbde000 0x00020000 |
| [DEBUG] RO MCACHE 3. 0x7fbdd000 0x00000378 |
| [DEBUG] TIME STAMP 4. 0x7fbdc000 0x00000910 |
| [DEBUG] ROMSTG STCK 5. 0x7fbdb000 0x00001000 |
| [DEBUG] AFTER CAR 6. 0x7fbcf000 0x0000c000 |
| [DEBUG] RAMSTAGE 7. 0x7fb93000 0x0003c000 |
| [DEBUG] SMM BACKUP 8. 0x7fb83000 0x00010000 |
| [DEBUG] COREBOOT 9. 0x7fb7b000 0x00008000 |
| [DEBUG] SMP TABLE 10. 0x7fb7a000 0x00001000 |
| [DEBUG] ACPI 11. 0x7fb56000 0x00024000 |
| [DEBUG] SMBIOS 12. 0x7fb55000 0x00001000 |
| [DEBUG] IMD small region: |
| [DEBUG] IMD ROOT 0. 0x7fbfec00 0x00000400 |
| [DEBUG] FMAP 1. 0x7fbfeb40 0x000000b6 |
| [DEBUG] ROMSTAGE 2. 0x7fbfeb20 0x00000004 |
| [DEBUG] ACPI GNVS 3. 0x7fbfea20 0x00000100 |
| [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 167 / 33 ms |
| [INFO ] CBFS: Found 'fallback/payload' @0x54180 size 0x11bf1 in mcache @0x7fbdd284 |
| [DEBUG] Checking segment from ROM address 0xffe543ac |
| [DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable. |
| [DEBUG] Checking segment from ROM address 0xffe543c8 |
| [DEBUG] Loading segment from ROM address 0xffe543ac |
| [DEBUG] code (compression=1) |
| [DEBUG] New segment dstaddr 0x000de6e0 memsize 0x21920 srcaddr 0xffe543e4 filesize 0x11bb9 |
| [DEBUG] Loading Segment: addr: 0x000de6e0 memsz: 0x0000000000021920 filesz: 0x0000000000011bb9 |
| [DEBUG] using LZMA |
| [SPEW ] [ 0x000de6e0, 00100000, 0x00100000) <- ffe543e4 |
| [DEBUG] Loading segment from ROM address 0xffe543c8 |
| [DEBUG] Entry Point 0x000fd28c |
| [SPEW ] Loaded segments |
| [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 42 / 3 ms |
| [DEBUG] ICH-NM10-PCH: watchdog disabled |
| [DEBUG] Jumping to boot code at 0x000fd28c(0x7fb7b000) |
| [SPEW ] CPU0: stack: 0x7fbc2000 - 0x7fbc3000, lowest used address 0x7fbc2a48, stack used: 1464 bytes |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| BUILD: gcc: (coreboot toolchain v2022-04-04_9a8d0a03db) 11.2.0 binutils: (GNU Binutils) 2.37 |
| Found coreboot cbmem console @ 7fbde000 |
| Found mainboard LENOVO ThinkPad T60 |
| Relocating init from 0x000dfe40 to 0x7fb07aa0 (size 54464) |
| Found CBFS header at 0xffe0022c |
| multiboot: eax=7fbbf378, ebx=7fbbf344 |
| Found 21 PCI devices (max PCI bus is 06) |
| Copying SMBIOS from 0x7fb55000 to 0x000f61e0 |
| Copying SMBIOS 3.0 from 0x7fb55020 to 0x000f61c0 |
| Copying ACPI RSDP from 0x7fb56000 to 0x000f6190 |
| Copying MPTABLE from 0x7fb7a000/7fb7a010 to 0x000f5fd0 |
| table(50434146)=0x7fb593f0 (via xsdt) |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| Machine UUID b0a6e801-4954-11cb-89d2-fd20d24d8810 |
| EHCI init on dev 00:1d.7 (regs=0x8c404020) |
| UHCI init on dev 00:1d.0 (io=1000) |
| UHCI init on dev 00:1d.1 (io=1020) |
| UHCI init on dev 00:1d.2 (io=1040) |
| UHCI init on dev 00:1d.3 (io=1060) |
| ATA controller 1 at 1f0/3f4/0 (irq 14 dev f9) |
| ATA controller 2 at 170/374/0 (irq 15 dev f9) |
| AHCI controller at 00:1f.2, iobase 0x8c405000, irq 0 |
| Searching bootorder for: HALT |
| Found 0 lpt ports |
| Found 1 serial ports |
| DVD/CD [ata0-0: HL-DT-STCD-RW/DVD DRIVE GCC-4247N ATAPI-5 DVD/CD] |
| Searching bootorder for: /pci@i0cf8/*@1f,1/drive@0/disk@0 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,1/drive@0/disk@0 |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-6 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: registering: "AHCI/0: SanDisk SDSSDH3 512G ATA-11 Hard-Disk (476 GiBytes)" |
| PS2 keyboard initialized |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f5ee0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1000215216 |
| Space available for UMB: d0000-ec000, f5a00-f5eb0 |
| Returned 253952 bytes of ZoneHigh |
| e820 map has 6 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007fb53000 = 1 RAM |
| 4: 000000007fb53000 - 0000000080000000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| enter handle_19: |
| NULL |
| Booting from DVD/CD... |
| Device reports MEDIUM NOT PRESENT - 2 tries left |
| Device reports MEDIUM NOT PRESENT - 1 tries left |
| Device reports MEDIUM NOT PRESENT - 0 tries left |
| Boot failed: Could not read from CDROM (code 0003) |
| enter handle_18: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |