| |
| coreboot-4.11-947-ga988091d39 Sat Jan 18 22:07:47 UTC 2020 bootblock starting (log level: 7)... |
| FMAP: Found "FLASH" version 1.1 at 0x0. |
| FMAP: base = 0xffe00000 size = 0x200000 #areas = 3 |
| FMAP: area COREBOOT found @ 200 (2096640 bytes) |
| CBFS: Locating 'fallback/romstage' |
| CBFS: Found @ offset 80 size c224 |
| BS: bootblock times (exec / console): total (unknown) / 1 ms |
| PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe00000, size: 0x00010000 |
| |
| |
| coreboot-4.11-947-ga988091d39 Sat Jan 18 22:07:47 UTC 2020 romstage starting (log level: 7)... |
| SMBus controller enabled |
| Setting up static southbridge registers... done. |
| Disabling Watchdog reboot... done. |
| |
| Mobile Intel(R) 82945PM Express Chipset |
| (G)MCH capable of up to FSB 800 MHz |
| (G)MCH capable of up to DDR2-667 |
| Setting up static northbridge registers...FMAP: area COREBOOT found @ 200 (2096640 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 33b40 size 680 |
| done. |
| Waiting for MCHBAR to come up...ok |
| SB: Resume from S3 detected. |
| Setting up RAM controller. |
| This mainboard supports Dual Channel Operation. |
| Reading SPD using i2c block operation. |
| DDR II Channel 0 Socket 0: x8DDS |
| DIMM 0 side 0 = 512 MB |
| DIMM 0 side 1 = 512 MB |
| DDR II Channel 0 Socket 1: N/A |
| Reading SPD using i2c block operation. |
| DDR II Channel 1 Socket 0: x8DDS |
| DIMM 2 side 0 = 1024 MB |
| DIMM 2 side 1 = 1024 MB |
| DDR II Channel 1 Socket 1: N/A |
| Memory will be driven at 667MT with CAS=5 clocks |
| tRAS = 15 cycles |
| tRP = 5 cycles |
| tRCD = 5 cycles |
| tWR = 5 cycles |
| tRFC = 43 cycles |
| Refresh: 7.8us |
| Setting Graphics Frequency... |
| FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz |
| Setting Memory Frequency... CLKCFG = 0x00010023, CLKCFG = 0x00010043, ok |
| Setting mode of operation for memory channels...Dual Channel Asymmetric. |
| Programming Clock Crossing...MEM=667 FSB=667... ok |
| Setting RAM size... |
| C0DRB = 0x20202010 |
| C1DRB = 0x60606040 |
| TOLUD = 0x00c0 |
| Setting row attributes... |
| C0DRA = 0x0033 |
| C1DRA = 0x0033 |
| one dimm per channel config.. |
| Initializing System Memory IO... |
| Programming Dual Channel RCOMP |
| Table Index: 18 |
| Programming DLL Timings... |
| Enabling System Memory IO... |
| RAM initialization finished. |
| Setting up Egress Port RCRB |
| Loading port arbitration table ...ok |
| Wait for VC1 negotiation ...ok |
| Setting up DMI RCRB |
| Wait for VC1 negotiation ...done.. |
| Internal graphics: enabled |
| Waiting for DMI hardware...ok |
| Enabling PCI Express x16 Link |
| SLOTSTS: 0048 |
| PCIe link training ... Detected PCIe device 1002:7149 |
| PCIe x16 link training succeeded. |
| PCIe device class: 030000 |
| PCIe device is VGA. Disabling IGD. |
| Setting up Root Complex Topology |
| SMM Memory Map |
| SMRAM : 0xbfe00000 0x200000 |
| Subregion 0: 0xbfe00000 0x100000 |
| Subregion 1: 0xbff00000 0x100000 |
| Subregion 2: 0xc0000000 0x0 |
| MTRR Range: Start=bf400000 End=bf800000 (Size 400000) |
| MTRR Range: Start=bf800000 End=bfc00000 (Size 400000) |
| MTRR Range: Start=bfe00000 End=c0000000 (Size 200000) |
| MTRR Range: Start=ffe00000 End=0 (Size 200000) |
| BS: romstage times (exec / console): total (unknown) / 4 ms |
| |
| |
| coreboot-4.11-947-ga988091d39 Sat Jan 18 22:07:47 UTC 2020 postcar starting (log level: 7)... |
| Jumping to image. |
| |
| |
| coreboot-4.11-947-ga988091d39 Sat Jan 18 22:07:47 UTC 2020 ramstage starting (log level: 7)... |
| S3 Resume. |
| Enumerating buses... |
| Root Device scanning... |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/27a0] enabled |
| PCI: 00:01.0 subordinate bus PCI Express |
| PCI: 00:01.0 [8086/27a1] enabled |
| PCI: Static device PCI: 00:02.0 not found, disabling it. |
| PCI: Static device PCI: 00:02.1 not found, disabling it. |
| PCI: 00:1b.0 [8086/27d8] enabled |
| PCI: 00:1c.0 [8086/27d0] enabled |
| PCI: 00:1c.1 [8086/27d2] enabled |
| PCI: 00:1c.2 [8086/27d4] enabled |
| PCI: 00:1c.3 [8086/27d6] enabled |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1d.0 [8086/27c8] enabled |
| PCI: 00:1d.1 [8086/27c9] enabled |
| PCI: 00:1d.2 [8086/27ca] enabled |
| PCI: 00:1d.3 [8086/27cb] enabled |
| PCI: 00:1d.7 [8086/27cc] enabled |
| PCI: 00:1e.0 [8086/2448] enabled |
| PCI: 00:1e.2: Disabling device |
| PCI: 00:1e.2: Disabling device |
| PCI: 00:1e.2 [8086/27de] disabled |
| PCI: 00:1e.3: Disabling device |
| PCI: 00:1e.3: Disabling device |
| PCI: 00:1e.3 [8086/27dd] disabled |
| PCI: 00:1f.0 [8086/27b9] enabled |
| PCI: 00:1f.1 [8086/27df] enabled |
| Set SATA mode early |
| Set SATA mode early |
| PCI: 00:1f.2 [8086/27c5] enabled |
| PCI: 00:1f.3 [8086/27da] enabled |
| PCI: Leftover static devices: |
| PCI: 00:02.0 |
| PCI: 00:02.1 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: Check your devicetree.cb. |
| PCI: 00:01.0 scanning... |
| PCI: pci_scan_bus for bus 01 |
| PCI: 01:00.0 [1002/7149] enabled |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled L0s and L1 |
| PCIe: Max_Payload_Size adjusted to 128 |
| Failed to enable LTR for dev = PCI: 01:00.0 |
| scan_bus: bus PCI: 00:01.0 finished in 0 msecs |
| PCI: 00:1c.0 scanning... |
| PCI: pci_scan_bus for bus 02 |
| PCI: 02:00.0 [8086/109a] enabled |
| scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| PCI: 00:1c.1 scanning... |
| PCI: pci_scan_bus for bus 03 |
| scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| PCI: 00:1c.2 scanning... |
| PCI: pci_scan_bus for bus 04 |
| scan_bus: bus PCI: 00:1c.2 finished in 0 msecs |
| PCI: 00:1c.3 scanning... |
| PCI: pci_scan_bus for bus 05 |
| scan_bus: bus PCI: 00:1c.3 finished in 0 msecs |
| PCI: 00:1e.0 scanning... |
| PCI: pci_scan_bus for bus 06 |
| PCI: 06:00.0 [104c/ac56] enabled |
| scan_bus: bus PCI: 00:1e.0 finished in 0 msecs |
| PCI: 00:1f.0 scanning... |
| PMH7: ID 03 Revision 10 |
| PNP: 00ff.1 enabled |
| H8: EC Firmware ID 79HT50WW-3.4, Version 7.01A |
| No CMOS option 'usb_always_on'. |
| H8: BDC detection not implemented. Assuming BDC installed |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| No CMOS option 'fn_ctrl_swap'. |
| PNP: 00ff.2 enabled |
| PNP: 164e.2 enabled |
| PNP: 164e.3 disabled |
| PNP: 164e.7 enabled |
| PNP: 164e.19 enabled |
| PNP: 002e.0 disabled |
| PNP: 002e.1 enabled |
| PNP: 002e.2 disabled |
| PNP: 002e.3 enabled |
| PNP: 002e.7 enabled |
| PNP: 002e.a disabled |
| scan_bus: bus PCI: 00:1f.0 finished in 9 msecs |
| PCI: 00:1f.3 scanning... |
| bus: PCI: 00:1f.3[0]->I2C: 01:69 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| scan_bus: bus DOMAIN: 0000 finished in 10 msecs |
| scan_bus: bus Root Device finished in 10 msecs |
| done |
| BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 0 ms |
| found VGA at PCI: 01:00.0 |
| Setting up VGA for PCI: 01:00.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| pci_tolm: 0xffffffff |
| TSEG decoded, subtracting 2M |
| Unused RAM between cbmem_top and TOM: 0x800K |
| Available memory: 3141632K (3068M) |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| Done reading resources. |
| skipping PNP: 00ff.2@60 fixed resource, size=0! |
| skipping PNP: 00ff.2@62 fixed resource, size=0! |
| skipping PNP: 00ff.2@64 fixed resource, size=0! |
| skipping PNP: 00ff.2@66 fixed resource, size=0! |
| Setting resources... |
| DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem |
| DOMAIN: 0000 04 <- [0x00000c0000 - 0x00bfffffff] size 0xbff40000 gran 0x00 mem |
| DOMAIN: 0000 06 <- [0x00bfe00000 - 0x00bfffffff] size 0x00200000 gran 0x00 mem |
| DOMAIN: 0000 07 <- [0x00bfc00000 - 0x00bfdfffff] size 0x00200000 gran 0x00 mem |
| PCI: 00:01.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io |
| PCI: 00:01.0 24 <- [0x00e0000000 - 0x00e7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem |
| PCI: 00:01.0 20 <- [0x00ec100000 - 0x00ec1fffff] size 0x00100000 gran 0x14 bus 01 mem |
| PCI: 01:00.0 10 <- [0x00e0000000 - 0x00e7ffffff] size 0x08000000 gran 0x1b prefmem |
| PCI: 01:00.0 14 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io |
| PCI: 01:00.0 18 <- [0x00ec120000 - 0x00ec12ffff] size 0x00010000 gran 0x10 mem |
| PCI: 01:00.0 30 <- [0x00ec100000 - 0x00ec11ffff] size 0x00020000 gran 0x11 romem |
| PCI: 00:1b.0 10 <- [0x00ec300000 - 0x00ec303fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x0000005000 - 0x0000005fff] size 0x00001000 gran 0x0c bus 02 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.0 20 <- [0x00ec200000 - 0x00ec2fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 02:00.0 10 <- [0x00ec200000 - 0x00ec21ffff] size 0x00020000 gran 0x11 mem |
| PCI: 02:00.0 18 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.1 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem |
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io |
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 prefmem |
| PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 mem |
| PCI: 00:1d.0 20 <- [0x0000006000 - 0x000000601f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.1 20 <- [0x0000006020 - 0x000000603f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.2 20 <- [0x0000006040 - 0x000000605f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.3 20 <- [0x0000006060 - 0x000000607f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.7 10 <- [0x00ec304000 - 0x00ec3043ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 06 io |
| PCI: 00:1e.0 24 <- [0x00ea100000 - 0x00ec0fffff] size 0x02000000 gran 0x14 bus 06 prefmem |
| PCI: 00:1e.0 20 <- [0x00e8000000 - 0x00ea0fffff] size 0x02100000 gran 0x14 bus 06 mem |
| PCI: 06:00.0 10 <- [0x00ea000000 - 0x00ea000fff] size 0x00001000 gran 0x0c mem |
| PCI: 06:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io |
| PCI: 06:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io |
| PCI: 06:00.0 1c <- [0x00ea100000 - 0x00ec0fffff] size 0x02000000 gran 0x0c prefmem |
| PCI: 06:00.0 24 <- [0x00e8000000 - 0x00e9ffffff] size 0x02000000 gran 0x0c mem |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io |
| ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned |
| ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned |
| ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned |
| PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io |
| ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned |
| PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io |
| ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned |
| PNP: 002e.1 60 <- [0x00000003bc - 0x00000003c3] size 0x00000008 gran 0x03 io |
| PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq |
| ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned |
| PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io |
| ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned |
| PCI: 00:1f.1 10 <- [0x00000060b0 - 0x00000060b7] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.1 14 <- [0x00000060d0 - 0x00000060d3] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.1 18 <- [0x00000060b8 - 0x00000060bf] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.1 1c <- [0x00000060d4 - 0x00000060d7] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.1 20 <- [0x00000060a0 - 0x00000060af] size 0x00000010 gran 0x04 io |
| PCI: 00:1f.2 10 <- [0x00000060c0 - 0x00000060c7] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x00000060d8 - 0x00000060db] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x00000060c8 - 0x00000060cf] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x00000060dc - 0x00000060df] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000006080 - 0x000000609f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00ec305000 - 0x00ec3053ff] size 0x00000400 gran 0x0a mem |
| Done setting resources. |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 17aa/2015 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:01.0 bridge ctrl <- 001b |
| PCI: 00:01.0 cmd <- 07 |
| PCI: 00:1b.0 subsystem <- 17aa/2010 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0013 |
| PCI: 00:1c.0 subsystem <- 17aa/2001 |
| PCI: 00:1c.0 cmd <- 107 |
| PCI: 00:1c.1 bridge ctrl <- 0013 |
| PCI: 00:1c.1 subsystem <- 8086/27d2 |
| PCI: 00:1c.1 cmd <- 100 |
| PCI: 00:1c.2 bridge ctrl <- 0013 |
| PCI: 00:1c.2 subsystem <- 8086/27d4 |
| PCI: 00:1c.2 cmd <- 100 |
| PCI: 00:1c.3 bridge ctrl <- 0013 |
| PCI: 00:1c.3 subsystem <- 8086/27d6 |
| PCI: 00:1c.3 cmd <- 100 |
| PCI: 00:1d.0 subsystem <- 17aa/200a |
| PCI: 00:1d.0 cmd <- 01 |
| PCI: 00:1d.1 subsystem <- 17aa/200a |
| PCI: 00:1d.1 cmd <- 01 |
| PCI: 00:1d.2 subsystem <- 17aa/200a |
| PCI: 00:1d.2 cmd <- 01 |
| PCI: 00:1d.3 subsystem <- 17aa/200a |
| PCI: 00:1d.3 cmd <- 01 |
| PCI: 00:1d.7 subsystem <- 17aa/200b |
| PCI: 00:1d.7 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0013 |
| PCI: 00:1e.0 subsystem <- 8086/2448 |
| PCI: 00:1e.0 cmd <- 107 |
| PCI: 00:1f.0 subsystem <- 8086/27b9 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.1 subsystem <- 17aa/200c |
| PCI: 00:1f.1 cmd <- 01 |
| PCI: 00:1f.2 subsystem <- 17aa/200d |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 8086/27da |
| PCI: 00:1f.3 cmd <- 101 |
| PCI: 01:00.0 subsystem <- 17aa/20a4 |
| PCI: 01:00.0 cmd <- 03 |
| PCI: 02:00.0 cmd <- 03 |
| PCI: 06:00.0 bridge ctrl <- 0143 |
| PCI: 06:00.0 subsystem <- 17aa/2012 |
| PCI: 06:00.0 cmd <- 03 |
| done. |
| Initializing devices... |
| Root Device init |
| Root Device init finished in 0 msecs |
| CPU_CLUSTER: 0 init |
| FMAP: area COREBOOT found @ 200 (2096640 bytes) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset c340 size 15000 |
| microcode: sig=0x6f2 pf=0x20 revision=0x0 |
| microcode: updated to revision 0x5c date=2010-10-02 |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x00000000bfc00000 size 0xbfb40000 type 6 |
| 0x00000000bfc00000 - 0x00000000e0000000 size 0x20400000 type 0 |
| 0x00000000e0000000 - 0x00000000e8000000 size 0x08000000 type 1 |
| 0x00000000e8000000 - 0x0000000100000000 size 0x18000000 type 0 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 5/4. |
| MTRR: UC selected as default type. |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| MTRR: 1 base 0x0000000080000000 mask 0x0000000fc0000000 type 6 |
| MTRR: 2 base 0x00000000bfc00000 mask 0x0000000fffc00000 type 0 |
| MTRR: 3 base 0x00000000e0000000 mask 0x0000000ff8000000 type 1 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| CPU has 2 cores. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| CPU: Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz. |
| Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 1 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...done. |
| Waiting for 2nd SIPI to complete...done. |
| AP: slot 1 apic_id 1. |
| Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 0x00038000. Will call 0xbfbb101d(0x00000000) |
| Installing SMM handler to 0xbfe00000 |
| Loading module at 0xbfe10000 with entry 0xbfe1064b. filesize: 0x1690 memsize: 0x56e8 |
| Processing 70 relocs. Offset value of 0xbfe10000 |
| Loading module at 0xbfe08000 with entry 0xbfe08000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0xbfe08000 |
| SMM Module: placing jmp sequence at 0xbfe07c00 rel16 0x03fd |
| SMM Module: stub loaded at 0xbfe08000. Will call 0xbfe1064b(0x00000000) |
| Initializing Southbridge SMI... |
| |
| New SMBASE 0xbfe00000 |
| In relocation handler: cpu 0 |
| New SMBASE=0xbfe00000 |
| Relocation complete. |
| VMX status: enabled |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| IA32_FEATURE_CONTROL status: locked |
| New SMBASE 0xbfdffc00 |
| In relocation handler: cpu 1 |
| New SMBASE=0xbfdffc00 |
| Relocation complete. |
| Initializing CPU #0 |
| CPU: vendor Intel device 6f2 |
| CPU: family 06, model 0f, stepping 02 |
| Enabling cache |
| CPU: Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz. |
| Setting up local APIC... |
| apic_id: 0x00 done. |
| CPU #0 initialized |
| Initializing CPU #1 |
| CPU: vendor Intel device 6f2 |
| CPU: family 06, model 0f, stepping 02 |
| Enabling cache |
| CPU: Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz. |
| Setting up local APIC... |
| apic_id: 0x01 done. |
| CPU #1 initialized |
| bsp_do_flight_plan done after 4 msecs. |
| CPU 1 going down... |
| Initializing southbridge SMI... |
| SMI_STS: |
| GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO1 GPIO0 |
| ALT_GP_SMI_STS: GPI15 GPI14 GPI12 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| Locking SMM. |
| CPU_CLUSTER: 0 init finished in 19 msecs |
| PCI: 00:1b.0 init |
| Azalia: codec type: Azalia |
| Azalia: base = ec300000 |
| Azalia: codec_mask = 03 |
| Azalia: Initializing codec #1 |
| Azalia: codec viddid: 14f12bfa |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 11d41981 |
| Azalia: verb_size: 44 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 4 msecs |
| PCI: 00:1c.0 init |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.0 init finished in 0 msecs |
| PCI: 00:1c.1 init |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.1 init finished in 0 msecs |
| PCI: 00:1c.2 init |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.2 init finished in 0 msecs |
| PCI: 00:1c.3 init |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.3 init finished in 0 msecs |
| PCI: 00:1d.0 init |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 0 msecs |
| PCI: 00:1d.1 init |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.1 init finished in 0 msecs |
| PCI: 00:1d.2 init |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.2 init finished in 0 msecs |
| PCI: 00:1d.3 init |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.3 init finished in 0 msecs |
| PCI: 00:1d.7 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.7 init finished in 0 msecs |
| PCI: 00:1e.0 init |
| PCI: 00:1e.0 init finished in 0 msecs |
| PCI: 00:1f.0 init |
| i82801gx: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| No CMOS option 'power_on_after_fail'. |
| Set power on after power failure. |
| NMI sources enabled. |
| rtc_failed = 0x0 |
| S3 wakeup, enabling ACPI via APMC |
| PCI: 00:1f.0 init finished in 1 msecs |
| PCI: 00:1f.1 init |
| i82801gx_ide: initializing... IDE0 |
| PCI: 00:1f.1 init finished in 0 msecs |
| PCI: 00:1f.2 init |
| i82801gx_sata: initializing... |
| SATA controller in AHCI mode. |
| PCI: 00:1f.2 init finished in 0 msecs |
| PCI: 01:00.0 init |
| PCI: 01:00.0 init finished in 0 msecs |
| PCI: 02:00.0 init |
| PCI: 02:00.0 init finished in 0 msecs |
| PCI: 06:00.0 init |
| Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller |
| PCI: 06:00.0 init finished in 0 msecs |
| PNP: 00ff.2 init |
| PNP: 00ff.2 init finished in 0 msecs |
| PNP: 164e.2 init |
| PNP: 164e.2 init finished in 0 msecs |
| PNP: 164e.7 init |
| PNP: 164e.7 init finished in 0 msecs |
| PNP: 164e.19 init |
| PNP: 164e.19 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:69 init |
| Changing 12 of the 12 ck505 config bytes. |
| I2C: 01:69 init finished in 26 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| I2C: 01:54 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| I2C: 01:55 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| I2C: 01:56 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| I2C: 01:57 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 21 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| I2C: 01:5d init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| I2C: 01:5e init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| I2C: 01:5f init finished in 0 msecs |
| Devices initialized |
| BS: BS_DEV_INIT run times (exec / console): 75 / 0 ms |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Manufacturer: c2 |
| SF: Detected MX25L1605D with sector size 0x1000, total 0x200000 |
| Devices finalized |
| Trying to find the wakeup vector... |
| Looking on 0x000f68d0 for valid checksum |
| Checksum 1 passed |
| Checksum 2 passed all OK |
| RSDP found at 0x000f68d0 |
| RSDT found at 0xbfb61030 ends at 0xbfb6106c |
| FADT found at 0xbfb644e0 |
| FACS found at 0xbfb61240 |
| OS waking vector is 0x0009c080 |
| Restore GNVS pointer to 0xbfbfea20 |
| |