| 2C: 01:5f enabled |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 31 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 6640 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 6652 usecs |
| done |
| FMAP: area RW_MRC_CACHE found @ 710000 (65536 bytes) |
| MRC: No data in cbmem for 'RW_MRC_CACHE'. |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 6820 exit 6 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PCI: 00:1a.0 EHCI BAR hook registered |
| PCI: 00:1c.0 read_resources bus 1 link: 0 |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.1 read_resources bus 2 link: 0 |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| PCI: 00:1c.3 read_resources bus 3 link: 0 |
| PCI: 00:1c.3 read_resources bus 3 link: 0 done |
| More than one caller of pci_ehci_read_resources from PCI: 00:1d.0 |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| PCI: 00:1f.3 read_resources bus 1 link: 0 |
| PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.4 |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 01:00.0 |
| PCI: 01:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.2 |
| PCI: 00:1c.1 child on link 0 NONE |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| NONE |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 |
| NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 |
| PCI: 00:1c.3 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PNP: 00ff.f |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:19.0 18 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 20 * [0x1060 - 0x107f] io |
| PCI: 00:1f.2 10 * [0x1080 - 0x1087] io |
| PCI: 00:1f.2 18 * [0x1088 - 0x108f] io |
| PCI: 00:1f.2 14 * [0x1090 - 0x1093] io |
| PCI: 00:1f.2 1c * [0x1094 - 0x1097] io |
| DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 01:00.0 10 * [0x0 - 0x1fff] mem |
| PCI: 00:1c.0 mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.1 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 00:1c.1 mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 03:00.0 10 * [0x0 - 0xff] mem |
| PCI: 00:1c.3 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:1c.1 24 * [0x10000000 - 0x107fffff] prefmem |
| PCI: 00:1c.1 20 * [0x10800000 - 0x10ffffff] mem |
| PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem |
| PCI: 00:1c.0 20 * [0x11400000 - 0x114fffff] mem |
| PCI: 00:1c.3 20 * [0x11500000 - 0x115fffff] mem |
| PCI: 00:19.0 10 * [0x11600000 - 0x1161ffff] mem |
| PCI: 00:04.0 10 * [0x11620000 - 0x11627fff] mem |
| PCI: 00:1b.0 10 * [0x11628000 - 0x1162bfff] mem |
| PCI: 00:19.0 14 * [0x1162c000 - 0x1162cfff] mem |
| PCI: 00:1f.6 10 * [0x1162d000 - 0x1162dfff] mem |
| PCI: 00:1f.2 24 * [0x1162e000 - 0x1162e7ff] mem |
| PCI: 00:1a.0 10 * [0x1162f000 - 0x1162f3ff] mem |
| PCI: 00:1d.0 10 * [0x11630000 - 0x116303ff] mem |
| PCI: 00:1f.3 10 * [0x11631000 - 0x116310ff] mem |
| DOMAIN: 0000 mem: base: 11631100 size: 11631100 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| skipping PNP: 00ff.2@60 fixed resource, size=0! |
| skipping PNP: 00ff.2@62 fixed resource, size=0! |
| skipping PNP: 00ff.2@64 fixed resource, size=0! |
| skipping PNP: 00ff.2@66 fixed resource, size=0! |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:167c size:1098 align:12 gran:0 limit:ffff |
| PCI: 00:1c.1 1c * [0x2000 - 0x2fff] io |
| PCI: 00:02.0 20 * [0x3000 - 0x303f] io |
| PCI: 00:19.0 18 * [0x3040 - 0x305f] io |
| PCI: 00:1f.2 20 * [0x3060 - 0x307f] io |
| PCI: 00:1f.2 10 * [0x3080 - 0x3087] io |
| PCI: 00:1f.2 18 * [0x3088 - 0x308f] io |
| PCI: 00:1f.2 14 * [0x3090 - 0x3093] io |
| PCI: 00:1f.2 1c * [0x3094 - 0x3097] io |
| DOMAIN: 0000 io: next_base: 3098 size: 1098 align: 12 gran: 0 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.1 io: base:2000 size:1000 align:12 gran:12 limit:2fff |
| NONE 18 * [0x2000 - 0x2fff] io |
| PCI: 00:1c.1 io: next_base: 3000 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1c.3 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.3 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:d0000000 size:11631100 align:28 gran:0 limit:efffffff |
| PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem |
| PCI: 00:1c.1 24 * [0xe0000000 - 0xe07fffff] prefmem |
| PCI: 00:1c.1 20 * [0xe0800000 - 0xe0ffffff] mem |
| PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem |
| PCI: 00:1c.0 20 * [0xe1400000 - 0xe14fffff] mem |
| PCI: 00:1c.3 20 * [0xe1500000 - 0xe15fffff] mem |
| PCI: 00:19.0 10 * [0xe1600000 - 0xe161ffff] mem |
| PCI: 00:04.0 10 * [0xe1620000 - 0xe1627fff] mem |
| PCI: 00:1b.0 10 * [0xe1628000 - 0xe162bfff] mem |
| PCI: 00:19.0 14 * [0xe162c000 - 0xe162cfff] mem |
| PCI: 00:1f.6 10 * [0xe162d000 - 0xe162dfff] mem |
| PCI: 00:1f.2 24 * [0xe162e000 - 0xe162e7ff] mem |
| PCI: 00:1a.0 10 * [0xe162f000 - 0xe162f3ff] mem |
| PCI: 00:1d.0 10 * [0xe1630000 - 0xe16303ff] mem |
| PCI: 00:1f.3 10 * [0xe1631000 - 0xe16310ff] mem |
| DOMAIN: 0000 mem: next_base: e1631100 size: 11631100 align: 28 gran: 0 done |
| PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:e1400000 size:100000 align:20 gran:20 limit:e14fffff |
| PCI: 01:00.0 10 * [0xe1400000 - 0xe1401fff] mem |
| PCI: 00:1c.0 mem: next_base: e1402000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.1 prefmem: base:e0000000 size:800000 align:22 gran:20 limit:e07fffff |
| NONE 14 * [0xe0000000 - 0xe07fffff] prefmem |
| PCI: 00:1c.1 prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done |
| PCI: 00:1c.1 mem: base:e0800000 size:800000 align:22 gran:20 limit:e0ffffff |
| NONE 10 * [0xe0800000 - 0xe0ffffff] mem |
| PCI: 00:1c.1 mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done |
| PCI: 00:1c.3 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.3 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.3 mem: base:e1500000 size:100000 align:20 gran:20 limit:e15fffff |
| PCI: 03:00.0 10 * [0xe1500000 - 0xe15000ff] mem |
| PCI: 00:1c.3 mem: next_base: e1500100 size: 100000 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x27b600000 TOLUD 0x82a00000 TOM 0x200000000 |
| MEBASE 0x1fe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 6070M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x00e1620000 - 0x00e1627fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:19.0 10 <- [0x00e1600000 - 0x00e161ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00e162c000 - 0x00e162cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 EHCI Debug Port hook triggered |
| PCI: 00:1a.0 10 <- [0x00e162f000 - 0x00e162f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 10 <- [0x00e162f000 - 0x00e162f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 EHCI Debug Port relocated |
| PCI: 00:1b.0 10 <- [0x00e1628000 - 0x00e162bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 bus 01 mem |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 |
| PCI: 01:00.0 10 <- [0x00e1400000 - 0x00e1401fff] size 0x00002000 gran 0x0d mem64 |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 |
| PCI: 00:1c.1 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 02 mem |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| NONE missing set_resources |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.3 20 <- [0x00e1500000 - 0x00e15fffff] size 0x00100000 gran 0x14 bus 03 mem |
| PCI: 00:1c.3 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x00e1500000 - 0x00e15000ff] size 0x00000100 gran 0x08 mem |
| PCI: 00:1c.3 assign_resources, bus 3 link: 0 |
| PCI: 00:1d.0 10 <- [0x00e1630000 - 0x00e16303ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00e162e000 - 0x00e162e7ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00e1631000 - 0x00e16310ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.6 10 <- [0x00e162d000 - 0x00e162dfff] size 0x00001000 gran 0x0c mem64 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 167c size 1098 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base d0000000 size 11631100 align 28 gran 0 limit efffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 17b600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit e13fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base e1620000 size 8000 align 15 gran 15 limit e1627fff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base e1600000 size 20000 align 17 gran 17 limit e161ffff flags 60000200 index 10 |
| PCI: 00:19.0 resource base e162c000 size 1000 align 12 gran 12 limit e162cfff flags 60000200 index 14 |
| PCI: 00:19.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base e162f000 size 400 align 12 gran 10 limit e162f3ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base e1628000 size 4000 align 14 gran 14 limit e162bfff flags 60000201 index 10 |
| PCI: 00:1c.4 |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base e1400000 size 100000 align 20 gran 20 limit e14fffff flags 60080202 index 20 |
| PCI: 01:00.0 |
| PCI: 01:00.0 resource base e1400000 size 2000 align 13 gran 13 limit e1401fff flags 60000201 index 10 |
| PCI: 00:1c.2 |
| PCI: 00:1c.1 child on link 0 NONE |
| PCI: 00:1c.1 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c |
| PCI: 00:1c.1 resource base e0000000 size 800000 align 22 gran 20 limit e07fffff flags 60081202 index 24 |
| PCI: 00:1c.1 resource base e0800000 size 800000 align 22 gran 20 limit e0ffffff flags 60080202 index 20 |
| NONE |
| NONE resource base e0800000 size 800000 align 22 gran 22 limit e0ffffff flags 40000200 index 10 |
| NONE resource base e0000000 size 800000 align 22 gran 22 limit e07fffff flags 40001200 index 14 |
| NONE resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18 |
| PCI: 00:1c.3 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.3 resource base e1500000 size 100000 align 20 gran 20 limit e15fffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base e1500000 size 100 align 12 gran 8 limit e15000ff flags 60000200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base e1630000 size 400 align 12 gran 10 limit e16303ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PNP: 00ff.f |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base e162e000 size 800 align 12 gran 11 limit e162e7ff flags 60000200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base e1631000 size 100 align 12 gran 8 limit e16310ff flags 60000201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| PCI: 00:1f.6 resource base e162d000 size 1000 align 12 gran 12 limit e162dfff flags 60000201 index 10 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2743 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 17aa/21ce |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 17aa/21ce |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:19.0 subsystem <- 17aa/21ce |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 17aa/21ce |
| PCI: 00:1a.0 cmd <- 106 |
| PCI: 00:1b.0 subsystem <- 17aa/21ce |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 17aa/21ce |
| PCI: 00:1c.0 cmd <- 106 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 17aa/21ce |
| PCI: 00:1c.1 cmd <- 107 |
| PCI: 00:1c.3 bridge ctrl <- 0003 |
| PCI: 00:1c.3 subsystem <- 17aa/21ce |
| PCI: 00:1c.3 cmd <- 106 |
| PCI: 00:1d.0 subsystem <- 17aa/21ce |
| PCI: 00:1d.0 cmd <- 102 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 17aa/21ce |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 17aa/21ce |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 17aa/21ce |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 00:1f.6 subsystem <- 17aa/21ce |
| PCI: 00:1f.6 cmd <- 02 |
| PCI: 01:00.0 cmd <- 02 |
| PCI: 03:00.0 subsystem <- 17aa/21ce |
| PCI: 03:00.0 cmd <- 06 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 184 exit 0 |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=0, nvlocked=1 |
| TPM: setup succeeded |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 1 usecs |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 7ffa28ac(7ffc9b20) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 8001048b. filesize: 0x1b90 memsize: 0x5bb8 |
| Processing 60 relocs. Offset value of 0x80010000 |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x80008000 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at 80006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd |
| SMM Module: stub loaded at 80008000. Will call 8001048b(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: MCSMI PM1 |
| PM1_STS: PRBTNOR PWRBTN TMROF |
| PM1_EN: 0 |
| GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 TCO_SCI |
| ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000027b600000 size 0x17b600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/4. |
| MTRR: UC selected as default type. |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6 |
| MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x00 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 4 cores, 2 threads per core |
| CPU: 0 has core 1 |
| CPU1: stack_base 7ffc0000, stack_end 7ffc0ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| CPU: 0 has core 2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x01 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #1 initialized |
| CPU2: stack_base 7ffbf000, stack_end 7ffbfff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x02 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #2 initialized |
| CPU3: stack_base 7ffbe000, stack_end 7ffbeff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 4 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x03 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #3 initialized |
| CPU4: stack_base 7ffbd000, stack_end 7ffbdff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 4. |
| After apic_write. |
| In relocation handler: cpu 4 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 4. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 5 |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x04 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #4 initialized |
| CPU5: stack_base 7ffbc000, stack_end 7ffbcff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 5. |
| After apic_write. |
| In relocation handler: cpu 5 |
| New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 5. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 6 |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x05 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #5 initialized |
| CPU6: stack_base 7ffbb000, stack_end 7ffbbff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 6. |
| After apic_write. |
| In relocation handler: cpu 6 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 6. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x06 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #6 initialized |
| CPU7: stack_base 7ffba000, stack_end 7ffbaff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 7. |
| After apic_write. |
| In relocation handler: cpu 7 |
| New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 7. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #7 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x07 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #7 initialized |
| All AP CPUs stopped (602 loops) |
| CPU0: stack: 7ffc1000 - 7ffc2000, lowest used address 7ffc1aac, stack used: 1364 bytes |
| CPU1: stack: 7ffc0000 - 7ffc1000, lowest used address 7ffc0c40, stack used: 960 bytes |
| CPU2: stack: 7ffbf000 - 7ffc0000, lowest used address 7ffbfc40, stack used: 960 bytes |
| CPU3: stack: 7ffbe000 - 7ffbf000, lowest used address 7ffbec40, stack used: 960 bytes |
| CPU4: stack: 7ffbd000 - 7ffbe000, lowest used address 7ffbdc40, stack used: 960 bytes |
| CPU5: stack: 7ffbc000 - 7ffbd000, lowest used address 7ffbcc40, stack used: 960 bytes |
| CPU6: stack: 7ffbb000 - 7ffbc000, lowest used address 7ffbbc40, stack used: 960 bytes |
| CPU7: stack: 7ffba000 - 7ffbb000, lowest used address 7ffbac40, stack used: 960 bytes |
| CPU_CLUSTER: 0 init finished in 190450 usecs |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG10. |
| Disabling PEG60. |
| Disabling Device 7. |
| Disabling PEG IO clock. |
| Set BIOS_RESET_CPL |
| CPU TDP: 35 Watts |
| PCI: 00:00.0 init finished in 1019 usecs |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 25W-35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| PCI: 00:02.0 init finished in 162 usecs |
| PCI: 00:04.0 init ... |
| PCI: 00:04.0 init finished in 0 usecs |
| PCI: 00:19.0 init ... |
| PCI: 00:19.0 init finished in 0 usecs |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 14 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: base = e1628000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862805 |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 14f1506e |
| Azalia: verb_size: 52 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 4308 usecs |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 11 usecs |
| PCI: 00:1c.1 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 15 usecs |
| PCI: 00:1c.3 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.3 init finished in 11 usecs |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 14 usecs |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| PCH: detected QM67, device id: 0x1c4f, rev id 0x5 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| Set power off after power failure. |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| NMI sources enabled. |
| CougarPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 935 usecs |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| SATA: Controller in AHCI mode. |
| ABAR: e162e000 |
| PCI: 00:1f.2 init finished in 360 usecs |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| PCI: 00:1f.6 init ... |
| PCI: 00:1f.6 init finished in 0 usecs |
| PCI: 01:00.0 init ... |
| PCI: 01:00.0 init finished in 0 usecs |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 15 usecs |
| PNP: 00ff.2 init ... |
| PNP: 00ff.2 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ... |
| I2C: 01:54 init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ... |
| I2C: 01:55 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ... |
| I2C: 01:56 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ... |
| I2C: 01:57 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ... |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 26018 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ... |
| I2C: 01:5d init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ... |
| I2C: 01:5e init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ... |
| I2C: 01:5f init finished in 1 usecs |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 0 |
| I2C: 01:54: enabled 1 |
| I2C: 01:55: enabled 1 |
| I2C: 01:56: enabled 1 |
| I2C: 01:57: enabled 1 |
| I2C: 01:5c: enabled 1 |
| I2C: 01:5d: enabled 1 |
| I2C: 01:5e: enabled 1 |
| I2C: 01:5f: enabled 1 |
| PCI: 00:04.0: enabled 1 |
| PCI: 01:00.0: enabled 1 |
| NONE: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 15021 run 223561 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 49 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 3ac80 size 3875 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff46000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| Generating ACPI PIRQ entries |
| ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:04.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=1 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=2 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=7 |
| ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=0 |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: * H8 |
| H8: BDC installed |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| \_SB.PCI0.RP01.WIFI: PCI: 01:00.0 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 7ff35000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff4caa0 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Found @ offset 35a00 size 558 |
| Found a VBT of 3985 bytes after decompression |
| GMA: Found VBT in CBFS |
| GMA: Found valid VBT in CBFS |
| ACPI: * HPET |
| ACPI: added table 6/32, length now 60 |
| ACPI: done. |
| ACPI tables: 35552 bytes. |
| smbios_write_tables: 7ff34000 |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x30 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x14 |
| recv_ec_data: 0x03 |
| Create SMBIOS type 17 |
| PCI: 01:00.0 (unknown) |
| SMBIOS tables: 669 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum dfe7 |
| Writing coreboot table at 0x7ff6a000 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff33fff: RAM |
| 4. 000000007ff34000-000000007ff82fff: CONFIGURATION TABLES |
| 5. 000000007ff83000-000000007ffcdfff: RAMSTAGE |
| 6. 000000007ffce000-000000007fffffff: CONFIGURATION TABLES |
| 7. 0000000080000000-00000000829fffff: RESERVED |
| 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| 9. 00000000fed40000-00000000fed44fff: RESERVED |
| 10. 0000000100000000-000000027b5fffff: RAM |
| Manufacturer: ef |
| SF: Detected W25Q64 with sector size 0x1000, total 0x800000 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| Wrote coreboot table at: 7ff6a000, 0xb0c bytes, checksum 47 |
| coreboot table: 2852 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| TIME STAMP 3. 7ffdd000 00000910 |
| ROMSTG STCK 4. 7ffd8000 00005000 |
| AFTER CAR 5. 7ffce000 0000a000 |
| RAMSTAGE 6. 7ff82000 0004c000 |
| SMM BACKUP 7. 7ff72000 00010000 |
| COREBOOT 8. 7ff6a000 00008000 |
| ACPI 9. 7ff46000 00024000 |
| ACPI GNVS 10. 7ff45000 00001000 |
| TCPA TCGLOG11. 7ff35000 00010000 |
| SMBIOS 12. 7ff34000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| USBDEBUG 1. 7fffeba0 00000058 |
| MEM INFO 2. 7fffea40 00000149 |
| ROMSTAGE 3. 7fffea20 00000004 |
| COREBOOTFWD 4. 7fffe9e0 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 26768 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 3e540 size 6399c |
| Loading segment from ROM address 0xfff5e578 |
| code (compression=1) |
| New segment dstaddr 0x8200 memsize 0x1b988 srcaddr 0xfff5e5cc filesize 0x99fd |
| Loading segment from ROM address 0xfff5e594 |
| code (compression=1) |
| New segment dstaddr 0x100000 memsize 0x125694 srcaddr 0xfff67fc9 filesize 0x59f4b |
| Loading segment from ROM address 0xfff5e5b0 |
| Entry Point 0x00008200 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000001b988 filesz: 0x00000000000099fd |
| lb: [0x000000007ff83000, 0x000000007ffcdc58) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x000000000001b988 filesz: 0x00000000000099fd |
| using LZMA |
| [ 0x00008200, 0001c143, 0x00023b88) <- fff5e5cc |
| Clearing Segment: addr: 0x000000000001c143 memsz: 0x0000000000007a45 |
| dest 00008200, end 00023b88, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000125694 filesz: 0x0000000000059f4b |
| lb: [0x000000007ff83000, 0x000000007ffcdc58) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000125694 filesz: 0x0000000000059f4b |
| using LZMA |
| [ 0x00100000, 00225694, 0x00225694) <- fff67fc9 |
| dest 00100000, end 00225694, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 196994 exit 0 |
| PCH: watchdog disabled |
| Jumping to boot code at 00008200(7ff6a000) |
| CPU0: stack: 7ffc1000 - 7ffc2000, lowest used address 7ffc1aac, stack used: 1364 bytes |
| error: no suitable video mode found. |
|
error: file `/boot/grub/i386-coreboot/jpeg.mod' not found. |
|
error: file `/boot/grub/i386-coreboot/gfxterm_background.mod' not found. |
|
error: file `/dejavusansmono.pf2' not found. |
|
error: file `/boot/grub/layouts/usqwerty.gkb' not found. |
|
GNU GRUB version 2.02 |
|
|
|
+----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
|
Press enter to boot the selected OS, `e' to edit the commands |
|
before booting or `c' for a command-line. *Load Operating System (incl. fully encrypted disks) [o] ? Search ISOLINUX menu (AHCI) [a] ? Search ISOLINUX menu (USB) [u] ? Search ISOLINUX menu (CD/DVD) [d] ? Load test configuration (grubtest.cfg) inside of CBFS [t] ? Search for GRUB2 configuration on external media [s] ? Poweroff [p] ? Reboot [r] ? ? ? ? ? The highlighted entry will be executed automatically in 1s. The highlighted entry will be executed automatically in 0s. Booting `Load Operating System (incl. fully encrypted disks) [o]' |
|
|
|
error: file `/boot/grub/fonts/unicode.pf2' not found. |
|
error: no suitable video mode found. |
|
GNU GRUB version 2.02 |
|
|
|
+----------------------------------------------------------------------------+||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
|
Press enter to boot the selected OS, `e' to edit the commands |
|
before booting or `c' for a command-line. ESC to return |
|
previous menu. *Gentoo GNU/Linux ? Advanced options for Gentoo GNU/Linux ? ? ? ? ? ? ? ? ? ? The highlighted entry will be executed automatically in 5s. The highlighted entry will be executed automatically in 4s. The highlighted entry will be executed automatically in 3s. The highlighted entry will be executed automatically in 2s. The highlighted entry will be executed automatically in 1s. The highlighted entry will be executed automatically in 0s. Booting `Gentoo GNU/Linux' |
|
|
|
error: file `/boot/grub/i386-coreboot/all_video.mod' not found. |
|
Loading Linux 4.14.63-gentoo-r1 ... |
|
Loading initial ramdisk ... |
|
|
|
Press any key to continue... |
|
|
| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| : 28T |
| Selected tWR : 12T |
| Selected tFAW : 24T |
| Selected tRRD : 5T |
| Selected tRTP : 6T |
| Selected tWTR : 6T |
| Selected tRFC : 128T |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 2 |
| PCI(0, 0, 0)[bc] = 82a00000 |
| PCI(0, 0, 0)[a8] = 7b600000 |
| PCI(0, 0, 0)[ac] = 2 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| PCI(0, 0, 0)[7c] = 7f |
| PCI(0, 0, 0)[70] = fe000000 |
| PCI(0, 0, 0)[74] = 1 |
| PCI(0, 0, 0)[78] = fe000c00 |
| Done memory map |
| Done io registers |
| Done jedec reset |
| Done MRS commands |
| t123: 1767, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : 0x4e |
| ME: FWS2: 0x164e0002 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x4e |
| ME: Current PM event: 0x6 |
| ME: Progress code : 0x1 |
| Waited long enough, or CPU was not replaced, continue... |
| PASSED! Tell ME that DRAM is ready |
| ME: FWS2: 0x162c0002 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x2c |
| ME: Current PM event: 0x6 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: Continue to boot |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : 0x2c |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1596 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00620010): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 4096 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00620010): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 4096 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ 7ffff000 254 entries. |
| IMD: root @ 7fffec00 62 entries. |
| External stage cache: |
| IMD: root @ 803ff000 254 entries. |
| IMD: root @ 803fec00 62 entries. |
| CBMEM entry for DIMM info: 0x7fffea40 |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Found @ offset 35380 size 4470 |
| Decompressing stage fallback/postcar @ 0x7ffcdfc0 (34160 bytes) |
| Loading module at 7ffce000 with entry 7ffce000. filesize: 0x4210 memsize: 0x8530 |
| Processing 129 relocs. Offset value of 0x7dfce000 |
| |
| |
| coreboot-4.8-1420-g401f8c59bd Thu Sep 6 16:31:10 UTC 2018 postcar starting... |
| usbdebug: Failed hardware init |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 1ac40 size 193c4 |
| Decompressing stage fallback/ramstage @ 0x7ff82fc0 (301976 bytes) |
| Loading module at 7ff83000 with entry 7ff83000. filesize: 0x35290 memsize: 0x49b58 |
| Processing 3513 relocs. Offset value of 0x7fe83000 |
| |
| |
| coreboot-4.8-1420-g401f8c59bd Thu Sep 6 16:31:10 UTC 2018 ramstage starting... |
| Capability: type 0x01 @ 0x50 |
| Capability: type 0x01 @ 0x50 |
| Capability: type 0x0a @ 0x58 |
| usbdebug: Failed hardware init |
| Normal boot. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 0 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 0 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/0154] ops |
| PCI: 00:00.0 [8086/0154] enabled |
| PCI: Static device PCI: 00:01.0 not found, disabling it. |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0166] enabled |
| PCI: 00:04.0 [8086/0153] enabled |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 [8086/1c3a] ops |
| PCI: 00:16.0 [8086/1c3a] disabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0 [8086/1502] enabled |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1c2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1c20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0: Disabling device |
| PCI: 00:1c.0: check set enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1c10] disabled |
| PCH: Remap PCIe function 1 to 0 |
| PCI: 00:1c.1 [8086/0000] bus ops |
| PCI: 00:1c.1 [8086/1c12] enabled |
| PCI: 00:1c.2: Disabling device |
| PCI: 00:1c.2 [8086/0000] bus ops |
| PCI: 00:1c.2 [8086/1c14] disabled |
| PCH: Remap PCIe function 3 to 0 |
| PCI: 00:1c.3 [8086/0000] bus ops |
| PCI: 00:1c.3 [8086/1c16] enabled |
| PCH: Remap PCIe function 4 to 0 |
| PCI: 00:1c.4 [8086/0000] bus ops |
| PCI: 00:1c.4 [8086/1c18] enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfed31a0c |
| PCH: PCIe map 1c.0 -> 1c.4 |
| PCH: PCIe map 1c.1 -> 1c.0 |
| PCH: PCIe map 1c.3 -> 1c.1 |
| PCH: PCIe map 1c.4 -> 1c.3 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1c26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1e.0 [8086/2448] bus ops |
| PCI: 00:1e.0 [8086/2448] disabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1c4f] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| PCI: 00:1f.2 [8086/1c01] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1c22] enabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1c09] disabled No operations |
| PCI: 00:1f.6 [8086/1c24] enabled |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| PCI: pci_scan_bus for bus 01 |
| PCI: 01:00.0 [8086/0000] ops |
| PCI: 01:00.0 [8086/0085] enabled |
| Capability: type 0x01 @ 0xc8 |
| Capability: type 0x05 @ 0xd0 |
| Capability: type 0x10 @ 0xe0 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| Capability: type 0x01 @ 0xc8 |
| Capability: type 0x05 @ 0xd0 |
| Capability: type 0x10 @ 0xe0 |
| Failed to enable LTR for dev = PCI: 01:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 332 usecs |
| PCI: 00:1c.1 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.1 |
| PCI: pci_scan_bus for bus 02 |
| scan_bus: scanning of bus PCI: 00:1c.1 took 54 usecs |
| PCI: 00:1c.3 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.3 |
| PCI: pci_scan_bus for bus 03 |
| PCI: 03:00.0 [1180/0000] ops |
| PCI: 03:00.0 [1180/e822] enabled |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 03:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.3 took 254 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| PMH7: ID 04 Revision 01 |
| PNP: 00ff.1 enabled |
| PNP: 0c31.0 enabled |
| Clearing EC output queue... |
| EC output queue has been cleared. |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x30 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x14 |
| recv_ec_data: 0x03 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x12 |
| EC Firmware ID 83HT30WW-3.20, Version 0.01C |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| No CMOS option 'low_battery_beep'. |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| recv_ec_data: 0x60 |
| recv_ec_data: 0x10 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| H8: BDC installed |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| recv_ec_data: 0x60 |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| recv_ec_data: 0x60 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| recv_ec_data: 0xa7 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| recv_ec_data: 0xa7 |
| recv_ec_data: 0x20 |
| PNP: 00ff.2 enabled |
| Hybrid graphics: Not installed |
| PNP: 00ff.f disabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 5308 usecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 32 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 6418 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 6430 usecs |
| done |
| FMAP: area RW_MRC_CACHE found @ 710000 (65536 bytes) |
| MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| Manufacturer: ef |
| SF: Detected W25Q64 with sector size 0x1000, total 0x800000 |
| MRC: no data in 'RW_MRC_CACHE' |
| MRC: cache data 'RW_MRC_CACHE' needs update. |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 6598 exit 5475 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PCI: 00:1a.0 EHCI BAR hook registered |
| PCI: 00:1c.0 read_resources bus 1 link: 0 |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.1 read_resources bus 2 link: 0 |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| PCI: 00:1c.3 read_resources bus 3 link: 0 |
| PCI: 00:1c.3 read_resources bus 3 link: 0 done |
| More than one caller of pci_ehci_read_resources from PCI: 00:1d.0 |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| PCI: 00:1f.3 read_resources bus 1 link: 0 |
| PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.4 |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 01:00.0 |
| PCI: 01:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.2 |
| PCI: 00:1c.1 child on link 0 NONE |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| NONE |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 |
| NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 |
| PCI: 00:1c.3 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PNP: 00ff.f |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 1c * [0x0 - 0xfff] io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] io |
| PCI: 00:19.0 18 * [0x1040 - 0x105f] io |
| PCI: 00:1f.2 20 * [0x1060 - 0x107f] io |
| PCI: 00:1f.2 10 * [0x1080 - 0x1087] io |
| PCI: 00:1f.2 18 * [0x1088 - 0x108f] io |
| PCI: 00:1f.2 14 * [0x1090 - 0x1093] io |
| PCI: 00:1f.2 1c * [0x1094 - 0x1097] io |
| DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 01:00.0 10 * [0x0 - 0x1fff] mem |
| PCI: 00:1c.0 mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.1 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 00:1c.1 mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 03:00.0 10 * [0x0 - 0xff] mem |
| PCI: 00:1c.3 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem |
| PCI: 00:1c.1 24 * [0x10000000 - 0x107fffff] prefmem |
| PCI: 00:1c.1 20 * [0x10800000 - 0x10ffffff] mem |
| PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem |
| PCI: 00:1c.0 20 * [0x11400000 - 0x114fffff] mem |
| PCI: 00:1c.3 20 * [0x11500000 - 0x115fffff] mem |
| PCI: 00:19.0 10 * [0x11600000 - 0x1161ffff] mem |
| PCI: 00:04.0 10 * [0x11620000 - 0x11627fff] mem |
| PCI: 00:1b.0 10 * [0x11628000 - 0x1162bfff] mem |
| PCI: 00:19.0 14 * [0x1162c000 - 0x1162cfff] mem |
| PCI: 00:1f.6 10 * [0x1162d000 - 0x1162dfff] mem |
| PCI: 00:1f.2 24 * [0x1162e000 - 0x1162e7ff] mem |
| PCI: 00:1a.0 10 * [0x1162f000 - 0x1162f3ff] mem |
| PCI: 00:1d.0 10 * [0x11630000 - 0x116303ff] mem |
| PCI: 00:1f.3 10 * [0x11631000 - 0x116310ff] mem |
| DOMAIN: 0000 mem: base: 11631100 size: 11631100 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| skipping PNP: 00ff.2@60 fixed resource, size=0! |
| skipping PNP: 00ff.2@62 fixed resource, size=0! |
| skipping PNP: 00ff.2@64 fixed resource, size=0! |
| skipping PNP: 00ff.2@66 fixed resource, size=0! |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:167c size:1098 align:12 gran:0 limit:ffff |
| PCI: 00:1c.1 1c * [0x2000 - 0x2fff] io |
| PCI: 00:02.0 20 * [0x3000 - 0x303f] io |
| PCI: 00:19.0 18 * [0x3040 - 0x305f] io |
| PCI: 00:1f.2 20 * [0x3060 - 0x307f] io |
| PCI: 00:1f.2 10 * [0x3080 - 0x3087] io |
| PCI: 00:1f.2 18 * [0x3088 - 0x308f] io |
| PCI: 00:1f.2 14 * [0x3090 - 0x3093] io |
| PCI: 00:1f.2 1c * [0x3094 - 0x3097] io |
| DOMAIN: 0000 io: next_base: 3098 size: 1098 align: 12 gran: 0 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.1 io: base:2000 size:1000 align:12 gran:12 limit:2fff |
| NONE 18 * [0x2000 - 0x2fff] io |
| PCI: 00:1c.1 io: next_base: 3000 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1c.3 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.3 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:d0000000 size:11631100 align:28 gran:0 limit:efffffff |
| PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem |
| PCI: 00:1c.1 24 * [0xe0000000 - 0xe07fffff] prefmem |
| PCI: 00:1c.1 20 * [0xe0800000 - 0xe0ffffff] mem |
| PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem |
| PCI: 00:1c.0 20 * [0xe1400000 - 0xe14fffff] mem |
| PCI: 00:1c.3 20 * [0xe1500000 - 0xe15fffff] mem |
| PCI: 00:19.0 10 * [0xe1600000 - 0xe161ffff] mem |
| PCI: 00:04.0 10 * [0xe1620000 - 0xe1627fff] mem |
| PCI: 00:1b.0 10 * [0xe1628000 - 0xe162bfff] mem |
| PCI: 00:19.0 14 * [0xe162c000 - 0xe162cfff] mem |
| PCI: 00:1f.6 10 * [0xe162d000 - 0xe162dfff] mem |
| PCI: 00:1f.2 24 * [0xe162e000 - 0xe162e7ff] mem |
| PCI: 00:1a.0 10 * [0xe162f000 - 0xe162f3ff] mem |
| PCI: 00:1d.0 10 * [0xe1630000 - 0xe16303ff] mem |
| PCI: 00:1f.3 10 * [0xe1631000 - 0xe16310ff] mem |
| DOMAIN: 0000 mem: next_base: e1631100 size: 11631100 align: 28 gran: 0 done |
| PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:e1400000 size:100000 align:20 gran:20 limit:e14fffff |
| PCI: 01:00.0 10 * [0xe1400000 - 0xe1401fff] mem |
| PCI: 00:1c.0 mem: next_base: e1402000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.1 prefmem: base:e0000000 size:800000 align:22 gran:20 limit:e07fffff |
| NONE 14 * [0xe0000000 - 0xe07fffff] prefmem |
| PCI: 00:1c.1 prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done |
| PCI: 00:1c.1 mem: base:e0800000 size:800000 align:22 gran:20 limit:e0ffffff |
| NONE 10 * [0xe0800000 - 0xe0ffffff] mem |
| PCI: 00:1c.1 mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done |
| PCI: 00:1c.3 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.3 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.3 mem: base:e1500000 size:100000 align:20 gran:20 limit:e15fffff |
| PCI: 03:00.0 10 * [0xe1500000 - 0xe15000ff] mem |
| PCI: 00:1c.3 mem: next_base: e1500100 size: 100000 align: 20 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x27b600000 TOLUD 0x82a00000 TOM 0x200000000 |
| MEBASE 0x1fe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 6070M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x00e1620000 - 0x00e1627fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:19.0 10 <- [0x00e1600000 - 0x00e161ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00e162c000 - 0x00e162cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 EHCI Debug Port hook triggered |
| PCI: 00:1a.0 10 <- [0x00e162f000 - 0x00e162f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 10 <- [0x00e162f000 - 0x00e162f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1a.0 EHCI Debug Port relocated |
| PCI: 00:1b.0 10 <- [0x00e1628000 - 0x00e162bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 bus 01 mem |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 |
| PCI: 01:00.0 10 <- [0x00e1400000 - 0x00e1401fff] size 0x00002000 gran 0x0d mem64 |
| PCI: 00:1c.0 assign_resources, bus 1 link: 0 |
| PCI: 00:1c.1 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 02 mem |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| NONE missing set_resources |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.3 20 <- [0x00e1500000 - 0x00e15fffff] size 0x00100000 gran 0x14 bus 03 mem |
| PCI: 00:1c.3 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x00e1500000 - 0x00e15000ff] size 0x00000100 gran 0x08 mem |
| PCI: 00:1c.3 assign_resources, bus 3 link: 0 |
| PCI: 00:1d.0 10 <- [0x00e1630000 - 0x00e16303ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00e162e000 - 0x00e162e7ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00e1631000 - 0x00e16310ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.6 10 <- [0x00e162d000 - 0x00e162dfff] size 0x00001000 gran 0x0c mem64 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 167c size 1098 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base d0000000 size 11631100 align 28 gran 0 limit efffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 17b600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit e13fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base e1620000 size 8000 align 15 gran 15 limit e1627fff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base e1600000 size 20000 align 17 gran 17 limit e161ffff flags 60000200 index 10 |
| PCI: 00:19.0 resource base e162c000 size 1000 align 12 gran 12 limit e162cfff flags 60000200 index 14 |
| PCI: 00:19.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base e162f000 size 400 align 12 gran 10 limit e162f3ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base e1628000 size 4000 align 14 gran 14 limit e162bfff flags 60000201 index 10 |
| PCI: 00:1c.4 |
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base e1400000 size 100000 align 20 gran 20 limit e14fffff flags 60080202 index 20 |
| PCI: 01:00.0 |
| PCI: 01:00.0 resource base e1400000 size 2000 align 13 gran 13 limit e1401fff flags 60000201 index 10 |
| PCI: 00:1c.2 |
| PCI: 00:1c.1 child on link 0 NONE |
| PCI: 00:1c.1 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c |
| PCI: 00:1c.1 resource base e0000000 size 800000 align 22 gran 20 limit e07fffff flags 60081202 index 24 |
| PCI: 00:1c.1 resource base e0800000 size 800000 align 22 gran 20 limit e0ffffff flags 60080202 index 20 |
| NONE |
| NONE resource base e0800000 size 800000 align 22 gran 22 limit e0ffffff flags 40000200 index 10 |
| NONE resource base e0000000 size 800000 align 22 gran 22 limit e07fffff flags 40001200 index 14 |
| NONE resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18 |
| PCI: 00:1c.3 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.3 resource base e1500000 size 100000 align 20 gran 20 limit e15fffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base e1500000 size 100 align 12 gran 8 limit e15000ff flags 60000200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base e1630000 size 400 align 12 gran 10 limit e16303ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PNP: 00ff.f |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base e162e000 size 800 align 12 gran 11 limit e162e7ff flags 60000200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base e1631000 size 100 align 12 gran 8 limit e16310ff flags 60000201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| PCI: 00:1f.6 resource base e162d000 size 1000 align 12 gran 12 limit e162dfff flags 60000201 index 10 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2745 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 17aa/21ce |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 17aa/21ce |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:19.0 subsystem <- 17aa/21ce |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 17aa/21ce |
| PCI: 00:1a.0 cmd <- 106 |
| PCI: 00:1b.0 subsystem <- 17aa/21ce |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 17aa/21ce |
| PCI: 00:1c.0 cmd <- 106 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 17aa/21ce |
| PCI: 00:1c.1 cmd <- 107 |
| PCI: 00:1c.3 bridge ctrl <- 0003 |
| PCI: 00:1c.3 subsystem <- 17aa/21ce |
| PCI: 00:1c.3 cmd <- 106 |
| PCI: 00:1d.0 subsystem <- 17aa/21ce |
| PCI: 00:1d.0 cmd <- 102 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 17aa/21ce |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 17aa/21ce |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 17aa/21ce |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 00:1f.6 subsystem <- 17aa/21ce |
| PCI: 00:1f.6 cmd <- 02 |
| PCI: 01:00.0 cmd <- 02 |
| PCI: 03:00.0 subsystem <- 17aa/21ce |
| PCI: 03:00.0 cmd <- 06 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 187 exit 0 |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=0, nvlocked=1 |
| TPM: setup succeeded |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 1 usecs |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 7ffa0670(7ffc8a20) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 8001048b. filesize: 0x1b90 memsize: 0x5bb8 |
| Processing 60 relocs. Offset value of 0x80010000 |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x80008000 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at 80006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd |
| SMM Module: stub loaded at 80008000. Will call 8001048b(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: MCSMI PM1 |
| PM1_STS: RTC TMROF |
| PM1_EN: 0 |
| GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 TCO_SCI |
| ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000027b600000 size 0x17b600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/4. |
| MTRR: UC selected as default type. |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6 |
| MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x00 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 4 cores, 2 threads per core |
| CPU: 0 has core 1 |
| CPU1: stack_base 7ffbf000, stack_end 7ffbfff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| CPU: 0 has core 2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x01 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #1 initialized |
| CPU2: stack_base 7ffbe000, stack_end 7ffbeff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x02 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #2 initialized |
| CPU3: stack_base 7ffbd000, stack_end 7ffbdff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 4 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x03 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #3 initialized |
| CPU4: stack_base 7ffbc000, stack_end 7ffbcff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 4. |
| After apic_write. |
| In relocation handler: cpu 4 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 4. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 5 |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x04 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #4 initialized |
| CPU5: stack_base 7ffbb000, stack_end 7ffbbff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 5. |
| After apic_write. |
| In relocation handler: cpu 5 |
| New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 5. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 6 |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x05 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #5 initialized |
| CPU6: stack_base 7ffba000, stack_end 7ffbaff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 6. |
| After apic_write. |
| In relocation handler: cpu 6 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 6. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x06 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #6 initialized |
| CPU7: stack_base 7ffb9000, stack_end 7ffb9ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 7. |
| After apic_write. |
| In relocation handler: cpu 7 |
| New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 7. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #7 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 147c0 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT NOT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x07 done. |
| VMX is locked, so set_vmx will do nothing |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2200 |
| CPU #7 initialized |
| All AP CPUs stopped (602 loops) |
| CPU0: stack: 7ffc0000 - 7ffc1000, lowest used address 7ffc0aac, stack used: 1364 bytes |
| CPU1: stack: 7ffbf000 - 7ffc0000, lowest used address 7ffbfc40, stack used: 960 bytes |
| CPU2: stack: 7ffbe000 - 7ffbf000, lowest used address 7ffbec40, stack used: 960 bytes |
| CPU3: stack: 7ffbd000 - 7ffbe000, lowest used address 7ffbdc40, stack used: 960 bytes |
| CPU4: stack: 7ffbc000 - 7ffbd000, lowest used address 7ffbcc40, stack used: 960 bytes |
| CPU5: stack: 7ffbb000 - 7ffbc000, lowest used address 7ffbbc40, stack used: 960 bytes |
| CPU6: stack: 7ffba000 - 7ffbb000, lowest used address 7ffbac40, stack used: 960 bytes |
| CPU7: stack: 7ffb9000 - 7ffba000, lowest used address 7ffb9c40, stack used: 960 bytes |
| CPU_CLUSTER: 0 init finished in 191902 usecs |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG10. |
| Disabling PEG60. |
| Disabling Device 7. |
| Disabling PEG IO clock. |
| Set BIOS_RESET_CPL |
| CPU TDP: 35 Watts |
| PCI: 00:00.0 init finished in 1020 usecs |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 25W-35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| EDID: |
| 00 ff ff ff ff ff ff 00 30 e4 e2 02 00 00 00 00 |
| 00 14 01 03 80 1f 11 78 0a 43 45 97 59 57 8e 28 |
| 21 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 |
| 01 01 01 01 01 01 80 25 40 80 60 84 1a 30 30 20 |
| 35 00 36 ae 10 00 00 19 00 00 00 00 00 00 00 00 |
| 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 4c |
| 47 20 44 69 73 70 6c 61 79 0a 20 20 00 00 00 fe |
| 00 4c 50 31 34 30 57 44 32 2d 54 4c 42 31 00 38 |
| Extracted contents: |
| header: 00 ff ff ff ff ff ff 00 |
| serial number: 30 e4 e2 02 00 00 00 00 00 14 |
| version: 01 03 |
| basic params: 80 1f 11 78 0a |
| chroma info: 43 45 97 59 57 8e 28 21 50 54 |
| established: 00 00 00 |
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 |
| descriptor 1: 80 25 40 80 60 84 1a 30 30 20 35 00 36 ae 10 00 00 19 |
| descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| descriptor 3: 00 00 00 fe 00 4c 47 20 44 69 73 70 6c 61 79 0a 20 20 |
| descriptor 4: 00 00 00 fe 00 4c 50 31 34 30 57 44 32 2d 54 4c 42 31 |
| extensions: 00 |
| checksum: 38 |
| |
| Manufacturer: LGD Model 2e2 Serial Number 0 |
| Made week 0 of 2010 |
| EDID version: 1.3 |
| Digital display |
| Maximum image size: 31 cm x 17 cm |
| Gamma: 220% |
| Check DPMS levels |
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2 |
| First detailed timing is preferred timing |
| Established timings supported: |
| Standard timings supported: |
| Detailed timings |
| Hex of detail: 8025408060841a303020350036ae10000019 |
| Detailed mode (IN HEX): Clock 96000 KHz, 136 mm x ae mm |
| 0640 0670 0690 06c0 hborder 0 |
| 0384 0387 038c 039e vborder 0 |
| -hsync -vsync |
| Did detailed timing |
| Hex of detail: 000000000000000000000000000000000000 |
| Manufacturer-specified data, tag 0 |
| Hex of detail: 000000fe004c4720446973706c61790a2020 |
| ASCII string: LG Display |
| Hex of detail: 000000fe004c503134305744322d544c4231 |
| ASCII string: LP140WD2-TLB1 |
| Checksum |
| Checksum: 0x38 (valid) |
| WARNING: EDID block does NOT fully conform to EDID 1.3. |
| Missing name descriptor |
| Missing monitor ranges |
| bringing up panel at resolution 1600 x 900 |
| Borders 0 x 0 |
| Blank 128 x 26 |
| Sync 32 x 5 |
| Front porch 48 x 3 |
| Spread spectrum clock |
| Dual channel |
| Polarities 1, 1 |
| Data M1=6710886, N1=8388608 |
| Link frequency 270000 kHz |
| Link M1=186413, N1=524288 |
| Pixel N=10, M1=21, M2=7, P1=2 |
| Pixel clock 96000 kHz |
| waiting for panel powerup |
| panel powered up |
| PCI: 00:02.0 init finished in 41757 usecs |
| PCI: 00:04.0 init ... |
| PCI: 00:04.0 init finished in 1 usecs |
| PCI: 00:19.0 init ... |
| PCI: 00:19.0 init finished in 0 usecs |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 14 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: base = e1628000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862805 |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 14f1506e |
| Azalia: verb_size: 52 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 4310 usecs |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 12 usecs |
| PCI: 00:1c.1 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 14 usecs |
| PCI: 00:1c.3 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.3 init finished in 11 usecs |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 14 usecs |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| PCH: detected QM67, device id: 0x1c4f, rev id 0x5 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| Set power off after power failure. |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| NMI sources enabled. |
| CougarPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 933 usecs |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| SATA: Controller in AHCI mode. |
| ABAR: e162e000 |
| PCI: 00:1f.2 init finished in 362 usecs |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| PCI: 00:1f.6 init ... |
| PCI: 00:1f.6 init finished in 0 usecs |
| PCI: 01:00.0 init ... |
| PCI: 01:00.0 init finished in 1 usecs |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 15 usecs |
| PNP: 00ff.2 init ... |
| PNP: 00ff.2 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ... |
| I2C: 01:54 init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ... |
| I2C: 01:55 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ... |
| I2C: 01:56 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ... |
| I2C: 01:57 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ... |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 25566 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ... |
| I2C: 01:5d init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ... |
| I2C: 01:5e init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ... |
| I2C: 01:5f init finished in 1 usecs |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.2: enabled 0 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 0 |
| I2C: 01:54: enabled 1 |
| I2C: 01:55: enabled 1 |
| I2C: 01:56: enabled 1 |
| I2C: 01:57: enabled 1 |
| I2C: 01:5c: enabled 1 |
| I2C: 01:5d: enabled 1 |
| I2C: 01:5e: enabled 1 |
| I2C: 01:5f: enabled 1 |
| PCI: 00:04.0: enabled 1 |
| PCI: 01:00.0: enabled 1 |
| NONE: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 15040 run 266160 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 49 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 39840 size 3875 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff46000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| Generating ACPI PIRQ entries |
| ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:04.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=1 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=2 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=7 |
| ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=0 |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: * H8 |
| H8: BDC installed |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| \_SB.PCI0.RP01.WIFI: PCI: 01:00.0 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 7ff35000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff4caa0 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Found @ offset 345c0 size 558 |
| Found a VBT of 3985 bytes after decompression |
| GMA: Found VBT in CBFS |
| GMA: Found valid VBT in CBFS |
| ACPI: * HPET |
| ACPI: added table 6/32, length now 60 |
| ACPI: done. |
| ACPI tables: 35552 bytes. |
| smbios_write_tables: 7ff34000 |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x30 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x14 |
| recv_ec_data: 0x03 |
| Create SMBIOS type 17 |
| PCI: 01:00.0 (unknown) |
| SMBIOS tables: 669 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum dfe7 |
| Writing coreboot table at 0x7ff6a000 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 34b80 size 7a8 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff33fff: RAM |
| 4. 000000007ff34000-000000007ff82fff: CONFIGURATION TABLES |
| 5. 000000007ff83000-000000007ffccfff: RAMSTAGE |
| 6. 000000007ffcd000-000000007fffffff: CONFIGURATION TABLES |
| 7. 0000000080000000-00000000829fffff: RESERVED |
| 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| 9. 00000000fed40000-00000000fed44fff: RESERVED |
| 10. 0000000100000000-000000027b5fffff: RAM |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| Wrote coreboot table at: 7ff6a000, 0xb24 bytes, checksum 5995 |
| coreboot table: 2876 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| TIME STAMP 3. 7ffdd000 00000910 |
| MRC DATA 4. 7ffdc000 000005d4 |
| ROMSTG STCK 5. 7ffd7000 00005000 |
| AFTER CAR 6. 7ffcd000 0000a000 |
| RAMSTAGE 7. 7ff82000 0004b000 |
| SMM BACKUP 8. 7ff72000 00010000 |
| COREBOOT 9. 7ff6a000 00008000 |
| ACPI 10. 7ff46000 00024000 |
| ACPI GNVS 11. 7ff45000 00001000 |
| TCPA TCGLOG12. 7ff35000 00010000 |
| SMBIOS 13. 7ff34000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| USBDEBUG 1. 7fffeba0 00000058 |
| MEM INFO 2. 7fffea40 00000149 |
| ROMSTAGE 3. 7fffea20 00000004 |
| COREBOOTFWD 4. 7fffe9e0 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 26747 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [720000:7fffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 3d100 size 6399c |
| Loading segment from ROM address 0xfff5d138 |
| code (compression=1) |
| New segment dstaddr 0x8200 memsize 0x1b988 srcaddr 0xfff5d18c filesize 0x99fd |
| Loading segment from ROM address 0xfff5d154 |
| code (compression=1) |
| New segment dstaddr 0x100000 memsize 0x125694 srcaddr 0xfff66b89 filesize 0x59f4b |
| Loading segment from ROM address 0xfff5d170 |
| Entry Point 0x00008200 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000001b988 filesz: 0x00000000000099fd |
| lb: [0x000000007ff83000, 0x000000007ffccb58) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x000000000001b988 filesz: 0x00000000000099fd |
| using LZMA |
| [ 0x00008200, 0001c143, 0x00023b88) <- fff5d18c |
| Clearing Segment: addr: 0x000000000001c143 memsz: 0x0000000000007a45 |
| dest 00008200, end 00023b88, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000125694 filesz: 0x0000000000059f4b |
| lb: [0x000000007ff83000, 0x000000007ffccb58) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000125694 filesz: 0x0000000000059f4b |
| using LZMA |
| [ 0x00100000, 00225694, 0x00225694) <- fff66b89 |
| dest 00100000, end 00225694, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 194137 exit 0 |
| PCH: watchdog disabled |
| Jumping to boot code at 00008200(7ff6a000) |
| CPU0: stack: 7ffc0000 - 7ffc1000, lowest used address 7ffc0840, stack used: 1984 bytes |
| tes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| PCI: 00:1f.2 [8086/1c01] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1c22] enabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1c09] disabled No operations |
| PCI: 00:1f.6 [8086/1c24] enabled |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| PCI: pci_scan_bus for bus 01 |
| PCI: 01:00.0 [8086/0000] ops |
| PCI: 01:00.0 [8086/0085] enabled |
| Capability: type 0x01 @ 0xc8 |
| Capability: type 0x05 @ 0xd0 |
| Capability: type 0x10 @ 0xe0 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| Capability: type 0x01 @ 0xc8 |
| Capability: type 0x05 @ 0xd0 |
| Capability: type 0x10 @ 0xe0 |
| Failed to enable LTR for dev = PCI: 01:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 331 usecs |
| PCI: 00:1c.1 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.1 |
| PCI: pci_scan_bus for bus 02 |
| scan_bus: scanning of bus PCI: 00:1c.1 took 54 usecs |
| PCI: 00:1c.3 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.3 |
| PCI: pci_scan_bus for bus 03 |
| PCI: 03:00.0 [1180/0000] ops |
| PCI: 03:00.0 [1180/e823] enabled |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 03:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.3 took 260 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| PMH7: ID 04 Revision 01 |
| PNP: 00ff.1 enabled |
| PNP: 0c31.0 enabled |
| Clearing EC output queue... |
| EC output queue has been cleared. |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x30 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x14 |
| recv_ec_data: 0x03 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x12 |
| EC Firmware ID 83HT30WW-3.20, Version 0.01C |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| No CMOS option 'low_battery_beep'. |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x10 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| H8: BDC installed |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| recv_ec_data: 0x20 |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| recv_ec_data: 0x20 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| recv_ec_data: 0xa7 |
| FMAP: area COREBOOT found @ 720000 (917504 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35fc0 size 7a8 |
| recv_ec_data: 0xa7 |
| recv_ec_data: 0x20 |
| PNP: 00ff.2 enabled |
| Hybrid graphics: Not installed |
| PNP: 00ff.f disabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 5523 usecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I |