| |
| |
| coreboot-4.9-1305-g237baa1433 Fri Apr 12 10:19:59 UTC 2019 romstage starting (log level: 7)... |
| |
| Mobile Intel(R) 82945GM/GME Express Chipset |
| (G)MCH capable of up to FSB 800 MHz |
| (G)MCH capable of up to DDR2-667 |
| Setting up static southbridge registers... done. |
| Disabling Watchdog reboot... done. |
| Setting up static northbridge registers... done. |
| Waiting for MCHBAR to come up...ok |
| PM1_CNT: 00001c00 |
| SMBus controller enabled. |
| Setting up RAM controller. |
| This mainboard supports Dual Channel Operation. |
| Reading SPD using i2c block operation. |
| DDR II Channel 0 Socket 0: x8DDS |
| DIMM 0 side 0 = 512 MB |
| DIMM 0 side 1 = 512 MB |
| DDR II Channel 0 Socket 1: N/A |
| Reading SPD using i2c block operation. |
| DDR II Channel 1 Socket 0: x8DDS |
| DIMM 2 side 0 = 512 MB |
| DIMM 2 side 1 = 512 MB |
| DDR II Channel 1 Socket 1: N/A |
| Memory will be driven at 667MT with CAS=5 clocks |
| tRAS = 15 cycles |
| tRP = 5 cycles |
| tRCD = 5 cycles |
| tWR = 5 cycles |
| tRFC = 35 cycles |
| Refresh: 7.8us |
| Setting Graphics Frequency... |
| FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz |
| Setting Memory Frequency... CLKCFG = 0x00010023, CLKCFG = 0x00010043, ok |
| Setting mode of operation for memory channels...Dual Channel Interleaved. |
| Programming Clock Crossing...MEM=667 FSB=667... ok |
| Setting RAM size... |
| C0DRB = 0x20202010 |
| C1DRB = 0x20202010 |
| TOLUD = 0x0080 |
| Setting row attributes... |
| C0DRA = 0x0033 |
| C1DRA = 0x0033 |
| one dimm per channel config.. |
| Initializing System Memory IO... |
| Programming Dual Channel RCOMP |
| Table Index: 18 |
| Programming DLL Timings... |
| Enabling System Memory IO... |
| jedec enable sequence: bank 0 |
| jedec enable sequence: bank 1 |
| bankaddr from bank size of rank 0 |
| jedec enable sequence: bank 4 |
| jedec enable sequence: bank 5 |
| bankaddr from bank size of rank 4 |
| RAM initialization finished. |
| Setting up Egress Port RCRB |
| Loading port arbitration table ...ok |
| Wait for VC1 negotiation ...ok |
| Setting up DMI RCRB |
| Wait for VC1 negotiation ...done.. |
| Internal graphics: enabled |
| Waiting for DMI hardware...ok |
| Enabling PCI Express x16 Link |
| SLOTSTS: 0000 |
| Disabling PCI Express x16 Link |
| Wait for link to enter detect state... ok |
| Setting up Root Complex Topology |
| CBMEM: |
| IMD: root @ 7f3ff000 254 entries. |
| IMD: root @ 7f3fec00 62 entries. |
| External stage cache: |
| IMD: root @ 7f7ff000 254 entries. |
| IMD: root @ 7f7fec00 62 entries. |
| MTRR Range: Start=ffc00000 End=0 (Size 400000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7ec00000 End=7f000000 (Size 400000) |
| MTRR Range: Start=7f000000 End=7f400000 (Size 400000) |
| MTRR Range: Start=7f600000 End=7f800000 (Size 200000) |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Found @ offset 3d400 size 3e00 |
| Decompressing stage fallback/postcar @ 0x7f3cffc0 (32464 bytes) |
| Loading module at 7f3d0000 with entry 7f3d0000. filesize: 0x3bd0 memsize: 0x7e90 |
| Processing 117 relocs. Offset value of 0x7d3d0000 |
| |
| |
| coreboot-4.9-1305-g237baa1433 Fri Apr 12 10:19:59 UTC 2019 postcar starting (log level: 7)... |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 20d40 size 14eb2 |
| Decompressing stage fallback/ramstage @ 0x7f391fc0 (246304 bytes) |
| Loading module at 7f392000 with entry 7f392000. filesize: 0x2b628 memsize: 0x3c1e0 |
| Processing 3114 relocs. Offset value of 0x7e592000 |
| |
| |
| coreboot-4.9-1305-g237baa1433 Fri Apr 12 10:19:59 UTC 2019 ramstage starting (log level: 7)... |
| Normal boot. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 |
| Enumerating buses... |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/27a0] enabled |
| PCI: 00:02.0 [8086/27a2] enabled |
| PCI: 00:02.1 [8086/27a6] enabled |
| PCI: 00:1b.0 [8086/27d8] enabled |
| PCI: 00:1c.0 [8086/27d0] enabled |
| PCI: 00:1c.1 [8086/27d2] enabled |
| PCI: 00:1c.2 [8086/27d4] enabled |
| PCI: 00:1c.3 [8086/27d6] enabled |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1d.0 [8086/27c8] enabled |
| PCI: 00:1d.1 [8086/27c9] enabled |
| PCI: 00:1d.2 [8086/27ca] enabled |
| PCI: 00:1d.3 [8086/27cb] enabled |
| PCI: 00:1d.7 [8086/27cc] enabled |
| PCI: 00:1e.0 [8086/2448] enabled |
| PCI: 00:1e.2: Disabling device |
| PCI: 00:1e.2: Disabling device |
| PCI: 00:1e.2 [8086/27de] disabled |
| PCI: 00:1e.3: Disabling device |
| PCI: 00:1e.3: Disabling device |
| PCI: 00:1e.3 [8086/27dd] disabled |
| PCI: 00:1f.0 [8086/27b9] enabled |
| PCI: 00:1f.1: Disabling device |
| PCI: 00:1f.1: Disabling device |
| PCI: 00:1f.1 [8086/27df] disabled |
| Set SATA mode early |
| Set SATA mode early |
| PCI: 00:1f.2 [8086/27c4] enabled |
| PCI: 00:1f.3 [8086/27da] enabled |
| PCI: Leftover static devices: |
| PCI: 00:01.0 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: Check your devicetree.cb. |
| PCI: pci_scan_bus for bus 01 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 2651 usecs |
| PCI: pci_scan_bus for bus 02 |
| PCI: 02:00.0 [8086/4222] enabled |
| scan_bus: scanning of bus PCI: 00:1c.1 took 5624 usecs |
| PCI: pci_scan_bus for bus 03 |
| scan_bus: scanning of bus PCI: 00:1c.2 took 2651 usecs |
| PCI: pci_scan_bus for bus 04 |
| PCI: 04:00.0 [10ec/8168] enabled |
| scan_bus: scanning of bus PCI: 00:1c.3 took 5612 usecs |
| PCI: pci_scan_bus for bus 05 |
| PCI: 05:05.0 [104c/8039] enabled |
| PCI: 05:05.1 [104c/803a] enabled |
| PCI: 05:05.2 [104c/803b] enabled |
| PCI: 05:05.3 [104c/803c] enabled |
| PCI: 05:05.4 [104c/803d] enabled |
| PCI: pci_scan_bus for bus 06 |
| scan_bus: scanning of bus PCI: 05:05.0 took 2665 usecs |
| scan_bus: scanning of bus PCI: 00:1e.0 took 25000 usecs |
| PNP: 002e.0 disabled |
| PNP: 002e.1 disabled |
| PNP: 002e.3 enabled |
| PNP: 002e.4 enabled |
| PNP: 002e.5 disabled |
| PNP: 002e.7 disabled |
| PNP: 002e.8 disabled |
| PNP: 004e.0 disabled |
| PNP: 004e.1 disabled |
| PNP: 004e.5 enabled |
| PNP: 004e.7 disabled |
| PNP: 004e.8 disabled |
| PNP: 004e.9 disabled |
| PNP: 004e.a disabled |
| PNP: 004e.b disabled |
| scan_bus: scanning of bus PCI: 00:1f.0 took 28517 usecs |
| scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 201342 usecs |
| scan_bus: scanning of bus Root Device took 210388 usecs |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 217815 exit 0 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| pci_tolm: 0xffffffff |
| IGD decoded, subtracting 8M UMA |
| TSEG decoded, subtracting 2M |
| Unused RAM between cbmem_top and TOM: 0x800K |
| Available memory: 2084864K (2036M) |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PNP: 002e.3 missing read_resources |
| Done reading resources. |
| skipping PNP: 002e.3@60 fixed resource, size=0! |
| skipping PNP: 002e.3@70 fixed resource, size=0! |
| Setting resources... |
| DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem |
| DOMAIN: 0000 04 <- [0x00000c0000 - 0x007fffffff] size 0x7ff40000 gran 0x00 mem |
| DOMAIN: 0000 05 <- [0x007f800000 - 0x007fffffff] size 0x00800000 gran 0x00 mem |
| DOMAIN: 0000 06 <- [0x007f600000 - 0x007f7fffff] size 0x00200000 gran 0x00 mem |
| DOMAIN: 0000 07 <- [0x007f400000 - 0x007f5fffff] size 0x00200000 gran 0x00 mem |
| PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem |
| PCI: 00:02.0 14 <- [0x0000004090 - 0x0000004097] size 0x00000008 gran 0x03 io |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem |
| PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem |
| PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem |
| PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 02:00.0 10 <- [0x00e4100000 - 0x00e4100fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.3 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io |
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.3 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 04 mem |
| PCI: 04:00.0 10 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io |
| PCI: 04:00.0 18 <- [0x00e4220000 - 0x00e4220fff] size 0x00001000 gran 0x0c mem64 |
| PCI: 04:00.0 30 <- [0x00e4200000 - 0x00e421ffff] size 0x00020000 gran 0x11 romem |
| PCI: 00:1d.0 20 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.1 20 <- [0x0000004020 - 0x000000403f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.2 20 <- [0x0000004040 - 0x000000405f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.3 20 <- [0x0000004060 - 0x000000407f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c bus 05 io |
| PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem |
| PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem |
| PCI: 05:05.0 In set resources |
| PCI: 05:05.0 10 <- [0x00e2004000 - 0x00e2004fff] size 0x00001000 gran 0x0c mem |
| PCI: 05:05.0 2c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x02 io |
| PCI: 05:05.0 34 <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io |
| PCI: 05:05.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem |
| PCI: 05:05.0 24 <- [0x00e0004000 - 0x00e2003fff] size 0x02000000 gran 0x0c mem |
| PCI: 05:05.0 done set resources |
| PCI: 05:05.1 10 <- [0x00e2008000 - 0x00e20087ff] size 0x00000800 gran 0x0b mem |
| PCI: 05:05.1 14 <- [0x00e0000000 - 0x00e0003fff] size 0x00004000 gran 0x0e mem |
| PCI: 05:05.2 10 <- [0x00e2005000 - 0x00e2005fff] size 0x00001000 gran 0x0c mem |
| PCI: 05:05.3 10 <- [0x00e2009000 - 0x00e20090ff] size 0x00000100 gran 0x08 mem |
| PCI: 05:05.4 10 <- [0x00e2006000 - 0x00e2006fff] size 0x00001000 gran 0x0c mem |
| PCI: 05:05.4 14 <- [0x00e2007000 - 0x00e2007fff] size 0x00001000 gran 0x0c mem |
| PNP: 002e.3 missing set_resources |
| PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PNP: 004e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io |
| PNP: 004e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 10 <- [0x0000004098 - 0x000000409f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x00000040a8 - 0x00000040ab] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x00000040a0 - 0x00000040a7] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x00000040ac - 0x00000040af] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000004080 - 0x000000408f] size 0x00000010 gran 0x04 io |
| PCI: 00:1f.2 24 <- [0x00e4445000 - 0x00e44453ff] size 0x00000400 gran 0x0a mem |
| Done setting resources. |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 468309 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 8086/27a0 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 8086/27a2 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:02.1 subsystem <- 8086/27a6 |
| PCI: 00:02.1 cmd <- 02 |
| PCI: 00:1b.0 subsystem <- 8086/27d8 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 8086/27d0 |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 8086/27d2 |
| PCI: 00:1c.1 cmd <- 106 |
| PCI: 00:1c.2 bridge ctrl <- 0003 |
| PCI: 00:1c.2 subsystem <- 8086/27d4 |
| PCI: 00:1c.2 cmd <- 100 |
| PCI: 00:1c.3 bridge ctrl <- 0003 |
| PCI: 00:1c.3 subsystem <- 8086/27d6 |
| PCI: 00:1c.3 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 8086/27c8 |
| PCI: 00:1d.0 cmd <- 01 |
| PCI: 00:1d.1 subsystem <- 8086/27c9 |
| PCI: 00:1d.1 cmd <- 01 |
| PCI: 00:1d.2 subsystem <- 8086/27ca |
| PCI: 00:1d.2 cmd <- 01 |
| PCI: 00:1d.3 subsystem <- 8086/27cb |
| PCI: 00:1d.3 cmd <- 01 |
| PCI: 00:1d.7 subsystem <- 8086/27cc |
| PCI: 00:1d.7 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0003 |
| PCI: 00:1e.0 cmd <- 107 |
| PCI: 00:1f.0 subsystem <- 8086/27b9 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 8086/27c4 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 8086/27da |
| PCI: 00:1f.3 cmd <- 101 |
| PCI: 02:00.0 cmd <- 02 |
| PCI: 04:00.0 cmd <- 03 |
| PCI: 05:05.0 bridge ctrl <- 0143 |
| PCI: 05:05.0 cmd <- 07 |
| PCI: 05:05.1 cmd <- 02 |
| PCI: 05:05.2 cmd <- 02 |
| PCI: 05:05.3 cmd <- 06 |
| PCI: 05:05.4 cmd <- 02 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 122923 exit 0 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 2570 usecs |
| CPU_CLUSTER: 0 init ... |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset bcc0 size 15000 |
| microcode: sig=0x6f6 pf=0x20 revision=0x0 |
| microcode: updated to revision 0xd1 date=2010-10-01 |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x000000007f400000 size 0x7f340000 type 6 |
| 0x000000007f400000 - 0x00000000d0000000 size 0x50c00000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 6/4. |
| MTRR: UC selected as default type. |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| MTRR: 1 base 0x000000007f400000 mask 0x0000000fffc00000 type 0 |
| MTRR: 2 base 0x000000007f800000 mask 0x0000000fff800000 type 0 |
| MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| CPU has 2 cores. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 1 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...done. |
| AP: slot 1 apic_id 1. |
| Waiting for 2nd SIPI to complete...done. |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 7f3a807d(00000000) |
| Installing SMM handler to 0x7f600000 |
| Loading module at 7f610000 with entry 7f61013a. filesize: 0xa50 memsize: 0x4a68 |
| Processing 42 relocs. Offset value of 0x7f610000 |
| Loading module at 7f608000 with entry 7f608000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x7f608000 |
| SMM Module: placing jmp sequence at 7f607c00 rel16 0x03fd |
| SMM Module: stub loaded at 7f608000. Will call 7f61013a(00000000) |
| Initializing Southbridge SMI... |
| |
| New SMBASE 0x7f600000 |
| In relocation handler: cpu 0 |
| New SMBASE=0x7f600000 |
| Relocation complete. |
| VMX status: enabled |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| IA32_FEATURE_CONTROL status: locked |
| New SMBASE 0x7f5ffc00 |
| In relocation handler: cpu 1 |
| New SMBASE=0x7f5ffc00 |
| Relocation complete. |
| Initializing CPU #0 |
| CPU: vendor Intel device 6f6 |
| CPU: family 06, model 0f, stepping 06 |
| Enabling cache |
| CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| Setting up local APIC... apic_id: 0x00 done. |
| CPU #0 initialized |
| Initializing CPU #1 |
| CPU: vendor Intel device 6f6 |
| CPU: family 06, model 0f, stepping 06 |
| Enabling cache |
| CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| Setting up local APIC... apic_id: 0x01 done. |
| CPU #1 initialized |
| bsp_do_flight_plan done after 124 msecs. |
| CPU 1 going down... |
| Initializing southbridge SMI... |
| SMI_STS: GPI |
| GPE0_STS: GPIO11 GPIO1 GPIO0 |
| ALT_GP_SMI_STS: GPI11 GPI8 GPI7 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| Locking SMM. |
| CPU_CLUSTER: 0 init finished in 335139 usecs |
| PCI: 00:02.0 init ... |
| Initializing VGA without OPROM. |
| No display connected on slave 2 |
| WARNING: EDID block does NOT fully conform to EDID 1.3. |
| Missing name descriptor |
| Missing monitor ranges |
| bringing up panel at resolution 1280 x 800 |
| Borders 0 x 0 |
| Blank 130 x 19 |
| Sync 26 x 4 |
| Front porch 39 x 2 |
| DREF clock |
| Single channel |
| Polarities 1, 1 |
| Pixel N=3, M1=16, M2=5, P1=2 |
| Pixel clock 69285 kHz |
| VGA mode: text |
| waiting for panel powerup |
| panel powered up |
| gtt_setup is enabled. |
| 8M UMA |
| GTT PGETBL_CTL register: 0x7ffc0001 |
| GTT Enabled |
| PCI: 00:02.0 init finished in 138002 usecs |
| PCI: 00:02.1 init ... |
| PCI: 00:02.1 init finished in 2002 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: codec type: Azalia |
| Azalia: base = e4440000 |
| Azalia: codec_mask = 03 |
| Azalia: Initializing codec #1 |
| Azalia: codec viddid: 14f12c06 |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 10ec0262 |
| Azalia: verb_size: 52 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 30483 usecs |
| PCI: 00:1c.0 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.0 init finished in 4802 usecs |
| PCI: 00:1c.1 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.1 init finished in 4801 usecs |
| PCI: 00:1c.2 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.2 init finished in 4801 usecs |
| PCI: 00:1c.3 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.3 init finished in 4802 usecs |
| PCI: 00:1d.0 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 5227 usecs |
| PCI: 00:1d.1 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.1 init finished in 5227 usecs |
| PCI: 00:1d.2 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.2 init finished in 5226 usecs |
| PCI: 00:1d.3 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.3 init finished in 5227 usecs |
| PCI: 00:1d.7 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.7 init finished in 5232 usecs |
| PCI: 00:1e.0 init ... |
| PCI: 00:1e.0 init finished in 2013 usecs |
| PCI: 00:1f.0 init ... |
| i82801gx: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| Set power on after power failure. |
| NMI sources disabled. |
| rtc_failed = 0x0 |
| RTC Init |
| Disabling ACPI via APMC: |
| done. |
| PCI: 00:1f.0 init finished in 23872 usecs |
| PCI: 00:1f.2 init ... |
| i82801gx_sata: initializing... |
| SATA controller in combined mode. |
| PCI: 00:1f.2 init finished in 7853 usecs |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 2002 usecs |
| PCI: 04:00.0 init ... |
| PCI: 04:00.0 init finished in 2001 usecs |
| PCI: 05:05.0 init ... |
| TI PCIxx12 init |
| PCI: 05:05.0 init finished in 3482 usecs |
| PCI: 05:05.1 init ... |
| PCI: 05:05.1 init finished in 2001 usecs |
| PCI: 05:05.2 init ... |
| PCI: 05:05.2 init finished in 2002 usecs |
| PCI: 05:05.3 init ... |
| PCI: 05:05.3 init finished in 2002 usecs |
| PCI: 05:05.4 init ... |
| PCI: 05:05.4 init finished in 2001 usecs |
| PNP: 002e.4 init ... |
| PNP: 002e.4 init finished in 1915 usecs |
| PNP: 004e.5 init ... |
| PNP: 004e.5 init finished in 1916 usecs |
| Devices initialized |
| BS: BS_DEV_INIT times (us): entry 7 run 705943 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 5236 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0 |
| Copying Interrupt Routing Table to 0x000f0000... done. |
| Copying Interrupt Routing Table to 0x7f378000... done. |
| PIRQ table: 320 bytes. |
| Wrote the mp table end at: 000f0410 - 000f05a4 |
| Wrote the mp table end at: 7f377010 - 7f3771a4 |
| MP table: 420 bytes. |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 41240 size 3f0f |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7f353000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 2 core(s) each. |
| clocks between 1000 and 2000 MHz. |
| adding 4 P-States between busratio 6 and c, incl. P0 |
| PSS: 2000MHz power 35000 control 0xc24 status 0xc24 |
| PSS: 1666MHz power 31666 control 0xa1d status 0xa1d |
| PSS: 1333MHz power 28333 control 0x818 status 0x818 |
| PSS: 1000MHz power 25000 control 0x613 status 0x613 |
| clocks between 1000 and 2000 MHz. |
| adding 4 P-States between busratio 6 and c, incl. P0 |
| PSS: 2000MHz power 35000 control 0xc24 status 0xc24 |
| PSS: 1666MHz power 31666 control 0xa1d status 0xa1d |
| PSS: 1333MHz power 28333 control 0x818 status 0x818 |
| PSS: 1000MHz power 25000 control 0x613 status 0x613 |
| Generating ACPI PIRQ entries |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * MADT |
| ACPI: added table 4/32, length now 52 |
| current = 7f357ab0 |
| ACPI: * ECDT |
| ACPI: added table 5/32, length now 56 |
| current = 7f357b10 |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'vbt.bin' |
| CBFS: 'vbt.bin' not found. |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'pci8086,27a2.rom' |
| CBFS: 'pci8086,27a2.rom' not found. |
| PCI Option ROM loading disabled for PCI: 00:02.0 |
| GMA: locate_vbt_vbios: aa55 8086 0 0 3 |
| GMA: Found valid VBT in legacy area |
| ACPI: * HPET |
| ACPI: added table 6/32, length now 60 |
| ACPI: done. |
| ACPI tables: 27472 bytes. |
| smbios_write_tables: 7f352000 |
| SMBIOS tables: 450 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum f0a6 |
| Writing coreboot table at 0x7f379000 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000c0000-000000007f351fff: RAM |
| 3. 000000007f352000-000000007f391fff: CONFIGURATION TABLES |
| 4. 000000007f392000-000000007f3cefff: RAMSTAGE |
| 5. 000000007f3cf000-000000007f3fffff: CONFIGURATION TABLES |
| 6. 000000007f400000-000000007fffffff: RESERVED |
| 7. 00000000f0000000-00000000f3ffffff: RESERVED |
| Manufacturer: 20 |
| SF: Detected M25P32 with sector size 0x10000, total 0x400000 |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| FMAP: Found "FLASH" version 1.1 at 0. |
| FMAP: base = ffc00000 size = 400000 #areas = 3 |
| Wrote coreboot table at: 7f379000, 0x2fc bytes, checksum 4450 |
| coreboot table: 788 bytes. |
| IMD ROOT 0. 7f3ff000 00001000 |
| IMD SMALL 1. 7f3fe000 00001000 |
| CONSOLE 2. 7f3de000 00020000 |
| TIME STAMP 3. 7f3dd000 00000910 |
| ROMSTG STCK 4. 7f3d8000 00005000 |
| AFTER CAR 5. 7f3cf000 00009000 |
| RAMSTAGE 6. 7f391000 0003e000 |
| SMM BACKUP 7. 7f381000 00010000 |
| COREBOOT 8. 7f379000 00008000 |
| IRQ TABLE 9. 7f378000 00001000 |
| SMP TABLE 10. 7f377000 00001000 |
| ACPI 11. 7f353000 00024000 |
| SMBIOS 12. 7f352000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7f3fec00 00000400 |
| ROMSTAGE 1. 7f3febe0 00000004 |
| ACPI GNVS 2. 7f3feae0 00000100 |
| COREBOOTFWD 3. 7f3feaa0 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 322811 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 451c0 size 10c81 |
| Checking segment from ROM address 0xffc453f8 |
| Checking segment from ROM address 0xffc45414 |
| Loading segment from ROM address 0xffc453f8 |
| code (compression=1) |
| New segment dstaddr 0x000e01e0 memsize 0x1fe20 srcaddr 0xffc45430 filesize 0x10c49 |
| Loading Segment: addr: 0x000e01e0 memsz: 0x000000000001fe20 filesz: 0x0000000000010c49 |
| using LZMA |
| Loading segment from ROM address 0xffc45414 |
| Entry Point 0x000fd258 |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 87459 exit 0 |
| ICH7 watchdog disabled |
| Jumping to boot code at 000fd258(7f379000) |
| SeaBIOS (version rel-1.12.0-14-gf4c6e4c) |
| BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30 |
| Found coreboot cbmem console @ 7f3de000 |
| Found mainboard Getac P470 |
| Relocating init from 0x000e1860 to 0x7f3051c0 (size 52640) |
| Found CBFS header at 0xffc00238 |
| multiboot: eax=7f3bd100, ebx=7f3bd0b4 |
| Found 24 PCI devices (max PCI bus is 06) |
| Copying SMBIOS entry point from 0x7f352000 to 0x000f6280 |
| Copying ACPI RSDP from 0x7f353000 to 0x000f6250 |
| Copying MPTABLE from 0x7f377000/7f377010 to 0x000f60a0 |
| Copying PIR from 0x7f378000 to 0x000f5f60 |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.12.0-14-gf4c6e4c) |
| EHCI init on dev 00:1d.7 (regs=0xe4444020) |
| UHCI init on dev 00:1d.0 (io=4000) |
| UHCI init on dev 00:1d.1 (io=4020) |
| UHCI init on dev 00:1d.2 (io=4040) |
| UHCI init on dev 00:1d.3 (io=4060) |
| ATA controller 1 at 1f0/3f4/0 (irq 14 dev fa) |
| ATA controller 2 at 170/374/0 (irq 15 dev fa) |
| Searching bootorder for: /pci@i0cf8/pci-bridge@1e/*@5,3 |
| Found 0 lpt ports |
| Found 2 serial ports |
| DVD/CD [ata1-0: MATSHITADVD-RAM UJ-850S ATAPI-7 DVD/CD] |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0 |
| ata0-0: FUJITSU MHW2120BH ATA-8 Hard-Disk (111 GiBytes) |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| PS2 keyboard initialized |
| Initialized USB HUB (0 ports used) |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f5ec0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 |
| Space available for UMB: c7000-ed000, f5aa0-f5e90 |
| Returned 262144 bytes of ZoneHigh |
| e820 map has 6 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007f352000 = 1 RAM |
| 4: 000000007f352000 - 0000000080000000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| enter handle_19: |
| NULL |
| Booting from DVD/CD... |
| Device reports MEDIUM NOT PRESENT |
| scsi_is_ready returned -1 |
| Boot failed: Could not read from CDROM (code 0003) |
| enter handle_18: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |
| |
| coreboot-4.9-1305-g237baa1433 Fri Apr 12 10:19:59 UTC 2019 romstage starting (log level: 7)... |
| |
| Mobile Intel(R) 82945GM/GME Express Chipset |
| (G)MCH capable of up to FSB 800 MHz |
| (G)MCH capable of up to DDR2-667 |
| Setting up static southbridge registers... done. |
| Disabling Watchdog reboot... done. |
| Setting up static northbridge registers... done. |
| Waiting for MCHBAR to come up...ok |
| PM1_CNT: 00001400 |
| Resume from S3 detected. |
| SMBus controller enabled. |
| Setting up RAM controller. |
| This mainboard supports Dual Channel Operation. |
| Reading SPD using i2c block operation. |
| DDR II Channel 0 Socket 0: x8DDS |
| DIMM 0 side 0 = 512 MB |
| DIMM 0 side 1 = 512 MB |
| DDR II Channel 0 Socket 1: N/A |
| Reading SPD using i2c block operation. |
| DDR II Channel 1 Socket 0: x8DDS |
| DIMM 2 side 0 = 512 MB |
| DIMM 2 side 1 = 512 MB |
| DDR II Channel 1 Socket 1: N/A |
| Memory will be driven at 667MT with CAS=5 clocks |
| tRAS = 15 cycles |
| tRP = 5 cycles |
| tRCD = 5 cycles |
| tWR = 5 cycles |
| tRFC = 35 cycles |
| Refresh: 7.8us |
| Setting Graphics Frequency... |
| FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz |
| Setting Memory Frequency... CLKCFG = 0x00010023, CLKCFG = 0x00010043, ok |
| Setting mode of operation for memory channels...Dual Channel Interleaved. |
| Programming Clock Crossing...MEM=667 FSB=667... ok |
| Setting RAM size... |
| C0DRB = 0x20202010 |
| C1DRB = 0x20202010 |
| TOLUD = 0x0080 |
| Setting row attributes... |
| C0DRA = 0x0033 |
| C1DRA = 0x0033 |
| one dimm per channel config.. |
| Initializing System Memory IO... |
| Programming Dual Channel RCOMP |
| Table Index: 18 |
| Programming DLL Timings... |
| Enabling System Memory IO... |
| RAM initialization finished. |
| Setting up Egress Port RCRB |
| Loading port arbitration table ...ok |
| Wait for VC1 negotiation ...ok |
| Setting up DMI RCRB |
| Wait for VC1 negotiation ...done.. |
| Internal graphics: enabled |
| Waiting for DMI hardware...ok |
| Enabling PCI Express x16 Link |
| SLOTSTS: 0000 |
| Disabling PCI Express x16 Link |
| Wait for link to enter detect state... ok |
| Setting up Root Complex Topology |
| MTRR Range: Start=ffc00000 End=0 (Size 400000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7ec00000 End=7f000000 (Size 400000) |
| MTRR Range: Start=7f000000 End=7f400000 (Size 400000) |
| MTRR Range: Start=7f600000 End=7f800000 (Size 200000) |
| |
| |
| coreboot-4.9-1305-g237baa1433 Fri Apr 12 10:19:59 UTC 2019 postcar starting (log level: 7)... |
| Jumping to image. |
| |
| |
| coreboot-4.9-1305-g237baa1433 Fri Apr 12 10:19:59 UTC 2019 ramstage starting (log level: 7)... |
| S3 Resume. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 |
| Enumerating buses... |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/27a0] enabled |
| PCI: 00:02.0 [8086/27a2] enabled |
| PCI: 00:02.1 [8086/27a6] enabled |
| PCI: 00:1b.0 [8086/27d8] enabled |
| PCI: 00:1c.0 [8086/27d0] enabled |
| PCI: 00:1c.1 [8086/27d2] enabled |
| PCI: 00:1c.2 [8086/27d4] enabled |
| PCI: 00:1c.3 [8086/27d6] enabled |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1d.0 [8086/27c8] enabled |
| PCI: 00:1d.1 [8086/27c9] enabled |
| PCI: 00:1d.2 [8086/27ca] enabled |
| PCI: 00:1d.3 [8086/27cb] enabled |
| PCI: 00:1d.7 [8086/27cc] enabled |
| PCI: 00:1e.0 [8086/2448] enabled |
| PCI: 00:1e.2: Disabling device |
| PCI: 00:1e.2: Disabling device |
| PCI: 00:1e.2 [8086/27de] disabled |
| PCI: 00:1e.3: Disabling device |
| PCI: 00:1e.3: Disabling device |
| PCI: 00:1e.3 [8086/27dd] disabled |
| PCI: 00:1f.0 [8086/27b9] enabled |
| PCI: 00:1f.1: Disabling device |
| PCI: 00:1f.1: Disabling device |
| PCI: 00:1f.1 [8086/27df] disabled |
| Set SATA mode early |
| Set SATA mode early |
| PCI: 00:1f.2 [8086/27c4] enabled |
| PCI: 00:1f.3 [8086/27da] enabled |
| PCI: Leftover static devices: |
| PCI: 00:01.0 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: Check your devicetree.cb. |
| PCI: pci_scan_bus for bus 01 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 2650 usecs |
| PCI: pci_scan_bus for bus 02 |
| PCI: 02:00.0 [8086/4222] enabled |
| scan_bus: scanning of bus PCI: 00:1c.1 took 5623 usecs |
| PCI: pci_scan_bus for bus 03 |
| scan_bus: scanning of bus PCI: 00:1c.2 took 2650 usecs |
| PCI: pci_scan_bus for bus 04 |
| PCI: 04:00.0 [10ec/8168] enabled |
| scan_bus: scanning of bus PCI: 00:1c.3 took 5612 usecs |
| PCI: pci_scan_bus for bus 05 |
| PCI: 05:05.0 [104c/8039] enabled |
| PCI: 05:05.1 [104c/803a] enabled |
| PCI: 05:05.2 [104c/803b] enabled |
| PCI: 05:05.3 [104c/803c] enabled |
| PCI: 05:05.4 [104c/803d] enabled |
| PCI: pci_scan_bus for bus 06 |
| scan_bus: scanning of bus PCI: 05:05.0 took 2665 usecs |
| scan_bus: scanning of bus PCI: 00:1e.0 took 25003 usecs |
| PNP: 002e.0 disabled |
| PNP: 002e.1 disabled |
| PNP: 002e.3 enabled |
| PNP: 002e.4 enabled |
| PNP: 002e.5 disabled |
| PNP: 002e.7 disabled |
| PNP: 002e.8 disabled |
| PNP: 004e.0 disabled |
| PNP: 004e.1 disabled |
| PNP: 004e.5 enabled |
| PNP: 004e.7 disabled |
| PNP: 004e.8 disabled |
| PNP: 004e.9 disabled |
| PNP: 004e.a disabled |
| PNP: 004e.b disabled |
| scan_bus: scanning of bus PCI: 00:1f.0 took 28508 usecs |
| scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 201315 usecs |
| scan_bus: scanning of bus Root Device took 210361 usecs |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 217786 exit 0 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| pci_tolm: 0xffffffff |
| IGD decoded, subtracting 8M UMA |
| TSEG decoded, subtracting 2M |
| Unused RAM between cbmem_top and TOM: 0x800K |
| Available memory: 2084864K (2036M) |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PNP: 002e.3 missing read_resources |
| Done reading resources. |
| skipping PNP: 002e.3@60 fixed resource, size=0! |
| skipping PNP: 002e.3@70 fixed resource, size=0! |
| Setting resources... |
| DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem |
| DOMAIN: 0000 04 <- [0x00000c0000 - 0x007fffffff] size 0x7ff40000 gran 0x00 mem |
| DOMAIN: 0000 05 <- [0x007f800000 - 0x007fffffff] size 0x00800000 gran 0x00 mem |
| DOMAIN: 0000 06 <- [0x007f600000 - 0x007f7fffff] size 0x00200000 gran 0x00 mem |
| DOMAIN: 0000 07 <- [0x007f400000 - 0x007f5fffff] size 0x00200000 gran 0x00 mem |
| PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem |
| PCI: 00:02.0 14 <- [0x0000004090 - 0x0000004097] size 0x00000008 gran 0x03 io |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem |
| PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem |
| PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem |
| PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 02:00.0 10 <- [0x00e4100000 - 0x00e4100fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.3 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io |
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.3 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 04 mem |
| PCI: 04:00.0 10 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io |
| PCI: 04:00.0 18 <- [0x00e4220000 - 0x00e4220fff] size 0x00001000 gran 0x0c mem64 |
| PCI: 04:00.0 30 <- [0x00e4200000 - 0x00e421ffff] size 0x00020000 gran 0x11 romem |
| PCI: 00:1d.0 20 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.1 20 <- [0x0000004020 - 0x000000403f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.2 20 <- [0x0000004040 - 0x000000405f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.3 20 <- [0x0000004060 - 0x000000407f] size 0x00000020 gran 0x05 io |
| PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c bus 05 io |
| PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem |
| PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem |
| PCI: 05:05.0 In set resources |
| PCI: 05:05.0 10 <- [0x00e2004000 - 0x00e2004fff] size 0x00001000 gran 0x0c mem |
| PCI: 05:05.0 2c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x02 io |
| PCI: 05:05.0 34 <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io |
| PCI: 05:05.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem |
| PCI: 05:05.0 24 <- [0x00e0004000 - 0x00e2003fff] size 0x02000000 gran 0x0c mem |
| PCI: 05:05.0 done set resources |
| PCI: 05:05.1 10 <- [0x00e2008000 - 0x00e20087ff] size 0x00000800 gran 0x0b mem |
| PCI: 05:05.1 14 <- [0x00e0000000 - 0x00e0003fff] size 0x00004000 gran 0x0e mem |
| PCI: 05:05.2 10 <- [0x00e2005000 - 0x00e2005fff] size 0x00001000 gran 0x0c mem |
| PCI: 05:05.3 10 <- [0x00e2009000 - 0x00e20090ff] size 0x00000100 gran 0x08 mem |
| PCI: 05:05.4 10 <- [0x00e2006000 - 0x00e2006fff] size 0x00001000 gran 0x0c mem |
| PCI: 05:05.4 14 <- [0x00e2007000 - 0x00e2007fff] size 0x00001000 gran 0x0c mem |
| PNP: 002e.3 missing set_resources |
| PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PNP: 004e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io |
| PNP: 004e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 10 <- [0x0000004098 - 0x000000409f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x00000040a8 - 0x00000040ab] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x00000040a0 - 0x00000040a7] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x00000040ac - 0x00000040af] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000004080 - 0x000000408f] size 0x00000010 gran 0x04 io |
| PCI: 00:1f.2 24 <- [0x00e4445000 - 0x00e44453ff] size 0x00000400 gran 0x0a mem |
| Done setting resources. |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 468288 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 8086/27a0 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 8086/27a2 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:02.1 subsystem <- 8086/27a6 |
| PCI: 00:02.1 cmd <- 02 |
| PCI: 00:1b.0 subsystem <- 8086/27d8 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 8086/27d0 |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 8086/27d2 |
| PCI: 00:1c.1 cmd <- 106 |
| PCI: 00:1c.2 bridge ctrl <- 0003 |
| PCI: 00:1c.2 subsystem <- 8086/27d4 |
| PCI: 00:1c.2 cmd <- 100 |
| PCI: 00:1c.3 bridge ctrl <- 0003 |
| PCI: 00:1c.3 subsystem <- 8086/27d6 |
| PCI: 00:1c.3 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 8086/27c8 |
| PCI: 00:1d.0 cmd <- 01 |
| PCI: 00:1d.1 subsystem <- 8086/27c9 |
| PCI: 00:1d.1 cmd <- 01 |
| PCI: 00:1d.2 subsystem <- 8086/27ca |
| PCI: 00:1d.2 cmd <- 01 |
| PCI: 00:1d.3 subsystem <- 8086/27cb |
| PCI: 00:1d.3 cmd <- 01 |
| PCI: 00:1d.7 subsystem <- 8086/27cc |
| PCI: 00:1d.7 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0003 |
| PCI: 00:1e.0 cmd <- 107 |
| PCI: 00:1f.0 subsystem <- 8086/27b9 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 8086/27c4 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 8086/27da |
| PCI: 00:1f.3 cmd <- 101 |
| PCI: 02:00.0 cmd <- 02 |
| PCI: 04:00.0 cmd <- 03 |
| PCI: 05:05.0 bridge ctrl <- 0143 |
| PCI: 05:05.0 cmd <- 07 |
| PCI: 05:05.1 cmd <- 02 |
| PCI: 05:05.2 cmd <- 02 |
| PCI: 05:05.3 cmd <- 06 |
| PCI: 05:05.4 cmd <- 02 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 122924 exit 0 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 2314 usecs |
| CPU_CLUSTER: 0 init ... |
| CBFS: 'Master Header Locator' located CBFS at [200:400000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset bcc0 size 15000 |
| microcode: sig=0x6f6 pf=0x20 revision=0x0 |
| microcode: updated to revision 0xd1 date=2010-10-01 |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x000000007f400000 size 0x7f340000 type 6 |
| 0x000000007f400000 - 0x00000000d0000000 size 0x50c00000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 6/4. |
| MTRR: UC selected as default type. |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| MTRR: 1 base 0x000000007f400000 mask 0x0000000fffc00000 type 0 |
| MTRR: 2 base 0x000000007f800000 mask 0x0000000fff800000 type 0 |
| MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| CPU has 2 cores. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 1 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...done. |
| AP: slot 1 apic_id 1. |
| Waiting for 2nd SIPI to complete...done. |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 7f3a807d(00000000) |
| Installing SMM handler to 0x7f600000 |
| Loading module at 7f610000 with entry 7f61013a. filesize: 0xa50 memsize: 0x4a68 |
| Processing 42 relocs. Offset value of 0x7f610000 |
| Loading module at 7f608000 with entry 7f608000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x7f608000 |
| SMM Module: placing jmp sequence at 7f607c00 rel16 0x03fd |
| SMM Module: stub loaded at 7f608000. Will call 7f61013a(00000000) |
| Initializing Southbridge SMI... |
| |
| New SMBASE 0x7f600000 |
| In relocation handler: cpu 0 |
| New SMBASE=0x7f600000 |
| Relocation complete. |
| VMX status: enabled |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| IA32_FEATURE_CONTROL status: locked |
| New SMBASE 0x7f5ffc00 |
| In relocation handler: cpu 1 |
| New SMBASE=0x7f5ffc00 |
| Relocation complete. |
| Initializing CPU #0 |
| CPU: vendor Intel device 6f6 |
| CPU: family 06, model 0f, stepping 06 |
| Enabling cache |
| CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| Setting up local APIC... apic_id: 0x00 done. |
| CPU #0 initialized |
| Initializing CPU #1 |
| CPU: vendor Intel device 6f6 |
| CPU: family 06, model 0f, stepping 06 |
| Enabling cache |
| CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz. |
| Setting up local APIC... apic_id: 0x01 done. |
| CPU #1 initialized |
| bsp_do_flight_plan done after 124 msecs. |
| CPU 1 going down... |
| Initializing southbridge SMI... |
| SMI_STS: |
| GPE0_STS: GPIO15 GPIO11 GPIO1 GPIO0 |
| ALT_GP_SMI_STS: GPI11 GPI7 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| Locking SMM. |
| CPU_CLUSTER: 0 init finished in 335132 usecs |
| PCI: 00:02.0 init ... |
| Skipping native VGA initialization when resuming from ACPI S3. |
| PCI: 00:02.0 init finished in 7614 usecs |
| PCI: 00:02.1 init ... |
| PCI: 00:02.1 init finished in 2002 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: codec type: Azalia |
| Azalia: base = e4440000 |
| Azalia: codec_mask = 03 |
| Azalia: Initializing codec #1 |
| Azalia: codec viddid: 14f12c06 |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 10ec0262 |
| Azalia: verb_size: 52 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 30485 usecs |
| PCI: 00:1c.0 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.0 init finished in 4803 usecs |
| PCI: 00:1c.1 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.1 init finished in 4802 usecs |
| PCI: 00:1c.2 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.2 init finished in 4802 usecs |
| PCI: 00:1c.3 init ... |
| Initializing ICH7 PCIe bridge. |
| PCI: 00:1c.3 init finished in 4802 usecs |
| PCI: 00:1d.0 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 5226 usecs |
| PCI: 00:1d.1 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.1 init finished in 5226 usecs |
| PCI: 00:1d.2 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.2 init finished in 5226 usecs |
| PCI: 00:1d.3 init ... |
| UHCI: Setting up controller.. done. |
| PCI: 00:1d.3 init finished in 5226 usecs |
| PCI: 00:1d.7 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.7 init finished in 5232 usecs |
| PCI: 00:1e.0 init ... |
| PCI: 00:1e.0 init finished in 2012 usecs |
| PCI: 00:1f.0 init ... |
| i82801gx: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| Set power on after power failure. |
| NMI sources disabled. |
| rtc_failed = 0x0 |
| S3 wakeup, enabling ACPI via APMC |
| PCI: 00:1f.0 init finished in 23125 usecs |
| PCI: 00:1f.2 init ... |
| i82801gx_sata: initializing... |
| SATA controller in combined mode. |
| PCI: 00:1f.2 init finished in 7852 usecs |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 2002 usecs |
| PCI: 04:00.0 init ... |
| PCI: 04:00.0 init finished in 2001 usecs |
| PCI: 05:05.0 init ... |
| TI PCIxx12 init |
| PCI: 05:05.0 init finished in 3481 usecs |
| PCI: 05:05.1 init ... |
| PCI: 05:05.1 init finished in 2001 usecs |
| PCI: 05:05.2 init ... |
| PCI: 05:05.2 init finished in 2001 usecs |
| PCI: 05:05.3 init ... |
| PCI: 05:05.3 init finished in 2002 usecs |
| PCI: 05:05.4 init ... |
| PCI: 05:05.4 init finished in 2002 usecs |
| PNP: 002e.4 init ... |
| PNP: 002e.4 init finished in 1914 usecs |
| PNP: 004e.5 init ... |
| PNP: 004e.5 init finished in 1915 usecs |
| Devices initialized |
| BS: BS_DEV_INIT times (us): entry 7 run 574377 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 5237 exit 0 |
| Trying to find the wakeup vector... |
| Looking on 000f6250 for valid checksum |
| Checksum 1 passed |
| Checksum 2 passed all OK |
| RSDP found at 000f6250 |
| RSDT found at 7f353030 ends at 7f35306c |
| FADT found at 7f3571a0 |
| FACS found at 7f353240 |
| OS waking vector is 0009a1d0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 23066 exit 0 |
| Restore GNVS pointer to 7f3feae0 |
| |