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review.coreboot.org / board-status / 8eb9cf0a82f5ced6af467437800a82481e837e30 / . / protectli / vault_bsw / 4.11-1387-g5dd4f5f206 / 2020-03-06T12_54_49Z / coreboot_console.txt
blob: ca5440988cdcdd72f700636d4286ac400fe3a782 [file] [log] [blame]
coreboot-4.11-1387-g5dd4f5f206 Fri Mar 6 12:54:49 UTC 2020 bootblock starting (log level: 8)...
RTC Init
FMAP: Found "FLASH" version 1.1 at 0x310000.
FMAP: base = 0xff800000 size = 0x800000 #areas = 4
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 7084
BS: bootblock times (exec / console): total (unknown) / 30 ms
coreboot-4.11-1387-g5dd4f5f206 Fri Mar 6 12:54:49 UTC 2020 romstage starting (log level: 8)...
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 40fdc0 size 4b100
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 7180 size 21c00
microcode: sig=0x406c4 pf=0x1 revision=0x411
microcode: Update skipped, already up-to-date
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using FSP 1.1
FSP_INFO_HEADER: 0xfff20094
FSP Signature: $BSWFSP$
FSP Header Version: 2
FSP Revision: 1.1.8.0
pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000
gpe0_sts: 00000000 gpe0_en: 00000000 tco_sts: 00000000
prsts: 00040910 gen_pmcon1: 00201a08 gen_pmcon2: 00000000
prev_sleep_state 0
FMAP: area RW_MRC_CACHE found @ 300000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
No MRC cache found.
VPD Data: 0xfff4b92c
UPD Data: 0xfff4b940
Updating UPD values for MemoryInit
Calling FspMemoryInit: 0xfff6a10f
0x00000000: NvsBufferPtr
0xfef01e28: RtBufferPtr
0xfef01dd0: HobListPtr
FspMemoryInit returned 0x00000000
Reserving 0x0000000000200000 bytes for FSP
0x00800000: smm_size
0x7d000000: smm_base
0x7d000000: cbmem_top
CBMEM:
IMD: root @ 0x7cfff000 254 entries.
IMD: root @ 0x7cffec00 62 entries.
External stage cache:
IMD: root @ 0x7d7ff000 254 entries.
IMD: root @ 0x7d7fec00 62 entries.
0x7cdfe000: fsp_reserved_memory_area
MRC data at 0x7ce1eed8 27760 bytes
CBMEM entry for DIMM info: 0x7cffe900
1 DIMMs found
Disable ROM shadow below 1MB.
SMM Memory Map
SMRAM : 0x7d000000 0x800000
Subregion 0: 0x7d000000 0x700000
Subregion 1: 0x7d700000 0x100000
Subregion 2: 0x7d800000 0x0
MTRR Range: Start=7c800000 End=7d000000 (Size 800000)
MTRR Range: Start=7d000000 End=7d800000 (Size 800000)
MTRR Range: Start=ff800000 End=0 (Size 800000)
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset 5bbc0 size 47fc
Decompressing stage fallback/postcar @ 0x7cdcbfc0 (34864 bytes)
Loading module at 0x7cdcc000 with entry 0x7cdcc000. filesize: 0x4510 memsize: 0x87f0
Processing 164 relocs. Offset value of 0x7adcc000
BS: romstage times (exec / console): total (unknown) / 201 ms
coreboot-4.11-1387-g5dd4f5f206 Fri Mar 6 12:54:49 UTC 2020 postcar starting (log level: 8)...
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 28e00 size 12313
Decompressing stage fallback/ramstage @ 0x7cd96fc0 (209144 bytes)
Loading module at 0x7cd97000 with entry 0x7cd97000. filesize: 0x24e88 memsize: 0x330b8
Processing 2665 relocs. Offset value of 0x7bf97000
BS: postcar times (exec / console): total (unknown) / 39 ms
coreboot-4.11-1387-g5dd4f5f206 Fri Mar 6 12:54:49 UTC 2020 ramstage starting (log level: 8)...
Normal boot.
src/soc/intel/braswell/chip.c/soc_init
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 7180 size 21c00
microcode: sig=0x406c4 pf=0x1 revision=0x411
Cpuid 000406c4 cpus 4 rid 35 step D1
msr(17) = 000000f090041c4e
msr(ce) = 0000060002001400
msr(66a) = 0000000000140602
msr(66c) = 000000001c1c1c1c
msr(66b) = 00000000003a2d2d
msr(66d) = 000000004e4e4e4e
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 40fdc0 size 4b100
Ignoring FSPP entry: ffffffff
Ignoring FSPP entry: ffffffff
FSP: Saving binary in cache
FSP_INFO_HEADER: 0x7cd48094
FSP Signature: $BSWFSP$
FSP Header Version: 2
FSP Revision: 1.1.8.0
0x7cd7392c: VPD Data
0x7cd73940: UPD Data
Updating UPD values for SiliconInit
Calling FspSiliconInit
Calling FspSiliconInit(0x7cdc0d0b) at 0x7cd9211d
FspSiliconInit returned 0x00000000
north
Write Pad: Base(fed8c400) - conf0 = 918200 conf1= 5c00000 gpio #- 0 pad # = 0
Write Pad: Base(fed8c408) - conf0 = 918200 conf1= 5c00000 gpio #- 1 pad # = 1
Write Pad: Base(fed8c410) - conf0 = 918200 conf1= 5c00000 gpio #- 2 pad # = 2
Write Pad: Base(fed8c418) - conf0 = 918200 conf1= 5c00000 gpio #- 3 pad # = 3
Write Pad: Base(fed8c420) - conf0 = 918200 conf1= 5c00000 gpio #- 4 pad # = 4
Write Pad: Base(fed8c428) - conf0 = 918200 conf1= 5c00000 gpio #- 5 pad # = 5
Write Pad: Base(fed8c430) - conf0 = 918200 conf1= 5c00000 gpio #- 6 pad # = 6
Write Pad: Base(fed8c438) - conf0 = 918200 conf1= 5c00000 gpio #- 7 pad # = 7
Write Pad: Base(fed8c440) - conf0 = 918200 conf1= 5c00000 gpio #- 8 pad # = 8
Write Pad: Base(fed8c800) - conf0 = 8c108200 conf1= 5c00001 gpio #- 15 pad # = 9
Write Pad: Base(fed8c808) - conf0 = 108102 conf1= 5c00000 gpio #- 16 pad # = 10
Write Pad: Base(fed8c810) - conf0 = 110300 conf1= 5c00000 gpio #- 17 pad # = 11
Write Pad: Base(fed8c818) - conf0 = fc908200 conf1= 5c00001 gpio #- 18 pad # = 12
Write Pad: Base(fed8c820) - conf0 = 110300 conf1= 5c00000 gpio #- 19 pad # = 13
Write Pad: Base(fed8c828) - conf0 = 918200 conf1= 5c00000 gpio #- 20 pad # = 14
Write Pad: Base(fed8c830) - conf0 = 2c108200 conf1= 5c00002 gpio #- 21 pad # = 15
Write Pad: Base(fed8c838) - conf0 = 910300 conf1= 5c00000 gpio #- 22 pad # = 16
Write Pad: Base(fed8c840) - conf0 = 38908200 conf1= 5c00004 gpio #- 23 pad # = 17
Write Pad: Base(fed8c848) - conf0 = 910300 conf1= 5c00000 gpio #- 24 pad # = 18
Write Pad: Base(fed8c850) - conf0 = ec908200 conf1= 5c00001 gpio #- 25 pad # = 19
Write Pad: Base(fed8c858) - conf0 = 10300 conf1= 5c00000 gpio #- 26 pad # = 20
Write Pad: Base(fed8c860) - conf0 = 118200 conf1= 5c00000 gpio #- 27 pad # = 21
Write Pad: Base(fed8cc00) - conf0 = 10300 conf1= 5c00000 gpio #- 30 pad # = 22
Write Pad: Base(fed8cc08) - conf0 = 10300 conf1= 5c00000 gpio #- 31 pad # = 23
Write Pad: Base(fed8cc20) - conf0 = 10300 conf1= 5c00000 gpio #- 34 pad # = 26
Write Pad: Base(fed8cc28) - conf0 = 918200 conf1= 5c00000 gpio #- 35 pad # = 27
Write Pad: Base(fed8cc30) - conf0 = 918200 conf1= 5c00000 gpio #- 36 pad # = 28
Write Pad: Base(fed8cc38) - conf0 = 10300 conf1= 5c00000 gpio #- 37 pad # = 29
Write Pad: Base(fed8cc48) - conf0 = 10300 conf1= 5c00000 gpio #- 39 pad # = 31
Write Pad: Base(fed8cc58) - conf0 = 10300 conf1= 5c00000 gpio #- 41 pad # = 33
Write Pad: Base(fed8d000) - conf0 = 918200 conf1= 5c00000 gpio #- 45 pad # = 34
Write Pad: Base(fed8d008) - conf0 = 918200 conf1= 5c00000 gpio #- 46 pad # = 35
Write Pad: Base(fed8d010) - conf0 = 918200 conf1= 5c00000 gpio #- 47 pad # = 36
Write Pad: Base(fed8d018) - conf0 = 918200 conf1= 5c00000 gpio #- 48 pad # = 37
Write Pad: Base(fed8d020) - conf0 = 918200 conf1= 5c00000 gpio #- 49 pad # = 38
Write Pad: Base(fed8d028) - conf0 = 918200 conf1= 5c00000 gpio #- 50 pad # = 39
Write Pad: Base(fed8d030) - conf0 = 918200 conf1= 5c00000 gpio #- 51 pad # = 40
Write Pad: Base(fed8d038) - conf0 = 918200 conf1= 5c00000 gpio #- 52 pad # = 41
Write Pad: Base(fed8d040) - conf0 = 918200 conf1= 5c00000 gpio #- 53 pad # = 42
Write Pad: Base(fed8d048) - conf0 = 918200 conf1= 5c00000 gpio #- 54 pad # = 43
Write Pad: Base(fed8d050) - conf0 = 918200 conf1= 5c00000 gpio #- 55 pad # = 44
Write Pad: Base(fed8d058) - conf0 = 918200 conf1= 5c00000 gpio #- 56 pad # = 45
Write Pad: Base(fed8d400) - conf0 = 918200 conf1= 5c00000 gpio #- 60 pad # = 46
Write Pad: Base(fed8d408) - conf0 = 3010000 conf1= 5c00020 gpio #- 61 pad # = 47
Write Pad: Base(fed8d410) - conf0 = c10300 conf1= 5c00000 gpio #- 62 pad # = 48
Write Pad: Base(fed8d418) - conf0 = 918200 conf1= 5c00000 gpio #- 63 pad # = 49
Write Pad: Base(fed8d420) - conf0 = 918200 conf1= 5c00000 gpio #- 64 pad # = 50
Write Pad: Base(fed8d428) - conf0 = 918200 conf1= 5c00000 gpio #- 65 pad # = 51
Write Pad: Base(fed8d430) - conf0 = c10300 conf1= 5c00000 gpio #- 66 pad # = 52
Write Pad: Base(fed8d438) - conf0 = c10300 conf1= 5c00000 gpio #- 67 pad # = 53
Write Pad: Base(fed8d440) - conf0 = 3010000 conf1= 5c00020 gpio #- 68 pad # = 54
Write Pad: Base(fed8d448) - conf0 = 918200 conf1= 5c00000 gpio #- 69 pad # = 55
Write Pad: Base(fed8d450) - conf0 = 918200 conf1= 5c00000 gpio #- 70 pad # = 56
Write Pad: Base(fed8d458) - conf0 = c10300 conf1= 5c00000 gpio #- 71 pad # = 57
Write Pad: Base(fed8d460) - conf0 = 918200 conf1= 5c00000 gpio #- 72 pad # = 58
gpio_wake_mask0 = 200 gpio_wake_mask1 = 0 gpio_int_mask = c10c
southwest
Write Pad: Base(fed84400) - conf0 = 910300 conf1= 5c00000 gpio #- 0 pad # = 0
Write Pad: Base(fed84408) - conf0 = 910300 conf1= 5c00000 gpio #- 1 pad # = 1
Write Pad: Base(fed84410) - conf0 = 910300 conf1= 5c00000 gpio #- 2 pad # = 2
Write Pad: Base(fed84418) - conf0 = 910300 conf1= 5c00000 gpio #- 3 pad # = 3
Write Pad: Base(fed84420) - conf0 = 908102 conf1= 5c00000 gpio #- 4 pad # = 4
Write Pad: Base(fed84428) - conf0 = 910300 conf1= 5c00000 gpio #- 5 pad # = 5
Write Pad: Base(fed84430) - conf0 = 910300 conf1= 5c00000 gpio #- 6 pad # = 6
Write Pad: Base(fed84438) - conf0 = 908102 conf1= 5c00000 gpio #- 7 pad # = 7
Write Pad: Base(fed84800) - conf0 = 918200 conf1= 5c00000 gpio #- 15 pad # = 8
Write Pad: Base(fed84808) - conf0 = 918200 conf1= 5c00000 gpio #- 16 pad # = 9
Write Pad: Base(fed84810) - conf0 = 918200 conf1= 5c00000 gpio #- 17 pad # = 10
Write Pad: Base(fed84818) - conf0 = 918200 conf1= 5c00000 gpio #- 18 pad # = 11
Write Pad: Base(fed84820) - conf0 = 918200 conf1= 5c00000 gpio #- 19 pad # = 12
Write Pad: Base(fed84828) - conf0 = 918200 conf1= 5c00000 gpio #- 20 pad # = 13
Write Pad: Base(fed84830) - conf0 = 918200 conf1= 5c00000 gpio #- 21 pad # = 14
Write Pad: Base(fed84838) - conf0 = 918200 conf1= 5c00000 gpio #- 22 pad # = 15
Write Pad: Base(fed84c00) - conf0 = 120300 conf1= 5c00000 gpio #- 30 pad # = 16
Write Pad: Base(fed84c08) - conf0 = 120300 conf1= 5c00000 gpio #- 31 pad # = 17
Write Pad: Base(fed84c10) - conf0 = 120300 conf1= 5c00000 gpio #- 32 pad # = 18
Write Pad: Base(fed84c18) - conf0 = 120300 conf1= 5c00000 gpio #- 33 pad # = 19
Write Pad: Base(fed84c20) - conf0 = 108102 conf1= 5c00000 gpio #- 34 pad # = 20
Write Pad: Base(fed84c28) - conf0 = 120300 conf1= 5c00000 gpio #- 35 pad # = 21
Write Pad: Base(fed84c30) - conf0 = 120300 conf1= 5c00000 gpio #- 36 pad # = 22
Write Pad: Base(fed84c38) - conf0 = 118200 conf1= 5c00000 gpio #- 37 pad # = 23
Write Pad: Base(fed85000) - conf0 = 918200 conf1= 5c00000 gpio #- 45 pad # = 24
Write Pad: Base(fed85008) - conf0 = 918200 conf1= 5c00000 gpio #- 46 pad # = 25
Write Pad: Base(fed85010) - conf0 = 918200 conf1= 5c00000 gpio #- 47 pad # = 26
Write Pad: Base(fed85018) - conf0 = 918200 conf1= 5c00000 gpio #- 48 pad # = 27
Write Pad: Base(fed85020) - conf0 = 918200 conf1= 5c00000 gpio #- 49 pad # = 28
Write Pad: Base(fed85028) - conf0 = 918200 conf1= 5c00000 gpio #- 50 pad # = 29
Write Pad: Base(fed85030) - conf0 = 918200 conf1= 5c00000 gpio #- 51 pad # = 30
Write Pad: Base(fed85038) - conf0 = 918200 conf1= 5c00000 gpio #- 52 pad # = 31
Write Pad: Base(fed85400) - conf0 = 918200 conf1= 5c00000 gpio #- 60 pad # = 32
Write Pad: Base(fed85408) - conf0 = 918200 conf1= 5c00000 gpio #- 61 pad # = 33
Write Pad: Base(fed85410) - conf0 = 918200 conf1= 5c00000 gpio #- 62 pad # = 34
Write Pad: Base(fed85418) - conf0 = 918200 conf1= 5c00000 gpio #- 63 pad # = 35
Write Pad: Base(fed85420) - conf0 = 918200 conf1= 5c00000 gpio #- 64 pad # = 36
Write Pad: Base(fed85428) - conf0 = 918200 conf1= 5c00000 gpio #- 65 pad # = 37
Write Pad: Base(fed85430) - conf0 = 918200 conf1= 5c00000 gpio #- 66 pad # = 38
Write Pad: Base(fed85438) - conf0 = 918200 conf1= 5c00000 gpio #- 67 pad # = 39
Write Pad: Base(fed85800) - conf0 = 918200 conf1= 5c00000 gpio #- 75 pad # = 40
Write Pad: Base(fed85808) - conf0 = 918200 conf1= 5c00000 gpio #- 76 pad # = 41
Write Pad: Base(fed85810) - conf0 = 10300 conf1= 5c00000 gpio #- 77 pad # = 42
Write Pad: Base(fed85818) - conf0 = 918200 conf1= 5c00000 gpio #- 78 pad # = 43
Write Pad: Base(fed85820) - conf0 = 910300 conf1= 5c00000 gpio #- 79 pad # = 44
Write Pad: Base(fed85828) - conf0 = 918200 conf1= 5c00000 gpio #- 80 pad # = 45
Write Pad: Base(fed85830) - conf0 = 910300 conf1= 5c00000 gpio #- 81 pad # = 46
Write Pad: Base(fed85838) - conf0 = 910300 conf1= 5c00000 gpio #- 82 pad # = 47
Write Pad: Base(fed85c00) - conf0 = 918200 conf1= 5c00000 gpio #- 90 pad # = 48
Write Pad: Base(fed85c08) - conf0 = 918200 conf1= 5c00000 gpio #- 91 pad # = 49
Write Pad: Base(fed85c10) - conf0 = 918200 conf1= 5c00000 gpio #- 92 pad # = 50
Write Pad: Base(fed85c18) - conf0 = 918200 conf1= 5c00000 gpio #- 93 pad # = 51
Write Pad: Base(fed85c20) - conf0 = 918200 conf1= 5c00000 gpio #- 94 pad # = 52
Write Pad: Base(fed85c28) - conf0 = 918200 conf1= 5c00000 gpio #- 95 pad # = 53
Write Pad: Base(fed85c30) - conf0 = 918200 conf1= 5c00000 gpio #- 96 pad # = 54
Write Pad: Base(fed85c38) - conf0 = 918200 conf1= 5c00000 gpio #- 97 pad # = 55
gpio_wake_mask0 = 0 gpio_wake_mask1 = 0 gpio_int_mask = 0
southeast
Write Pad: Base(fed9c400) - conf0 = 918200 conf1= 5c00000 gpio #- 0 pad # = 0
Write Pad: Base(fed9c408) - conf0 = 918200 conf1= 5c00000 gpio #- 1 pad # = 1
Write Pad: Base(fed9c410) - conf0 = 918200 conf1= 5c00000 gpio #- 2 pad # = 2
Write Pad: Base(fed9c418) - conf0 = 918200 conf1= 5c00000 gpio #- 3 pad # = 3
Write Pad: Base(fed9c420) - conf0 = 918200 conf1= 5c00000 gpio #- 4 pad # = 4
Write Pad: Base(fed9c428) - conf0 = 918200 conf1= 5c00000 gpio #- 5 pad # = 5
Write Pad: Base(fed9c430) - conf0 = 918200 conf1= 5c00000 gpio #- 6 pad # = 6
Write Pad: Base(fed9c438) - conf0 = 918200 conf1= 5c00000 gpio #- 7 pad # = 7
Write Pad: Base(fed9c800) - conf0 = 918200 conf1= 5c00000 gpio #- 15 pad # = 8
Write Pad: Base(fed9c808) - conf0 = 918200 conf1= 5c00000 gpio #- 16 pad # = 9
Write Pad: Base(fed9c810) - conf0 = 918200 conf1= 5c00000 gpio #- 17 pad # = 10
Write Pad: Base(fed9c818) - conf0 = 918200 conf1= 5c00000 gpio #- 18 pad # = 11
Write Pad: Base(fed9c820) - conf0 = 918200 conf1= 5c00000 gpio #- 19 pad # = 12
Write Pad: Base(fed9c828) - conf0 = 918200 conf1= 5c00000 gpio #- 20 pad # = 13
Write Pad: Base(fed9c830) - conf0 = 918200 conf1= 5c00000 gpio #- 21 pad # = 14
Write Pad: Base(fed9c838) - conf0 = 918200 conf1= 5c00000 gpio #- 22 pad # = 15
Write Pad: Base(fed9c840) - conf0 = 918200 conf1= 5c00000 gpio #- 23 pad # = 16
Write Pad: Base(fed9c848) - conf0 = 918200 conf1= 5c00000 gpio #- 24 pad # = 17
Write Pad: Base(fed9c850) - conf0 = 918200 conf1= 5c00000 gpio #- 25 pad # = 18
Write Pad: Base(fed9c858) - conf0 = 918200 conf1= 5c00000 gpio #- 26 pad # = 19
Write Pad: Base(fed9cc00) - conf0 = 918200 conf1= 5c00000 gpio #- 30 pad # = 20
Write Pad: Base(fed9cc08) - conf0 = 918200 conf1= 5c00000 gpio #- 31 pad # = 21
Write Pad: Base(fed9cc10) - conf0 = 918200 conf1= 5c00000 gpio #- 32 pad # = 22
Write Pad: Base(fed9cc18) - conf0 = 918200 conf1= 5c00000 gpio #- 33 pad # = 23
Write Pad: Base(fed9cc20) - conf0 = 918200 conf1= 5c00000 gpio #- 34 pad # = 24
Write Pad: Base(fed9cc28) - conf0 = 918200 conf1= 5c00000 gpio #- 35 pad # = 25
Write Pad: Base(fed9d000) - conf0 = 910300 conf1= 5c00000 gpio #- 45 pad # = 26
Write Pad: Base(fed9d008) - conf0 = 910300 conf1= 5c00000 gpio #- 46 pad # = 27
Write Pad: Base(fed9d010) - conf0 = 910300 conf1= 5c00000 gpio #- 47 pad # = 28
Write Pad: Base(fed9d018) - conf0 = 10300 conf1= 5c00000 gpio #- 48 pad # = 29
Write Pad: Base(fed9d020) - conf0 = 10300 conf1= 5c00000 gpio #- 49 pad # = 30
Write Pad: Base(fed9d028) - conf0 = 910300 conf1= 5c00000 gpio #- 50 pad # = 31
Write Pad: Base(fed9d030) - conf0 = 10300 conf1= 5c00000 gpio #- 51 pad # = 32
Write Pad: Base(fed9d038) - conf0 = 910300 conf1= 5c00000 gpio #- 52 pad # = 33
Write Pad: Base(fed9d400) - conf0 = 918200 conf1= 5c00000 gpio #- 60 pad # = 34
Write Pad: Base(fed9d408) - conf0 = 918200 conf1= 5c00000 gpio #- 61 pad # = 35
Write Pad: Base(fed9d410) - conf0 = 918200 conf1= 5c00000 gpio #- 62 pad # = 36
Write Pad: Base(fed9d418) - conf0 = 918200 conf1= 5c00000 gpio #- 63 pad # = 37
Write Pad: Base(fed9d420) - conf0 = 918200 conf1= 5c00000 gpio #- 64 pad # = 38
Write Pad: Base(fed9d428) - conf0 = 918200 conf1= 5c00000 gpio #- 65 pad # = 39
Write Pad: Base(fed9d430) - conf0 = 918200 conf1= 5c00000 gpio #- 66 pad # = 40
Write Pad: Base(fed9d438) - conf0 = 918200 conf1= 5c00000 gpio #- 67 pad # = 41
Write Pad: Base(fed9d440) - conf0 = 918200 conf1= 5c00000 gpio #- 68 pad # = 42
Write Pad: Base(fed9d448) - conf0 = 918200 conf1= 5c00000 gpio #- 69 pad # = 43
Write Pad: Base(fed9d800) - conf0 = 10300 conf1= 5c00000 gpio #- 75 pad # = 44
Write Pad: Base(fed9d808) - conf0 = 10300 conf1= 5c00000 gpio #- 76 pad # = 45
Write Pad: Base(fed9d810) - conf0 = 4008200 conf1= 5c00003 gpio #- 77 pad # = 46
Write Pad: Base(fed9d818) - conf0 = 918200 conf1= 5c00000 gpio #- 78 pad # = 47
Write Pad: Base(fed9d820) - conf0 = 910300 conf1= 5c00000 gpio #- 79 pad # = 48
Write Pad: Base(fed9d828) - conf0 = 910300 conf1= 5c00000 gpio #- 80 pad # = 49
Write Pad: Base(fed9d830) - conf0 = 918200 conf1= 5c00000 gpio #- 81 pad # = 50
Write Pad: Base(fed9d838) - conf0 = 10300 conf1= 5c00000 gpio #- 82 pad # = 51
Write Pad: Base(fed9d840) - conf0 = 10300 conf1= 5c00000 gpio #- 83 pad # = 52
Write Pad: Base(fed9d848) - conf0 = 110300 conf1= 5c00000 gpio #- 84 pad # = 53
Write Pad: Base(fed9d850) - conf0 = 918200 conf1= 5c00000 gpio #- 85 pad # = 54
gpio_wake_mask0 = 0 gpio_wake_mask1 = 0 gpio_int_mask = 1
east
Write Pad: Base(fed94400) - conf0 = 910300 conf1= 5c00000 gpio #- 0 pad # = 0
Write Pad: Base(fed94408) - conf0 = 910300 conf1= 5c00000 gpio #- 1 pad # = 1
Write Pad: Base(fed94410) - conf0 = 910300 conf1= 5c00000 gpio #- 2 pad # = 2
Write Pad: Base(fed94418) - conf0 = 910300 conf1= 5c00000 gpio #- 3 pad # = 3
Write Pad: Base(fed94420) - conf0 = 110300 conf1= 5c00000 gpio #- 4 pad # = 4
Write Pad: Base(fed94428) - conf0 = 910300 conf1= 5c00000 gpio #- 5 pad # = 5
Write Pad: Base(fed94430) - conf0 = 110300 conf1= 5c00000 gpio #- 6 pad # = 6
Write Pad: Base(fed94438) - conf0 = 910300 conf1= 5c00000 gpio #- 7 pad # = 7
Write Pad: Base(fed94440) - conf0 = 910300 conf1= 5c00000 gpio #- 8 pad # = 8
Write Pad: Base(fed94448) - conf0 = 910300 conf1= 5c00000 gpio #- 9 pad # = 9
Write Pad: Base(fed94450) - conf0 = 8c10000 conf1= 5c00000 gpio #- 10 pad # = 10
Write Pad: Base(fed94458) - conf0 = 918200 conf1= 5c00000 gpio #- 11 pad # = 11
Write Pad: Base(fed94800) - conf0 = 918200 conf1= 5c00000 gpio #- 15 pad # = 12
Write Pad: Base(fed94808) - conf0 = 918200 conf1= 5c00000 gpio #- 16 pad # = 13
Write Pad: Base(fed94810) - conf0 = 918200 conf1= 5c00000 gpio #- 17 pad # = 14
Write Pad: Base(fed94818) - conf0 = 918200 conf1= 5c00000 gpio #- 18 pad # = 15
Write Pad: Base(fed94820) - conf0 = 918200 conf1= 5c00000 gpio #- 19 pad # = 16
Write Pad: Base(fed94828) - conf0 = 918200 conf1= 5c00000 gpio #- 20 pad # = 17
Write Pad: Base(fed94830) - conf0 = 918200 conf1= 5c00000 gpio #- 21 pad # = 18
Write Pad: Base(fed94838) - conf0 = 918200 conf1= 5c00000 gpio #- 22 pad # = 19
Write Pad: Base(fed94840) - conf0 = 918200 conf1= 5c00000 gpio #- 23 pad # = 20
Write Pad: Base(fed94848) - conf0 = 918200 conf1= 5c00000 gpio #- 24 pad # = 21
Write Pad: Base(fed94850) - conf0 = 918200 conf1= 5c00000 gpio #- 25 pad # = 22
Write Pad: Base(fed94858) - conf0 = 918200 conf1= 5c00000 gpio #- 26 pad # = 23
gpio_wake_mask0 = 0 gpio_wake_mask1 = 0 gpio_int_mask = 0
Routing SW and N gpios
gpio_rout = 6002 alt_gpio_smi = 800000 gpe0a_en = 410000
Tri-state TDO and TMS
BS: BS_DEV_INIT_CHIPS run times (exec / console): 145 / 1456 ms
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
DOMAIN: 0000: enabled 1
APIC: 00: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:0b.0: enabled 0
PCI: 00:10.0: enabled 0
PCI: 00:12.0: enabled 0
PCI: 00:13.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:18.0: enabled 0
PCI: 00:18.1: enabled 0
PCI: 00:18.2: enabled 0
PCI: 00:18.3: enabled 0
PCI: 00:18.4: enabled 0
PCI: 00:18.5: enabled 0
PCI: 00:18.6: enabled 0
PCI: 00:18.7: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1e.3: enabled 0
PCI: 00:1e.4: enabled 0
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.a: enabled 0
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:0b.0: enabled 0
PCI: 00:10.0: enabled 0
PCI: 00:12.0: enabled 0
PCI: 00:13.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:18.0: enabled 0
PCI: 00:18.1: enabled 0
PCI: 00:18.2: enabled 0
PCI: 00:18.3: enabled 0
PCI: 00:18.4: enabled 0
PCI: 00:18.5: enabled 0
PCI: 00:18.6: enabled 0
PCI: 00:18.7: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1e.3: enabled 0
PCI: 00:1e.4: enabled 0
PCI: 00:1f.0: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:1f.3: enabled 1
Root Device scanning...
scan_static_bus for Root Device
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 7
vendor: 0x8086. device: 0x2280
class: 0x06 Bridge
subclass: 0x00 Host bridge
prog: 0x00
revision: 0x35
CPU_CLUSTER: 0 enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 6
vendor: 0x8086. device: 0x2280
class: 0x06 Bridge
subclass: 0x00 Host bridge
prog: 0x00
revision: 0x35
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x2280
class: 0x06 Bridge
subclass: 0x00 Host bridge
prog: 0x00
revision: 0x35
PCI: 00:00.0 [8086/2280] ops
PCI: 00:00.0 [8086/2280] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22b1
class: 0x03 Display
subclass: 0x00 VGA compatible controller
prog: 0x00
revision: 0x35
PCI: 00:02.0 [8086/22b1] ops
PCI: 00:02.0 [8086/22b1] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:03.0: Disabling device: 03.0
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
Could not place 03.0 into D3Hot. Keeping device visible.
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:0b.0: Disabling device: 0b.0
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
Could not place 0b.0 into D3Hot. Keeping device visible.
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:10.0: Disabling device: 10.0
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:12.0: Disabling device: 12.0
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22a3
class: 0x01 Mass storage
subclass: 0x06 SATA controller
prog: 0x01
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:13.0 [8086/0000] ops
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:13.0 [8086/22a3] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22b5
class: 0x0c Serial bus
subclass: 0x03 USB controller
prog: 0x30
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:14.0 [8086/22b5] ops
PCI: 00:14.0 [8086/22b5] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.0: Disabling device: 18.0
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c1
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.1: Disabling device: 18.1
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.1 [8086/0000] ops
PCI: 00:18.1 [8086/22c1] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c2
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.2: Disabling device: 18.2
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.2 [8086/0000] ops
PCI: 00:18.2 [8086/22c2] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c3
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.3: Disabling device: 18.3
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.3 [8086/0000] ops
PCI: 00:18.3 [8086/22c3] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c4
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.4: Disabling device: 18.4
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.4 [8086/0000] ops
PCI: 00:18.4 [8086/22c4] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c5
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.5: Disabling device: 18.5
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.5 [8086/0000] ops
PCI: 00:18.5 [8086/22c5] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c6
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.6: Disabling device: 18.6
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.6 [8086/0000] ops
PCI: 00:18.6 [8086/22c6] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c7
class: 0x0c Serial bus
subclass: 0x80 Serial Bus Controller
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:18.7: Disabling device: 18.7
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
PCI: 00:18.7 [8086/0000] ops
PCI: 00:18.7 [8086/22c7] disabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: Static device PCI: 00:1a.0 not found, disabling it.
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x2284
class: 0x04 Multimedia
subclass: 0x03 Audio device
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1b.0 [8086/0000] bus ops
PCI: 00:1b.0 [8086/2284] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22c8
class: 0x06 Bridge
subclass: 0x04 PCI bridge
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.0 [8086/0000] bus ops
src/soc/intel/braswell/pcie.c/pcie_enable (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_port_enabled (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_device_present (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.0 [8086/22c8] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22ca
class: 0x06 Bridge
subclass: 0x04 PCI bridge
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.1 [8086/0000] bus ops
src/soc/intel/braswell/pcie.c/pcie_enable (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_port_enabled (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_device_present (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.1 [8086/22ca] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22cc
class: 0x06 Bridge
subclass: 0x04 PCI bridge
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.2 [8086/0000] bus ops
src/soc/intel/braswell/pcie.c/pcie_enable (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_port_enabled (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_device_present (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.2 [8086/22cc] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x22ce
class: 0x06 Bridge
subclass: 0x04 PCI bridge
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.3 [8086/0000] bus ops
src/soc/intel/braswell/pcie.c/pcie_enable (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_port_enabled (Intel Braswell SoC)
src/soc/intel/braswell/pcie.c/check_device_present (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1c.3 [8086/22ce] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1e.0: Disabling device: 1e.0
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1e.3: Disabling device: 1e.3
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0xffff. device: 0xffff
class: 0xff Unassigned class
subclass: 0xff ???
prog: 0xff
revision: 0xff
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1e.4: Disabling device: 1e.4
src/soc/intel/braswell/southcluster.c/place_device_in_d3hot (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/set_d3hot_bits (Intel Braswell SoC, 0x00000080)
Power management CAP offset 0x80.
src/soc/intel/braswell/southcluster.c/sc_disable_devfn (Intel Braswell SoC)
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x229c
class: 0x06 Bridge
subclass: 0x01 ISA bridge
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1f.0 [8086/229c] bus ops
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1f.0 [8086/229c] enabled
----------
src/soc/intel/braswell/chip.c/enable_dev (Intel Braswell SoC), type: 2
vendor: 0x8086. device: 0x2292
class: 0x0c Serial bus
subclass: 0x05 SMBus
prog: 0x00
revision: 0x35
src/soc/intel/braswell/southcluster.c/southcluster_enable_dev (Intel Braswell SoC)
PCI: 00:1f.3 [8086/2292] enabled
PCI: Leftover static devices:
PCI: 00:03.0
PCI: 00:0b.0
PCI: 00:10.0
PCI: 00:12.0
PCI: 00:18.0
PCI: 00:1a.0
PCI: 00:1e.0
PCI: 00:1e.3
PCI: 00:1e.4
PCI: Check your devicetree.cb.
PCI: 00:1b.0 scanning...
scan_bus: bus PCI: 00:1b.0 finished in 0 msecs
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [8086/157b] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 01:00.0
scan_bus: bus PCI: 00:1c.0 finished in 25 msecs
PCI: 00:1c.1 scanning...
do_pci_scan_bridge for PCI: 00:1c.1
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [8086/157b] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 02:00.0
scan_bus: bus PCI: 00:1c.1 finished in 25 msecs
PCI: 00:1c.2 scanning...
do_pci_scan_bridge for PCI: 00:1c.2
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [8086/157b] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 03:00.0
scan_bus: bus PCI: 00:1c.2 finished in 25 msecs
PCI: 00:1c.3 scanning...
do_pci_scan_bridge for PCI: 00:1c.3
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [8086/157b] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 04:00.0
scan_bus: bus PCI: 00:1c.3 finished in 25 msecs
PCI: 00:1f.0 scanning...
scan_static_bus for PCI: 00:1f.0
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.4 disabled
PNP: 002e.5 disabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.a disabled
scan_static_bus for PCI: 00:1f.0 done
scan_bus: bus PCI: 00:1f.0 finished in 19 msecs
scan_bus: bus DOMAIN: 0000 finished in 1444 msecs
scan_static_bus for Root Device done
scan_bus: bus Root Device finished in 1495 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 1680 ms
FMAP: area RW_MRC_CACHE found @ 300000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
Manufacturer: c2
SF: Detected c2 2537 with sector size 0x1000, total 0x800000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
BS: BS_DEV_ENUMERATE exit times (exec / console): 131 / 23 ms
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.1 read_resources bus 2 link: 0
PCI: 00:1c.1 read_resources bus 2 link: 0 done
PCI: 00:1c.2 read_resources bus 3 link: 0
PCI: 00:1c.2 read_resources bus 3 link: 0 done
PCI: 00:1c.3 read_resources bus 4 link: 0
PCI: 00:1c.3 read_resources bus 4 link: 0 done
src/soc/intel/braswell/southcluster.c/sc_read_resources (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/sc_add_mmio_resources (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000feb00000, 0x0000000000100000)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fed03000, 0x0000000000000400)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fed80000, 0x0000000000040000)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fed08000, 0x0000000000002000)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fed01000, 0x0000000000000400)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fea00000, 0x0000000000100000)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fed06000, 0x0000000000000800)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fed1c000, 0x0000000000000400)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000ff800000, 0x0000000000800000)
src/soc/intel/braswell/southcluster.c/add_mmio_resource (Intel Braswell SoC, 0x00000000fec00000, 0x0000000000001000)
src/soc/intel/braswell/southcluster.c/sc_add_io_resources (Intel Braswell SoC)
src/soc/intel/braswell/southcluster.c/sc_add_io_resource (Intel Braswell SoC, 0x00000500, 0x00000100, 0x00000048)
src/soc/intel/braswell/southcluster.c/sc_add_io_resource (Intel Braswell SoC, 0x00000400, 0x00000080, 0x00000040)
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 002e.1 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 27
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI: 00:00.0 resource base 100000 size 7ccfe000 align 0 gran 0 limit 0 flags e0004200 index 1
PCI: 00:00.0 resource base 7cdfe000 size a02000 align 0 gran 0 limit 0 flags f0004200 index 2
PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3
PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 4
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6
PCI: 00:00.0 resource base fee00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:13.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
PCI: 00:14.0
PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:18.6
PCI: 00:18.7
PCI: 00:1b.0
PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:1c.0 child on link 0 PCI: 01:00.0
PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:1c.1 child on link 0 PCI: 02:00.0
PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 02:00.0
PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 02:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:1c.2 child on link 0 PCI: 03:00.0
PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:1c.3 child on link 0 PCI: 04:00.0
PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:1f.0 child on link 0 PNP: 002e.0
PCI: 00:1f.0 resource base feb00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index feb
PCI: 00:1f.0 resource base fed03000 size 400 align 0 gran 0 limit 0 flags f0000200 index 44
PCI: 00:1f.0 resource base fed80000 size 40000 align 0 gran 0 limit 0 flags f0000200 index 4c
PCI: 00:1f.0 resource base fed08000 size 2000 align 0 gran 0 limit 0 flags f0000200 index 50
PCI: 00:1f.0 resource base fed01000 size 400 align 0 gran 0 limit 0 flags f0000200 index 54
PCI: 00:1f.0 resource base fea00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 58
PCI: 00:1f.0 resource base fed06000 size 800 align 0 gran 0 limit 0 flags f0000200 index 5c
PCI: 00:1f.0 resource base fed1c000 size 400 align 0 gran 0 limit 0 flags f0000200 index f0
PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index fff
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index fec
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
PNP: 002e.0
PNP: 002e.1
PNP: 002e.1 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 002e.1 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.4
PNP: 002e.5
PNP: 002e.6
PNP: 002e.7
PNP: 002e.a
PCI: 00:1f.3
PCI: 00:1f.3 resource base 0 size 20 align 12 gran 5 limit ffffffff flags 200 index 10
PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 18 * [0x0 - 0x1f] io
PCI: 00:1c.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 02:00.0 18 * [0x0 - 0x1f] io
PCI: 00:1c.1 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 03:00.0 18 * [0x0 - 0x1f] io
PCI: 00:1c.2 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 04:00.0 18 * [0x0 - 0x1f] io
PCI: 00:1c.3 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 1c * [0x0 - 0xfff] io
PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io
PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io
PCI: 00:1c.3 1c * [0x3000 - 0x3fff] io
PCI: 00:02.0 20 * [0x4000 - 0x403f] io
PCI: 00:13.0 20 * [0x4040 - 0x405f] io
PCI: 00:1f.3 20 * [0x4060 - 0x407f] io
DOMAIN: 0000 io: base: 4080 size: 4080 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 01:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:1c.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 02:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:1c.1 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:1c.2 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem
PCI: 00:1c.3 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
PCI: 00:1c.0 20 * [0x11000000 - 0x110fffff] mem
PCI: 00:1c.1 20 * [0x11100000 - 0x111fffff] mem
PCI: 00:1c.2 20 * [0x11200000 - 0x112fffff] mem
PCI: 00:1c.3 20 * [0x11300000 - 0x113fffff] mem
PCI: 00:14.0 10 * [0x11400000 - 0x1140ffff] mem
PCI: 00:1b.0 10 * [0x11410000 - 0x11413fff] mem
PCI: 00:13.0 24 * [0x11414000 - 0x114147ff] mem
PCI: 00:1f.3 10 * [0x11415000 - 0x1141501f] mem
DOMAIN: 0000 mem: base: 11415020 size: 11415020 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 27 base e0000000 limit efffffff mem (fixed)
constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
constrain_resources: PCI: 00:00.0 01 base 00100000 limit 7cdfdfff mem (fixed)
constrain_resources: PCI: 00:00.0 02 base 7cdfe000 limit 7d7fffff mem (fixed)
constrain_resources: PCI: 00:00.0 03 base 7d800000 limit 7fffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
skipping PNP: 002e.1@60 fixed resource, size=0!
skipping PNP: 002e.1@70 fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:4080 align:12 gran:0 limit:ffff
PCI: 00:1c.0 1c * [0x1000 - 0x1fff] io
PCI: 00:1c.1 1c * [0x2000 - 0x2fff] io
PCI: 00:1c.2 1c * [0x3000 - 0x3fff] io
PCI: 00:1c.3 1c * [0x4000 - 0x4fff] io
PCI: 00:02.0 20 * [0x5000 - 0x503f] io
PCI: 00:13.0 20 * [0x5040 - 0x505f] io
PCI: 00:1f.3 20 * [0x5060 - 0x507f] io
DOMAIN: 0000 io: next_base: 5080 size: 4080 align: 12 gran: 0 done
PCI: 00:1c.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
PCI: 01:00.0 18 * [0x1000 - 0x101f] io
PCI: 00:1c.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.1 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 02:00.0 18 * [0x2000 - 0x201f] io
PCI: 00:1c.1 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.2 io: base:3000 size:1000 align:12 gran:12 limit:3fff
PCI: 03:00.0 18 * [0x3000 - 0x301f] io
PCI: 00:1c.2 io: next_base: 3020 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.3 io: base:4000 size:1000 align:12 gran:12 limit:4fff
PCI: 04:00.0 18 * [0x4000 - 0x401f] io
PCI: 00:1c.3 io: next_base: 4020 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:c0000000 size:11415020 align:28 gran:0 limit:dfffffff
PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
PCI: 00:1c.0 20 * [0xd1000000 - 0xd10fffff] mem
PCI: 00:1c.1 20 * [0xd1100000 - 0xd11fffff] mem
PCI: 00:1c.2 20 * [0xd1200000 - 0xd12fffff] mem
PCI: 00:1c.3 20 * [0xd1300000 - 0xd13fffff] mem
PCI: 00:14.0 10 * [0xd1400000 - 0xd140ffff] mem
PCI: 00:1b.0 10 * [0xd1410000 - 0xd1413fff] mem
PCI: 00:13.0 24 * [0xd1414000 - 0xd14147ff] mem
PCI: 00:1f.3 10 * [0xd1415000 - 0xd141501f] mem
DOMAIN: 0000 mem: next_base: d1415020 size: 11415020 align: 28 gran: 0 done
PCI: 00:1c.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:1c.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
PCI: 01:00.0 10 * [0xd1000000 - 0xd101ffff] mem
PCI: 01:00.0 1c * [0xd1020000 - 0xd1023fff] mem
PCI: 00:1c.0 mem: next_base: d1024000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.1 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:1c.1 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 mem: base:d1100000 size:100000 align:20 gran:20 limit:d11fffff
PCI: 02:00.0 10 * [0xd1100000 - 0xd111ffff] mem
PCI: 02:00.0 1c * [0xd1120000 - 0xd1123fff] mem
PCI: 00:1c.1 mem: next_base: d1124000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.2 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:1c.2 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.2 mem: base:d1200000 size:100000 align:20 gran:20 limit:d12fffff
PCI: 03:00.0 10 * [0xd1200000 - 0xd121ffff] mem
PCI: 03:00.0 1c * [0xd1220000 - 0xd1223fff] mem
PCI: 00:1c.2 mem: next_base: d1224000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.3 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:1c.3 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 mem: base:d1300000 size:100000 align:20 gran:20 limit:d13fffff
PCI: 04:00.0 10 * [0xd1300000 - 0xd131ffff] mem
PCI: 04:00.0 1c * [0xd1320000 - 0xd1323fff] mem
PCI: 00:1c.3 mem: next_base: d1324000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
src/soc/intel/braswell/chip.c/pci_domain_set_resources (Intel Braswell SoC)
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 missing set_resources
PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000005000 - 0x000000503f] size 0x00000040 gran 0x06 io
PCI: 00:13.0 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io
PCI: 00:13.0 24 <- [0x00d1414000 - 0x00d14147ff] size 0x00000800 gran 0x0b mem
PCI: 00:14.0 10 <- [0x00d1400000 - 0x00d140ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:1b.0 10 <- [0x00d1410000 - 0x00d1413fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d101ffff] size 0x00020000 gran 0x11 mem
PCI: 01:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 01:00.0 1c <- [0x00d1020000 - 0x00d1023fff] size 0x00004000 gran 0x0e mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.1 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00d1100000 - 0x00d111ffff] size 0x00020000 gran 0x11 mem
PCI: 02:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 02:00.0 1c <- [0x00d1120000 - 0x00d1123fff] size 0x00004000 gran 0x0e mem
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 00:1c.2 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:1c.2 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.2 20 <- [0x00d1200000 - 0x00d12fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:1c.2 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00d1200000 - 0x00d121ffff] size 0x00020000 gran 0x11 mem
PCI: 03:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
PCI: 03:00.0 1c <- [0x00d1220000 - 0x00d1223fff] size 0x00004000 gran 0x0e mem
PCI: 00:1c.2 assign_resources, bus 3 link: 0
PCI: 00:1c.3 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:1c.3 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:1c.3 20 <- [0x00d1300000 - 0x00d13fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:1c.3 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00d1300000 - 0x00d131ffff] size 0x00020000 gran 0x11 mem
PCI: 04:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io
PCI: 04:00.0 1c <- [0x00d1320000 - 0x00d1323fff] size 0x00004000 gran 0x0e mem
PCI: 00:1c.3 assign_resources, bus 4 link: 0
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.1 missing set_resources
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.3 10 <- [0x00d1415000 - 0x00d141501f] size 0x00000020 gran 0x05 mem
PCI: 00:1f.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 1000 size 4080 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base c0000000 size 11415020 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 27
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI: 00:00.0 resource base 100000 size 7ccfe000 align 0 gran 0 limit 0 flags e0004200 index 1
PCI: 00:00.0 resource base 7cdfe000 size a02000 align 0 gran 0 limit 0 flags f0004200 index 2
PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3
PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 4
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6
PCI: 00:00.0 resource base fee00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:02.0
PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
PCI: 00:02.0 resource base 5000 size 40 align 6 gran 6 limit 503f flags 60000100 index 20
PCI: 00:13.0
PCI: 00:13.0 resource base 5040 size 20 align 5 gran 5 limit 505f flags 60000100 index 20
PCI: 00:13.0 resource base d1414000 size 800 align 12 gran 11 limit d14147ff flags 60000200 index 24
PCI: 00:14.0
PCI: 00:14.0 resource base d1400000 size 10000 align 16 gran 16 limit d140ffff flags 60000201 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:18.6
PCI: 00:18.7
PCI: 00:1b.0
PCI: 00:1b.0 resource base d1410000 size 4000 align 14 gran 14 limit d1413fff flags 60000201 index 10
PCI: 00:1c.0 child on link 0 PCI: 01:00.0
PCI: 00:1c.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:1c.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base d1000000 size 20000 align 17 gran 17 limit d101ffff flags 60000200 index 10
PCI: 01:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
PCI: 01:00.0 resource base d1020000 size 4000 align 14 gran 14 limit d1023fff flags 60000200 index 1c
PCI: 00:1c.1 child on link 0 PCI: 02:00.0
PCI: 00:1c.1 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
PCI: 00:1c.1 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:1c.1 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60080202 index 20
PCI: 02:00.0
PCI: 02:00.0 resource base d1100000 size 20000 align 17 gran 17 limit d111ffff flags 60000200 index 10
PCI: 02:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
PCI: 02:00.0 resource base d1120000 size 4000 align 14 gran 14 limit d1123fff flags 60000200 index 1c
PCI: 00:1c.2 child on link 0 PCI: 03:00.0
PCI: 00:1c.2 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
PCI: 00:1c.2 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:1c.2 resource base d1200000 size 100000 align 20 gran 20 limit d12fffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base d1200000 size 20000 align 17 gran 17 limit d121ffff flags 60000200 index 10
PCI: 03:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18
PCI: 03:00.0 resource base d1220000 size 4000 align 14 gran 14 limit d1223fff flags 60000200 index 1c
PCI: 00:1c.3 child on link 0 PCI: 04:00.0
PCI: 00:1c.3 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
PCI: 00:1c.3 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:1c.3 resource base d1300000 size 100000 align 20 gran 20 limit d13fffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base d1300000 size 20000 align 17 gran 17 limit d131ffff flags 60000200 index 10
PCI: 04:00.0 resource base 4000 size 20 align 5 gran 5 limit 401f flags 60000100 index 18
PCI: 04:00.0 resource base d1320000 size 4000 align 14 gran 14 limit d1323fff flags 60000200 index 1c
PCI: 00:1f.0 child on link 0 PNP: 002e.0
PCI: 00:1f.0 resource base feb00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index feb
PCI: 00:1f.0 resource base fed03000 size 400 align 0 gran 0 limit 0 flags f0000200 index 44
PCI: 00:1f.0 resource base fed80000 size 40000 align 0 gran 0 limit 0 flags f0000200 index 4c
PCI: 00:1f.0 resource base fed08000 size 2000 align 0 gran 0 limit 0 flags f0000200 index 50
PCI: 00:1f.0 resource base fed01000 size 400 align 0 gran 0 limit 0 flags f0000200 index 54
PCI: 00:1f.0 resource base fea00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 58
PCI: 00:1f.0 resource base fed06000 size 800 align 0 gran 0 limit 0 flags f0000200 index 5c
PCI: 00:1f.0 resource base fed1c000 size 400 align 0 gran 0 limit 0 flags f0000200 index f0
PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index fff
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index fec
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
PNP: 002e.0
PNP: 002e.1
PNP: 002e.1 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 002e.1 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.4
PNP: 002e.5
PNP: 002e.6
PNP: 002e.7
PNP: 002e.a
PCI: 00:1f.3
PCI: 00:1f.3 resource base d1415000 size 20 align 12 gran 5 limit d141501f flags 60000200 index 10
PCI: 00:1f.3 resource base 5060 size 20 align 5 gran 5 limit 507f flags 60000100 index 20
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 4 / 2340 ms
Calling FspNotify(0x00000020)
BS: BS_DEV_RESOURCES exit times (exec / console): 0 / 3 ms
Enabling resources...
PCI: 00:02.0 subsystem <- 8086/22b1
PCI: 00:02.0 cmd <- 03
PCI: 00:13.0 subsystem <- 8086/22a3
PCI: 00:13.0 cmd <- 107
PCI: 00:14.0 subsystem <- 8086/22b5
PCI: 00:14.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 8086/2284
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 8086/22c8
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.1 bridge ctrl <- 0013
PCI: 00:1c.1 subsystem <- 8086/22ca
PCI: 00:1c.1 cmd <- 107
PCI: 00:1c.2 bridge ctrl <- 0013
PCI: 00:1c.2 subsystem <- 8086/22cc
PCI: 00:1c.2 cmd <- 107
PCI: 00:1c.3 bridge ctrl <- 0013
PCI: 00:1c.3 subsystem <- 8086/22ce
PCI: 00:1c.3 cmd <- 107
PCI: 00:1f.3 subsystem <- 8086/2292
PCI: 00:1f.3 cmd <- 103
PCI: 01:00.0 cmd <- 03
PCI: 02:00.0 cmd <- 03
PCI: 03:00.0 cmd <- 03
PCI: 04:00.0 cmd <- 03
done.
BS: BS_DEV_ENABLE run times (exec / console): 0 / 72 ms
Initializing devices...
Root Device init
Root Device init finished in 0 msecs
CPU_CLUSTER: 0 init
src/soc/intel/braswell/cpu.c/soc_init_cpus (Intel Braswell SoC)
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007d800000 size 0x7d740000 type 6
0x000000007d800000 - 0x00000000c0000000 size 0x42800000 type 0
0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 6/5.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x000000007d800000 mask 0x0000000fff800000 type 0
MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff0000000 type 1
MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Turbo is available and visible
Setting up SMI for CPU
Will perform SMM setup.
CPU: Intel(R) Celeron(R) CPU J3160 @ 1.60GHz.
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 3 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...AP: slot 1 apic_id 2.
done.
AP: slot 3 apic_id 4.
Waiting for 2nd SIPI to complete...done.
AP: slot 2 apic_id 6.
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b0 memsize: 0x1b0
Processing 13 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 0x00038000. Will call 0x7cda95f6(0x00000000)
Installing SMM handler to 0x7d000000
Loading module at 0x7d010000 with entry 0x7d010056. filesize: 0x508 memsize: 0x4518
Processing 23 relocs. Offset value of 0x7d010000
Loading module at 0x7d008000 with entry 0x7d008000. filesize: 0x1b0 memsize: 0x1b0
Processing 13 relocs. Offset value of 0x7d008000
SMM Module: placing jmp sequence at 0x7d007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 0x7d007800 rel16 0x07fd
SMM Module: placing jmp sequence at 0x7d007400 rel16 0x0bfd
SMM Module: stub loaded at 0x7d008000. Will call 0x7d010056(0x00000000)
Initializing Southbridge SMI... pmbase = 0x0400
SMI_STS: PM1
PM1_STS: TMROF
New SMBASE 0x7d000000
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0x7cfffc00
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0x7cfff400
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0x7cfff800
Relocation complete.
microcode: Update skipped, already up-to-date
Initializing CPU #0
CPU: vendor Intel device 406c4
CPU: family 06, model 4c, stepping 04
src/soc/intel/braswell/cpu.c/soc_core_init (Intel(R) Celeron(R) CPU J3160 @ 1.60GHz)
Init Braswell core.
Setting up local APIC...
apic_id: 0x00 done.
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
CPU #0 initialized
Initializing CPU #1
Initializing CPU #3
CPU: vendor Intel device 406c4
CPU: family 06, model 4c, stepping 04
Initializing CPU #2
src/soc/intel/braswell/cpu.c/soc_core_init (Intel(R) Celeron(R) CPU J3160 @ 1.60GHz)
Init Braswell core.
Setting up local APIC...
CPU: vendor Intel device 406c4
apic_id: 0x02 done.
CPU: vendor Intel device 406c4
Turbo is available and visible
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
CPU: family 06, model 4c, stepping 04
CPU #1 initialized
CPU: family 06, model 4c, stepping 04
src/soc/intel/braswell/cpu.c/soc_core_init (Intel(R) Celeron(R) CPU J3160 @ 1.60GHz)
Init Braswell core.
Setting up local APIC...
src/soc/intel/braswell/cpu.c/soc_core_init (Intel(R) Celeron(R) CPU J3160 @ 1.60GHz)
Init Braswell core.
Setting up local APIC...
apic_id: 0x06 done.
apic_id: 0x04 done.
Turbo is available and visible
Turbo is available and visible
VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
CPU #2 initialized
CPU #3 initialized
bsp_do_flight_plan done after 237 msecs.
Enabling SMIs.
GPIO_ROUT = 00006002
ALT_GPIO_SMI = 00000080
CPU_CLUSTER: 0 init finished in 472 msecs
PCI: 00:02.0 init
src/soc/intel/braswell/gfx.c/gfx_init (Intel Braswell SoC)
src/soc/intel/braswell/gfx.c/gfx_pre_vbios_init (Intel Braswell SoC)
GFX: Pre VBIOS Init
src/soc/intel/braswell/gfx.c/gfx_post_vbios_init (Intel Braswell SoC)
GFX: Post VBIOS Init
PCI: 00:02.0 init finished in 21 msecs
PCI: 00:13.0 init
src/soc/intel/braswell/sata.c/sata_init (Intel Braswell SoC)
PCI: 00:13.0 init finished in 5 msecs
PCI: 00:14.0 init
PCI: 00:14.0 init finished in 0 msecs
PCI: 00:1c.0 init
src/soc/intel/braswell/pcie.c/pcie_init (Intel Braswell SoC)
PCI: 00:1c.0 init finished in 5 msecs
PCI: 00:1c.1 init
src/soc/intel/braswell/pcie.c/pcie_init (Intel Braswell SoC)
PCI: 00:1c.1 init finished in 5 msecs
PCI: 00:1c.2 init
src/soc/intel/braswell/pcie.c/pcie_init (Intel Braswell SoC)
PCI: 00:1c.2 init finished in 5 msecs
PCI: 00:1c.3 init
src/soc/intel/braswell/pcie.c/pcie_init (Intel Braswell SoC)
PCI: 00:1c.3 init finished in 5 msecs
PCI: 00:1f.0 init
src/soc/intel/braswell/southcluster.c/sc_init (Intel Braswell SoC)
Enable serial irq
Disabling slp_x stretching.
PCI_CFG IRQ: Write PIRQ assignments
PCI IRQ: Found device 0:02.00 using PIN A
Warning: PCI Device 2 does not have an IRQ entry, skipping it
PCI IRQ: Found device 0:13.00 using PIN A
INT_PIN : 1 (PIN A)
PIRQ : D
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 0:14.00 using PIN A
INT_PIN : 1 (PIN A)
PIRQ : E
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 0:1B.00 using PIN A
INT_PIN : 1 (PIN A)
PIRQ : G
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 0:1C.00 using PIN A
INT_PIN : 1 (PIN A)
PIRQ : A
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 0:1C.01 using PIN B
INT_PIN : 2 (PIN B)
PIRQ : B
INT_LINE : 0x5 (IRQ 5)
PCI IRQ: Found device 0:1C.02 using PIN C
INT_PIN : 3 (PIN C)
PIRQ : C
INT_LINE : 0x5 (IRQ 5)
PCI IRQ: Found device 0:1C.03 using PIN D
INT_PIN : 4 (PIN D)
PIRQ : D
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 0:1F.03 using PIN B
INT_PIN : 2 (PIN B)
PIRQ : C
INT_LINE : 0x5 (IRQ 5)
PCI IRQ: Found device 1:00.00 using PIN A
With INT_PIN swizzled to PIN A
Attached to bridge device 0:1Ch.00h
INT_PIN : 1 (PIN A)
Swizzled to : 1 (PIN A)
PIRQ : A
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 2:00.00 using PIN A
With INT_PIN swizzled to PIN A
Attached to bridge device 0:1Ch.01h
INT_PIN : 1 (PIN A)
Swizzled to : 1 (PIN A)
PIRQ : A
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 3:00.00 using PIN A
With INT_PIN swizzled to PIN A
Attached to bridge device 0:1Ch.02h
INT_PIN : 1 (PIN A)
Swizzled to : 1 (PIN A)
PIRQ : A
INT_LINE : 0xB (IRQ 11)
PCI IRQ: Found device 4:00.00 using PIN A
With INT_PIN swizzled to PIN A
Attached to bridge device 0:1Ch.03h
INT_PIN : 1 (PIN A)
Swizzled to : 1 (PIN A)
PIRQ : A
INT_LINE : 0xB (IRQ 11)
PCI_CFG IRQ: Finished writing PIRQ assignments
PCI: 00:1f.0 init finished in 170 msecs
PCI: 00:1f.3 init
PCI: 00:1f.3 init finished in 0 msecs
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
PCI: 02:00.0 init
PCI: 02:00.0 init finished in 0 msecs
PCI: 03:00.0 init
PCI: 03:00.0 init finished in 0 msecs
PCI: 04:00.0 init
PCI: 04:00.0 init finished in 0 msecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
DOMAIN: 0000: enabled 1
APIC: 00: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:0b.0: enabled 0
PCI: 00:10.0: enabled 0
PCI: 00:12.0: enabled 0
PCI: 00:13.0: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:18.0: enabled 0
PCI: 00:18.1: enabled 0
PCI: 00:18.2: enabled 0
PCI: 00:18.3: enabled 0
PCI: 00:18.4: enabled 0
PCI: 00:18.5: enabled 0
PCI: 00:18.6: enabled 0
PCI: 00:18.7: enabled 0
PCI: 00:1a.0: enabled 0
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1e.3: enabled 0
PCI: 00:1e.4: enabled 0
PCI: 00:1f.0: enabled 1
PCI: 00:1f.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.a: enabled 0
PCI: 01:00.0: enabled 1
PCI: 02:00.0: enabled 1
PCI: 03:00.0: enabled 1
PCI: 04:00.0: enabled 1
APIC: 02: enabled 1
APIC: 06: enabled 1
APIC: 04: enabled 1
BS: BS_DEV_INIT run times (exec / console): 141 / 731 ms
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
src/soc/intel/braswell/southcluster.c/finalize_chipset (0x00000000)
BS: BS_POST_DEVICE exit times (exec / console): 0 / 6 ms
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 60400 size 2742
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7cd0c000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * FADT
SCI is IRQ9
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Turbo is available and visible
PSS: 1601MHz power 7000 control 0x1c4e status 0x1c4e
PSS: 1600MHz power 7000 control 0x143a status 0x143a
PSS: 1520MHz power 6570 control 0x1341 status 0x1341
PSS: 1440MHz power 6155 control 0x123f status 0x123f
PSS: 1360MHz power 5747 control 0x113e status 0x113e
PSS: 1280MHz power 5342 control 0x103c status 0x103c
PSS: 1200MHz power 4950 control 0xf3b status 0xf3b
PSS: 1120MHz power 4566 control 0xe39 status 0xe39
PSS: 1040MHz power 4190 control 0xd38 status 0xd38
PSS: 960MHz power 3826 control 0xc36 status 0xc36
PSS: 880MHz power 3465 control 0xb35 status 0xb35
PSS: 800MHz power 3111 control 0xa33 status 0xa33
PSS: 720MHz power 2765 control 0x932 status 0x932
PSS: 640MHz power 2430 control 0x830 status 0x830
PSS: 560MHz power 2099 control 0x72f status 0x72f
PSS: 480MHz power 1778 control 0x62d status 0x62d
Turbo is available and visible
PSS: 1601MHz power 7000 control 0x1c4e status 0x1c4e
PSS: 1600MHz power 7000 control 0x143a status 0x143a
PSS: 1520MHz power 6570 control 0x1341 status 0x1341
PSS: 1440MHz power 6155 control 0x123f status 0x123f
PSS: 1360MHz power 5747 control 0x113e status 0x113e
PSS: 1280MHz power 5342 control 0x103c status 0x103c
PSS: 1200MHz power 4950 control 0xf3b status 0xf3b
PSS: 1120MHz power 4566 control 0xe39 status 0xe39
PSS: 1040MHz power 4190 control 0xd38 status 0xd38
PSS: 960MHz power 3826 control 0xc36 status 0xc36
PSS: 880MHz power 3465 control 0xb35 status 0xb35
PSS: 800MHz power 3111 control 0xa33 status 0xa33
PSS: 720MHz power 2765 control 0x932 status 0x932
PSS: 640MHz power 2430 control 0x830 status 0x830
PSS: 560MHz power 2099 control 0x72f status 0x72f
PSS: 480MHz power 1778 control 0x62d status 0x62d
Turbo is available and visible
PSS: 1601MHz power 7000 control 0x1c4e status 0x1c4e
PSS: 1600MHz power 7000 control 0x143a status 0x143a
PSS: 1520MHz power 6570 control 0x1341 status 0x1341
PSS: 1440MHz power 6155 control 0x123f status 0x123f
PSS: 1360MHz power 5747 control 0x113e status 0x113e
PSS: 1280MHz power 5342 control 0x103c status 0x103c
PSS: 1200MHz power 4950 control 0xf3b status 0xf3b
PSS: 1120MHz power 4566 control 0xe39 status 0xe39
PSS: 1040MHz power 4190 control 0xd38 status 0xd38
PSS: 960MHz power 3826 control 0xc36 status 0xc36
PSS: 880MHz power 3465 control 0xb35 status 0xb35
PSS: 800MHz power 3111 control 0xa33 status 0xa33
PSS: 720MHz power 2765 control 0x932 status 0x932
PSS: 640MHz power 2430 control 0x830 status 0x830
PSS: 560MHz power 2099 control 0x72f status 0x72f
PSS: 480MHz power 1778 control 0x62d status 0x62d
Turbo is available and visible
PSS: 1601MHz power 7000 control 0x1c4e status 0x1c4e
PSS: 1600MHz power 7000 control 0x143a status 0x143a
PSS: 1520MHz power 6570 control 0x1341 status 0x1341
PSS: 1440MHz power 6155 control 0x123f status 0x123f
PSS: 1360MHz power 5747 control 0x113e status 0x113e
PSS: 1280MHz power 5342 control 0x103c status 0x103c
PSS: 1200MHz power 4950 control 0xf3b status 0xf3b
PSS: 1120MHz power 4566 control 0xe39 status 0xe39
PSS: 1040MHz power 4190 control 0xd38 status 0xd38
PSS: 960MHz power 3826 control 0xc36 status 0xc36
PSS: 880MHz power 3465 control 0xb35 status 0xb35
PSS: 800MHz power 3111 control 0xa33 status 0xa33
PSS: 720MHz power 2765 control 0x932 status 0x932
PSS: 640MHz power 2430 control 0x830 status 0x830
PSS: 560MHz power 2099 control 0x72f status 0x72f
PSS: 480MHz power 1778 control 0x62d status 0x62d
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * MADT
ACPI: added table 4/32, length now 52
current = 7cd0ff30
ACPI: * SSDT2 not generated.
current = 7cd0ff30
ACPI: done.
ACPI tables: 16176 bytes.
smbios_write_tables: 7cd0b000
Create SMBIOS type 17
SMBIOS tables: 645 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 830b
Writing coreboot table at 0x7cd30000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007cd0afff: RAM
4. 000000007cd0b000-000000007cd96fff: CONFIGURATION TABLES
5. 000000007cd97000-000000007cdcafff: RAMSTAGE
6. 000000007cdcb000-000000007cffffff: CONFIGURATION TABLES
7. 000000007d000000-000000007fffffff: RESERVED
8. 00000000e0000000-00000000efffffff: RESERVED
9. 00000000fea00000-00000000fec00fff: RESERVED
10. 00000000fed01000-00000000fed01fff: RESERVED
11. 00000000fed03000-00000000fed03fff: RESERVED
12. 00000000fed06000-00000000fed06fff: RESERVED
13. 00000000fed08000-00000000fed09fff: RESERVED
14. 00000000fed1c000-00000000fed1cfff: RESERVED
15. 00000000fed80000-00000000fedbffff: RESERVED
16. 00000000fee00000-00000000feefffff: RESERVED
17. 00000000ff800000-00000000ffffffff: RESERVED
18. 0000000100000000-000000017fffffff: RAM
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
Wrote coreboot table at: 0x7cd30000, 0x45c bytes, checksum 3f1d
coreboot table: 1140 bytes.
IMD ROOT 0. 0x7cfff000 0x00001000
IMD SMALL 1. 0x7cffe000 0x00001000
FSP MEMORY 2. 0x7cdfe000 0x00200000
CONSOLE 3. 0x7cdde000 0x00020000
TIME STAMP 4. 0x7cddd000 0x00000910
MRC DATA 5. 0x7cdd6000 0x00006c80
ROMSTG STCK 6. 0x7cdd5000 0x00001000
AFTER CAR 7. 0x7cdcb000 0x0000a000
RAMSTAGE 8. 0x7cd96000 0x00035000
ACPI GNVS 9. 0x7cd94000 0x000010a6
REFCODE 10. 0x7cd48000 0x0004b100
SMM BACKUP 11. 0x7cd38000 0x00010000
COREBOOT 12. 0x7cd30000 0x00008000
ACPI 13. 0x7cd0c000 0x00024000
SMBIOS 14. 0x7cd0b000 0x00000800
IMD small region:
IMD ROOT 0. 0x7cffec00 0x00000400
FMAP 1. 0x7cffeb20 0x000000e0
POWER STATE 2. 0x7cffeae0 0x00000024
FSP RUNTIME 3. 0x7cffeac0 0x00000008
MEM INFO 4. 0x7cffe900 0x000001b9
ROMSTAGE 5. 0x7cffe8e0 0x00000004
BS: BS_WRITE_TABLES run times (exec / console): 2 / 553 ms
FMAP: area COREBOOT found @ 310200 (5176832 bytes)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 62bc0 size 10f7b
Checking segment from ROM address 0xffb72df8
Payload being loaded at below 1MiB without region being marked as RAM usable.
Checking segment from ROM address 0xffb72e14
Loading segment from ROM address 0xffb72df8
code (compression=1)
New segment dstaddr 0x000dfc60 memsize 0x203a0 srcaddr 0xffb72e30 filesize 0x10f43
Loading Segment: addr: 0x000dfc60 memsz: 0x00000000000203a0 filesz: 0x0000000000010f43
using LZMA
[ 0x000dfc60, 00100000, 0x00100000) <- ffb72e30
Loading segment from ROM address 0xffb72e14
Entry Point 0x000fd263
Loaded segments
BS: BS_PAYLOAD_LOAD run times (exec / console): 31 / 60 ms
Calling FspNotify(0x00000040)
BS: BS_PAYLOAD_LOAD exit times (exec / console): 13 / 3 ms
Jumping to boot code at 0x000fd263(0x7cd30000)
CPU0: stack: 0x7cdc0000 - 0x7cdc1000, lowest used address 0x7cdc0a9c, stack used: 1380 bytes
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
BUILD: gcc: (coreboot toolchain v1.52 June 11th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30
Found coreboot cbmem console @ 7cdde000
Found mainboard Protectli FW4B
Relocating init from 0x000e1340 to 0x7ccbdd40 (size 53792)
Found CBFS header at 0xffb10238
multiboot: eax=7cdbb9e0, ebx=7cdbb9a4
Found 15 PCI devices (max PCI bus is 04)
Copying SMBIOS entry point from 0x7cd0b000 to 0x000f6280
Copying ACPI RSDP from 0x7cd0c000 to 0x000f6250
Using pmtimer, ioport 0x408
Scan for VGA option rom
Running option rom at c000:0003
sercon: using ioport 0x3f8
sercon: configuring in splitmode (vgabios c000:0014)
Turning on vga text mode console
XHCI init on dev 00:14.0: regs @ 0xd1400000, 13 ports, 32 slots, 32 byte contexts
XHCI protocol USB 2.00, 7 ports (offset 1), def 3011
XHCI protocol USB 3.00, 6 ports (offset 8), def 3000
XHCI extcap 0xc0 @ 0xd1408070
XHCI extcap 0x1 @ 0xd140846c
XHCI extcap 0xc6 @ 0xd14084f4
XHCI extcap 0xc7 @ 0xd1408500
XHCI extcap 0xc2 @ 0xd1408600
XHCI extcap 0xa @ 0xd1408700
XHCI extcap 0xc3 @ 0xd1408740
XHCI extcap 0xc4 @ 0xd1408800
XHCI extcap 0xc5 @ 0xd1408900
AHCI controller at 00:13.0, iobase 0xd1414000, irq 11
Found 0 lpt ports
Found 1 serial ports
Got ps2 nak (status=51)
XHCI no devices found
WARNING - Timeout at ahci_port_reset:326!
Searching bootorder for: /pci@i0cf8/*@13/drive@0/disk@0
AHCI/0: Set transfer mode to UDMA-6
Searching bios-geometry for: /pci@i0cf8/*@13/drive@0/disk@0
AHCI/0: registering: "AHCI/0: Hoodisk SSD ATA-11 Hard-Disk (30533 MiBytes)"
All threads complete.
Scan for option roms
Running option rom at d000:0003
pmm call arg1=1
pmm call arg1=0
pmm call arg1=1
pmm call arg1=0