|
|
|
|
| coreboot-4.0-5405-gdec9198 Sam Feb 1 18:40:13 CET 2014 starting...
|
| PM1_CNT: 00001c00
|
| SMBus controller enabled.
|
| Intel ME early init
|
| Intel ME firmware is ready
|
| ME: Requested 32MB UMA
|
| SMBus controller enabled.
|
| find_current_mrc_cache_local: No valid MRC cache found.
|
| Timings:
|
| channel 0, slot 0, rank 0
|
| lane 0: 20 (20) 73 (7e) 5e (5e) 7b (7b)
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| lane 1: 20 (20) 69 (74) 5e (5e) 7a (7a)
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| lane 2: 20 (20) 7b (86) 72 (72) 8e (8e)
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| lane 3: 20 (20) 58 (63) 49 (49) 66 (66)
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| lane 4: 20 (20) c3 (ce) a9 (a9) c4 (c4)
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| lane 5: 20 (20) a1 (ac) 7b (7b) 96 (96)
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| lane 6: 20 (20) b3 (be) 95 (95) b1 (b1)
|
| lane 7: 20 (20) ad (b8) 8a (8a) a5 (a5)
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| lane 8: 15 (20) 100 (10b) 80 (80) 80 (80)
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| channel 0, slot 0, rank 1
|
| lane 0: 20 (20) 72 (7d) 5e (5e) 7a (7a)
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| lane 1: 20 (20) 69 (74) 5d (5d) 79 (79)
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| lane 2: 20 (20) 7c (87) 72 (72) 8e (8e)
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| lane 3: 20 (20) 59 (64) 45 (45) 62 (62)
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| lane 4: 20 (20) c2 (cd) a9 (a9) c5 (c5)
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| lane 5: 20 (20) a0 (ab) 78 (78) 92 (92)
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| lane 6: 20 (20) b2 (bd) 94 (94) b1 (b1)
|
| lane 7: 20 (20) b0 (bb) 89 (89) a4 (a4)
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| lane 8: 15 (20) 100 (10b) 80 (80) 80 (80)
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| channel 1, slot 0, rank 0
|
| lane 0: 20 (20) 8d (98) 71 (71) 89 (89)
|
| lane 1: 20 (20) 8b (96) 6f (6f) 88 (88)
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| lane 2: 20 (20) 98 (a3) 7c (7c) 95 (95)
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| lane 3: 20 (20) 92 (9d) 82 (82) 9c (9c)
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| lane 4: 20 (20) ae (b9) 91 (91) aa (aa)
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| lane 5: 20 (20) b0 (bb) 89 (89) a2 (a2)
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| lane 6: 20 (20) bb (c6) 95 (95) ad (ad)
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| lane 7: 20 (20) ba (c5) 94 (94) ac (ac)
|
| lane 8: 15 (20) 100 (10b) 80 (80) 80 (80)
|
| [178] = 38 (0)
|
| [10b] = 0 (0)
|
| Timings:
|
| channel 0, slot 0, rank 0
|
| lane 0: 20 (20) 7e (7e) 5e (5e) 7b (7b)
|
| lane 1: 20 (20) 74 (74) 5e (5e) 7a (7a)
|
| lane 2: 20 (20) 86 (86) 72 (72) 8e (8e)
|
| lane 3: 20 (20) 63 (63) 49 (49) 66 (66)
|
| lane 4: 20 (20) ce (ce) a9 (a9) c4 (c4)
|
| lane 5: 20 (20) ac (ac) 7b (7b) 96 (96)
|
| lane 6: 20 (20) be (be) 95 (95) b1 (b1)
|
| lane 7: 20 (20) b8 (b8) 8a (8a) a5 (a5)
|
| lane 8: 15 (20) 100 (10b) 80 (80) 80 (80)
|
| channel 0, slot 0, rank 1
|
| lane 0: 20 (20) 7d (7d) 5e (5e) 7a (7a)
|
| lane 1: 20 (20) 74 (74) 5d (5d) 79 (79)
|
| lane 2: 20 (20) 87 (87) 72 (72) 8e (8e)
|
| lane 3: 20 (20) 64 (64) 45 (45) 62 (62)
|
| lane 4: 20 (20) cd (cd) a9 (a9) c5 (c5)
|
| lane 5: 20 (20) ab (ab) 78 (78) 92 (92)
|
| lane 6: 20 (20) bd (bd) 94 (94) b1 (b1)
|
| lane 7: 20 (20) bb (bb) 89 (89) a4 (a4)
|
| lane 8: 15 (20) 100 (10b) 80 (80) 80 (80)
|
| channel 1, slot 0, rank 0
|
| lane 0: 20 (20) 98 (98) 71 (71) 89 (89)
|
| lane 1: 20 (20) 96 (96) 6f (6f) 88 (88)
|
| lane 2: 20 (20) a3 (a3) 7c (7c) 95 (95)
|
| lane 3: 20 (20) 9d (9d) 82 (82) 9c (9c)
|
| lane 4: 20 (20) b9 (b9) 91 (91) aa (aa)
|
| lane 5: 20 (20) bb (bb) 89 (89) a2 (a2)
|
| lane 6: 20 (20) c6 (c6) 95 (95) ad (ad)
|
| lane 7: 20 (20) c5 (c5) 94 (94) ac (ac)
|
| lane 8: 15 (20) 100 (10b) 80 (80) 80 (80)
|
| [178] = 42 (0)
|
| [10b] = 0 (0)
|
| Timings:
|
| channel 0, slot 0, rank 0
|
| lane 0: 20 (20) 7e (7e) 5e (5e) 7b (7b)
|
| lane 1: 20 (20) 74 (74) 5e (5e) 7a (7a)
|
| lane 2: 20 (20) 86 (86) 72 (72) 8e (8e)
|
| lane 3: 20 (20) 63 (6 |
| |
| *** Log truncated, 35301 characters dropped. *** |
| |
| Adding CBMEM entry as no. 3
|
| Adding CBMEM entry as no. 4
|
| Relocate MRC DATA from ff7ff158 to b76e0600 (1472 bytes)
|
| ME: FW Partition Table : OK
|
| ME: Bringup Loader Failure : NO
|
| ME: Firmware Init Complete : NO
|
| ME: Manufacturing Mode : NO
|
| ME: Boot Options Present : NO
|
| ME: Update In Progress : NO
|
| ME: Current Working State : Normal
|
| ME: Current Operation State : Bring up
|
| ME: Current Operation Mode : Normal
|
| ME: Error Code : No Error
|
| ME: Progress Phase : BUP Phase
|
| ME: Power Management Event : Clean Moff->Mx wake
|
| ME: Progress Phase State : 0x41
|
| Loading image.
|
| CBFS: loading stage fallback/coreboot_ram @ 0x100000 (434232 bytes), entry @ 0x100000
|
| Jumping to image.
|
| coreboot-4.0-5405-gdec9198 Sam Feb 1 18:40:13 CET 2014 booting...
|
| clocks_per_usec: 2128
|
| BS: Entering BS_PRE_DEVICE state.
|
| BS: Exiting BS_PRE_DEVICE state.
|
| BS: Entering BS_DEV_INIT_CHIPS state.
|
| BS: Exiting BS_DEV_INIT_CHIPS state.
|
| BS: Entering BS_DEV_ENUMERATE state.
|
| Enumerating buses...
|
| Show all devs...Before device enumeration.
|
| Root Device: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.2: enabled 1
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.4: enabled 1
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1f.0: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| Compare with tree...
|
| Root Device: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.2: enabled 1
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.4: enabled 1
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1f.0: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| starting SPI configuration
|
| SPI configured
|
| ... pmbase = 0x0500
|
| Keyboard init...
|
| Keyboard controller output buffer result timeout
|
| scan_static_bus for Root Device
|
| PNP: 00ff.1 enabled
|
| recv_ec_data: 0x36
|
| recv_ec_data: 0x53
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x33
|
| recv_ec_data: 0x33
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x12
|
| recv_ec_data: 0x03
|
| recv_ec_data: 0x40
|
| recv_ec_data: 0x11
|
| EC Firmware ID 6SHT33WW-3.18, Version 4.01B
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0x10
|
| recv_ec_data: 0x20
|
| recv_ec_data: 0x30
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0xa6
|
| recv_ec_data: 0x01
|
| recv_ec_data: 0x70
|
| dock is not connected
|
| PNP: 00ff.2 enabled
|
| CPU_CLUSTER: 0 enabled
|
| DOMAIN: 0000 enabled
|
| DOMAIN: 0000 scanning...
|
| PCI: pci_scan_bus for bus 00
|
| PCI: 00:00.0 [8086/0044] ops
|
| Normal boot.
|
| PCI: 00:00.0 [8086/0044] enabled
|
| Capability: type 0x0d @ 0x88
|
| Capability: type 0x01 @ 0x80
|
| Capability: type 0x05 @ 0x90
|
| Capability: type 0x10 @ 0xa0
|
| Capability: type 0x0d @ 0x88
|
| Capability: type 0x01 @ 0x80
|
| Capability: type 0x05 @ 0x90
|
| Capability: type 0x10 @ 0xa0
|
| PCI: 00:01.0 subordinate bus PCI Express
|
| PCI: 00:01.0 [8086/0045] enabled
|
| PCI: 00:02.0 [8086/0000] ops
|
| PCI: 00:02.0 [8086/0046] enabled
|
| PCI: 00:16.0 [8086/0000] bus ops
|
| PCI: 00:16.0 [8086/3b64] enabled
|
| PCI: Static device PCI: 00:16.2 not found, disabling it.
|
| PCI: 00:19.0 [8086/10ea] enabled
|
| PCI: 00:1a.0 [8086/0000] ops
|
| PCI: 00:1a.0 [8086/3b3c] enabled
|
| PCI: 00:1b.0 [8086/0000] ops
|
| PCI: 00:1b.0 [8086/3b56] enabled
|
| Capability: type 0x10 @ 0x40
|
| Capability: type 0x05 @ 0x80
|
| Capability: type 0x0d @ 0x90
|
| Capability: type 0x01 @ 0xa0
|
| Capability: type 0x10 @ 0x40
|
| PCI: 00:1c.0 subordinate bus PCI Express
|
| PCI: 00:1c.0 [8086/3b42] enabled
|
| Capability: type 0x10 @ 0x40
|
| Capability: type 0x05 @ 0x80
|
| Capability: type 0x0d @ 0x90
|
| Capability: type 0x01 @ 0xa0
|
| Capability: type 0x10 @ 0x40
|
| PCI: 00:1c.3 subordinate bus PCI Express
|
| PCI: 00:1c.3 [8086/3b48] enabled
|
| Capability: type 0x10 @ 0x40
|
| Capability: type 0x05 @ 0x80
|
| Capability: type 0x0d @ 0x90
|
| Capability: type 0x01 @ 0xa0
|
| Capability: type 0x10 @ 0x40
|
| PCI: 00:1c.4 subordinate bus PCI Express
|
| PCI: 00:1c.4 [8086/3b4a] enabled
|
| PCI: 00:1d.0 [8086/0000] ops
|
| PCI: 00:1d.0 [8086/3b34] enabled
|
| PCI: 00:1e.0 [8086/2448] bus ops
|
| PCI: 00:1e.0 [8086/2448] enabled
|
| PCI: 00:1f.0 [8086/0000] bus ops
|
| PCI: 00:1f.0 [8086/3b07] enabled
|
| PCI: 00:1f.2 [8086/0000] ops
|
| PCI: 00:1f.2 [8086/3b2e] enabled
|
| PCI: 00:1f.3 [8086/0000] bus ops
|
| PCI: 00:1f.3 [8086/3b30] enabled
|
| PCI: 00:1f.6 [8086/0000] ops
|
| PCI: 00:1f.6 [8086/3b32] enabled
|
| do_pci_scan_bridge for PCI: 00:01.0
|
| PCI: pci_scan_bus for bus 01
|
| PCI: pci_scan_bus returning with max=001
|
| do_pci_scan_bridge returns max 1
|
| scan_static_bus for PCI: 00:16.0
|
| scan_static_bus for PCI: 00:16.0 done
|
| do_pci_scan_bridge for PCI: 00:1c.0
|
| PCI: pci_scan_bus for bus 02
|
| PCI: pci_scan_bus returning with max=002
|
| do_pci_scan_bridge returns max 2
|
| do_pci_scan_bridge for PCI: 00:1c.3
|
| PCI: pci_scan_bus for bus 03
|
| PCI: pci_scan_bus returning with max=003
|
| do_pci_scan_bridge returns max 3
|
| do_pci_scan_bridge for PCI: 00:1c.4
|
| PCI: pci_scan_bus for bus 04
|
| PCI: 04:00.0 [8086/4238] enabled
|
| PCI: pci_scan_bus returning with max=004
|
| Capability: type 0x01 @ 0xc8
|
| Capability: type 0x05 @ 0xd0
|
| Capability: type 0x10 @ 0xe0
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| do_pci_scan_bridge returns max 4
|
| do_pci_scan_bridge for PCI: 00:1e.0
|
| PCI: pci_scan_bus for bus 05
|
| PCI: pci_scan_bus returning with max=005
|
| do_pci_scan_bridge returns max 5
|
| scan_static_bus for PCI: 00:1f.0
|
| scan_static_bus for PCI: 00:1f.0 done
|
| scan_static_bus for PCI: 00:1f.3
|
| scan_static_bus for PCI: 00:1f.3 done
|
| PCI: pci_scan_bus returning with max=005
|
| scan_static_bus for Root Device done
|
| done
|
| BS: Exiting BS_DEV_ENUMERATE state.
|
| BS: Entering BS_DEV_RESOURCES state.
|
| found VGA at PCI: 00:02.0
|
| Setting up VGA for PCI: 00:02.0
|
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
| Allocating resources...
|
| Reading resources...
|
| Root Device read_resources bus 0 link: 0
|
| PNP: 00ff.1 missing read_resources
|
| PNP: 00ff.2 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
| APIC: 00 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0
|
| ram_before_4g_top: 0xb7800000
|
| TOUUD: 0xbc0
|
| CBMEM region b76d0000-b77fffff (cbmem_late_set_table)
|
| PCI: 00:01.0 read_resources bus 1 link: 0
|
| PCI: 00:01.0 read_resources bus 1 link: 0 done
|
| PCI: 00:1c.0 read_resources bus 2 link: 0
|
| PCI: 00:1c.0 read_resources bus 2 link: 0 done
|
| PCI: 00:1c.3 read_resources bus 3 link: 0
|
| PCI: 00:1c.3 read_resources bus 3 link: 0 done
|
| PCI: 00:1c.4 read_resources bus 4 link: 0
|
| PCI: 00:1c.4 read_resources bus 4 link: 0 done
|
| PCI: 00:1e.0 read_resources bus 5 link: 0
|
| PCI: 00:1e.0 read_resources bus 5 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0 done
|
| Root Device read_resources bus 0 link: 0 done
|
| Done reading resources.
|
| Show resources in subtree (Root Device)...After reading.
|
| Root Device child on link 0 PNP: 00ff.1
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
|
| PCI: 00:00.0 resource base c0000 size b7740000 align 0 gran 0 limit 0 flags e0004200 index 4
|
| PCI: 00:00.0 resource base b7800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
|
| PCI: 00:00.0 resource base b9c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 6
|
| PCI: 00:00.0 resource base ba000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index a
|
| PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index b
|
| PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
|
| PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
|
| PCI: 00:01.0
|
| PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
|
| PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.2
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
|
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.0
|
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.3
|
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.4 child on link 0 PCI: 04:00.0
|
| PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 04:00.0
|
| PCI: 04:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1f.0
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PCI: 00:1f.0 resource base 1680 size 1c align 0 gran 0 limit 0 flags c0040100 index 10000400
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
|
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
|
| PCI: 00:1f.3
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1f.6
|
| PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
|
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
| PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:19.0 18 * [0x0 - 0x1f] io
|
| PCI: 00:1f.2 20 * [0x20 - 0x3f] io
|
| PCI: 00:02.0 20 * [0x40 - 0x47] io
|
| PCI: 00:1f.2 10 * [0x48 - 0x4f] io
|
| PCI: 00:1f.2 18 * [0x50 - 0x57] io
|
| PCI: 00:1f.2 14 * [0x58 - 0x5b] io
|
| PCI: 00:1f.2 1c * [0x5c - 0x5f] io
|
| DOMAIN: 0000 compute_resources_io: base: 60 size: 60 align: 5 gran: 0 limit: ffff done
|
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
| PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 04:00.0 10 * [0x0 - 0x1fff] mem
|
| PCI: 00:1c.4 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:02.0 10 * [0x0 - 0x3fffff] mem
|
| PCI: 00:1c.4 20 * [0x400000 - 0x4fffff] mem
|
| PCI: 00:19.0 10 * [0x500000 - 0x51ffff] mem
|
| PCI: 00:1b.0 10 * [0x520000 - 0x523fff] mem
|
| PCI: 00:19.0 14 * [0x524000 - 0x524fff] mem
|
| PCI: 00:1f.6 10 * [0x525000 - 0x525fff] mem
|
| PCI: 00:1f.2 24 * [0x526000 - 0x5267ff] mem
|
| PCI: 00:1a.0 10 * [0x526800 - 0x526bff] mem
|
| PCI: 00:1d.0 10 * [0x526c00 - 0x526fff] mem
|
| PCI: 00:1f.3 10 * [0x527000 - 0x5270ff] mem
|
| PCI: 00:16.0 10 * [0x527100 - 0x52710f] mem
|
| DOMAIN: 0000 compute_resources_mem: base: 527110 size: 527110 align: 22 gran: 0 limit: ffffffff done
|
| avoid_fixed_resources: DOMAIN: 0000
|
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
| constrain_resources: DOMAIN: 0000
|
| constrain_resources: PCI: 00:00.0
|
| constrain_resources: PCI: 00:01.0
|
| constrain_resources: PCI: 00:02.0
|
| constrain_resources: PCI: 00:16.0
|
| constrain_resources: PCI: 00:19.0
|
| constrain_resources: PCI: 00:1a.0
|
| constrain_resources: PCI: 00:1b.0
|
| constrain_resources: PCI: 00:1c.0
|
| constrain_resources: PCI: 00:1c.3
|
| constrain_resources: PCI: 00:1c.4
|
| constrain_resources: PCI: 04:00.0
|
| constrain_resources: PCI: 00:1d.0
|
| constrain_resources: PCI: 00:1e.0
|
| constrain_resources: PCI: 00:1f.0
|
| constrain_resources: PCI: 00:1f.2
|
| constrain_resources: PCI: 00:1f.3
|
| constrain_resources: PCI: 00:1f.6
|
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
|
| lim->base 0000169c lim->limit 0000ffff
|
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
|
| lim->base bc000000 lim->limit cfffffff
|
| Setting resources...
|
| DOMAIN: 0000 allocate_resources_io: base:169c size:60 align:5 gran:0 limit:ffff
|
| Assigned: PCI: 00:19.0 18 * [0x1800 - 0x181f] io
|
| Assigned: PCI: 00:1f.2 20 * [0x1820 - 0x183f] io
|
| Assigned: PCI: 00:02.0 20 * [0x1840 - 0x1847] io
|
| Assigned: PCI: 00:1f.2 10 * [0x1848 - 0x184f] io
|
| Assigned: PCI: 00:1f.2 18 * [0x1850 - 0x1857] io
|
| Assigned: PCI: 00:1f.2 14 * [0x1858 - 0x185b] io
|
| Assigned: PCI: 00:1f.2 1c * [0x185c - 0x185f] io
|
| DOMAIN: 0000 allocate_resources_io: next_base: 1860 size: 60 align: 5 gran: 0 done
|
| PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| DOMAIN: 0000 allocate_resources_mem: base:cf800000 size:527110 align:22 gran:0 limit:cfffffff
|
| Assigned: PCI: 00:02.0 10 * [0xcf800000 - 0xcfbfffff] mem
|
| Assigned: PCI: 00:1c.4 20 * [0xcfc00000 - 0xcfcfffff] mem
|
| Assigned: PCI: 00:19.0 10 * [0xcfd00000 - 0xcfd1ffff] mem
|
| Assigned: PCI: 00:1b.0 10 * [0xcfd20000 - 0xcfd23fff] mem
|
| Assigned: PCI: 00:19.0 14 * [0xcfd24000 - 0xcfd24fff] mem
|
| Assigned: PCI: 00:1f.6 10 * [0xcfd25000 - 0xcfd25fff] mem
|
| Assigned: PCI: 00:1f.2 24 * [0xcfd26000 - 0xcfd267ff] mem
|
| Assigned: PCI: 00:1a.0 10 * [0xcfd26800 - 0xcfd26bff] mem
|
| Assigned: PCI: 00:1d.0 10 * [0xcfd26c00 - 0xcfd26fff] mem
|
| Assigned: PCI: 00:1f.3 10 * [0xcfd27000 - 0xcfd270ff] mem
|
| Assigned: PCI: 00:16.0 10 * [0xcfd27100 - 0xcfd2710f] mem
|
| DOMAIN: 0000 allocate_resources_mem: next_base: cfd27110 size: 527110 align: 22 gran: 0 done
|
| PCI: 00:01.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:01.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:01.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:01.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1c.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.3 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1c.3 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.3 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1c.3 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.4 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1c.4 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.4 allocate_resources_mem: base:cfc00000 size:100000 align:20 gran:20 limit:cfffffff
|
| Assigned: PCI: 04:00.0 10 * [0xcfc00000 - 0xcfc01fff] mem
|
| PCI: 00:1c.4 allocate_resources_mem: next_base: cfc02000 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1e.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1e.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1e.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
|
| PCI: 00:1e.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
|
| Root Device assign_resources, bus 0 link: 0
|
| PNP: 00ff.1 missing set_resources
|
| PNP: 00ff.2 missing set_resources
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
| PCI: 00:01.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
| PCI: 00:01.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 mem
|
| PCI: 00:02.0 10 <- [0x00cf800000 - 0x00cfbfffff] size 0x00400000 gran 0x16 mem64
|
| PCI: 00:02.0 20 <- [0x0000001840 - 0x0000001847] size 0x00000008 gran 0x03 io
|
| PCI: 00:16.0 10 <- [0x00cfd27100 - 0x00cfd2710f] size 0x00000010 gran 0x04 mem64
|
| PCI: 00:19.0 10 <- [0x00cfd00000 - 0x00cfd1ffff] size 0x00020000 gran 0x11 mem
|
| PCI: 00:19.0 14 <- [0x00cfd24000 - 0x00cfd24fff] size 0x00001000 gran 0x0c mem
|
| PCI: 00:19.0 18 <- [0x0000001800 - 0x000000181f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1a.0 10 <- [0x00cfd26800 - 0x00cfd26bff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1b.0 10 <- [0x00cfd20000 - 0x00cfd23fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
| PCI: 00:1c.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
| PCI: 00:1c.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 mem
|
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
|
| PCI: 00:1c.3 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
| PCI: 00:1c.3 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 mem
|
| PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
|
| PCI: 00:1c.4 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
|
| PCI: 00:1c.4 20 <- [0x00cfc00000 - 0x00cfcfffff] size 0x00100000 gran 0x14 bus 04 mem
|
| PCI: 00:1c.4 assign_resources, bus 4 link: 0
|
| PCI: 04:00.0 10 <- [0x00cfc00000 - 0x00cfc01fff] size 0x00002000 gran 0x0d mem64
|
| PCI: 00:1c.4 assign_resources, bus 4 link: 0
|
| PCI: 00:1d.0 10 <- [0x00cfd26c00 - 0x00cfd26fff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
|
| PCI: 00:1e.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
|
| PCI: 00:1e.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 mem
|
| PCI: 00:1f.2 10 <- [0x0000001848 - 0x000000184f] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 14 <- [0x0000001858 - 0x000000185b] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 18 <- [0x0000001850 - 0x0000001857] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 1c <- [0x000000185c - 0x000000185f] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 20 <- [0x0000001820 - 0x000000183f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1f.2 24 <- [0x00cfd26000 - 0x00cfd267ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1f.3 10 <- [0x00cfd27000 - 0x00cfd270ff] size 0x00000100 gran 0x08 mem64
|
| PCI: 00:1f.6 10 <- [0x00cfd25000 - 0x00cfd25fff] size 0x00001000 gran 0x0c mem64
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| Root Device assign_resources, bus 0 link: 0
|
| Done setting resources.
|
| Show resources in subtree (Root Device)...After assigning values.
|
| Root Device child on link 0 PNP: 00ff.1
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 169c size 60 align 5 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base cf800000 size 527110 align 22 gran 0 limit cfffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
|
| PCI: 00:00.0 resource base c0000 size b7740000 align 0 gran 0 limit 0 flags e0004200 index 4
|
| PCI: 00:00.0 resource base b7800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
|
| PCI: 00:00.0 resource base b9c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 6
|
| PCI: 00:00.0 resource base ba000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index a
|
| PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index b
|
| PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
|
| PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
|
| PCI: 00:01.0
|
| PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:01.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
|
| PCI: 00:01.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base cf800000 size 400000 align 22 gran 22 limit cfffffff flags 60000201 index 10
|
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
|
| PCI: 00:02.0 resource base 1840 size 8 align 3 gran 3 limit ffff flags 60000100 index 20
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base cfd27100 size 10 align 4 gran 4 limit cfffffff flags 60000201 index 10
|
| PCI: 00:16.2
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base cfd00000 size 20000 align 17 gran 17 limit cfffffff flags 60000200 index 10
|
| PCI: 00:19.0 resource base cfd24000 size 1000 align 12 gran 12 limit cfffffff flags 60000200 index 14
|
| PCI: 00:19.0 resource base 1800 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base cfd26800 size 400 align 10 gran 10 limit cfffffff flags 60000200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base cfd20000 size 4000 align 14 gran 14 limit cfffffff flags 60000201 index 10
|
| PCI: 00:1c.0
|
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
|
| PCI: 00:1c.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
|
| PCI: 00:1c.3
|
| PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.3 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
|
| PCI: 00:1c.3 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
|
| PCI: 00:1c.4 child on link 0 PCI: 04:00.0
|
| PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.4 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
|
| PCI: 00:1c.4 resource base cfc00000 size 100000 align 20 gran 20 limit cfffffff flags 60080202 index 20
|
| PCI: 04:00.0
|
| PCI: 04:00.0 resource base cfc00000 size 2000 align 13 gran 13 limit cfffffff flags 60000201 index 10
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base cfd26c00 size 400 align 10 gran 10 limit cfffffff flags 60000200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1e.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
|
| PCI: 00:1e.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
|
| PCI: 00:1f.0
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PCI: 00:1f.0 resource base 1680 size 1c align 0 gran 0 limit 0 flags c0040100 index 10000400
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 1848 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
|
| PCI: 00:1f.2 resource base 1858 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
|
| PCI: 00:1f.2 resource base 1850 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
|
| PCI: 00:1f.2 resource base 185c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
|
| PCI: 00:1f.2 resource base 1820 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
|
| PCI: 00:1f.2 resource base cfd26000 size 800 align 11 gran 11 limit cfffffff flags 60000200 index 24
|
| PCI: 00:1f.3
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base cfd27000 size 100 align 8 gran 8 limit cfffffff flags 60000201 index 10
|
| PCI: 00:1f.6
|
| PCI: 00:1f.6 resource base cfd25000 size 1000 align 12 gran 12 limit cfffffff flags 60000201 index 10
|
| Done allocating resources.
|
| BS: Exiting BS_DEV_RESOURCES state.
|
| BS: Entering BS_DEV_ENABLE state.
|
| Enabling resources...
|
| PCI: 00:00.0 subsystem <- 17aa/2193
|
| PCI: 00:00.0 cmd <- 06
|
| PCI: 00:01.0 bridge ctrl <- 0003
|
| PCI: 00:01.0 cmd <- 00
|
| PCI: 00:02.0 subsystem <- 17aa/215a
|
| PCI: 00:02.0 cmd <- 03
|
| PCI: 00:16.0 cmd <- 02
|
| PCI: 00:19.0 subsystem <- 17aa/2153
|
| PCI: 00:19.0 cmd <- 03
|
| PCI: 00:1b.0 subsystem <- 17aa/215e
|
| PCI: 00:1b.0 cmd <- 02
|
| PCI: 00:1c.0 bridge ctrl <- 0003
|
| PCI: 00:1c.0 cmd <- 00
|
| PCI: 00:1c.3 bridge ctrl <- 0003
|
| PCI: 00:1c.3 cmd <- 00
|
| PCI: 00:1c.4 bridge ctrl <- 0003
|
| PCI: 00:1c.4 cmd <- 06
|
| PCI: 00:1e.0 bridge ctrl <- 0003
|
| PCI: 00:1e.0 cmd <- 00 (NOT WRITTEN!)
|
| pch_decode_init
|
| PCI: 00:1f.0 subsystem <- 17aa/2166
|
| PCI: 00:1f.0 cmd <- 107
|
| PCI: 00:1f.2 subsystem <- 17aa/2168
|
| PCI: 00:1f.2 cmd <- 03
|
| PCI: 00:1f.3 subsystem <- 17aa/2167
|
| PCI: 00:1f.3 cmd <- 03
|
| PCI: 00:1f.6 cmd <- 02
|
| PCI: 04:00.0 cmd <- 02
|
| done.
|
| BS: Exiting BS_DEV_ENABLE state.
|
| BS: Entering BS_DEV_INIT state.
|
| Initializing devices...
|
| Root Device init
|
| CPU_CLUSTER: 0 init
|
| start_eip=0x00001000, code_size=0x00000031
|
| Installing SMM handler to 0xb7800000
|
| Installing IED header to 0xb7c00000
|
| Initializing SMM handler... ... pmbase = 0x0500
|
|
|
| SMI_STS: MCSMI PM1
|
| PM1_STS: WAK BM TMROF
|
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
|
| ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
| TCO_STS:
|
| ... raise SMI#
|
| Initializing CPU #0
|
| CPU: vendor Intel device 20652
|
| CPU: family 06, model 25, stepping 02
|
| Enabling cache
|
| microcode: sig=0x20652 pf=0x10 revision=0x0
|
| CPU: Intel(R) Core(TM) i7 CPU L 640 @ 2.13GHz.
|
| CPU:lapic=0, boot_cpu=1
|
| MTRR: Physical address space:
|
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
| 0x00000000000c0000 - 0x00000000b7800000 size 0xb7740000 type 6
|
| 0x00000000b7800000 - 0x0000000100000000 size 0x48800000 type 0
|
| MTRR addr 0x0-0x10 set to 6 type @ 0
|
| MTRR addr 0x10-0x20 set to 6 type @ 1
|
| MTRR addr 0x20-0x30 set to 6 type @ 2
|
| MTRR addr 0x30-0x40 set to 6 type @ 3
|
| MTRR addr 0x40-0x50 set to 6 type @ 4
|
| MTRR addr 0x50-0x60 set to 6 type @ 5
|
| MTRR addr 0x60-0x70 set to 6 type @ 6
|
| MTRR addr 0x70-0x80 set to 6 type @ 7
|
| MTRR addr 0x80-0x84 set to 6 type @ 8
|
| MTRR addr 0x84-0x88 set to 6 type @ 9
|
| MTRR addr 0x88-0x8c set to 6 type @ 10
|
| MTRR addr 0x8c-0x90 set to 6 type @ 11
|
| MTRR addr 0x90-0x94 set to 6 type @ 12
|
| MTRR addr 0x94-0x98 set to 6 type @ 13
|
| MTRR addr 0x98-0x9c set to 6 type @ 14
|
| MTRR addr 0x9c-0xa0 set to 6 type @ 15
|
| MTRR addr 0xa0-0xa4 set to 0 type @ 16
|
| MTRR addr 0xa4-0xa8 set to 0 type @ 17
|
| MTRR addr 0xa8-0xac set to 0 type @ 18
|
| MTRR addr 0xac-0xb0 set to 0 type @ 19
|
| MTRR addr 0xb0-0xb4 set to 0 type @ 20
|
| MTRR addr 0xb4-0xb8 set to 0 type @ 21
|
| MTRR addr 0xb8-0xbc set to 0 type @ 22
|
| MTRR addr 0xbc-0xc0 set to 0 type @ 23
|
| MTRR addr 0xc0-0xc1 set to 6 type @ 24
|
| MTRR addr 0xc1-0xc2 set to 6 type @ 25
|
| MTRR addr 0xc2-0xc3 set to 6 type @ 26
|
| MTRR addr 0xc3-0xc4 set to 6 type @ 27
|
| MTRR addr 0xc4-0xc5 set to 6 type @ 28
|
| MTRR addr 0xc5-0xc6 set to 6 type @ 29
|
| MTRR addr 0xc6-0xc7 set to 6 type @ 30
|
| MTRR addr 0xc7-0xc8 set to 6 type @ 31
|
| MTRR addr 0xc8-0xc9 set to 6 type @ 32
|
| MTRR addr 0xc9-0xca set to 6 type @ 33
|
| MTRR addr 0xca-0xcb set to 6 type @ 34
|
| MTRR addr 0xcb-0xcc set to 6 type @ 35
|
| MTRR addr 0xcc-0xcd set to 6 type @ 36
|
| MTRR addr 0xcd-0xce set to 6 type @ 37
|
| MTRR addr 0xce-0xcf set to 6 type @ 38
|
| MTRR addr 0xcf-0xd0 set to 6 type @ 39
|
| MTRR addr 0xd0-0xd1 set to 6 type @ 40
|
| MTRR addr 0xd1-0xd2 set to 6 type @ 41
|
| MTRR addr 0xd2-0xd3 set to 6 type @ 42
|
| MTRR addr 0xd3-0xd4 set to 6 type @ 43
|
| MTRR addr 0xd4-0xd5 set to 6 type @ 44
|
| MTRR addr 0xd5-0xd6 set to 6 type @ 45
|
| MTRR addr 0xd6-0xd7 set to 6 type @ 46
|
| MTRR addr 0xd7-0xd8 set to 6 type @ 47
|
| MTRR addr 0xd8-0xd9 set to 6 type @ 48
|
| MTRR addr 0xd9-0xda set to 6 type @ 49
|
| MTRR addr 0xda-0xdb set to 6 type @ 50
|
| MTRR addr 0xdb-0xdc set to 6 type @ 51
|
| MTRR addr 0xdc-0xdd set to 6 type @ 52
|
| MTRR addr 0xdd-0xde set to 6 type @ 53
|
| MTRR addr 0xde-0xdf set to 6 type @ 54
|
| MTRR addr 0xdf-0xe0 set to 6 type @ 55
|
| MTRR addr 0xe0-0xe1 set to 6 type @ 56
|
| MTRR addr 0xe1-0xe2 set to 6 type @ 57
|
| MTRR addr 0xe2-0xe3 set to 6 type @ 58
|
| MTRR addr 0xe3-0xe4 set to 6 type @ 59
|
| MTRR addr 0xe4-0xe5 set to 6 type @ 60
|
| MTRR addr 0xe5-0xe6 set to 6 type @ 61
|
| MTRR addr 0xe6-0xe7 set to 6 type @ 62
|
| MTRR addr 0xe7-0xe8 set to 6 type @ 63
|
| MTRR addr 0xe8-0xe9 set to 6 type @ 64
|
| MTRR addr 0xe9-0xea set to 6 type @ 65
|
| MTRR addr 0xea-0xeb set to 6 type @ 66
|
| MTRR addr 0xeb-0xec set to 6 type @ 67
|
| MTRR addr 0xec-0xed set to 6 type @ 68
|
| MTRR addr 0xed-0xee set to 6 type @ 69
|
| MTRR addr 0xee-0xef set to 6 type @ 70
|
| MTRR addr 0xef-0xf0 set to 6 type @ 71
|
| MTRR addr 0xf0-0xf1 set to 6 type @ 72
|
| MTRR addr 0xf1-0xf2 set to 6 type @ 73
|
| MTRR addr 0xf2-0xf3 set to 6 type @ 74
|
| MTRR addr 0xf3-0xf4 set to 6 type @ 75
|
| MTRR addr 0xf4-0xf5 set to 6 type @ 76
|
| MTRR addr 0xf5-0xf6 set to 6 type @ 77
|
| MTRR addr 0xf6-0xf7 set to 6 type @ 78
|
| MTRR addr 0xf7-0xf8 set to 6 type @ 79
|
| MTRR addr 0xf8-0xf9 set to 6 type @ 80
|
| MTRR addr 0xf9-0xfa set to 6 type @ 81
|
| MTRR addr 0xfa-0xfb set to 6 type @ 82
|
| MTRR addr 0xfb-0xfc set to 6 type @ 83
|
| MTRR addr 0xfc-0xfd set to 6 type @ 84
|
| MTRR addr 0xfd-0xfe set to 6 type @ 85
|
| MTRR addr 0xfe-0xff set to 6 type @ 86
|
| MTRR addr 0xff-0x100 set to 6 type @ 87
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: default type WB/UC MTRR counts: 3/5.
|
| MTRR: WB selected as default type.
|
| MTRR: 0 base 0x00000000b7800000 mask 0x0000000fff800000 type 0
|
| MTRR: 1 base 0x00000000b8000000 mask 0x0000000ff8000000 type 0
|
| MTRR: 2 base 0x00000000c0000000 mask 0x0000000fc0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x00 done.
|
| Enabling VMX
|
| model_x06ax: frequency set to 2128
|
| Turbo is available and visible
|
| CPU: 0 has 2 cores, 2 threads per core
|
| CPU: 0 has core 1
|
| CPU1: stack_base 00164000, stack_end 00164ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 1.
|
| After apic_write.
|
| Initializing CPU #1
|
| Startup point 1.
|
| CPU: vendor Intel device 20652
|
| Waiting for send to finish...
|
| CPU: family 06, model 25, stepping 02
|
| +Enabling cache
|
| Sending STARTUP #2 to 1.
|
| After apic_write.
|
| microcode: sig=0x20652 pf=0x10 revision=0x0
|
| CPU: Intel(R) Core(TM) i7 CPU L 640 @ 2.13GHz.
|
| CPU:lapic=1, boot_cpu=0
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x250 0x0606060606060606
|
| After Startup.
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| CPU: 0 has core 4
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| CPU2: stack_base 00163000, stack_end 00163ff8
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Asserting INIT.
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Waiting for send to finish...
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| +call enable_fixed_mtrr()
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| MTRR: 0 base 0x00000000b7800000 mask 0x0000000fff800000 type 0
|
| Sending STARTUP #1 to 4.
|
| MTRR: 1 base 0x00000000b8000000 mask 0x0000000ff8000000 type 0
|
| After apic_write.
|
| MTRR: 2 base 0x00000000c0000000 mask 0x0000000fc0000000 type 0
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Initializing CPU #2
|
| Setting up local apic...Sending STARTUP #2 to 4.
|
| apic_id: 0x01 done.
|
| After apic_write.
|
| Enabling VMX
|
| model_x06ax: frequency set to 2128
|
| CPU #1 initialized
|
| CPU: vendor Intel device 20652
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: family 06, model 25, stepping 02
|
| After Startup.
|
| CPU: 0 has core 5
|
| CPU3: stack_base 00162000, stack_end 00162ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Enabling cache
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 5.
|
| After apic_write.
|
| Initializing CPU #3
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +microcode: sig=0x20652 pf=0x10 revision=0x0
|
| Sending STARTUP #2 to 5.
|
| After apic_write.
|
| CPU: vendor Intel device 20652
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: Intel(R) Core(TM) i7 CPU L 640 @ 2.13GHz.
|
| After Startup.
|
| CPU #0 initialized
|
| Waiting for 2 CPUS to stop
|
| CPU: family 06, model 25, stepping 02
|
| CPU:lapic=4, boot_cpu=0
|
| Enabling cache
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| microcode: sig=0x20652 pf=0x10 revision=0x0
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| CPU: Intel(R) Core(TM) i7 CPU L 640 @ 2.13GHz.
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| CPU:lapic=5, boot_cpu=0
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: 0 base 0x00000000b7800000 mask 0x0000000fff800000 type 0
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: 1 base 0x00000000b8000000 mask 0x0000000ff8000000 type 0
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| MTRR: 2 base 0x00000000c0000000 mask 0x0000000fc0000000 type 0
|
| call enable_fixed_mtrr()
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x04 done.
|
| Enabling VMX
|
| MTRR: 0 base 0x00000000b7800000 mask 0x0000000fff800000 type 0
|
| model_x06ax: frequency set to 2128
|
| MTRR: 1 base 0x00000000b8000000 mask 0x0000000ff8000000 type 0
|
| CPU #2 initialized
|
| MTRR: 2 base 0x00000000c0000000 mask 0x0000000fc0000000 type 0
|
| Waiting for 1 CPUS to stop
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x05 done.
|
| Enabling VMX
|
| model_x06ax: frequency set to 2128
|
| CPU #3 initialized
|
| All AP CPUs stopped (4836 loops)
|
| CPU1: stack: 00164000 - 00165000, lowest used address 00164c9c, stack used: 868 bytes
|
| CPU2: stack: 00163000 - 00164000, lowest used address 00163c9c, stack used: 868 bytes
|
| CPU3: stack: 00162000 - 00163000, lowest used address 00162c9c, stack used: 868 bytes
|
| PCI: 00:00.0 init
|
| Set BIOS_RESET_CPL
|
| PCI: 00:02.0 init
|
| GT Power Management Init
|
| IVB GT1 Power Meter Weights
|
| GT init timeout
|
| In CBFS, ROM address for PCI: 00:02.0 = fff00678
|
| PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
|
| PCI ROM image, vendor ID 8086, device ID 0046,
|
| PCI ROM image, Class Code 030000, Code Type 00
|
| Copying VGA ROM Image from fff00678 to 0xc0000, 0x10000 bytes
|
| Real mode stub @00000600: 867 bytes
|
| Calling Option ROM...
|
| Unknown INT15 function 5f70!
|
| int15 call returned error.
|
| ... Option ROM returned.
|
| GT Power Management Init (post VBIOS)
|
| GT init timeout
|
| PCI: 00:16.0 init
|
| ME: FW Partition Table : OK
|
| ME: Bringup Loader Failure : NO
|
| ME: Firmware Init Complete : NO
|
| ME: Manufacturing Mode : NO
|
| ME: Boot Options Present : NO
|
| ME: Update In Progress : NO
|
| ME: Current Working State : Normal
|
| ME: Current Operation State : M0 with UMA
|
| ME: Current Operation Mode : Normal
|
| ME: Error Code : No Error
|
| ME: Progress Phase : Host Communication
|
| ME: Power Management Event : Clean Moff->Mx wake
|
| ME: Progress Phase State : Host communication established
|
| ME: BIOS path: Normal
|
| ME: Extend SHA-256: 9074058e31fa4998d285679f15f1e232ed8b7a91180914195d3519ccf663f82e
|
| PCI: 00:19.0 init
|
| PCI: 00:1a.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1b.0 init
|
| Azalia: base = cfd20000
|
| Azalia: V1CTL disabled.
|
| Azalia: codec_mask = 09
|
| Azalia: Initializing codec #3
|
| Azalia: codec viddid: 80862804
|
| Azalia: verb_size: 16
|
| Azalia: verb loaded.
|
| Azalia: Initializing codec #0
|
| Azalia: codec viddid: 14f15069
|
| Azalia: verb_size: 44
|
| Azalia: verb loaded.
|
| PCI: 00:1d.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1e.0 init
|
| PCI init.
|
| PCI: 00:1f.0 init
|
| pch: lpc_init
|
| IOAPIC: Initializing IOAPIC at 0xfec00000
|
| IOAPIC: Bootstrap Processor Local APIC = 0x00
|
| IOAPIC: ID = 0x01
|
| IOAPIC: Dumping registers
|
| reg 0x0000: 0x01000000
|
| reg 0x0001: 0x00170020
|
| reg 0x0002: 0x00170020
|
| Set power on after power failure.
|
| NMI sources enabled.
|
| Mobile 5 PM init
|
| rtc_failed = 0x0
|
| RTC Init
|
| i8259_configure_irq_trigger: current interrupts are 0x0
|
| i8259_configure_irq_trigger: try to set interrupts 0x200
|
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
|
| done.
|
| Locking SMM.
|
| PCI: 00:1f.2 init
|
| SATA: Initializing...
|
| SATA: Controller in AHCI mode.
|
| ABAR: CFD26000
|
| PCI: 00:1f.3 init
|
| PCI: 00:1f.6 init
|
| Thermal init start.
|
| Thermal init done.
|
| PCI: 04:00.0 init
|
| Devices initialized
|
| Show all devs...After init.
|
| Root Device: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.4: enabled 1
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1f.0: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| PCI: 00:01.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:1e.0: enabled 1
|
| PCI: 00:1f.6: enabled 1
|
| PCI: 04:00.0: enabled 1
|
| APIC: 01: enabled 1
|
| APIC: 04: enabled 1
|
| APIC: 05: enabled 1
|
| BS: Exiting BS_DEV_INIT state.
|
| BS: Entering BS_POST_DEVICE state.
|
| CBMEM region b76d0000-b77fffff (cbmem_check_toc)
|
| Adding CBMEM entry as no. 5
|
| Moving GDT to b76e0c00...ok
|
| Finalize devices...
|
| Devices finalized
|
| BS: Exiting BS_POST_DEVICE state.
|
| BS: Entering BS_OS_RESUME_CHECK state.
|
| BS: Exiting BS_OS_RESUME_CHECK state.
|
| BS: Entering BS_WRITE_TABLES state.
|
| Updating MRC cache data.
|
| find_current_mrc_cache_local: No valid MRC cache found.
|
| SF: Detected MX25L6405D with page size 1000, total 800000
|
| Need to erase the MRC cache region of 65536 bytes at fffe0000
|
| SF: Successfully erased 65536 bytes @ 0x7e0000
|
| Finally: write MRC cache update to flash at fffe0000
|
| Copying Interrupt Routing Table to 0x000f0000... done.
|
| Adding CBMEM entry as no. 6
|
| Copying Interrupt Routing Table to 0xb76e0e00... done.
|
| PIRQ table: 288 bytes.
|
| Wrote the mp table end at: 000f0410 - 000f05d4
|
| Adding CBMEM entry as no. 7
|
| Wrote the mp table end at: b76e1e10 - b76e1fd4
|
| MP table: 468 bytes.
|
| Adding CBMEM entry as no. 8
|
| ACPI: Writing ACPI tables at b76e2e00.
|
| ACPI: * HPET
|
| ACPI: added table 1/32, length now 40
|
| ACPI: * MADT
|
| ACPI: added table 2/32, length now 44
|
| ACPI: * MCFG
|
| ACPI: added table 3/32, length now 48
|
| ACPI: * FACS
|
| ACPI: Patching up global NVS in DSDT at offset 0x020d -> 0xb76e6c60
|
| ACPI: * DSDT @ b76e3160 Length 3af1
|
| ACPI: * FADT
|
| ACPI: added table 4/32, length now 52
|
| ACPI: * SSDT
|
| Found 1 CPU(s) with 4 core(s) each.
|
| PSS: 2134MHz power 25000 control 0x16 status 0x16
|
| PSS: 2133MHz power 25000 control 0x10 status 0x10
|
| PSS: 2000MHz power 23143 control 0xf status 0xf
|
| PSS: 1866MHz power 21371 control 0xe status 0xe
|
| PSS: 1733MHz power 19609 control 0xd status 0xd
|
| PSS: 1600MHz power 17887 control 0xc status 0xc
|
| PSS: 1466MHz power 16196 control 0xb status 0xb
|
| PSS: 1333MHz power 14562 control 0xa status 0xa
|
| PSS: 1200MHz power 12940 control 0x9 status 0x9
|
| PSS: 2134MHz power 25000 control 0x16 status 0x16
|
| PSS: 2133MHz power 25000 control 0x10 status 0x10
|
| PSS: 2000MHz power 23143 control 0xf status 0xf
|
| PSS: 1866MHz power 21371 control 0xe status 0xe
|
| PSS: 1733MHz power 19609 control 0xd status 0xd
|
| PSS: 1600MHz power 17887 control 0xc status 0xc
|
| PSS: 1466MHz power 16196 control 0xb status 0xb
|
| PSS: 1333MHz power 14562 control 0xa status 0xa
|
| PSS: 1200MHz power 12940 control 0x9 status 0x9
|
| PSS: 2134MHz power 25000 control 0x16 status 0x16
|
| PSS: 2133MHz power 25000 control 0x10 status 0x10
|
| PSS: 2000MHz power 23143 control 0xf status 0xf
|
| PSS: 1866MHz power 21371 control 0xe status 0xe
|
| PSS: 1733MHz power 19609 control 0xd status 0xd
|
| PSS: 1600MHz power 17887 control 0xc status 0xc
|
| PSS: 1466MHz power 16196 control 0xb status 0xb
|
| PSS: 1333MHz power 14562 control 0xa status 0xa
|
| PSS: 1200MHz power 12940 control 0x9 status 0x9
|
| PSS: 2134MHz power 25000 control 0x16 status 0x16
|
| PSS: 2133MHz power 25000 control 0x10 status 0x10
|
| PSS: 2000MHz power 23143 control 0xf status 0xf
|
| PSS: 1866MHz power 21371 control 0xe status 0xe
|
| PSS: 1733MHz power 19609 control 0xd status 0xd
|
| PSS: 1600MHz power 17887 control 0xc status 0xc
|
| PSS: 1466MHz power 16196 control 0xb status 0xb
|
| PSS: 1333MHz power 14562 control 0xa status 0xa
|
| PSS: 1200MHz power 12940 control 0x9 status 0x9
|
| ACPI: added table 5/32, length now 56
|
| current = b76e7aa0
|
| ACPI: done.
|
| Laptop handling...
|
| ACPI tables: 19616 bytes.
|
| Adding CBMEM entry as no. 9
|
| smbios_write_tables: b76ee200
|
| Root Device (LENOVO 3626EN1)
|
| PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
|
| PNP: 00ff.2 (Lenovo H8 EC)
|
| CPU_CLUSTER: 0 (Intel i7 (Nehalem) integrated Northbridge)
|
| APIC: 00 (unknown)
|
| DOMAIN: 0000 (Intel i7 (Nehalem) integrated Northbridge)
|
| PCI: 00:00.0 (Intel i7 (Nehalem) integrated Northbridge)
|
| PCI: 00:02.0 (Intel i7 (Nehalem) integrated Northbridge)
|
| PCI: 00:16.2 (unknown)
|
| PCI: 00:19.0 (unknown)
|
| PCI: 00:1a.0 (unknown)
|
| PCI: 00:1b.0 (unknown)
|
| PCI: 00:1c.0 (unknown)
|
| PCI: 00:1c.3 (unknown)
|
| PCI: 00:1c.4 (unknown)
|
| PCI: 00:1d.0 (unknown)
|
| PCI: 00:1f.0 (unknown)
|
| PCI: 00:1f.2 (unknown)
|
| PCI: 00:1f.3 (unknown)
|
| PCI: 00:01.0 (unknown)
|
| PCI: 00:16.0 (unknown)
|
| PCI: 00:1e.0 (unknown)
|
| PCI: 00:1f.6 (unknown)
|
| PCI: 04:00.0 (unknown)
|
| APIC: 01 (unknown)
|
| APIC: 04 (unknown)
|
| APIC: 05 (unknown)
|
| SMBIOS tables: 312 bytes.
|
| Adding CBMEM entry as no. 10
|
| Adding CBMEM entry as no. 11
|
| Writing table forward entry at 0x00000500
|
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5e5f
|
| Table forward entry ends at 0x00000528.
|
| ... aligned to 0x00001000
|
| Writing coreboot table at 0xb77eea00
|
| rom_table_end = 0xb77eea00
|
| ... aligned to 0xb77f0000
|
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
| 1. 0000000000001000-000000000009ffff: RAM
|
| 2. 00000000000a0000-00000000000fffff: RESERVED
|
| 3. 0000000000100000-00000000b76cffff: RAM
|
| 4. 00000000b76d0000-00000000b77fffff: CONFIGURATION TABLES
|
| 5. 00000000b7800000-00000000b7ffffff: RESERVED
|
| 6. 00000000b9c00000-00000000bbffffff: RESERVED
|
| 7. 00000000d0000000-00000000efffffff: RESERVED
|
| 8. 00000000fed00000-00000000fedfffff: RESERVED
|
| Wrote coreboot table at: b77eea00, 0x82c bytes, checksum 6c74
|
| coreboot table: 2116 bytes.
|
| FREE SPACE 0. b77f6a00 00009600
|
| CAR GLOBALS 1. b76d0200 00000200
|
| CONSOLE 2. b76d0400 00010000
|
| TIME STAMP 3. b76e0400 00000200
|
| MRC DATA 4. b76e0600 00000600
|
| GDT 5. b76e0c00 00000200
|
| IRQ TABLE 6. b76e0e00 00001000
|
| SMP TABLE 7. b76e1e00 00001000
|
| ACPI 8. b76e2e00 0000b400
|
| SMBIOS 9. b76ee200 00000800
|
| ACPI RESUME10. b76eea00 00100000
|
| COREBOOT 11. b77eea00 00008000
|
| BS: Exiting BS_WRITE_TABLES state.
|
| BS: Entering BS_PAYLOAD_LOAD state.
|
| Loading segment from rom address 0xfff11038
|
| code (compression=1)
|
| New segment dstaddr 0xe6db0 memsize 0x19250 srcaddr 0xfff11070 filesize 0xcaf5
|
| (cleaned up) New segment addr 0xe6db0 size 0x19250 offset 0xfff11070 filesize 0xcaf5
|
| Loading segment from rom address 0xfff11054
|
| Entry Point 0x000fc746
|
| Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB
|
| Loading Segment: addr: 0x00000000000e6db0 memsz: 0x0000000000019250 filesz: 0x000000000000caf5
|
| lb: [0x0000000000100000, 0x000000000016a038)
|
| Post relocation: addr: 0x00000000000e6db0 memsz: 0x0000000000019250 filesz: 0x000000000000caf5
|
| using LZMA
|
| [ 0x000e6db0, 00100000, 0x00100000) <- fff11070
|
| dest 000e6db0, end 00100000, bouncebuffer b75fbf90
|
| Loaded segments
|
| BS: Exiting BS_PAYLOAD_LOAD state.
|
| BS: Entering BS_PAYLOAD_BOOT state.
|
| PCH watchdog disabled
|
| Jumping to boot code at 000fc746
|
| CPU0: stack: 00165000 - 00166000, lowest used address 00165adc, stack used: 1316 bytes
|
| entry = 0x000fc746
|
| lb_start = 0x00100000
|
| lb_size = 0x0006a038
|
| buffer = 0xb75fbf90
|
| |