| coreboot-4.0-6723-ga0a3727 Fri Aug 15 21:16:16 BST 2014 booting... |
| clocks_per_usec: 499 |
| BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 |
| Enumerating buses... |
| Show all devs...Before device enumeration. |
| Root Device: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:01.1: enabled 1 |
| PCI: 00:0f.0: enabled 1 |
| PCI: 00:0f.1: enabled 1 |
| PCI: 00:0f.2: enabled 1 |
| PCI: 00:0f.4: enabled 1 |
| PCI: 00:0f.5: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| Compare with tree... |
| Root Device: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:01.1: enabled 1 |
| PCI: 00:0f.0: enabled 1 |
| PCI: 00:0f.1: enabled 1 |
| PCI: 00:0f.2: enabled 1 |
| PCI: 00:0f.4: enabled 1 |
| PCI: 00:0f.5: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| scan_static_bus for Root Device |
| >> Entering northbridge.c: enable_dev with path 6 |
| >> Entering northbridge.c: pci_domain_enable |
| Enter northbridge_init_early |
| writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 |
| writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 |
| sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 |
| sizeram: sizem 0x100MB |
| SysmemInit: enable for 256MBytes |
| usable RAM: 268304383 bytes |
| SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 |
| sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 |
| sizeram: sizem 0x100MB |
| SMMGL0Init: 268304384 bytes |
| SMMGL0Init: offset is 0x80400000 |
| SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 |
| writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 |
| writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 |
| writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 |
| sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 |
| sizeram: sizem 0x100MB |
| SysmemInit: enable for 256MBytes |
| usable RAM: 268304383 bytes |
| SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 |
| SMMGL1Init: |
| SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 |
| writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 |
| writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 |
| CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 |
| CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 |
| L2 cache enabled |
| Enabling cache |
| GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 |
| GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 |
| Exit northbridge_init_early |
| Done cpubug fixes |
| Not Doing ChipsetFlashSetup() |
| Preparing for VSA... |
| Real mode stub @00000600: 867 bytes |
| CBFS: loading stage vsa @ 0x60000 (57504 bytes), entry @ 0x60020 |
| VSA: Buffer @00060000 *[0k]=ba |
| VSA: Signature *[0x20-0x23] is b0:10:e6:80 |
| Calling VSA module... |
| ... VSA module returned. |
| VSM: VSA2 VR signature verified. |
| Graphics init... |
| VRC_VG value: 0x2808 |
| DOMAIN: 0000 enabled |
| >> Entering northbridge.c: enable_dev with path 7 |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| >> Entering northbridge.c: enable_dev with path 2 |
| PCI: 00:01.0 [1022/2080] ops |
| PCI: 00:01.0 [1022/2080] enabled |
| >> Entering northbridge.c: enable_dev with path 2 |
| PCI: 00:01.1 [1022/2081] enabled |
| PCI: 00:01.2 [1022/2082] enabled |
| PCI: 00:09.0 [1106/3053] enabled |
| PCI: 00:0a.0 [1106/3053] enabled |
| PCI: 00:0b.0 [1106/3053] enabled |
| PCI: 00:0c.0 [168c/1014] enabled |
| cs5536: southbridge_enable: dev is 00117794 |
| PCI: 00:0f.0 [1022/2090] bus ops |
| PCI: 00:0f.0 [1022/2090] enabled |
| cs5536: southbridge_enable: dev is 0011782c |
| PCI: Static device PCI: 00:0f.1 not found, disabling it. |
| cs5536: southbridge_enable: dev is 001178c4 |
| PCI: 00:0f.2 [1022/209a] ops |
| PCI: 00:0f.2 [1022/209a] enabled |
| PCI: 00:0f.3 [1022/2093] enabled |
| cs5536: southbridge_enable: dev is 0011795c |
| PCI: 00:0f.4 [1022/2094] enabled |
| cs5536: southbridge_enable: dev is 001179f4 |
| PCI: 00:0f.5 [1022/2095] enabled |
| PCI: 00:0f.6 [1022/2096] enabled |
| PCI: 00:0f.7 [1022/2097] enabled |
| scan_static_bus for PCI: 00:0f.0 |
| scan_static_bus for PCI: 00:0f.0 done |
| PCI: pci_scan_bus returning with max=000 |
| scan_static_bus for Root Device done |
| done |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 1030801 exit 0 |
| found VGA at PCI: 00:01.1 |
| Setting up VGA for PCI: 00:01.1 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| APIC: 00 missing read_resources |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 DOMAIN: 0000 |
| DOMAIN: 0000 child on link 0 PCI: 00:01.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10 |
| PCI: 00:01.1 |
| PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 |
| PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14 |
| PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18 |
| PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c |
| PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 20 |
| PCI: 00:01.2 |
| PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 |
| PCI: 00:09.0 |
| PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 |
| PCI: 00:0a.0 |
| PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 |
| PCI: 00:0b.0 |
| PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 |
| PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 |
| PCI: 00:0c.0 |
| PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10 |
| PCI: 00:0f.0 |
| PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 |
| PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18 |
| PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c |
| PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20 |
| PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 |
| PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 |
| PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:0f.1 |
| PCI: 00:0f.2 |
| PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 |
| PCI: 00:0f.3 |
| PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 |
| PCI: 00:0f.4 |
| PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| PCI: 00:0f.5 |
| PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| PCI: 00:0f.6 |
| PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10 |
| PCI: 00:0f.7 |
| PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:09.0 10 * [0x0 - 0xff] io |
| PCI: 00:0a.0 10 * [0x400 - 0x4ff] io |
| PCI: 00:0b.0 10 * [0x800 - 0x8ff] io |
| PCI: 00:0f.0 14 * [0xc00 - 0xcff] io |
| PCI: 00:0f.0 20 * [0x1000 - 0x107f] io |
| PCI: 00:0f.3 10 * [0x1080 - 0x10ff] io |
| PCI: 00:0f.0 18 * [0x1400 - 0x143f] io |
| PCI: 00:0f.0 24 * [0x1440 - 0x147f] io |
| PCI: 00:0f.0 1c * [0x1480 - 0x149f] io |
| PCI: 00:0f.2 20 * [0x14a0 - 0x14af] io |
| PCI: 00:0f.0 10 * [0x14b0 - 0x14b7] io |
| PCI: 00:01.0 10 * [0x14b8 - 0x14bb] io |
| DOMAIN: 0000 compute_resources_io: base: 14bc size: 14bc align: 8 gran: 0 limit: ffff done |
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:01.1 10 * [0x0 - 0xffffff] mem |
| PCI: 00:0c.0 10 * [0x1000000 - 0x100ffff] mem |
| PCI: 00:01.1 14 * [0x1010000 - 0x1013fff] mem |
| PCI: 00:01.1 18 * [0x1014000 - 0x1017fff] mem |
| PCI: 00:01.1 1c * [0x1018000 - 0x101bfff] mem |
| PCI: 00:01.1 20 * [0x101c000 - 0x101ffff] mem |
| PCI: 00:01.2 10 * [0x1020000 - 0x1023fff] mem |
| PCI: 00:0f.6 10 * [0x1024000 - 0x1025fff] mem |
| PCI: 00:0f.4 10 * [0x1026000 - 0x1026fff] mem |
| PCI: 00:0f.5 10 * [0x1027000 - 0x1027fff] mem |
| PCI: 00:0f.7 10 * [0x1028000 - 0x1028fff] mem |
| PCI: 00:09.0 14 * [0x1029000 - 0x10290ff] mem |
| PCI: 00:0a.0 14 * [0x1029100 - 0x10291ff] mem |
| PCI: 00:0b.0 14 * [0x1029200 - 0x10292ff] mem |
| DOMAIN: 0000 compute_resources_mem: base: 1029300 size: 1029300 align: 24 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: DOMAIN: 0000 |
| constrain_resources: PCI: 00:01.0 |
| constrain_resources: PCI: 00:01.1 |
| constrain_resources: PCI: 00:01.2 |
| constrain_resources: PCI: 00:09.0 |
| constrain_resources: PCI: 00:0a.0 |
| constrain_resources: PCI: 00:0b.0 |
| constrain_resources: PCI: 00:0c.0 |
| constrain_resources: PCI: 00:0f.0 |
| constrain_resources: PCI: 00:0f.2 |
| constrain_resources: PCI: 00:0f.3 |
| constrain_resources: PCI: 00:0f.4 |
| constrain_resources: PCI: 00:0f.5 |
| constrain_resources: PCI: 00:0f.6 |
| constrain_resources: PCI: 00:0f.7 |
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff |
| lim->base 00001000 lim->limit 0000ffff |
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff |
| lim->base 00000000 lim->limit febfffff |
| Setting resources... |
| DOMAIN: 0000 allocate_resources_io: base:1000 size:14bc align:8 gran:0 limit:ffff |
| Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io |
| Assigned: PCI: 00:0a.0 10 * [0x1400 - 0x14ff] io |
| Assigned: PCI: 00:0b.0 10 * [0x1800 - 0x18ff] io |
| Assigned: PCI: 00:0f.0 14 * [0x1c00 - 0x1cff] io |
| Assigned: PCI: 00:0f.0 20 * [0x2000 - 0x207f] io |
| Assigned: PCI: 00:0f.3 10 * [0x2080 - 0x20ff] io |
| Assigned: PCI: 00:0f.0 18 * [0x2400 - 0x243f] io |
| Assigned: PCI: 00:0f.0 24 * [0x2440 - 0x247f] io |
| Assigned: PCI: 00:0f.0 1c * [0x2480 - 0x249f] io |
| Assigned: PCI: 00:0f.2 20 * [0x24a0 - 0x24af] io |
| Assigned: PCI: 00:0f.0 10 * [0x24b0 - 0x24b7] io |
| Assigned: PCI: 00:01.0 10 * [0x24b8 - 0x24bb] io |
| DOMAIN: 0000 allocate_resources_io: next_base: 24bc size: 14bc align: 8 gran: 0 done |
| DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1029300 align:24 gran:0 limit:febfffff |
| Assigned: PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem |
| Assigned: PCI: 00:0c.0 10 * [0xfe000000 - 0xfe00ffff] mem |
| Assigned: PCI: 00:01.1 14 * [0xfe010000 - 0xfe013fff] mem |
| Assigned: PCI: 00:01.1 18 * [0xfe014000 - 0xfe017fff] mem |
| Assigned: PCI: 00:01.1 1c * [0xfe018000 - 0xfe01bfff] mem |
| Assigned: PCI: 00:01.1 20 * [0xfe01c000 - 0xfe01ffff] mem |
| Assigned: PCI: 00:01.2 10 * [0xfe020000 - 0xfe023fff] mem |
| Assigned: PCI: 00:0f.6 10 * [0xfe024000 - 0xfe025fff] mem |
| Assigned: PCI: 00:0f.4 10 * [0xfe026000 - 0xfe026fff] mem |
| Assigned: PCI: 00:0f.5 10 * [0xfe027000 - 0xfe027fff] mem |
| Assigned: PCI: 00:0f.7 10 * [0xfe028000 - 0xfe028fff] mem |
| Assigned: PCI: 00:09.0 14 * [0xfe029000 - 0xfe0290ff] mem |
| Assigned: PCI: 00:0a.0 14 * [0xfe029100 - 0xfe0291ff] mem |
| Assigned: PCI: 00:0b.0 14 * [0xfe029200 - 0xfe0292ff] mem |
| DOMAIN: 0000 allocate_resources_mem: next_base: fe029300 size: 1029300 align: 24 gran: 0 done |
| Root Device assign_resources, bus 0 link: 0 |
| >> Entering northbridge.c: pci_domain_set_resources |
| CBMEM region f7b0000-f7dffff (cbmem_late_set_table) |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem |
| PCI: 00:01.1 14 <- [0x00fe010000 - 0x00fe013fff] size 0x00004000 gran 0x0e mem |
| PCI: 00:01.1 18 <- [0x00fe014000 - 0x00fe017fff] size 0x00004000 gran 0x0e mem |
| PCI: 00:01.1 1c <- [0x00fe018000 - 0x00fe01bfff] size 0x00004000 gran 0x0e mem |
| PCI: 00:01.1 20 <- [0x00fe01c000 - 0x00fe01ffff] size 0x00004000 gran 0x0e mem |
| PCI: 00:01.2 10 <- [0x00fe020000 - 0x00fe023fff] size 0x00004000 gran 0x0e mem |
| PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io |
| PCI: 00:09.0 14 <- [0x00fe029000 - 0x00fe0290ff] size 0x00000100 gran 0x08 mem |
| PCI: 00:0a.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io |
| PCI: 00:0a.0 14 <- [0x00fe029100 - 0x00fe0291ff] size 0x00000100 gran 0x08 mem |
| PCI: 00:0b.0 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io |
| PCI: 00:0b.0 14 <- [0x00fe029200 - 0x00fe0292ff] size 0x00000100 gran 0x08 mem |
| PCI: 00:0c.0 10 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 mem |
| PCI: 00:0f.0 10 <- [0x00000024b0 - 0x00000024b7] size 0x00000008 gran 0x03 io |
| PCI: 00:0f.0 14 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io |
| PCI: 00:0f.0 18 <- [0x0000002400 - 0x000000243f] size 0x00000040 gran 0x06 io |
| PCI: 00:0f.0 1c <- [0x0000002480 - 0x000000249f] size 0x00000020 gran 0x05 io |
| PCI: 00:0f.0 20 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io |
| PCI: 00:0f.0 24 <- [0x0000002440 - 0x000000247f] size 0x00000040 gran 0x06 io |
| PCI: 00:0f.2 20 <- [0x00000024a0 - 0x00000024af] size 0x00000010 gran 0x04 io |
| PCI: 00:0f.3 10 <- [0x0000002080 - 0x00000020ff] size 0x00000080 gran 0x07 io |
| PCI: 00:0f.4 10 <- [0x00fe026000 - 0x00fe026fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:0f.5 10 <- [0x00fe027000 - 0x00fe027fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:0f.6 10 <- [0x00fe024000 - 0x00fe025fff] size 0x00002000 gran 0x0d mem |
| PCI: 00:0f.7 10 <- [0x00fe028000 - 0x00fe028fff] size 0x00001000 gran 0x0c mem |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 DOMAIN: 0000 |
| DOMAIN: 0000 child on link 0 PCI: 00:01.0 |
| DOMAIN: 0000 resource base 1000 size 14bc align 8 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base fd000000 size 1029300 align 24 gran 0 limit febfffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a |
| DOMAIN: 0000 resource base c0000 size f720000 align 0 gran 0 limit 0 flags e0004200 index b |
| PCI: 00:01.0 |
| PCI: 00:01.0 resource base 24b8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10 |
| PCI: 00:01.1 |
| PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10 |
| PCI: 00:01.1 resource base fe010000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14 |
| PCI: 00:01.1 resource base fe014000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18 |
| PCI: 00:01.1 resource base fe018000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c |
| PCI: 00:01.1 resource base fe01c000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 20 |
| PCI: 00:01.2 |
| PCI: 00:01.2 resource base fe020000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10 |
| PCI: 00:09.0 |
| PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 |
| PCI: 00:09.0 resource base fe029000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 |
| PCI: 00:0a.0 |
| PCI: 00:0a.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 |
| PCI: 00:0a.0 resource base fe029100 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 |
| PCI: 00:0b.0 |
| PCI: 00:0b.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 |
| PCI: 00:0b.0 resource base fe029200 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 |
| PCI: 00:0c.0 |
| PCI: 00:0c.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 10 |
| PCI: 00:0f.0 |
| PCI: 00:0f.0 resource base 24b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 |
| PCI: 00:0f.0 resource base 1c00 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 |
| PCI: 00:0f.0 resource base 2400 size 40 align 6 gran 6 limit ffff flags 60000100 index 18 |
| PCI: 00:0f.0 resource base 2480 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c |
| PCI: 00:0f.0 resource base 2000 size 80 align 7 gran 7 limit ffff flags 60000100 index 20 |
| PCI: 00:0f.0 resource base 2440 size 40 align 6 gran 6 limit ffff flags 60000100 index 24 |
| PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 |
| PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:0f.1 |
| PCI: 00:0f.2 |
| PCI: 00:0f.2 resource base 24a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 |
| PCI: 00:0f.3 |
| PCI: 00:0f.3 resource base 2080 size 80 align 7 gran 7 limit ffff flags 60000100 index 10 |
| PCI: 00:0f.4 |
| PCI: 00:0f.4 resource base fe026000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 |
| PCI: 00:0f.5 |
| PCI: 00:0f.5 resource base fe027000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 |
| PCI: 00:0f.6 |
| PCI: 00:0f.6 resource base fe024000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10 |
| PCI: 00:0f.7 |
| PCI: 00:0f.7 resource base fe028000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 3640843 exit 0 |
| Enabling resources... |
| PCI: 00:01.0 cmd <- 05 |
| PCI: 00:01.1 subsystem <- 0000/0000 |
| PCI: 00:01.1 cmd <- 03 |
| PCI: 00:01.2 cmd <- 02 |
| PCI: 00:09.0 cmd <- 83 |
| PCI: 00:0a.0 cmd <- 83 |
| PCI: 00:0b.0 cmd <- 83 |
| PCI: 00:0c.0 cmd <- 02 |
| PCI: 00:0f.0 cmd <- 09 |
| PCI: 00:0f.2 cmd <- 01 |
| PCI: 00:0f.3 cmd <- 01 |
| PCI: 00:0f.4 subsystem <- 0000/0000 |
| PCI: 00:0f.4 cmd <- 02 |
| PCI: 00:0f.5 subsystem <- 0000/0000 |
| PCI: 00:0f.5 cmd <- 02 |
| PCI: 00:0f.6 cmd <- 02 |
| PCI: 00:0f.7 cmd <- 02 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 124954 exit 0 |
| Initializing devices... |
| Root Device init |
| ALIX.2D ENTER init |
| ALIX.2D EXIT init |
| Root Device init 14886 usecs |
| CPU_CLUSTER: 0 init |
| >> Entering northbridge.c: cpu_bus_init |
| Initializing CPU #0 |
| CPU: vendor AMD device 5a2 |
| CPU: family 05, model 0a, stepping 02 |
| geode_lx_init |
| Enabling cache |
| A20 (0x92): 2 |
| A20 (0x92): 2 |
| CPU geode_lx_init DONE |
| CPU #0 initialized |
| CPU_CLUSTER: 0 init 66546 usecs |
| PCI: 00:01.0 init |
| >> Entering northbridge.c: northbridge_init |
| PCI: 00:01.0 init 16680 usecs |
| PCI: 00:01.1 init |
| PCI: 00:01.1 init 4979 usecs |
| PCI: 00:01.2 init |
| PCI: 00:01.2 init 4979 usecs |
| PCI: 00:09.0 init |
| PCI: 00:09.0 init 4979 usecs |
| PCI: 00:0a.0 init |
| PCI: 00:0a.0 init 4979 usecs |
| PCI: 00:0b.0 init |
| PCI: 00:0b.0 init 4979 usecs |
| PCI: 00:0c.0 init |
| PCI: 00:0c.0 init 4979 usecs |
| PCI: 00:0f.0 init |
| cs5536: southbridge_init |
| RTC Init |
| GPIO_ADDR: 00001C00 |
| uarts_init: enable COM1 |
| uarts_init: enable COM2 |
| uarts_init: wrote COM2 address 0x2f8 |
| uarts_init: set COM2 irq |
| uarts_init: set output enable |
| uarts_init: set OUTAUX1 |
| uarts_init: set pullup COM2 |
| uarts_init: COM2 enabled |
| cs5536: southbridge_init: enable_ide_nand_flash is 0 |
| Disabling VPCI device: 0x80000900 |
| Disabling VPCI device: 0x80007B00 |
| PCI: 00:0f.0 init 111251 usecs |
| PCI: 00:0f.2 init |
| cs5536_ide: ide_init |
| PCI: 00:0f.2 init 10762 usecs |
| PCI: 00:0f.3 init |
| PCI: 00:0f.3 init 4979 usecs |
| PCI: 00:0f.4 init |
| PCI: 00:0f.4 init 4979 usecs |
| PCI: 00:0f.5 init |
| PCI: 00:0f.5 init 4979 usecs |
| PCI: 00:0f.6 init |
| PCI: 00:0f.6 init 4979 usecs |
| PCI: 00:0f.7 init |
| PCI: 00:0f.7 init 4979 usecs |
| Devices initialized |
| Show all devs...After init. |
| Root Device: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:01.1: enabled 1 |
| PCI: 00:0f.0: enabled 1 |
| PCI: 00:0f.1: enabled 0 |
| PCI: 00:0f.2: enabled 1 |
| PCI: 00:0f.4: enabled 1 |
| PCI: 00:0f.5: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| PCI: 00:01.2: enabled 1 |
| PCI: 00:09.0: enabled 1 |
| PCI: 00:0a.0: enabled 1 |
| PCI: 00:0b.0: enabled 1 |
| PCI: 00:0c.0: enabled 1 |
| PCI: 00:0f.3: enabled 1 |
| PCI: 00:0f.6: enabled 1 |
| PCI: 00:0f.7: enabled 1 |
| CPU: 00: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 0 run 549462 exit 0 |
| CBMEM region f7b0000-f7dffff (cbmem_check_toc) |
| CBMEM region f7b0000-f7dffff (cbmem_initialize_empty) |
| Adding CBMEM entry as no. 1 |
| Moving GDT to 0f7b0200...ok |
| Adding CBMEM entry as no. 2 |
| Finalize devices... |
| Devices finalized |
| Adding CBMEM entry as no. 3 |
| BS: BS_POST_DEVICE times (us): entry 49575 run 17988 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3 exit 0 |
| Copying Interrupt Routing Table to 0x000f0000... done. |
| PIRQ Entry 0 Dev/Fn: 1 Slot: 0 |
| INT: A link: 1 bitmap: 800 IRQ: 11 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 11 to 0:1.2 |
| PIRQ Entry 1 Dev/Fn: 9 Slot: 0 |
| INT: A link: 2 bitmap: 400 IRQ: 10 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 10 to 0:9.0 |
| PIRQ Entry 2 Dev/Fn: A Slot: 0 |
| INT: A link: 3 bitmap: 800 IRQ: 11 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 11 to 0:a.0 |
| PIRQ Entry 3 Dev/Fn: B Slot: 0 |
| INT: A link: 4 bitmap: 200 IRQ: 9 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 9 to 0:b.0 |
| PIRQ Entry 4 Dev/Fn: C Slot: 0 |
| INT: A link: 1 bitmap: 800 IRQ: 11 |
| INT: B link: 2 bitmap: 400 IRQ: 10 |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 11 to 0:c.0 |
| PIRQ Entry 5 Dev/Fn: E Slot: 0 |
| INT: A link: 3 bitmap: 800 IRQ: 11 |
| INT: B link: 4 bitmap: 200 IRQ: 9 |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| PIRQ Entry 6 Dev/Fn: F Slot: 0 |
| INT: A link: 1 bitmap: 800 IRQ: 11 |
| INT: B link: 2 bitmap: 400 IRQ: 10 |
| INT: C link: 3 bitmap: 800 IRQ: 11 |
| INT: D link: 4 bitmap: 200 IRQ: 9 |
| Assigning IRQ 9 to 0:f.4 |
| Assigning IRQ 9 to 0:f.5 |
| PIRQA: 11 |
| PIRQB: 10 |
| PIRQC: 11 |
| PIRQD: 9 |
| Adding CBMEM entry as no. 4 |
| Copying Interrupt Routing Table to 0x0f7c0600... done. |
| PIRQ Entry 0 Dev/Fn: 1 Slot: 0 |
| INT: A link: 1 bitmap: 800 IRQ: 11 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 11 to 0:1.2 |
| PIRQ Entry 1 Dev/Fn: 9 Slot: 0 |
| INT: A link: 2 bitmap: 400 IRQ: 10 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 10 to 0:9.0 |
| PIRQ Entry 2 Dev/Fn: A Slot: 0 |
| INT: A link: 3 bitmap: 800 IRQ: 11 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 11 to 0:a.0 |
| PIRQ Entry 3 Dev/Fn: B Slot: 0 |
| INT: A link: 4 bitmap: 200 IRQ: 9 |
| INT: B link: 0 bitmap: 0 not routed |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 9 to 0:b.0 |
| PIRQ Entry 4 Dev/Fn: C Slot: 0 |
| INT: A link: 1 bitmap: 800 IRQ: 11 |
| INT: B link: 2 bitmap: 400 IRQ: 10 |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| Assigning IRQ 11 to 0:c.0 |
| PIRQ Entry 5 Dev/Fn: E Slot: 0 |
| INT: A link: 3 bitmap: 800 IRQ: 11 |
| INT: B link: 4 bitmap: 200 IRQ: 9 |
| INT: C link: 0 bitmap: 0 not routed |
| INT: D link: 0 bitmap: 0 not routed |
| PIRQ Entry 6 Dev/Fn: F Slot: 0 |
| INT: A link: 1 bitmap: 800 IRQ: 11 |
| INT: B link: 2 bitmap: 400 IRQ: 10 |
| INT: C link: 3 bitmap: 800 IRQ: 11 |
| INT: D link: 4 bitmap: 200 IRQ: 9 |
| Assigning IRQ 9 to 0:f.4 |
| Assigning IRQ 9 to 0:f.5 |
| PIRQA: 11 |
| PIRQB: 10 |
| PIRQC: 11 |
| PIRQD: 9 |
| PIRQ table: 144 bytes. |
| Adding CBMEM entry as no. 5 |
| smbios_write_tables: 0f7c1600 |
| Root Device (PC Engines ALIX.2C) |
| DOMAIN: 0000 (AMD LX Northbridge) |
| PCI: 00:01.0 (AMD LX Northbridge) |
| PCI: 00:01.1 (AMD LX Northbridge) |
| PCI: 00:0f.0 (AMD Geode CS5536 Southbridge) |
| PCI: 00:0f.1 (AMD Geode CS5536 Southbridge) |
| PCI: 00:0f.2 (AMD Geode CS5536 Southbridge) |
| PCI: 00:0f.4 (AMD Geode CS5536 Southbridge) |
| PCI: 00:0f.5 (AMD Geode CS5536 Southbridge) |
| CPU_CLUSTER: 0 (AMD LX Northbridge) |
| APIC: 00 (unknown) |
| PCI: 00:01.2 (unknown) |
| PCI: 00:09.0 (unknown) |
| PCI: 00:0a.0 (unknown) |
| PCI: 00:0b.0 (unknown) |
| PCI: 00:0c.0 (unknown) |
| PCI: 00:0f.3 (unknown) |
| PCI: 00:0f.6 (unknown) |
| PCI: 00:0f.7 (unknown) |
| CPU: 00 (unknown) |
| SMBIOS tables: 348 bytes. |
| Adding CBMEM entry as no. 6 |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum d262 |
| Table forward entry ends at 0x00000528. |
| ... aligned to 0x00001000 |
| Writing coreboot table at 0x0f7c1e00 |
| rom_table_end = 0x0f7c1e00 |
| ... aligned to 0x0f7d0000 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000c0000-000000000f7affff: RAM |
| 3. 000000000f7b0000-000000000f7dffff: CONFIGURATION TABLES |
| Wrote coreboot table at: 0f7c1e00, 0x158 bytes, checksum 106b |
| coreboot table: 368 bytes. |
| FREE SPACE 0. 0f7c9e00 00016200 |
| GDT 1. 0f7b0200 00000200 |
| CONSOLE 2. 0f7b0400 00010000 |
| TIME STAMP 3. 0f7c0400 00000200 |
| IRQ TABLE 4. 0f7c0600 00001000 |
| SMBIOS 5. 0f7c1600 00000800 |
| COREBOOT 6. 0f7c1e00 00008000 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 1232140 exit 0 |
| CBFS: located payload @ fff9fdb8, 52946 bytes. |
| Loading segment from rom address 0xfff9fdb8 |
| code (compression=1) |
| New segment dstaddr 0xe7170 memsize 0x18e90 srcaddr 0xfff9fdf0 filesize 0xce9a |
| (cleaned up) New segment addr 0xe7170 size 0x18e90 offset 0xfff9fdf0 filesize 0xce9a |
| Loading segment from rom address 0xfff9fdd4 |
| Entry Point 0x000fd53e |
| Bounce Buffer at 0f74a000, 417792 bytes |
| Loading Segment: addr: 0x00000000000e7170 memsz: 0x0000000000018e90 filesz: 0x000000000000ce9a |
| lb: [0x0000000000100000, 0x0000000000133000) |
| Post relocation: addr: 0x00000000000e7170 memsz: 0x0000000000018e90 filesz: 0x000000000000ce9a |
| using LZMA |
| [ 0x000e7170, 00100000, 0x00100000) <- fff9fdf0 |
| dest 000e7170, end 00100000, bouncebuffer f74a000 |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 306782 exit 0 |
| Jumping to boot code at 000fd53e |
| CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb2c, stack used: 1236 bytes |
| entry = 0x000fd53e |
| lb_start = 0x00100000 |
| lb_size = 0x00033000 |
| buffer = 0x0f74a000 |
| ----- [ SeaBIOS rel-1.7.4-0-g96917a8-20140815_211649-debian-vm ] ----- |
| Found coreboot cbmem console @ f7b0400 |
| Found mainboard PC Engines ALIX.2C |
| Relocating init from 0x000e81e9 to 0x0f796060 (size 40659) |
| Found CBFS header at 0xfffffcd0 |
| CPU Mhz=498 |
| Found 10 PCI devices (max PCI bus is 00) |
| Copying SMBIOS entry point from 0x0f7c1600 to 0x000f20a0 |
| Scan for VGA option rom |
| EHCI init on dev 00:0f.5 (regs=0xfe027010) |
| WARNING - Timeout at i8042_flush:71! |
| Found 0 lpt ports |
| Found 2 serial ports |
| ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a) |
| ATA controller 2 at 170/374/0 (irq 15 dev 7a) |
| ata0-0: HMS360404D5CF00 ATA-4 Hard-Disk (3906 MiBytes) |
| Searching bootorder for: /pci@i0cf8/*@f,2/drive@0/disk@0 |
| All threads complete. |
| Scan for option roms |
| |
| Press F12 for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f2050: PCHS=7936/16/63 translation=large LCHS=992/128/63 s=7999488 |
| Space available for UMB: c0000-ef000, f0000-f2050 |
| Returned 65536 bytes of ZoneHigh |
| e820 map has 5 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000000f7b0000 = 1 RAM |
| 4: 000000000f7b0000 - 000000000f7e0000 = 2 RESERVED |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |