blob: e28cf2d6c2ddf40a618db2674aaa371c6e9660dd [file] [log] [blame]
coreboot-4.6-1491-g612ec0e Sun Sep 17 21:31:22 UTC 2017 ramstage starting...
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:0f.2: enabled 1
PCI: 00:0f.4: enabled 1
PCI: 00:0f.5: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
Compare with tree...
Root Device: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:0f.2: enabled 1
PCI: 00:0f.4: enabled 1
PCI: 00:0f.5: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
>> Entering northbridge.c: enable_dev with path 6
>> Entering northbridge.c: pci_domain_enable
Enter northbridge_init_early
writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SysmemInit: enable for 256MBytes
usable RAM: 268304383 bytes
SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SMMGL0Init: 268304384 bytes
SMMGL0Init: offset is 0x80400000
SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0
writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SysmemInit: enable for 256MBytes
usable RAM: 268304383 bytes
SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100
SMMGL1Init:
SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0
writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00
CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
L2 cache enabled
Enabling cache
GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000
Exit northbridge_init_early
Done cpubug fixes
Not Doing ChipsetFlashSetup()
Preparing for VSA...
Real mode stub @00000600: 867 bytes
CBFS: 'Master Header Locator' located CBFS at [c0100:fffc0)
CBFS: Locating 'vsa'
CBFS: Found @ offset 1e0c0 size e0bc
VSA: Buffer @00060000 *[0k]=ba
VSA: Signature *[0x20-0x23] is b0:10:e6:80
Calling VSA module...
... VSA module returned.
VSM: VSA2 VR signature verified.
Graphics init...
VRC_VG value: 0x2808
DOMAIN: 0000 enabled
>> Entering northbridge.c: enable_dev with path 7
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
>> Entering northbridge.c: enable_dev with path 2
PCI: 00:01.0 [1022/2080] ops
PCI: 00:01.0 [1022/2080] enabled
>> Entering northbridge.c: enable_dev with path 2
PCI: 00:01.1 [1022/2081] enabled
PCI: 00:01.2 [1022/2082] enabled
PCI: 00:09.0 [1106/3053] enabled
cs5536: southbridge_enable: dev is 001116c0
PCI: 00:0f.0 [1022/2090] bus ops
PCI: 00:0f.0 [1022/2090] enabled
cs5536: southbridge_enable: dev is 00111620
PCI: Static device PCI: 00:0f.1 not found, disabling it.
cs5536: southbridge_enable: dev is 00111580
PCI: 00:0f.2 [1022/209a] ops
PCI: 00:0f.2 [1022/209a] enabled
PCI: 00:0f.3 [1022/2093] enabled
cs5536: southbridge_enable: dev is 001114e0
PCI: 00:0f.4 [1022/2094] enabled
cs5536: southbridge_enable: dev is 00111440
PCI: 00:0f.5 [1022/2095] enabled
PCI: 00:0f.6 [1022/2096] enabled
PCI: 00:0f.7 [1022/2097] enabled
PCI: 00:0f.0 scanning...
scan_generic_bus for PCI: 00:0f.0
scan_generic_bus for PCI: 00:0f.0 done
scan_bus: scanning of bus PCI: 00:0f.0 took 8785 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 93484 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 332630 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 394855 exit 0
found VGA at PCI: 00:01.1
Setting up VGA for PCI: 00:01.1
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
DOMAIN: 0000 read_resources bus 0 link: 0
DOMAIN: 0000 read_resources bus 0 link: 0 done
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 DOMAIN: 0000
DOMAIN: 0000 child on link 0 PCI: 00:01.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10
PCI: 00:01.1
PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 20
PCI: 00:01.2
PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:09.0
PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 00:09.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
PCI: 00:0f.0
PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18
PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c
PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20
PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:0f.1
PCI: 00:0f.2
PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:0f.3
PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10
PCI: 00:0f.4
PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:0f.5
PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:0f.6
PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
PCI: 00:0f.7
PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:09.0 10 * [0x0 - 0xff] io
PCI: 00:0f.0 14 * [0x400 - 0x4ff] io
PCI: 00:0f.0 20 * [0x800 - 0x87f] io
PCI: 00:0f.3 10 * [0x880 - 0x8ff] io
PCI: 00:0f.0 18 * [0xc00 - 0xc3f] io
PCI: 00:0f.0 24 * [0xc40 - 0xc7f] io
PCI: 00:0f.0 1c * [0xc80 - 0xc9f] io
PCI: 00:0f.2 20 * [0xca0 - 0xcaf] io
PCI: 00:0f.0 10 * [0xcb0 - 0xcb7] io
PCI: 00:01.0 10 * [0xcb8 - 0xcbb] io
DOMAIN: 0000 io: base: cbc size: cbc align: 8 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.1 10 * [0x0 - 0xffffff] mem
PCI: 00:01.1 14 * [0x1000000 - 0x1003fff] mem
PCI: 00:01.1 18 * [0x1004000 - 0x1007fff] mem
PCI: 00:01.1 1c * [0x1008000 - 0x100bfff] mem
PCI: 00:01.1 20 * [0x100c000 - 0x100ffff] mem
PCI: 00:01.2 10 * [0x1010000 - 0x1013fff] mem
PCI: 00:0f.6 10 * [0x1014000 - 0x1015fff] mem
PCI: 00:0f.4 10 * [0x1016000 - 0x1016fff] mem
PCI: 00:0f.5 10 * [0x1017000 - 0x1017fff] mem
PCI: 00:0f.7 10 * [0x1018000 - 0x1018fff] mem
PCI: 00:09.0 14 * [0x1019000 - 0x10190ff] mem
DOMAIN: 0000 mem: base: 1019100 size: 1019100 align: 24 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:0f.0 01 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:0f.0 03 base fec00000 limit fec00fff mem (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base fd000000 limit febfffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:cbc align:8 gran:0 limit:ffff
PCI: 00:09.0 10 * [0x1000 - 0x10ff] io
PCI: 00:0f.0 14 * [0x1400 - 0x14ff] io
PCI: 00:0f.0 20 * [0x1800 - 0x187f] io
PCI: 00:0f.3 10 * [0x1880 - 0x18ff] io
PCI: 00:0f.0 18 * [0x1c00 - 0x1c3f] io
PCI: 00:0f.0 24 * [0x1c40 - 0x1c7f] io
PCI: 00:0f.0 1c * [0x1c80 - 0x1c9f] io
PCI: 00:0f.2 20 * [0x1ca0 - 0x1caf] io
PCI: 00:0f.0 10 * [0x1cb0 - 0x1cb7] io
PCI: 00:01.0 10 * [0x1cb8 - 0x1cbb] io
DOMAIN: 0000 io: next_base: 1cbc size: cbc align: 8 gran: 0 done
DOMAIN: 0000 mem: base:fd000000 size:1019100 align:24 gran:0 limit:febfffff
PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem
PCI: 00:01.1 14 * [0xfe000000 - 0xfe003fff] mem
PCI: 00:01.1 18 * [0xfe004000 - 0xfe007fff] mem
PCI: 00:01.1 1c * [0xfe008000 - 0xfe00bfff] mem
PCI: 00:01.1 20 * [0xfe00c000 - 0xfe00ffff] mem
PCI: 00:01.2 10 * [0xfe010000 - 0xfe013fff] mem
PCI: 00:0f.6 10 * [0xfe014000 - 0xfe015fff] mem
PCI: 00:0f.4 10 * [0xfe016000 - 0xfe016fff] mem
PCI: 00:0f.5 10 * [0xfe017000 - 0xfe017fff] mem
PCI: 00:0f.7 10 * [0xfe018000 - 0xfe018fff] mem
PCI: 00:09.0 14 * [0xfe019000 - 0xfe0190ff] mem
DOMAIN: 0000 mem: next_base: fe019100 size: 1019100 align: 24 gran: 0 done
Root Device assign_resources, bus 0 link: 0
>> Entering northbridge.c: pci_domain_set_resources
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem
PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 20 <- [0x00fe00c000 - 0x00fe00ffff] size 0x00004000 gran 0x0e mem
PCI: 00:01.2 10 <- [0x00fe010000 - 0x00fe013fff] size 0x00004000 gran 0x0e mem
PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:09.0 14 <- [0x00fe019000 - 0x00fe0190ff] size 0x00000100 gran 0x08 mem
PCI: 00:0f.0 10 <- [0x0000001cb0 - 0x0000001cb7] size 0x00000008 gran 0x03 io
PCI: 00:0f.0 14 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
PCI: 00:0f.0 18 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
PCI: 00:0f.0 1c <- [0x0000001c80 - 0x0000001c9f] size 0x00000020 gran 0x05 io
PCI: 00:0f.0 20 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io
PCI: 00:0f.0 24 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io
PCI: 00:0f.2 20 <- [0x0000001ca0 - 0x0000001caf] size 0x00000010 gran 0x04 io
PCI: 00:0f.3 10 <- [0x0000001880 - 0x00000018ff] size 0x00000080 gran 0x07 io
PCI: 00:0f.4 10 <- [0x00fe016000 - 0x00fe016fff] size 0x00001000 gran 0x0c mem
PCI: 00:0f.5 10 <- [0x00fe017000 - 0x00fe017fff] size 0x00001000 gran 0x0c mem
PCI: 00:0f.6 10 <- [0x00fe014000 - 0x00fe015fff] size 0x00002000 gran 0x0d mem
PCI: 00:0f.7 10 <- [0x00fe018000 - 0x00fe018fff] size 0x00001000 gran 0x0c mem
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 DOMAIN: 0000
DOMAIN: 0000 child on link 0 PCI: 00:01.0
DOMAIN: 0000 resource base 1000 size cbc align 8 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base fd000000 size 1019100 align 24 gran 0 limit febfffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
DOMAIN: 0000 resource base c0000 size f720000 align 0 gran 0 limit 0 flags e0004200 index b
PCI: 00:01.0
PCI: 00:01.0 resource base 1cb8 size 4 align 2 gran 2 limit 1cbb flags 40000100 index 10
PCI: 00:01.1
PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit fdffffff flags 60000200 index 10
PCI: 00:01.1 resource base fe000000 size 4000 align 14 gran 14 limit fe003fff flags 60000200 index 14
PCI: 00:01.1 resource base fe004000 size 4000 align 14 gran 14 limit fe007fff flags 60000200 index 18
PCI: 00:01.1 resource base fe008000 size 4000 align 14 gran 14 limit fe00bfff flags 60000200 index 1c
PCI: 00:01.1 resource base fe00c000 size 4000 align 14 gran 14 limit fe00ffff flags 60000200 index 20
PCI: 00:01.2
PCI: 00:01.2 resource base fe010000 size 4000 align 14 gran 14 limit fe013fff flags 60000200 index 10
PCI: 00:09.0
PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
PCI: 00:09.0 resource base fe019000 size 100 align 12 gran 8 limit fe0190ff flags 60000200 index 14
PCI: 00:0f.0
PCI: 00:0f.0 resource base 1cb0 size 8 align 3 gran 3 limit 1cb7 flags 60000100 index 10
PCI: 00:0f.0 resource base 1400 size 100 align 8 gran 8 limit 14ff flags 60000100 index 14
PCI: 00:0f.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 18
PCI: 00:0f.0 resource base 1c80 size 20 align 5 gran 5 limit 1c9f flags 60000100 index 1c
PCI: 00:0f.0 resource base 1800 size 80 align 7 gran 7 limit 187f flags 60000100 index 20
PCI: 00:0f.0 resource base 1c40 size 40 align 6 gran 6 limit 1c7f flags 60000100 index 24
PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:0f.1
PCI: 00:0f.2
PCI: 00:0f.2 resource base 1ca0 size 10 align 4 gran 4 limit 1caf flags 60000100 index 20
PCI: 00:0f.3
PCI: 00:0f.3 resource base 1880 size 80 align 7 gran 7 limit 18ff flags 60000100 index 10
PCI: 00:0f.4
PCI: 00:0f.4 resource base fe016000 size 1000 align 12 gran 12 limit fe016fff flags 60000200 index 10
PCI: 00:0f.5
PCI: 00:0f.5 resource base fe017000 size 1000 align 12 gran 12 limit fe017fff flags 60000200 index 10
PCI: 00:0f.6
PCI: 00:0f.6 resource base fe014000 size 2000 align 13 gran 13 limit fe015fff flags 60000200 index 10
PCI: 00:0f.7
PCI: 00:0f.7 resource base fe018000 size 1000 align 12 gran 12 limit fe018fff flags 60000200 index 10
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 976335 exit 0
Enabling resources...
PCI: 00:01.0 cmd <- 05
PCI: 00:01.1 subsystem <- 1022/2081
PCI: 00:01.1 cmd <- 03
PCI: 00:01.2 cmd <- 02
PCI: 00:09.0 cmd <- 83
PCI: 00:0f.0 cmd <- 09
PCI: 00:0f.2 cmd <- 01
PCI: 00:0f.3 cmd <- 01
PCI: 00:0f.4 subsystem <- 1022/2094
PCI: 00:0f.4 cmd <- 02
PCI: 00:0f.5 subsystem <- 1022/2095
PCI: 00:0f.5 cmd <- 02
PCI: 00:0f.6 cmd <- 02
PCI: 00:0f.7 cmd <- 02
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 35980 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 1921 usecs
CPU_CLUSTER: 0 init ...
>> Entering northbridge.c: cpu_bus_init
Initializing CPU #0
CPU: vendor AMD device 5a2
CPU: family 05, model 0a, stepping 02
geode_lx_init
Enabling cache
A20 (0x92): 2
A20 (0x92): 2
CPU geode_lx_init DONE
CPU #0 initialized
CPU_CLUSTER: 0 init finished in 22674 usecs
PCI: 00:01.0 init ...
>> Entering northbridge.c: northbridge_init
PCI: 00:01.0 init finished in 5922 usecs
PCI: 00:01.1 init ...
CBFS: 'Master Header Locator' located CBFS at [c0100:fffc0)
CBFS: Locating 'pci1022,2081.rom'
CBFS: 'pci1022,2081.rom' not found.
PCI Option ROM loading disabled for PCI: 00:01.1
PCI: 00:01.1 init finished in 18214 usecs
PCI: 00:01.2 init ...
PCI: 00:01.2 init finished in 2003 usecs
PCI: 00:09.0 init ...
PCI: 00:09.0 init finished in 2003 usecs
PCI: 00:0f.0 init ...
cs5536: southbridge_init
RTC Init
GPIO_ADDR: 00001400
uarts_init: enable COM1
uarts_init: enable COM2
uarts_init: wrote COM2 address 0x2f8
uarts_init: set COM2 irq
uarts_init: set output enable
uarts_init: set OUTAUX1
uarts_init: set pullup COM2
uarts_init: COM2 enabled
cs5536: southbridge_init: enable_ide_nand_flash is 0
Disabling VPCI device: 0x80000900
Disabling VPCI device: 0x80007B00
PCI: 00:0f.0 init finished in 37880 usecs
PCI: 00:0f.2 init ...
cs5536_ide: ide_init
PCI: 00:0f.2 init finished in 3982 usecs
PCI: 00:0f.3 init ...
PCI: 00:0f.3 init finished in 2004 usecs
PCI: 00:0f.4 init ...
PCI: 00:0f.4 init finished in 2003 usecs
PCI: 00:0f.5 init ...
PCI: 00:0f.5 init finished in 2004 usecs
PCI: 00:0f.6 init ...
PCI: 00:0f.6 init finished in 2004 usecs
PCI: 00:0f.7 init ...
PCI: 00:0f.7 init finished in 2004 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 0
PCI: 00:0f.2: enabled 1
PCI: 00:0f.4: enabled 1
PCI: 00:0f.5: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI: 00:01.2: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0f.3: enabled 1
PCI: 00:0f.6: enabled 1
PCI: 00:0f.7: enabled 1
CPU: 00: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 195437 exit 0
CBMEM:
IMD: root @ 0f7df000 254 entries.
IMD: root @ 0f7dec00 62 entries.
Moving GDT to 0f7dea00...ok
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 11046 run 3495 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
Copying Interrupt Routing Table to 0x000f0000... done.
PIRQ Entry 0 Dev/Fn: 1 Slot: 0
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
Assigning IRQ 11 to 0:1.2
PIRQ Entry 1 Dev/Fn: 9 Slot: 0
INT: A link: 2 bitmap: 400 IRQ: 10
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
Assigning IRQ 10 to 0:9.0
PIRQ Entry 2 Dev/Fn: A Slot: 0
INT: A link: 3 bitmap: 800 IRQ: 11
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 3 Dev/Fn: B Slot: 0
INT: A link: 4 bitmap: 200 IRQ: 9
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 4 Dev/Fn: C Slot: 0
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 400 IRQ: 10
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 5 Dev/Fn: E Slot: 0
INT: A link: 3 bitmap: 800 IRQ: 11
INT: B link: 4 bitmap: 200 IRQ: 9
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 6 Dev/Fn: F Slot: 0
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 400 IRQ: 10
INT: C link: 3 bitmap: 800 IRQ: 11
INT: D link: 4 bitmap: 200 IRQ: 9
Assigning IRQ 9 to 0:f.4
Assigning IRQ 9 to 0:f.5
PIRQA: 11
PIRQB: 10
PIRQC: 11
PIRQD: 9
Copying Interrupt Routing Table to 0x0f7b4000... done.
PIRQ Entry 0 Dev/Fn: 1 Slot: 0
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
Assigning IRQ 11 to 0:1.2
PIRQ Entry 1 Dev/Fn: 9 Slot: 0
INT: A link: 2 bitmap: 400 IRQ: 10
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
Assigning IRQ 10 to 0:9.0
PIRQ Entry 2 Dev/Fn: A Slot: 0
INT: A link: 3 bitmap: 800 IRQ: 11
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 3 Dev/Fn: B Slot: 0
INT: A link: 4 bitmap: 200 IRQ: 9
INT: B link: 0 bitmap: 0 not routed
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 4 Dev/Fn: C Slot: 0
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 400 IRQ: 10
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 5 Dev/Fn: E Slot: 0
INT: A link: 3 bitmap: 800 IRQ: 11
INT: B link: 4 bitmap: 200 IRQ: 9
INT: C link: 0 bitmap: 0 not routed
INT: D link: 0 bitmap: 0 not routed
PIRQ Entry 6 Dev/Fn: F Slot: 0
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 400 IRQ: 10
INT: C link: 3 bitmap: 800 IRQ: 11
INT: D link: 4 bitmap: 200 IRQ: 9
Assigning IRQ 9 to 0:f.4
Assigning IRQ 9 to 0:f.5
PIRQA: 11
PIRQB: 10
PIRQC: 11
PIRQD: 9
PIRQ table: 144 bytes.
smbios_write_tables: 0f7b3000
Root Device (PC Engines ALIX.2D)
DOMAIN: 0000 (AMD LX Northbridge)
PCI: 00:01.0 (AMD LX Northbridge)
PCI: 00:01.1 (AMD LX Northbridge)
PCI: 00:0f.0 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.1 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.2 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.4 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.5 (AMD Geode CS5536 Southbridge)
CPU_CLUSTER: 0 (AMD LX Northbridge)
APIC: 00 (unknown)
PCI: 00:01.2 (unknown)
PCI: 00:09.0 (unknown)
PCI: 00:0f.3 (unknown)
PCI: 00:0f.6 (unknown)
PCI: 00:0f.7 (unknown)
CPU: 00 (unknown)
SMBIOS tables: 374 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum a063
Writing coreboot table at 0x0f7b5000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-000000000f7b2fff: RAM
3. 000000000f7b3000-000000000f7dffff: CONFIGURATION TABLES
CBFS: 'Master Header Locator' located CBFS at [c0100:fffc0)
FMAP: Found "FLASH" version 1.1 at c0000.
FMAP: base = fff00000 size = 100000 #areas = 3
Wrote coreboot table at: 0f7b5000, 0x1f8 bytes, checksum 824f
coreboot table: 528 bytes.
IMD ROOT 0. 0f7df000 00001000
IMD SMALL 1. 0f7de000 00001000
CONSOLE 2. 0f7be000 00020000
TIME STAMP 3. 0f7bd000 00000400
COREBOOT 4. 0f7b5000 00008000
IRQ TABLE 5. 0f7b4000 00001000
SMBIOS 6. 0f7b3000 00000800
IMD small region:
IMD ROOT 0. 0f7dec00 00000400
GDT 1. 0f7dea00 00000200
BS: BS_WRITE_TABLES times (us): entry 0 run 395886 exit 0
CBFS: 'Master Header Locator' located CBFS at [c0100:fffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset df00 size f9af
Loading segment from ROM address 0xfffce038
code (compression=1)
New segment dstaddr 0xe23c0 memsize 0x1dc40 srcaddr 0xfffce070 filesize 0xf977
Loading segment from ROM address 0xfffce054
Entry Point 0x000ff06e
Bounce Buffer at 0f73a000, 493904 bytes
Loading Segment: addr: 0x00000000000e23c0 memsz: 0x000000000001dc40 filesz: 0x000000000000f977
lb: [0x0000000000100000, 0x000000000013c4a8)
Post relocation: addr: 0x00000000000e23c0 memsz: 0x000000000001dc40 filesz: 0x000000000000f977
using LZMA
[ 0x000e23c0, 00100000, 0x00100000) <- fffce070
dest 000e23c0, end 00100000, bouncebuffer f73a000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 198030 exit 0
Jumping to boot code at 000ff06e(0f7b5000)
CPU0: stack: 00113000 - 00114000, lowest used address 00113c00, stack used: 1024 bytes
entry = 0x000ff06e
lb_start = 0x00100000
lb_size = 0x0003c4a8
buffer = 0x0f73a000
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
BUILD: gcc: (coreboot toolchain v1.47 August 16th, 2017) 6.3.0 binutils: (GNU Binutils) 2.28
Found coreboot cbmem console @ f7be000
Found mainboard PC Engines ALIX.2D
Relocating init from 0x000e3940 to 0x0f766da0 (size 49600)
Found CBFS header at 0xfffc0138
multiboot: eax=0, ebx=0
Found 7 PCI devices (max PCI bus is 00)
Copying SMBIOS entry point from 0x0f7b3000 to 0x000f7120
CPU Mhz=498
Scan for VGA option rom
EHCI init on dev 00:0f.5 (regs=0xfe017010)
OHCI init on dev 00:0f.4 (regs=0xfe016000)
WARNING - Timeout at i8042_flush:71!
ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a)
ATA controller 2 at 170/374/0 (irq 15 dev 7a)
Found 0 lpt ports
Found 2 serial ports
ata0-0: CF 2GB ATA-7 Hard-Disk (1919 MiBytes)
Searching bootorder for: /pci@i0cf8/*@f,2/drive@0/disk@0
All threads complete.
Scan for option roms
Press ESC for boot menu.
Searching bootorder for: HALT
drive 0x000f70b0: PCHS=3900/16/63 translation=large LCHS=975/64/63 s=3931200
Space available for UMB: c0000-ef000, f6940-f70b0
Returned 262144 bytes of ZoneHigh
e820 map has 5 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000000f7b3000 = 1 RAM
4: 000000000f7b3000 - 000000000f7e0000 = 2 RESERVED
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00