| |
| [NOTE ] coreboot-4.20-1205-g52fb64be42f3 Sun Aug 20 02:19:36 UTC 2023 x86_32 bootblock starting (log level: 8)... |
| [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x260000. |
| [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 |
| [DEBUG] FMAP: area COREBOOT found @ 260200 (1703424 bytes) |
| [INFO ] CBFS: mcache @0xfefc2e00 built for 16 files, used 0x364 of 0x4000 bytes |
| [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xe018 in mcache @0xfefc2e2c |
| [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms |
| [DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe60000, size: 0x00010000 |
| |
| |
| [NOTE ] coreboot-4.20-1205-g52fb64be42f3 Sun Aug 20 02:19:36 UTC 2023 x86_32 romstage starting (log level: 8)... |
| [DEBUG] SMBus controller enabled |
| [WARN ] Ignoring S4-assertion-width violation. |
| [DEBUG] Stepping B3 |
| [SPEW ] 2 CPU cores |
| [SPEW ] AMT enabled |
| [SPEW ] capable of DDR2 of 800 MHz or lower |
| [SPEW ] VT-d enabled |
| [SPEW ] GMCH: GM45 |
| [SPEW ] TXT enabled |
| [SPEW ] Render frequency: 533 MHz |
| [SPEW ] IGD enabled |
| [SPEW ] PCIe-to-GMCH enabled |
| [SPEW ] GMCH supports DDR3 with 1067 MT or less |
| [SPEW ] GMCH supports FSB with up to 1067 MHz |
| [DEBUG] 0:50:8 |
| [DEBUG] 2:52:8 |
| [SPEW ] DDR mask 5, DDR 2 |
| [SPEW ] Bank 0 populated: |
| [SPEW ] Raw card type: A |
| [SPEW ] Row addr bits: 14 |
| [SPEW ] Col addr bits: 10 |
| [SPEW ] byte width: 1 |
| [SPEW ] page size: 1024 |
| [SPEW ] banks: 8 |
| [SPEW ] ranks: 2 |
| [SPEW ] tAAmin: 3840 |
| [SPEW ] tCKmin: 640 |
| [SPEW ] Max clock: 400 MHz |
| [SPEW ] CAS: 0x0070 |
| [SPEW ] Bank 1 populated: |
| [SPEW ] Raw card type: A |
| [SPEW ] Row addr bits: 14 |
| [SPEW ] Col addr bits: 10 |
| [SPEW ] byte width: 1 |
| [SPEW ] page size: 1024 |
| [SPEW ] banks: 8 |
| [SPEW ] ranks: 2 |
| [SPEW ] tAAmin: 3840 |
| [SPEW ] tCKmin: 640 |
| [SPEW ] Max clock: 400 MHz |
| [SPEW ] CAS: 0x0070 |
| [SPEW ] Trying CAS 6, tCK 640. |
| [SPEW ] Found compatible clock / CAS pair: 400 / 6. |
| [SPEW ] Timing values: |
| [SPEW ] tCLK: 640 |
| [SPEW ] tRAS: 18 |
| [SPEW ] tRP: 6 |
| [SPEW ] tRCD: 6 |
| [SPEW ] tRFC: 51 |
| [SPEW ] tWR: 6 |
| [SPEW ] tRD: 9 |
| [SPEW ] tRRD: 3 |
| [SPEW ] tFAW: 15 |
| [SPEW ] tWL: 5 |
| [DEBUG] Changing memory frequency: old 3, new 5. |
| [DEBUG] Setting IGD memory frequencies for VCO #1. |
| [DEBUG] Memory configured in dual-channel asymmetric mode. |
| [SPEW ] Memory map: |
| [SPEW ] TOM = 512MB |
| [SPEW ] TOLUD = 512MB |
| [SPEW ] TOUUD = 512MB |
| [SPEW ] REMAP: base = 65535MB |
| [SPEW ] limit = 0MB |
| [SPEW ] usedMEsize: 0MB |
| [DEBUG] JEDEC init @0x00000000 |
| [DEBUG] JEDEC init @0x08000000 |
| [DEBUG] JEDEC init @0x10000000 |
| [DEBUG] JEDEC init @0x18000000 |
| [DEBUG] group 0, ch 0: 5.0.2.11.0 |
| [DEBUG] group 1, ch 0: 5.0.2.9.0 |
| [DEBUG] group 2, ch 0: 5.0.2.9.0 |
| [DEBUG] group 3, ch 0: 5.0.2.11.0 |
| [DEBUG] group 0, ch 1: 5.0.2.12.0 |
| [DEBUG] group 1, ch 1: 5.0.2.13.0 |
| [DEBUG] group 2, ch 1: 5.0.2.12.0 |
| [DEBUG] group 3, ch 1: 5.0.2.12.0 |
| [DEBUG] IGD decoded, subtracting 32M UMA and 4M GTT |
| [DEBUG] Memory configured in dual-channel interleaved mode. |
| [SPEW ] Memory map: |
| [SPEW ] TOM = 4096MB |
| [SPEW ] TOLUD = 2048MB |
| [SPEW ] TOUUD = 6144MB |
| [SPEW ] REMAP: base = 4096MB |
| [SPEW ] limit = 6080MB |
| [SPEW ] usedMEsize: 0MB |
| [DEBUG] Enabling IGD. |
| [DEBUG] Finally disabling PEG in favor of IGD. |
| [DEBUG] PEG x1 disabled, SDVO disabled |
| [DEBUG] ICH9 waits for VC1 negotiation... done. |
| [DEBUG] ICH9 waits for port arbitration table update... done. |
| [DEBUG] CBMEM: |
| [DEBUG] IMD: root @ 0x7d7ff000 254 entries. |
| [DEBUG] IMD: root @ 0x7d7fec00 62 entries. |
| [DEBUG] FMAP: area COREBOOT found @ 260200 (1703424 bytes) |
| [DEBUG] External stage cache: |
| [DEBUG] IMD: root @ 0x7dbff000 254 entries. |
| [DEBUG] IMD: root @ 0x7dbfec00 62 entries. |
| [SPEW ] exit main() |
| [DEBUG] SMM Memory Map |
| [DEBUG] SMRAM : 0x7da00000 0x200000 |
| [DEBUG] Subregion 0: 0x7da00000 0x100000 |
| [DEBUG] Subregion 1: 0x7db00000 0x100000 |
| [DEBUG] Subregion 2: 0x7dc00000 0x0 |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/postcar' @0x53e00 size 0x5a60 in mcache @0xfefc305c |
| [DEBUG] Loading module at 0x7d7d0000 with entry 0x7d7d0031. filesize: 0x5660 memsize: 0xb998 |
| [DEBUG] Processing 240 relocs. Offset value of 0x7b7d0000 |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 2 ms |
| |
| |
| [NOTE ] coreboot-4.20-1205-g52fb64be42f3 Sun Aug 20 02:19:36 UTC 2023 x86_32 postcar starting (log level: 8)... |
| [DEBUG] Normal boot |
| [DEBUG] FMAP: area COREBOOT found @ 260200 (1703424 bytes) |
| [INFO ] CBFS: Found 'fallback/ramstage' @0x2f180 size 0x1a0b4 in mcache @0x7d7dd0dc |
| [DEBUG] Loading module at 0x7d78d000 with entry 0x7d78d000. filesize: 0x32570 memsize: 0x416b0 |
| [DEBUG] Processing 3718 relocs. Offset value of 0x7978d000 |
| [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms |
| |
| |
| [NOTE ] coreboot-4.20-1205-g52fb64be42f3 Sun Aug 20 02:19:36 UTC 2023 x86_32 ramstage starting (log level: 8)... |
| [DEBUG] Normal boot |
| [DEBUG] Initializing i82801ix southbridge... |
| [INFO ] Enumerating buses... |
| [SPEW ] Show all devs... Before device enumeration. |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 0 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:02.1: enabled 1 |
| [SPEW ] PCI: 00:03.0: enabled 1 |
| [SPEW ] PCI: 00:03.1: enabled 0 |
| [SPEW ] PCI: 00:03.2: enabled 0 |
| [SPEW ] PCI: 00:03.3: enabled 0 |
| [SPEW ] PCI: 00:19.0: enabled 1 |
| [SPEW ] PCI: 00:1a.0: enabled 1 |
| [SPEW ] PCI: 00:1a.1: enabled 1 |
| [SPEW ] PCI: 00:1a.2: enabled 1 |
| [SPEW ] PCI: 00:1a.7: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 1 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1d.1: enabled 1 |
| [SPEW ] PCI: 00:1d.2: enabled 1 |
| [SPEW ] PCI: 00:1d.7: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 1 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.5: enabled 0 |
| [SPEW ] PCI: 00:1f.6: enabled 0 |
| [SPEW ] PNP: 00ff.0: enabled 1 |
| [SPEW ] Compare with tree... |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 0 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:02.1: enabled 1 |
| [SPEW ] PCI: 00:03.0: enabled 1 |
| [SPEW ] PCI: 00:03.1: enabled 0 |
| [SPEW ] PCI: 00:03.2: enabled 0 |
| [SPEW ] PCI: 00:03.3: enabled 0 |
| [SPEW ] PCI: 00:19.0: enabled 1 |
| [SPEW ] PCI: 00:1a.0: enabled 1 |
| [SPEW ] PCI: 00:1a.1: enabled 1 |
| [SPEW ] PCI: 00:1a.2: enabled 1 |
| [SPEW ] PCI: 00:1a.7: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 1 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1d.1: enabled 1 |
| [SPEW ] PCI: 00:1d.2: enabled 1 |
| [SPEW ] PCI: 00:1d.7: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 1 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PNP: 00ff.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.5: enabled 0 |
| [SPEW ] PCI: 00:1f.6: enabled 0 |
| [DEBUG] Root Device scanning... |
| [SPEW ] scan_static_bus for Root Device |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 0000 enabled |
| [DEBUG] DOMAIN: 0000 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 00 |
| [DEBUG] PCI: 00:00.0 [8086/2a40] enabled |
| [SPEW ] PCI: 00:02.0 [8086/0000] ops |
| [DEBUG] PCI: 00:02.0 [8086/2a42] enabled |
| [DEBUG] PCI: 00:02.1 [8086/2a43] enabled |
| [INFO ] PCI: Static device PCI: 00:03.0 not found, disabling it. |
| [DEBUG] PCI: 00:19.0 [8086/10f5] enabled |
| [DEBUG] PCI: 00:1a.0 [8086/2937] enabled |
| [DEBUG] PCI: 00:1a.1 [8086/2938] enabled |
| [DEBUG] PCI: 00:1a.2 [8086/2939] enabled |
| [SPEW ] PCI: 00:1a.7 [8086/0000] ops |
| [DEBUG] PCI: 00:1a.7 [8086/293c] enabled |
| [SPEW ] PCI: 00:1b.0 [8086/293e] ops |
| [DEBUG] PCI: 00:1b.0 [8086/293e] enabled |
| [SPEW ] PCI: 00:1c.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.0 [8086/2940] enabled |
| [SPEW ] PCI: 00:1c.1 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.1 [8086/2942] enabled |
| [SPEW ] PCI: 00:1c.2 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.2 [8086/2944] enabled |
| [SPEW ] PCI: 00:1c.3 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.3 [8086/2946] enabled |
| [DEBUG] PCI: 00:1d.0 [8086/2934] enabled |
| [DEBUG] PCI: 00:1d.1 [8086/2935] enabled |
| [DEBUG] PCI: 00:1d.2 [8086/2936] enabled |
| [SPEW ] PCI: 00:1d.7 [8086/0000] ops |
| [DEBUG] PCI: 00:1d.7 [8086/293a] enabled |
| [SPEW ] PCI: 00:1e.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1e.0 [8086/2448] enabled |
| [SPEW ] PCI: 00:1f.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1f.0 [8086/2917] enabled |
| [SPEW ] PCI: 00:1f.2 [8086/0000] ops |
| [DEBUG] PCI: 00:1f.2 [8086/2928] enabled |
| [SPEW ] PCI: 00:1f.3 [8086/2930] bus ops |
| [DEBUG] PCI: 00:1f.3 [8086/2930] enabled |
| [WARN ] PCI: Leftover static devices: |
| [WARN ] PCI: 00:01.0 |
| [WARN ] PCI: 00:03.0 |
| [WARN ] PCI: 00:03.1 |
| [WARN ] PCI: 00:03.2 |
| [WARN ] PCI: 00:03.3 |
| [WARN ] PCI: 00:1c.4 |
| [WARN ] PCI: 00:1c.5 |
| [WARN ] PCI: 00:1f.5 |
| [WARN ] PCI: 00:1f.6 |
| [WARN ] PCI: Check your devicetree.cb. |
| [DEBUG] PCI: 00:1c.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.0 |
| [DEBUG] PCI: pci_scan_bus for bus 01 |
| [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.1 |
| [DEBUG] PCI: pci_scan_bus for bus 02 |
| [DEBUG] PCI: 02:00.0 [8086/4232] enabled |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 02:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.2 |
| [DEBUG] PCI: pci_scan_bus for bus 03 |
| [DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.3 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.3 |
| [DEBUG] PCI: pci_scan_bus for bus 04 |
| [DEBUG] scan_bus: bus PCI: 00:1c.3 finished in 0 msecs |
| [DEBUG] PCI: 00:1e.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1e.0 |
| [DEBUG] PCI: pci_scan_bus for bus 0d |
| [DEBUG] PCI: 0d:01.0 [1180/0476] enabled |
| [DEBUG] PCI: 0d:01.1 [1180/0832] enabled |
| [DEBUG] PCI: 0d:01.2 [1180/0822] enabled |
| [DEBUG] PCI: 0d:01.3 [1180/0843] enabled |
| [DEBUG] PCI: 0d:01.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 0d:01.0 |
| [DEBUG] PCI: pci_scan_bus for bus 0e |
| [DEBUG] scan_bus: bus PCI: 0d:01.0 finished in 0 msecs |
| [DEBUG] scan_bus: bus PCI: 00:1e.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 scanning... |
| [SPEW ] scan_static_bus for PCI: 00:1f.0 |
| [DEBUG] PNP: 00ff.0 enabled |
| [SPEW ] scan_static_bus for PCI: 00:1f.0 done |
| [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.3 scanning... |
| [SPEW ] scan_generic_bus for PCI: 00:1f.3 |
| [SPEW ] scan_generic_bus for PCI: 00:1f.3 done |
| [DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 0 msecs |
| [SPEW ] scan_static_bus for Root Device done |
| [DEBUG] scan_bus: bus Root Device finished in 0 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms |
| [DEBUG] found VGA at PCI: 00:02.0 |
| [DEBUG] Setting up VGA for PCI: 00:02.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [SPEW ] Root Device read_resources bus 0 link: 0 |
| [DEBUG] TOUUD 0x180000000 TOLUD 0x80000000 TOM 0x100000000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x3, base: 0x0, size: 0xa0000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x4, base: 0xa0000, size: 0x20000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x5, base: 0xc0000, size: 0x40000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x6, base: 0x100000, size: 0x7d800000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x7, base: 0x7da00000, size: 0x200000 |
| [DEBUG] Unused RAM between cbmem_top and TOM: 0x200000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x8, base: 0x7d800000, size: 0x200000 |
| [SPEW ] dev: DOMAIN: 0000, index: 0x9, base: 0x7dc00000, size: 0x2400000 |
| [INFO ] Available memory above 4GB: 2048M |
| [SPEW ] dev: DOMAIN: 0000, index: 0xa, base: 0x100000000, size: 0x80000000 |
| [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| [SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 |
| [SPEW ] PCI: 00:1c.0 read_resources bus 1 link: 0 |
| [SPEW ] PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| [SPEW ] PCI: 00:1c.1 read_resources bus 2 link: 0 |
| [SPEW ] PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| [SPEW ] PCI: 00:1c.2 read_resources bus 3 link: 0 |
| [SPEW ] PCI: 00:1c.2 read_resources bus 3 link: 0 done |
| [SPEW ] PCI: 00:1c.3 read_resources bus 4 link: 0 |
| [SPEW ] PCI: 00:1c.3 read_resources bus 4 link: 0 done |
| [SPEW ] PCI: 00:1e.0 read_resources bus 13 link: 0 |
| [SPEW ] PCI: 0d:01.0 read_resources bus 14 link: 0 |
| [SPEW ] PCI: 0d:01.0 read_resources bus 14 link: 0 done |
| [SPEW ] PCI: 00:1e.0 read_resources bus 13 link: 0 done |
| [SPEW ] PCI: 00:1f.0 read_resources bus 0 link: 0 |
| [SPEW ] PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| [SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 done |
| [SPEW ] Root Device read_resources bus 0 link: 0 done |
| [INFO ] Done reading resources. |
| [SPEW ] Show resources in subtree (Root Device)...After reading. |
| [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 |
| [DEBUG] CPU_CLUSTER: 0 |
| [DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| [SPEW ] DOMAIN: 0000 resource base 7d800000 size 0 align 0 gran 0 limit fdffffff flags 40040200 index 10000100 |
| [SPEW ] DOMAIN: 0000 resource base 100000000 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000200 |
| [SPEW ] DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| [SPEW ] DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 4 |
| [SPEW ] DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 5 |
| [SPEW ] DOMAIN: 0000 resource base 100000 size 7d800000 align 0 gran 0 limit 0 flags e0004200 index 6 |
| [SPEW ] DOMAIN: 0000 resource base 7da00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| [SPEW ] DOMAIN: 0000 resource base 7d800000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 8 |
| [SPEW ] DOMAIN: 0000 resource base 7dc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| [SPEW ] DOMAIN: 0000 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index a |
| [SPEW ] DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index b |
| [DEBUG] PCI: 00:00.0 |
| [DEBUG] PCI: 00:02.0 |
| [SPEW ] PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| [SPEW ] PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| [SPEW ] PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:02.1 |
| [SPEW ] PCI: 00:02.1 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:19.0 |
| [SPEW ] PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| [SPEW ] PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| [SPEW ] PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| [DEBUG] PCI: 00:1a.0 |
| [SPEW ] PCI: 00:1a.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1a.1 |
| [SPEW ] PCI: 00:1a.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1a.2 |
| [SPEW ] PCI: 00:1a.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1a.7 |
| [SPEW ] PCI: 00:1a.7 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1b.0 |
| [SPEW ] PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:1c.0 |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 02:00.0 |
| [SPEW ] PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:1c.2 |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 00:1c.3 child on link 0 NONE |
| [SPEW ] PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] NONE |
| [SPEW ] NONE resource base 0 size 800000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| [SPEW ] NONE resource base 0 size 10000000 align 12 gran 12 limit ffffffffffffffff flags 101200 index 14 |
| [SPEW ] NONE resource base 0 size 800 align 12 gran 12 limit ffff flags 100 index 18 |
| [DEBUG] PCI: 00:1d.0 |
| [SPEW ] PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.1 |
| [SPEW ] PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.2 |
| [SPEW ] PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:1d.7 |
| [SPEW ] PCI: 00:1d.7 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1e.0 child on link 0 PCI: 0d:01.0 |
| [SPEW ] PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 0d:01.0 |
| [SPEW ] PCI: 0d:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| [SPEW ] PCI: 0d:01.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c |
| [SPEW ] PCI: 0d:01.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 |
| [SPEW ] PCI: 0d:01.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c |
| [SPEW ] PCI: 0d:01.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 |
| [DEBUG] PCI: 0d:01.1 |
| [SPEW ] PCI: 0d:01.1 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 0d:01.2 |
| [SPEW ] PCI: 0d:01.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 0d:01.3 |
| [SPEW ] PCI: 0d:01.3 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1f.0 child on link 0 PNP: 00ff.0 |
| [SPEW ] PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| [SPEW ] PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| [SPEW ] PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| [DEBUG] PNP: 00ff.0 |
| [DEBUG] PCI: 00:1f.2 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| [DEBUG] PCI: 00:1f.3 |
| [SPEW ] PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| [SPEW ] PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (relative placement) === |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 02:00.0 10 * [0x0 - 0x1fff] mem |
| [DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] NONE 18 * [0x0 - 0x7ff] io |
| [DEBUG] PCI: 00:1c.3 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] NONE 10 * [0x0 - 0x7fffff] mem |
| [DEBUG] PCI: 00:1c.3 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem |
| [DEBUG] PCI: 00:1c.3 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 0d:01.0 2c * [0x0 - 0xfff] io |
| [DEBUG] PCI: 0d:01.0 34 * [0x1000 - 0x1fff] io |
| [DEBUG] PCI: 00:1e.0 io: size: 2000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1e.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 0d:01.0 24 * [0x0 - 0x1ffffff] mem |
| [DEBUG] PCI: 0d:01.0 10 * [0x2000000 - 0x2000fff] mem |
| [DEBUG] PCI: 0d:01.1 10 * [0x2001000 - 0x20017ff] mem |
| [DEBUG] PCI: 0d:01.2 10 * [0x2002000 - 0x20020ff] mem |
| [DEBUG] PCI: 0d:01.3 10 * [0x2003000 - 0x20030ff] mem |
| [DEBUG] PCI: 00:1e.0 mem: size: 2100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 0d:01.0 1c * [0x0 - 0x1ffffff] prefmem |
| [DEBUG] PCI: 00:1e.0 prefmem: size: 2000000 align: 20 gran: 20 limit: ffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] avoid_fixed_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 1000, Size: f000, Tag: 100 |
| [DEBUG] PCI: 00:1e.0 1c * [0xe000 - 0xffff] limit: ffff io |
| [DEBUG] PCI: 00:1c.3 1c * [0xd000 - 0xdfff] limit: dfff io |
| [DEBUG] PCI: 00:19.0 18 * [0xcfe0 - 0xcfff] limit: cfff io |
| [DEBUG] PCI: 00:1a.0 20 * [0xcfc0 - 0xcfdf] limit: cfdf io |
| [DEBUG] PCI: 00:1a.1 20 * [0xcfa0 - 0xcfbf] limit: cfbf io |
| [DEBUG] PCI: 00:1a.2 20 * [0xcf80 - 0xcf9f] limit: cf9f io |
| [DEBUG] PCI: 00:1d.0 20 * [0xcf60 - 0xcf7f] limit: cf7f io |
| [DEBUG] PCI: 00:1d.1 20 * [0xcf40 - 0xcf5f] limit: cf5f io |
| [DEBUG] PCI: 00:1d.2 20 * [0xcf20 - 0xcf3f] limit: cf3f io |
| [DEBUG] PCI: 00:1f.2 20 * [0xcf00 - 0xcf1f] limit: cf1f io |
| [DEBUG] PCI: 00:02.0 20 * [0xcef8 - 0xceff] limit: ceff io |
| [DEBUG] PCI: 00:1f.2 10 * [0xcef0 - 0xcef7] limit: cef7 io |
| [DEBUG] PCI: 00:1f.2 18 * [0xcee8 - 0xceef] limit: ceef io |
| [DEBUG] PCI: 00:1f.2 14 * [0xcee4 - 0xcee7] limit: cee7 io |
| [DEBUG] PCI: 00:1f.2 1c * [0xcee0 - 0xcee3] limit: cee3 io |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 7d800000 size: 0 align: 0 gran: 0 limit: fdffffff |
| [DEBUG] DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 04 base 000a0000 limit 000bffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 05 base 000c0000 limit 000fffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 06 base 00100000 limit 7d8fffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 07 base 7da00000 limit 7dbfffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 08 base 7d800000 limit 7d9fffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 09 base 7dc00000 limit 7fffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 0a base 100000000 limit 17fffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: DOMAIN: 0000 0b base f0000000 limit f3ffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed) |
| [DEBUG] avoid_fixed_resources: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 80000000, Size: 70000000, Tag: 200 |
| [INFO ] * Base: f4000000, Size: a000000, Tag: 200 |
| [INFO ] * Base: 180000000, Size: e80000000, Tag: 200 |
| [DEBUG] PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem |
| [DEBUG] PCI: 00:02.0 10 * [0xfdc00000 - 0xfdffffff] limit: fdffffff mem |
| [DEBUG] PCI: 00:1c.3 24 * [0xff0000000 - 0xfffffffff] limit: fffffffff prefmem |
| [DEBUG] PCI: 00:1e.0 20 * [0xfbb00000 - 0xfdbfffff] limit: fdbfffff mem |
| [DEBUG] PCI: 00:1e.0 24 * [0xf9b00000 - 0xfbafffff] limit: fbafffff prefmem |
| [DEBUG] PCI: 00:1c.3 20 * [0xf9300000 - 0xf9afffff] limit: f9afffff mem |
| [DEBUG] PCI: 00:02.1 10 * [0xf9200000 - 0xf92fffff] limit: f92fffff mem |
| [DEBUG] PCI: 00:1c.1 20 * [0xf9100000 - 0xf91fffff] limit: f91fffff mem |
| [DEBUG] PCI: 00:19.0 10 * [0xf90e0000 - 0xf90fffff] limit: f90fffff mem |
| [DEBUG] PCI: 00:1b.0 10 * [0xf90dc000 - 0xf90dffff] limit: f90dffff mem |
| [DEBUG] PCI: 00:19.0 14 * [0xf90db000 - 0xf90dbfff] limit: f90dbfff mem |
| [DEBUG] PCI: 00:1f.2 24 * [0xf90da000 - 0xf90da7ff] limit: f90da7ff mem |
| [DEBUG] PCI: 00:1a.7 10 * [0xf90d9000 - 0xf90d93ff] limit: f90d93ff mem |
| [DEBUG] PCI: 00:1d.7 10 * [0xf90d8000 - 0xf90d83ff] limit: f90d83ff mem |
| [DEBUG] PCI: 00:1f.3 10 * [0xf90d7000 - 0xf90d70ff] limit: f90d70ff mem |
| [DEBUG] DOMAIN: 0000 mem: base: 7d800000 size: 0 align: 0 gran: 0 limit: fdffffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done |
| [DEBUG] PCI: 02:00.0 10 * [0xf9100000 - 0xf9101fff] limit: f9101fff mem |
| [DEBUG] NONE 18 * [0xd000 - 0xd7ff] limit: d7ff io |
| [DEBUG] NONE 14 * [0xff0000000 - 0xfffffffff] limit: fffffffff prefmem |
| [DEBUG] NONE 10 * [0xf9300000 - 0xf9afffff] limit: f9afffff mem |
| [DEBUG] PCI: 0d:01.0 2c * [0xe000 - 0xefff] limit: efff io |
| [DEBUG] PCI: 0d:01.0 34 * [0xf000 - 0xffff] limit: ffff io |
| [DEBUG] PCI: 0d:01.0 1c * [0xf9b00000 - 0xfbafffff] limit: fbafffff prefmem |
| [DEBUG] PCI: 0d:01.0 10 * [0xfdb00000 - 0xfdb00fff] limit: fdb00fff mem |
| [DEBUG] PCI: 0d:01.0 24 * [0xfbb00000 - 0xfdafffff] limit: fdafffff mem |
| [DEBUG] PCI: 0d:01.1 10 * [0xfdb01000 - 0xfdb017ff] limit: fdb017ff mem |
| [DEBUG] PCI: 0d:01.2 10 * [0xfdb02000 - 0xfdb020ff] limit: fdb020ff mem |
| [DEBUG] PCI: 0d:01.3 10 * [0xfdb03000 - 0xfdb030ff] limit: fdb030ff mem |
| [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| [SPEW ] Root Device assign_resources, bus 0 link: 0 |
| [DEBUG] DOMAIN: 0000 03 <- [0x0000000000000000 - 0x000000000009ffff] size 0x000a0000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 04 <- [0x00000000000a0000 - 0x00000000000bffff] size 0x00020000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 05 <- [0x00000000000c0000 - 0x00000000000fffff] size 0x00040000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 06 <- [0x0000000000100000 - 0x000000007d8fffff] size 0x7d800000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 07 <- [0x000000007da00000 - 0x000000007dbfffff] size 0x00200000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 08 <- [0x000000007d800000 - 0x000000007d9fffff] size 0x00200000 gran 0x00 mem |
| [DEBUG] DOMAIN: 0000 09 <- [0x000000007dc00000 - 0x000000007fffffff] size 0x02400000 gran 0x00 mem |
| [SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| [DEBUG] PCI: 00:02.0 10 <- [0x00000000fdc00000 - 0x00000000fdffffff] size 0x00400000 gran 0x16 mem64 |
| [DEBUG] PCI: 00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64 |
| [DEBUG] PCI: 00:02.0 20 <- [0x000000000000cef8 - 0x000000000000ceff] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:02.1 10 <- [0x00000000f9200000 - 0x00000000f92fffff] size 0x00100000 gran 0x14 mem64 |
| [DEBUG] PCI: 00:19.0 10 <- [0x00000000f90e0000 - 0x00000000f90fffff] size 0x00020000 gran 0x11 mem |
| [DEBUG] PCI: 00:19.0 14 <- [0x00000000f90db000 - 0x00000000f90dbfff] size 0x00001000 gran 0x0c mem |
| [DEBUG] PCI: 00:19.0 18 <- [0x000000000000cfe0 - 0x000000000000cfff] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1a.0 20 <- [0x000000000000cfc0 - 0x000000000000cfdf] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1a.1 20 <- [0x000000000000cfa0 - 0x000000000000cfbf] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1a.2 20 <- [0x000000000000cf80 - 0x000000000000cf9f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1a.7 10 <- [0x00000000f90d9000 - 0x00000000f90d93ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1b.0 10 <- [0x00000000f90dc000 - 0x00000000f90dffff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| [DEBUG] PCI: 00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 01 mem |
| [DEBUG] PCI: 00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| [DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| [DEBUG] PCI: 00:1c.1 20 <- [0x00000000f9100000 - 0x00000000f91fffff] size 0x00100000 gran 0x14 bus 02 mem |
| [SPEW ] PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| [DEBUG] PCI: 02:00.0 10 <- [0x00000000f9100000 - 0x00000000f9101fff] size 0x00002000 gran 0x0d mem64 |
| [SPEW ] PCI: 00:1c.1 assign_resources, bus 2 link: 0 done |
| [DEBUG] PCI: 00:1c.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| [DEBUG] PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| [DEBUG] PCI: 00:1c.2 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 03 mem |
| [DEBUG] PCI: 00:1c.3 1c <- [0x000000000000d000 - 0x000000000000dfff] size 0x00001000 gran 0x0c bus 04 io |
| [DEBUG] PCI: 00:1c.3 24 <- [0x0000000ff0000000 - 0x0000000fffffffff] size 0x10000000 gran 0x14 bus 04 prefmem |
| [DEBUG] PCI: 00:1c.3 20 <- [0x00000000f9300000 - 0x00000000f9afffff] size 0x00800000 gran 0x14 bus 04 mem |
| [SPEW ] PCI: 00:1c.3 assign_resources, bus 4 link: 0 |
| [SPEW ] PCI: 00:1c.3 assign_resources, bus 4 link: 0 done |
| [DEBUG] PCI: 00:1d.0 20 <- [0x000000000000cf60 - 0x000000000000cf7f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.1 20 <- [0x000000000000cf40 - 0x000000000000cf5f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.2 20 <- [0x000000000000cf20 - 0x000000000000cf3f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1d.7 10 <- [0x00000000f90d8000 - 0x00000000f90d83ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1e.0 1c <- [0x000000000000e000 - 0x000000000000ffff] size 0x00002000 gran 0x0c bus 0d io |
| [DEBUG] PCI: 00:1e.0 24 <- [0x00000000f9b00000 - 0x00000000fbafffff] size 0x02000000 gran 0x14 bus 0d prefmem |
| [DEBUG] PCI: 00:1e.0 20 <- [0x00000000fbb00000 - 0x00000000fdbfffff] size 0x02100000 gran 0x14 bus 0d mem |
| [SPEW ] PCI: 00:1e.0 assign_resources, bus 13 link: 0 |
| [DEBUG] PCI: 0d:01.0 10 <- [0x00000000fdb00000 - 0x00000000fdb00fff] size 0x00001000 gran 0x0c mem |
| [DEBUG] PCI: 0d:01.0 2c <- [0x000000000000e000 - 0x000000000000efff] size 0x00001000 gran 0x02 io |
| [DEBUG] PCI: 0d:01.0 34 <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x02 io |
| [DEBUG] PCI: 0d:01.0 1c <- [0x00000000f9b00000 - 0x00000000fbafffff] size 0x02000000 gran 0x0c prefmem |
| [DEBUG] PCI: 0d:01.0 24 <- [0x00000000fbb00000 - 0x00000000fdafffff] size 0x02000000 gran 0x0c mem |
| [DEBUG] PCI: 0d:01.1 10 <- [0x00000000fdb01000 - 0x00000000fdb017ff] size 0x00000800 gran 0x0b mem |
| [DEBUG] PCI: 0d:01.2 10 <- [0x00000000fdb02000 - 0x00000000fdb020ff] size 0x00000100 gran 0x08 mem |
| [DEBUG] PCI: 0d:01.3 10 <- [0x00000000fdb03000 - 0x00000000fdb030ff] size 0x00000100 gran 0x08 mem |
| [SPEW ] PCI: 00:1e.0 assign_resources, bus 13 link: 0 done |
| [SPEW ] PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| [SPEW ] PCI: 00:1f.0 assign_resources, bus 0 link: 0 done |
| [DEBUG] PCI: 00:1f.2 10 <- [0x000000000000cef0 - 0x000000000000cef7] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 14 <- [0x000000000000cee4 - 0x000000000000cee7] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 18 <- [0x000000000000cee8 - 0x000000000000ceef] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 1c <- [0x000000000000cee0 - 0x000000000000cee3] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 20 <- [0x000000000000cf00 - 0x000000000000cf1f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1f.2 24 <- [0x00000000f90da000 - 0x00000000f90da7ff] size 0x00000800 gran 0x0b mem |
| [DEBUG] PCI: 00:1f.3 10 <- [0x00000000f90d7000 - 0x00000000f90d70ff] size 0x00000100 gran 0x08 mem64 |
| [SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 done |
| [SPEW ] Root Device assign_resources, bus 0 link: 0 done |
| [INFO ] Done setting resources. |
| [SPEW ] Show resources in subtree (Root Device)...After assigning values. |
| [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 |
| [DEBUG] CPU_CLUSTER: 0 |
| [DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| [SPEW ] DOMAIN: 0000 resource base 7d800000 size 0 align 0 gran 0 limit fdffffff flags 40040200 index 10000100 |
| [SPEW ] DOMAIN: 0000 resource base 100000000 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000200 |
| [SPEW ] DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| [SPEW ] DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 4 |
| [SPEW ] DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 5 |
| [SPEW ] DOMAIN: 0000 resource base 100000 size 7d800000 align 0 gran 0 limit 0 flags e0004200 index 6 |
| [SPEW ] DOMAIN: 0000 resource base 7da00000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| [SPEW ] DOMAIN: 0000 resource base 7d800000 size 200000 align 0 gran 0 limit 0 flags f0000200 index 8 |
| [SPEW ] DOMAIN: 0000 resource base 7dc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| [SPEW ] DOMAIN: 0000 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index a |
| [SPEW ] DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index b |
| [DEBUG] PCI: 00:00.0 |
| [DEBUG] PCI: 00:02.0 |
| [SPEW ] PCI: 00:02.0 resource base fdc00000 size 400000 align 22 gran 22 limit fdffffff flags 60000201 index 10 |
| [SPEW ] PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 |
| [SPEW ] PCI: 00:02.0 resource base cef8 size 8 align 3 gran 3 limit ceff flags 60000100 index 20 |
| [DEBUG] PCI: 00:02.1 |
| [SPEW ] PCI: 00:02.1 resource base f9200000 size 100000 align 20 gran 20 limit f92fffff flags 60000201 index 10 |
| [DEBUG] PCI: 00:19.0 |
| [SPEW ] PCI: 00:19.0 resource base f90e0000 size 20000 align 17 gran 17 limit f90fffff flags 60000200 index 10 |
| [SPEW ] PCI: 00:19.0 resource base f90db000 size 1000 align 12 gran 12 limit f90dbfff flags 60000200 index 14 |
| [SPEW ] PCI: 00:19.0 resource base cfe0 size 20 align 5 gran 5 limit cfff flags 60000100 index 18 |
| [DEBUG] PCI: 00:1a.0 |
| [SPEW ] PCI: 00:1a.0 resource base cfc0 size 20 align 5 gran 5 limit cfdf flags 60000100 index 20 |
| [DEBUG] PCI: 00:1a.1 |
| [SPEW ] PCI: 00:1a.1 resource base cfa0 size 20 align 5 gran 5 limit cfbf flags 60000100 index 20 |
| [DEBUG] PCI: 00:1a.2 |
| [SPEW ] PCI: 00:1a.2 resource base cf80 size 20 align 5 gran 5 limit cf9f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1a.7 |
| [SPEW ] PCI: 00:1a.7 resource base f90d9000 size 400 align 12 gran 10 limit f90d93ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1b.0 |
| [SPEW ] PCI: 00:1b.0 resource base f90dc000 size 4000 align 14 gran 14 limit f90dffff flags 60000201 index 10 |
| [DEBUG] PCI: 00:1c.0 |
| [SPEW ] PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| [DEBUG] PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| [SPEW ] PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.1 resource base f9100000 size 100000 align 20 gran 20 limit f91fffff flags 60080202 index 20 |
| [DEBUG] PCI: 02:00.0 |
| [SPEW ] PCI: 02:00.0 resource base f9100000 size 2000 align 13 gran 13 limit f9101fff flags 60000201 index 10 |
| [DEBUG] PCI: 00:1c.2 |
| [SPEW ] PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.2 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| [DEBUG] PCI: 00:1c.3 child on link 0 NONE |
| [SPEW ] PCI: 00:1c.3 resource base d000 size 1000 align 12 gran 12 limit dfff flags 60080102 index 1c |
| [SPEW ] PCI: 00:1c.3 resource base ff0000000 size 10000000 align 20 gran 20 limit fffffffff flags 60081202 index 24 |
| [SPEW ] PCI: 00:1c.3 resource base f9300000 size 800000 align 20 gran 20 limit f9afffff flags 60080202 index 20 |
| [DEBUG] NONE |
| [SPEW ] NONE resource base f9300000 size 800000 align 12 gran 12 limit f9afffff flags 40000200 index 10 |
| [SPEW ] NONE resource base ff0000000 size 10000000 align 12 gran 12 limit fffffffff flags 40101200 index 14 |
| [SPEW ] NONE resource base d000 size 800 align 12 gran 12 limit d7ff flags 40000100 index 18 |
| [DEBUG] PCI: 00:1d.0 |
| [SPEW ] PCI: 00:1d.0 resource base cf60 size 20 align 5 gran 5 limit cf7f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.1 |
| [SPEW ] PCI: 00:1d.1 resource base cf40 size 20 align 5 gran 5 limit cf5f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.2 |
| [SPEW ] PCI: 00:1d.2 resource base cf20 size 20 align 5 gran 5 limit cf3f flags 60000100 index 20 |
| [DEBUG] PCI: 00:1d.7 |
| [SPEW ] PCI: 00:1d.7 resource base f90d8000 size 400 align 12 gran 10 limit f90d83ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1e.0 child on link 0 PCI: 0d:01.0 |
| [SPEW ] PCI: 00:1e.0 resource base e000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c |
| [SPEW ] PCI: 00:1e.0 resource base f9b00000 size 2000000 align 20 gran 20 limit fbafffff flags 60081202 index 24 |
| [SPEW ] PCI: 00:1e.0 resource base fbb00000 size 2100000 align 20 gran 20 limit fdbfffff flags 60080202 index 20 |
| [DEBUG] PCI: 0d:01.0 |
| [SPEW ] PCI: 0d:01.0 resource base fdb00000 size 1000 align 12 gran 12 limit fdb00fff flags 60000200 index 10 |
| [SPEW ] PCI: 0d:01.0 resource base e000 size 1000 align 2 gran 2 limit efff flags 60000100 index 2c |
| [SPEW ] PCI: 0d:01.0 resource base f000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 |
| [SPEW ] PCI: 0d:01.0 resource base f9b00000 size 2000000 align 12 gran 12 limit fbafffff flags 60001200 index 1c |
| [SPEW ] PCI: 0d:01.0 resource base fbb00000 size 2000000 align 12 gran 12 limit fdafffff flags 60000200 index 24 |
| [DEBUG] PCI: 0d:01.1 |
| [SPEW ] PCI: 0d:01.1 resource base fdb01000 size 800 align 12 gran 11 limit fdb017ff flags 60000200 index 10 |
| [DEBUG] PCI: 0d:01.2 |
| [SPEW ] PCI: 0d:01.2 resource base fdb02000 size 100 align 12 gran 8 limit fdb020ff flags 60000200 index 10 |
| [DEBUG] PCI: 0d:01.3 |
| [SPEW ] PCI: 0d:01.3 resource base fdb03000 size 100 align 12 gran 8 limit fdb030ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1f.0 child on link 0 PNP: 00ff.0 |
| [SPEW ] PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| [SPEW ] PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| [SPEW ] PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| [DEBUG] PNP: 00ff.0 |
| [DEBUG] PCI: 00:1f.2 |
| [SPEW ] PCI: 00:1f.2 resource base cef0 size 8 align 3 gran 3 limit cef7 flags 60000100 index 10 |
| [SPEW ] PCI: 00:1f.2 resource base cee4 size 4 align 2 gran 2 limit cee7 flags 60000100 index 14 |
| [SPEW ] PCI: 00:1f.2 resource base cee8 size 8 align 3 gran 3 limit ceef flags 60000100 index 18 |
| [SPEW ] PCI: 00:1f.2 resource base cee0 size 4 align 2 gran 2 limit cee3 flags 60000100 index 1c |
| [SPEW ] PCI: 00:1f.2 resource base cf00 size 20 align 5 gran 5 limit cf1f flags 60000100 index 20 |
| [SPEW ] PCI: 00:1f.2 resource base f90da000 size 800 align 12 gran 11 limit f90da7ff flags 60000200 index 24 |
| [DEBUG] PCI: 00:1f.3 |
| [SPEW ] PCI: 00:1f.3 resource base f90d7000 size 100 align 12 gran 8 limit f90d70ff flags 60000201 index 10 |
| [SPEW ] PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 1 ms |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:02.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:02.0 cmd <- 03 |
| [DEBUG] PCI: 00:02.1 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:02.1 cmd <- 02 |
| [DEBUG] PCI: 00:19.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:19.0 cmd <- 103 |
| [DEBUG] PCI: 00:1a.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1a.0 cmd <- 01 |
| [DEBUG] PCI: 00:1a.1 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1a.1 cmd <- 01 |
| [DEBUG] PCI: 00:1a.2 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1a.2 cmd <- 01 |
| [DEBUG] PCI: 00:1a.7 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1a.7 cmd <- 102 |
| [DEBUG] PCI: 00:1b.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1b.0 cmd <- 102 |
| [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1c.0 cmd <- 100 |
| [DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.1 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1c.1 cmd <- 106 |
| [DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.2 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1c.2 cmd <- 100 |
| [DEBUG] PCI: 00:1c.3 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.3 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1c.3 cmd <- 107 |
| [DEBUG] PCI: 00:1d.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1d.0 cmd <- 01 |
| [DEBUG] PCI: 00:1d.1 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1d.1 cmd <- 01 |
| [DEBUG] PCI: 00:1d.2 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1d.2 cmd <- 01 |
| [DEBUG] PCI: 00:1d.7 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1d.7 cmd <- 102 |
| [DEBUG] PCI: 00:1e.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1e.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1e.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.0 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1f.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.2 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1f.2 cmd <- 03 |
| [DEBUG] PCI: 00:1f.3 subsystem <- 1028/0233 |
| [DEBUG] PCI: 00:1f.3 cmd <- 103 |
| [DEBUG] PCI: 02:00.0 cmd <- 02 |
| [DEBUG] PCI: 0d:01.0 bridge ctrl <- 0503 |
| [DEBUG] PCI: 0d:01.0 cmd <- 03 |
| [DEBUG] PCI: 0d:01.1 cmd <- 02 |
| [DEBUG] PCI: 0d:01.2 cmd <- 06 |
| [DEBUG] PCI: 0d:01.3 cmd <- 06 |
| [INFO ] done. |
| [INFO ] Initializing devices... |
| [DEBUG] CPU_CLUSTER: 0 init |
| [DEBUG] microcode: sig=0x1067a pf=0x80 revision=0x0 |
| [DEBUG] FMAP: area COREBOOT found @ 260200 (1703424 bytes) |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xe140 size 0x21000 in mcache @0x7d7dd0ac |
| [INFO ] microcode: load microcode patch |
| [INFO ] microcode: updated to revision 0xa0b date=2010-09-28 |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007d7fffff size 0x7d740000 type 6 |
| [DEBUG] 0x000000007d800000 - 0x00000000dfffffff size 0x62800000 type 0 |
| [DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1 |
| [DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0 |
| [DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6 |
| [DEBUG] 0x0000000ff0000000 - 0x0000000fffffffff size 0x10000000 type 0 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [SPEW ] apic_id 0x0 call enable_fixed_mtrr() |
| [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 7/5. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 1 base 0x000000007d800000 mask 0x0000000fff800000 type 0 |
| [DEBUG] MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 |
| [DEBUG] MTRR: 3 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1 |
| [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [DEBUG] CPU has 2 cores. |
| [DEBUG] Setting up SMI for CPU |
| [INFO ] Will perform SMM setup. |
| [INFO ] CPU: Intel(R) Core(TM)2 Duo CPU P8800 @ 2.66GHz. |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] CPU: APIC: 00 enabled |
| [DEBUG] CPU: APIC: 01 enabled |
| [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 |
| [DEBUG] Processing 16 relocs. Offset value of 0x00030000 |
| [SPEW ] CLFLUSH [0x30000, 0x30178] |
| [DEBUG] Attempting to start 1 APs |
| [DEBUG] Waiting for 10ms after sending INIT. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [SPEW ] APs are ready after 15us |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [SPEW ] APs are ready after 0us |
| [INFO ] LAPIC 0x1 in XAPIC mode. |
| [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000a0b |
| [SPEW ] APs are ready after 200us |
| [SPEW ] smm_setup_relocation_handler: enter |
| [SPEW ] smm_setup_relocation_handler: exit |
| [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x198 memsize: 0x198 |
| [DEBUG] Processing 9 relocs. Offset value of 0x00038000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x7da00800 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 |
| [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7d7a8e84 |
| [DEBUG] Installing permanent SMM handler to 0x7da00000 |
| [DEBUG] HANDLER [0x7daff000-0x7daff688] |
| |
| [DEBUG] CPU 0 |
| [DEBUG] ss0 [0x7dafec00-0x7daff000] |
| [DEBUG] stub0 [0x7daf7000-0x7daf7198] |
| |
| [DEBUG] CPU 1 |
| [DEBUG] ss1 [0x7dafe800-0x7dafec00] |
| [DEBUG] stub1 [0x7daf6c00-0x7daf6d98] |
| |
| [DEBUG] stacks [0x7da00000-0x7da00800] |
| [DEBUG] Loading module at 0x7daff000 with entry 0x7daff056. filesize: 0x678 memsize: 0x688 |
| [DEBUG] Processing 27 relocs. Offset value of 0x7daff000 |
| [DEBUG] Loading module at 0x7daf7000 with entry 0x7daf7000. filesize: 0x198 memsize: 0x198 |
| [DEBUG] Processing 9 relocs. Offset value of 0x7daf7000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x7da00800 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x100000 |
| [DEBUG] SMM Module: placing smm entry code at 7daf6c00, cpu # 0x1 |
| [SPEW ] smm_place_entry_code: copying from 7daf7000 to 7daf6c00 0x198 bytes |
| [DEBUG] SMM Module: stub loaded at 7daf7000. Will call 0x7daff056 |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7daef000, cpu = 0 |
| [DEBUG] In relocation handler: cpu 0 |
| [DEBUG] New SMBASE=0x7daef000 |
| [SPEW ] SMM revision: 0x00030100 |
| [WARN ] SMRR not enabled, skip writing SMRR... |
| [DEBUG] Relocation complete. |
| [DEBUG] VMX status: enabled |
| [DEBUG] VMX status: enabled |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7daeec00, cpu = 1 |
| [DEBUG] In relocation handler: cpu 1 |
| [DEBUG] New SMBASE=0x7daeec00 |
| [SPEW ] SMM revision: 0x00030100 |
| [DEBUG] Writing SMRR. base = 0x7da00000, mask=0xffe00800 |
| [DEBUG] Relocation complete. |
| [SPEW ] APs are ready after 700us |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 1067a |
| [DEBUG] CPU: family 06, model 17, stepping 0a |
| [INFO ] CPU: Intel(R) Core(TM)2 Duo CPU P8800 @ 2.66GHz. |
| [DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 1: 0, 0, 8, 0x1b, 25000; encoded: 0x081b |
| [DEBUG] writing P-State 0: 0, 0, 10, 0x20, 35000; encoded: 0x0a20 |
| [INFO ] CPU #0 initialized |
| [INFO ] Initializing CPU #1 |
| [DEBUG] CPU: vendor Intel device 1067a |
| [DEBUG] CPU: family 06, model 17, stepping 0a |
| [INFO ] CPU: Intel(R) Core(TM)2 Duo CPU P8800 @ 2.66GHz. |
| [DEBUG] writing P-State 3: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 3: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 3: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 3: 0, 0, 6, 0x17, 15000; encoded: 0x0617 |
| [DEBUG] writing P-State 2: 0, 0, 8, 0x1b, 25000; encoded: 0x081b |
| [DEBUG] writing P-State 1: 0, 0, 10, 0x20, 35000; encoded: 0x0a20 |
| [INFO ] CPU #1 initialized |
| [SPEW ] APs are ready after 100us |
| [DEBUG] CPU 1 going down... |
| [INFO ] bsp_do_flight_plan done after 11 msecs. |
| [DEBUG] SMI_STS: |
| [SPEW ] PM1_STS: |
| [SPEW ] PM1_EN: 100 |
| [DEBUG] GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO7 GPIO6 GPIO0 |
| [DEBUG] ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI8 GPI7 GPI6 GPI1 GPI0 |
| [DEBUG] TCO_STS: |
| [DEBUG] Locking SMM. |
| [DEBUG] CPU_CLUSTER: 0 init finished in 31 msecs |
| [DEBUG] DOMAIN: 0000 init |
| [DEBUG] DOMAIN: 0000 init finished in 0 msecs |
| [DEBUG] PCI: 00:00.0 init |
| [DEBUG] PCI: 00:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:02.0 init |
| [INFO ] CBFS: Found 'vbt.bin' @0x53400 size 0x537 in mcache @0x7d7dd204 |
| [INFO ] Found a VBT of 7168 bytes after decompression |
| [INFO ] GMA: Found VBT in CBFS |
| [INFO ] GMA: Found valid VBT in CBFS |
| [DEBUG] LVDS EDID |
| [SPEW ] EDID: |
| [SPEW ] 00 ff ff ff ff ff ff 00 30 e4 bc 0a 00 00 00 00 |
| [SPEW ] 00 12 01 03 80 1e 13 78 0a 1f 35 93 59 55 8a 28 |
| [SPEW ] 22 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 |
| [SPEW ] 01 01 01 01 01 01 1c 1b 00 7e 50 20 16 30 30 20 |
| [SPEW ] 36 00 30 be 10 00 00 1b 1c 1b 00 7e 50 20 16 30 |
| [SPEW ] 30 20 36 00 30 be 10 00 00 1b 00 00 00 fe 00 47 |
| [SPEW ] 30 32 32 48 80 31 34 31 57 58 35 0a 00 00 00 00 |
| [SPEW ] 00 3c 58 74 90 ac c8 e4 ff 01 01 0a 20 20 00 52 |
| [SPEW ] Extracted contents: |
| [SPEW ] header: 00 ff ff ff ff ff ff 00 |
| [SPEW ] serial number: 30 e4 bc 0a 00 00 00 00 00 12 |
| [SPEW ] version: 01 03 |
| [SPEW ] basic params: 80 1e 13 78 0a |
| [SPEW ] chroma info: 1f 35 93 59 55 8a 28 22 50 54 |
| [SPEW ] established: 00 00 00 |
| [SPEW ] standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 |
| [SPEW ] descriptor 1: 1c 1b 00 7e 50 20 16 30 30 20 36 00 30 be 10 00 00 1b |
| [SPEW ] descriptor 2: 1c 1b 00 7e 50 20 16 30 30 20 36 00 30 be 10 00 00 1b |
| [SPEW ] descriptor 3: 00 00 00 fe 00 47 30 32 32 48 80 31 34 31 57 58 35 0a |
| [SPEW ] descriptor 4: 00 00 00 00 00 3c 58 74 90 ac c8 e4 ff 01 01 0a 20 20 |
| [SPEW ] extensions: 00 |
| [SPEW ] checksum: 52 |
| |
| [SPEW ] Manufacturer: LGD Model abc Serial Number 0 |
| [SPEW ] Made week 0 of 2008 |
| [SPEW ] EDID version: 1.3 |
| [SPEW ] Digital display |
| [SPEW ] Maximum image size: 30 cm x 19 cm |
| [SPEW ] Gamma: 220% |
| [SPEW ] Check DPMS levels |
| [SPEW ] Supported color formats: RGB 4:4:4, YCrCb 4:2:2 |
| [SPEW ] First detailed timing is preferred timing |
| [SPEW ] Established timings supported: |
| [SPEW ] Standard timings supported: |
| [SPEW ] Detailed timings |
| [SPEW ] Hex of detail: 1c1b007e502016303020360030be1000001b |
| [SPEW ] Detailed mode (IN HEX): Clock 69400 KHz, 130 mm x be mm |
| [SPEW ] 0500 0530 0550 057e hborder 0 |
| [SPEW ] 0320 0323 0329 0336 vborder 0 |
| [SPEW ] +hsync -vsync |
| [SPEW ] Did detailed timing |
| [SPEW ] Hex of detail: 1c1b007e502016303020360030be1000001b |
| [SPEW ] Detailed mode (IN HEX): Clock 69400 KHz, 130 mm x be mm |
| [SPEW ] 0500 0530 0550 057e hborder 0 |
| [SPEW ] 0320 0323 0329 0336 vborder 0 |
| [SPEW ] +hsync -vsync |
| [SPEW ] Hex of detail: 000000fe004730323248803134315758350a |
| [SPEW ] ASCII string: G022H?141WX5 |
| [SPEW ] Hex of detail: 00000000003c587490acc8e4ff01010a2020 |
| [SPEW ] Manufacturer-specified data, tag 0 |
| [SPEW ] Checksum |
| [SPEW ] Checksum: 0x52 (valid) |
| [WARN ] EDID block does NOT fully conform to EDID 1.3. |
| [ERROR] Missing name descriptor |
| [ERROR] Missing monitor ranges |
| [DEBUG] Found EDID string: G022H?141WX5 in lookup table, pwm: 12315Hz |
| [INFO ] framebuffer_info: bytes_per_line: 5120, bits_per_pixel: 32 |
| [INFO ] x_res x y_res: 1280 x 800, size: 4096000 at 0xe0000000 |
| [DEBUG] PCI: 00:02.0 init finished in 84 msecs |
| [DEBUG] PCI: 00:02.1 init |
| [DEBUG] PCI: 00:02.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:19.0 init |
| [DEBUG] PCI: 00:19.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1a.0 init |
| [DEBUG] PCI: 00:1a.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1a.1 init |
| [DEBUG] PCI: 00:1a.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1a.2 init |
| [DEBUG] PCI: 00:1a.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1a.7 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1a.7 init finished in 0 msecs |
| [DEBUG] PCI: 00:1b.0 init |
| [DEBUG] Azalia: base = 0xf90dc000 |
| [DEBUG] Azalia: codec_mask = 05 |
| [DEBUG] azalia_audio: Initializing codec #2 |
| [DEBUG] azalia_audio: codec viddid: 80862802 |
| [DEBUG] azalia_audio: No verb! |
| [DEBUG] azalia_audio: Initializing codec #0 |
| [DEBUG] azalia_audio: codec viddid: 111d76b2 |
| [DEBUG] azalia_audio: verb_size: 52 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] PCI: 00:1b.0 init finished in 4 msecs |
| [DEBUG] PCI: 00:1c.0 init |
| [DEBUG] Initializing ICH9 PCIe root port. |
| [DEBUG] PCI: 00:1c.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 init |
| [DEBUG] Initializing ICH9 PCIe root port. |
| [DEBUG] PCI: 00:1c.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 init |
| [DEBUG] Initializing ICH9 PCIe root port. |
| [DEBUG] PCI: 00:1c.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.3 init |
| [DEBUG] Initializing ICH9 PCIe root port. |
| [DEBUG] PCI: 00:1c.3 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.0 init |
| [DEBUG] PCI: 00:1d.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.1 init |
| [DEBUG] PCI: 00:1d.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.2 init |
| [DEBUG] PCI: 00:1d.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.7 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.7 init finished in 0 msecs |
| [DEBUG] PCI: 00:1e.0 init |
| [DEBUG] PCI: 00:1e.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 init |
| [DEBUG] i82801ix: lpc_init |
| [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 |
| [DEBUG] IOAPIC: ID = 0x00 |
| [SPEW ] IOAPIC: Dumping registers |
| [SPEW ] reg 0x0000: 0x00000000 |
| [SPEW ] reg 0x0001: 0x00170020 |
| [SPEW ] reg 0x0002: 0x00170020 |
| [DEBUG] IOAPIC: 24 interrupts |
| [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 |
| [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000 |
| [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00000700 |
| [INFO ] Set power on after power failure. |
| [INFO ] NMI sources disabled. |
| [DEBUG] rtc_failed = 0x0 |
| [DEBUG] RTC Init |
| [DEBUG] apm_control: Disabling ACPI. |
| [DEBUG] APMC done. |
| [DEBUG] PCI: 00:1f.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.2 init |
| [DEBUG] i82801ix_sata: initializing... |
| [DEBUG] SATA controller in AHCI mode. |
| [DEBUG] ABAR: 0xf90da000 |
| [DEBUG] PCI: 00:1f.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.3 init |
| [DEBUG] PCI: 00:1f.3 init finished in 0 msecs |
| [DEBUG] PCI: 02:00.0 init |
| [DEBUG] PCI: 02:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 0d:01.1 init |
| [DEBUG] PCI: 0d:01.1 init finished in 0 msecs |
| [DEBUG] PCI: 0d:01.2 init |
| [DEBUG] PCI: 0d:01.2 init finished in 0 msecs |
| [DEBUG] PCI: 0d:01.3 init |
| [DEBUG] PCI: 0d:01.3 init finished in 0 msecs |
| [DEBUG] PNP: 00ff.0 init |
| [DEBUG] PNP: 00ff.0 init finished in 0 msecs |
| [INFO ] Devices initialized |
| [SPEW ] Show all devs... After init. |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 0 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:02.1: enabled 1 |
| [SPEW ] PCI: 00:03.0: enabled 0 |
| [SPEW ] PCI: 00:03.1: enabled 0 |
| [SPEW ] PCI: 00:03.2: enabled 0 |
| [SPEW ] PCI: 00:03.3: enabled 0 |
| [SPEW ] PCI: 00:19.0: enabled 1 |
| [SPEW ] PCI: 00:1a.0: enabled 1 |
| [SPEW ] PCI: 00:1a.1: enabled 1 |
| [SPEW ] PCI: 00:1a.2: enabled 1 |
| [SPEW ] PCI: 00:1a.7: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 1 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1d.1: enabled 1 |
| [SPEW ] PCI: 00:1d.2: enabled 1 |
| [SPEW ] PCI: 00:1d.7: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 1 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.5: enabled 0 |
| [SPEW ] PCI: 00:1f.6: enabled 0 |
| [SPEW ] PNP: 00ff.0: enabled 1 |
| [SPEW ] PCI: 02:00.0: enabled 1 |
| [SPEW ] NONE: enabled 1 |
| [SPEW ] PCI: 0d:01.0: enabled 1 |
| [SPEW ] PCI: 0d:01.1: enabled 1 |
| [SPEW ] PCI: 0d:01.2: enabled 1 |
| [SPEW ] PCI: 0d:01.3: enabled 1 |
| [SPEW ] APIC: 00: enabled 1 |
| [SPEW ] APIC: 01: enabled 1 |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 120 / 1 ms |
| [INFO ] Finalize devices... |
| [INFO ] Devices finalized |
| [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x51000 size 0x2399 in mcache @0x7d7dd1d8 |
| [WARN ] CBFS: 'fallback/slic' not found. |
| [INFO ] ACPI: Writing ACPI tables at 7d74d000. |
| [DEBUG] ACPI: * FACS |
| [DEBUG] ACPI: * FACP |
| [DEBUG] ACPI: added table 1/32, length now 44 |
| [DEBUG] Found 1 CPU(s) with 2 core(s) each. |
| [DEBUG] clocks between 800 and 2800 MHz. |
| [DEBUG] adding 5 P-States between busratio 6 and a, incl. P0 |
| [DEBUG] PSS: 2667MHz power 35000 control 0x4a2a status 0x4a2a |
| [DEBUG] PSS: 2666MHz power 35000 control 0xa20 status 0xa20 |
| [DEBUG] PSS: 2133MHz power 25000 control 0x81b status 0x81b |
| [DEBUG] PSS: 1600MHz power 15000 control 0x617 status 0x617 |
| [DEBUG] PSS: 800MHz power 12000 control 0x860d status 0x860d |
| [DEBUG] clocks between 800 and 2800 MHz. |
| [DEBUG] adding 5 P-States between busratio 6 and a, incl. P0 |
| [DEBUG] PSS: 2667MHz power 35000 control 0x4a2a status 0x4a2a |
| [DEBUG] PSS: 2666MHz power 35000 control 0xa20 status 0xa20 |
| [DEBUG] PSS: 2133MHz power 25000 control 0x81b status 0x81b |
| [DEBUG] PSS: 1600MHz power 15000 control 0x617 status 0x617 |
| [DEBUG] PSS: 800MHz power 12000 control 0x860d status 0x860d |
| [DEBUG] PCI space above 4GB MMIO is at 0x180000000, len = 0xe80000000 |
| [WARN ] CBFS: 'pci8086,2a43.rom' not found. |
| [DEBUG] PCI Option ROM loading disabled for PCI: 00:02.1 |
| [WARN ] PCI: 00:02.1: Missing PCI Option ROM |
| [DEBUG] Generating ACPI PIRQ entries |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:19.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1a.1: pin=1 pirq=1 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1a.2: pin=2 pirq=2 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=0 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.1: pin=1 pirq=1 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1d.2: pin=2 pirq=2 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=1 |
| [SPEW ] ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2 |
| [DEBUG] ACPI: * SSDT |
| [DEBUG] ACPI: added table 2/32, length now 52 |
| [DEBUG] ACPI: * MCFG |
| [DEBUG] ACPI: added table 3/32, length now 60 |
| [DEBUG] IOAPIC: 24 interrupts |
| [DEBUG] ACPI: * APIC |
| [DEBUG] ACPI: added table 4/32, length now 68 |
| [DEBUG] current = 7d750150 |
| [DEBUG] ACPI: * DMAR |
| [DEBUG] ACPI: added table 5/32, length now 76 |
| [DEBUG] current = 7d7501d0 |
| [DEBUG] ACPI: * HPET |
| [DEBUG] ACPI: added table 6/32, length now 84 |
| [INFO ] ACPI: done. |
| [DEBUG] ACPI tables: 12816 bytes. |
| [DEBUG] smbios_write_tables: 7d745000 |
| [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.20-1205-g52fb64be42f3' |
| [DEBUG] SMBIOS tables: 666 bytes. |
| [DEBUG] Writing table forward entry at 0x00000500 |
| [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7267 |
| [DEBUG] Writing coreboot table at 0x7d771000 |
| [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| [DEBUG] 1. 0000000000001000-000000000009ffff: RAM |
| [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED |
| [DEBUG] 3. 0000000000100000-000000007d744fff: RAM |
| [DEBUG] 4. 000000007d745000-000000007d78cfff: CONFIGURATION TABLES |
| [DEBUG] 5. 000000007d78d000-000000007d7cefff: RAMSTAGE |
| [DEBUG] 6. 000000007d7cf000-000000007d7fffff: CONFIGURATION TABLES |
| [DEBUG] 7. 000000007d800000-000000007fffffff: RESERVED |
| [DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| [DEBUG] 9. 0000000100000000-000000017fffffff: RAM |
| [INFO ] Manufacturer: ef |
| [INFO ] SF: Detected ef 3016 with sector size 0x1000, total 0x400000 |
| [DEBUG] Wrote coreboot table at: 0x7d771000, 0x380 bytes, checksum 46d0 |
| [DEBUG] coreboot table: 920 bytes. |
| [DEBUG] IMD ROOT 0. 0x7d7ff000 0x00001000 |
| [DEBUG] IMD SMALL 1. 0x7d7fe000 0x00001000 |
| [DEBUG] CONSOLE 2. 0x7d7de000 0x00020000 |
| [DEBUG] RO MCACHE 3. 0x7d7dd000 0x00000364 |
| [DEBUG] TIME STAMP 4. 0x7d7dc000 0x00000910 |
| [DEBUG] AFTER CAR 5. 0x7d7cf000 0x0000d000 |
| [DEBUG] RAMSTAGE 6. 0x7d78c000 0x00043000 |
| [DEBUG] SMM BACKUP 7. 0x7d77c000 0x00010000 |
| [DEBUG] IGD OPREGION 8. 0x7d779000 0x00002f29 |
| [DEBUG] COREBOOT 9. 0x7d771000 0x00008000 |
| [DEBUG] ACPI 10. 0x7d74d000 0x00024000 |
| [DEBUG] SMBIOS 11. 0x7d745000 0x00008000 |
| [DEBUG] IMD small region: |
| [DEBUG] IMD ROOT 0. 0x7d7fec00 0x00000400 |
| [DEBUG] FMAP 1. 0x7d7feb40 0x000000b6 |
| [DEBUG] ROMSTAGE 2. 0x7d7feb20 0x00000004 |
| [DEBUG] ROMSTG STCK 3. 0x7d7fea80 0x00000088 |
| [DEBUG] ACPI GNVS 4. 0x7d7fe980 0x00000100 |
| [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 0 ms |
| [INFO ] CBFS: Found 'fallback/payload' @0x598c0 size 0x118bb in mcache @0x7d7dd2a0 |
| [DEBUG] Checking segment from ROM address 0xffeb9aec |
| [DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable. |
| [DEBUG] Checking segment from ROM address 0xffeb9b08 |
| [DEBUG] Loading segment from ROM address 0xffeb9aec |
| [DEBUG] code (compression=1) |
| [DEBUG] New segment dstaddr 0x000deda0 memsize 0x21260 srcaddr 0xffeb9b24 filesize 0x11883 |
| [DEBUG] Loading Segment: addr: 0x000deda0 memsz: 0x0000000000021260 filesz: 0x0000000000011883 |
| [DEBUG] using LZMA |
| [SPEW ] [ 0x000deda0, 00100000, 0x00100000) <- ffeb9b24 |
| [DEBUG] Loading segment from ROM address 0xffeb9b08 |
| [DEBUG] Entry Point 0x000fd262 |
| [SPEW ] Loaded segments |
| [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 31 / 0 ms |
| [DEBUG] ICH-NM10-PCH: watchdog disabled |
| [DEBUG] Jumping to boot code at 0x000fd262(0x7d771000) |
| [SPEW ] CPU0: stack: 0x7d7bf580 - 0x7d7c1580, lowest used address 0x7d7c0edc, stack used: 1700 bytes |
| SeaBIOS (version rel-1.16.2-0-gea1b7a0) |
| BUILD: gcc: (coreboot toolchain v2023-07-17_e4d660b2dc) 11.4.0 binutils: (GNU Binutils) 2.40 |
| Found coreboot cbmem console @ 7d7de000 |
| Found mainboard Dell Inc. Latitude E6400 |
| Relocating init from 0x000e0500 to 0x7c737a80 (size 54496) |
| Found CBFS header at 0xffe6022c |
| multiboot: eax=7d7bedbc, ebx=7d7bed84 |
| Found 26 PCI devices (max PCI bus is 0e) |
| Copying SMBIOS from 0x7d745000 to 0x000f67c0 |
| Copying SMBIOS 3.0 from 0x7d745020 to 0x000f67a0 |
| Copying ACPI RSDP from 0x7d74d000 to 0x000f6770 |
| table(50434146)=0x7d74f630 (via xsdt) |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.16.2-0-gea1b7a0) |
| EHCI init on dev 00:1a.7 (regs=0xf90d9020) |
| EHCI init on dev 00:1d.7 (regs=0xf90d8020) |
| UHCI init on dev 00:1a.0 (io=cfc0) |
| UHCI init on dev 00:1a.1 (io=cfa0) |
| UHCI init on dev 00:1a.2 (io=cf80) |
| UHCI init on dev 00:1d.0 (io=cf60) |
| UHCI init on dev 00:1d.1 (io=cf40) |
| UHCI init on dev 00:1d.2 (io=cf20) |
| AHCI controller at 00:1f.2, iobase 0xf90da000, irq 3 |
| Searching bootorder for: /pci@i0cf8/pci-bridge@1e/*@1,2 |
| Searching bootorder for: HALT |
| Found 0 lpt ports |
| Found 0 serial ports |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-6 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: registering: "AHCI/0: WDC WDBNCE5000PNC ATA-11 Hard-Disk (465 GiBytes)" |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@1/disk@0 |
| AHCI/1: registering: "DVD/CD [AHCI/1: TSSTcorp DVD+/-RW TS-U633A ATAPI-0 DVD/CD]" |
| USB keyboard initialized |
| USB mouse initialized |
| Initialized USB HUB (2 ports used) |
| PS2 keyboard initialized |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f6700: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168 |
| Space available for UMB: c7000-ec000, f5fe0-f6680 |
| Returned 16760832 bytes of ZoneHigh |
| e820 map has 7 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007d741000 = 1 RAM |
| 4: 000000007d741000 - 0000000080000000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 6: 0000000100000000 - 0000000180000000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from DVD/CD... |
| Device reports MEDIUM NOT PRESENT - 2 tries left |
| Device reports MEDIUM NOT PRESENT - 1 tries left |
| Device reports MEDIUM NOT PRESENT - 0 tries left |
| Boot failed: Could not read from CDROM (code 0003) |
| enter handle_18: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |