|
|
|
|
| coreboot-4.0-6522-ge0ceac3 Die Jul 29 01:35:36 CEST 2014 starting...
|
| Setting up static southbridge registers... done.
|
| Disabling Watchdog reboot... done.
|
| Setting up static northbridge registers... done.
|
| Initializing Graphics...
|
| Back from sandybridge_early_initialization()
|
| SMBus controller enabled.
|
| CPU id(306a9): Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz
|
| AES supported, TXT supported, VT supported
|
| PCH type: QM77, device id: 1e55, rev id 4
|
| Intel ME early init
|
| Intel ME firmware is ready
|
| ME: Requested 32MB UMA
|
| Starting native Platform init
|
| Row addr bits : 16
|
| Column addr bits : 10
|
| Number of ranks : 2
|
| DIMM Capacity : 8192 MB
|
| CAS latencies : 6 7 8 9 10 11
|
| tCKmin : 1.250 ns
|
| tAAmin : 13.125 ns
|
| tWRmin : 15.000 ns
|
| tRCDmin : 13.125 ns
|
| tRRDmin : 6.000 ns
|
| tRPmin : 13.125 ns
|
| tRASmin : 35.000 ns
|
| tRCmin : 48.125 ns
|
| tRFCmin : 260.000 ns
|
| tWTRmin : 7.500 ns
|
| tRTPmin : 7.500 ns
|
| tFAWmin : 30.000 ns
|
| rankmap[0] = 0x3
|
| Row addr bits : 16
|
| Column addr bits : 10
|
| Number of ranks : 2
|
| DIMM Capacity : 8192 MB
|
| CAS latencies : 6 7 8 9 10 11
|
| tCKmin : 1.250 ns
|
| tAAmin : 13.125 ns
|
| tWRmin : 15.000 ns
|
| tRCDmin : 13.125 ns
|
| tRRDmin : 6.000 ns
|
| tRPmin : 13.125 ns
|
| tRASmin : 35.000 ns
|
| tRCmin : 48.125 ns
|
| tRFCmin : 260.000 ns
|
| tWTRmin : 7.500 ns
|
| tRTPmin : 7.500 ns
|
| tFAWmin : 30.000 ns
|
| rankmap[1] = 0x3
|
| PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy...done
|
| MCU frequency is set at : 800 MHz
|
| Selected DRAM frequency: 800 MHz
|
| Minimum CAS latency : 11T
|
| Selected CAS latency : 11T
|
| Selected CWL latency : 8T
|
| Selected tRCD : 11T
|
| Selected tRP : 11T
|
| Selected tRAS : 28T
|
| Selected tWR : 12T
|
| Selected tFAW : 24T
|
| Selected tRRD : 5T
|
| Selected tRTP : 6T
|
| Selected tWTR : 6T
|
| Selected tRFC : 208T
|
| [c14] = 3000000
|
| [320c] = 4024000
|
| [d14] = 3000000
|
| [330c] = 4024000
|
| [4000] = 1c8bbb
|
| [4004] = cc186465
|
| [400c] = a08b4
|
| [4298] = 6cd01860
|
| [42a4] = 41f88200
|
| [4400] = 1c8bbb
|
| [4404] = cc186465
|
| [440c] = a08b4
|
| [4698] = 6cd01860
|
| [46a4] = 41f88200
|
| Done dimm mapping
|
| PCI:[a0] = 0
|
| PCI:[a4] = 4
|
| PCI:[bc] = c2a00000
|
| PCI:[a8] = 3b600000
|
| PCI:[ac] = 4
|
| PCI:[b8] |
| |
| *** Log truncated, 3883 characters dropped. *** |
| |
| Adding CBMEM entry as no. 4
|
| Adding CBMEM entry as no. 5
|
| Relocate MRC DATA from feffa77c to bfee0800 (1040 bytes)
|
| Adding CBMEM entry as no. 6
|
| Trying CBFS ramstage loader.
|
| CBFS: loading stage fallback/ramstage @ 0x100000 (487484 bytes), entry @ 0x100000
|
| coreboot-4.0-6522-ge0ceac3 Die Jul 29 01:35:36 CEST 2014 booting...
|
| BS: Entering BS_PRE_DEVICE state.
|
| BS: Exiting BS_PRE_DEVICE state.
|
| BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0
|
| BS: Entering BS_DEV_INIT_CHIPS state.
|
| BS: Exiting BS_DEV_INIT_CHIPS state.
|
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
|
| BS: Entering BS_DEV_ENUMERATE state.
|
| Enumerating buses...
|
| Show all devs...Before device enumeration.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 0
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 00:54: enabled 1
|
| I2C: 00:55: enabled 1
|
| I2C: 00:56: enabled 1
|
| I2C: 00:57: enabled 1
|
| I2C: 00:5c: enabled 1
|
| I2C: 00:5d: enabled 1
|
| I2C: 00:5e: enabled 1
|
| I2C: 00:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 1
|
| Compare with tree...
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 0
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 00:54: enabled 1
|
| I2C: 00:55: enabled 1
|
| I2C: 00:56: enabled 1
|
| I2C: 00:57: enabled 1
|
| I2C: 00:5c: enabled 1
|
| I2C: 00:5d: enabled 1
|
| I2C: 00:5e: enabled 1
|
| I2C: 00:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 1
|
| scan_static_bus for Root Device
|
| CPU_CLUSTER: 0 enabled
|
| DOMAIN: 0000 enabled
|
| DOMAIN: 0000 scanning...
|
| PCI: pci_scan_bus for bus 00
|
| PCI: 00:00.0 [8086/0154] ops
|
| Normal boot.
|
| PCI: 00:00.0 [8086/0154] enabled
|
| PCI: 00:02.0 [8086/0000] ops
|
| PCI: 00:02.0 [8086/0166] enabled
|
| PCI: 00:14.0 [8086/0000] ops
|
| PCI: 00:14.0 [8086/1e31] enabled
|
| PCI: 00:16.0 [8086/1e3a] bus ops
|
| PCI: 00:16.0 [8086/1e3a] enabled
|
| PCI: 00:16.1: Disabling device
|
| PCI: 00:16.1 [8086/1e3b] disabled No operations
|
| PCI: 00:16.2: Disabling device
|
| PCI: 00:16.2 [8086/1e3c] disabled No operations
|
| PCI: 00:16.3: Disabling device
|
| PCI: 00:16.3 [8086/1e3d] disabled No operations
|
| PCI: 00:19.0 [8086/1502] enabled
|
| PCI: 00:1a.0 [8086/0000] ops
|
| PCI: 00:1a.0 [8086/1e2d] enabled
|
| PCI: 00:1b.0 [8086/0000] ops
|
| PCI: 00:1b.0 [8086/1e20] enabled
|
| PCH: PCIe Root Port coalescing is enabled
|
| PCI: 00:1c.0 [8086/0000] bus ops
|
| PCI: 00:1c.0 [8086/1e10] enabled
|
| PCI: 00:1c.1 [8086/0000] bus ops
|
| PCI: 00:1c.1 [8086/1e12] enabled
|
| PCI: 00:1c.2 [8086/0000] bus ops
|
| PCI: 00:1c.2 [8086/1e14] enabled
|
| PCI: 00:1c.3: Disabling device
|
| PCI: 00:1c.4: Disabling device
|
| PCI: 00:1c.4: check set enabled
|
| PCI: 00:1c.5: Disabling device
|
| PCI: 00:1c.6: Disabling device
|
| PCI: 00:1c.7: Disabling device
|
| PCH: RPFN 0x76543210 -> 0xfedcb210
|
| PCI: 00:1d.0 [8086/0000] ops
|
| PCI: 00:1d.0 [8086/1e26] enabled
|
| PCI: 00:1e.0: Disabling device
|
| PCI: 00:1f.0 [8086/0000] bus ops
|
| PCI: 00:1f.0 [8086/1e55] enabled
|
| PCI: 00:1f.2 [8086/0000] ops
|
| PCI: 00:1f.2 [8086/1e01] enabled
|
| PCI: 00:1f.3 [8086/0000] bus ops
|
| PCI: 00:1f.3 [8086/1e22] enabled
|
| PCI: 00:1f.5: Disabling device
|
| PCI: Static device PCI: 00:1f.6 not found, disabling it.
|
| scan_static_bus for PCI: 00:16.0
|
| scan_static_bus for PCI: 00:16.0 done
|
| do_pci_scan_bridge for PCI: 00:1c.0
|
| PCI: pci_scan_bus for bus 01
|
| PCI: 01:00.0 [1180/e823] enabled
|
| PCI: 01:00.1 [1180/e232] enabled
|
| PCI: 01:00.2 [1180/e852] enabled
|
| PCI: pci_scan_bus returning with max=001
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| do_pci_scan_bridge returns max 1
|
| do_pci_scan_bridge for PCI: 00:1c.1
|
| PCI: pci_scan_bus for bus 02
|
| PCI: 02:00.0 [8086/0085] enabled
|
| PCI: pci_scan_bus returning with max=002
|
| Capability: type 0x01 @ 0xc8
|
| Capability: type 0x05 @ 0xd0
|
| Capability: type 0x10 @ 0xe0
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L1
|
| do_pci_scan_bridge returns max 2
|
| do_pci_scan_bridge for PCI: 00:1c.2
|
| PCI: pci_scan_bus for bus 03
|
| PCI: pci_scan_bus returning with max=003
|
| do_pci_scan_bridge returns max 3
|
| scan_static_bus for PCI: 00:1f.0
|
| PNP: 00ff.1 enabled
|
| recv_ec_data: 0x47
|
| recv_ec_data: 0x32
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x33
|
| recv_ec_data: 0x31
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x16
|
| recv_ec_data: 0x03
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0x11
|
| EC Firmware ID G2HT31WW-3.22, Version 0.01B
|
| recv_ec_data: 0x40
|
| recv_ec_data: 0x90
|
| recv_ec_data: 0x60
|
| recv_ec_data: 0x70
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0xa6
|
| recv_ec_data: 0xe0
|
| recv_ec_data: 0x70
|
| PNP: 00ff.2 enabled
|
| scan_static_bus for PCI: 00:1f.0 done
|
| scan_static_bus for PCI: 00:1f.3
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
|
| scan_static_bus for PCI: 00:1f.3 done
|
| PCI: pci_scan_bus returning with max=003
|
| scan_static_bus for Root Device done
|
| done
|
| BS: Exiting BS_DEV_ENUMERATE state.
|
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 5757 exit 0
|
| BS: Entering BS_DEV_RESOURCES state.
|
| found VGA at PCI: 00:02.0
|
| Setting up VGA for PCI: 00:02.0
|
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
| Allocating resources...
|
| Reading resources...
|
| Root Device read_resources bus 0 link: 0
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
| APIC: 00 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0
|
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
| PCI: 00:1a.0 EHCI BAR hook registered
|
| PCI: 00:1c.0 read_resources bus 1 link: 0
|
| PCI: 00:1c.0 read_resources bus 1 link: 0 done
|
| PCI: 00:1c.1 read_resources bus 2 link: 0
|
| PCI: 00:1c.1 read_resources bus 2 link: 0 done
|
| PCI: 00:1c.2 read_resources bus 3 link: 0
|
| PCI: 00:1c.2 read_resources bus 3 link: 0 done
|
| More than one caller of pci_ehci_read_resources from PCI: 00:1d.0
|
| PCI: 00:1f.0 read_resources bus 0 link: 0
|
| PNP: 00ff.1 missing read_resources
|
| PNP: 00ff.2 missing read_resources
|
| PCI: 00:1f.0 read_resources bus 0 link: 0 done
|
| PCI: 00:1f.3 read_resources bus 1 link: 0
|
| PCI: 00:1f.3 read_resources bus 1 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0 done
|
| Root Device read_resources bus 0 link: 0 done
|
| Done reading resources.
|
| Show resources in subtree (Root Device)...After reading.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
|
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
|
| PCI: 00:14.0
|
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
|
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0
|
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 01:00.1
|
| PCI: 01:00.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 01:00.2
|
| PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0
|
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 02:00.0
|
| PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.3
|
| PCI: 00:1c.4
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
|
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.5
|
| PCI: 00:1f.6
|
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:02.0 20 * [0x0 - 0x3f] io
|
| PCI: 00:19.0 18 * [0x40 - 0x5f] io
|
| PCI: 00:1f.2 20 * [0x60 - 0x7f] io
|
| PCI: 00:1f.2 10 * [0x80 - 0x87] io
|
| PCI: 00:1f.2 18 * [0x88 - 0x8f] io
|
| PCI: 00:1f.2 14 * [0x90 - 0x93] io
|
| PCI: 00:1f.2 1c * [0x94 - 0x97] io
|
| DOMAIN: 0000 compute_resources_io: base: 98 size: 98 align: 6 gran: 0 limit: ffff done
|
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 01:00.0 10 * [0x0 - 0xff] mem
|
| PCI: 01:00.1 10 * [0x100 - 0x1ff] mem
|
| PCI: 01:00.2 10 * [0x200 - 0x2ff] mem
|
| PCI: 00:1c.0 compute_resources_mem: base: 300 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 02:00.0 10 * [0x0 - 0x1fff] mem
|
| PCI: 00:1c.1 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
|
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
|
| PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem
|
| PCI: 00:1c.1 20 * [0x10500000 - 0x105fffff] mem
|
| PCI: 00:19.0 10 * [0x10600000 - 0x1061ffff] mem
|
| PCI: 00:14.0 10 * [0x10620000 - 0x1062ffff] mem
|
| PCI: 00:1b.0 10 * [0x10630000 - 0x10633fff] mem
|
| PCI: 00:19.0 14 * [0x10634000 - 0x10634fff] mem
|
| PCI: 00:1f.2 24 * [0x10635000 - 0x106357ff] mem
|
| PCI: 00:1a.0 10 * [0x10635800 - 0x10635bff] mem
|
| PCI: 00:1d.0 10 * [0x10635c00 - 0x10635fff] mem
|
| PCI: 00:1f.3 10 * [0x10636000 - 0x106360ff] mem
|
| PCI: 00:16.0 10 * [0x10636100 - 0x1063610f] mem
|
| DOMAIN: 0000 compute_resources_mem: base: 10636110 size: 10636110 align: 28 gran: 0 limit: ffffffff done
|
| avoid_fixed_resources: DOMAIN: 0000
|
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
| constrain_resources: DOMAIN: 0000
|
| constrain_resources: PCI: 00:00.0
|
| constrain_resources: PCI: 00:02.0
|
| constrain_resources: PCI: 00:14.0
|
| constrain_resources: PCI: 00:16.0
|
| constrain_resources: PCI: 00:19.0
|
| constrain_resources: PCI: 00:1a.0
|
| constrain_resources: PCI: 00:1b.0
|
| constrain_resources: PCI: 00:1c.0
|
| constrain_resources: PCI: 01:00.0
|
| constrain_resources: PCI: 01:00.1
|
| constrain_resources: PCI: 01:00.2
|
| constrain_resources: PCI: 00:1c.1
|
| constrain_resources: PCI: 02:00.0
|
| constrain_resources: PCI: 00:1c.2
|
| constrain_resources: PCI: 00:1d.0
|
| constrain_resources: PCI: 00:1f.0
|
| constrain_resources: PNP: 00ff.1
|
| constrain_resources: PNP: 00ff.2
|
| skipping PNP: 00ff.2@60 fixed resource, size=0!
|
| skipping PNP: 00ff.2@62 fixed resource, size=0!
|
| skipping PNP: 00ff.2@64 fixed resource, size=0!
|
| skipping PNP: 00ff.2@66 fixed resource, size=0!
|
| constrain_resources: PCI: 00:1f.2
|
| constrain_resources: PCI: 00:1f.3
|
| constrain_resources: I2C: 01:54
|
| constrain_resources: I2C: 01:55
|
| constrain_resources: I2C: 01:56
|
| constrain_resources: I2C: 01:57
|
| constrain_resources: I2C: 01:5c
|
| constrain_resources: I2C: 01:5d
|
| constrain_resources: I2C: 01:5e
|
| constrain_resources: I2C: 01:5f
|
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
|
| lim->base 0000167c lim->limit 0000ffff
|
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
|
| lim->base 00000000 lim->limit efffffff
|
| Setting resources...
|
| DOMAIN: 0000 allocate_resources_io: base:167c size:98 align:6 gran:0 limit:ffff
|
| Assigned: PCI: 00:02.0 20 * [0x1800 - 0x183f] io
|
| Assigned: PCI: 00:19.0 18 * [0x1840 - 0x185f] io
|
| Assigned: PCI: 00:1f.2 20 * [0x1860 - 0x187f] io
|
| Assigned: PCI: 00:1f.2 10 * [0x1880 - 0x1887] io
|
| Assigned: PCI: 00:1f.2 18 * [0x1888 - 0x188f] io
|
| Assigned: PCI: 00:1f.2 14 * [0x1890 - 0x1893] io
|
| Assigned: PCI: 00:1f.2 1c * [0x1894 - 0x1897] io
|
| DOMAIN: 0000 allocate_resources_io: next_base: 1898 size: 98 align: 6 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10636110 align:28 gran:0 limit:efffffff
|
| Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
|
| Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
|
| Assigned: PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem
|
| Assigned: PCI: 00:1c.1 20 * [0xe0500000 - 0xe05fffff] mem
|
| Assigned: PCI: 00:19.0 10 * [0xe0600000 - 0xe061ffff] mem
|
| Assigned: PCI: 00:14.0 10 * [0xe0620000 - 0xe062ffff] mem
|
| Assigned: PCI: 00:1b.0 10 * [0xe0630000 - 0xe0633fff] mem
|
| Assigned: PCI: 00:19.0 14 * [0xe0634000 - 0xe0634fff] mem
|
| Assigned: PCI: 00:1f.2 24 * [0xe0635000 - 0xe06357ff] mem
|
| Assigned: PCI: 00:1a.0 10 * [0xe0635800 - 0xe0635bff] mem
|
| Assigned: PCI: 00:1d.0 10 * [0xe0635c00 - 0xe0635fff] mem
|
| Assigned: PCI: 00:1f.3 10 * [0xe0636000 - 0xe06360ff] mem
|
| Assigned: PCI: 00:16.0 10 * [0xe0636100 - 0xe063610f] mem
|
| DOMAIN: 0000 allocate_resources_mem: next_base: e0636110 size: 10636110 align: 28 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 01:00.0 10 * [0xe0400000 - 0xe04000ff] mem
|
| Assigned: PCI: 01:00.1 10 * [0xe0400100 - 0xe04001ff] mem
|
| Assigned: PCI: 01:00.2 10 * [0xe0400200 - 0xe04002ff] mem
|
| PCI: 00:1c.0 allocate_resources_mem: next_base: e0400300 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_mem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 02:00.0 10 * [0xe0500000 - 0xe0501fff] mem
|
| PCI: 00:1c.1 allocate_resources_mem: next_base: e0502000 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| Root Device assign_resources, bus 0 link: 0
|
| TOUUD 0x43b600000 TOLUD 0xc2a00000 TOM 0x400000000
|
| MEBASE 0x3fe000000
|
| IGD decoded, subtracting 32M UMA and 2M GTT
|
| TSEG base 0xc0000000 size 8M
|
| Available memory below 4GB: 3072M
|
| Available memory above 4GB: 13238M
|
| Adding PCIe config bar base=0xf0000000 size=0x4000000
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
|
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
|
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
|
| PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io
|
| PCI: 00:14.0 10 <- [0x00e0620000 - 0x00e062ffff] size 0x00010000 gran 0x10 mem64
|
| PCI: 00:16.0 10 <- [0x00e0636100 - 0x00e063610f] size 0x00000010 gran 0x04 mem64
|
| PCI: 00:19.0 10 <- [0x00e0600000 - 0x00e061ffff] size 0x00020000 gran 0x11 mem
|
| PCI: 00:19.0 14 <- [0x00e0634000 - 0x00e0634fff] size 0x00001000 gran 0x0c mem
|
| PCI: 00:19.0 18 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1a.0 EHCI Debug Port hook triggered
|
| PCI: 00:1a.0 10 <- [0x00e0635800 - 0x00e0635bff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1a.0 10 <- [0x00e0635800 - 0x00e0635bff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1a.0 EHCI Debug Port relocated
|
| PCI: 00:1b.0 10 <- [0x00e0630000 - 0x00e0633fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
| PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
|
| PCI: 00:1c.0 assign_resources, bus 1 link: 0
|
| PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e04000ff] size 0x00000100 gran 0x08 mem
|
| PCI: 01:00.1 10 <- [0x00e0400100 - 0x00e04001ff] size 0x00000100 gran 0x08 mem
|
| PCI: 01:00.2 10 <- [0x00e0400200 - 0x00e04002ff] size 0x00000100 gran 0x08 mem
|
| PCI: 00:1c.0 assign_resources, bus 1 link: 0
|
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
| PCI: 00:1c.1 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 02 mem
|
| PCI: 00:1c.1 assign_resources, bus 2 link: 0
|
| PCI: 02:00.0 10 <- [0x00e0500000 - 0x00e0501fff] size 0x00002000 gran 0x0d mem64
|
| PCI: 00:1c.1 assign_resources, bus 2 link: 0
|
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
|
| PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
| PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
|
| PCI: 00:1d.0 10 <- [0x00e0635c00 - 0x00e0635fff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PNP: 00ff.1 missing set_resources
|
| PNP: 00ff.2 missing set_resources
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PCI: 00:1f.2 10 <- [0x0000001880 - 0x0000001887] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 14 <- [0x0000001890 - 0x0000001893] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 18 <- [0x0000001888 - 0x000000188f] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 1c <- [0x0000001894 - 0x0000001897] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 20 <- [0x0000001860 - 0x000000187f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1f.2 24 <- [0x00e0635000 - 0x00e06357ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1f.3 10 <- [0x00e0636000 - 0x00e06360ff] size 0x00000100 gran 0x08 mem64
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| Root Device assign_resources, bus 0 link: 0
|
| Done setting resources.
|
| Show resources in subtree (Root Device)...After assigning values.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 167c size 98 align 6 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base d0000000 size 10636110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
|
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
|
| DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
|
| DOMAIN: 0000 resource base 100000000 size 33b600000 align 0 gran 0 limit 0 flags e0004200 index 5
|
| DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
|
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
|
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
|
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
|
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10
|
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
|
| PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
|
| PCI: 00:14.0
|
| PCI: 00:14.0 resource base e0620000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base e0636100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base e0600000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10
|
| PCI: 00:19.0 resource base e0634000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14
|
| PCI: 00:19.0 resource base 1840 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base e0635800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base e0630000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.0 child on link 0 PCI: 01:00.0
|
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 01:00.0
|
| PCI: 01:00.0 resource base e0400000 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 01:00.1
|
| PCI: 01:00.1 resource base e0400100 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 01:00.2
|
| PCI: 01:00.2 resource base e0400200 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0
|
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.1 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 02:00.0
|
| PCI: 02:00.0 resource base e0500000 size 2000 align 13 gran 13 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 00:1c.3
|
| PCI: 00:1c.4
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base e0635c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 1880 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
|
| PCI: 00:1f.2 resource base 1890 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
|
| PCI: 00:1f.2 resource base 1888 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
|
| PCI: 00:1f.2 resource base 1894 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
|
| PCI: 00:1f.2 resource base 1860 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
|
| PCI: 00:1f.2 resource base e0635000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base e0636000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.5
|
| PCI: 00:1f.6
|
| Done allocating resources.
|
| BS: Exiting BS_DEV_RESOURCES state.
|
| BS: BS_DEV_RESOURCES times (us): entry 0 run 2635 exit 0
|
| BS: Entering BS_DEV_ENABLE state.
|
| Enabling resources...
|
| PCI: 00:00.0 subsystem <- 0000/0000
|
| PCI: 00:00.0 cmd <- 06
|
| PCI: 00:02.0 subsystem <- 0000/0000
|
| PCI: 00:02.0 cmd <- 03
|
| PCI: 00:14.0 subsystem <- 0000/0000
|
| PCI: 00:14.0 cmd <- 102
|
| PCI: 00:16.0 subsystem <- 0000/0000
|
| PCI: 00:16.0 cmd <- 02
|
| PCI: 00:19.0 subsystem <- 0000/0000
|
| PCI: 00:19.0 cmd <- 103
|
| PCI: 00:1a.0 subsystem <- 0000/0000
|
| PCI: 00:1a.0 cmd <- 102
|
| PCI: 00:1b.0 subsystem <- 0000/0000
|
| PCI: 00:1b.0 cmd <- 102
|
| PCI: 00:1c.0 bridge ctrl <- 0003
|
| PCI: 00:1c.0 subsystem <- 0000/0000
|
| PCI: 00:1c.0 cmd <- 106
|
| PCI: 00:1c.1 bridge ctrl <- 0003
|
| PCI: 00:1c.1 subsystem <- 0000/0000
|
| PCI: 00:1c.1 cmd <- 106
|
| PCI: 00:1c.2 bridge ctrl <- 0003
|
| PCI: 00:1c.2 subsystem <- 0000/0000
|
| PCI: 00:1c.2 cmd <- 100
|
| PCI: 00:1d.0 subsystem <- 0000/0000
|
| PCI: 00:1d.0 cmd <- 102
|
| pch_decode_init
|
| PCI: 00:1f.0 subsystem <- 0000/0000
|
| PCI: 00:1f.0 cmd <- 107
|
| PCI: 00:1f.2 subsystem <- 0000/0000
|
| PCI: 00:1f.2 cmd <- 03
|
| PCI: 00:1f.3 subsystem <- 0000/0000
|
| PCI: 00:1f.3 cmd <- 103
|
| PCI: 01:00.0 cmd <- 06
|
| PCI: 01:00.1 cmd <- 06
|
| PCI: 01:00.2 cmd <- 06
|
| PCI: 02:00.0 cmd <- 02
|
| done.
|
| BS: Exiting BS_DEV_ENABLE state.
|
| BS: BS_DEV_ENABLE times (us): entry 0 run 162 exit 0
|
| BS: Entering BS_DEV_INIT state.
|
| Initializing devices...
|
| Root Device init
|
| Keyboard init...
|
| Keyboard controller output buffer result timeout
|
| Root Device init 512143 usecs
|
| CPU_CLUSTER: 0 init
|
| start_eip=0x00001000, code_size=0x00000031
|
| Installing SMM handler to 0xc0000000
|
| Installing IED header to 0xc0400000
|
| Initializing SMM handler... ... pmbase = 0x0500
|
|
|
| SMI_STS: MCSMI PM1
|
| PM1_STS: WAK PWRBTN TMROF
|
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW
|
| ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
|
| TCO_STS:
|
| ... raise SMI#
|
| Initializing CPU #0
|
| CPU: vendor Intel device 306a9
|
| CPU: family 06, model 3a, stepping 09
|
| Enabling cache
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz.
|
| MTRR: Physical address space:
|
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
|
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
|
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
|
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
|
| 0x0000000100000000 - 0x000000043b600000 size 0x33b600000 type 6
|
| MTRR addr 0x0-0x10 set to 6 type @ 0
|
| MTRR addr 0x10-0x20 set to 6 type @ 1
|
| MTRR addr 0x20-0x30 set to 6 type @ 2
|
| MTRR addr 0x30-0x40 set to 6 type @ 3
|
| MTRR addr 0x40-0x50 set to 6 type @ 4
|
| MTRR addr 0x50-0x60 set to 6 type @ 5
|
| MTRR addr 0x60-0x70 set to 6 type @ 6
|
| MTRR addr 0x70-0x80 set to 6 type @ 7
|
| MTRR addr 0x80-0x84 set to 6 type @ 8
|
| MTRR addr 0x84-0x88 set to 6 type @ 9
|
| MTRR addr 0x88-0x8c set to 6 type @ 10
|
| MTRR addr 0x8c-0x90 set to 6 type @ 11
|
| MTRR addr 0x90-0x94 set to 6 type @ 12
|
| MTRR addr 0x94-0x98 set to 6 type @ 13
|
| MTRR addr 0x98-0x9c set to 6 type @ 14
|
| MTRR addr 0x9c-0xa0 set to 6 type @ 15
|
| MTRR addr 0xa0-0xa4 set to 0 type @ 16
|
| MTRR addr 0xa4-0xa8 set to 0 type @ 17
|
| MTRR addr 0xa8-0xac set to 0 type @ 18
|
| MTRR addr 0xac-0xb0 set to 0 type @ 19
|
| MTRR addr 0xb0-0xb4 set to 0 type @ 20
|
| MTRR addr 0xb4-0xb8 set to 0 type @ 21
|
| MTRR addr 0xb8-0xbc set to 0 type @ 22
|
| MTRR addr 0xbc-0xc0 set to 0 type @ 23
|
| MTRR addr 0xc0-0xc1 set to 6 type @ 24
|
| MTRR addr 0xc1-0xc2 set to 6 type @ 25
|
| MTRR addr 0xc2-0xc3 set to 6 type @ 26
|
| MTRR addr 0xc3-0xc4 set to 6 type @ 27
|
| MTRR addr 0xc4-0xc5 set to 6 type @ 28
|
| MTRR addr 0xc5-0xc6 set to 6 type @ 29
|
| MTRR addr 0xc6-0xc7 set to 6 type @ 30
|
| MTRR addr 0xc7-0xc8 set to 6 type @ 31
|
| MTRR addr 0xc8-0xc9 set to 6 type @ 32
|
| MTRR addr 0xc9-0xca set to 6 type @ 33
|
| MTRR addr 0xca-0xcb set to 6 type @ 34
|
| MTRR addr 0xcb-0xcc set to 6 type @ 35
|
| MTRR addr 0xcc-0xcd set to 6 type @ 36
|
| MTRR addr 0xcd-0xce set to 6 type @ 37
|
| MTRR addr 0xce-0xcf set to 6 type @ 38
|
| MTRR addr 0xcf-0xd0 set to 6 type @ 39
|
| MTRR addr 0xd0-0xd1 set to 6 type @ 40
|
| MTRR addr 0xd1-0xd2 set to 6 type @ 41
|
| MTRR addr 0xd2-0xd3 set to 6 type @ 42
|
| MTRR addr 0xd3-0xd4 set to 6 type @ 43
|
| MTRR addr 0xd4-0xd5 set to 6 type @ 44
|
| MTRR addr 0xd5-0xd6 set to 6 type @ 45
|
| MTRR addr 0xd6-0xd7 set to 6 type @ 46
|
| MTRR addr 0xd7-0xd8 set to 6 type @ 47
|
| MTRR addr 0xd8-0xd9 set to 6 type @ 48
|
| MTRR addr 0xd9-0xda set to 6 type @ 49
|
| MTRR addr 0xda-0xdb set to 6 type @ 50
|
| MTRR addr 0xdb-0xdc set to 6 type @ 51
|
| MTRR addr 0xdc-0xdd set to 6 type @ 52
|
| MTRR addr 0xdd-0xde set to 6 type @ 53
|
| MTRR addr 0xde-0xdf set to 6 type @ 54
|
| MTRR addr 0xdf-0xe0 set to 6 type @ 55
|
| MTRR addr 0xe0-0xe1 set to 6 type @ 56
|
| MTRR addr 0xe1-0xe2 set to 6 type @ 57
|
| MTRR addr 0xe2-0xe3 set to 6 type @ 58
|
| MTRR addr 0xe3-0xe4 set to 6 type @ 59
|
| MTRR addr 0xe4-0xe5 set to 6 type @ 60
|
| MTRR addr 0xe5-0xe6 set to 6 type @ 61
|
| MTRR addr 0xe6-0xe7 set to 6 type @ 62
|
| MTRR addr 0xe7-0xe8 set to 6 type @ 63
|
| MTRR addr 0xe8-0xe9 set to 6 type @ 64
|
| MTRR addr 0xe9-0xea set to 6 type @ 65
|
| MTRR addr 0xea-0xeb set to 6 type @ 66
|
| MTRR addr 0xeb-0xec set to 6 type @ 67
|
| MTRR addr 0xec-0xed set to 6 type @ 68
|
| MTRR addr 0xed-0xee set to 6 type @ 69
|
| MTRR addr 0xee-0xef set to 6 type @ 70
|
| MTRR addr 0xef-0xf0 set to 6 type @ 71
|
| MTRR addr 0xf0-0xf1 set to 6 type @ 72
|
| MTRR addr 0xf1-0xf2 set to 6 type @ 73
|
| MTRR addr 0xf2-0xf3 set to 6 type @ 74
|
| MTRR addr 0xf3-0xf4 set to 6 type @ 75
|
| MTRR addr 0xf4-0xf5 set to 6 type @ 76
|
| MTRR addr 0xf5-0xf6 set to 6 type @ 77
|
| MTRR addr 0xf6-0xf7 set to 6 type @ 78
|
| MTRR addr 0xf7-0xf8 set to 6 type @ 79
|
| MTRR addr 0xf8-0xf9 set to 6 type @ 80
|
| MTRR addr 0xf9-0xfa set to 6 type @ 81
|
| MTRR addr 0xfa-0xfb set to 6 type @ 82
|
| MTRR addr 0xfb-0xfc set to 6 type @ 83
|
| MTRR addr 0xfc-0xfd set to 6 type @ 84
|
| MTRR addr 0xfd-0xfe set to 6 type @ 85
|
| MTRR addr 0xfe-0xff set to 6 type @ 86
|
| MTRR addr 0xff-0x100 set to 6 type @ 87
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: default type WB/UC MTRR counts: 3/11.
|
| MTRR: WB selected as default type.
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x00 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2800
|
| Turbo is available but hidden
|
| Turbo has been enabled
|
| CPU: 0 has 2 cores, 2 threads per core
|
| CPU: 0 has core 1
|
| CPU1: stack_base 00171000, stack_end 00171ff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 1.
|
| After apic_write.
|
| Initializing CPU #1
|
| Startup point 1.
|
| CPU: vendor Intel device 306a9
|
| Waiting for send to finish...
|
| CPU: family 06, model 3a, stepping 09
|
| +Enabling cache
|
| Sending STARTUP #2 to 1.
|
| After apic_write.
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| CPU: 0 has core 2
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| CPU2: stack_base 00170000, stack_end 00170ff8
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Asserting INIT.
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Waiting for send to finish...
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| +call enable_fixed_mtrr()
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x01 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2800
|
| CPU #1 initialized
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 2.
|
| After apic_write.
|
| Initializing CPU #2
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 306a9
|
| Sending STARTUP #2 to 2.
|
| After apic_write.
|
| CPU: family 06, model 3a, stepping 09
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Enabling cache
|
| After Startup.
|
| CPU: 0 has core 3
|
| CPU3: stack_base 0016f000, stack_end 0016fff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +microcode: sig=0x306a9 pf=0x10 revision=0x0
|
| microcode: updated to revision 0x17 date=2013-01-09
|
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x269 0x0606060606060606
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 3.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Initializing CPU #3
|
| Sending STARTUP #2 to 3.
|
| After apic_write.
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 306a9
|
| After Startup.
|
| CPU #0 initialized
|
| Waiting for 2 CPUS to stop
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| CPU: family 06, model 3a, stepping 09
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| Enabling cache
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| microcode: sig=0x306a9 pf=0x10 revision=0x17
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| CPU: Intel(R) Core(TM) i5-3360M CPU @ 2.80GHz.
|
| call enable_fixed_mtrr()
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
|
| MTRR check
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| Fixed MTRRs : MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| Enabled
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| Variable MTRRs: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| Enabled
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Setting up local apic...MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| apic_id: 0x02 call enable_fixed_mtrr()
|
| done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| model_x06ax: frequency set to 2800
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| CPU #2 initialized
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| Waiting for 1 CPUS to stop
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x03 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2800
|
| CPU #3 initialized
|
| All AP CPUs stopped (4278 loops)
|
| CPU1: stack: 00171000 - 00172000, lowest used address 00171cd0, stack used: 816 bytes
|
| CPU2: stack: 00170000 - 00171000, lowest used address 00170cd0, stack used: 816 bytes
|
| CPU3: stack: 0016f000 - 00170000, lowest used address 0016fcd0, stack used: 816 bytes
|
| CPU_CLUSTER: 0 init 128984 usecs
|
| PCI: 00:00.0 init
|
| Set BIOS_RESET_CPL
|
| CPU TDP: 35 Watts
|
| PCI: 00:00.0 init 1008 usecs
|
| PCI: 00:02.0 init
|
| GT Power Management Init
|
| IVB GT2 25W-35W Power Meter Weights
|
| GT Power Management Init (post VBIOS)
|
| Initializing VGA without OPROM.
|
| EDID:
|
| 00 ff ff ff ff ff ff 00 30 e4 d8 02 00 00 00 00
|
| 00 16 01 03 80 1c 10 78 ea 88 55 99 5b 55 8f 26
|
| 1d 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
|
| 01 01 01 01 01 01 60 1d 56 d8 50 00 18 30 30 40
|
| 47 00 15 9c 10 00 00 1b 00 00 00 00 00 00 00 00
|
| 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 4c
|
| 47 20 44 69 73 70 6c 61 79 0a 20 20 00 00 00 fe
|
| 00 4c 50 31 32 35 57 48 32 2d 53 4c 42 33 00 59
|
| Extracted contents:
|
| header: 00 ff ff ff ff ff ff 00
|
| serial number: 30 e4 d8 02 00 00 00 00 00 16
|
| version: 01 03
|
| basic params: 80 1c 10 78 ea
|
| chroma info: 88 55 99 5b 55 8f 26 1d 50 54
|
| established: 00 00 00
|
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
| descriptor 1: 60 1d 56 d8 50 00 18 30 30 40 47 00 15 9c 10 00 00 1b
|
| descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
| descriptor 3: 00 00 00 fe 00 4c 47 20 44 69 73 70 6c 61 79 0a 20 20
|
| descriptor 4: 00 00 00 fe 00 4c 50 31 32 35 57 48 32 2d 53 4c 42 33
|
| extensions: 00
|
| checksum: 59
|
|
|
| Manufacturer: LGD Model 2d8 Serial Number 0
|
| Made week 0 of 2012
|
| EDID version: 1.3
|
| Digital display
|
| Maximum image size: 28 cm x 16 cm
|
| Gamma: 220%
|
| Check DPMS levels
|
| DPMS levels: Standby Suspend Off
|
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2
|
| First detailed timing is preferred timing
|
| Established timings supported:
|
| Standard timings supported:
|
| Detailed timings
|
| Hex of detail: 601d56d85000183030404700159c1000001b
|
| Did detailed timing
|
| Detailed mode (IN HEX): Clock 75200 KHz, 115 mm x 9c mm
|
| 0556 0586 05c6 062e hborder 0
|
| 0300 0304 030b 0318 vborder 0
|
| +hsync -vsync
|
| Hex of detail: 000000000000000000000000000000000000
|
| Manufacturer-specified data, tag 0
|
| Hex of detail: 000000fe004c4720446973706c61790a2020
|
| ASCII string: LG
|
| Hex of detail: 000000fe004c503132355748322d534c4233
|
| ASCII string: LP125WH2
|
| Checksum
|
| Checksum: 0x59 (valid)
|
|
|
| Unknown extension block
|
|
|
| EDID block does NOT conform to EDID 1.3!
|
| Missing name descriptor
|
| Missing monitor ranges
|
| Detailed block string not properly terminated
|
| EDID block does not conform at all!
|
| Detailed blocks filled with garbage
|
| bringing up panel at resolution 1376 x 768
|
| Borders 0 x 0
|
| Blank 216 x 24
|
| Sync 64 x 7
|
| Front porch 48 x 4
|
| Spread spectrum clock
|
| Single channel
|
| Polarities 0, 1
|
| Data M1=5256861, N1=8388608
|
| Link frequency 270000 kHz
|
| Link M1=146023, N1=524288
|
| Pixel N=9, M1=14, M2=9, P1=1
|
| Pixel clock 150476 kHz
|
| waiting for panel powerup
|
| panel powered up
|
| PCI: 00:02.0 init 32512 usecs
|
| PCI: 00:14.0 init
|
| XHCI: Setting up controller.. done.
|
| PCI: 00:14.0 init 4 usecs
|
| PCI: 00:16.0 init
|
| ME: FW Partition Table : OK
|
| ME: Bringup Loader Failure : NO
|
| ME: Firmware Init Complete : NO
|
| ME: Manufacturing Mode : NO
|
| ME: Boot Options Present : NO
|
| ME: Update In Progress : NO
|
| ME: Current Working State : Normal
|
| ME: Current Operation State : M0 with UMA
|
| ME: Current Operation Mode : Normal
|
| ME: Error Code : No Error
|
| ME: Progress Phase : Host Communication
|
| ME: Power Management Event : Clean Moff->Mx wake
|
| ME: Progress Phase State : Host communication established
|
| ME: BIOS path: Normal
|
| ME: Extend SHA-256: e4296030ae179336fc242e1a495f7121e9bea777ff01a32141277ff3e64e84b8
|
| ME: MBP item header 00020103
|
| ME: MBP item header 00050102
|
| ME: MBP item header 00020501
|
| ME: MBP item header 00020201
|
| ME: MBP item header 00020104
|
| ME: unknown mbp item id 0x104! Skipping
|
| ME: MBP item header 02030101
|
| ME: MBP item header 02060301
|
| ME: MBP item header 02090401
|
| ME: mbp read OK after 1 cycles
|
| ME: found version 8.1.20.1336
|
| ME Capability: Full Network manageability : enabled
|
| ME Capability: Regular Network manageability : disabled
|
| ME Capability: Manageability : enabled
|
| ME Capability: Small business technology : disabled
|
| ME Capability: Level III manageability : disabled
|
| ME Capability: IntelR Anti-Theft (AT) : enabled
|
| ME Capability: IntelR Capability Licensing Service (CLS) : enabled
|
| ME Capability: IntelR Power Sharing Technology (MPC) : enabled
|
| ME Capability: ICC Over Clocking : enabled
|
| ME Capability: Protected Audio Video Path (PAVP) : enabled
|
| ME Capability: IPV6 : enabled
|
| ME Capability: KVM Remote Control (KVM) : enabled
|
| ME Capability: Outbreak Containment Heuristic (OCH) : disabled
|
| ME Capability: Virtual LAN (VLAN) : enabled
|
| ME Capability: TLS : enabled
|
| ME Capability: Wireless LAN (WLAN) : enabled
|
| PCI: 00:16.0 init 63 usecs
|
| PCI: 00:19.0 init
|
| PCI: 00:19.0 init 1 usecs
|
| PCI: 00:1a.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1a.0 init 13 usecs
|
| PCI: 00:1b.0 init
|
| Azalia: base = e0630000
|
| Azalia: codec_mask = 09
|
| Azalia: Initializing codec #3
|
| Azalia: codec viddid: 80862806
|
| Azalia: verb_size: 16
|
| Azalia: verb loaded.
|
| Azalia: Initializing codec #0
|
| Azalia: codec viddid: 10ec0269
|
| Azalia: verb_size: 500
|
| Azalia: verb loaded.
|
| PCI: 00:1b.0 init 23598 usecs
|
| PCI: 00:1c.0 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.0 init 10 usecs
|
| PCI: 00:1c.1 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.1 init 10 usecs
|
| PCI: 00:1c.2 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.2 init 9 usecs
|
| PCI: 00:1d.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1d.0 init 13 usecs
|
| PCI: 00:1f.0 init
|
| pch: lpc_init
|
| IOAPIC: Initializing IOAPIC at 0xfec00000
|
| IOAPIC: Bootstrap Processor Local APIC = 0x00
|
| IOAPIC: ID = 0x02
|
| IOAPIC: Dumping registers
|
| reg 0x0000: 0x02000000
|
| reg 0x0001: 0x00170020
|
| reg 0x0002: 0x00170020
|
| Set power on after power failure.
|
| NMI sources enabled.
|
| PantherPoint PM init
|
| rtc_failed = 0x0
|
| RTC Init
|
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
|
| done.
|
| Locking SMM.
|
| PCI: 00:1f.0 init 1103 usecs
|
| PCI: 00:1f.2 init
|
| SATA: Initializing...
|
| SATA: Controller in AHCI mode.
|
| ABAR: E0635000
|
| PCI: 00:1f.2 init 600 usecs
|
| PCI: 00:1f.3 init
|
| PCI: 00:1f.3 init 7 usecs
|
| PCI: 01:00.0 init
|
| PCI: 01:00.0 init 1 usecs
|
| PCI: 01:00.1 init
|
| PCI: 01:00.1 init 1 usecs
|
| PCI: 01:00.2 init
|
| PCI: 01:00.2 init 0 usecs
|
| PCI: 02:00.0 init
|
| PCI: 02:00.0 init 0 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
| I2C: 01:54 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
| I2C: 01:55 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
| I2C: 01:56 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
| I2C: 01:57 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
| Locking EEPROM RFID
|
| init EEPROM done
|
| I2C: 01:5c init 25460 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
| I2C: 01:5d init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
| I2C: 01:5e init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
| I2C: 01:5f init 1 usecs
|
| Devices initialized
|
| Show all devs...After init.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:14.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 0
|
| PCI: 00:1c.4: enabled 0
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 01:54: enabled 1
|
| I2C: 01:55: enabled 1
|
| I2C: 01:56: enabled 1
|
| I2C: 01:57: enabled 1
|
| I2C: 01:5c: enabled 1
|
| I2C: 01:5d: enabled 1
|
| I2C: 01:5e: enabled 1
|
| I2C: 01:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 0
|
| PCI: 01:00.0: enabled 1
|
| PCI: 01:00.1: enabled 1
|
| PCI: 01:00.2: enabled 1
|
| PCI: 02:00.0: enabled 1
|
| APIC: 01: enabled 1
|
| APIC: 02: enabled 1
|
| APIC: 03: enabled 1
|
| BS: Exiting BS_DEV_INIT state.
|
| BS: BS_DEV_INIT times (us): entry 0 run 725579 exit 0
|
| BS: Entering BS_POST_DEVICE state.
|
| CBMEM region bfed0000-bfffffff (cbmem_check_toc)
|
| Adding CBMEM entry as no. 7
|
| Moving GDT to bfee1000...ok
|
| Finalize devices...
|
| Devices finalized
|
| BS: Exiting BS_POST_DEVICE state.
|
| BS: BS_POST_DEVICE times (us): entry 7 run 2 exit 0
|
| BS: Entering BS_OS_RESUME_CHECK state.
|
| BS: Exiting BS_OS_RESUME_CHECK state.
|
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
|
| BS: Entering BS_WRITE_TABLES state.
|
| Updating MRC cache data.
|
| find_current_mrc_cache_local: No valid MRC cache found.
|
| flash size 0xc00000 bytes
|
| SF: Detected Opaque HW-sequencing with page size 1000, total c00000
|
| Need to erase the MRC cache region of 65536 bytes at fffe0000
|
| SF: Successfully erased 65536 bytes @ 0xbe0000
|
| Finally: write MRC cache update to flash at fffe0000
|
| SF: Successfully written 1056 bytes @ 0xbe0000
|
| Adding CBMEM entry as no. 8
|
| ACPI: Writing ACPI tables at bfee1200.
|
| ACPI: * FACS
|
| ACPI: * DSDT
|
| ACPI: * FADT
|
| ACPI: added table 1/32, length now 40
|
| ACPI: * HPET
|
| ACPI: added table 2/32, length now 44
|
| ACPI: * MADT
|
| ACPI: added table 3/32, length now 48
|
| ACPI: * MCFG
|
| ACPI: added table 4/32, length now 52
|
| ACPI: Patching up global NVS in DSDT at offset 0x00bd -> 0xbfee4c10
|
| Adding CBMEM entry as no. 9
|
| ACPI: * DSDT @ bfee1450 Length 35cf
|
| ACPI: * SSDT
|
| Found 1 CPU(s) with 4 core(s) each.
|
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300
|
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00
|
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800
|
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00
|
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300
|
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00
|
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800
|
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00
|
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300
|
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00
|
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800
|
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00
|
| PSS: 2801MHz power 35000 control 0x2300 status 0x2300
|
| PSS: 2800MHz power 35000 control 0x1c00 status 0x1c00
|
| PSS: 2400MHz power 28615 control 0x1800 status 0x1800
|
| PSS: 2000MHz power 22765 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 17346 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 12373 control 0xc00 status 0xc00
|
| ACPI: added table 5/32, length now 56
|
| current = bfee6e40
|
| ACPI: done.
|
| ACPI tables: 23616 bytes.
|
| Adding CBMEM entry as no. 10
|
| smbios_write_tables: bfeec800
|
| Root Device (LENOVO 2325TLU)
|
| CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| APIC: 00 (Socket rPGA989 CPU)
|
| APIC: acac (Intel SandyBridge/IvyBridge CPU)
|
| DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:01.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
|
| PNP: 00ff.2 (Lenovo H8 EC)
|
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| I2C: 01:54 (AT24RF08C)
|
| I2C: 01:55 (AT24RF08C)
|
| I2C: 01:56 (AT24RF08C)
|
| I2C: 01:57 (AT24RF08C)
|
| I2C: 01:5c (AT24RF08C)
|
| I2C: 01:5d (AT24RF08C)
|
| I2C: 01:5e (AT24RF08C)
|
| I2C: 01:5f (AT24RF08C)
|
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 01:00.0 (unknown)
|
| PCI: 01:00.1 (unknown)
|
| PCI: 01:00.2 (unknown)
|
| PCI: 02:00.0 (unknown)
|
| APIC: 01 (unknown)
|
| APIC: 02 (unknown)
|
| APIC: 03 (unknown)
|
| SMBIOS tables: 367 bytes.
|
| Adding CBMEM entry as no. 11
|
| Adding CBMEM entry as no. 12
|
| Writing table forward entry at 0x00000500
|
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6fdf
|
| Table forward entry ends at 0x00000528.
|
| ... aligned to 0x00001000
|
| Writing coreboot table at 0xbffed000
|
| rom_table_end = 0xbffed000
|
| ... aligned to 0xbfff0000
|
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
| 1. 0000000000001000-000000000009ffff: RAM
|
| 2. 00000000000a0000-00000000000fffff: RESERVED
|
| 3. 0000000000100000-000000001fffffff: RAM
|
| 4. 0000000020000000-00000000201fffff: RESERVED
|
| 5. 0000000020200000-000000003fffffff: RAM
|
| 6. 0000000040000000-00000000401fffff: RESERVED
|
| 7. 0000000040200000-00000000bfecffff: RAM
|
| 8. 00000000bfed0000-00000000bfffffff: CONFIGURATION TABLES
|
| 9. 00000000c0000000-00000000c29fffff: RESERVED
|
| 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
| 11. 0000000100000000-000000043b5fffff: RAM
|
| Wrote coreboot table at: bffed000, 0x8c8 bytes, checksum ff93
|
| coreboot table: 2272 bytes.
|
| FREE SPACE 0. bfff5000 0000b000
|
| CAR GLOBALS 1. bfed0200 00000200
|
| USBDEBUG 2. bfed0400 00000200
|
| CONSOLE 3. bfed0600 00010000
|
| TIME STAMP 4. bfee0600 00000200
|
| MRC DATA 5. bfee0800 00000600
|
| ROMSTAGE 6. bfee0e00 00000200
|
| GDT 7. bfee1000 00000200
|
| ACPI 8. bfee1200 0000b400
|
| GNVS PTR 9. bfeec600 00000200
|
| SMBIOS 10. bfeec800 00000800
|
| ACPI RESUME11. bfeed000 00100000
|
| COREBOOT 12. bffed000 00008000
|
| BS: Exiting BS_WRITE_TABLES state.
|
| BS: BS_WRITE_TABLES times (us): entry 952937 run 15822 exit 0
|
| BS: Entering BS_PAYLOAD_LOAD state.
|
| CBFS: located payload @ fff3d638, 245452 bytes.
|
| Loading segment from rom address 0xfff3d638
|
| code (compression=1)
|
| New segment dstaddr 0x8200 memsize 0x17dc0 srcaddr 0xfff3d68c filesize 0x8403
|
| (cleaned up) New segment addr 0x8200 size 0x17dc0 offset 0xfff3d68c filesize 0x8403
|
| Loading segment from rom address 0xfff3d654
|
| code (compression=1)
|
| New segment dstaddr 0x100000 memsize 0xa5fd0 srcaddr 0xfff45a8f filesize 0x33a75
|
| (cleaned up) New segment addr 0x100000 size 0xa5fd0 offset 0xfff45a8f filesize 0x33a75
|
| Loading segment from rom address 0xfff3d670
|
| Entry Point 0x00008200
|
| Bounce Buffer at bfdb2000, 1167372 bytes
|
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017dc0 filesz: 0x0000000000008403
|
| lb: [0x0000000000100000, 0x000000000017703c)
|
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017dc0 filesz: 0x0000000000008403
|
| using LZMA
|
| [ 0x00008200, 0001868f, 0x0001ffc0) <- fff3d68c
|
| Clearing Segment: addr: 0x000000000001868f memsz: 0x0000000000007931
|
| dest 00008200, end 0001ffc0, bouncebuffer bfdb2000
|
| Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000a5fd0 filesz: 0x0000000000033a75
|
| lb: [0x0000000000100000, 0x000000000017703c)
|
| segment: [0x0000000000100000, 0x0000000000133a75, 0x00000000001a5fd0)
|
| bounce: [0x00000000bfdb2000, 0x00000000bfde5a75, 0x00000000bfe57fd0)
|
| Post relocation: addr: 0x00000000bfdb2000 memsz: 0x00000000000a5fd0 filesz: 0x0000000000033a75
|
| using LZMA
|
| [ 0xbfdb2000, bfe57fd0, 0xbfe57fd0) <- fff45a8f
|
| dest bfdb2000, end bfe57fd0, bouncebuffer bfdb2000
|
| move suffix around: from bfe2903c, to 17703c, amount: 2ef94
|
| Loaded segments
|
| BS: Exiting BS_PAYLOAD_LOAD state.
|
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 122119 exit 0
|
| BS: Entering BS_PAYLOAD_BOOT state.
|
| PCH watchdog disabled
|
| Jumping to boot code at 00008200
|
| CPU0: stack: 00172000 - 00173000, lowest used address 00172aac, stack used: 1364 bytes
|
| entry = 0x00008200
|
| lb_start = 0x00100000
|
| lb_size = 0x0007703c
|
| buffer = 0xbfdb2000
|
| error: terminal `console' isn't found. |
|
error: file `/boot/grub/i386-coreboot/password_pbkdf2.mod' not found. |
|
GNU GRUB version 2.02~beta2 |
|
|
|
+----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
|
Press enter to boot the selected OS, `e' to edit the commands |
|
before booting or `c' for a command-line. *Debian GNU/Linux Advanced options for Debian GNU/Linux Debian GNU/Linux, with Xen hypervisor Advanced options for Debian GNU/Linux (with Xen hypervisor) Memory test (memtest86+) Memory test (memtest86+, serial console 115200) Memory test (memtest86+, experimental multiboot) Memory test (memtest86+, serial console 115200, experime |
| 724 bytes lost |