| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| = cc186465 |
| OTHP [440c] = a08b4 |
| OTHP [440c] = 8b4 |
| REFI [4698] = 6cd01860 |
| SRFTP [46a4] = 41f88200 |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 4 |
| PCI(0, 0, 0)[bc] = 82a00000 |
| PCI(0, 0, 0)[a8] = 7b600000 |
| PCI(0, 0, 0)[ac] = 4 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| PCI(0, 0, 0)[7c] = 7f |
| PCI(0, 0, 0)[70] = fe000000 |
| PCI(0, 0, 0)[74] = 3 |
| PCI(0, 0, 0)[78] = fe000c00 |
| Done memory map |
| RCOMP...done |
| COMP2 done |
| COMP1 done |
| FORCE RCOMP and wait 20us...done |
| Done io registers |
| CPE |
| CP5b |
| CP5c |
| OTHP [400c] = 8b4 |
| OTHP [440c] = 8b4 |
| t123: 1767, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : 0x4e |
| ME: FWS2: 0x164e0002 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x4e |
| ME: Current PM event: 0x6 |
| ME: Progress code : 0x1 |
| Waited long enough, or CPU was not replaced, continue... |
| PASSED! Tell ME that DRAM is ready |
| ME: FWS2: 0x162c0002 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x2c |
| ME: Current PM event: 0x6 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: Continue to boot |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : 0x2c |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1596 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ 7ffff000 254 entries. |
| IMD: root @ 7fffec00 62 entries. |
| External stage cache: |
| IMD: root @ 803ff000 254 entries. |
| IMD: root @ 803fec00 62 entries. |
| CBMEM entry for DIMM info: 0x7fffea40 |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| CBFS @ 30200 size 7cfe00 |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 13c5c |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 13d40 |
| CBFS: File @ offset 13d40 size 6800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 13d40 |
| CBFS: Checking offset 1a5c0 |
| CBFS: File @ offset 1a5c0 size 46dd0 |
| CBFS: Unmatched 'fallback/ramstage' at 1a5c0 |
| CBFS: Checking offset 61400 |
| CBFS: File @ offset 61400 size 4a7 |
| CBFS: Unmatched 'config' at 61400 |
| CBFS: Checking offset 61900 |
| CBFS: File @ offset 61900 size 2a1 |
| CBFS: Unmatched 'revision' at 61900 |
| CBFS: Checking offset 61c00 |
| CBFS: File @ offset 61c00 size 100 |
| CBFS: Unmatched 'cmos.default' at 61c00 |
| CBFS: Checking offset 61d40 |
| CBFS: File @ offset 61d40 size 531 |
| CBFS: Unmatched 'vbt.bin' at 61d40 |
| CBFS: Checking offset 622c0 |
| CBFS: File @ offset 622c0 size 4ac |
| CBFS: Unmatched 'cmos_layout.bin' at 622c0 |
| CBFS: Checking offset 627c0 |
| CBFS: File @ offset 627c0 size 33d4 |
| CBFS: Found @ offset 627c0 size 33d4 |
| Decompressing stage fallback/postcar @ 0x7ffd8fc0 (13832 bytes) |
| Loading module at 7ffd9000 with entry 7ffd9000. filesize: 0x3190 memsize: 0x35c8 |
| Processing 122 relocs. Offset value of 0x7dfd9000 |
| |
| |
| coreboot-4.10-91-g1a64194307 Sun Jul 28 16:34:11 UTC 2019 postcar starting (log level: 7)... |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 1a5c0 size 46dd0 |
| Decompressing stage fallback/ramstage @ 0x7ff7ffc0 (359320 bytes) |
| Loading module at 7ff80000 with entry 7ff80000. filesize: 0x429d8 memsize: 0x57b58 |
| Processing 4327 relocs. Offset value of 0x7f180000 |
| |
| |
| coreboot-4.10-91-g1a64194307 Sun Jul 28 16:34:11 UTC 2019 ramstage starting (log level: 7)... |
| get_vpd_size: No RO_VPD FMAP section. |
| get_vpd_size: No RW_VPD FMAP section. |
| Normal boot. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 1 |
| Enumerating buses... |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/0154] enabled |
| PCI: 00:01.0 [8086/0151] enabled |
| PCI: 00:02.0 [8086/0166] enabled |
| PCI: 00:04.0 [8086/0153] enabled |
| PCI: 00:16.0 [8086/1c3a] enabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.1 [8086/1c3b] disabled No operations |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.2 [8086/1c3c] disabled No operations |
| PCI: 00:16.3 [8086/1c3d] enabled |
| PCI: 00:19.0 [8086/1502] enabled |
| PCI: 00:1a.0 [8086/1c2d] enabled |
| PCI: 00:1b.0 [8086/1c20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0 [8086/1c10] enabled |
| PCI: 00:1c.1 [8086/1c12] enabled |
| PCI: 00:1c.2 [8086/1c14] enabled |
| PCI: 00:1c.3 [8086/1c16] enabled |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.4: check set enabled |
| PCI: 00:1c.4 [8086/1c18] disabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.5 [8086/1c1a] disabled |
| PCH: Remap PCIe function 6 to 4 |
| PCI: 00:1c.6 [8086/1c1c] enabled |
| PCH: Remap PCIe function 7 to 4 |
| PCH: PCIe map 1c.4 -> 1c.7 |
| PCH: PCIe map 1c.6 -> 1c.4 |
| PCH: PCIe map 1c.7 -> 1c.6 |
| PCI: 00:1c.6 [8086/1c1e] enabled |
| PCI: 00:1d.0 [8086/1c26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1e.0 [8086/2448] disabled |
| PCI: 00:1f.0 [8086/1c4f] enabled |
| FMAP: area COREBOOT found @ 30200 (8191488 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 622c0 size 4ac |
| PCI: 00:1f.2 [8086/1c01] enabled |
| PCI: 00:1f.3: Disabling device |
| PCI: 00:1f.3 [8086/1c22] disabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1c09] disabled No operations |
| PCI: 00:1f.6: Disabling device |
| PCI: 00:1f.6 [8086/1c24] disabled No operations |
| PCI: pci_scan_bus for bus 01 |
| scan_bus: scanning of bus PCI: 00:01.0 took 7 usecs |
| PCI: pci_scan_bus for bus 02 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 38 usecs |
| PCI: pci_scan_bus for bus 03 |
| scan_bus: scanning of bus PCI: 00:1c.1 took 39 usecs |
| PCI: pci_scan_bus for bus 04 |
| PCI: 04:00.0 [197b/2380] enabled |
| PCI: 04:00.1 [197b/2392] enabled |
| PCI: 04:00.2 [197b/2391] enabled |
| PCI: 04:00.3 [197b/2393] enabled |
| PCI: 04:00.4 [197b/2394] enabled |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Enabling Common Clock Configuration |
| PCIE CLK PM is not supported by endpoint |
| ASPM: Enabled None |
| Failed to enable LTR for dev = PCI: 04:00.0 |
| Failed to enable LTR for dev = PCI: 04:00.1 |
| Failed to enable LTR for dev = PCI: 04:00.2 |
| Failed to enable LTR for dev = PCI: 04:00.3 |
| Failed to enable LTR for dev = PCI: 04:00.4 |
| scan_bus: scanning of bus PCI: 00:1c.2 took 837 usecs |
| PCI: pci_scan_bus for bus 05 |
| scan_bus: scanning of bus PCI: 00:1c.3 took 39 usecs |
| PCI: pci_scan_bus for bus 06 |
| scan_bus: scanning of bus PCI: 00:1c.4 took 38 usecs |
| PCI: pci_scan_bus for bus 07 |
| PCI: 07:00.0 [1033/0194] enabled |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| scan_bus: scanning of bus PCI: 00:1c.6 took 232 usecs |
| KBC1126: initialize fan control.KBC1126: fan control initialized. |
| PNP: 00ff.1 disabled |
| PNP: 004e.3 enabled |
| PNP: 004e.4 enabled |
| PNP: 004e.5 disabled |
| PNP: 0c31.0 enabled |
| scan_bus: scanning of bus PCI: 00:1f.0 took 4067 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 5658 usecs |
| scan_bus: scanning of bus Root Device took 5663 usecs |
| done |
| FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) |
| MRC: No data in cbmem for 'RW_MRC_CACHE'. |
| MRC: Could not find region 'UNIFIED_MRC_CACHE' |
| FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) |
| MRC: NOT enabling PRR for 'RW_MRC_CACHE'. |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 5683 exit 7 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| Done reading resources. |
| Setting resources... |
| TOUUD 0x47b600000 TOLUD 0x82a00000 TOM 0x400000000 |
| MEBASE 0x3fe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 14262M |
| PCI: 00:01.0 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:01.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:01.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:02.0 10 <- [0x00e2400000 - 0x00e27fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x00e2920000 - 0x00e2927fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:16.0 10 <- [0x00e2931000 - 0x00e293100f] size 0x00000010 gran 0x04 mem64 |
| PCI: 00:16.3 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io |
| PCI: 00:16.3 14 <- [0x00e292c000 - 0x00e292cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 10 <- [0x00e2900000 - 0x00e291ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00e292d000 - 0x00e292dfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 10 <- [0x00e292f000 - 0x00e292f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00e2928000 - 0x00e292bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem |
| PCI: 00:1c.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io |
| PCI: 00:1c.1 24 <- [0x00e0c00000 - 0x00e13fffff] size 0x00800000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.1 20 <- [0x00e1400000 - 0x00e1bfffff] size 0x00800000 gran 0x14 bus 03 mem |
| NONE missing set_resources |
| PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io |
| PCI: 00:1c.2 24 <- [0x00e1c00000 - 0x00e23fffff] size 0x00800000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.2 20 <- [0x00e0000000 - 0x00e08fffff] size 0x00900000 gran 0x14 bus 04 mem |
| PCI: 04:00.0 10 <- [0x00e0810000 - 0x00e08107ff] size 0x00000800 gran 0x0b mem |
| PCI: 04:00.0 14 <- [0x00e0811000 - 0x00e08110ff] size 0x00000100 gran 0x08 mem |
| PCI: 04:00.1 10 <- [0x00e0812000 - 0x00e08120ff] size 0x00000100 gran 0x08 mem |
| PCI: 04:00.1 30 <- [0x00e0800000 - 0x00e080ffff] size 0x00010000 gran 0x10 romem |
| PCI: 04:00.2 10 <- [0x00e0813000 - 0x00e08130ff] size 0x00000100 gran 0x08 mem |
| PCI: 04:00.3 10 <- [0x00e0814000 - 0x00e08140ff] size 0x00000100 gran 0x08 mem |
| PCI: 04:00.4 10 <- [0x00e0815000 - 0x00e08150ff] size 0x00000100 gran 0x08 mem |
| NONE missing set_resources |
| PCI: 00:1c.3 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 05 io |
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 prefmem |
| PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 mem |
| PCI: 00:1c.4 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 06 io |
| PCI: 00:1c.4 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 06 prefmem |
| PCI: 00:1c.4 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 06 mem |
| PCI: 00:1c.6 1c <- [0x000000fdff - 0x000000fdfe] size 0x00000000 gran 0x0c bus 07 io |
| PCI: 00:1c.6 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 07 prefmem |
| PCI: 00:1c.6 20 <- [0x00e2800000 - 0x00e28fffff] size 0x00100000 gran 0x14 bus 07 mem |
| PCI: 07:00.0 10 <- [0x00e2800000 - 0x00e2801fff] size 0x00002000 gran 0x0d mem64 |
| PCI: 00:1d.0 10 <- [0x00e2930000 - 0x00e29303ff] size 0x00000400 gran 0x0a mem |
| PNP: 004e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io |
| PNP: 004e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq |
| ERROR: PNP: 004e.3 74 not allocated |
| PNP: 004e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io |
| PNP: 004e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq |
| PCI: 00:1f.2 10 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000003098 - 0x000000309b] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000003090 - 0x0000003097] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x000000309c - 0x000000309f] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00e292e000 - 0x00e292e7ff] size 0x00000800 gran 0x0b mem |
| Done setting resources. |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 1934 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 103c/161c |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:01.0 bridge ctrl <- 0003 |
| PCI: 00:01.0 subsystem <- 8086/0151 |
| PCI: 00:01.0 cmd <- 00 |
| PCI: 00:02.0 subsystem <- 103c/161c |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:16.0 subsystem <- 103c/161c |
| PCI: 00:16.0 cmd <- 02 |
| PCI: 00:16.3 subsystem <- 103c/161c |
| PCI: 00:16.3 cmd <- 03 |
| PCI: 00:19.0 subsystem <- 103c/161c |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 103c/161c |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 103c/161c |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 103c/161c |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 103c/161c |
| PCI: 00:1c.1 cmd <- 107 |
| PCI: 00:1c.2 bridge ctrl <- 0003 |
| PCI: 00:1c.2 subsystem <- 103c/161c |
| PCI: 00:1c.2 cmd <- 107 |
| PCI: 00:1c.3 bridge ctrl <- 0003 |
| PCI: 00:1c.3 subsystem <- 103c/161c |
| PCI: 00:1c.3 cmd <- 100 |
| PCI: 00:1c.4 bridge ctrl <- 0003 |
| PCI: 00:1c.4 subsystem <- 8086/1c1c |
| PCI: 00:1c.4 cmd <- 100 |
| PCI: 00:1c.6 bridge ctrl <- 0003 |
| PCI: 00:1c.6 subsystem <- 103c/161c |
| PCI: 00:1c.6 cmd <- 106 |
| PCI: 00:1d.0 subsystem <- 103c/161c |
| PCI: 00:1d.0 cmd <- 102 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 103c/161c |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 103c/161c |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 04:00.0 cmd <- 02 |
| PCI: 04:00.1 cmd <- 06 |
| PCI: 04:00.2 cmd <- 06 |
| PCI: 04:00.3 cmd <- 06 |
| PCI: 04:00.4 cmd <- 06 |
| PCI: 07:00.0 cmd <- 02 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 211 exit 0 |
| Found TPM SLB9635 TT 1.2 by Infineon |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=0, nvlocked=1 |
| TPM: setup succeeded |
| read 6000 from 07e4 |
| wrote 00000004 to 0890 |
| read 03040003 from 0894 |
| wrote 00001000 to 0890 |
| read 24900024 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 0 usecs |
| CPU_CLUSTER: 0 init ... |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000047b600000 size 0x37b600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/5. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0 |
| MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| CPU has 4 cores, 8 threads enabled. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13d40 size 6800 |
| microcode: sig=0x306a9 pf=0x10 revision=0x21 |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 7 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...done. |
| Waiting for 2nd SIPI to complete...AP: slot 1 apic_id 1. |
| done. |
| AP: slot 2 apic_id 5. |
| AP: slot 7 apic_id 7. |
| AP: slot 5 apic_id 3. |
| AP: slot 4 apic_id 4. |
| AP: slot 3 apic_id 2. |
| AP: slot 6 apic_id 6. |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 7ffa3b32(00000000) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 800114bb. filesize: 0x3fd0 memsize: 0x7ff8 |
| Processing 240 relocs. Offset value of 0x80010000 |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x80008000 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at 80006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd |
| SMM Module: stub loaded at 80008000. Will call 800114bb(00000000) |
| Initializing Southbridge SMI... |
| |
| New SMBASE 0x80000000 |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffffc00 |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffff800 |
| In relocation handler: cpu 2 |
| New SMBASE=0x7ffff800 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffff000 |
| In relocation handler: cpu 4 |
| New SMBASE=0x7ffff000 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffff400 |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7fffec00 |
| In relocation handler: cpu 5 |
| New SMBASE=0x7fffec00 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7fffe800 |
| In relocation handler: cpu 6 |
| New SMBASE=0x7fffe800 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7fffe400 |
| In relocation handler: cpu 7 |
| New SMBASE=0x7fffe400 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| apic_id: 0x00 done. |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| Turbo is available but hidden |
| Turbo is available and visible |
| CPU #0 initialized |
| Initializing CPU #1 |
| Initializing CPU #3 |
| Initializing CPU #7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| Enabling cache |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| Enabling cache |
| Enabling cache |
| Initializing CPU #2 |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| Enabling cache |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| Setting up local APIC... |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| Setting up local APIC... |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| Setting up local APIC... |
| apic_id: 0x06 done. |
| apic_id: 0x03 done. |
| apic_id: 0x02 done. |
| apic_id: 0x04 done. |
| VMX status: enabled |
| apic_id: 0x07 done. |
| VMX status: enabled |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| IA32_FEATURE_CONTROL status: locked |
| CPU: platform id 4 |
| VMX status: enabled |
| apic_id: 0x05 IA32_FEATURE_CONTROL status: locked |
| done. |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| IA32_FEATURE_CONTROL status: locked |
| CPU: cpuid(1) 0x306a9 |
| VMX status: enabled |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| IA32_FEATURE_CONTROL status: locked |
| Setting up local APIC... |
| model_x06ax: energy policy set to 6 |
| model_x06ax: energy policy set to 6 |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| model_x06ax: frequency set to 2700 |
| CPU #5 initialized |
| CPU #3 initialized |
| model_x06ax: energy policy set to 6 |
| apic_id: 0x01 done. |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #6 initialized |
| VMX status: enabled |
| model_x06ax: frequency set to 2700 |
| CPU #7 initialized |
| model_x06ax: frequency set to 2700 |
| model_x06ax: energy policy set to 6 |
| CPU #4 initialized |
| IA32_FEATURE_CONTROL status: locked |
| model_x06ax: frequency set to 2700 |
| CPU #2 initialized |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #1 initialized |
| bsp_do_flight_plan done after 93 msecs. |
| Initializing southbridge SMI... |
| SMI_STS: |
| GPE0_STS: GPIO15 GPIO9 GPIO4 |
| ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI4 GPI3 GPI1 |
| TCO_STS: INTRD_DET |
| Locking SMM. |
| CPU_CLUSTER: 0 init finished in 106934 usecs |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG60. |
| Disabling Device 7. |
| Set BIOS_RESET_CPL |
| CPU TDP: 45 Watts |
| PCI: 00:00.0 init finished in 1013 usecs |
| PCI: 00:01.0 init ... |
| PCI: 00:01.0 init finished in 1 usecs |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| [0.180862] HW.GFX.GMA.Initialize |
| [0.180867] HW.GFX.GMA.Panel.Setup_PP_Sequencer |
| [0.180869] HW.GFX.GMA.Registers.Read: 0x012c07d0 <- 0x000c7208:PCH_PP_ON_DELAYS |
| [0.180874] HW.GFX.GMA.Registers.Read: 0x00e607d0 <- 0x000c720c:PCH_PP_OFF_DELAYS |
| [0.180877] HW.GFX.GMA.Registers.Read: 0x00186905 <- 0x000c7210:PCH_PP_DIVISOR |
| [0.180879] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL |
| [0.180881] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL |
| [0.180883] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL |
| [0.180886] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_LVDS |
| [0.180889] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000e1180:PCH_LVDS |
| [0.180891] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB |
| [0.180893] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB |
| [0.180895] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B |
| [0.180897] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4100:PCH_DP_B |
| [0.180899] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL |
| [0.180901] HW.GFX.GMA.Registers.Read: 0x00101010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.180903] HW.GFX.GMA.Registers.Write: 0x00101013 -> 0x000c4030:SHOTPLUG_CTL |
| [0.180906] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC |
| [0.180908] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1150:PCH_HDMIC |
| [0.180910] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C |
| [0.180912] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4200:PCH_DP_C |
| [0.180914] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL |
| [0.180916] HW.GFX.GMA.Registers.Read: 0x00101010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.180918] HW.GFX.GMA.Registers.Write: 0x00101310 -> 0x000c4030:SHOTPLUG_CTL |
| [0.180921] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID |
| [0.180923] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1160:PCH_HDMID |
| [0.180925] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D |
| [0.180927] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4300:PCH_DP_D |
| [0.180929] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL |
| [0.180931] HW.GFX.GMA.Registers.Read: 0x00101010 <- 0x000c4030:SHOTPLUG_CTL |
| [0.180933] HW.GFX.GMA.Registers.Write: 0x00131010 -> 0x000c4030:SHOTPLUG_CTL |
| [0.181038] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL |
| [0.181041] HW.GFX.GMA.Registers.Read: 0x00002900 <- 0x00041000:CPU_VGACNTRL |
| [0.181043] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL |
| [0.181045] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL |
| [0.181049] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL |
| [0.181053] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ |
| [0.181056] HW.GFX.GMA.Registers.Read: 0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ |
| [0.181058] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ |
| [0.181061] HW.GFX.GMA.Panel.On |
| [0.181062] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL |
| [0.181064] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL |
| [0.181066] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL |
| [0.181069] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL |
| [0.181071] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL |
| [0.181074] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.181076] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.181078] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181080] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 |
| [0.181083] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.181085] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181087] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181090] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181523] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181525] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.181527] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181529] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 |
| [0.181532] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.181534] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181536] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181539] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181982] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181984] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.181986] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181988] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 |
| [0.181991] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B |
| [0.181993] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181995] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.181998] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.182430] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B |
| [0.182432] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.182433] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C |
| [0.182435] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182437] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1 |
| [0.182440] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C |
| [0.182442] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182444] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182447] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182892] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182894] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C |
| [0.182896] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182898] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1 |
| [0.182901] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C |
| [0.182903] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182905] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.182908] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183350] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183352] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C |
| [0.183354] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183356] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1 |
| [0.183359] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C |
| [0.183361] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183363] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183366] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183797] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C |
| [0.183799] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.183800] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.183802] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.183804] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 |
| [0.183807] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.183809] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.183811] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.183814] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184248] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184250] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.184252] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184254] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 |
| [0.184257] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.184259] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184261] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184264] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184696] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184698] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.184700] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184702] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 |
| [0.184705] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D |
| [0.184707] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184709] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.184712] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.185150] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D |
| [0.185152] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.185153] HW.GFX.GMA.I2C.I2C_Read |
| [0.185154] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.185155] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.185159] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 |
| [0.185161] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 |
| [0.185164] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.185166] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.185169] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.185172] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.185270] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.185272] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.185273] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.185276] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.185279] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.185280] HW.GFX.GMA.I2C.I2C_Read |
| [0.185281] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.185282] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.185286] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.185288] HW.GFX.GMA.I2C.Reset_GMBUS |
| [0.185289] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.185292] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.185295] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.185298] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2 |
| [0.185300] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0 |
| [0.185303] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.185306] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.185309] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.185312] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.185399] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.185401] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.185402] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.185405] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.185408] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.185409] HW.GFX.GMA.I2C.I2C_Read |
| [0.185410] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.185411] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.185415] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.185417] HW.GFX.GMA.I2C.Reset_GMBUS |
| [0.185418] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.185421] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.185424] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.185427] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2 |
| [0.185429] HW.GFX.GMA.Registers.Write: 0x00000006 -> 0x000c5100:PCH_GMBUS0 |
| [0.185432] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.185435] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.185438] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.185441] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.185536] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.185538] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.185539] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.185542] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.185545] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.185546] HW.GFX.GMA.I2C.I2C_Read |
| [0.185547] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.185548] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.185552] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 |
| [0.185554] HW.GFX.GMA.I2C.Reset_GMBUS |
| [0.185555] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.185558] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.185561] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.185564] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2 |
| [0.185566] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0 |
| [0.185569] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.185572] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.185575] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.185578] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.186041] HW.GFX.GMA.Registers.Read: 0x00008a04 <- 0x000c5108:PCH_GMBUS2 |
| [0.186044] HW.GFX.GMA.Registers.Read: 0xffffff00 <- 0x000c510c:PCH_GMBUS3 |
| [0.186046] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.186294] HW.GFX.GMA.Registers.Read: 0x00008a08 <- 0x000c5108:PCH_GMBUS2 |
| [0.186297] HW.GFX.GMA.Registers.Read: 0x00ffffff <- 0x000c510c:PCH_GMBUS3 |
| [0.186299] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.186544] HW.GFX.GMA.Registers.Read: 0x00008a0c <- 0x000c5108:PCH_GMBUS2 |
| [0.186547] HW.GFX.GMA.Registers.Read: 0x2843f022 <- 0x000c510c:PCH_GMBUS3 |
| [0.186549] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.186787] HW.GFX.GMA.Registers.Read: 0x00008a10 <- 0x000c5108:PCH_GMBUS2 |
| [0.186790] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x000c510c:PCH_GMBUS3 |
| [0.186792] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.187030] HW.GFX.GMA.Registers.Read: 0x00008a14 <- 0x000c5108:PCH_GMBUS2 |
| [0.187033] HW.GFX.GMA.Registers.Read: 0x03011324 <- 0x000c510c:PCH_GMBUS3 |
| [0.187035] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.187273] HW.GFX.GMA.Registers.Read: 0x00008a18 <- 0x000c5108:PCH_GMBUS2 |
| [0.187276] HW.GFX.GMA.Registers.Read: 0x781e2f68 <- 0x000c510c:PCH_GMBUS3 |
| [0.187278] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.187519] HW.GFX.GMA.Registers.Read: 0x00008a1c <- 0x000c5108:PCH_GMBUS2 |
| [0.187522] HW.GFX.GMA.Registers.Read: 0xa530b1ee <- 0x000c510c:PCH_GMBUS3 |
| [0.187524] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.187762] HW.GFX.GMA.Registers.Read: 0x00008a20 <- 0x000c5108:PCH_GMBUS2 |
| [0.187765] HW.GFX.GMA.Registers.Read: 0x259a4a56 <- 0x000c510c:PCH_GMBUS3 |
| [0.187767] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.188007] HW.GFX.GMA.Registers.Read: 0x00008a24 <- 0x000c5108:PCH_GMBUS2 |
| [0.188010] HW.GFX.GMA.Registers.Read: 0xa5545011 <- 0x000c510c:PCH_GMBUS3 |
| [0.188012] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.188254] HW.GFX.GMA.Registers.Read: 0x00008a28 <- 0x000c5108:PCH_GMBUS2 |
| [0.188257] HW.GFX.GMA.Registers.Read: 0x4081f06b <- 0x000c510c:PCH_GMBUS3 |
| [0.188259] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.188497] HW.GFX.GMA.Registers.Read: 0x00008a2c <- 0x000c5108:PCH_GMBUS2 |
| [0.188500] HW.GFX.GMA.Registers.Read: 0x00958081 <- 0x000c510c:PCH_GMBUS3 |
| [0.188502] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.188741] HW.GFX.GMA.Registers.Read: 0x00008a30 <- 0x000c5108:PCH_GMBUS2 |
| [0.188744] HW.GFX.GMA.Registers.Read: 0x00b300a9 <- 0x000c510c:PCH_GMBUS3 |
| [0.188746] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.188984] HW.GFX.GMA.Registers.Read: 0x00008a34 <- 0x000c5108:PCH_GMBUS2 |
| [0.188987] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x000c510c:PCH_GMBUS3 |
| [0.188989] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.189231] HW.GFX.GMA.Registers.Read: 0x00008a38 <- 0x000c5108:PCH_GMBUS2 |
| [0.189234] HW.GFX.GMA.Registers.Read: 0x39210101 <- 0x000c510c:PCH_GMBUS3 |
| [0.189236] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.189475] HW.GFX.GMA.Registers.Read: 0x00008a3c <- 0x000c5108:PCH_GMBUS2 |
| [0.189478] HW.GFX.GMA.Registers.Read: 0x1a623090 <- 0x000c510c:PCH_GMBUS3 |
| [0.189480] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.189729] HW.GFX.GMA.Registers.Read: 0x00008a40 <- 0x000c5108:PCH_GMBUS2 |
| [0.189732] HW.GFX.GMA.Registers.Read: 0xb0684027 <- 0x000c510c:PCH_GMBUS3 |
| [0.189734] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.189972] HW.GFX.GMA.Registers.Read: 0x00008a44 <- 0x000c5108:PCH_GMBUS2 |
| [0.189975] HW.GFX.GMA.Registers.Read: 0x28d90036 <- 0x000c510c:PCH_GMBUS3 |
| [0.189977] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.190215] HW.GFX.GMA.Registers.Read: 0x00008a48 <- 0x000c5108:PCH_GMBUS2 |
| [0.190218] HW.GFX.GMA.Registers.Read: 0x1c000011 <- 0x000c510c:PCH_GMBUS3 |
| [0.190220] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.190459] HW.GFX.GMA.Registers.Read: 0x00008a4c <- 0x000c5108:PCH_GMBUS2 |
| [0.190462] HW.GFX.GMA.Registers.Read: 0xfd000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.190464] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.190702] HW.GFX.GMA.Registers.Read: 0x00008a50 <- 0x000c5108:PCH_GMBUS2 |
| [0.190705] HW.GFX.GMA.Registers.Read: 0x184c3200 <- 0x000c510c:PCH_GMBUS3 |
| [0.190707] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.190949] HW.GFX.GMA.Registers.Read: 0x00008a54 <- 0x000c5108:PCH_GMBUS2 |
| [0.190952] HW.GFX.GMA.Registers.Read: 0x0a001153 <- 0x000c510c:PCH_GMBUS3 |
| [0.190954] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.191193] HW.GFX.GMA.Registers.Read: 0x00008a58 <- 0x000c5108:PCH_GMBUS2 |
| [0.191196] HW.GFX.GMA.Registers.Read: 0x20202020 <- 0x000c510c:PCH_GMBUS3 |
| [0.191198] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.191439] HW.GFX.GMA.Registers.Read: 0x00008a5c <- 0x000c5108:PCH_GMBUS2 |
| [0.191442] HW.GFX.GMA.Registers.Read: 0x00002020 <- 0x000c510c:PCH_GMBUS3 |
| [0.191444] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.191682] HW.GFX.GMA.Registers.Read: 0x00008a60 <- 0x000c5108:PCH_GMBUS2 |
| [0.191685] HW.GFX.GMA.Registers.Read: 0x4800fc00 <- 0x000c510c:PCH_GMBUS3 |
| [0.191687] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.191925] HW.GFX.GMA.Registers.Read: 0x00008a64 <- 0x000c5108:PCH_GMBUS2 |
| [0.191928] HW.GFX.GMA.Registers.Read: 0x454c2050 <- 0x000c510c:PCH_GMBUS3 |
| [0.191930] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.192170] HW.GFX.GMA.Registers.Read: 0x00008a68 <- 0x000c5108:PCH_GMBUS2 |
| [0.192173] HW.GFX.GMA.Registers.Read: 0x31303232 <- 0x000c510c:PCH_GMBUS3 |
| [0.192175] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.192416] HW.GFX.GMA.Registers.Read: 0x00008a6c <- 0x000c5108:PCH_GMBUS2 |
| [0.192419] HW.GFX.GMA.Registers.Read: 0x20200a77 <- 0x000c510c:PCH_GMBUS3 |
| [0.192421] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.192659] HW.GFX.GMA.Registers.Read: 0x00008a70 <- 0x000c5108:PCH_GMBUS2 |
| [0.192662] HW.GFX.GMA.Registers.Read: 0xff000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.192664] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.192904] HW.GFX.GMA.Registers.Read: 0x00008a74 <- 0x000c5108:PCH_GMBUS2 |
| [0.192907] HW.GFX.GMA.Registers.Read: 0x4b4e4300 <- 0x000c510c:PCH_GMBUS3 |
| [0.192909] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.193150] HW.GFX.GMA.Registers.Read: 0x00008a78 <- 0x000c5108:PCH_GMBUS2 |
| [0.193153] HW.GFX.GMA.Registers.Read: 0x31363339 <- 0x000c510c:PCH_GMBUS3 |
| [0.193155] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.193393] HW.GFX.GMA.Registers.Read: 0x00008a7c <- 0x000c5108:PCH_GMBUS2 |
| [0.193396] HW.GFX.GMA.Registers.Read: 0x0a303336 <- 0x000c510c:PCH_GMBUS3 |
| [0.193398] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.193637] HW.GFX.GMA.Registers.Read: 0x0000ca80 <- 0x000c5108:PCH_GMBUS2 |
| [0.193640] HW.GFX.GMA.Registers.Read: 0x46002020 <- 0x000c510c:PCH_GMBUS3 |
| [0.193642] HW.GFX.GMA.Registers.Wait: 0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2 |
| [0.193645] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.193648] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 |
| [0.193665] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.193667] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.193670] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.193673] EDID+0x0000: 00 ff ff ff ff ff ff 00 22 f0 43 28 01 01 01 01 |
| [0.193677] EDID+0x0010: 24 13 01 03 68 2f 1e 78 ee b1 30 a5 56 4a 9a 25 |
| [0.193681] EDID+0x0020: 11 50 54 a5 6b f0 81 40 81 80 95 00 a9 00 b3 00 |
| [0.193685] EDID+0x0030: 01 01 01 01 01 01 21 39 90 30 62 1a 27 40 68 b0 |
| [0.193688] EDID+0x0040: 36 00 d9 28 11 00 00 1c 00 00 00 fd 00 32 4c 18 |
| [0.193691] EDID+0x0050: 53 11 00 0a 20 20 20 20 20 20 00 00 00 fc 00 48 |
| [0.193694] EDID+0x0060: 50 20 4c 45 32 32 30 31 77 0a 20 20 00 00 00 ff |
| [0.193697] EDID+0x0070: 00 43 4e 4b 39 33 36 31 36 33 30 0a 20 20 00 46 |
| [0.193701] HW.GFX.GMA.Panel.Wait_On |
| [0.211075] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS |
| [0.211079] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL |
| [0.211082] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL |
| [0.211084] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL |
| [0.211087] HW.GFX.GMA.Display_Probing.Read_EDID |
| [0.211088] HW.GFX.GMA.I2C.I2C_Read |
| [0.211089] HW.GFX.GMA.I2C.Init_GMBUS |
| [0.211090] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 |
| [0.211094] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 |
| [0.211096] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c5100:PCH_GMBUS0 |
| [0.211098] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 |
| [0.211101] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 |
| [0.211104] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 |
| [0.211107] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.211572] HW.GFX.GMA.Registers.Read: 0x00008a04 <- 0x000c5108:PCH_GMBUS2 |
| [0.211575] HW.GFX.GMA.Registers.Read: 0xffffff00 <- 0x000c510c:PCH_GMBUS3 |
| [0.211577] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.211822] HW.GFX.GMA.Registers.Read: 0x00008a08 <- 0x000c5108:PCH_GMBUS2 |
| [0.211825] HW.GFX.GMA.Registers.Read: 0x00ffffff <- 0x000c510c:PCH_GMBUS3 |
| [0.211827] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.212065] HW.GFX.GMA.Registers.Read: 0x00008a0c <- 0x000c5108:PCH_GMBUS2 |
| [0.212068] HW.GFX.GMA.Registers.Read: 0x0306e430 <- 0x000c510c:PCH_GMBUS3 |
| [0.212070] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.212308] HW.GFX.GMA.Registers.Read: 0x00008a10 <- 0x000c5108:PCH_GMBUS2 |
| [0.212311] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.212313] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.212552] HW.GFX.GMA.Registers.Read: 0x00008a14 <- 0x000c5108:PCH_GMBUS2 |
| [0.212555] HW.GFX.GMA.Registers.Read: 0x04011400 <- 0x000c510c:PCH_GMBUS3 |
| [0.212557] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.212804] HW.GFX.GMA.Registers.Read: 0x00008a18 <- 0x000c5108:PCH_GMBUS2 |
| [0.212807] HW.GFX.GMA.Registers.Read: 0x78111f90 <- 0x000c510c:PCH_GMBUS3 |
| [0.212809] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.213047] HW.GFX.GMA.Registers.Read: 0x00008a1c <- 0x000c5108:PCH_GMBUS2 |
| [0.213050] HW.GFX.GMA.Registers.Read: 0x97454302 <- 0x000c510c:PCH_GMBUS3 |
| [0.213052] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.213291] HW.GFX.GMA.Registers.Read: 0x00008a20 <- 0x000c5108:PCH_GMBUS2 |
| [0.213294] HW.GFX.GMA.Registers.Read: 0x288e5759 <- 0x000c510c:PCH_GMBUS3 |
| [0.213296] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.213549] HW.GFX.GMA.Registers.Read: 0x00008a24 <- 0x000c5108:PCH_GMBUS2 |
| [0.213552] HW.GFX.GMA.Registers.Read: 0x00545021 <- 0x000c510c:PCH_GMBUS3 |
| [0.213554] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.213792] HW.GFX.GMA.Registers.Read: 0x00008a28 <- 0x000c5108:PCH_GMBUS2 |
| [0.213795] HW.GFX.GMA.Registers.Read: 0x01010000 <- 0x000c510c:PCH_GMBUS3 |
| [0.213797] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.214036] HW.GFX.GMA.Registers.Read: 0x00008a2c <- 0x000c5108:PCH_GMBUS2 |
| [0.214039] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x000c510c:PCH_GMBUS3 |
| [0.214041] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.214281] HW.GFX.GMA.Registers.Read: 0x00008a30 <- 0x000c5108:PCH_GMBUS2 |
| [0.214284] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x000c510c:PCH_GMBUS3 |
| [0.214286] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.214524] HW.GFX.GMA.Registers.Read: 0x00008a34 <- 0x000c5108:PCH_GMBUS2 |
| [0.214527] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x000c510c:PCH_GMBUS3 |
| [0.214529] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.214776] HW.GFX.GMA.Registers.Read: 0x00008a38 <- 0x000c5108:PCH_GMBUS2 |
| [0.214779] HW.GFX.GMA.Registers.Read: 0x2fa80101 <- 0x000c510c:PCH_GMBUS3 |
| [0.214781] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.215020] HW.GFX.GMA.Registers.Read: 0x00008a3c <- 0x000c5108:PCH_GMBUS2 |
| [0.215023] HW.GFX.GMA.Registers.Read: 0x84624040 <- 0x000c510c:PCH_GMBUS3 |
| [0.215025] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.215270] HW.GFX.GMA.Registers.Read: 0x00008a40 <- 0x000c5108:PCH_GMBUS2 |
| [0.215273] HW.GFX.GMA.Registers.Read: 0x60a03024 <- 0x000c510c:PCH_GMBUS3 |
| [0.215275] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.215517] HW.GFX.GMA.Registers.Read: 0x00008a44 <- 0x000c5108:PCH_GMBUS2 |
| [0.215520] HW.GFX.GMA.Registers.Read: 0xae360035 <- 0x000c510c:PCH_GMBUS3 |
| [0.215522] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.215761] HW.GFX.GMA.Registers.Read: 0x00008a48 <- 0x000c5108:PCH_GMBUS2 |
| [0.215764] HW.GFX.GMA.Registers.Read: 0x19000010 <- 0x000c510c:PCH_GMBUS3 |
| [0.215766] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.216006] HW.GFX.GMA.Registers.Read: 0x00008a4c <- 0x000c5108:PCH_GMBUS2 |
| [0.216009] HW.GFX.GMA.Registers.Read: 0x40401fc5 <- 0x000c510c:PCH_GMBUS3 |
| [0.216011] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.216262] HW.GFX.GMA.Registers.Read: 0x00008a50 <- 0x000c5108:PCH_GMBUS2 |
| [0.216265] HW.GFX.GMA.Registers.Read: 0x30248462 <- 0x000c510c:PCH_GMBUS3 |
| [0.216267] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.216506] HW.GFX.GMA.Registers.Read: 0x00008a54 <- 0x000c5108:PCH_GMBUS2 |
| [0.216509] HW.GFX.GMA.Registers.Read: 0x003560a0 <- 0x000c510c:PCH_GMBUS3 |
| [0.216511] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.216750] HW.GFX.GMA.Registers.Read: 0x00008a58 <- 0x000c5108:PCH_GMBUS2 |
| [0.216753] HW.GFX.GMA.Registers.Read: 0x0010ae36 <- 0x000c510c:PCH_GMBUS3 |
| [0.216755] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.216996] HW.GFX.GMA.Registers.Read: 0x00008a5c <- 0x000c5108:PCH_GMBUS2 |
| [0.216999] HW.GFX.GMA.Registers.Read: 0x00001900 <- 0x000c510c:PCH_GMBUS3 |
| [0.217001] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.217239] HW.GFX.GMA.Registers.Read: 0x00008a60 <- 0x000c5108:PCH_GMBUS2 |
| [0.217242] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.217244] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.217493] HW.GFX.GMA.Registers.Read: 0x00008a64 <- 0x000c5108:PCH_GMBUS2 |
| [0.217496] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.217498] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.217739] HW.GFX.GMA.Registers.Read: 0x00008a68 <- 0x000c5108:PCH_GMBUS2 |
| [0.217742] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.217744] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.217982] HW.GFX.GMA.Registers.Read: 0x00008a6c <- 0x000c5108:PCH_GMBUS2 |
| [0.217985] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.217987] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.218225] HW.GFX.GMA.Registers.Read: 0x00008a70 <- 0x000c5108:PCH_GMBUS2 |
| [0.218228] HW.GFX.GMA.Registers.Read: 0x02000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.218230] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.218471] HW.GFX.GMA.Registers.Read: 0x00008a74 <- 0x000c5108:PCH_GMBUS2 |
| [0.218474] HW.GFX.GMA.Registers.Read: 0xff3a0a00 <- 0x000c510c:PCH_GMBUS3 |
| [0.218476] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.218714] HW.GFX.GMA.Registers.Read: 0x00008a78 <- 0x000c5108:PCH_GMBUS2 |
| [0.218717] HW.GFX.GMA.Registers.Read: 0x197d3c0a <- 0x000c510c:PCH_GMBUS3 |
| [0.218719] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.218957] HW.GFX.GMA.Registers.Read: 0x00008a7c <- 0x000c5108:PCH_GMBUS2 |
| [0.218960] HW.GFX.GMA.Registers.Read: 0x007d331b <- 0x000c510c:PCH_GMBUS3 |
| [0.218962] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 |
| [0.219202] HW.GFX.GMA.Registers.Read: 0x0000ca80 <- 0x000c5108:PCH_GMBUS2 |
| [0.219205] HW.GFX.GMA.Registers.Read: 0x9d000000 <- 0x000c510c:PCH_GMBUS3 |
| [0.219207] HW.GFX.GMA.Registers.Wait: 0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2 |
| [0.219211] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1 |
| [0.219214] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 |
| [0.219238] HW.GFX.GMA.I2C.Release_GMBUS |
| [0.219239] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 |
| [0.219242] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 |
| [0.219245] EDID+0x0000: 00 ff ff ff ff ff ff 00 30 e4 06 03 00 00 00 00 |
| [0.219248] EDID+0x0010: 00 14 01 04 90 1f 11 78 02 43 45 97 59 57 8e 28 |
| [0.219252] EDID+0x0020: 21 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 |
| [0.219255] EDID+0x0030: 01 01 01 01 01 01 a8 2f 40 40 62 84 24 30 a0 60 |
| [0.219258] EDID+0x0040: 35 00 36 ae 10 00 00 19 c5 1f 40 40 62 84 24 30 |
| [0.219262] EDID+0x0050: a0 60 35 00 36 ae 10 00 00 19 00 00 00 00 00 00 |
| [0.219265] EDID+0x0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 |
| [0.219268] EDID+0x0070: 00 0a 3a ff 0a 3c 7d 19 1b 33 7d 00 00 00 00 9d |
| |
| [0.219273] CONFIG => |
| [0.219274] (Primary => |
| [0.219275] (Port => Analog , |
| [0.219276] Framebuffer => |
| [0.219277] (Width => 1600, |
| [0.219278] Height => 900, |
| [0.219279] Start_X => 0, |
| [0.219280] Start_Y => 0, |
| [0.219281] Stride => 1600, |
| [0.219282] V_Stride => 900, |
| [0.219283] Tiling => Linear , |
| [0.219284] Rotation => No_Rotation, |
| [0.219285] Offset => 0x00000000, |
| [0.219286] BPC => 8), |
| [0.219287] Mode => |
| [0.219287] (Dotclock => 146250000, |
| [0.219289] H_Visible => 1680, |
| [0.219290] H_Sync_Begin => 1784, |
| [0.219291] H_Sync_End => 1960, |
| [0.219292] H_Total => 2240, |
| [0.219293] V_Visible => 1050, |
| [0.219294] V_Sync_Begin => 1053, |
| [0.219295] V_Sync_End => 1059, |
| [0.219296] V_Total => 1089, |
| [0.219297] H_Sync_Active_High => False, |
| [0.219298] V_Sync_Active_High => True, |
| [0.219299] BPC => 5)), |
| [0.219300] Secondary => |
| [0.219301] (Port => Internal, |
| [0.219302] Framebuffer => |
| [0.219303] (Width => 1600, |
| [0.219304] Height => 900, |
| [0.219305] Start_X => 0, |
| [0.219306] Start_Y => 0, |
| [0.219307] Stride => 1600, |
| [0.219308] V_Stride => 900, |
| [0.219309] Tiling => Linear , |
| [0.219310] Rotation => No_Rotation, |
| [0.219311] Offset => 0x00000000, |
| [0.219312] BPC => 8), |
| [0.219313] Mode => |
| [0.219313] (Dotclock => 122000000, |
| [0.219315] H_Visible => 1600, |
| [0.219316] H_Sync_Begin => 1760, |
| [0.219317] H_Sync_End => 1856, |
| [0.219318] H_Total => 2176, |
| [0.219319] V_Visible => 900, |
| [0.219320] V_Sync_Begin => 903, |
| [0.219321] V_Sync_End => 908, |
| [0.219322] V_Total => 936, |
| [0.219323] H_Sync_Active_High => False, |
| [0.219324] V_Sync_Active_High => False, |
| [0.219325] BPC => 6)), |
| [0.219326] Tertiary => |
| [0.219327] (Port => Disabled, |
| [0.219328] Framebuffer => |
| [0.219329] (Width => 1, |
| [0.219330] Height => 1, |
| [0.219331] Start_X => 0, |
| [0.219332] Start_Y => 0, |
| [0.219333] Stride => 1, |
| [0.219334] V_Stride => 1, |
| [0.219335] Tiling => Linear , |
| [0.219336] Rotation => No_Rotation, |
| [0.219337] Offset => 0x00000000, |
| [0.219338] BPC => 8), |
| [0.219339] Mode => |
| [0.219339] (Dotclock => 19200000, |
| [0.219341] H_Visible => 1, |
| [0.219342] H_Sync_Begin => 1, |
| [0.219343] H_Sync_End => 1, |
| [0.219344] H_Total => 1, |
| [0.219345] V_Visible => 1, |
| [0.219346] V_Sync_Begin => 1, |
| [0.219347] V_Sync_End => 1, |
| [0.219348] V_Total => 1, |
| [0.219349] H_Sync_Active_High => False, |
| [0.219350] V_Sync_Active_High => False, |
| [0.219351] BPC => 5))); |
| |
| [0.220971] Trying to enable port Analog |
| [0.220973] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting |
| [0.220974] HW.GFX.GMA.PLLs.Alloc |
| [0.220975] HW.GFX.GMA.PLLs.On |
| [0.221084] Valid clock found. |
| [0.221085] Best/Target/Delta: 146400000/146250000/150000. |
| [0.221087] HW.GFX.GMA.PLLs.Program_DPLL |
| [0.221088] HW.GFX.GMA.Registers.Write: 0x00031505 -> 0x000c6040:PCH_FPA0 |
| [0.221091] HW.GFX.GMA.Registers.Write: 0x00031505 -> 0x000c6044:PCH_FPA1 |
| [0.221094] HW.GFX.GMA.Registers.Write: 0x44020002 -> 0x000c6014:PCH_DPLL_A |
| [0.221097] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DPLL_A |
| [0.221100] HW.GFX.GMA.Registers.Read: 0x44020002 <- 0x000c6014:PCH_DPLL_A |
| [0.221102] HW.GFX.GMA.Registers.Write: 0xc4020002 -> 0x000c6014:PCH_DPLL_A |
| [0.221106] HW.GFX.GMA.Registers.Read: 0xc4020002 <- 0x000c6014:PCH_DPLL_A |
| [0.221259] HW.GFX.GMA.Connectors.Pre_On |
| [0.221260] HW.GFX.GMA.Connectors.FDI.Pre_On |
| [0.221261] HW.GFX.GMA.Registers.Write: 0x00200090 -> 0x000f0010:FDI_RX_MISC_A |
| [0.221264] HW.GFX.GMA.Registers.Write: 0x7e000000 -> 0x000f0030:FDI_RXA_TUSIZE1 |
| [0.221267] HW.GFX.GMA.Registers.Unset_Mask: 0x00000700 !S FDI_RXA_IMR |
| [0.221270] HW.GFX.GMA.Registers.Read: 0x00000fff <- 0x000f0018:FDI_RXA_IMR |
| [0.221272] HW.GFX.GMA.Registers.Write: 0x000008ff -> 0x000f0018:FDI_RXA_IMR |
| [0.221275] HW.GFX.GMA.Registers.Read: 0x000008ff <- 0x000f0018:FDI_RXA_IMR |
| [0.221277] HW.GFX.GMA.Registers.Write: 0x00000700 -> 0x000f0014:FDI_RXA_IIR |
| [0.221280] HW.GFX.GMA.Registers.Write: 0x00082840 -> 0x000f000c:FDI_RXA_CTL |
| [0.221284] HW.GFX.GMA.Registers.Read: 0x00082840 <- 0x000f000c:FDI_RXA_CTL |
| [0.221507] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S FDI_RXA_CTL |
| [0.221510] HW.GFX.GMA.Registers.Read: 0x00082840 <- 0x000f000c:FDI_RXA_CTL |
| [0.221512] HW.GFX.GMA.Registers.Write: 0x00082850 -> 0x000f000c:FDI_RXA_CTL |
| [0.221515] HW.GFX.GMA.Registers.Write: 0x000c4800 -> 0x00060100:FDI_TX_CTL_A |
| [0.221518] HW.GFX.GMA.Registers.Read: 0x000c4800 <- 0x00060100:FDI_TX_CTL_A |
| [0.221621] HW.GFX.GMA.Pipe_Setup.On |
| [0.221622] HW.GFX.GMA.Transcoder.Setup |
| [0.221623] HW.GFX.GMA.Transcoder.Setup_Link |
| [0.221624] HW.GFX.GMA.DP_Info.Calculate_M_N |
| [0.221625] HW.GFX.GMA.Registers.Write: 0x7e680000 -> 0x00060030:PIPEA_DATA_M1 |
| [0.221627] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x00060034:PIPEA_DATA_N1 |
| [0.221629] HW.GFX.GMA.Registers.Write: 0x0008aaaa -> 0x00060040:PIPEA_LINK_M1 |
| [0.221631] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x00060044:PIPEA_LINK_N1 |
| [0.221633] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x00060000:HTOTAL_A |
| [0.221635] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x00060004:HBLANK_A |
| [0.221637] HW.GFX.GMA.Registers.Write: 0x07a706f7 -> 0x00060008:HSYNC_A |
| [0.221639] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x0006000c:VTOTAL_A |
| [0.221641] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x00060010:VBLANK_A |
| [0.221643] HW.GFX.GMA.Registers.Write: 0x0422041c -> 0x00060014:VSYNC_A |
| [0.221645] HW.GFX.GMA.Pipe_Setup.Setup_FB |
| [0.221646] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A |
| [0.221649] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A |
| [0.221651] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A |
| [0.221653] HW.GFX.GMA.Pipe_Setup.Setup_Display |
| [0.221654] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane |
| [0.221655] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DSPACNTR |
| [0.221657] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070180:DSPACNTR |
| [0.221659] HW.GFX.GMA.Registers.Write: 0x98004000 -> 0x00070180:DSPACNTR |
| [0.221661] HW.GFX.GMA.Registers.Write: 0x00001900 -> 0x00070188:DSPASTRIDE |
| [0.221663] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070184:DSPALINOFF |
| [0.221665] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF |
| [0.221667] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF |
| [0.221669] HW.GFX.GMA.Registers.Write: 0x063f0383 -> 0x0006001c:PIPEASRC |
| [0.221671] HW.GFX.GMA.Registers.Write: 0x80800000 -> 0x00068080:PFA_CTL_1 |
| [0.221674] HW.GFX.GMA.Registers.Write: 0x00000034 -> 0x00068070:PFA_WIN_POS |
| [0.221676] HW.GFX.GMA.Registers.Write: 0x069003b2 -> 0x00068074:PFA_WIN_SZ |
| [0.221678] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A |
| [0.221680] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A |
| [0.221682] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A |
| [0.221684] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00070008:PIPEACONF |
| [0.221686] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00070008:PIPEACONF |
| [0.221688] HW.GFX.GMA.Connectors.Post_On |
| [0.221689] HW.GFX.GMA.Connectors.FDI.Post_On |
| [0.221690] HW.GFX.GMA.Connectors.FDI.Auto_Training |
| [0.221691] HW.GFX.GMA.Registers.Unset_And_Set_Mask: FDI_TX_CTL_A |
| [0.221692] HW.GFX.GMA.Registers.Read: 0x000c4800 <- 0x00060100:FDI_TX_CTL_A |
| [0.221694] HW.GFX.GMA.Registers.Write: 0x800c4c00 -> 0x00060100:FDI_TX_CTL_A |
| [0.221696] HW.GFX.GMA.Registers.Read: 0x800c4c00 <- 0x00060100:FDI_TX_CTL_A |
| [0.221698] HW.GFX.GMA.Registers.Set_Mask: 0x80000400 .S FDI_RXA_CTL |
| [0.221701] HW.GFX.GMA.Registers.Read: 0x00082850 <- 0x000f000c:FDI_RXA_CTL |
| [0.221703] HW.GFX.GMA.Registers.Write: 0x80082c50 -> 0x000f000c:FDI_RXA_CTL |
| [0.221707] HW.GFX.GMA.Registers.Read: 0x80082c50 <- 0x000f000c:FDI_RXA_CTL |
| [0.221715] HW.GFX.GMA.Registers.Is_Set_Mask: FDI_TX_CTL_A |
| [0.221716] HW.GFX.GMA.Registers.Read: 0x800c4c02 <- 0x00060100:FDI_TX_CTL_A |
| [0.221718] HW.GFX.GMA.Registers.Set_Mask: 0x0c000000 .S FDI_RXA_CTL |
| [0.221721] HW.GFX.GMA.Registers.Read: 0x80082c50 <- 0x000f000c:FDI_RXA_CTL |
| [0.221723] HW.GFX.GMA.Registers.Write: 0x8c082c50 -> 0x000f000c:FDI_RXA_CTL |
| [0.221726] HW.GFX.GMA.PCH.Transcoder.On |
| [0.221727] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DPLL_SEL |
| [0.221729] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7000:PCH_DPLL_SEL |
| [0.221731] HW.GFX.GMA.Registers.Write: 0x00000008 -> 0x000c7000:PCH_DPLL_SEL |
| [0.221734] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x000e0000:TRANS_HTOTAL_A |
| [0.221737] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x000e0004:TRANS_HBLANK_A |
| [0.221740] HW.GFX.GMA.Registers.Write: 0x07a706f7 -> 0x000e0008:TRANS_HSYNC_A |
| [0.221743] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x000e000c:TRANS_VTOTAL_A |
| [0.221746] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x000e0010:TRANS_VBLANK_A |
| [0.221749] HW.GFX.GMA.Registers.Write: 0x0422041c -> 0x000e0014:TRANS_VSYNC_A |
| [0.221752] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S TRANSA_CHICKEN2 |
| [0.221755] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000f0064:TRANSA_CHICKEN2 |
| [0.221757] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0064:TRANSA_CHICKEN2 |
| [0.221760] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f0008:TRANSACONF |
| [0.221763] HW.GFX.GMA.PCH.VGA.On |
| [0.221764] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_ADPA |
| [0.221766] HW.GFX.GMA.Registers.Read: 0x00040000 <- 0x000e1100:PCH_ADPA |
| [0.221768] HW.GFX.GMA.Registers.Write: 0x80040010 -> 0x000e1100:PCH_ADPA |
| [0.221771] Enabled port Analog |
| |
| [0.221772] Trying to enable port Internal |
| [0.221773] HW.GFX.GMA.Registers.Is_Set_Mask: FDI_TX_CTL_C |
| [0.221774] HW.GFX.GMA.Registers.Read: 0x00040000 <- 0x00062100:FDI_TX_CTL_C |
| [0.221776] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting |
| [0.221777] HW.GFX.GMA.PLLs.Alloc |
| [0.221778] HW.GFX.GMA.PLLs.On |
| [0.221837] Valid clock found. |
| [0.221838] Best/Target/Delta: 122142857/122000000/142857. |
| [0.221840] HW.GFX.GMA.PLLs.Program_DPLL |
| [0.221841] HW.GFX.GMA.Registers.Write: 0x00021307 -> 0x000c6048:PCH_FPB0 |
| [0.221844] HW.GFX.GMA.Registers.Write: 0x00021307 -> 0x000c604c:PCH_FPB1 |
| [0.221847] HW.GFX.GMA.Registers.Write: 0x09086008 -> 0x000c6018:PCH_DPLL_B |
| [0.221850] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DPLL_B |
| [0.221853] HW.GFX.GMA.Registers.Read: 0x09086008 <- 0x000c6018:PCH_DPLL_B |
| [0.221855] HW.GFX.GMA.Registers.Write: 0x89086008 -> 0x000c6018:PCH_DPLL_B |
| [0.221859] HW.GFX.GMA.Registers.Read: 0x89086008 <- 0x000c6018:PCH_DPLL_B |
| [0.222012] HW.GFX.GMA.Connectors.Pre_On |
| [0.222013] HW.GFX.GMA.Connectors.FDI.Pre_On |
| [0.222014] HW.GFX.GMA.Registers.Set_Mask: 0x00001000 .S PCH_FDI_CHICKEN_B_C |
| [0.222017] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2000:PCH_FDI_CHICKEN_B_C |
| [0.222019] HW.GFX.GMA.Registers.Write: 0x00001000 -> 0x000c2000:PCH_FDI_CHICKEN_B_C |
| [0.222022] HW.GFX.GMA.Registers.Write: 0x00200090 -> 0x000f1010:FDI_RX_MISC_B |
| [0.222025] HW.GFX.GMA.Registers.Write: 0x7e000000 -> 0x000f1030:FDI_RXB_TUSIZE1 |
| [0.222028] HW.GFX.GMA.Registers.Unset_Mask: 0x00000700 !S FDI_RXB_IMR |
| [0.222031] HW.GFX.GMA.Registers.Read: 0x00000fff <- 0x000f1018:FDI_RXB_IMR |
| [0.222033] HW.GFX.GMA.Registers.Write: 0x000008ff -> 0x000f1018:FDI_RXB_IMR |
| [0.222036] HW.GFX.GMA.Registers.Read: 0x000008ff <- 0x000f1018:FDI_RXB_IMR |
| [0.222038] HW.GFX.GMA.Registers.Write: 0x00000700 -> 0x000f1014:FDI_RXB_IIR |
| [0.222041] HW.GFX.GMA.Registers.Write: 0x000a2840 -> 0x000f100c:FDI_RXB_CTL |
| [0.222045] HW.GFX.GMA.Registers.Read: 0x000a2840 <- 0x000f100c:FDI_RXB_CTL |
| [0.222268] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S FDI_RXB_CTL |
| [0.222271] HW.GFX.GMA.Registers.Read: 0x000a2840 <- 0x000f100c:FDI_RXB_CTL |
| [0.222273] HW.GFX.GMA.Registers.Write: 0x000a2850 -> 0x000f100c:FDI_RXB_CTL |
| [0.222276] HW.GFX.GMA.Registers.Write: 0x000c4800 -> 0x00061100:FDI_TX_CTL_B |
| [0.222278] HW.GFX.GMA.Registers.Read: 0x000c4800 <- 0x00061100:FDI_TX_CTL_B |
| [0.222381] HW.GFX.GMA.Pipe_Setup.On |
| [0.222382] HW.GFX.GMA.Transcoder.Setup |
| [0.222383] HW.GFX.GMA.Transcoder.Setup_Link |
| [0.222384] HW.GFX.GMA.DP_Info.Calculate_M_N |
| [0.222385] HW.GFX.GMA.Registers.Write: 0x7e411111 -> 0x00061030:PIPEB_DATA_M1 |
| [0.222387] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x00061034:PIPEB_DATA_N1 |
| [0.222389] HW.GFX.GMA.Registers.Write: 0x00073ac9 -> 0x00061040:PIPEB_LINK_M1 |
| [0.222391] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x00061044:PIPEB_LINK_N1 |
| [0.222393] HW.GFX.GMA.Registers.Write: 0x087f063f -> 0x00061000:HTOTAL_B |
| [0.222395] HW.GFX.GMA.Registers.Write: 0x087f063f -> 0x00061004:HBLANK_B |
| [0.222397] HW.GFX.GMA.Registers.Write: 0x073f06df -> 0x00061008:HSYNC_B |
| [0.222399] HW.GFX.GMA.Registers.Write: 0x03a70383 -> 0x0006100c:VTOTAL_B |
| [0.222401] HW.GFX.GMA.Registers.Write: 0x03a70383 -> 0x00061010:VBLANK_B |
| [0.222403] HW.GFX.GMA.Registers.Write: 0x038b0386 -> 0x00061014:VSYNC_B |
| [0.222405] HW.GFX.GMA.Pipe_Setup.Setup_FB |
| [0.222406] HW.GFX.GMA.Registers.Write: 0x10000000 -> 0x00071080:CUR_CTL_B |
| [0.222408] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00071088:CUR_POS_B |
| [0.222410] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071084:CUR_BASE_B |
| [0.222412] HW.GFX.GMA.Pipe_Setup.Setup_Display |
| [0.222413] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane |
| [0.222414] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DSPBCNTR |
| [0.222415] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071180:DSPBCNTR |
| [0.222417] HW.GFX.GMA.Registers.Write: 0x98004000 -> 0x00071180:DSPBCNTR |
| [0.222419] HW.GFX.GMA.Registers.Write: 0x00001900 -> 0x00071188:DSPBSTRIDE |
| [0.222421] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071184:DSPBLINOFF |
| [0.222423] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000711a4:DSPBTILEOFF |
| [0.222425] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007119c:DSPBSURF |
| [0.222427] HW.GFX.GMA.Registers.Write: 0x063f0383 -> 0x0006101c:PIPEBSRC |
| [0.222429] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PFB_CTL_1 |
| [0.222431] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068880:PFB_CTL_1 |
| [0.222433] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068880:PFB_CTL_1 |
| [0.222435] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068874:PFB_WIN_SZ |
| [0.222437] HW.GFX.GMA.Registers.Write: 0x10000000 -> 0x00071080:CUR_CTL_B |
| [0.222439] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00071088:CUR_POS_B |
| [0.222441] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071084:CUR_BASE_B |
| [0.222443] HW.GFX.GMA.Registers.Write: 0x80000050 -> 0x00071008:PIPEBCONF |
| [0.222445] HW.GFX.GMA.Registers.Read: 0xc0000050 <- 0x00071008:PIPEBCONF |
| [0.222447] HW.GFX.GMA.Connectors.Post_On |
| [0.222448] HW.GFX.GMA.Connectors.FDI.Post_On |
| [0.222449] HW.GFX.GMA.Connectors.FDI.Auto_Training |
| [0.222450] HW.GFX.GMA.Registers.Unset_And_Set_Mask: FDI_TX_CTL_B |
| [0.222451] HW.GFX.GMA.Registers.Read: 0x000c4800 <- 0x00061100:FDI_TX_CTL_B |
| [0.222453] HW.GFX.GMA.Registers.Write: 0x800c4c00 -> 0x00061100:FDI_TX_CTL_B |
| [0.222455] HW.GFX.GMA.Registers.Read: 0x800c4c00 <- 0x00061100:FDI_TX_CTL_B |
| [0.222457] HW.GFX.GMA.Registers.Set_Mask: 0x80000400 .S FDI_RXB_CTL |
| [0.222460] HW.GFX.GMA.Registers.Read: 0x000a2850 <- 0x000f100c:FDI_RXB_CTL |
| [0.222462] HW.GFX.GMA.Registers.Write: 0x800a2c50 -> 0x000f100c:FDI_RXB_CTL |
| [0.222466] HW.GFX.GMA.Registers.Read: 0x800a2c50 <- 0x000f100c:FDI_RXB_CTL |
| [0.222474] HW.GFX.GMA.Registers.Is_Set_Mask: FDI_TX_CTL_B |
| [0.222475] HW.GFX.GMA.Registers.Read: 0x800c4c02 <- 0x00061100:FDI_TX_CTL_B |
| [0.222477] HW.GFX.GMA.Registers.Set_Mask: 0x0c000000 .S FDI_RXB_CTL |
| [0.222480] HW.GFX.GMA.Registers.Read: 0x800a2c50 <- 0x000f100c:FDI_RXB_CTL |
| [0.222482] HW.GFX.GMA.Registers.Write: 0x8c0a2c50 -> 0x000f100c:FDI_RXB_CTL |
| [0.222485] HW.GFX.GMA.PCH.Transcoder.On |
| [0.222486] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DPLL_SEL |
| [0.222488] HW.GFX.GMA.Registers.Read: 0x00000008 <- 0x000c7000:PCH_DPLL_SEL |
| [0.222490] HW.GFX.GMA.Registers.Write: 0x00000098 -> 0x000c7000:PCH_DPLL_SEL |
| [0.222493] HW.GFX.GMA.Registers.Write: 0x087f063f -> 0x000e1000:TRANS_HTOTAL_B |
| [0.222496] HW.GFX.GMA.Registers.Write: 0x087f063f -> 0x000e1004:TRANS_HBLANK_B |
| [0.222499] HW.GFX.GMA.Registers.Write: 0x073f06df -> 0x000e1008:TRANS_HSYNC_B |
| [0.222502] HW.GFX.GMA.Registers.Write: 0x03a70383 -> 0x000e100c:TRANS_VTOTAL_B |
| [0.222505] HW.GFX.GMA.Registers.Write: 0x03a70383 -> 0x000e1010:TRANS_VBLANK_B |
| [0.222508] HW.GFX.GMA.Registers.Write: 0x038b0386 -> 0x000e1014:TRANS_VSYNC_B |
| [0.222511] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S TRANSB_CHICKEN2 |
| [0.222514] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000f1064:TRANSB_CHICKEN2 |
| [0.222516] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f1064:TRANSB_CHICKEN2 |
| [0.222519] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000f1008:TRANSBCONF |
| [0.222522] HW.GFX.GMA.PCH.LVDS.On |
| [0.222523] HW.GFX.GMA.Registers.Write: 0xa030033c -> 0x000e1180:PCH_LVDS |
| [0.222526] HW.GFX.GMA.Panel.On |
| [0.222527] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL |
| [0.222529] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL |
| [0.222531] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL |
| [0.222534] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL |
| [0.222536] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL |
| [0.222539] HW.GFX.GMA.Panel.Backlight_On |
| [0.222540] HW.GFX.GMA.Registers.Set_Mask: 0x00000004 .S PCH_PP_CONTROL |
| [0.222543] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL |
| [0.222545] HW.GFX.GMA.Registers.Write: 0xabcd0007 -> 0x000c7204:PCH_PP_CONTROL |
| [0.222548] Enabled port Internal |
| PCI: 00:02.0 init finished in 42137 usecs |
| PCI: 00:04.0 init ... |
| PCI: 00:04.0 init finished in 1 usecs |
| PCI: 00:16.0 init ... |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : M0 with UMA |
| ME: Current Operation Mode : Normal |
| ME: Error Code : Image Failure |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : M0 kernel load |
| ME: BIOS path: Error |
| PCI: 00:16.0 init finished in 35 usecs |
| PCI: 00:16.3 init ... |
| PCI: 00:16.3 init finished in 1 usecs |
| PCI: 00:19.0 init ... |
| PCI: 00:19.0 init finished in 0 usecs |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 14 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: base = e2928000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862805 |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 111d7605 |
| Azalia: verb_size: 44 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 3936 usecs |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 8 usecs |
| PCI: 00:1c.1 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 11 usecs |
| PCI: 00:1c.2 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.2 init finished in 11 usecs |
| PCI: 00:1c.3 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.3 init finished in 9 usecs |
| PCI: 00:1c.4 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.4 init finished in 9 usecs |
| PCI: 00:1c.6 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.6 init finished in 9 usecs |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 14 usecs |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| PCH: detected QM67, device id: 0x1c4f, rev id 0x5 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| FMAP: area COREBOOT found @ 30200 (8191488 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 622c0 size 4ac |
| Set power off after power failure. |
| FMAP: area COREBOOT found @ 30200 (8191488 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 622c0 size 4ac |
| NMI sources enabled. |
| CougarPoint PM init |
| RTC: failed = 0x0 |
| RTC Init |
| Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 1280 usecs |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| FMAP: area COREBOOT found @ 30200 (8191488 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 622c0 size 4ac |
| SATA: Controller in AHCI mode. |
| ABAR: e292e000 |
| PCI: 00:1f.2 init finished in 353 usecs |
| PCI: 04:00.0 init ... |
| PCI: 04:00.0 init finished in 1 usecs |
| PCI: 04:00.1 init ... |
| PCI: 04:00.1 init finished in 1 usecs |
| PCI: 04:00.2 init ... |
| PCI: 04:00.2 init finished in 0 usecs |
| PCI: 04:00.3 init ... |
| PCI: 04:00.3 init finished in 0 usecs |
| PCI: 04:00.4 init ... |
| PCI: 04:00.4 init finished in 0 usecs |
| PCI: 07:00.0 init ... |
| PCI: 07:00.0 init finished in 1 usecs |
| PNP: 004e.3 init ... |
| PNP: 004e.3 init finished in 1 usecs |
| PNP: 004e.4 init ... |
| PNP: 004e.4 init finished in 1 usecs |
| Devices initialized |
| BS: BS_DEV_INIT times (us): entry 64623 run 155821 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 380 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 65c00 size 336b |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff43000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| Generating ACPI PIRQ entries |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 7ff32000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff49960 |
| ACPI: * DMAR |
| ACPI: added table 6/32, length now 60 |
| current = 7ff49a30 |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Found @ offset 61d40 size 531 |
| Found a VBT of 3985 bytes after decompression |
| GMA: Found VBT in CBFS |
| GMA: Found valid VBT in CBFS |
| ACPI: * HPET |
| ACPI: added table 7/32, length now 64 |
| ACPI: done. |
| ACPI tables: 35440 bytes. |
| smbios_write_tables: 7ff31000 |
| Create SMBIOS type 17 |
| SMBIOS tables: 765 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum fe8 |
| Writing coreboot table at 0x7ff67000 |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 622c0 size 4ac |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff30fff: RAM |
| 4. 000000007ff31000-000000007ff7ffff: CONFIGURATION TABLES |
| 5. 000000007ff80000-000000007ffd7fff: RAMSTAGE |
| 6. 000000007ffd8000-000000007fffffff: CONFIGURATION TABLES |
| 7. 0000000080000000-00000000829fffff: RESERVED |
| 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| 9. 00000000fed40000-00000000fed44fff: RESERVED |
| 10. 00000000fed90000-00000000fed91fff: RESERVED |
| 11. 0000000100000000-000000047b5fffff: RAM |
| read e008 from 07e4 |
| wrote 00000004 to 0890 |
| read 03040003 from 0894 |
| wrote 00001000 to 0890 |
| read 24900024 from 0894 |
| read 00000000 from 0880 |
| wrote 00000000 to 0880 |
| read 0080 from 0870 |
| wrote 000c to 0870 |
| read e008 from 07e4 |
| read 05030201 from 0878 |
| read 0bd89f20 from 087c |
| read b32d from 0876 |
| read 5006 from 0874 |
| wrote 00000000 to 07e8 |
| wrote 4456 to 0871 |
| read 5481 from 0870 |
| read 5484 from 0870 |
| wrote 0004 to 0870 |
| read c21720c2 from 07f0 |
| read 20 from 07f4 |
| wrote 0000 to 0874 |
| Manufacturer: c2 |
| SF: Detected MX25L6405D with sector size 0x1000, total 0x800000 |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| Wrote coreboot table at: 7ff67000, 0x7f8 bytes, checksum 39e8 |
| coreboot table: 2064 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| ROMSTG STCK 3. 7ffdd000 00001000 |
| AFTER CAR 4. 7ffd8000 00005000 |
| RAMSTAGE 5. 7ff7f000 00059000 |
| SMM BACKUP 6. 7ff6f000 00010000 |
| COREBOOT 7. 7ff67000 00008000 |
| ACPI 8. 7ff43000 00024000 |
| ACPI GNVS 9. 7ff42000 00001000 |
| TCPA TCGLOG10. 7ff32000 00010000 |
| SMBIOS 11. 7ff31000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| MEM INFO 1. 7fffea40 000001b9 |
| ROMSTAGE 2. 7fffea20 00000004 |
| COREBOOTFWD 3. 7fffe9e0 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 5427 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [30200:800000) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 68fc0 size f7272 |
| Checking segment from ROM address 0xff8991f8 |
| Checking segment from ROM address 0xff899214 |
| Loading segment from ROM address 0xff8991f8 |
| code (compression=2) |
| New segment dstaddr 0x00800000 memsize 0x410000 srcaddr 0xff899230 filesize 0xf723a |
| Loading Segment: addr: 0x00800000 memsz: 0x0000000000410000 filesz: 0x00000000000f723a |
| using LZ4 |
| Loading segment from ROM address 0xff899214 |
| Entry Point 0x008008f0 |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 913140 exit 0 |
| ICH-NM10-PCH: watchdog disabled |
| Jumping to boot code at 008008f0(7ff67000) |
| |