| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| arting Sandy Bridge RAM training (full initialization). |
| 100MHz reference clock support: no |
| PLL_REF100_CFG value: 0x0 |
| Trying CAS 9, tCK 384. |
| Trying CAS 7, tCK 480. |
| Found compatible clock, CAS pair. |
| Selected DRAM frequency: 533 MHz |
| Selected CAS latency : 7T |
| PLL busy... done in 10 us |
| MCU frequency is set at : 533 MHz |
| Selected CWL latency : 6T |
| Selected tRCD : 7T |
| Selected tRP : 7T |
| Selected tRAS : 20T |
| Selected tWR : 8T |
| Selected tFAW : 20T |
| Selected tRRD : 4T |
| Selected tRTP : 4T |
| Selected tWTR : 4T |
| Selected tRFC : 59T |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 1 |
| PCI(0, 0, 0)[bc] = c2a00000 |
| PCI(0, 0, 0)[a8] = 3d600000 |
| PCI(0, 0, 0)[ac] = 1 |
| PCI(0, 0, 0)[b8] = c0000000 |
| PCI(0, 0, 0)[b0] = c0a00000 |
| PCI(0, 0, 0)[b4] = c0800000 |
| Done memory map |
| Done io registers |
| Done jedec reset |
| Done MRS commands |
| t123: 2128, 9120, 500 |
| ME: Wrong mode : 2 |
| ME: FWS2: 0x100a0000 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| Waited long enough, or CPU was not replaced, continue... |
| PASSED! Tell ME that DRAM is ready |
| ME: ME is reporting as disabled, so not waiting for a response. |
| ME: FWS2: 0x100a0000 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: No DID Ack received |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : YES |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1064 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00620008): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 2048 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00620008): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 2048 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ 0xbffff000 254 entries. |
| IMD: root @ 0xbfffec00 62 entries. |
| External stage cache: |
| IMD: root @ 0xc03ff000 254 entries. |
| IMD: root @ 0xc03fec00 62 entries. |
| CBMEM entry for DIMM info: 0xbfffe940 |
| POST: 0x3b |
| POST: 0x3c |
| POST: 0x3d |
| POST: 0x3f |
| SMM Memory Map |
| SMRAM : 0xc0000000 0x800000 |
| Subregion 0: 0xc0000000 0x300000 |
| Subregion 1: 0xc0300000 0x100000 |
| Subregion 2: 0xc0400000 0x400000 |
| MTRR Range: Start=bf800000 End=c0000000 (Size 800000) |
| MTRR Range: Start=c0000000 End=c0800000 (Size 800000) |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Found @ offset 419c0 size 46cc |
| Decompressing stage fallback/postcar @ 0xbffd1fc0 (34576 bytes) |
| Loading module at 0xbffd2000 with entry 0xbffd2000. filesize: 0x43d0 memsize: 0x86d0 |
| Processing 168 relocs. Offset value of 0xbdfd2000 |
| BS: romstage times (exec / console): total (unknown) / 506036 ms |
| |
| |
| coreboot-4.12-2974-ga32df26ec0 Sat Sep 26 11:42:28 UTC 2020 postcar starting (log level: 8)... |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 1a300 size 1bb92 |
| Decompressing stage fallback/ramstage @ 0xbff82fc0 (318800 bytes) |
| Loading module at 0xbff83000 with entry 0xbff83000. filesize: 0x38a78 memsize: 0x4dd10 |
| Processing 3933 relocs. Offset value of 0xbf183000 |
| BS: postcar times (exec / console): total (unknown) / 0 ms |
| |
| |
| coreboot-4.12-2974-ga32df26ec0 Sat Sep 26 11:42:28 UTC 2020 ramstage starting (log level: 8)... |
| POST: 0x39 |
| POST: 0x80 |
| Normal boot |
| POST: 0x70 |
| BS: BS_PRE_DEVICE run times (exec / console): 0 / 989 ms |
| POST: 0x71 |
| BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 989 ms |
| POST: 0x72 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 1 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 1 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| Root Device scanning... |
| scan_static_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| POST: 0x24 |
| PCI: 00:00.0 [8086/0000] ops |
| PCI: 00:00.0 [8086/0104] enabled |
| PCI: 00:01.0 [8086/0000] bus ops |
| PCI: 00:01.0 [8086/0101] disabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0126] enabled |
| PCI: 00:04.0 [8086/0103] enabled |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 [8086/1c3a] ops |
| PCI: 00:16.0 [8086/1c3a] disabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0 [8086/1502] enabled |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1c2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1c20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1c10] enabled |
| PCI: 00:1c.1 [8086/0000] bus ops |
| PCI: 00:1c.1 [8086/1c12] enabled |
| PCI: 00:1c.2 [8086/0000] bus ops |
| PCI: 00:1c.2 [8086/1c14] enabled |
| PCI: 00:1c.3 [8086/0000] bus ops |
| PCI: 00:1c.3 [8086/1c16] enabled |
| PCI: 00:1c.4 [8086/0000] bus ops |
| PCI: 00:1c.4 [8086/1c18] enabled |
| PCI: 00:1c.5: Disabling device |
| PCH: Remap PCIe function 6 to 5 |
| PCI: 00:1c.6 [8086/0000] bus ops |
| PCI: 00:1c.6 [8086/1c1c] enabled |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xf5e43210 |
| PCH: PCIe map 1c.5 -> 1c.6 |
| PCH: PCIe map 1c.6 -> 1c.5 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1c26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1e.0 [8086/2448] bus ops |
| PCI: 00:1e.0 [8086/2448] disabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1c4f] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| PCI: 00:1f.2 [8086/1c01] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1c22] enabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1c09] disabled No operations |
| PCI: 00:1f.6 [8086/1c24] enabled |
| POST: 0x25 |
| PCI: Leftover static devices: |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: Check your devicetree.cb. |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| PCI: pci_scan_bus for bus 01 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: bus PCI: 00:1c.0 finished in 8811 msecs |
| PCI: 00:1c.1 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.1 |
| PCI: pci_scan_bus for bus 02 |
| POST: 0x24 |
| PCI: 02:00.0 [8086/0000] ops |
| PCI: 02:00.0 [8086/0085] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| PCIe: Max_Payload_Size adjusted to 128 |
| Failed to enable LTR for dev = PCI: 02:00.0 |
| scan_bus: bus PCI: 00:1c.1 finished in 26614 msecs |
| PCI: 00:1c.2 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.2 |
| PCI: pci_scan_bus for bus 03 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: bus PCI: 00:1c.2 finished in 8811 msecs |
| PCI: 00:1c.3 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.3 |
| PCI: pci_scan_bus for bus 04 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: bus PCI: 00:1c.3 finished in 8811 msecs |
| PCI: 00:1c.4 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.4 |
| PCI: pci_scan_bus for bus 05 |
| POST: 0x24 |
| PCI: 05:00.0 [1180/0000] ops |
| PCI: 05:00.0 [1180/e823] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| PCIe: Max_Payload_Size adjusted to 128 |
| Failed to enable LTR for dev = PCI: 05:00.0 |
| scan_bus: bus PCI: 00:1c.4 finished in 27333 msecs |
| PCI: 00:1c.5 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.5 |
| PCI: pci_scan_bus for bus 06 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: bus PCI: 00:1c.5 finished in 8811 msecs |
| PCI: 00:1f.0 scanning... |
| scan_static_bus for PCI: 00:1f.0 |
| PMH7: ID 04 Revision 01 |
| PNP: 00ff.1 enabled |
| PNP: 0c31.0 enabled |
| Clearing EC output queue... |
| EC output queue has been cleared. |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x44 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x34 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x14 |
| recv_ec_data: 0x03 |
| recv_ec_data: 0x40 |
| recv_ec_data: 0x12 |
| H8: EC Firmware ID 8DHT34WW-3.20, Version 4.01C |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0x10 |
| H8: BDC detection not implemented. Assuming BDC installed |
| recv_ec_data: 0x20 |
| H8: WWAN not installed |
| recv_ec_data: 0x30 |
| recv_ec_data: 0x00 |
| recv_ec_data: 0xa6 |
| recv_ec_data: 0xa6 |
| recv_ec_data: 0x30 |
| PNP: 00ff.2 enabled |
| scan_static_bus for PCI: 00:1f.0 done |
| scan_bus: bus PCI: 00:1f.0 finished in 66989 msecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: bus PCI: 00:1f.3 finished in 36055 msecs |
| POST: 0x55 |
| scan_bus: bus DOMAIN: 0000 finished in 412258 msecs |
| scan_static_bus for Root Device done |
| scan_bus: bus Root Device finished in 429341 msecs |
| done |
| BS: BS_DEV_ENUMERATE run times (exec / console): 5 / 630474 ms |
| FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| Manufacturer: ef |
| SF: Detected ef 4017 with sector size 0x1000, total 0x800000 |
| MRC: no data in 'RW_MRC_CACHE' |
| MRC: cache data 'RW_MRC_CACHE' needs update. |
| MRC: updated 'RW_MRC_CACHE'. |
| BS: BS_DEV_ENUMERATE exit times (exec / console): 6 / 25985 ms |
| POST: 0x73 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| TOUUD 0x13d600000 TOLUD 0xc2a00000 TOM 0x100000000 |
| MEBASE 0x7ffff00000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0xc0000000 size 8M |
| Available memory below 4GB: 3072M |
| Available memory above 4GB: 982M |
| PCI: 00:1c.0 read_resources bus 1 link: 0 |
| PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.1 read_resources bus 2 link: 0 |
| PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| PCI: 00:1c.2 read_resources bus 3 link: 0 |
| PCI: 00:1c.2 read_resources bus 3 link: 0 done |
| PCI: 00:1c.3 read_resources bus 4 link: 0 |
| PCI: 00:1c.3 read_resources bus 4 link: 0 done |
| PCI: 00:1c.4 read_resources bus 5 link: 0 |
| PCI: 00:1c.4 read_resources bus 5 link: 0 done |
| PCI: 00:1c.5 read_resources bus 6 link: 0 |
| PCI: 00:1c.5 read_resources bus 6 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| PCI: 00:1f.3 read_resources bus 1 link: 0 |
| PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| PCI: 00:00.0 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| PCI: 00:00.0 resource base 100000000 size 3d600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| PCI: 00:00.0 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| PCI: 00:00.0 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index 9 |
| PCI: 00:00.0 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a |
| PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b |
| PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.2 |
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1c.3 child on link 0 NONE |
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| NONE |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 |
| NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 |
| PCI: 00:1c.4 child on link 0 PCI: 05:00.0 |
| PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 05:00.0 |
| PCI: 05:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.5 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.5 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.5 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 |
| ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 02:00.0 10 * [0x0 - 0x1fff] mem |
| PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.3 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 00:1c.3 mem: size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.3 prefmem: size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 05:00.0 10 * [0x0 - 0xff] mem |
| PCI: 00:1c.4 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| update_constraints: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| update_constraints: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed) |
| update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) |
| update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| DOMAIN: 0000: Resource ranges: |
| * Base: 1000, Size: 5e0, Tag: 100 |
| * Base: 15f0, Size: 10, Tag: 100 |
| * Base: 167c, Size: e984, Tag: 100 |
| PCI: 00:1c.3 1c * [0x2000 - 0x2fff] limit: 2fff io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io |
| PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io |
| PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io |
| PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io |
| PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io |
| PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io |
| PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed) |
| update_constraints: PCI: 00:00.0 04 base 00100000 limit bfffffff mem (fixed) |
| update_constraints: PCI: 00:00.0 05 base 100000000 limit 13d5fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 06 base c0000000 limit c29fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed) |
| update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 09 base 20000000 limit 201fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 0a base 40000000 limit 401fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 0b base fed90000 limit fed90fff mem (fixed) |
| update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed) |
| update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed) |
| update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) |
| DOMAIN: 0000: Resource ranges: |
| * Base: c2a00000, Size: 2d600000, Tag: 200 |
| * Base: f4000000, Size: ac00000, Tag: 200 |
| * Base: fec01000, Size: 13f000, Tag: 200 |
| * Base: fed45000, Size: 4b000, Tag: 200 |
| * Base: fed92000, Size: 26e000, Tag: 200 |
| * Base: 13d600000, Size: ec2a00000, Tag: 100200 |
| PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem |
| PCI: 00:1c.3 24 * [0xc2c00000 - 0xc33fffff] limit: c33fffff prefmem |
| PCI: 00:1c.3 20 * [0xc3400000 - 0xc3bfffff] limit: c3bfffff mem |
| PCI: 00:02.0 10 * [0xc3c00000 - 0xc3ffffff] limit: c3ffffff mem |
| PCI: 00:1c.1 20 * [0xc2a00000 - 0xc2afffff] limit: c2afffff mem |
| PCI: 00:1c.4 20 * [0xc2b00000 - 0xc2bfffff] limit: c2bfffff mem |
| PCI: 00:19.0 10 * [0xc4000000 - 0xc401ffff] limit: c401ffff mem |
| PCI: 00:04.0 10 * [0xc4020000 - 0xc4027fff] limit: c4027fff mem |
| PCI: 00:1b.0 10 * [0xc4028000 - 0xc402bfff] limit: c402bfff mem |
| PCI: 00:19.0 14 * [0xc402c000 - 0xc402cfff] limit: c402cfff mem |
| PCI: 00:1f.6 10 * [0xc402d000 - 0xc402dfff] limit: c402dfff mem |
| PCI: 00:1f.2 24 * [0xc402e000 - 0xc402e7ff] limit: c402e7ff mem |
| PCI: 00:1a.0 10 * [0xc402f000 - 0xc402f3ff] limit: c402f3ff mem |
| PCI: 00:1d.0 10 * [0xc4030000 - 0xc40303ff] limit: c40303ff mem |
| PCI: 00:1f.3 10 * [0xc4031000 - 0xc40310ff] limit: c40310ff mem |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| PCI: 00:1c.1 mem: base: c2a00000 size: 100000 align: 20 gran: 20 limit: c2afffff |
| PCI: 00:1c.1: Resource ranges: |
| * Base: c2a00000, Size: 100000, Tag: 200 |
| PCI: 02:00.0 10 * [0xc2a00000 - 0xc2a01fff] limit: c2a01fff mem |
| PCI: 00:1c.1 mem: base: c2a00000 size: 100000 align: 20 gran: 20 limit: c2afffff done |
| PCI: 00:1c.3 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff |
| PCI: 00:1c.3: Resource ranges: |
| * Base: 2000, Size: 1000, Tag: 100 |
| NONE 18 * [0x2000 - 0x2fff] limit: 2fff io |
| PCI: 00:1c.3 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done |
| PCI: 00:1c.3 prefmem: base: c2c00000 size: 800000 align: 22 gran: 20 limit: c33fffff |
| PCI: 00:1c.3: Resource ranges: |
| * Base: c2c00000, Size: 800000, Tag: 1200 |
| NONE 14 * [0xc2c00000 - 0xc33fffff] limit: c33fffff prefmem |
| PCI: 00:1c.3 prefmem: base: c2c00000 size: 800000 align: 22 gran: 20 limit: c33fffff done |
| PCI: 00:1c.3 mem: base: c3400000 size: 800000 align: 22 gran: 20 limit: c3bfffff |
| PCI: 00:1c.3: Resource ranges: |
| * Base: c3400000, Size: 800000, Tag: 200 |
| NONE 10 * [0xc3400000 - 0xc3bfffff] limit: c3bfffff mem |
| PCI: 00:1c.3 mem: base: c3400000 size: 800000 align: 22 gran: 20 limit: c3bfffff done |
| PCI: 00:1c.4 mem: base: c2b00000 size: 100000 align: 20 gran: 20 limit: c2bfffff |
| PCI: 00:1c.4: Resource ranges: |
| * Base: c2b00000, Size: 100000, Tag: 200 |
| PCI: 05:00.0 10 * [0xc2b00000 - 0xc2b000ff] limit: c2b000ff mem |
| PCI: 00:1c.4 mem: base: c2b00000 size: 100000 align: 20 gran: 20 limit: c2bfffff done |
| === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| Root Device assign_resources, bus 0 link: 0 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:02.0 10 <- [0x00c3c00000 - 0x00c3ffffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x00c4020000 - 0x00c4027fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:19.0 10 <- [0x00c4000000 - 0x00c401ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00c402c000 - 0x00c402cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 10 <- [0x00c402f000 - 0x00c402f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00c4028000 - 0x00c402bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00c2a00000 - 0x00c2afffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 02:00.0 10 <- [0x00c2a00000 - 0x00c2a01fff] size 0x00002000 gran 0x0d mem64 |
| PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.2 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io |
| PCI: 00:1c.3 24 <- [0x00c2c00000 - 0x00c33fffff] size 0x00800000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.3 20 <- [0x00c3400000 - 0x00c3bfffff] size 0x00800000 gran 0x14 bus 04 mem |
| PCI: 00:1c.3 assign_resources, bus 4 link: 0 |
| NONE missing set_resources |
| PCI: 00:1c.3 assign_resources, bus 4 link: 0 |
| PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io |
| PCI: 00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem |
| PCI: 00:1c.4 20 <- [0x00c2b00000 - 0x00c2bfffff] size 0x00100000 gran 0x14 bus 05 mem |
| PCI: 00:1c.4 assign_resources, bus 5 link: 0 |
| PCI: 05:00.0 10 <- [0x00c2b00000 - 0x00c2b000ff] size 0x00000100 gran 0x08 mem |
| PCI: 00:1c.4 assign_resources, bus 5 link: 0 |
| PCI: 00:1c.5 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io |
| PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 06 prefmem |
| PCI: 00:1c.5 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 06 mem |
| PCI: 00:1d.0 10 <- [0x00c4030000 - 0x00c40303ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000001080 - 0x0000001087] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000001090 - 0x0000001093] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000001088 - 0x000000108f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000001094 - 0x0000001097] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00c402e000 - 0x00c402e7ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00c4031000 - 0x00c40310ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.6 10 <- [0x00c402d000 - 0x00c402dfff] size 0x00001000 gran 0x0c mem64 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| PCI: 00:00.0 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| PCI: 00:00.0 resource base 100000000 size 3d600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| PCI: 00:00.0 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| PCI: 00:00.0 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index 9 |
| PCI: 00:00.0 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a |
| PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b |
| PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c |
| PCI: 00:01.0 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base c3c00000 size 400000 align 22 gran 22 limit c3ffffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base c4020000 size 8000 align 15 gran 15 limit c4027fff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base c4000000 size 20000 align 17 gran 17 limit c401ffff flags 60000200 index 10 |
| PCI: 00:19.0 resource base c402c000 size 1000 align 12 gran 12 limit c402cfff flags 60000200 index 14 |
| PCI: 00:19.0 resource base 1040 size 20 align 5 gran 5 limit 105f flags 60000100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base c402f000 size 400 align 12 gran 10 limit c402f3ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base c4028000 size 4000 align 14 gran 14 limit c402bfff flags 60000201 index 10 |
| PCI: 00:1c.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| PCI: 00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| PCI: 00:1c.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| PCI: 00:1c.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| PCI: 00:1c.1 resource base c2a00000 size 100000 align 20 gran 20 limit c2afffff flags 60080202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base c2a00000 size 2000 align 13 gran 13 limit c2a01fff flags 60000201 index 10 |
| PCI: 00:1c.2 |
| PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| PCI: 00:1c.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| PCI: 00:1c.2 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| PCI: 00:1c.3 child on link 0 NONE |
| PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c |
| PCI: 00:1c.3 resource base c2c00000 size 800000 align 22 gran 20 limit c33fffff flags 60081202 index 24 |
| PCI: 00:1c.3 resource base c3400000 size 800000 align 22 gran 20 limit c3bfffff flags 60080202 index 20 |
| NONE |
| NONE resource base c3400000 size 800000 align 22 gran 22 limit c3bfffff flags 40000200 index 10 |
| NONE resource base c2c00000 size 800000 align 22 gran 22 limit c33fffff flags 40001200 index 14 |
| NONE resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18 |
| PCI: 00:1c.4 child on link 0 PCI: 05:00.0 |
| PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| PCI: 00:1c.4 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| PCI: 00:1c.4 resource base c2b00000 size 100000 align 20 gran 20 limit c2bfffff flags 60080202 index 20 |
| PCI: 05:00.0 |
| PCI: 05:00.0 resource base c2b00000 size 100 align 12 gran 8 limit c2b000ff flags 60000200 index 10 |
| PCI: 00:1c.5 |
| PCI: 00:1c.5 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| PCI: 00:1c.5 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| PCI: 00:1c.5 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base c4030000 size 400 align 12 gran 10 limit c40303ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 1080 size 8 align 3 gran 3 limit 1087 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 1090 size 4 align 2 gran 2 limit 1093 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 1088 size 8 align 3 gran 3 limit 108f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 1094 size 4 align 2 gran 2 limit 1097 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 1060 size 20 align 5 gran 5 limit 107f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base c402e000 size 800 align 12 gran 11 limit c402e7ff flags 60000200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base c4031000 size 100 align 12 gran 8 limit c40310ff flags 60000201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| PCI: 00:1f.6 resource base c402d000 size 1000 align 12 gran 12 limit c402dfff flags 60000201 index 10 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES run times (exec / console): 1 / 4293098026 ms |
| POST: 0x74 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 8086/0104 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 8086/0126 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:19.0 subsystem <- 17aa/21ce |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 8086/1c2d |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 8086/1c20 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0013 |
| PCI: 00:1c.0 subsystem <- 8086/1c10 |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0013 |
| PCI: 00:1c.1 subsystem <- 8086/1c12 |
| PCI: 00:1c.1 cmd <- 106 |
| PCI: 00:1c.2 bridge ctrl <- 0013 |
| PCI: 00:1c.2 subsystem <- 8086/1c14 |
| PCI: 00:1c.2 cmd <- 100 |
| PCI: 00:1c.3 bridge ctrl <- 0013 |
| PCI: 00:1c.3 subsystem <- 8086/1c16 |
| PCI: 00:1c.3 cmd <- 107 |
| PCI: 00:1c.4 bridge ctrl <- 0013 |
| PCI: 00:1c.4 subsystem <- 8086/1c18 |
| PCI: 00:1c.4 cmd <- 106 |
| PCI: 00:1c.5 bridge ctrl <- 0013 |
| PCI: 00:1c.5 subsystem <- 8086/1c1c |
| PCI: 00:1c.5 cmd <- 100 |
| PCI: 00:1d.0 subsystem <- 8086/1c26 |
| PCI: 00:1d.0 cmd <- 102 |
| PCI: 00:1f.0 subsystem <- 8086/1c4f |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 8086/1c03 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 8086/1c22 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 00:1f.6 subsystem <- 8086/1c24 |
| PCI: 00:1f.6 cmd <- 02 |
| PCI: 02:00.0 cmd <- 02 |
| PCI: 05:00.0 subsystem <- 1180/e823 |
| PCI: 05:00.0 cmd <- 06 |
| done. |
| BS: BS_DEV_ENABLE run times (exec / console): 0 / 116708 ms |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=0, nvlocked=1 |
| TPM: setup succeeded |
| BS: BS_DEV_INIT entry times (exec / console): 16 / 23018 ms |
| POST: 0x75 |
| Initializing devices... |
| POST: 0x75 |
| CPU_CLUSTER: 0 init |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 |
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000013d600000 size 0x3d600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 3/4. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| CPU has 2 cores, 4 threads enabled. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13a80 size 6800 |
| microcode: sig=0x206a7 pf=0x10 revision=0x2f |
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. |
| Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 3 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1. |
| done. |
| AP: slot 3 apic_id 2. |
| AP: slot 2 apic_id 3. |
| Waiting for 2nd SIPI to complete...done. |
| Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| Unable to locate Global NVS |
| SMM Module: stub loaded at 0x00038000. Will call 0xbffa2753(0x00000000) |
| Installing permanent SMM handler to 0xc0000000 |
| Loading module at 0xc0010000 with entry 0xc001030c. filesize: 0x1590 memsize: 0x55b8 |
| Processing 69 relocs. Offset value of 0xc0010000 |
| Loading module at 0xc0008000 with entry 0xc0008000. filesize: 0x1b8 memsize: 0x1b8 |
| Processing 13 relocs. Offset value of 0xc0008000 |
| SMM Module: placing jmp sequence at 0xc0007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 0xc0007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 0xc0007400 rel16 0x0bfd |
| Unable to locate Global NVS |
| SMM Module: stub loaded at 0xc0008000. Will call 0xc001030c(0x00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xc0000000, cpu = 0 |
| In relocation handler: cpu 0 |
| New SMBASE=0xc0000000 IEDBASE=0xc0400000 |
| SMM revision: 0x00030101 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xbffffc00, cpu = 1 |
| MP record 2 timeout. |
| In relocation handler: cpu 1 |
| Initializing CPU #0 |
| New SMBASE=0xbffffc00 IEDBASE=0xc0400000 |
| CPU: vendor Intel device 206a7 |
| SMM revision: 0x00030101 |
| CPU: family 06, model 2a, stepping 07 |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| POST: 0x60 |
| Enabling cache |
| Relocation complete. |
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. |
| microcode: Update skipped, already up-to-date |
| CPU: platform id 4 |
| smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xbffff800, cpu = 2 |
| CPU: cpuid(1) 0x206a7 |
| In relocation handler: cpu 2 |
| New SMBASE=0xbffff800 IEDBASE=0xc0400000 |
| SMM revision: 0x00030101 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| Setting up local APIC... |
| Relocation complete. |
| apic_id: 0x00 done. |
| smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xbffff400, cpu = 3 |
| microcode: Update skipped, already up-to-date |
| In relocation handler: cpu 3 |
| New SMBASE=0xbffff400 IEDBASE=0xc0400000 |
| SMM revision: 0x00030101 |
| VMX status: enabled |
| Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| IA32_FEATURE_CONTROL status: locked |
| Relocation complete. |
| model_x06ax: energy policy set to 6 |
| microcode: Update skipped, already up-to-date |
| model_x06ax: frequency set to 2500 |
| Turbo is available but hidden |
| Turbo is available and visible |
| CPU #0 initialized |
| Initializing CPU #1 |
| MP record 3 timeout. |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| bsp_do_flight_plan done after 232330 msecs. |
| POST: 0x60 |
| Enabling cache |
| MP initialization failure. |
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. |
| CPU_CLUSTER: 0 init finished in 424040 msecs |
| CPU: platform id 4 |
| POST: 0x75 |
| CPU: cpuid(1) 0x206a7 |
| POST: 0x75 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| POST: 0x75 |
| Setting up local APIC... |
| POST: 0x75 |
| apic_id: 0x01 done. |
| POST: 0x75 |
| VMX status: enabled |
| POST: 0x75 |
| IA32_FEATURE_CONTROL status: locked |
| POST: 0x75 |
| model_x06ax: energy policy set to 6 |
| PCI: 00:00.0 init |
| model_x06ax: frequency set to 2500 |
| Disabling PEG12. |
| CPU #1 initialized |
| Disabling PEG11. |
| Initializing CPU #3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| CPU: vendor Intel device 206a7 |
| CPU: family 06, model 2a, stepping 07 |
| POST: 0x60 |
| Enabling cache |
| POST: 0x60 |
| Enabling cache |
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. |
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. |
| CPU: platform id 4 |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x206a7 |
| CPU: cpuid(1) 0x206a7 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| Setting up local APIC... |
| apic_id: 0x02 done. |
| apic_id: 0x03 done. |
| VMX status: enabled |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| IA32_FEATURE_CONTROL status: locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2500 |
| model_x06ax: frequency set to 2500 |
| CPU #3 initialized |
| CPU #2 initialized |
| Disabling PEG10. |
| Disabling PEG60. |
| Disabling Device 7. |
| Disabling PEG IO clock. |
| Set BIOS_RESET_CPL |
| CPU TDP: 35 Watts |
| PCI: 00:00.0 init finished in 99350 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:02.0 init |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Found @ offset 40c80 size 578 |
| Found a VBT of 3985 bytes after decompression |
| GMA: Found VBT in CBFS |
| GMA: Found valid VBT in CBFS |
| GT Power Management Init |
| SNB GT2 Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| |
| [36439.403270] CONFIG => |
| [36441.650434] (Primary => |
| [36444.436922] (Port => LVDS , |
| [36447.942511] Framebuffer => |
| [36451.178413] (Width => 1366, |
| [36455.043513] Height => 768, |
| [36458.818735] Start_X => 0, |
| [36462.414195] Start_Y => 0, |
| [36466.009652] Stride => 1376, |
| [36469.874761] V_Stride => 768, |
| [36473.649992] Tiling => Linear , |
| [36477.784775] Rotation => No_Rotation, |
| [36482.279084] Offset => 0x00000000, |
| [36486.413837] BPC => 8), |
| [36489.829550] Mode => |
| [36492.436240] (Dotclock => 69300000, |
| [36497.469847] H_Visible => 1366, |
| [36502.143965] H_Sync_Begin => 1414, |
| [36506.818067] H_Sync_End => 1446, |
| [36511.492138] H_Total => 1454, |
| [36516.166200] V_Visible => 768, |
| [36520.750422] V_Sync_Begin => 771, |
| [36525.334615] V_Sync_End => 777, |
| [36529.918846] V_Total => 793, |
| [36534.503032] H_Sync_Active_High => False, |
| [36539.267049] V_Sync_Active_High => False, |
| [36544.031033] BPC => 6)), |
| [36548.615231] Secondary => |
| [36551.401705] (Port => Disabled, |
| [36554.907258] Framebuffer => |
| [36558.143156] (Width => 1, |
| [36561.738608] Height => 1, |
| [36565.334057] Start_X => 0, |
| [36568.929516] Start_Y => 0, |
| [36572.524971] Stride => 1, |
| [36576.120415] V_Stride => 1, |
| [36579.715870] Tiling => Linear , |
| [36583.850684] Rotation => No_Rotation, |
| [36588.345002] Offset => 0x00000000, |
| [36592.479754] BPC => 8), |
| [36595.895452] Mode => |
| [36598.502147] (Dotclock => 1000000, |
| [36603.445898] H_Visible => 1, |
| [36607.850294] H_Sync_Begin => 1, |
| [36612.254735] H_Sync_End => 1, |
| [36616.659152] H_Total => 1, |
| [36621.063556] V_Visible => 1, |
| [36625.467986] V_Sync_Begin => 1, |
| [36629.872424] V_Sync_End => 1, |
| [36634.276842] V_Total => 1, |
| [36638.681269] H_Sync_Active_High => False, |
| [36643.445262] V_Sync_Active_High => False, |
| [36648.209231] BPC => 5)), |
| [36652.793429] Tertiary => |
| [36655.579904] (Port => Disabled, |
| [36659.085482] Framebuffer => |
| [36662.321369] (Width => 1, |
| [36665.916831] Height => 1, |
| [36669.512284] Start_X => 0, |
| [36673.107722] Start_Y => 0, |
| [36676.703148] Stride => 1, |
| [36680.298578] V_Stride => 1, |
| [36683.894029] Tiling => Linear , |
| [36688.028812] Rotation => No_Rotation, |
| [36692.523107] Offset => 0x00000000, |
| [36696.657865] BPC => 8), |
| [36700.073538] Mode => |
| [36702.680253] (Dotclock => 1000000, |
| [36707.624006] H_Visible => 1, |
| [36712.028465] H_Sync_Begin => 1, |
| [36716.432919] H_Sync_End => 1, |
| [36720.837367] H_Total => 1, |
| [36725.241787] V_Visible => 1, |
| [36729.646210] V_Sync_Begin => 1, |
| [36734.050613] V_Sync_End => 1, |
| [36738.455032] V_Total => 1, |
| [36742.859453] H_Sync_Active_High => False, |
| [36747.623421] V_Sync_Active_High => False, |
| [36752.387406] BPC => 5))); |
| PCI: 00:02.0 init finished in 348106 msecs |
| POST: 0x75 |
| PCI: 00:04.0 init |
| PCI: 00:04.0 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:19.0 init |
| PCI: 00:19.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1a.0 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 3235 msecs |
| POST: 0x75 |
| PCI: 00:1b.0 init |
| Azalia: base = c4028000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862805 |
| Azalia: No verb! |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 14f1506e |
| Azalia: verb_size: 52 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 20678 msecs |
| POST: 0x75 |
| PCI: 00:1c.0 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 2696 msecs |
| POST: 0x75 |
| PCI: 00:1c.1 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 2696 msecs |
| POST: 0x75 |
| PCI: 00:1c.2 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.2 init finished in 2696 msecs |
| POST: 0x75 |
| PCI: 00:1c.3 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.3 init finished in 2696 msecs |
| POST: 0x75 |
| PCI: 00:1c.4 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.4 init finished in 2696 msecs |
| POST: 0x75 |
| PCI: 00:1c.5 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.5 init finished in 2696 msecs |
| POST: 0x75 |
| PCI: 00:1d.0 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 3235 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.0 init |
| pch: lpc_init |
| PCH: detected QM67, device id: 0x1c4f, rev id 0x5 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| Set power off after power failure. |
| NMI sources disabled. |
| CougarPoint PM init |
| RTC: failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC. |
| APMC done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 41707 msecs |
| POST: 0x75 |
| PCI: 00:1f.2 init |
| SATA: Initializing... |
| SATA: Controller in AHCI mode. |
| ABAR: 0xc402e000 |
| PCI: 00:1f.2 init finished in 6292 msecs |
| POST: 0x75 |
| PCI: 00:1f.3 init |
| PCI: 00:1f.3 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.6 init |
| PCI: 00:1f.6 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 02:00.0 init |
| PCI: 02:00.0 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 05:00.0 init |
| PCI: 05:00.0 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PNP: 00ff.2 init |
| Keyboard init... |
| Keyboard controller output buffer result timeout |
| PS/2 keyboard initialized on primary channel |
| PNP: 00ff.2 init finished in 10390 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| I2C: 01:54 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| I2C: 01:55 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| I2C: 01:56 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| I2C: 01:57 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 3353 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| I2C: 01:5d init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| I2C: 01:5e init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| I2C: 01:5f init finished in 0 msecs |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 0 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:16.0: enabled 0 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 1 |
| PCI: 00:1c.4: enabled 1 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.5: enabled 1 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 1 |
| PCI: 05:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| I2C: 01:54: enabled 1 |
| I2C: 01:55: enabled 1 |
| I2C: 01:56: enabled 1 |
| I2C: 01:57: enabled 1 |
| I2C: 01:5c: enabled 1 |
| I2C: 01:5d: enabled 1 |
| I2C: 01:5e: enabled 1 |
| I2C: 01:5f: enabled 1 |
| PCI: 00:04.0: enabled 1 |
| PCI: 02:00.0: enabled 1 |
| NONE: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 02: enabled 1 |
| BS: BS_DEV_INIT run times (exec / console): 522642 / 793531 ms |
| POST: 0x76 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Finalizing SMM. |
| APMC done. |
| Devices finalized |
| BS: BS_POST_DEVICE run times (exec / console): 0 / 8539 ms |
| POST: 0x77 |
| BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 989 ms |
| POST: 0x79 |
| POST: 0x9c |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 3d300 size 3926 |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at bff44000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 4 core(s) each. |
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900 |
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00 |
| PSS: 800MHz power 9139 control 0x800 status 0x800 |
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900 |
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00 |
| PSS: 800MHz power 9139 control 0x800 status 0x800 |
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900 |
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00 |
| PSS: 800MHz power 9139 control 0x800 status 0x800 |
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000 |
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900 |
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00 |
| PSS: 800MHz power 9139 control 0x800 status 0x800 |
| Generating ACPI PIRQ entries |
| ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:04.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:19.0: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2 |
| ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=2 |
| ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=3 pirq=1 |
| \_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: * H8 |
| H8: BDC detection not implemented. Assuming BDC installed |
| H8: WWAN not installed |
| \_SB.PCI0.RP02.WF00.WF00: PCI: 02:00.0 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 0xbff33000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = bff497a0 |
| ACPI: * DMAR |
| ACPI: added table 6/32, length now 60 |
| current = bff49860 |
| ACPI: * HPET |
| ACPI: added table 7/32, length now 64 |
| ACPI: done. |
| ACPI tables: 22688 bytes. |
| smbios_write_tables: bff32000 |
| recv_ec_data: 0x38 |
| recv_ec_data: 0x44 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x34 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x14 |
| recv_ec_data: 0x03 |
| Create SMBIOS type 16 |
| Create SMBIOS type 17 |
| PCI: 02:00.0 (unknown) |
| SMBIOS tables: 1002 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum bfe7 |
| Writing coreboot table at 0xbff68000 |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000001fffffff: RAM |
| 4. 0000000020000000-00000000201fffff: RESERVED |
| 5. 0000000020200000-000000003fffffff: RAM |
| 6. 0000000040000000-00000000401fffff: RESERVED |
| 7. 0000000040200000-00000000bff31fff: RAM |
| 8. 00000000bff32000-00000000bff82fff: CONFIGURATION TABLES |
| 9. 00000000bff83000-00000000bffd0fff: RAMSTAGE |
| 10. 00000000bffd1000-00000000bfffffff: CONFIGURATION TABLES |
| 11. 00000000c0000000-00000000c29fffff: RESERVED |
| 12. 00000000f0000000-00000000f3ffffff: RESERVED |
| 13. 00000000fed40000-00000000fed44fff: RESERVED |
| 14. 00000000fed90000-00000000fed91fff: RESERVED |
| 15. 0000000100000000-000000013d5fffff: RAM |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| Wrote coreboot table at: 0xbff68000, 0x3f4 bytes, checksum 60ef |
| coreboot table: 1036 bytes. |
| IMD ROOT 0. 0xbffff000 0x00001000 |
| IMD SMALL 1. 0xbfffe000 0x00001000 |
| CONSOLE 2. 0xbffde000 0x00020000 |
| TIME STAMP 3. 0xbffdd000 0x00000910 |
| MRC DATA 4. 0xbffdc000 0x00000644 |
| ROMSTG STCK 5. 0xbffdb000 0x00001000 |
| AFTER CAR 6. 0xbffd1000 0x0000a000 |
| RAMSTAGE 7. 0xbff82000 0x0004f000 |
| SMM BACKUP 8. 0xbff72000 0x00010000 |
| 4f444749 9. 0xbff70000 0x00002000 |
| COREBOOT 10. 0xbff68000 0x00008000 |
| ACPI 11. 0xbff44000 0x00024000 |
| ACPI GNVS 12. 0xbff43000 0x00001000 |
| TCPA TCGLOG13. 0xbff33000 0x00010000 |
| SMBIOS 14. 0xbff32000 0x00000800 |
| IMD small region: |
| IMD ROOT 0. 0xbfffec00 0x00000400 |
| FMAP 1. 0xbfffeb20 0x000000e0 |
| MEM INFO 2. 0xbfffe940 0x000001e0 |
| ROMSTAGE 3. 0xbfffe920 0x00000004 |
| BS: BS_WRITE_TABLES run times (exec / console): 25 / 447995 ms |
| POST: 0x7a |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 46100 size 10e4b |
| Checking segment from ROM address 0xfff56338 |
| Payload being loaded at below 1MiB without region being marked as RAM usable. |
| Checking segment from ROM address 0xfff56354 |
| Loading segment from ROM address 0xfff56338 |
| code (compression=1) |
| New segment dstaddr 0x000dffa0 memsize 0x20060 srcaddr 0xfff56370 filesize 0x10e13 |
| Loading Segment: addr: 0x000dffa0 memsz: 0x0000000000020060 filesz: 0x0000000000010e13 |
| using LZMA |
| [ 0x000dffa0, 00100000, 0x00100000) <- fff56370 |
| Loading segment from ROM address 0xfff56354 |
| Entry Point 0x000fd265 |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD run times (exec / console): 31 / 61482 ms |
| POST: 0x7b |
| ICH-NM10-PCH: watchdog disabled |
| Jumping to boot code at 0x000fd265(0xbff68000) |
| POST: 0xf8 |
| CPU0: stack: 0xbffc4000 - 0xbffc5000, lowest used address 0xbffc48dc, stack used: 1828 bytes |
| SeaBIOS (version rel-1.14.0-0-g155821a) |
| BUILD: gcc: (coreboot toolchain v33f64b5d78 2020-09-12) 8.3.0 binutils: (GNU Binutils) 2.35 |
| Found coreboot cbmem console @ bffde000 |
| Found mainboard LENOVO ThinkPad X220 |
| Relocating init from 0x000e16c0 to 0xbfee4c00 (size 54016) |
| Found CBFS header at 0xfff10238 |
| multiboot: eax=bffbb020, ebx=bffbafe4 |
| Found 19 PCI devices (max PCI bus is 06) |
| Copying SMBIOS entry point from 0xbff32000 to 0x000f6780 |
| Copying ACPI RSDP from 0xbff44000 to 0x000f6750 |
| table(50434146)=0xbff47bc0 (via xsdt) |
| Using pmtimer, ioport 0x508 |
| table(41504354)=0xbff496f0 (via xsdt) |
| EHCI init on dev 00:1a.0 (regs=0xc402f020) |
| EHCI init on dev 00:1d.0 (regs=0xc4030020) |
| AHCI controller at 00:1f.2, iobase 0xc402e000, irq 11 |
| Searching bootorder for: /pci@i0cf8/pci-bridge@1c,4/*@0 |
| Searching bootorder for: HALT |
| Found 0 lpt ports |
| Found 0 serial ports |
| Scan for VGA option rom |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-6 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: registering: "AHCI/0: WDC WDS120G1G0A-00SS50 ATA-9 Hard-Disk (111 GiBytes)" |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.14.0-0-g155821a) |
| Machine UUID c7012201-507f-11cb-a996-d5921c6a55f5 |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Initialized USB HUB (0 ports used) |
| PS2 keyboard initialized |
| WARNING - Timeout at ehci_wait_td:517! |
| ehci pipe=0xbfedc780 cur=bfed4dc0 tok=80080d80 next=bfed4e00 td=0xbfed4dc0 status=80080d80 |
| Initialized USB HUB (0 ports used) |
| All threads complete. |
| Searching bootorder for: HALT |
| drive 0x000f66e0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 |
| Space available for UMB: c7000-ed000, f5fa0-f66e0 |
| Returned 253952 bytes of ZoneHigh |
| e820 map has 13 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 0000000020000000 = 1 RAM |
| 4: 0000000020000000 - 0000000020200000 = 2 RESERVED |
| 5: 0000000020200000 - 0000000040000000 = 1 RAM |
| 6: 0000000040000000 - 0000000040200000 = 2 RESERVED |
| 7: 0000000040200000 - 00000000bff30000 = 1 RAM |
| 8: 00000000bff30000 - 00000000c2a00000 = 2 RESERVED |
| 9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 10: 00000000fed40000 - 00000000fed45000 = 2 RESERVED |
| 11: 00000000fed90000 - 00000000fed92000 = 2 RESERVED |
| 12: 0000000100000000 - 000000013d600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |