| |
| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| 0T |
| Selected tRRD : 4T |
| Selected tRTP : 5T |
| Selected tWTR : 5T |
| Selected tRFC : 174T |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 6 |
| PCI(0, 0, 0)[bc] = 82a00000 |
| PCI(0, 0, 0)[a8] = 7d600000 |
| PCI(0, 0, 0)[ac] = 6 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| Done memory map |
| Done io registers |
| Done jedec reset |
| Done MRS commands |
| t123: 1912, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| ME: Wrong mode : 2 |
| ME: FWS2: 0x100a0100 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| PASSED! Tell ME that DRAM is ready |
| ME: ME is reporting as disabled, so not waiting for a response. |
| ME: FWS2: 0x100a0100 |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x0 |
| ME: Invoke MEBx : 0x0 |
| ME: CPU replaced : 0x0 |
| ME: MBP ready : 0x0 |
| ME: MFS failure : 0x0 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0xa |
| ME: Current PM event: 0x0 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: No DID Ack received |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1330 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00671020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank |
| DIMMB 4096 MB width x8 dual rank, selected |
| memcfg channel[1] config (00661020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 4096 MB width x8 dual rank |
| CBMEM: |
| IMD: root @ 7ffff000 254 entries. |
| IMD: root @ 7fffec00 62 entries. |
| External stage cache: |
| IMD: root @ 803ff000 254 entries. |
| IMD: root @ 803fec00 62 entries. |
| CBMEM entry for DIMM info: 0x7fffeaa0 |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| MTRR Range: Start=0 End=1000000 (Size 1000000) |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Found @ offset 366c0 size 4254 |
| Decompressing stage fallback/postcar @ 0x7ffcdfc0 (33552 bytes) |
| Loading module at 7ffce000 with entry 7ffce000. filesize: 0x4010 memsize: 0x82d0 |
| Processing 122 relocs. Offset value of 0x7dfce000 |
| |
| |
| coreboot-4.8-1435-gdce4d465a6 Fri Sep 7 19:17:15 UTC 2018 postcar starting... |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 1a2c0 size 1ae2a |
| Decompressing stage fallback/ramstage @ 0x7ff7efc0 (318424 bytes) |
| Loading module at 7ff7f000 with entry 7ff7f000. filesize: 0x39830 memsize: 0x4db98 |
| Processing 3520 relocs. Offset value of 0x7fe7f000 |
| |
| |
| coreboot-4.8-1435-gdce4d465a6 Fri Sep 7 19:17:15 UTC 2018 ramstage starting... |
| Normal boot. |
| BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 |
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0 |
| Enumerating buses... |
| Show all devs... Before device enumeration. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 1 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| Compare with tree... |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| DOMAIN: 0000: enabled 1 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 1 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| I2C: 00:54: enabled 1 |
| I2C: 00:55: enabled 1 |
| I2C: 00:56: enabled 1 |
| I2C: 00:57: enabled 1 |
| I2C: 00:5c: enabled 1 |
| I2C: 00:5d: enabled 1 |
| I2C: 00:5e: enabled 1 |
| I2C: 00:5f: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| Root Device scanning... |
| root_dev_scan_bus for Root Device |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/0154] ops |
| PCI: 00:00.0 [8086/0154] enabled |
| PCI: 00:01.0 [8086/0000] bus ops |
| PCI: 00:01.0 [8086/0151] enabled |
| PCI: 00:02.0 [8086/0000] ops |
| PCI: 00:02.0 [8086/0166] enabled |
| PCI: 00:04.0 [8086/0153] enabled |
| PCI: 00:14.0 [8086/0000] ops |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0 [8086/1e3a] ops |
| PCI: 00:16.0 [8086/1e3a] enabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: Static device PCI: 00:16.3 not found, disabling it. |
| PCI: 00:19.0 [8086/1502] enabled |
| PCI: 00:1a.0 [8086/0000] ops |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/0000] ops |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0 [8086/0000] bus ops |
| PCI: 00:1c.0 [8086/1e10] enabled |
| PCI: 00:1c.1 [8086/0000] bus ops |
| PCI: 00:1c.1 [8086/1e12] enabled |
| PCI: 00:1c.2 [8086/0000] bus ops |
| PCI: 00:1c.2 [8086/1e14] enabled |
| PCI: 00:1c.3: Disabling device |
| PCI: 00:1c.4: Disabling device |
| PCI: 00:1c.4: check set enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: RPFN 0x76543210 -> 0xfedcb210 |
| PCI: 00:1d.0 [8086/0000] ops |
| PCI: 00:1d.0 [8086/1e26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1e.0 [8086/2448] bus ops |
| PCI: 00:1e.0 [8086/2448] disabled |
| PCI: 00:1f.0 [8086/0000] bus ops |
| PCI: 00:1f.0 [8086/1e55] enabled |
| PCI: 00:1f.2 [8086/0000] ops |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| PCI: 00:1f.2 [8086/1e01] enabled |
| PCI: 00:1f.3 [8086/0000] bus ops |
| PCI: 00:1f.3 [8086/1e22] enabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1e09] disabled No operations |
| PCI: 00:1f.6: Disabling device |
| PCI: 00:1f.6 [8086/1e24] disabled No operations |
| PCI: 00:01.0 scanning... |
| do_pci_scan_bridge for PCI: 00:01.0 |
| PCI: pci_scan_bus for bus 01 |
| PCI: 01:00.0 [10de/0ffc] enabled |
| PCI: 01:00.1 [10de/0e1b] enabled |
| Capability: type 0x01 @ 0x60 |
| Capability: type 0x05 @ 0x68 |
| Capability: type 0x10 @ 0x78 |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x01 @ 0x60 |
| Capability: type 0x05 @ 0x68 |
| Capability: type 0x10 @ 0x78 |
| Capability: type 0x0d @ 0x88 |
| Capability: type 0x01 @ 0x80 |
| Capability: type 0x05 @ 0x90 |
| Capability: type 0x10 @ 0xa0 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x01 @ 0x60 |
| Capability: type 0x05 @ 0x68 |
| Capability: type 0x10 @ 0x78 |
| Failed to enable LTR for dev = PCI: 01:00.0 |
| Capability: type 0x01 @ 0x60 |
| Capability: type 0x05 @ 0x68 |
| Capability: type 0x10 @ 0x78 |
| Failed to enable LTR for dev = PCI: 01:00.1 |
| scan_bus: scanning of bus PCI: 00:01.0 took 283 usecs |
| PCI: 00:1c.0 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.0 |
| PCI: pci_scan_bus for bus 02 |
| PCI: 02:00.0 [1180/e823] enabled |
| PCI: 02:00.1 [1180/e232] enabled |
| PCI: 02:00.2 [1180/e852] enabled |
| PCI: 02:00.3 [1180/e832] enabled |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.0 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.1 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.2 |
| Capability: type 0x05 @ 0x50 |
| Capability: type 0x01 @ 0x78 |
| Capability: type 0x10 @ 0x80 |
| Failed to enable LTR for dev = PCI: 02:00.3 |
| scan_bus: scanning of bus PCI: 00:1c.0 took 834 usecs |
| PCI: 00:1c.1 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.1 |
| PCI: pci_scan_bus for bus 03 |
| PCI: 03:00.0 [8086/0000] ops |
| PCI: 03:00.0 [8086/0085] enabled |
| Capability: type 0x01 @ 0xc8 |
| Capability: type 0x05 @ 0xd0 |
| Capability: type 0x10 @ 0xe0 |
| Capability: type 0x10 @ 0x40 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| Capability: type 0x01 @ 0xc8 |
| Capability: type 0x05 @ 0xd0 |
| Capability: type 0x10 @ 0xe0 |
| Failed to enable LTR for dev = PCI: 03:00.0 |
| scan_bus: scanning of bus PCI: 00:1c.1 took 267 usecs |
| PCI: 00:1c.2 scanning... |
| do_pci_scan_bridge for PCI: 00:1c.2 |
| PCI: pci_scan_bus for bus 04 |
| scan_bus: scanning of bus PCI: 00:1c.2 took 46 usecs |
| PCI: 00:1f.0 scanning... |
| scan_lpc_bus for PCI: 00:1f.0 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| PMH7: ID 05 Revision 12 |
| PNP: 00ff.1 enabled |
| PNP: 0c31.0 enabled |
| Clearing EC output queue... |
| Discarding a garbage byte: 0x55 |
| EC output queue has been cleared. |
| recv_ec_data: 0x47 |
| recv_ec_data: 0x34 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x39 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x16 |
| recv_ec_data: 0x03 |
| recv_ec_data: 0x30 |
| recv_ec_data: 0x11 |
| EC Firmware ID G4HT39WW-3.22, Version 3.01B |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0x40 |
| recv_ec_data: 0x90 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| H8: BDC installed |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0x60 |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0x70 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0x00 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0xa7 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| recv_ec_data: 0xa7 |
| recv_ec_data: 0x70 |
| PNP: 00ff.2 enabled |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| Hybrid graphics: Switching panel to integrated GPU. |
| PNP: 00ff.f disabled |
| scan_lpc_bus for PCI: 00:1f.0 done |
| scan_bus: scanning of bus PCI: 00:1f.0 took 4758 usecs |
| PCI: 00:1f.3 scanning... |
| scan_generic_bus for PCI: 00:1f.3 |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_generic_bus for PCI: 00:1f.3 done |
| scan_bus: scanning of bus PCI: 00:1f.3 took 20 usecs |
| scan_bus: scanning of bus DOMAIN: 0000 took 6719 usecs |
| root_dev_scan_bus for Root Device done |
| scan_bus: scanning of bus Root Device took 6726 usecs |
| done |
| FMAP: area RW_MRC_CACHE found @ 610000 (65536 bytes) |
| MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| flash size 0xc00000 bytes |
| SF: Detected Opaque HW-sequencing with sector size 0x100, total 0xc00000 |
| SF size 0xc00000 does not correspond to CONFIG_ROM_SIZE 0x800000!! |
| MRC: no data in 'RW_MRC_CACHE' |
| MRC: cache data 'RW_MRC_CACHE' needs update. |
| SF: Successfully written 2 bytes @ 0x610000 |
| SF: Successfully written 2 bytes @ 0x610002 |
| SF: Successfully written 1492 bytes @ 0x610060 |
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 6837 exit 17260 |
| found VGA at PCI: 00:02.0 |
| found VGA at PCI: 01:00.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Root Device read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 |
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| PCI: 00:01.0 read_resources bus 1 link: 0 |
| PCI: 00:01.0 read_resources bus 1 link: 0 done |
| PCI: 00:1c.0 read_resources bus 2 link: 0 |
| PCI: 00:1c.0 read_resources bus 2 link: 0 done |
| PCI: 00:1c.1 read_resources bus 3 link: 0 |
| PCI: 00:1c.1 read_resources bus 3 link: 0 done |
| PCI: 00:1c.2 read_resources bus 4 link: 0 |
| PCI: 00:1c.2 read_resources bus 4 link: 0 done |
| PCI: 00:1f.0 read_resources bus 0 link: 0 |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| PCI: 00:1f.3 read_resources bus 1 link: 0 |
| PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| DOMAIN: 0000 read_resources bus 0 link: 0 done |
| Root Device read_resources bus 0 link: 0 done |
| Done reading resources. |
| Show resources in subtree (Root Device)...After reading. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 child on link 0 PCI: 01:00.0 |
| PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 01:00.0 |
| PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 |
| PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14 |
| PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c |
| PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24 |
| PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 |
| PCI: 01:00.1 |
| PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 02:00.1 |
| PCI: 02:00.1 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 02:00.2 |
| PCI: 02:00.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| PCI: 02:00.3 |
| PCI: 02:00.3 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 10 |
| PCI: 00:1c.1 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 |
| PCI: 00:1c.2 child on link 0 NONE |
| PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| NONE |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 |
| NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 |
| NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PNP: 00ff.f |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 01:00.0 24 * [0x0 - 0x7f] io |
| PCI: 00:01.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.2 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:01.0 1c * [0x0 - 0xfff] io |
| PCI: 00:1c.2 1c * [0x1000 - 0x1fff] io |
| PCI: 00:02.0 20 * [0x2000 - 0x203f] io |
| PCI: 00:19.0 18 * [0x2040 - 0x205f] io |
| PCI: 00:1f.2 20 * [0x2060 - 0x207f] io |
| PCI: 00:1f.2 10 * [0x2080 - 0x2087] io |
| PCI: 00:1f.2 18 * [0x2088 - 0x208f] io |
| PCI: 00:1f.2 14 * [0x2090 - 0x2093] io |
| PCI: 00:1f.2 1c * [0x2094 - 0x2097] io |
| DOMAIN: 0000 io: base: 2098 size: 2098 align: 12 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff |
| PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 01:00.0 14 * [0x0 - 0xfffffff] prefmem |
| PCI: 01:00.0 1c * [0x10000000 - 0x11ffffff] prefmem |
| PCI: 00:01.0 prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 01:00.0 10 * [0x0 - 0xffffff] mem |
| PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem |
| PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem |
| PCI: 00:01.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 02:00.3 10 * [0x0 - 0x7ff] mem |
| PCI: 02:00.0 10 * [0x1000 - 0x10ff] mem |
| PCI: 02:00.1 10 * [0x2000 - 0x20ff] mem |
| PCI: 02:00.2 10 * [0x3000 - 0x30ff] mem |
| PCI: 00:1c.0 mem: base: 3100 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 03:00.0 10 * [0x0 - 0x1fff] mem |
| PCI: 00:1c.1 mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done |
| PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.2 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 00:1c.2 mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:01.0 24 * [0x0 - 0x11ffffff] prefmem |
| PCI: 00:02.0 18 * [0x20000000 - 0x2fffffff] prefmem |
| PCI: 00:01.0 20 * [0x30000000 - 0x310fffff] mem |
| PCI: 00:1c.2 24 * [0x31400000 - 0x31bfffff] prefmem |
| PCI: 00:1c.2 20 * [0x31c00000 - 0x323fffff] mem |
| PCI: 00:02.0 10 * [0x32400000 - 0x327fffff] mem |
| PCI: 00:1c.0 20 * [0x32800000 - 0x328fffff] mem |
| PCI: 00:1c.1 20 * [0x32900000 - 0x329fffff] mem |
| PCI: 00:19.0 10 * [0x32a00000 - 0x32a1ffff] mem |
| PCI: 00:14.0 10 * [0x32a20000 - 0x32a2ffff] mem |
| PCI: 00:04.0 10 * [0x32a30000 - 0x32a37fff] mem |
| PCI: 00:1b.0 10 * [0x32a38000 - 0x32a3bfff] mem |
| PCI: 00:19.0 14 * [0x32a3c000 - 0x32a3cfff] mem |
| PCI: 00:1f.2 24 * [0x32a3d000 - 0x32a3d7ff] mem |
| PCI: 00:1a.0 10 * [0x32a3e000 - 0x32a3e3ff] mem |
| PCI: 00:1d.0 10 * [0x32a3f000 - 0x32a3f3ff] mem |
| PCI: 00:1f.3 10 * [0x32a40000 - 0x32a400ff] mem |
| PCI: 00:16.0 10 * [0x32a41000 - 0x32a4100f] mem |
| DOMAIN: 0000 mem: base: 32a41010 size: 32a41010 align: 28 gran: 0 limit: ffffffff done |
| avoid_fixed_resources: DOMAIN: 0000 |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff |
| constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| skipping PNP: 00ff.2@60 fixed resource, size=0! |
| skipping PNP: 00ff.2@62 fixed resource, size=0! |
| skipping PNP: 00ff.2@64 fixed resource, size=0! |
| skipping PNP: 00ff.2@66 fixed resource, size=0! |
| avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff |
| avoid_fixed_resources:@DOMAIN: 0000 10000100 base b0000000 limit efffffff |
| Setting resources... |
| DOMAIN: 0000 io: base:167c size:2098 align:12 gran:0 limit:ffff |
| PCI: 00:01.0 1c * [0x2000 - 0x2fff] io |
| PCI: 00:1c.2 1c * [0x3000 - 0x3fff] io |
| PCI: 00:02.0 20 * [0x4000 - 0x403f] io |
| PCI: 00:19.0 18 * [0x4040 - 0x405f] io |
| PCI: 00:1f.2 20 * [0x4060 - 0x407f] io |
| PCI: 00:1f.2 10 * [0x4080 - 0x4087] io |
| PCI: 00:1f.2 18 * [0x4088 - 0x408f] io |
| PCI: 00:1f.2 14 * [0x4090 - 0x4093] io |
| PCI: 00:1f.2 1c * [0x4094 - 0x4097] io |
| DOMAIN: 0000 io: next_base: 4098 size: 2098 align: 12 gran: 0 done |
| PCI: 00:01.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff |
| PCI: 01:00.0 24 * [0x2000 - 0x207f] io |
| PCI: 00:01.0 io: next_base: 2080 size: 1000 align: 12 gran: 12 done |
| PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff |
| PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done |
| PCI: 00:1c.2 io: base:3000 size:1000 align:12 gran:12 limit:3fff |
| NONE 18 * [0x3000 - 0x3fff] io |
| PCI: 00:1c.2 io: next_base: 4000 size: 1000 align: 12 gran: 12 done |
| DOMAIN: 0000 mem: base:b0000000 size:32a41010 align:28 gran:0 limit:efffffff |
| PCI: 00:01.0 24 * [0xb0000000 - 0xc1ffffff] prefmem |
| PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem |
| PCI: 00:01.0 20 * [0xe0000000 - 0xe10fffff] mem |
| PCI: 00:1c.2 24 * [0xe1400000 - 0xe1bfffff] prefmem |
| PCI: 00:1c.2 20 * [0xe1c00000 - 0xe23fffff] mem |
| PCI: 00:02.0 10 * [0xe2400000 - 0xe27fffff] mem |
| PCI: 00:1c.0 20 * [0xe2800000 - 0xe28fffff] mem |
| PCI: 00:1c.1 20 * [0xe2900000 - 0xe29fffff] mem |
| PCI: 00:19.0 10 * [0xe2a00000 - 0xe2a1ffff] mem |
| PCI: 00:14.0 10 * [0xe2a20000 - 0xe2a2ffff] mem |
| PCI: 00:04.0 10 * [0xe2a30000 - 0xe2a37fff] mem |
| PCI: 00:1b.0 10 * [0xe2a38000 - 0xe2a3bfff] mem |
| PCI: 00:19.0 14 * [0xe2a3c000 - 0xe2a3cfff] mem |
| PCI: 00:1f.2 24 * [0xe2a3d000 - 0xe2a3d7ff] mem |
| PCI: 00:1a.0 10 * [0xe2a3e000 - 0xe2a3e3ff] mem |
| PCI: 00:1d.0 10 * [0xe2a3f000 - 0xe2a3f3ff] mem |
| PCI: 00:1f.3 10 * [0xe2a40000 - 0xe2a400ff] mem |
| PCI: 00:16.0 10 * [0xe2a41000 - 0xe2a4100f] mem |
| DOMAIN: 0000 mem: next_base: e2a41010 size: 32a41010 align: 28 gran: 0 done |
| PCI: 00:01.0 prefmem: base:b0000000 size:12000000 align:28 gran:20 limit:c1ffffff |
| PCI: 01:00.0 14 * [0xb0000000 - 0xbfffffff] prefmem |
| PCI: 01:00.0 1c * [0xc0000000 - 0xc1ffffff] prefmem |
| PCI: 00:01.0 prefmem: next_base: c2000000 size: 12000000 align: 28 gran: 20 done |
| PCI: 00:01.0 mem: base:e0000000 size:1100000 align:24 gran:20 limit:e10fffff |
| PCI: 01:00.0 10 * [0xe0000000 - 0xe0ffffff] mem |
| PCI: 01:00.0 30 * [0xe1000000 - 0xe107ffff] mem |
| PCI: 01:00.1 10 * [0xe1080000 - 0xe1083fff] mem |
| PCI: 00:01.0 mem: next_base: e1084000 size: 1100000 align: 24 gran: 20 done |
| PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.0 mem: base:e2800000 size:100000 align:20 gran:20 limit:e28fffff |
| PCI: 02:00.3 10 * [0xe2800000 - 0xe28007ff] mem |
| PCI: 02:00.0 10 * [0xe2801000 - 0xe28010ff] mem |
| PCI: 02:00.1 10 * [0xe2802000 - 0xe28020ff] mem |
| PCI: 02:00.2 10 * [0xe2803000 - 0xe28030ff] mem |
| PCI: 00:1c.0 mem: next_base: e2803100 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.1 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff |
| PCI: 00:1c.1 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done |
| PCI: 00:1c.1 mem: base:e2900000 size:100000 align:20 gran:20 limit:e29fffff |
| PCI: 03:00.0 10 * [0xe2900000 - 0xe2901fff] mem |
| PCI: 00:1c.1 mem: next_base: e2902000 size: 100000 align: 20 gran: 20 done |
| PCI: 00:1c.2 prefmem: base:e1400000 size:800000 align:22 gran:20 limit:e1bfffff |
| NONE 14 * [0xe1400000 - 0xe1bfffff] prefmem |
| PCI: 00:1c.2 prefmem: next_base: e1c00000 size: 800000 align: 22 gran: 20 done |
| PCI: 00:1c.2 mem: base:e1c00000 size:800000 align:22 gran:20 limit:e23fffff |
| NONE 10 * [0xe1c00000 - 0xe23fffff] mem |
| PCI: 00:1c.2 mem: next_base: e2400000 size: 800000 align: 22 gran: 20 done |
| Root Device assign_resources, bus 0 link: 0 |
| TOUUD 0x67d600000 TOLUD 0x82a00000 TOM 0x600000000 |
| MEBASE 0x7ffff00000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 22486M |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| PCI: 00:01.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 01 io |
| PCI: 00:01.0 24 <- [0x00b0000000 - 0x00c1ffffff] size 0x12000000 gran 0x14 bus 01 prefmem |
| PCI: 00:01.0 20 <- [0x00e0000000 - 0x00e10fffff] size 0x01100000 gran 0x14 bus 01 mem |
| PCI: 00:01.0 assign_resources, bus 1 link: 0 |
| PCI: 01:00.0 10 <- [0x00e0000000 - 0x00e0ffffff] size 0x01000000 gran 0x18 mem |
| PCI: 01:00.0 14 <- [0x00b0000000 - 0x00bfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 01:00.0 1c <- [0x00c0000000 - 0x00c1ffffff] size 0x02000000 gran 0x19 prefmem64 |
| PCI: 01:00.0 24 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io |
| PCI: 01:00.0 30 <- [0x00e1000000 - 0x00e107ffff] size 0x00080000 gran 0x13 romem |
| PCI: 01:00.1 10 <- [0x00e1080000 - 0x00e1083fff] size 0x00004000 gran 0x0e mem |
| PCI: 00:01.0 assign_resources, bus 1 link: 0 |
| PCI: 00:02.0 10 <- [0x00e2400000 - 0x00e27fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000004000 - 0x000000403f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x00e2a30000 - 0x00e2a37fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:14.0 10 <- [0x00e2a20000 - 0x00e2a2ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:16.0 10 <- [0x00e2a41000 - 0x00e2a4100f] size 0x00000010 gran 0x04 mem64 |
| PCI: 00:19.0 10 <- [0x00e2a00000 - 0x00e2a1ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00e2a3c000 - 0x00e2a3cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000004040 - 0x000000405f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 10 <- [0x00e2a3e000 - 0x00e2a3e3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00e2a38000 - 0x00e2a3bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.0 20 <- [0x00e2800000 - 0x00e28fffff] size 0x00100000 gran 0x14 bus 02 mem |
| PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| PCI: 02:00.0 10 <- [0x00e2801000 - 0x00e28010ff] size 0x00000100 gran 0x08 mem |
| PCI: 02:00.1 10 <- [0x00e2802000 - 0x00e28020ff] size 0x00000100 gran 0x08 mem |
| PCI: 02:00.2 10 <- [0x00e2803000 - 0x00e28030ff] size 0x00000100 gran 0x08 mem |
| PCI: 02:00.3 10 <- [0x00e2800000 - 0x00e28007ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1c.0 assign_resources, bus 2 link: 0 |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.1 20 <- [0x00e2900000 - 0x00e29fffff] size 0x00100000 gran 0x14 bus 03 mem |
| PCI: 00:1c.1 assign_resources, bus 3 link: 0 |
| PCI: 03:00.0 10 <- [0x00e2900000 - 0x00e2901fff] size 0x00002000 gran 0x0d mem64 |
| PCI: 00:1c.1 assign_resources, bus 3 link: 0 |
| PCI: 00:1c.2 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io |
| PCI: 00:1c.2 24 <- [0x00e1400000 - 0x00e1bfffff] size 0x00800000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.2 20 <- [0x00e1c00000 - 0x00e23fffff] size 0x00800000 gran 0x14 bus 04 mem |
| PCI: 00:1c.2 assign_resources, bus 4 link: 0 |
| NONE missing set_resources |
| PCI: 00:1c.2 assign_resources, bus 4 link: 0 |
| PCI: 00:1d.0 10 <- [0x00e2a3f000 - 0x00e2a3f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| PCI: 00:1f.2 10 <- [0x0000004080 - 0x0000004087] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000004090 - 0x0000004093] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000004088 - 0x000000408f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000004094 - 0x0000004097] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000004060 - 0x000000407f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00e2a3d000 - 0x00e2a3d7ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00e2a40000 - 0x00e2a400ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| Root Device assign_resources, bus 0 link: 0 |
| Done setting resources. |
| Show resources in subtree (Root Device)...After assigning values. |
| Root Device child on link 0 CPU_CLUSTER: 0 |
| CPU_CLUSTER: 0 child on link 0 APIC: 00 |
| APIC: 00 |
| APIC: acac |
| DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| DOMAIN: 0000 resource base 167c size 2098 align 12 gran 0 limit ffff flags 40040100 index 10000000 |
| DOMAIN: 0000 resource base b0000000 size 32a41010 align 28 gran 0 limit efffffff flags 40040200 index 10000100 |
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| DOMAIN: 0000 resource base 100000000 size 57d600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| PCI: 00:00.0 |
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| PCI: 00:01.0 child on link 0 PCI: 01:00.0 |
| PCI: 00:01.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c |
| PCI: 00:01.0 resource base b0000000 size 12000000 align 28 gran 20 limit c1ffffff flags 60081202 index 24 |
| PCI: 00:01.0 resource base e0000000 size 1100000 align 24 gran 20 limit e10fffff flags 60080202 index 20 |
| PCI: 01:00.0 |
| PCI: 01:00.0 resource base e0000000 size 1000000 align 24 gran 24 limit e0ffffff flags 60000200 index 10 |
| PCI: 01:00.0 resource base b0000000 size 10000000 align 28 gran 28 limit bfffffff flags 60001201 index 14 |
| PCI: 01:00.0 resource base c0000000 size 2000000 align 25 gran 25 limit c1ffffff flags 60001201 index 1c |
| PCI: 01:00.0 resource base 2000 size 80 align 7 gran 7 limit 207f flags 60000100 index 24 |
| PCI: 01:00.0 resource base e1000000 size 80000 align 19 gran 19 limit e107ffff flags 60002200 index 30 |
| PCI: 01:00.1 |
| PCI: 01:00.1 resource base e1080000 size 4000 align 14 gran 14 limit e1083fff flags 60000200 index 10 |
| PCI: 00:02.0 |
| PCI: 00:02.0 resource base e2400000 size 400000 align 22 gran 22 limit e27fffff flags 60000201 index 10 |
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 |
| PCI: 00:02.0 resource base 4000 size 40 align 6 gran 6 limit 403f flags 60000100 index 20 |
| PCI: 00:04.0 |
| PCI: 00:04.0 resource base e2a30000 size 8000 align 15 gran 15 limit e2a37fff flags 60000201 index 10 |
| PCI: 00:14.0 |
| PCI: 00:14.0 resource base e2a20000 size 10000 align 16 gran 16 limit e2a2ffff flags 60000201 index 10 |
| PCI: 00:16.0 |
| PCI: 00:16.0 resource base e2a41000 size 10 align 12 gran 4 limit e2a4100f flags 60000201 index 10 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:19.0 |
| PCI: 00:19.0 resource base e2a00000 size 20000 align 17 gran 17 limit e2a1ffff flags 60000200 index 10 |
| PCI: 00:19.0 resource base e2a3c000 size 1000 align 12 gran 12 limit e2a3cfff flags 60000200 index 14 |
| PCI: 00:19.0 resource base 4040 size 20 align 5 gran 5 limit 405f flags 60000100 index 18 |
| PCI: 00:1a.0 |
| PCI: 00:1a.0 resource base e2a3e000 size 400 align 12 gran 10 limit e2a3e3ff flags 60000200 index 10 |
| PCI: 00:1b.0 |
| PCI: 00:1b.0 resource base e2a38000 size 4000 align 14 gran 14 limit e2a3bfff flags 60000201 index 10 |
| PCI: 00:1c.0 child on link 0 PCI: 02:00.0 |
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.0 resource base e2800000 size 100000 align 20 gran 20 limit e28fffff flags 60080202 index 20 |
| PCI: 02:00.0 |
| PCI: 02:00.0 resource base e2801000 size 100 align 12 gran 8 limit e28010ff flags 60000200 index 10 |
| PCI: 02:00.1 |
| PCI: 02:00.1 resource base e2802000 size 100 align 12 gran 8 limit e28020ff flags 60000200 index 10 |
| PCI: 02:00.2 |
| PCI: 02:00.2 resource base e2803000 size 100 align 12 gran 8 limit e28030ff flags 60000200 index 10 |
| PCI: 02:00.3 |
| PCI: 02:00.3 resource base e2800000 size 800 align 12 gran 11 limit e28007ff flags 60000200 index 10 |
| PCI: 00:1c.1 child on link 0 PCI: 03:00.0 |
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c |
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 |
| PCI: 00:1c.1 resource base e2900000 size 100000 align 20 gran 20 limit e29fffff flags 60080202 index 20 |
| PCI: 03:00.0 |
| PCI: 03:00.0 resource base e2900000 size 2000 align 13 gran 13 limit e2901fff flags 60000201 index 10 |
| PCI: 00:1c.2 child on link 0 NONE |
| PCI: 00:1c.2 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c |
| PCI: 00:1c.2 resource base e1400000 size 800000 align 22 gran 20 limit e1bfffff flags 60081202 index 24 |
| PCI: 00:1c.2 resource base e1c00000 size 800000 align 22 gran 20 limit e23fffff flags 60080202 index 20 |
| NONE |
| NONE resource base e1c00000 size 800000 align 22 gran 22 limit e23fffff flags 40000200 index 10 |
| NONE resource base e1400000 size 800000 align 22 gran 22 limit e1bfffff flags 40001200 index 14 |
| NONE resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 40000100 index 18 |
| PCI: 00:1c.3 |
| PCI: 00:1c.4 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: 00:1d.0 |
| PCI: 00:1d.0 resource base e2a3f000 size 400 align 12 gran 10 limit e2a3f3ff flags 60000200 index 10 |
| PCI: 00:1e.0 |
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| PNP: 00ff.1 |
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 |
| PNP: 0c31.0 |
| PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| PNP: 00ff.2 |
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| PNP: 00ff.f |
| PCI: 00:1f.2 |
| PCI: 00:1f.2 resource base 4080 size 8 align 3 gran 3 limit 4087 flags 60000100 index 10 |
| PCI: 00:1f.2 resource base 4090 size 4 align 2 gran 2 limit 4093 flags 60000100 index 14 |
| PCI: 00:1f.2 resource base 4088 size 8 align 3 gran 3 limit 408f flags 60000100 index 18 |
| PCI: 00:1f.2 resource base 4094 size 4 align 2 gran 2 limit 4097 flags 60000100 index 1c |
| PCI: 00:1f.2 resource base 4060 size 20 align 5 gran 5 limit 407f flags 60000100 index 20 |
| PCI: 00:1f.2 resource base e2a3d000 size 800 align 12 gran 11 limit e2a3d7ff flags 60000200 index 24 |
| PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| PCI: 00:1f.3 resource base e2a40000 size 100 align 12 gran 8 limit e2a400ff flags 60000201 index 10 |
| I2C: 01:54 |
| I2C: 01:55 |
| I2C: 01:56 |
| I2C: 01:57 |
| I2C: 01:5c |
| I2C: 01:5d |
| I2C: 01:5e |
| I2C: 01:5f |
| PCI: 00:1f.5 |
| PCI: 00:1f.6 |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES times (us): entry 0 run 3362 exit 0 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 17aa/21f6 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:01.0 bridge ctrl <- 0003 |
| PCI: 00:01.0 subsystem <- 17aa/21f6 |
| PCI: 00:01.0 cmd <- 07 |
| PCI: 00:02.0 subsystem <- 17aa/21f5 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:14.0 subsystem <- 17aa/21f6 |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:16.0 subsystem <- 17aa/21f6 |
| PCI: 00:16.0 cmd <- 02 |
| PCI: 00:19.0 subsystem <- 17aa/21f3 |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 17aa/21f6 |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 17aa/21f6 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0003 |
| PCI: 00:1c.0 subsystem <- 17aa/21f6 |
| PCI: 00:1c.0 cmd <- 106 |
| PCI: 00:1c.1 bridge ctrl <- 0003 |
| PCI: 00:1c.1 subsystem <- 17aa/21f6 |
| PCI: 00:1c.1 cmd <- 106 |
| PCI: 00:1c.2 bridge ctrl <- 0003 |
| PCI: 00:1c.2 subsystem <- 17aa/21f6 |
| PCI: 00:1c.2 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 17aa/21f6 |
| PCI: 00:1d.0 cmd <- 102 |
| pch_decode_init |
| PCI: 00:1f.0 subsystem <- 17aa/21f6 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 17aa/21f6 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 17aa/21f6 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 01:00.0 cmd <- 03 |
| PCI: 01:00.1 cmd <- 02 |
| PCI: 02:00.0 subsystem <- 17aa/21f6 |
| PCI: 02:00.0 cmd <- 06 |
| PCI: 02:00.1 cmd <- 06 |
| PCI: 02:00.2 cmd <- 06 |
| PCI: 02:00.3 cmd <- 02 |
| PCI: 03:00.0 cmd <- 02 |
| done. |
| BS: BS_DEV_ENABLE times (us): entry 0 run 189 exit 0 |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=1, nvlocked=1 |
| TPM: setup succeeded |
| Initializing devices... |
| Root Device init ... |
| Root Device init finished in 0 usecs |
| CPU_CLUSTER: 0 init ... |
| start_eip=0x00001000, code_size=0x00000031 |
| Setting up SMI for CPU |
| Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 00038000. Will call 7ff9e73e(7ffc8a60) |
| Installing SMM handler to 0x80000000 |
| Loading module at 80010000 with entry 80011272. filesize: 0x4058 memsize: 0x8080 |
| Processing 225 relocs. Offset value of 0x80010000 |
| Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 |
| Processing 13 relocs. Offset value of 0x80008000 |
| SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd |
| SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd |
| SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd |
| SMM Module: placing jmp sequence at 80006800 rel16 0x17fd |
| SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd |
| SMM Module: stub loaded at 80008000. Will call 80011272(00000000) |
| Initializing southbridge SMI... ... pmbase = 0x0500 |
| |
| SMI_STS: MCSMI PM1 |
| PM1_STS: WAK PWRBTN TMROF |
| PM1_EN: 100 |
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW TCO_SCI |
| ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI5 GPI4 GPI3 GPI1 GPI0 |
| TCO_STS: |
| ... raise SMI# |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| Locking SMM. |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x00000000b0000000 size 0x30000000 type 0 |
| 0x00000000b0000000 - 0x00000000c2000000 size 0x12000000 type 1 |
| 0x00000000c2000000 - 0x00000000d0000000 size 0x0e000000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x000000067d600000 size 0x57d600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 9/7. |
| MTRR: UC selected as default type. |
| MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| MTRR: 1 base 0x00000000b0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x00000000c0000000 mask 0x0000000ffe000000 type 1 |
| MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 4 base 0x0000000100000000 mask 0x0000000f00000000 type 6 |
| MTRR: 5 base 0x0000000200000000 mask 0x0000000e00000000 type 6 |
| MTRR: 6 base 0x0000000400000000 mask 0x0000000c00000000 type 6 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x00 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| Turbo is available but hidden |
| Turbo has been enabled |
| CPU: 0 has 4 cores, 2 threads per core |
| CPU: 0 has core 1 |
| CPU1: stack_base 7ffbf000, stack_end 7ffbfff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 1. |
| After apic_write. |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 1. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| Initializing CPU #1 |
| CPU: 0 has core 2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x01 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #1 initialized |
| CPU2: stack_base 7ffbe000, stack_end 7ffbeff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 2. |
| After apic_write. |
| In relocation handler: cpu 2 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 2. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 3 |
| Initializing CPU #2 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x02 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #2 initialized |
| CPU3: stack_base 7ffbd000, stack_end 7ffbdff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 3. |
| After apic_write. |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 3. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 4 |
| CPU4: stack_base 7ffbc000, stack_end 7ffbcff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 4. |
| After apic_write. |
| In relocation handler: cpu 4 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 4. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 5 |
| CPU5: stack_base 7ffbb000, stack_end 7ffbbff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 5. |
| After apic_write. |
| In relocation handler: cpu 5 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 5. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 6 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x03 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #3 initialized |
| CPU6: stack_base 7ffba000, stack_end 7ffbaff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 6. |
| After apic_write. |
| In relocation handler: cpu 6 |
| Startup point 1. |
| Waiting for send to finish... |
| +New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00 |
| Sending STARTUP #2 to 6. |
| After apic_write. |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU: 0 has core 7 |
| Initializing CPU #6 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x06 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #6 initialized |
| CPU7: stack_base 7ffb9000, stack_end 7ffb9ff8 |
| Asserting INIT. |
| Waiting for send to finish... |
| +Deasserting INIT. |
| Waiting for send to finish... |
| +#startup loops: 2. |
| Sending STARTUP #1 to 7. |
| After apic_write. |
| In relocation handler: cpu 7 |
| New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Startup point 1. |
| Waiting for send to finish... |
| +Sending STARTUP #2 to 7. |
| After apic_write. |
| Startup point 1. |
| Waiting for send to finish... |
| +After Startup. |
| CPU #0 initialized |
| Waiting for 3 CPUS to stop |
| Initializing CPU #7 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x07 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #7 initialized |
| Waiting for 2 CPUS to stop |
| Initializing CPU #4 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x0 |
| microcode: updated to revision 0x1f date=2018-02-07 |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x04 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #4 initialized |
| Waiting for 1 CPUS to stop |
| Initializing CPU #5 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| Enabling cache |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 13e40 size 6400 |
| microcode: sig=0x306a9 pf=0x10 revision=0x1f |
| CPU: Intel(R) Core(TM) i7-3740QM CPU @ 2.70GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| call enable_fixed_mtrr() |
| CPU physical address size: 36 bits |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| Setting up local APIC... apic_id: 0x05 done. |
| VMX status: enabled, locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2700 |
| CPU #5 initialized |
| All AP CPUs stopped (5346 loops) |
| CPU0: stack: 7ffc0000 - 7ffc1000, lowest used address 7ffc0a90, stack used: 1392 bytes |
| CPU1: stack: 7ffbf000 - 7ffc0000, lowest used address 7ffbfc80, stack used: 896 bytes |
| CPU2: stack: 7ffbe000 - 7ffbf000, lowest used address 7ffbec80, stack used: 896 bytes |
| CPU3: stack: 7ffbd000 - 7ffbe000, lowest used address 7ffbdc80, stack used: 896 bytes |
| CPU4: stack: 7ffbc000 - 7ffbd000, lowest used address 7ffbcc80, stack used: 896 bytes |
| CPU5: stack: 7ffbb000 - 7ffbc000, lowest used address 7ffbbc80, stack used: 896 bytes |
| CPU6: stack: 7ffba000 - 7ffbb000, lowest used address 7ffbac80, stack used: 896 bytes |
| CPU7: stack: 7ffb9000 - 7ffba000, lowest used address 7ffb9c80, stack used: 896 bytes |
| CPU_CLUSTER: 0 init finished in 219834 usecs |
| PCI: 00:00.0 init ... |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG60. |
| Disabling Device 7. |
| Set BIOS_RESET_CPL |
| CPU TDP: 45 Watts |
| PCI: 00:00.0 init finished in 1014 usecs |
| PCI: 00:01.0 init ... |
| PCI: 00:01.0 init finished in 1 usecs |
| PCI: 00:02.0 init ... |
| GT Power Management Init |
| IVB GT2 35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| Initializing VGA without OPROM. |
| |
| [0.379234] CONFIG => |
| [0.379235] (Primary => |
| [0.379235] (Port => Internal, |
| [0.379236] Framebuffer => |
| [0.379236] (Width => 640, |
| [0.379237] Height => 400, |
| [0.379237] Start_X => 0, |
| [0.379238] Start_Y => 0, |
| [0.379238] Stride => 1, |
| [0.379239] V_Stride => 1, |
| [0.379239] Tiling => Linear , |
| [0.379240] Rotation => No_Rotation, |
| [0.379240] Offset => 0xffffffff, |
| [0.379241] BPC => 8), |
| [0.379241] Mode => |
| [0.379242] (Dotclock => 139000000, |
| [0.379242] H_Visible => 1920, |
| [0.379243] H_Sync_Begin => 1980, |
| [0.379243] H_Sync_End => 2028, |
| [0.379244] H_Total => 2050, |
| [0.379244] V_Visible => 1080, |
| [0.379245] V_Sync_Begin => 1090, |
| [0.379245] V_Sync_End => 1100, |
| [0.379246] V_Total => 1130, |
| [0.379246] H_Sync_Active_High => False, |
| [0.379247] V_Sync_Active_High => False, |
| [0.379247] BPC => 5)), |
| [0.379248] Secondary => |
| [0.379248] (Port => Disabled, |
| [0.379249] Framebuffer => |
| [0.379249] (Width => 1, |
| [0.379250] Height => 1, |
| [0.379250] Start_X => 0, |
| [0.379251] Start_Y => 0, |
| [0.379251] Stride => 1, |
| [0.379252] V_Stride => 1, |
| [0.379252] Tiling => Linear , |
| [0.379253] Rotation => No_Rotation, |
| [0.379253] Offset => 0x00000000, |
| [0.379254] BPC => 8), |
| [0.379254] Mode => |
| [0.379255] (Dotclock => 24000000, |
| [0.379255] H_Visible => 1, |
| [0.379256] H_Sync_Begin => 1, |
| [0.379256] H_Sync_End => 1, |
| [0.379257] H_Total => 1, |
| [0.379257] V_Visible => 1, |
| [0.379258] V_Sync_Begin => 1, |
| [0.379258] V_Sync_End => 1, |
| [0.379259] V_Total => 1, |
| [0.379259] H_Sync_Active_High => False, |
| [0.379260] V_Sync_Active_High => False, |
| [0.379260] BPC => 5)), |
| [0.379261] Tertiary => |
| [0.379261] (Port => Disabled, |
| [0.379262] Framebuffer => |
| [0.379262] (Width => 1, |
| [0.379263] Height => 1, |
| [0.379263] Start_X => 0, |
| [0.379264] Start_Y => 0, |
| [0.379264] Stride => 1, |
| [0.379265] V_Stride => 1, |
| [0.379265] Tiling => Linear , |
| [0.379266] Rotation => No_Rotation, |
| [0.379266] Offset => 0x00000000, |
| [0.379267] BPC => 8), |
| [0.379267] Mode => |
| [0.379268] (Dotclock => 24000000, |
| [0.379268] H_Visible => 1, |
| [0.379269] H_Sync_Begin => 1, |
| [0.379269] H_Sync_End => 1, |
| [0.379270] H_Total => 1, |
| [0.379270] V_Visible => 1, |
| [0.379271] V_Sync_Begin => 1, |
| [0.379271] V_Sync_End => 1, |
| [0.379272] V_Total => 1, |
| [0.379272] H_Sync_Active_High => False, |
| [0.379273] V_Sync_Active_High => False, |
| [0.379273] BPC => 5))); |
| PCI: 00:02.0 init finished in 67263 usecs |
| PCI: 00:04.0 init ... |
| PCI: 00:04.0 init finished in 1 usecs |
| PCI: 00:14.0 init ... |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 7 usecs |
| PCI: 00:16.0 init ... |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Initializing |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Clean Moff->Mx wake |
| ME: Progress Phase State : Check to see if straps say ME DISABLED |
| intel_me_path: mbp is not ready! |
| ME: BIOS path: Error |
| PCI: 00:16.0 init finished in 17 usecs |
| PCI: 00:19.0 init ... |
| PCI: 00:19.0 init finished in 1 usecs |
| PCI: 00:1a.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 13 usecs |
| PCI: 00:1b.0 init ... |
| Azalia: base = e2a38000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: verb_size: 16 |
| Azalia: verb loaded. |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 10ec0269 |
| Azalia: verb_size: 72 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 5805 usecs |
| PCI: 00:1c.0 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 10 usecs |
| PCI: 00:1c.1 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 11 usecs |
| PCI: 00:1c.2 init ... |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.2 init finished in 14 usecs |
| PCI: 00:1d.0 init ... |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 13 usecs |
| PCI: 00:1f.0 init ... |
| pch: lpc_init |
| PCH: detected QM77, device id: 0x1e55, rev id 0x4 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| IOAPIC: Dumping registers |
| reg 0x0000: 0x02000000 |
| reg 0x0001: 0x00170020 |
| reg 0x0002: 0x00170020 |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| Set power off after power failure. |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| NMI sources enabled. |
| PantherPoint PM init |
| rtc_failed = 0x0 |
| RTC Init |
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 1297 usecs |
| PCI: 00:1f.2 init ... |
| SATA: Initializing... |
| FMAP: area COREBOOT found @ 620000 (1966080 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| SATA: Controller in AHCI mode. |
| ABAR: e2a3d000 |
| PCI: 00:1f.2 init finished in 343 usecs |
| PCI: 00:1f.3 init ... |
| PCI: 00:1f.3 init finished in 7 usecs |
| PCI: 01:00.0 init ... |
| PCI: 01:00.0 init finished in 1 usecs |
| PCI: 01:00.1 init ... |
| PCI: 01:00.1 init finished in 1 usecs |
| PCI: 02:00.0 init ... |
| PCI: 02:00.0 init finished in 1 usecs |
| PCI: 02:00.1 init ... |
| PCI: 02:00.1 init finished in 1 usecs |
| PCI: 02:00.2 init ... |
| PCI: 02:00.2 init finished in 1 usecs |
| PCI: 02:00.3 init ... |
| PCI: 02:00.3 init finished in 1 usecs |
| PCI: 03:00.0 init ... |
| PCI: 03:00.0 init finished in 1 usecs |
| PNP: 00ff.2 init ... |
| Keyboard init... |
| Keyboard controller output buffer result timeout |
| PS/2 keyboard initialized on primary channel |
| PNP: 00ff.2 init finished in 508294 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ... |
| I2C: 01:54 init finished in 2 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ... |
| I2C: 01:55 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ... |
| I2C: 01:56 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ... |
| I2C: 01:57 init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ... |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 25925 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ... |
| I2C: 01:5d init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ... |
| I2C: 01:5e init finished in 1 usecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ... |
| I2C: 01:5f init finished in 1 usecs |
| Devices initialized |
| Show all devs... After init. |
| Root Device: enabled 1 |
| CPU_CLUSTER: 0: enabled 1 |
| DOMAIN: 0000: enabled 1 |
| APIC: 00: enabled 1 |
| APIC: acac: enabled 0 |
| PCI: 00:14.0: enabled 1 |
| PCI: 00:16.0: enabled 1 |
| PCI: 00:16.1: enabled 0 |
| PCI: 00:16.2: enabled 0 |
| PCI: 00:16.3: enabled 0 |
| PCI: 00:19.0: enabled 1 |
| PCI: 00:1a.0: enabled 1 |
| PCI: 00:1b.0: enabled 1 |
| PCI: 00:1c.0: enabled 1 |
| PCI: 00:1c.1: enabled 1 |
| PCI: 00:1c.2: enabled 1 |
| PCI: 00:1c.3: enabled 0 |
| PCI: 00:1c.4: enabled 0 |
| PCI: 00:1c.5: enabled 0 |
| PCI: 00:1c.6: enabled 0 |
| PCI: 00:1c.7: enabled 0 |
| PCI: 00:1d.0: enabled 1 |
| PCI: 00:1e.0: enabled 0 |
| PCI: 00:1f.0: enabled 1 |
| PCI: 00:1f.2: enabled 1 |
| PCI: 00:1f.3: enabled 1 |
| PCI: 00:1f.5: enabled 0 |
| PCI: 00:1f.6: enabled 0 |
| PCI: 00:00.0: enabled 1 |
| PCI: 00:01.0: enabled 1 |
| PCI: 00:02.0: enabled 1 |
| PCI: 02:00.0: enabled 1 |
| PNP: 00ff.1: enabled 1 |
| PNP: 0c31.0: enabled 1 |
| PNP: 00ff.2: enabled 1 |
| PNP: 00ff.f: enabled 0 |
| I2C: 01:54: enabled 1 |
| I2C: 01:55: enabled 1 |
| I2C: 01:56: enabled 1 |
| I2C: 01:57: enabled 1 |
| I2C: 01:5c: enabled 1 |
| I2C: 01:5d: enabled 1 |
| I2C: 01:5e: enabled 1 |
| I2C: 01:5f: enabled 1 |
| PCI: 00:04.0: enabled 1 |
| PCI: 01:00.0: enabled 1 |
| PCI: 01:00.1: enabled 1 |
| PCI: 02:00.1: enabled 1 |
| PCI: 02:00.2: enabled 1 |
| PCI: 02:00.3: enabled 1 |
| PCI: 03:00.0: enabled 1 |
| NONE: enabled 1 |
| APIC: 01: enabled 1 |
| APIC: 02: enabled 1 |
| APIC: 03: enabled 1 |
| APIC: 04: enabled 1 |
| APIC: 05: enabled 1 |
| APIC: 06: enabled 1 |
| APIC: 07: enabled 1 |
| BS: BS_DEV_INIT times (us): entry 64049 run 829924 exit 0 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| BS: BS_POST_DEVICE times (us): entry 0 run 258 exit 0 |
| BS: BS_OS_RESUME_CHECK times (us): entry 1 run 0 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 3a980 size 3892 |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff42000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Generating ACPI PIRQ entries |
| ACPI_PIRQ_GEN: PCI: 00:01.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:04.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0 |
| ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=5 |
| ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 |
| ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=1 |
| ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=7 |
| Found 1 CPU(s) with 8 core(s) each. |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| PSS: 2701MHz power 45000 control 0x2500 status 0x2500 |
| PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 |
| PSS: 2400MHz power 38601 control 0x1800 status 0x1800 |
| PSS: 2200MHz power 34542 control 0x1600 status 0x1600 |
| PSS: 2000MHz power 30669 control 0x1400 status 0x1400 |
| PSS: 1800MHz power 26973 control 0x1200 status 0x1200 |
| PSS: 1600MHz power 23389 control 0x1000 status 0x1000 |
| PSS: 1400MHz power 19976 control 0xe00 status 0xe00 |
| PSS: 1200MHz power 16703 control 0xc00 status 0xc00 |
| \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: * H8 |
| H8: BDC installed |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'pci10de,0ffc.rom' |
| CBFS: Found @ offset bdf00 size 26000 |
| In CBFS, ROM address for PCI: 01:00.0 = ffeddf48 |
| PCI expansion ROM, signature 0xaa55, INIT size 0x16200, data ptr 0x0190 |
| PCI ROM image, vendor ID 10de, device ID 0ffb, |
| ID mismatch: vendor ID 10de, device ID 0ffb |
| PCI: 01:00.0: Missing PCI Option ROM |
| \_SB.PCI0.RP02.WIFI: PCI: 03:00.0 |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 7ff31000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff48d70 |
| ACPI: * DMAR |
| ACPI: added table 6/32, length now 60 |
| current = 7ff48e20 |
| ACPI: * HPET |
| ACPI: added table 7/32, length now 64 |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Found @ offset 358c0 size 58a |
| Found a VBT of 4459 bytes after decompression |
| GMA: Found VBT in CBFS |
| GMA: Found valid VBT in CBFS |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'pci10de,0ffc.rom' |
| CBFS: Found @ offset bdf00 size 26000 |
| In CBFS, ROM address for PCI: 01:00.0 = ffeddf48 |
| PCI expansion ROM, signature 0xaa55, INIT size 0x16200, data ptr 0x0190 |
| PCI ROM image, vendor ID 10de, device ID 0ffb, |
| ID mismatch: vendor ID 10de, device ID 0ffb |
| ACPI: done. |
| ACPI tables: 36448 bytes. |
| smbios_write_tables: 7ff30000 |
| recv_ec_data: 0x47 |
| recv_ec_data: 0x34 |
| recv_ec_data: 0x48 |
| recv_ec_data: 0x54 |
| recv_ec_data: 0x33 |
| recv_ec_data: 0x39 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x57 |
| recv_ec_data: 0x16 |
| recv_ec_data: 0x03 |
| Create SMBIOS type 17 |
| PCI: 03:00.0 (unknown) |
| SMBIOS tables: 867 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 1fe8 |
| Writing coreboot table at 0x7ff66000 |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 35ec0 size 79c |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff2ffff: RAM |
| 4. 000000007ff30000-000000007ff7efff: CONFIGURATION TABLES |
| 5. 000000007ff7f000-000000007ffccfff: RAMSTAGE |
| 6. 000000007ffcd000-000000007fffffff: CONFIGURATION TABLES |
| 7. 0000000080000000-00000000829fffff: RESERVED |
| 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| 9. 00000000fed40000-00000000fed44fff: RESERVED |
| 10. 00000000fed90000-00000000fed91fff: RESERVED |
| 11. 0000000100000000-000000067d5fffff: RAM |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| Wrote coreboot table at: 7ff66000, 0xb08 bytes, checksum e15e |
| coreboot table: 2848 bytes. |
| IMD ROOT 0. 7ffff000 00001000 |
| IMD SMALL 1. 7fffe000 00001000 |
| CONSOLE 2. 7ffde000 00020000 |
| TIME STAMP 3. 7ffdd000 00000910 |
| MRC DATA 4. 7ffdc000 000005d4 |
| ROMSTG STCK 5. 7ffd7000 00005000 |
| AFTER CAR 6. 7ffcd000 0000a000 |
| RAMSTAGE 7. 7ff7e000 0004f000 |
| SMM BACKUP 8. 7ff6e000 00010000 |
| COREBOOT 9. 7ff66000 00008000 |
| ACPI 10. 7ff42000 00024000 |
| ACPI GNVS 11. 7ff41000 00001000 |
| TCPA TCGLOG12. 7ff31000 00010000 |
| SMBIOS 13. 7ff30000 00000800 |
| IMD small region: |
| IMD ROOT 0. 7fffec00 00000400 |
| MEM INFO 1. 7fffeaa0 00000149 |
| ROMSTAGE 2. 7fffea80 00000004 |
| COREBOOTFWD 3. 7fffea40 00000028 |
| BS: BS_WRITE_TABLES times (us): entry 0 run 31763 exit 0 |
| CBFS: 'Master Header Locator' located CBFS at [620000:7fffc0) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 5a500 size 6399c |
| Loading segment from ROM address 0xffe7a538 |
| code (compression=1) |
| New segment dstaddr 0x8200 memsize 0x1b988 srcaddr 0xffe7a58c filesize 0x99fd |
| Loading segment from ROM address 0xffe7a554 |
| code (compression=1) |
| New segment dstaddr 0x100000 memsize 0x125694 srcaddr 0xffe83f89 filesize 0x59f4b |
| Loading segment from ROM address 0xffe7a570 |
| Entry Point 0x00008200 |
| Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000001b988 filesz: 0x00000000000099fd |
| lb: [0x000000007ff7f000, 0x000000007ffccb98) |
| Post relocation: addr: 0x0000000000008200 memsz: 0x000000000001b988 filesz: 0x00000000000099fd |
| using LZMA |
| [ 0x00008200, 0001c143, 0x00023b88) <- ffe7a58c |
| Clearing Segment: addr: 0x000000000001c143 memsz: 0x0000000000007a45 |
| dest 00008200, end 00023b88, bouncebuffer ffffffff |
| Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000125694 filesz: 0x0000000000059f4b |
| lb: [0x000000007ff7f000, 0x000000007ffccb98) |
| Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000125694 filesz: 0x0000000000059f4b |
| using LZMA |
| [ 0x00100000, 00225694, 0x00225694) <- ffe83f89 |
| dest 00100000, end 00225694, bouncebuffer ffffffff |
| Loaded segments |
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 155790 exit 0 |
| PCH: watchdog disabled |
| Jumping to boot code at 00008200(7ff66000) |
| CPU0: stack: 7ffc0000 - 7ffc1000, lowest used address 7ffc0a04, stack used: 1532 bytes |
| error: no suitable video mode found. |
|
error: file `/boot/grub/i386-coreboot/jpeg.mod' not found. |
|
error: file `/boot/grub/i386-coreboot/gfxterm_background.mod' not found. |
|
error: file `/dejavusansmono.pf2' not found. |
|
error: file `/boot/grub/layouts/usqwerty.gkb' not found. |
|
GNU GRUB version 2.02 |
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|
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+----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
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Press enter to boot the selected OS, `e' to edit the commands |
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before booting or `c' for a command-line. *Load Operating System (incl. fully encrypted disks) [o] ? Search ISOLINUX menu (AHCI) [a] ? Search ISOLINUX menu (USB) [u] ? Search ISOLINUX menu (CD/DVD) [d] ? Load test configuration (grubtest.cfg) inside of CBFS [t] ? Search for GRUB2 configuration on external media [s] ? Poweroff [p] ? Reboot [r] ? ? ? ? ? The highlighted entry will be executed automatically in 1s. er |
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ror: file `/boot/grub/i386-coreboot/usbserial_ftdi.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_pl2303.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_ftdi.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_pl2303.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_ftdi.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_pl2303.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_ftdi.mod' not found. |
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error: file `/boot/grub/i386-coreboot/usbserial_pl2303.mod' not found. |
|
error: file `/boot/grub/fonts/unicode.pf2' not found. |
|
error: no suitable video mode found. |
|
GNU GRUB version 2.02 |
|
|
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+----------------------------------------------------------------------------+||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. |
|
Press enter to boot the selected OS, `e' to edit the commands |
|
before booting or `c' for a command-line. ESC to return |
|
previous menu. *Gentoo GNU/Linux ? Advanced options for Gentoo GNU/Linux ? MemTest86 ? Memtest86+ ? ? ? ? ? ? ? ? The highlighted entry will be executed automatically in 5s. error: file `/boot/grub/i386-coreboot/all_video.mod' not found. |
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Loading Linux 4.16.13-gentoo ... |
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Loading initial ramdisk ... |
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Press any key to continue... |
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