blob: a18b986e90f2f275b1ea9aad45c2e0c8d655a920 [file] [log] [blame]
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20160108-64
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of ssdt.dat, Fri Nov 18 18:30:02 2016
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000078A (1930)
* Revision 0x02
* Checksum 0x03
* OEM ID "CORE "
* OEM Table ID "COREBOOT"
* OEM Revision 0x0000002A (42)
* Compiler ID "CORE"
* Compiler Version 0x0000002A (42)
*/
DefinitionBlock ("ssdt.aml", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A)
{
External (PPCM, IntObj)
External (TLVL, IntObj)
Device (CTBL)
{
Name (_HID, "GOOGCB00") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadOnly,
0x7ADD2000, // Address Base
0x00008000, // Address Length
)
})
}
Processor (\_PR.CP00, 0x00, 0x00000400, 0x06)
{
Name (_PCT, Package (0x02) // _PCT: Performance Control
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
}
})
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (PPCM) /* External reference */
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
0x00,
0x00000000,
0x000000FE,
0x00000001
}
})
Name (_PSS, Package (0x08) // _PSS: Performance Supported States
{
Package (0x06)
{
0x000005BA,
0x0002D2A8,
0x0000000A,
0x0000000A,
0x00000B3E,
0x00000B3E
},
Package (0x06)
{
0x00000535,
0x00028903,
0x0000000A,
0x0000000A,
0x00000A3C,
0x00000A3C
},
Package (0x06)
{
0x000004AF,
0x00024189,
0x0000000A,
0x0000000A,
0x00000939,
0x00000939
},
Package (0x06)
{
0x0000042A,
0x0001FB82,
0x0000000A,
0x0000000A,
0x00000836,
0x00000836
},
Package (0x06)
{
0x000003A5,
0x0001B677,
0x0000000A,
0x0000000A,
0x00000734,
0x00000734
},
Package (0x06)
{
0x0000031F,
0x00017365,
0x0000000A,
0x0000000A,
0x00000631,
0x00000631
},
Package (0x06)
{
0x0000029A,
0x000131C6,
0x0000000A,
0x0000000A,
0x0000052E,
0x0000052E
},
Package (0x06)
{
0x00000215,
0x0000F199,
0x0000000A,
0x0000000A,
0x0000042B,
0x0000042B
}
})
Name (_CST, Package (0x04) // _CST: C-States
{
0x00000003,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x00000001,
0x00000001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000051, // Address
0x01, // Access Size
)
},
0x00000002,
0x000001F4,
0x0000000A
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000052, // Address
0x01, // Access Size
)
},
0x00000003,
0x000005DC,
0x0000000A
}
})
Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
{
Package (0x05)
{
0x05,
0x00,
0x00000000,
0x000000FC,
0x00000002
}
})
Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
}
})
Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
{
Return (\TLVL) /* External reference */
}
Name (_TSS, Package (0x08) // _TSS: Throttling Supported States
{
Package (0x05)
{
0x00000064,
0x000003E8,
0x00000000,
0x00000000,
0x00000000
},
Package (0x05)
{
0x00000058,
0x0000036B,
0x00000000,
0x0000001E,
0x00000000
},
Package (0x05)
{
0x0000004B,
0x000002EE,
0x00000000,
0x0000001C,
0x00000000
},
Package (0x05)
{
0x0000003F,
0x00000271,
0x00000000,
0x0000001A,
0x00000000
},
Package (0x05)
{
0x00000032,
0x000001F4,
0x00000000,
0x00000018,
0x00000000
},
Package (0x05)
{
0x00000026,
0x00000177,
0x00000000,
0x00000016,
0x00000000
},
Package (0x05)
{
0x00000019,
0x000000FA,
0x00000000,
0x00000014,
0x00000000
},
Package (0x05)
{
0x0000000D,
0x0000007D,
0x00000000,
0x00000012,
0x00000000
}
})
}
Processor (\_PR.CP01, 0x01, 0x00000000, 0x00)
{
Name (_PCT, Package (0x02) // _PCT: Performance Control
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
}
})
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (PPCM) /* External reference */
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
0x00,
0x00000001,
0x000000FE,
0x00000001
}
})
Name (_PSS, Package (0x08) // _PSS: Performance Supported States
{
Package (0x06)
{
0x000005BA,
0x0002D2A8,
0x0000000A,
0x0000000A,
0x00000B3E,
0x00000B3E
},
Package (0x06)
{
0x00000535,
0x00028903,
0x0000000A,
0x0000000A,
0x00000A3C,
0x00000A3C
},
Package (0x06)
{
0x000004AF,
0x00024189,
0x0000000A,
0x0000000A,
0x00000939,
0x00000939
},
Package (0x06)
{
0x0000042A,
0x0001FB82,
0x0000000A,
0x0000000A,
0x00000836,
0x00000836
},
Package (0x06)
{
0x000003A5,
0x0001B677,
0x0000000A,
0x0000000A,
0x00000734,
0x00000734
},
Package (0x06)
{
0x0000031F,
0x00017365,
0x0000000A,
0x0000000A,
0x00000631,
0x00000631
},
Package (0x06)
{
0x0000029A,
0x000131C6,
0x0000000A,
0x0000000A,
0x0000052E,
0x0000052E
},
Package (0x06)
{
0x00000215,
0x0000F199,
0x0000000A,
0x0000000A,
0x0000042B,
0x0000042B
}
})
Name (_CST, Package (0x04) // _CST: C-States
{
0x00000003,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x00000001,
0x00000001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000051, // Address
0x01, // Access Size
)
},
0x00000002,
0x000001F4,
0x0000000A
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000052, // Address
0x01, // Access Size
)
},
0x00000003,
0x000005DC,
0x0000000A
}
})
Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
{
Package (0x05)
{
0x05,
0x00,
0x00000001,
0x000000FC,
0x00000002
}
})
Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
}
})
Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
{
Return (\TLVL) /* External reference */
}
Name (_TSS, Package (0x08) // _TSS: Throttling Supported States
{
Package (0x05)
{
0x00000064,
0x000003E8,
0x00000000,
0x00000000,
0x00000000
},
Package (0x05)
{
0x00000058,
0x0000036B,
0x00000000,
0x0000001E,
0x00000000
},
Package (0x05)
{
0x0000004B,
0x000002EE,
0x00000000,
0x0000001C,
0x00000000
},
Package (0x05)
{
0x0000003F,
0x00000271,
0x00000000,
0x0000001A,
0x00000000
},
Package (0x05)
{
0x00000032,
0x000001F4,
0x00000000,
0x00000018,
0x00000000
},
Package (0x05)
{
0x00000026,
0x00000177,
0x00000000,
0x00000016,
0x00000000
},
Package (0x05)
{
0x00000019,
0x000000FA,
0x00000000,
0x00000014,
0x00000000
},
Package (0x05)
{
0x0000000D,
0x0000007D,
0x00000000,
0x00000012,
0x00000000
}
})
}
}