| CPU: ID 0x6fd, Processor Type 0x0, Family 0x6, Model 0xf, Stepping 0xd |
| Northbridge: 8086:2770 (945P) |
| Southbridge: 8086:27b8 (ICH7) |
| IGD: 8086:2772 (unknown) |
| |
| ===================== SHARED MSRs (All Cores) ===================== |
| MSR 0x00000017 = 0x00000000:0x8B008A27 (IA32_PLATFORM_ID) |
| MSR 0x0000002A = 0x00000000:0x42880000 (EBL_CR_POWERON) |
| MSR 0x0000003F = 0x00000000:0x000000EA (IA32_TEMPERATURE_OFFSET) |
| MSR 0x000000A8 = 0x00000000:0x0000061D (EMTTM_CR_TABLE0) |
| MSR 0x000000A9 = 0x00000000:0x0000061D (EMTTM_CR_TABLE1) |
| MSR 0x000000AA = 0x00000000:0x0000061D (EMTTM_CR_TABLE2) |
| MSR 0x000000AB = 0x00000000:0x0000061D (EMTTM_CR_TABLE3) |
| MSR 0x000000AC = 0x00000000:0x0000061D (EMTTM_CR_TABLE4) |
| MSR 0x000000AD = 0x00000000:0x0000061D (EMTTM_CR_TABLE5) |
| MSR 0x000000CD = 0x00000000:0x00000802 (FSB_CLOCK_STS) |
| MSR 0x000000E2 = 0x00000000:0x0026B40B (PMG_CST_CONFIG_CONTROL) |
| MSR 0x000000E3 = 0x00000000:0x08090514 (PMG_IO_BASE_ADDR) |
| MSR 0x000000E4 = 0x00000000:0x00010514 (PMG_IO_CAPTURE_ADDR) |
| MSR 0x000000EE = 0xA8000000:0xC37D4700 (EXT_CONFIG) |
| MSR 0x0000011E = 0x00000000:0xBE702105 (BBL_CR_CTL3) |
| MSR 0x00000194 = 0x00000000:0x00000000 (CLOCK_FLEX_MAX) |
| MSR 0x00000198 = 0x0A270A27:0x06000A27 (IA32_PERF_STATUS) |
| MSR 0x000001A0 = 0x00000041:0x64972489 (IA32_MISC_ENABLES) |
| MSR 0x000001AA = 0x00000000:0x7E2F043F (PIC_SENS_CFG) |
| MSR 0x00000400 = 0x00000000:0x42880000 (IA32_MC0_CTL) |
| MSR 0x00000401 = 0x10000000:0x00000000 (IA32_MC0_STATUS) |
| MSR 0x00000402 = 0x00000000:0xFED000F0 (IA32_MC0_ADDR) |
| MSR 0x0000040C = 0x00000000:0x00000001 (IA32_MC4_CTL) |
| MSR 0x0000040D = 0x00200000:0x00000000 (IA32_MC4_STATUS) |
| MSR 0x0000040E = 0x000000B7:0xF0A02660 (IA32_MC4_ADDR) |
| |
| ====================== UNIQUE MSRs (core 0) ====================== |
| MSR 0x00000010 = 0x000001F7:0x9DA1843E (IA32_TIME_STAMP_COUNTER) |
| MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE) |
| MSR 0x0000003A = 0x00000000:0x00000000 (IA32_FEATURE_CONTROL) |
| MSR 0x0000008B = 0x00000000:0x00000000 (IA32_BIOS_SIGN_ID) |
| MSR 0x000000E1 = 0x00000000:0xF0F00000 (SMM_CST_MISC_INFO) |
| MSR 0x000000E7 = 0x00000134:0x8CAE9C02 (IA32_MPERF) |
| MSR 0x000000E8 = 0x00000134:0x8CAED686 (IA32_APERF) |
| MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP) |
| MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| MSR 0x00000199 = 0x00000000:0x00000A27 (IA32_PERF_CONTROL) |
| MSR 0x0000019A = 0x00000000:0x00000002 (IA32_THERM_CTL) |
| MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| MSR 0x0000019C = 0x00000000:0x88230000 (IA32_THERM_STATUS) |
| MSR 0x0000019D = 0x00000000:0x0000061D (MSR_THERM2_CTL) |
| MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL) |
| MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0) |
| MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0) |
| MSR 0x00000202 = 0x00000000:0x7F800000 (IA32_MTRR_PHYSBASE1) |
| MSR 0x00000203 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK1) |
| MSR 0x00000204 = 0x00000000:0xD0000001 (IA32_MTRR_PHYSBASE2) |
| MSR 0x00000205 = 0x0000000F:0xF0000800 (IA32_MTRR_PHYSMASK2) |
| MSR 0x00000206 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE3) |
| MSR 0x00000207 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK3) |
| MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| MSR 0x00000268 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C0000) |
| MSR 0x00000269 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C8000) |
| MSR 0x0000026A = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D0000) |
| MSR 0x0000026B = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D8000) |
| MSR 0x0000026C = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E0000) |
| MSR 0x0000026D = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E8000) |
| MSR 0x0000026E = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F0000) |
| MSR 0x0000026F = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F8000) |
| MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| |
| ====================== UNIQUE MSRs (core 1) ====================== |
| MSR 0x00000010 = 0x000001F7:0x9DABD452 (IA32_TIME_STAMP_COUNTER) |
| MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE) |
| MSR 0x0000003A = 0x00000000:0x00000000 (IA32_FEATURE_CONTROL) |
| MSR 0x0000008B = 0x00000000:0x00000000 (IA32_BIOS_SIGN_ID) |
| MSR 0x000000E1 = 0x00000000:0xF0F00000 (SMM_CST_MISC_INFO) |
| MSR 0x000000E7 = 0x00000131:0x9FDA59B8 (IA32_MPERF) |
| MSR 0x000000E8 = 0x00000131:0x9FDA6430 (IA32_APERF) |
| MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP) |
| MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| MSR 0x00000199 = 0x00000000:0x00000A27 (IA32_PERF_CONTROL) |
| MSR 0x0000019A = 0x00000000:0x00000002 (IA32_THERM_CTL) |
| MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| MSR 0x0000019C = 0x00000000:0x88230000 (IA32_THERM_STATUS) |
| MSR 0x0000019D = 0x00000000:0x0000061D (MSR_THERM2_CTL) |
| MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL) |
| MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0) |
| MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0) |
| MSR 0x00000202 = 0x00000000:0x7F800000 (IA32_MTRR_PHYSBASE1) |
| MSR 0x00000203 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK1) |
| MSR 0x00000204 = 0x00000000:0xD0000001 (IA32_MTRR_PHYSBASE2) |
| MSR 0x00000205 = 0x0000000F:0xF0000800 (IA32_MTRR_PHYSMASK2) |
| MSR 0x00000206 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE3) |
| MSR 0x00000207 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK3) |
| MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| MSR 0x00000268 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C0000) |
| MSR 0x00000269 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C8000) |
| MSR 0x0000026A = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D0000) |
| MSR 0x0000026B = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D8000) |
| MSR 0x0000026C = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E0000) |
| MSR 0x0000026D = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E8000) |
| MSR 0x0000026E = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F0000) |
| MSR 0x0000026F = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F8000) |
| MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| |
| |