| /* |
| * Intel ACPI Component Architecture |
| * AML/ASL+ Disassembler version 20160831-64 |
| * Copyright (c) 2000 - 2016 Intel Corporation |
| * |
| * Disassembling to symbolic ASL+ operators |
| * |
| * Disassembly of ssdt.dat, Mon Jan 2 17:42:50 2017 |
| * |
| * Original Table Header: |
| * Signature "SSDT" |
| * Length 0x0000025A (602) |
| * Revision 0x02 |
| * Checksum 0xE9 |
| * OEM ID "CORE " |
| * OEM Table ID "COREBOOT" |
| * OEM Revision 0x0000002A (42) |
| * Compiler ID "CORE" |
| * Compiler Version 0x0000002A (42) |
| */ |
| DefinitionBlock ("", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A) |
| { |
| External (_SB_.PCI0.GFX0, DeviceObj) |
| |
| Device (CTBL) |
| { |
| Name (_HID, "GOOGCB00") // _HID: Hardware ID |
| Name (_UID, Zero) // _UID: Unique ID |
| Method (_STA, 0, NotSerialized) // _STA: Status |
| { |
| Return (0x0F) |
| } |
| |
| Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings |
| { |
| Memory32Fixed (ReadOnly, |
| 0x7F75D000, // Address Base |
| 0x00008000, // Address Length |
| ) |
| }) |
| } |
| |
| Processor (\_PR.CP00, 0x00, 0x00000510, 0x06) |
| { |
| Name (_PCT, Package (0x02) // _PCT: Performance Control |
| { |
| ResourceTemplate () |
| { |
| Register (FFixedHW, |
| 0x00, // Bit Width |
| 0x00, // Bit Offset |
| 0x0000000000000000, // Address |
| ,) |
| }, |
| |
| ResourceTemplate () |
| { |
| Register (FFixedHW, |
| 0x00, // Bit Width |
| 0x00, // Bit Offset |
| 0x0000000000000000, // Address |
| ,) |
| } |
| }) |
| Name (_PSD, Package (0x01) // _PSD: Power State Dependencies |
| { |
| Package (0x05) |
| { |
| 0x05, |
| 0x00, |
| 0x00000000, |
| 0x000000FD, |
| 0x00000002 |
| } |
| }) |
| Name (_PSS, Package (0x03) // _PSS: Performance Supported States |
| { |
| Package (0x06) |
| { |
| 0x000007D0, |
| 0x000088B8, |
| 0x00000000, |
| 0x00000000, |
| 0x00000A27, |
| 0x00000A27 |
| }, |
| |
| Package (0x06) |
| { |
| 0x00000640, |
| 0x00007530, |
| 0x00000000, |
| 0x00000000, |
| 0x00000822, |
| 0x00000822 |
| }, |
| |
| Package (0x06) |
| { |
| 0x000004B0, |
| 0x000061A8, |
| 0x00000000, |
| 0x00000000, |
| 0x0000061D, |
| 0x0000061D |
| } |
| }) |
| Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities |
| { |
| Return (0x00) |
| } |
| } |
| |
| Processor (\_PR.CP01, 0x01, 0x00000000, 0x00) |
| { |
| Name (_PCT, Package (0x02) // _PCT: Performance Control |
| { |
| ResourceTemplate () |
| { |
| Register (FFixedHW, |
| 0x00, // Bit Width |
| 0x00, // Bit Offset |
| 0x0000000000000000, // Address |
| ,) |
| }, |
| |
| ResourceTemplate () |
| { |
| Register (FFixedHW, |
| 0x00, // Bit Width |
| 0x00, // Bit Offset |
| 0x0000000000000000, // Address |
| ,) |
| } |
| }) |
| Name (_PSD, Package (0x01) // _PSD: Power State Dependencies |
| { |
| Package (0x05) |
| { |
| 0x05, |
| 0x00, |
| 0x00000000, |
| 0x000000FD, |
| 0x00000002 |
| } |
| }) |
| Name (_PSS, Package (0x03) // _PSS: Performance Supported States |
| { |
| Package (0x06) |
| { |
| 0x000007D0, |
| 0x000088B8, |
| 0x00000000, |
| 0x00000000, |
| 0x00000A27, |
| 0x00000A27 |
| }, |
| |
| Package (0x06) |
| { |
| 0x00000640, |
| 0x00007530, |
| 0x00000000, |
| 0x00000000, |
| 0x00000822, |
| 0x00000822 |
| }, |
| |
| Package (0x06) |
| { |
| 0x000004B0, |
| 0x000061A8, |
| 0x00000000, |
| 0x00000000, |
| 0x0000061D, |
| 0x0000061D |
| } |
| }) |
| Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities |
| { |
| Return (0x00) |
| } |
| } |
| |
| Scope (\_SB.PCI0.GFX0) |
| { |
| Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices |
| { |
| Return (Package (0x00) {}) |
| } |
| } |
| } |
| |