|
|
|
|
| coreboot-4.0-6835-g8603513 Sam Aug 30 19:29:21 CEST 2014 starting...
|
| Setting up static southbridge registers... done.
|
| Disabling Watchdog reboot... done.
|
| Setting up static northbridge registers... done.
|
| Initializing Graphics...
|
| Back from sandybridge_early_initialization()
|
| SMBus controller enabled.
|
| CPU id(206a7): Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz
|
| AES supported, TXT supported, VT supported
|
| PCH type: QM67, device id: 1c4f, rev id 5
|
| Intel ME early init
|
| Intel ME firmware is ready
|
| ME: Requested 32MB UMA
|
| Starting native Platform init
|
| Row addr bits : 16
|
| Column addr bits : 10
|
| Number of ranks : 2
|
| DIMM Capacity : 8192 MB
|
| CAS latencies : 6 7 8 9 10 11
|
| tCKmin : 1.250 ns
|
| tAAmin : 13.125 ns
|
| tWRmin : 15.000 ns
|
| tRCDmin : 13.125 ns
|
| tRRDmin : 6.000 ns
|
| tRPmin : 13.125 ns
|
| tRASmin : 35.000 ns
|
| tRCmin : 48.125 ns
|
| tRFCmin : 260.000 ns
|
| tWTRmin : 7.500 ns
|
| tRTPmin : 7.500 ns
|
| tFAWmin : 30.000 ns
|
| rankmap[0] = 0x3
|
| Row addr bits : 16
|
| Column addr bits : 10
|
| Number of ranks : 2
|
| DIMM Capacity : 8192 MB
|
| CAS latencies : 6 7 8 9 10 11
|
| tCKmin : 1.250 ns
|
| tAAmin : 13.125 ns
|
| tWRmin : 15.000 ns
|
| tRCDmin : 13.125 ns
|
| tRRDmin : 6.000 ns
|
| tRPmin : 13.125 ns
|
| tRASmin : 35.000 ns
|
| tRCmin : 48.125 ns
|
| tRFCmin : 260.000 ns
|
| tWTRmin : 7.500 ns
|
| tRTPmin : 7.500 ns
|
| tFAWmin : 30.000 ns
|
| rankmap[1] = 0x3
|
| PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy... PLL busy...done
|
| MCU frequency is set at : 800 MHz
|
| Selected DRAM frequency: 800 MHz
|
| Minimum CAS latency : 11T
|
| Selected CAS latency : 11T
|
| Selected CWL latency : 8T
|
| Selected tRCD : 11T
|
| Selected tRP : 11T
|
| Selected tRAS : 28T
|
| Selected tWR : 12T
|
| Selected tFAW : 24T
|
| Selected tRRD : 5T
|
| Selected tRTP : 6T
|
| Selected tWTR : 6T
|
| Selected tRFC : 208T
|
| [c14] = 3000000
|
| [320c] = 4024000
|
| [d14] = 3000000
|
| [330c] = 4024000
|
| [4000] = 1c8bbb
|
| [4004] = cc186465
|
| [400c] = a08b4
|
| [4298] = 6cd01860
|
| [42a4] = 41f88200
|
| [4400] = 1c8bbb
|
| [4404] = cc186465
|
| [440c] = a08b4
|
| [4698] = 6cd01860
|
| [46a4] = 41f88200
|
| Done dimm mapping
|
| PCI:[a0] = 0
|
| PCI:[a4] = 4
|
| PCI:[bc] = c2a00 |
| |
| *** Log truncated, 3935 characters dropped. *** |
| |
| Adding CBMEM entry as no. 3
|
| Adding CBMEM entry as no. 4
|
| Relocate MRC DATA from feffa77c to bfee0600 (1040 bytes)
|
| Adding CBMEM entry as no. 5
|
| Trying CBFS ramstage loader.
|
| CBFS: loading stage fallback/ramstage @ 0x100000 (479340 bytes), entry @ 0x100000
|
| coreboot-4.0-6835-g8603513 Sam Aug 30 19:29:21 CEST 2014 booting...
|
| BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
|
| BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4 exit 0
|
| Enumerating buses...
|
| Show all devs...Before device enumeration.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.4: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:00.1: enabled 1
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 00:54: enabled 1
|
| I2C: 00:55: enabled 1
|
| I2C: 00:56: enabled 1
|
| I2C: 00:57: enabled 1
|
| I2C: 00:5c: enabled 1
|
| I2C: 00:5d: enabled 1
|
| I2C: 00:5e: enabled 1
|
| I2C: 00:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 1
|
| Compare with tree...
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 1
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.4: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:00.1: enabled 1
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 00:54: enabled 1
|
| I2C: 00:55: enabled 1
|
| I2C: 00:56: enabled 1
|
| I2C: 00:57: enabled 1
|
| I2C: 00:5c: enabled 1
|
| I2C: 00:5d: enabled 1
|
| I2C: 00:5e: enabled 1
|
| I2C: 00:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 1
|
| scan_static_bus for Root Device
|
| CPU_CLUSTER: 0 enabled
|
| DOMAIN: 0000 enabled
|
| DOMAIN: 0000 scanning...
|
| PCI: pci_scan_bus for bus 00
|
| PCI: 00:00.0 [8086/0104] ops
|
| Normal boot.
|
| PCI: 00:00.0 [8086/0104] enabled
|
| PCI: 00:02.0 [8086/0000] ops
|
| PCI: 00:02.0 [8086/0126] enabled
|
| PCI: 00:16.0 [8086/1c3a] bus ops
|
| PCI: 00:16.0 [8086/1c3a] enabled
|
| PCI: 00:16.1: Disabling device
|
| PCI: 00:16.1 [8086/1c3b] disabled No operations
|
| PCI: 00:16.2: Disabling device
|
| PCI: 00:16.2 [8086/1c3c] disabled No operations
|
| PCI: 00:16.3: Disabling device
|
| PCI: 00:16.3 [8086/1c3d] disabled No operations
|
| PCI: 00:19.0 [8086/1502] enabled
|
| PCI: 00:1a.0 [8086/0000] ops
|
| PCI: 00:1a.0 [8086/1c2d] enabled
|
| PCI: 00:1b.0 [8086/0000] ops
|
| PCI: 00:1b.0 [8086/1c20] enabled
|
| PCH: PCIe Root Port coalescing is enabled
|
| PCI: 00:1c.0 [8086/0000] bus ops
|
| PCI: 00:1c.0 [8086/1c10] enabled
|
| PCI: 00:1c.1 [8086/0000] bus ops
|
| PCI: 00:1c.1 [8086/1c12] enabled
|
| PCI: Static device PCI: 00:1c.2 not found, disabling it.
|
| PCI: 00:1c.3 [8086/0000] bus ops
|
| PCI: 00:1c.3 [8086/1c16] enabled
|
| PCI: 00:1c.4 [8086/0000] bus ops
|
| PCI: 00:1c.4 [8086/1c18] enabled
|
| PCI: 00:1c.5: Disabling device
|
| PCI: 00:1c.6: Disabling device
|
| PCI: 00:1c.7: Disabling device
|
| PCH: RPFN 0x76543210 -> 0xfed43210
|
| PCI: 00:1d.0 [8086/0000] ops
|
| PCI: 00:1d.0 [8086/1c26] enabled
|
| PCI: 00:1e.0: Disabling device
|
| PCI: 00:1f.0 [8086/0000] bus ops
|
| PCI: 00:1f.0 [8086/1c4f] enabled
|
| PCI: 00:1f.2 [8086/0000] ops
|
| PCI: 00:1f.2 [8086/1c01] enabled
|
| PCI: 00:1f.3 [8086/0000] bus ops
|
| PCI: 00:1f.3 [8086/1c22] enabled
|
| PCI: 00:1f.5: Disabling device
|
| PCI: Static device PCI: 00:1f.6 not found, disabling it.
|
| scan_static_bus for PCI: 00:16.0
|
| scan_static_bus for PCI: 00:16.0 done
|
| do_pci_scan_bridge for PCI: 00:1c.0
|
| PCI: pci_scan_bus for bus 01
|
| PCI: pci_scan_bus returning with max=001
|
| do_pci_scan_bridge returns max 1
|
| do_pci_scan_bridge for PCI: 00:1c.1
|
| PCI: pci_scan_bus for bus 02
|
| PCI: 02:00.0 [8086/0085] enabled
|
| PCI: pci_scan_bus returning with max=002
|
| Capability: type 0x01 @ 0xc8
|
| Capability: type 0x05 @ 0xd0
|
| Capability: type 0x10 @ 0xe0
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L1
|
| do_pci_scan_bridge returns max 2
|
| do_pci_scan_bridge for PCI: 00:1c.3
|
| PCI: pci_scan_bus for bus 03
|
| PCI: pci_scan_bus returning with max=003
|
| do_pci_scan_bridge returns max 3
|
| do_pci_scan_bridge for PCI: 00:1c.4
|
| PCI: pci_scan_bus for bus 04
|
| PCI: 04:00.0 [1180/e823] enabled
|
| PCI: 04:00.1 [1180/e232] enabled
|
| PCI: 04:00.2 [1180/e852] enabled
|
| PCI: pci_scan_bus returning with max=004
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| Capability: type 0x05 @ 0x50
|
| Capability: type 0x01 @ 0x78
|
| Capability: type 0x10 @ 0x80
|
| Capability: type 0x10 @ 0x40
|
| Enabling Common Clock Configuration
|
| ASPM: Enabled L0s and L1
|
| do_pci_scan_bridge returns max 4
|
| scan_static_bus for PCI: 00:1f.0
|
| PNP: 00ff.1 enabled
|
| recv_ec_data: 0x38
|
| recv_ec_data: 0x5a
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x32
|
| recv_ec_data: 0x34
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x14
|
| recv_ec_data: 0x03
|
| recv_ec_data: 0x80
|
| recv_ec_data: 0x10
|
| EC Firmware ID 8ZHT24WW-3.20, Version 8.01A
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0x10
|
| recv_ec_data: 0x20
|
| recv_ec_data: 0x30
|
| recv_ec_data: 0x00
|
| recv_ec_data: 0xa6
|
| recv_ec_data: 0x60
|
| recv_ec_data: 0x70
|
| PNP: 00ff.2 enabled
|
| scan_static_bus for PCI: 00:1f.0 done
|
| scan_static_bus for PCI: 00:1f.3
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
|
| scan_static_bus for PCI: 00:1f.3 done
|
| PCI: pci_scan_bus returning with max=004
|
| scan_static_bus for Root Device done
|
| done
|
| BS: BS_DEV_ENUMERATE times (us): entry 0 run 7652 exit 0
|
| found VGA at PCI: 00:02.0
|
| Setting up VGA for PCI: 00:02.0
|
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
| Allocating resources...
|
| Reading resources...
|
| Root Device read_resources bus 0 link: 0
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0
|
| APIC: 00 missing read_resources
|
| CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0
|
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
| PCI: 00:1c.0 read_resources bus 1 link: 0
|
| PCI: 00:1c.0 read_resources bus 1 link: 0 done
|
| PCI: 00:1c.1 read_resources bus 2 link: 0
|
| PCI: 00:1c.1 read_resources bus 2 link: 0 done
|
| PCI: 00:1c.3 read_resources bus 3 link: 0
|
| PCI: 00:1c.3 read_resources bus 3 link: 0 done
|
| PCI: 00:1c.4 read_resources bus 4 link: 0
|
| PCI: 00:1c.4 read_resources bus 4 link: 0 done
|
| PCI: 00:1f.0 read_resources bus 0 link: 0
|
| PNP: 00ff.1 missing read_resources
|
| PNP: 00ff.2 missing read_resources
|
| PCI: 00:1f.0 read_resources bus 0 link: 0 done
|
| PCI: 00:1f.3 read_resources bus 1 link: 0
|
| PCI: 00:1f.3 read_resources bus 1 link: 0 done
|
| DOMAIN: 0000 read_resources bus 0 link: 0 done
|
| Root Device read_resources bus 0 link: 0 done
|
| Done reading resources.
|
| Show resources in subtree (Root Device)...After reading.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
|
| PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
|
| PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
|
| PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.0
|
| PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0
|
| PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 02:00.0
|
| PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.3
|
| PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 00:1c.4 child on link 0 PCI: 04:00.0
|
| PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
|
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
|
| PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
|
| PCI: 04:00.0
|
| PCI: 04:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 04:00.1
|
| PCI: 04:00.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 04:00.2
|
| PCI: 04:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
|
| PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
|
| PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
|
| PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
|
| PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.5
|
| PCI: 00:1f.6
|
| DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
|
| PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
|
| PCI: 00:02.0 20 * [0x0 - 0x3f] io
|
| PCI: 00:19.0 18 * [0x40 - 0x5f] io
|
| PCI: 00:1f.2 20 * [0x60 - 0x7f] io
|
| PCI: 00:1f.2 10 * [0x80 - 0x87] io
|
| PCI: 00:1f.2 18 * [0x88 - 0x8f] io
|
| PCI: 00:1f.2 14 * [0x90 - 0x93] io
|
| PCI: 00:1f.2 1c * [0x94 - 0x97] io
|
| DOMAIN: 0000 compute_resources_io: base: 98 size: 98 align: 6 gran: 0 limit: ffff done
|
| DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 02:00.0 10 * [0x0 - 0x1fff] mem
|
| PCI: 00:1c.1 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
| PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
| PCI: 00:1c.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
|
| PCI: 04:00.0 10 * [0x0 - 0xff] mem
|
| PCI: 04:00.1 10 * [0x100 - 0x1ff] mem
|
| PCI: 04:00.2 10 * [0x200 - 0x2ff] mem
|
| PCI: 00:1c.4 compute_resources_mem: base: 300 size: 100000 align: 20 gran: 20 limit: ffffffff done
|
| PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
|
| PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
|
| PCI: 00:1c.1 20 * [0x10400000 - 0x104fffff] mem
|
| PCI: 00:1c.4 20 * [0x10500000 - 0x105fffff] mem
|
| PCI: 00:19.0 10 * [0x10600000 - 0x1061ffff] mem
|
| PCI: 00:1b.0 10 * [0x10620000 - 0x10623fff] mem
|
| PCI: 00:19.0 14 * [0x10624000 - 0x10624fff] mem
|
| PCI: 00:1f.2 24 * [0x10625000 - 0x106257ff] mem
|
| PCI: 00:1a.0 10 * [0x10625800 - 0x10625bff] mem
|
| PCI: 00:1d.0 10 * [0x10625c00 - 0x10625fff] mem
|
| PCI: 00:1f.3 10 * [0x10626000 - 0x106260ff] mem
|
| PCI: 00:16.0 10 * [0x10626100 - 0x1062610f] mem
|
| DOMAIN: 0000 compute_resources_mem: base: 10626110 size: 10626110 align: 28 gran: 0 limit: ffffffff done
|
| avoid_fixed_resources: DOMAIN: 0000
|
| avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
|
| avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
|
| constrain_resources: DOMAIN: 0000
|
| constrain_resources: PCI: 00:00.0
|
| constrain_resources: PCI: 00:02.0
|
| constrain_resources: PCI: 00:16.0
|
| constrain_resources: PCI: 00:19.0
|
| constrain_resources: PCI: 00:1a.0
|
| constrain_resources: PCI: 00:1b.0
|
| constrain_resources: PCI: 00:1c.0
|
| constrain_resources: PCI: 00:1c.1
|
| constrain_resources: PCI: 02:00.0
|
| constrain_resources: PCI: 00:1c.3
|
| constrain_resources: PCI: 00:1c.4
|
| constrain_resources: PCI: 04:00.0
|
| constrain_resources: PCI: 04:00.1
|
| constrain_resources: PCI: 04:00.2
|
| constrain_resources: PCI: 00:1d.0
|
| constrain_resources: PCI: 00:1f.0
|
| constrain_resources: PNP: 00ff.1
|
| constrain_resources: PNP: 00ff.2
|
| skipping PNP: 00ff.2@60 fixed resource, size=0!
|
| skipping PNP: 00ff.2@62 fixed resource, size=0!
|
| skipping PNP: 00ff.2@64 fixed resource, size=0!
|
| skipping PNP: 00ff.2@66 fixed resource, size=0!
|
| constrain_resources: PCI: 00:1f.2
|
| constrain_resources: PCI: 00:1f.3
|
| constrain_resources: I2C: 01:54
|
| constrain_resources: I2C: 01:55
|
| constrain_resources: I2C: 01:56
|
| constrain_resources: I2C: 01:57
|
| constrain_resources: I2C: 01:5c
|
| constrain_resources: I2C: 01:5d
|
| constrain_resources: I2C: 01:5e
|
| constrain_resources: I2C: 01:5f
|
| avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
|
| lim->base 0000167c lim->limit 0000ffff
|
| avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
|
| lim->base 00000000 lim->limit efffffff
|
| Setting resources...
|
| DOMAIN: 0000 allocate_resources_io: base:167c size:98 align:6 gran:0 limit:ffff
|
| Assigned: PCI: 00:02.0 20 * [0x1800 - 0x183f] io
|
| Assigned: PCI: 00:19.0 18 * [0x1840 - 0x185f] io
|
| Assigned: PCI: 00:1f.2 20 * [0x1860 - 0x187f] io
|
| Assigned: PCI: 00:1f.2 10 * [0x1880 - 0x1887] io
|
| Assigned: PCI: 00:1f.2 18 * [0x1888 - 0x188f] io
|
| Assigned: PCI: 00:1f.2 14 * [0x1890 - 0x1893] io
|
| Assigned: PCI: 00:1f.2 1c * [0x1894 - 0x1897] io
|
| DOMAIN: 0000 allocate_resources_io: next_base: 1898 size: 98 align: 6 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| PCI: 00:1c.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
|
| PCI: 00:1c.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
|
| DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10626110 align:28 gran:0 limit:efffffff
|
| Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
|
| Assigned: PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
|
| Assigned: PCI: 00:1c.1 20 * [0xe0400000 - 0xe04fffff] mem
|
| Assigned: PCI: 00:1c.4 20 * [0xe0500000 - 0xe05fffff] mem
|
| Assigned: PCI: 00:19.0 10 * [0xe0600000 - 0xe061ffff] mem
|
| Assigned: PCI: 00:1b.0 10 * [0xe0620000 - 0xe0623fff] mem
|
| Assigned: PCI: 00:19.0 14 * [0xe0624000 - 0xe0624fff] mem
|
| Assigned: PCI: 00:1f.2 24 * [0xe0625000 - 0xe06257ff] mem
|
| Assigned: PCI: 00:1a.0 10 * [0xe0625800 - 0xe0625bff] mem
|
| Assigned: PCI: 00:1d.0 10 * [0xe0625c00 - 0xe0625fff] mem
|
| Assigned: PCI: 00:1f.3 10 * [0xe0626000 - 0xe06260ff] mem
|
| Assigned: PCI: 00:16.0 10 * [0xe0626100 - 0xe062610f] mem
|
| DOMAIN: 0000 allocate_resources_mem: next_base: e0626110 size: 10626110 align: 28 gran: 0 done
|
| PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.1 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 02:00.0 10 * [0xe0400000 - 0xe0401fff] mem
|
| PCI: 00:1c.1 allocate_resources_mem: next_base: e0402000 size: 100000 align: 20 gran: 20 done
|
| PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.4 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
|
| PCI: 00:1c.4 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
|
| PCI: 00:1c.4 allocate_resources_mem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff
|
| Assigned: PCI: 04:00.0 10 * [0xe0500000 - 0xe05000ff] mem
|
| Assigned: PCI: 04:00.1 10 * [0xe0500100 - 0xe05001ff] mem
|
| Assigned: PCI: 04:00.2 10 * [0xe0500200 - 0xe05002ff] mem
|
| PCI: 00:1c.4 allocate_resources_mem: next_base: e0500300 size: 100000 align: 20 gran: 20 done
|
| Root Device assign_resources, bus 0 link: 0
|
| TOUUD 0x43b600000 TOLUD 0xc2a00000 TOM 0x400000000
|
| MEBASE 0x3fe000000
|
| IGD decoded, subtracting 32M UMA and 2M GTT
|
| TSEG base 0xc0000000 size 8M
|
| Available memory below 4GB: 3072M
|
| Available memory above 4GB: 13238M
|
| Adding PCIe config bar base=0xf0000000 size=0x4000000
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
|
| PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
|
| PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
|
| PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io
|
| PCI: 00:16.0 10 <- [0x00e0626100 - 0x00e062610f] size 0x00000010 gran 0x04 mem64
|
| PCI: 00:19.0 10 <- [0x00e0600000 - 0x00e061ffff] size 0x00020000 gran 0x11 mem
|
| PCI: 00:19.0 14 <- [0x00e0624000 - 0x00e0624fff] size 0x00001000 gran 0x0c mem
|
| PCI: 00:19.0 18 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1a.0 10 <- [0x00e0625800 - 0x00e0625bff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1b.0 10 <- [0x00e0620000 - 0x00e0623fff] size 0x00004000 gran 0x0e mem64
|
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
| PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
| PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem
|
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
| PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
| PCI: 00:1c.1 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 02 mem
|
| PCI: 00:1c.1 assign_resources, bus 2 link: 0
|
| PCI: 02:00.0 10 <- [0x00e0400000 - 0x00e0401fff] size 0x00002000 gran 0x0d mem64
|
| PCI: 00:1c.1 assign_resources, bus 2 link: 0
|
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
|
| PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
| PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
|
| PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
|
| PCI: 00:1c.4 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem
|
| PCI: 00:1c.4 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 04 mem
|
| PCI: 00:1c.4 assign_resources, bus 4 link: 0
|
| PCI: 04:00.0 10 <- [0x00e0500000 - 0x00e05000ff] size 0x00000100 gran 0x08 mem
|
| PCI: 04:00.1 10 <- [0x00e0500100 - 0x00e05001ff] size 0x00000100 gran 0x08 mem
|
| PCI: 04:00.2 10 <- [0x00e0500200 - 0x00e05002ff] size 0x00000100 gran 0x08 mem
|
| PCI: 00:1c.4 assign_resources, bus 4 link: 0
|
| PCI: 00:1d.0 10 <- [0x00e0625c00 - 0x00e0625fff] size 0x00000400 gran 0x0a mem
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PNP: 00ff.1 missing set_resources
|
| PNP: 00ff.2 missing set_resources
|
| PCI: 00:1f.0 assign_resources, bus 0 link: 0
|
| PCI: 00:1f.2 10 <- [0x0000001880 - 0x0000001887] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 14 <- [0x0000001890 - 0x0000001893] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 18 <- [0x0000001888 - 0x000000188f] size 0x00000008 gran 0x03 io
|
| PCI: 00:1f.2 1c <- [0x0000001894 - 0x0000001897] size 0x00000004 gran 0x02 io
|
| PCI: 00:1f.2 20 <- [0x0000001860 - 0x000000187f] size 0x00000020 gran 0x05 io
|
| PCI: 00:1f.2 24 <- [0x00e0625000 - 0x00e06257ff] size 0x00000800 gran 0x0b mem
|
| PCI: 00:1f.3 10 <- [0x00e0626000 - 0x00e06260ff] size 0x00000100 gran 0x08 mem64
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| PCI: 00:1f.3 assign_resources, bus 1 link: 0
|
| DOMAIN: 0000 assign_resources, bus 0 link: 0
|
| Root Device assign_resources, bus 0 link: 0
|
| Done setting resources.
|
| Show resources in subtree (Root Device)...After assigning values.
|
| Root Device child on link 0 CPU_CLUSTER: 0
|
| CPU_CLUSTER: 0 child on link 0 APIC: 00
|
| APIC: 00
|
| APIC: acac
|
| DOMAIN: 0000 child on link 0 PCI: 00:00.0
|
| DOMAIN: 0000 resource base 167c size 98 align 6 gran 0 limit ffff flags 40040100 index 10000000
|
| DOMAIN: 0000 resource base d0000000 size 10626110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
|
| DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
|
| DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
|
| DOMAIN: 0000 resource base 100000000 size 33b600000 align 0 gran 0 limit 0 flags e0004200 index 5
|
| DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
|
| DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
|
| DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
|
| DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
|
| DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
|
| DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
|
| PCI: 00:00.0
|
| PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
|
| PCI: 00:01.0
|
| PCI: 00:02.0
|
| PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10
|
| PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
|
| PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
|
| PCI: 00:16.0
|
| PCI: 00:16.0 resource base e0626100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
|
| PCI: 00:16.1
|
| PCI: 00:16.2
|
| PCI: 00:16.3
|
| PCI: 00:19.0
|
| PCI: 00:19.0 resource base e0600000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10
|
| PCI: 00:19.0 resource base e0624000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14
|
| PCI: 00:19.0 resource base 1840 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
|
| PCI: 00:1a.0
|
| PCI: 00:1a.0 resource base e0625800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1b.0
|
| PCI: 00:1b.0 resource base e0620000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.0
|
| PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 00:1c.1 child on link 0 PCI: 02:00.0
|
| PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.1 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 02:00.0
|
| PCI: 02:00.0 resource base e0400000 size 2000 align 13 gran 13 limit efffffff flags 60000201 index 10
|
| PCI: 00:1c.2
|
| PCI: 00:1c.3
|
| PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 00:1c.4 child on link 0 PCI: 04:00.0
|
| PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
|
| PCI: 00:1c.4 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
|
| PCI: 00:1c.4 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
|
| PCI: 04:00.0
|
| PCI: 04:00.0 resource base e0500000 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 04:00.1
|
| PCI: 04:00.1 resource base e0500100 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 04:00.2
|
| PCI: 04:00.2 resource base e0500200 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10
|
| PCI: 00:1c.5
|
| PCI: 00:1c.6
|
| PCI: 00:1c.7
|
| PCI: 00:1d.0
|
| PCI: 00:1d.0 resource base e0625c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
|
| PCI: 00:1e.0
|
| PCI: 00:1f.0 child on link 0 PNP: 00ff.1
|
| PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
|
| PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
|
| PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
|
| PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
|
| PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
|
| PNP: 00ff.1
|
| PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
|
| PNP: 00ff.2
|
| PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
|
| PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
|
| PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
|
| PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
|
| PCI: 00:1f.2
|
| PCI: 00:1f.2 resource base 1880 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
|
| PCI: 00:1f.2 resource base 1890 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
|
| PCI: 00:1f.2 resource base 1888 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
|
| PCI: 00:1f.2 resource base 1894 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
|
| PCI: 00:1f.2 resource base 1860 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
|
| PCI: 00:1f.2 resource base e0625000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24
|
| PCI: 00:1f.3 child on link 0 I2C: 01:54
|
| PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
|
| PCI: 00:1f.3 resource base e0626000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
|
| I2C: 01:54
|
| I2C: 01:55
|
| I2C: 01:56
|
| I2C: 01:57
|
| I2C: 01:5c
|
| I2C: 01:5d
|
| I2C: 01:5e
|
| I2C: 01:5f
|
| PCI: 00:1f.5
|
| PCI: 00:1f.6
|
| Done allocating resources.
|
| BS: BS_DEV_RESOURCES times (us): entry 0 run 3456 exit 0
|
| Enabling resources...
|
| PCI: 00:00.0 subsystem <- 17aa/21db
|
| PCI: 00:00.0 cmd <- 06
|
| PCI: 00:02.0 subsystem <- 17aa/21db
|
| PCI: 00:02.0 cmd <- 03
|
| PCI: 00:16.0 subsystem <- 17aa/21db
|
| PCI: 00:16.0 cmd <- 02
|
| PCI: 00:19.0 subsystem <- 17aa/21ce
|
| PCI: 00:19.0 cmd <- 103
|
| PCI: 00:1a.0 subsystem <- 17aa/21db
|
| PCI: 00:1a.0 cmd <- 102
|
| PCI: 00:1b.0 subsystem <- 17aa/21db
|
| PCI: 00:1b.0 cmd <- 102
|
| PCI: 00:1c.0 bridge ctrl <- 0003
|
| PCI: 00:1c.0 subsystem <- 17aa/21db
|
| PCI: 00:1c.0 cmd <- 100
|
| PCI: 00:1c.1 bridge ctrl <- 0003
|
| PCI: 00:1c.1 subsystem <- 17aa/21db
|
| PCI: 00:1c.1 cmd <- 106
|
| PCI: 00:1c.3 bridge ctrl <- 0003
|
| PCI: 00:1c.3 subsystem <- 17aa/21db
|
| PCI: 00:1c.3 cmd <- 100
|
| PCI: 00:1c.4 bridge ctrl <- 0003
|
| PCI: 00:1c.4 subsystem <- 17aa/21db
|
| PCI: 00:1c.4 cmd <- 106
|
| PCI: 00:1d.0 subsystem <- 17aa/21db
|
| PCI: 00:1d.0 cmd <- 102
|
| pch_decode_init
|
| PCI: 00:1f.0 subsystem <- 17aa/21db
|
| PCI: 00:1f.0 cmd <- 107
|
| PCI: 00:1f.2 subsystem <- 17aa/21db
|
| PCI: 00:1f.2 cmd <- 03
|
| PCI: 00:1f.3 subsystem <- 17aa/21db
|
| PCI: 00:1f.3 cmd <- 103
|
| PCI: 02:00.0 cmd <- 02
|
| PCI: 04:00.0 subsystem <- 17aa/21db
|
| PCI: 04:00.0 cmd <- 106
|
| PCI: 04:00.1 subsystem <- 17aa/21db
|
| PCI: 04:00.1 cmd <- 106
|
| PCI: 04:00.2 cmd <- 06
|
| done.
|
| BS: BS_DEV_ENABLE times (us): entry 0 run 228 exit 0
|
| Initializing devices...
|
| Root Device init
|
| Keyboard init...
|
| Keyboard controller output buffer result timeout
|
| Keyboard controller output buffer result timeout
|
| Keyboard reset failed ACK: 0xaa
|
| Root Device init 870682 usecs
|
| CPU_CLUSTER: 0 init
|
| start_eip=0x00001000, code_size=0x00000031
|
| Installing SMM handler to 0xc0000000
|
| Installing IED header to 0xc0400000
|
| Initializing SMM handler... ... pmbase = 0x0500
|
|
|
| SMI_STS: MCSMI PM1
|
| PM1_STS: WAK PWRBTN TMROF
|
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0
|
| ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
|
| TCO_STS:
|
| ... raise SMI#
|
| Initializing CPU #0
|
| CPU: vendor Intel device 206a7
|
| CPU: family 06, model 2a, stepping 07
|
| Enabling cache
|
| microcode: sig=0x206a7 pf=0x10 revision=0x28
|
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz.
|
| MTRR: Physical address space:
|
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
|
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
|
| 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
|
| 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
|
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
|
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
|
| 0x0000000100000000 - 0x000000043b600000 size 0x33b600000 type 6
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: default type WB/UC MTRR counts: 3/11.
|
| MTRR: WB selected as default type.
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x00 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2500
|
| Turbo is available but hidden
|
| Turbo has been enabled
|
| CPU: 0 has 2 cores, 2 threads per core
|
| CPU: 0 has core 1
|
| CPU1: stack_base 0016f000, stack_end 0016fff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| Sending STARTUP #1 to 1.
|
| After apic_write.
|
| Initializing CPU #1
|
| Startup point 1.
|
| CPU: vendor Intel device 206a7
|
| Waiting for send to finish...
|
| CPU: family 06, model 2a, stepping 07
|
| +Enabling cache
|
| Sending STARTUP #2 to 1.
|
| After apic_write.
|
| microcode: sig=0x206a7 pf=0x10 revision=0x28
|
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz.
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +After Startup.
|
| CPU: 0 has core 2
|
| CPU2: stack_base 0016e000, stack_end 0016eff8
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +Deasserting INIT.
|
| Waiting for send to finish...
|
| +#startup loops: 2.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| Sending STARTUP #1 to 2.
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| After apic_write.
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| Initializing CPU #2
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| CPU: vendor Intel device 206a7
|
| Startup point 1.
|
| CPU: family 06, model 2a, stepping 07
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| Enabling cache
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| microcode: sig=0x206a7 pf=0x10 revision=0x0
|
| Waiting for send to finish...
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| +MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| Sending STARTUP #2 to 2.
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| microcode: updated to revision 0x28 date=2012-04-24
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz.
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| After apic_write.
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| Startup point 1.
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| Waiting for send to finish...
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
|
| MTRR check
|
| +Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x01 done.
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| Enabling VMX
|
| After Startup.
|
| CPU: 0 has core 3
|
| CPU3: stack_base 0016d000, stack_end 0016dff8
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| model_x06ax: energy policy set to 6
|
| Asserting INIT.
|
| Waiting for send to finish...
|
| +model_x06ax: frequency set to 2500
|
| CPU #1 initialized
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| Deasserting INIT.
|
| Waiting for send to finish...
|
| +MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| #startup loops: 2.
|
| Sending STARTUP #1 to 3.
|
| After apic_write.
|
| call enable_fixed_mtrr()
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +Initializing CPU #3
|
| Sending STARTUP #2 to 3.
|
| After apic_write.
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| Startup point 1.
|
| Waiting for send to finish...
|
| +CPU: vendor Intel device 206a7
|
| After Startup.
|
| CPU #0 initialized
|
| Waiting for 2 CPUS to stop
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| CPU: family 06, model 2a, stepping 07
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
| Enabling cache
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x02 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2500
|
| CPU #2 initialized
|
| Waiting for 1 CPUS to stop
|
| microcode: sig=0x206a7 pf=0x10 revision=0x28
|
| CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz.
|
| MTRR: Fixed MSR 0x250 0x0606060606060606
|
| MTRR: Fixed MSR 0x258 0x0606060606060606
|
| MTRR: Fixed MSR 0x259 0x0000000000000000
|
| MTRR: Fixed MSR 0x268 0x0606060606060606
|
| MTRR: Fixed MSR 0x269 0x0606060606060606
|
| MTRR: Fixed MSR 0x26a 0x0606060606060606
|
| MTRR: Fixed MSR 0x26b 0x0606060606060606
|
| MTRR: Fixed MSR 0x26c 0x0606060606060606
|
| MTRR: Fixed MSR 0x26d 0x0606060606060606
|
| MTRR: Fixed MSR 0x26e 0x0606060606060606
|
| MTRR: Fixed MSR 0x26f 0x0606060606060606
|
| call enable_fixed_mtrr()
|
| MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
|
| MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
| MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
|
|
|
| MTRR check
|
| Fixed MTRRs : Enabled
|
| Variable MTRRs: Enabled
|
|
|
| Setting up local apic... apic_id: 0x03 done.
|
| Enabling VMX
|
| model_x06ax: energy policy set to 6
|
| model_x06ax: frequency set to 2500
|
| CPU #3 initialized
|
| All AP CPUs stopped (3115 loops)
|
| CPU1: stack: 0016f000 - 00170000, lowest used address 0016fcc0, stack used: 832 bytes
|
| CPU2: stack: 0016e000 - 0016f000, lowest used address 0016ecc0, stack used: 832 bytes
|
| CPU3: stack: 0016d000 - 0016e000, lowest used address 0016dcc0, stack used: 832 bytes
|
| CPU_CLUSTER: 0 init 130372 usecs
|
| PCI: 00:00.0 init
|
| Set BIOS_RESET_CPL
|
| CPU TDP: 35 Watts
|
| PCI: 00:00.0 init 1011 usecs
|
| PCI: 00:02.0 init
|
| GT Power Management Init
|
| SNB GT2 Power Meter Weights
|
| GT Power Management Init (post VBIOS)
|
| Initializing VGA without OPROM.
|
| EDID:
|
| 00 ff ff ff ff ff ff 00 30 e4 d8 02 00 00 00 00
|
| 00 16 01 03 80 1c 10 78 ea 88 55 99 5b 55 8f 26
|
| 1d 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
|
| 01 01 01 01 01 01 60 1d 56 d8 50 00 18 30 30 40
|
| 47 00 15 9c 10 00 00 1b 00 00 00 00 00 00 00 00
|
| 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 4c
|
| 47 20 44 69 73 70 6c 61 79 0a 20 20 00 00 00 fe
|
| 00 4c 50 31 32 35 57 48 32 2d 53 4c 42 33 00 59
|
| Extracted contents:
|
| header: 00 ff ff ff ff ff ff 00
|
| serial number: 30 e4 d8 02 00 00 00 00 00 16
|
| version: 01 03
|
| basic params: 80 1c 10 78 ea
|
| chroma info: 88 55 99 5b 55 8f 26 1d 50 54
|
| established: 00 00 00
|
| standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
|
| descriptor 1: 60 1d 56 d8 50 00 18 30 30 40 47 00 15 9c 10 00 00 1b
|
| descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
| descriptor 3: 00 00 00 fe 00 4c 47 20 44 69 73 70 6c 61 79 0a 20 20
|
| descriptor 4: 00 00 00 fe 00 4c 50 31 32 35 57 48 32 2d 53 4c 42 33
|
| extensions: 00
|
| checksum: 59
|
|
|
| Manufacturer: LGD Model 2d8 Serial Number 0
|
| Made week 0 of 2012
|
| EDID version: 1.3
|
| Digital display
|
| Maximum image size: 28 cm x 16 cm
|
| Gamma: 220%
|
| Check DPMS levels
|
| DPMS levels: Standby Suspend Off
|
| Supported color formats: RGB 4:4:4, YCrCb 4:2:2
|
| First detailed timing is preferred timing
|
| Established timings supported:
|
| Standard timings supported:
|
| Detailed timings
|
| Hex of detail: 601d56d85000183030404700159c1000001b
|
| Did detailed timing
|
| Detailed mode (IN HEX): Clock 75200 KHz, 115 mm x 9c mm
|
| 0556 0586 05c6 062e hborder 0
|
| 0300 0304 030b 0318 vborder 0
|
| +hsync -vsync
|
| Hex of detail: 000000000000000000000000000000000000
|
| Manufacturer-specified data, tag 0
|
| Hex of detail: 000000fe004c4720446973706c61790a2020
|
| ASCII string: LG
|
| Hex of detail: 000000fe004c503132355748322d534c4233
|
| ASCII string: LP125WH2
|
| Checksum
|
| Checksum: 0x59 (valid)
|
|
|
| Unknown extension block
|
|
|
| EDID block does NOT conform to EDID 1.3!
|
| Missing name descriptor
|
| Missing monitor ranges
|
| Detailed block string not properly terminated
|
| EDID block does not conform at all!
|
| Detailed blocks filled with garbage
|
| bringing up panel at resolution 1376 x 768
|
| Borders 0 x 0
|
| Blank 216 x 24
|
| Sync 64 x 7
|
| Front porch 48 x 4
|
| Spread spectrum clock
|
| Single channel
|
| Polarities 0, 1
|
| Data M1=1314215, N1=8388608
|
| Link frequency 270000 kHz
|
| Link M1=146023, N1=524288
|
| Pixel N=9, M1=14, M2=9, P1=1
|
| Pixel clock 150476 kHz
|
| waiting for panel powerup
|
| panel powered up
|
| PCI: 00:02.0 init 26828 usecs
|
| PCI: 00:16.0 init
|
| ME: FW Partition Table : OK
|
| ME: Bringup Loader Failure : NO
|
| ME: Firmware Init Complete : NO
|
| ME: Manufacturing Mode : NO
|
| ME: Boot Options Present : NO
|
| ME: Update In Progress : NO
|
| ME: Current Working State : Normal
|
| ME: Current Operation State : M0 with UMA
|
| ME: Current Operation Mode : Normal
|
| ME: Error Code : No Error
|
| ME: Progress Phase : Host Communication
|
| ME: Power Management Event : Clean Moff->Mx wake
|
| ME: Progress Phase State : Host communication established
|
| ME: BIOS path: Normal
|
| ME: Extend SHA-256: 9dde6eb9d0486f3b7e39c847c30fb5e6cab3c007280854734503b4bbaaa464e5
|
| ME: Firmware Version 7.1.1088.13 (code) 7.1.1088.13 (recovery)
|
| ME Capability: Full Network manageability : enabled
|
| ME Capability: Regular Network manageability : disabled
|
| ME Capability: Manageability : enabled
|
| ME Capability: Small business technology : disabled
|
| ME Capability: Level III manageability : disabled
|
| ME Capability: IntelR Anti-Theft (AT) : enabled
|
| ME Capability: IntelR Capability Licensing Service (CLS) : enabled
|
| ME Capability: IntelR Power Sharing Technology (MPC) : enabled
|
| ME Capability: ICC Over Clocking : enabled
|
| ME Capability: Protected Audio Video Path (PAVP) : enabled
|
| ME Capability: IPV6 : enabled
|
| ME Capability: KVM Remote Control (KVM) : enabled
|
| ME Capability: Outbreak Containment Heuristic (OCH) : disabled
|
| ME Capability: Virtual LAN (VLAN) : enabled
|
| ME Capability: TLS : enabled
|
| ME Capability: Wireless LAN (WLAN) : enabled
|
| PCI: 00:16.0 init 1964 usecs
|
| PCI: 00:19.0 init
|
| PCI: 00:19.0 init 0 usecs
|
| PCI: 00:1a.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1a.0 init 12 usecs
|
| PCI: 00:1b.0 init
|
| Azalia: base = e0620000
|
| Azalia: codec_mask = 09
|
| Azalia: Initializing codec #3
|
| Azalia: codec viddid: 80862805
|
| Azalia: verb_size: 16
|
| Azalia: verb loaded.
|
| Azalia: Initializing codec #0
|
| Azalia: codec viddid: 14f1506e
|
| Azalia: verb_size: 476
|
| Azalia: verb loaded.
|
| PCI: 00:1b.0 init 22576 usecs
|
| PCI: 00:1c.0 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.0 init 10 usecs
|
| PCI: 00:1c.1 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.1 init 9 usecs
|
| PCI: 00:1c.3 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.3 init 9 usecs
|
| PCI: 00:1c.4 init
|
| Initializing PCH PCIe bridge.
|
| PCI: 00:1c.4 init 9 usecs
|
| PCI: 00:1d.0 init
|
| EHCI: Setting up controller.. done.
|
| PCI: 00:1d.0 init 11 usecs
|
| PCI: 00:1f.0 init
|
| pch: lpc_init
|
| IOAPIC: Initializing IOAPIC at 0xfec00000
|
| IOAPIC: Bootstrap Processor Local APIC = 0x00
|
| IOAPIC: ID = 0x02
|
| IOAPIC: Dumping registers
|
| reg 0x0000: 0x02000000
|
| reg 0x0001: 0x00170020
|
| reg 0x0002: 0x00170020
|
| Set power off after power failure.
|
| NMI sources disabled.
|
| CougarPoint PM init
|
| rtc_failed = 0x0
|
| RTC Init
|
| Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
|
| done.
|
| Locking SMM.
|
| PCI: 00:1f.0 init 349 usecs
|
| PCI: 00:1f.2 init
|
| SATA: Initializing...
|
| SATA: Controller in AHCI mode.
|
| ABAR: E0625000
|
| PCI: 00:1f.2 init 73 usecs
|
| PCI: 00:1f.3 init
|
| PCI: 00:1f.3 init 7 usecs
|
| PCI: 02:00.0 init
|
| PCI: 02:00.0 init 0 usecs
|
| PCI: 04:00.0 init
|
| PCI: 04:00.0 init 0 usecs
|
| PCI: 04:00.1 init
|
| PCI: 04:00.1 init 0 usecs
|
| PCI: 04:00.2 init
|
| PCI: 04:00.2 init 0 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
| I2C: 01:54 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
| I2C: 01:55 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
| I2C: 01:56 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
| I2C: 01:57 init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
| Locking EEPROM RFID
|
| init EEPROM done
|
| I2C: 01:5c init 26632 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
| I2C: 01:5d init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
| I2C: 01:5e init 1 usecs
|
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
| I2C: 01:5f init 1 usecs
|
| Devices initialized
|
| Show all devs...After init.
|
| Root Device: enabled 1
|
| CPU_CLUSTER: 0: enabled 1
|
| APIC: 00: enabled 1
|
| APIC: acac: enabled 0
|
| DOMAIN: 0000: enabled 1
|
| PCI: 00:00.0: enabled 1
|
| PCI: 00:01.0: enabled 0
|
| PCI: 00:02.0: enabled 1
|
| PCI: 00:16.0: enabled 1
|
| PCI: 00:16.1: enabled 0
|
| PCI: 00:16.2: enabled 0
|
| PCI: 00:16.3: enabled 0
|
| PCI: 00:19.0: enabled 1
|
| PCI: 00:1a.0: enabled 1
|
| PCI: 00:1b.0: enabled 1
|
| PCI: 00:1c.0: enabled 1
|
| PCI: 00:1c.1: enabled 1
|
| PCI: 00:1c.2: enabled 0
|
| PCI: 00:1c.3: enabled 1
|
| PCI: 00:1c.4: enabled 1
|
| PCI: 04:00.0: enabled 1
|
| PCI: 04:00.1: enabled 1
|
| PCI: 00:1c.5: enabled 0
|
| PCI: 00:1c.6: enabled 0
|
| PCI: 00:1c.7: enabled 0
|
| PCI: 00:1d.0: enabled 1
|
| PCI: 00:1e.0: enabled 0
|
| PCI: 00:1f.0: enabled 1
|
| PNP: 00ff.1: enabled 1
|
| PNP: 00ff.2: enabled 1
|
| PCI: 00:1f.2: enabled 1
|
| PCI: 00:1f.3: enabled 1
|
| I2C: 01:54: enabled 1
|
| I2C: 01:55: enabled 1
|
| I2C: 01:56: enabled 1
|
| I2C: 01:57: enabled 1
|
| I2C: 01:5c: enabled 1
|
| I2C: 01:5d: enabled 1
|
| I2C: 01:5e: enabled 1
|
| I2C: 01:5f: enabled 1
|
| PCI: 00:1f.5: enabled 0
|
| PCI: 00:1f.6: enabled 0
|
| PCI: 02:00.0: enabled 1
|
| PCI: 04:00.2: enabled 1
|
| APIC: 01: enabled 1
|
| APIC: 02: enabled 1
|
| APIC: 03: enabled 1
|
| BS: BS_DEV_INIT times (us): entry 0 run 1080707 exit 0
|
| CBMEM region bfed0000-bfffffff (cbmem_check_toc)
|
| Adding CBMEM entry as no. 6
|
| Moving GDT to bfee0e00...ok
|
| Finalize devices...
|
| Devices finalized
|
| BS: BS_POST_DEVICE times (us): entry 8 run 4 exit 0
|
| BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
|
| Updating MRC cache data.
|
| find_current_mrc_cache_local: No valid MRC cache found.
|
| SF: Detected MX25L6405D with page size 1000, total 800000
|
| Need to erase the MRC cache region of 65536 bytes at fffe0000
|
| SF: Successfully erased 65536 bytes @ 0x7e0000
|
| Finally: write MRC cache update to flash at fffe0000
|
| Adding CBMEM entry as no. 7
|
| ACPI: Writing ACPI tables at bfee1000.
|
| ACPI: * FACS
|
| ACPI: * DSDT
|
| ACPI: * FADT
|
| ACPI: added table 1/32, length now 40
|
| ACPI: * HPET
|
| ACPI: added table 2/32, length now 44
|
| ACPI: * MADT
|
| ACPI: added table 3/32, length now 48
|
| ACPI: * MCFG
|
| ACPI: added table 4/32, length now 52
|
| ACPI: Patching up global NVS in DSDT at offset 0x00bd -> 0xbfee4ab0
|
| Adding CBMEM entry as no. 8
|
| ACPI: * DSDT @ bfee1250 Length 366e
|
| ACPI: * SSDT
|
| Found 1 CPU(s) with 4 core(s) each.
|
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000
|
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900
|
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00
|
| PSS: 800MHz power 9139 control 0x800 status 0x800
|
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000
|
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900
|
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00
|
| PSS: 800MHz power 9139 control 0x800 status 0x800
|
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000
|
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900
|
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00
|
| PSS: 800MHz power 9139 control 0x800 status 0x800
|
| PSS: 2501MHz power 35000 control 0x2000 status 0x2000
|
| PSS: 2500MHz power 35000 control 0x1900 status 0x1900
|
| PSS: 2000MHz power 26404 control 0x1400 status 0x1400
|
| PSS: 1600MHz power 20160 control 0x1000 status 0x1000
|
| PSS: 1200MHz power 14397 control 0xc00 status 0xc00
|
| PSS: 800MHz power 9139 control 0x800 status 0x800
|
| ACPI: added table 5/32, length now 56
|
| current = bfee6ce0
|
| ACPI: done.
|
| ACPI tables: 23776 bytes.
|
| Adding CBMEM entry as no. 9
|
| smbios_write_tables: bfeec600
|
| Root Device (LENOVO 4299Y48)
|
| recv_ec_data: 0x38
|
| recv_ec_data: 0x5a
|
| recv_ec_data: 0x48
|
| recv_ec_data: 0x54
|
| recv_ec_data: 0x32
|
| recv_ec_data: 0x34
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x57
|
| recv_ec_data: 0x14
|
| recv_ec_data: 0x03
|
| CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| APIC: 00 (Socket rPGA989 CPU)
|
| APIC: acac (Intel SandyBridge/IvyBridge CPU)
|
| DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:01.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
|
| PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 04:00.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 04:00.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
|
| PNP: 00ff.2 (Lenovo H8 EC)
|
| PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| I2C: 01:54 (AT24RF08C)
|
| I2C: 01:55 (AT24RF08C)
|
| I2C: 01:56 (AT24RF08C)
|
| I2C: 01:57 (AT24RF08C)
|
| I2C: 01:5c (AT24RF08C)
|
| I2C: 01:5d (AT24RF08C)
|
| I2C: 01:5e (AT24RF08C)
|
| I2C: 01:5f (AT24RF08C)
|
| PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
|
| PCI: 02:00.0 (unknown)
|
| PCI: 04:00.2 (unknown)
|
| APIC: 01 (unknown)
|
| APIC: 02 (unknown)
|
| APIC: 03 (unknown)
|
| SMBIOS tables: 442 bytes.
|
| Adding CBMEM entry as no. 10
|
| Adding CBMEM entry as no. 11
|
| Writing table forward entry at 0x00000500
|
| Wrote coreboot table at: 00000500, 0x10 bytes, checksum 71df
|
| Table forward entry ends at 0x00000528.
|
| ... aligned to 0x00001000
|
| Writing coreboot table at 0xbffece00
|
| rom_table_end = 0xbffece00
|
| ... aligned to 0xbfff0000
|
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
| 1. 0000000000001000-000000000009ffff: RAM
|
| 2. 00000000000a0000-00000000000fffff: RESERVED
|
| 3. 0000000000100000-000000001fffffff: RAM
|
| 4. 0000000020000000-00000000201fffff: RESERVED
|
| 5. 0000000020200000-000000003fffffff: RAM
|
| 6. 0000000040000000-00000000401fffff: RESERVED
|
| 7. 0000000040200000-00000000bfecffff: RAM
|
| 8. 00000000bfed0000-00000000bfffffff: CONFIGURATION TABLES
|
| 9. 00000000c0000000-00000000c29fffff: RESERVED
|
| 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
| 11. 0000000100000000-000000043b5fffff: RAM
|
| Wrote coreboot table at: bffece00, 0x1f4 bytes, checksum a47a
|
| coreboot table: 524 bytes.
|
| FREE SPACE 0. bfff4e00 0000b200
|
| CAR GLOBALS 1. bfed0200 00000200
|
| CONSOLE 2. bfed0400 00010000
|
| TIME STAMP 3. bfee0400 00000200
|
| MRC DATA 4. bfee0600 00000600
|
| ROMSTAGE 5. bfee0c00 00000200
|
| GDT 6. bfee0e00 00000200
|
| ACPI 7. bfee1000 0000b400
|
| GNVS PTR 8. bfeec400 00000200
|
| SMBIOS 9. bfeec600 00000800
|
| ACPI RESUME10. bfeece00 00100000
|
| COREBOOT 11. bffece00 00008000
|
| BS: BS_WRITE_TABLES times (us): entry 691328 run 25821 exit 0
|
| CBFS: located payload @ fff3ae38, 282027 bytes.
|
| Loading segment from rom address 0xfff3ae38
|
| code (compression=1)
|
| New segment dstaddr 0x8200 memsize 0x17d18 srcaddr 0xfff3ae8c filesize 0x83ea
|
| (cleaned up) New segment addr 0x8200 size 0x17d18 offset 0xfff3ae8c filesize 0x83ea
|
| Loading segment from rom address 0xfff3ae54
|
| code (compression=1)
|
| New segment dstaddr 0x100000 memsize 0xe1840 srcaddr 0xfff43276 filesize 0x3c96d
|
| (cleaned up) New segment addr 0x100000 size 0xe1840 offset 0xfff43276 filesize 0x3c96d
|
| Loading segment from rom address 0xfff3ae70
|
| Entry Point 0x00008200
|
| Bounce Buffer at bfd79000, 1403052 bytes
|
| Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017d18 filesz: 0x00000000000083ea
|
| lb: [0x0000000000100000, 0x000000000017506c)
|
| Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017d18 filesz: 0x00000000000083ea
|
| using LZMA
|
| [ 0x00008200, 000185e3, 0x0001ff18) <- fff3ae8c
|
| Clearing Segment: addr: 0x00000000000185e3 memsz: 0x0000000000007935
|
| dest 00008200, end 0001ff18, bouncebuffer bfd79000
|
| Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000e1840 filesz: 0x000000000003c96d
|
| lb: [0x0000000000100000, 0x000000000017506c)
|
| segment: [0x0000000000100000, 0x000000000013c96d, 0x00000000001e1840)
|
| bounce: [0x00000000bfd79000, 0x00000000bfdb596d, 0x00000000bfe5a840)
|
| Post relocation: addr: 0x00000000bfd79000 memsz: 0x00000000000e1840 filesz: 0x000000000003c96d
|
| using LZMA
|
| [ 0xbfd79000, bfe5a840, 0xbfe5a840) <- fff43276
|
| dest bfd79000, end bfe5a840, bouncebuffer bfd79000
|
| move suffix around: from bfdee06c, to 17506c, amount: 6c7d4
|
| Loaded segments
|
| BS: BS_PAYLOAD_LOAD times (us): entry 0 run 166960 exit 0
|
| PCH watchdog disabled
|
| Jumping to boot code at 00008200
|
| CPU0: stack: 00170000 - 00171000, lowest used address 00170abc, stack used: 1348 bytes
|
| entry = 0x00008200
|
| lb_start = 0x00100000
|
| lb_size = 0x0007506c
|
| buffer = 0xbfd79000
|
| error: file `/boot/grub/fonts/unicode.pf2' not found. |
|
|