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Kevin O'Connor1f2c3072009-05-06 23:35:59 -04001// QEMU Cirrus CLGD 54xx VGABIOS Extension.
2//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (c) 2004 Makoto Suzuki (suzu)
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
Kevin O'Connord83c87b2013-01-21 01:14:12 -05008#include "clext.h" // clext_setup
Kevin O'Connor6f775082011-12-31 18:39:59 -05009#include "vgabios.h" // VBE_VENDOR_STRING
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040010#include "biosvar.h" // GET_GLOBAL
11#include "util.h" // dprintf
Kevin O'Connor3c065362011-12-27 21:34:33 -050012#include "bregs.h" // struct bregs
Kevin O'Connored68e5b2011-12-31 04:15:12 -050013#include "stdvga.h" // VGAREG_SEQU_ADDRESS
Kevin O'Connor5d369d82013-09-02 20:48:46 -040014#include "hw/pci.h" // pci_config_readl
15#include "hw/pci_regs.h" // PCI_BASE_ADDRESS_0
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040016#include "string.h" // memset16_far
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040017
Kevin O'Connore48a5372011-12-20 23:56:14 -050018
19/****************************************************************
Kevin O'Connora96d4902012-02-01 21:10:44 -050020 * Cirrus mode tables
Kevin O'Connore48a5372011-12-20 23:56:14 -050021 ****************************************************************/
22
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040023/* VGA */
24static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
25static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
26static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
27
28/* extensions */
29static u16 cgraph_svgacolor[] VAR16 = {
30 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
31 0x0009,0x000a,0x000b,
32 0xffff
33};
34/* 640x480x8 */
35static u16 cseq_640x480x8[] VAR16 = {
36 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
37 0x580b,0x580c,0x580d,0x580e,
38 0x0412,0x0013,0x2017,
39 0x331b,0x331c,0x331d,0x331e,
40 0xffff
41};
42static u16 ccrtc_640x480x8[] VAR16 = {
43 0x2c11,
44 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
45 0x4009,0x000c,0x000d,
46 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
47 0x001a,0x221b,0x001d,
48 0xffff
49};
50/* 640x480x16 */
51static u16 cseq_640x480x16[] VAR16 = {
52 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
53 0x580b,0x580c,0x580d,0x580e,
54 0x0412,0x0013,0x2017,
55 0x331b,0x331c,0x331d,0x331e,
56 0xffff
57};
58static u16 ccrtc_640x480x16[] VAR16 = {
59 0x2c11,
60 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
61 0x4009,0x000c,0x000d,
62 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
63 0x001a,0x221b,0x001d,
64 0xffff
65};
66/* 640x480x24 */
67static u16 cseq_640x480x24[] VAR16 = {
68 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
69 0x580b,0x580c,0x580d,0x580e,
70 0x0412,0x0013,0x2017,
71 0x331b,0x331c,0x331d,0x331e,
72 0xffff
73};
74static u16 ccrtc_640x480x24[] VAR16 = {
75 0x2c11,
76 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
77 0x4009,0x000c,0x000d,
Kevin O'Connore19a68f2012-01-14 14:52:01 -050078 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
79 0x001a,0x221b,0x001d,
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040080 0xffff
81};
82/* 800x600x8 */
83static u16 cseq_800x600x8[] VAR16 = {
84 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
85 0x230b,0x230c,0x230d,0x230e,
86 0x0412,0x0013,0x2017,
87 0x141b,0x141c,0x141d,0x141e,
88 0xffff
89};
90static u16 ccrtc_800x600x8[] VAR16 = {
91 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
92 0x6009,0x000c,0x000d,
93 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
94 0x001a,0x221b,0x001d,
95 0xffff
96};
97/* 800x600x16 */
98static u16 cseq_800x600x16[] VAR16 = {
99 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
100 0x230b,0x230c,0x230d,0x230e,
101 0x0412,0x0013,0x2017,
102 0x141b,0x141c,0x141d,0x141e,
103 0xffff
104};
105static u16 ccrtc_800x600x16[] VAR16 = {
106 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
107 0x6009,0x000c,0x000d,
108 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
109 0x001a,0x221b,0x001d,
110 0xffff
111};
112/* 800x600x24 */
113static u16 cseq_800x600x24[] VAR16 = {
114 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
115 0x230b,0x230c,0x230d,0x230e,
116 0x0412,0x0013,0x2017,
117 0x141b,0x141c,0x141d,0x141e,
118 0xffff
119};
120static u16 ccrtc_800x600x24[] VAR16 = {
121 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
122 0x6009,0x000c,0x000d,
123 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
124 0x001a,0x321b,0x001d,
125 0xffff
126};
127/* 1024x768x8 */
128static u16 cseq_1024x768x8[] VAR16 = {
129 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
130 0x760b,0x760c,0x760d,0x760e,
131 0x0412,0x0013,0x2017,
132 0x341b,0x341c,0x341d,0x341e,
133 0xffff
134};
135static u16 ccrtc_1024x768x8[] VAR16 = {
136 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
137 0x6009,0x000c,0x000d,
138 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
139 0x001a,0x221b,0x001d,
140 0xffff
141};
142/* 1024x768x16 */
143static u16 cseq_1024x768x16[] VAR16 = {
144 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
145 0x760b,0x760c,0x760d,0x760e,
146 0x0412,0x0013,0x2017,
147 0x341b,0x341c,0x341d,0x341e,
148 0xffff
149};
150static u16 ccrtc_1024x768x16[] VAR16 = {
151 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
152 0x6009,0x000c,0x000d,
153 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
154 0x001a,0x321b,0x001d,
155 0xffff
156};
157/* 1024x768x24 */
158static u16 cseq_1024x768x24[] VAR16 = {
159 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
160 0x760b,0x760c,0x760d,0x760e,
161 0x0412,0x0013,0x2017,
162 0x341b,0x341c,0x341d,0x341e,
163 0xffff
164};
165static u16 ccrtc_1024x768x24[] VAR16 = {
166 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
167 0x6009,0x000c,0x000d,
168 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
169 0x001a,0x321b,0x001d,
170 0xffff
171};
172/* 1280x1024x8 */
173static u16 cseq_1280x1024x8[] VAR16 = {
174 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
175 0x760b,0x760c,0x760d,0x760e,
176 0x0412,0x0013,0x2017,
177 0x341b,0x341c,0x341d,0x341e,
178 0xffff
179};
180static u16 ccrtc_1280x1024x8[] VAR16 = {
181 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
182 0x6009,0x000c,0x000d,
183 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
184 0x001a,0x221b,0x001d,
185 0xffff
186};
187/* 1280x1024x16 */
188static u16 cseq_1280x1024x16[] VAR16 = {
189 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
190 0x760b,0x760c,0x760d,0x760e,
191 0x0412,0x0013,0x2017,
192 0x341b,0x341c,0x341d,0x341e,
193 0xffff
194};
195static u16 ccrtc_1280x1024x16[] VAR16 = {
196 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
197 0x6009,0x000c,0x000d,
198 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
199 0x001a,0x321b,0x001d,
200 0xffff
201};
202
203/* 1600x1200x8 */
204static u16 cseq_1600x1200x8[] VAR16 = {
205 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
206 0x760b,0x760c,0x760d,0x760e,
207 0x0412,0x0013,0x2017,
208 0x341b,0x341c,0x341d,0x341e,
209 0xffff
210};
211static u16 ccrtc_1600x1200x8[] VAR16 = {
212 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
213 0x6009,0x000c,0x000d,
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500214 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400215 0x001a,0x221b,0x001d,
216 0xffff
217};
218
Kevin O'Connor643290f2012-01-13 22:08:52 -0500219struct cirrus_mode_s {
Kevin O'Connora96d4902012-02-01 21:10:44 -0500220 u16 mode, vesamode;
Kevin O'Connor643290f2012-01-13 22:08:52 -0500221 struct vgamode_s info;
222
223 u16 hidden_dac; /* 0x3c6 */
224 u16 *seq; /* 0x3c4 */
225 u16 *graph; /* 0x3ce */
226 u16 *crtc; /* 0x3d4 */
227};
228
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400229static struct cirrus_mode_s cirrus_modes[] VAR16 = {
Kevin O'Connora96d4902012-02-01 21:10:44 -0500230 {0x5f,0x101,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500231 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500232 {0x64,0x111,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500233 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500234 {0x66,0x110,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500235 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500236 {0x71,0x112,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500237 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400238
Kevin O'Connora96d4902012-02-01 21:10:44 -0500239 {0x5c,0x103,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500240 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500241 {0x65,0x114,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500242 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500243 {0x67,0x113,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500244 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400245
Kevin O'Connora96d4902012-02-01 21:10:44 -0500246 {0x60,0x105,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500247 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500248 {0x74,0x117,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500249 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500250 {0x68,0x116,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500251 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400252
Kevin O'Connora96d4902012-02-01 21:10:44 -0500253 {0x78,0x115,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500254 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500255 {0x79,0x118,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500256 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400257
Kevin O'Connora96d4902012-02-01 21:10:44 -0500258 {0x6d,0x107,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500259 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500260 {0x69,0x119,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500261 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
Kevin O'Connora96d4902012-02-01 21:10:44 -0500262 {0x75,0x11a,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500263 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400264
Kevin O'Connora96d4902012-02-01 21:10:44 -0500265 {0x7b,0xffff,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500266 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400267};
268
Kevin O'Connor2c8ba892012-01-02 10:51:26 -0500269static struct cirrus_mode_s mode_switchback VAR16 =
Kevin O'Connora96d4902012-02-01 21:10:44 -0500270 {0xfe,0xffff,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
Kevin O'Connore48a5372011-12-20 23:56:14 -0500271
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500272int
273is_cirrus_mode(struct vgamode_s *vmode_g)
274{
275 return (vmode_g >= &cirrus_modes[0].info
276 && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
277}
278
Kevin O'Connora96d4902012-02-01 21:10:44 -0500279struct vgamode_s *
280clext_find_mode(int mode)
281{
282 struct cirrus_mode_s *table_g = cirrus_modes;
283 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
284 if (GET_GLOBAL(table_g->mode) == mode
285 || GET_GLOBAL(table_g->vesamode) == mode)
286 return &table_g->info;
287 table_g++;
288 }
289 return stdvga_find_mode(mode);
290}
291
Kevin O'Connor59f75d42012-01-27 20:52:29 -0500292void
293clext_list_modes(u16 seg, u16 *dest, u16 *last)
294{
295 int i;
Kevin O'Connora96d4902012-02-01 21:10:44 -0500296 for (i=0; i<ARRAY_SIZE(cirrus_modes) && dest<last; i++) {
297 u16 mode = GET_GLOBAL(cirrus_modes[i].vesamode);
298 if (mode == 0xffff)
299 continue;
300 SET_FARVAR(seg, *dest, mode);
Kevin O'Connor59f75d42012-01-27 20:52:29 -0500301 dest++;
302 }
303 stdvga_list_modes(seg, dest, last);
304}
305
Kevin O'Connor643290f2012-01-13 22:08:52 -0500306
Kevin O'Connora96d4902012-02-01 21:10:44 -0500307/****************************************************************
308 * helper functions
309 ****************************************************************/
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500310
Kevin O'Connor9961f992012-01-21 11:53:44 -0500311int
312clext_get_window(struct vgamode_s *vmode_g, int window)
313{
314 return stdvga_grdc_read(window + 9);
315}
316
317int
318clext_set_window(struct vgamode_s *vmode_g, int window, int val)
319{
320 if (val >= 0x100)
321 return -1;
322 stdvga_grdc_write(window + 9, val);
323 return 0;
324}
325
Kevin O'Connor3876b532012-01-24 00:07:44 -0500326int
327clext_get_linelength(struct vgamode_s *vmode_g)
328{
329 u16 crtc_addr = stdvga_get_crtc();
330 u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
331 u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400332 return (((reg1b & 0x10) << 4) + reg13) * 8 / stdvga_vram_ratio(vmode_g);
Kevin O'Connor3876b532012-01-24 00:07:44 -0500333}
334
335int
336clext_set_linelength(struct vgamode_s *vmode_g, int val)
337{
338 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400339 val = DIV_ROUND_UP(val * stdvga_vram_ratio(vmode_g), 8);
340 stdvga_crtc_write(crtc_addr, 0x13, val);
341 stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (val & 0x100) >> 4);
Kevin O'Connor3876b532012-01-24 00:07:44 -0500342 return 0;
343}
344
Kevin O'Connord61fc532012-01-27 20:37:45 -0500345int
346clext_get_displaystart(struct vgamode_s *vmode_g)
347{
348 u16 crtc_addr = stdvga_get_crtc();
349 u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
350 u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
351 u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
352 u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
353 int val = (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
354 | ((b4 & 0x80) << 12));
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400355 return val * 4 / stdvga_vram_ratio(vmode_g);
Kevin O'Connord61fc532012-01-27 20:37:45 -0500356}
357
358int
359clext_set_displaystart(struct vgamode_s *vmode_g, int val)
360{
361 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400362 val = val * stdvga_vram_ratio(vmode_g) / 4;
Kevin O'Connord61fc532012-01-27 20:37:45 -0500363 stdvga_crtc_write(crtc_addr, 0x0d, val);
364 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
365 stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (val & 0x0800) >> 4);
366 stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
367 , ((val & 0x0100) >> 8) | ((val & 0x0600) >> 7));
368 return 0;
369}
370
Kevin O'Connor2469f892012-02-04 12:40:02 -0500371int
372clext_size_state(int states)
373{
374 if (states & 8)
375 return -1;
376 return stdvga_size_state(states);
377}
378
379int
380clext_save_state(u16 seg, void *data, int states)
381{
382 if (states & 8)
383 return -1;
384 return stdvga_save_state(seg, data, states);
385}
386
387int
388clext_restore_state(u16 seg, void *data, int states)
389{
390 if (states & 8)
391 return -1;
392 return stdvga_restore_state(seg, data, states);
393}
394
Kevin O'Connor987029a2012-02-01 21:16:34 -0500395
396/****************************************************************
397 * Mode setting
398 ****************************************************************/
399
400static void
401cirrus_switch_mode_setregs(u16 *data, u16 port)
402{
403 for (;;) {
404 u16 val = GET_GLOBAL(*data);
405 if (val == 0xffff)
406 return;
407 outw(val, port);
408 data++;
409 }
410}
411
412static void
413cirrus_switch_mode(struct cirrus_mode_s *table)
414{
415 // Unlock cirrus special
416 stdvga_sequ_write(0x06, 0x12);
417 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
418 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
419 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
420
421 stdvga_pelmask_write(0x00);
422 stdvga_pelmask_read();
423 stdvga_pelmask_read();
424 stdvga_pelmask_read();
425 stdvga_pelmask_read();
426 stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
427 stdvga_pelmask_write(0xff);
428
429 u8 memmodel = GET_GLOBAL(table->info.memmodel);
430 u8 on = 0;
431 if (memmodel == MM_PLANAR)
432 on = 0x41;
433 else if (memmodel != MM_TEXT)
434 on = 0x01;
435 stdvga_attr_mask(0x10, 0x01, on);
Laszlo Ersek2eeafbf2013-02-14 05:43:32 +0100436 stdvga_attrindex_write(0x20);
Kevin O'Connor987029a2012-02-01 21:16:34 -0500437}
438
Kevin O'Connore48a5372011-12-20 23:56:14 -0500439static void
440cirrus_enable_16k_granularity(void)
441{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500442 stdvga_grdc_mask(0x0b, 0x00, 0x20);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500443}
444
445static void
Kevin O'Connorb7b92932013-03-09 13:04:47 -0500446cirrus_clear_vram(u16 fill)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500447{
448 cirrus_enable_16k_granularity();
Kevin O'Connorb7b92932013-03-09 13:04:47 -0500449 int count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
450 int i;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500451 for (i=0; i<count; i++) {
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500452 stdvga_grdc_write(0x09, i);
Kevin O'Connorb7b92932013-03-09 13:04:47 -0500453 memset16_far(SEG_GRAPH, 0, fill, 16 * 1024);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500454 }
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500455 stdvga_grdc_write(0x09, 0x00);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500456}
457
458int
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500459clext_set_mode(struct vgamode_s *vmode_g, int flags)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400460{
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500461 if (!is_cirrus_mode(vmode_g)) {
462 cirrus_switch_mode(&mode_switchback);
463 dprintf(1, "cirrus mode switch regular\n");
464 return stdvga_set_mode(vmode_g, flags);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400465 }
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500466 struct cirrus_mode_s *table_g = container_of(
467 vmode_g, struct cirrus_mode_s, info);
468 cirrus_switch_mode(table_g);
469 if (!(flags & MF_LINEARFB))
470 cirrus_enable_16k_granularity();
471 if (!(flags & MF_NOCLEARMEM))
Kevin O'Connorb7b92932013-03-09 13:04:47 -0500472 // fill with 0xff to keep win 2K happy
473 cirrus_clear_vram(flags & MF_LEGACY ? 0xffff : 0x0000);
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500474 return 0;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400475}
476
Kevin O'Connore48a5372011-12-20 23:56:14 -0500477
478/****************************************************************
479 * extbios
480 ****************************************************************/
481
482static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500483clext_101280(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500484{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500485 u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500486 if (v == 0xa0)
487 // 5430
488 regs->ax = 0x0032;
489 else if (v == 0xb8)
490 // 5446
491 regs->ax = 0x0039;
492 else
493 regs->ax = 0x00ff;
494 regs->bx = 0x00;
495 return;
496}
497
498static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500499clext_101281(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500500{
501 // XXX
502 regs->ax = 0x0100;
503}
504
505static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500506clext_101282(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500507{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500508 regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500509 regs->ah = 0xAF;
510}
511
512static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500513clext_101285(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500514{
Kevin O'Connor5e1694c2012-01-21 10:43:30 -0500515 regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500516}
517
518static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500519clext_10129a(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500520{
521 regs->ax = 0x4060;
522 regs->cx = 0x1132;
523}
524
525extern void a0h_callback(void);
526ASM16(
527 // fatal: not implemented yet
528 "a0h_callback:"
529 "cli\n"
530 "hlt\n"
Kevin O'Connor900ded02012-03-05 17:10:13 -0500531 "lretw");
Kevin O'Connore48a5372011-12-20 23:56:14 -0500532
533static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500534clext_1012a0(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500535{
Kevin O'Connora96d4902012-02-01 21:10:44 -0500536 struct vgamode_s *table_g = clext_find_mode(regs->al & 0x7f);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500537 regs->ah = (table_g ? 1 : 0);
Kevin O'Connor4c85a262012-02-12 11:50:52 -0500538 regs->bx = (u32)a0h_callback;
539 regs->ds = regs->si = regs->es = regs->di = 0xffff;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500540}
541
542static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500543clext_1012a1(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500544{
545 regs->bx = 0x0e00; // IBM 8512/8513, color
546}
547
548static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500549clext_1012a2(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500550{
551 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
552}
553
554static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500555clext_1012ae(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500556{
557 regs->al = 0x01; // High Refresh 75Hz
558}
559
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500560static void
561clext_1012XX(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500562{
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500563 debug_stub(regs);
564}
565
566void
567clext_1012(struct bregs *regs)
568{
Kevin O'Connore48a5372011-12-20 23:56:14 -0500569 switch (regs->bl) {
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500570 case 0x80: clext_101280(regs); break;
571 case 0x81: clext_101281(regs); break;
572 case 0x82: clext_101282(regs); break;
573 case 0x85: clext_101285(regs); break;
574 case 0x9a: clext_10129a(regs); break;
575 case 0xa0: clext_1012a0(regs); break;
576 case 0xa1: clext_1012a1(regs); break;
577 case 0xa2: clext_1012a2(regs); break;
578 case 0xae: clext_1012ae(regs); break;
579 default: clext_1012XX(regs); break;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500580 }
581}
582
583
584/****************************************************************
Kevin O'Connore48a5372011-12-20 23:56:14 -0500585 * init
586 ****************************************************************/
587
Kevin O'Connor987029a2012-02-01 21:16:34 -0500588static int
589cirrus_check(void)
590{
591 stdvga_sequ_write(0x06, 0x92);
592 return stdvga_sequ_read(0x06) == 0x12;
593}
594
595static u8
596cirrus_get_memsize(void)
597{
598 // get DRAM band width
599 u8 v = stdvga_sequ_read(0x0f);
600 u8 x = (v >> 3) & 0x03;
601 if (x == 0x03 && v & 0x80)
602 // 4MB
603 return 0x40;
604 return 0x04 << x;
605}
606
Kevin O'Connor161d2012011-12-31 19:42:21 -0500607int
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500608clext_setup(void)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400609{
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500610 int ret = stdvga_setup();
Kevin O'Connor161d2012011-12-31 19:42:21 -0500611 if (ret)
612 return ret;
613
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400614 dprintf(1, "cirrus init\n");
615 if (! cirrus_check())
Kevin O'Connor161d2012011-12-31 19:42:21 -0500616 return -1;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400617 dprintf(1, "cirrus init 2\n");
618
Kevin O'Connorcfd7ef92012-02-02 22:52:17 -0500619 // memory setup
620 stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
621 // set vga mode
622 stdvga_sequ_write(0x07, 0x00);
623 // reset bitblt
624 stdvga_grdc_write(0x31, 0x04);
625 stdvga_grdc_write(0x31, 0x00);
626
627 if (GET_GLOBAL(HaveRunInit))
628 return 0;
629
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500630 u32 lfb_addr = 0;
Kevin O'Connor8cf8f8e2012-01-16 19:05:27 -0500631 int bdf = GET_GLOBAL(VgaBDF);
632 if (CONFIG_VGA_PCI && bdf >= 0)
633 lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500634 & PCI_BASE_ADDRESS_MEM_MASK);
635 SET_VGA(VBE_framebuffer, lfb_addr);
Kevin O'Connor643290f2012-01-13 22:08:52 -0500636 u16 totalmem = cirrus_get_memsize();
637 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
638 SET_VGA(VBE_win_granularity, 16);
639
Kevin O'Connor161d2012011-12-31 19:42:21 -0500640 return 0;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400641}