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Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit system callbacks
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2002 MandrakeSoft S.A.
5//
6// This file may be distributed under the terms of the GNU GPLv3 license.
7
8#include "util.h" // irq_restore
9#include "biosvar.h" // CONFIG_BIOS_TABLE
10#include "ioport.h" // inb
11#include "cmos.h" // inb_cmos
12
13#define RET_EUNSUPPORTED 0x86
14
15
16// Use PS2 System Control port A to set A20 enable
17static inline u8
18set_a20(u8 cond)
19{
20 // get current setting first
21 u8 newval, oldval = inb(PORT_A20);
22 if (cond)
23 newval = oldval | 0x02;
24 else
25 newval = oldval & ~0x02;
26 outb(newval, PORT_A20);
27
28 return (newval & 0x02) != 0;
29}
30
31static inline void
32handle_ret(struct bregs *regs, u8 code)
33{
34 regs->ah = code;
35 set_cf(regs, code);
36}
37
38static void
39handle_152400(struct bregs *regs)
40{
41 set_a20(0);
42 handle_ret(regs, 0);
43}
44
45static void
46handle_152401(struct bregs *regs)
47{
48 set_a20(1);
49 handle_ret(regs, 0);
50}
51
52static void
53handle_152402(struct bregs *regs)
54{
55 regs->al = !!(inb(PORT_A20) & 0x20);
56 handle_ret(regs, 0);
57}
58
59static void
60handle_152403(struct bregs *regs)
61{
62 regs->bx = 3;
63 handle_ret(regs, 0);
64}
65
66static void
67handle_1524XX(struct bregs *regs)
68{
69 handle_ret(regs, RET_EUNSUPPORTED);
70}
71
72// removable media eject
73static void
74handle_1552(struct bregs *regs)
75{
76 handle_ret(regs, 0);
77}
78
79// Set Interval requested.
80static void
81handle_158300(struct bregs *regs)
82{
83 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) {
84 // Interval already set.
85 DEBUGF("int15: Func 83h, failed, already waiting.\n" );
86 handle_ret(regs, RET_EUNSUPPORTED);
87 }
88 // Interval not already set.
89 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
90 u32 v = (regs->es << 16) | regs->bx;
91 SET_BDA(ptr_user_wait_complete_flag, v);
92 v = (regs->dx << 16) | regs->cx;
93 SET_BDA(user_wait_timeout, v);
94
95 // Unmask IRQ8 so INT70 will get through.
96 u8 irqDisable = inb(PORT_PIC2_DATA);
97 outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
98 // Turn on the Periodic Interrupt timer
99 u8 bRegister = inb_cmos(CMOS_STATUS_B);
100 outb_cmos(CMOS_STATUS_B, bRegister | CSB_EN_ALARM_IRQ);
101
102 set_cf(regs, 0); // XXX - no set ah?
103}
104
105// Clear interval requested
106static void
107handle_158301(struct bregs *regs)
108{
109 SET_BDA(rtc_wait_flag, 0); // Clear status byte
110 // Turn off the Periodic Interrupt timer
111 u8 bRegister = inb_cmos(CMOS_STATUS_B);
112 outb_cmos(CMOS_STATUS_B, bRegister & ~CSB_EN_ALARM_IRQ);
113 set_cf(regs, 0); // XXX - no set ah?
114}
115
116static void
117handle_1583XX(struct bregs *regs)
118{
119 regs->al--;
120 handle_ret(regs, RET_EUNSUPPORTED);
121}
122
123// Sleep for n microseconds. currently using the
124// refresh request port 0x61 bit4, toggling every 15usec
125static void
126usleep(u32 count)
127{
128 count = count / 15;
129 u8 kbd = inb(PORT_KBD_CTRLB);
130 while (count)
131 if ((inb(PORT_KBD_CTRLB) ^ kbd) & KBD_REFRESH)
132 count--;
133}
134
135// Wait for CX:DX microseconds. currently using the
136// refresh request port 0x61 bit4, toggling every 15usec
137static void
138handle_1586(struct bregs *regs)
139{
140 irq_enable();
141 usleep((regs->cx << 16) | regs->dx);
142 irq_disable();
143}
144
145static void
146handle_1587(struct bregs *regs)
147{
148 // +++ should probably have descriptor checks
149 // +++ should have exception handlers
150
151 // turn off interrupts
152 unsigned long flags = irq_save();
153
154 u8 prev_a20_enable = set_a20(1); // enable A20 line
155
156 // 128K max of transfer on 386+ ???
157 // source == destination ???
158
159 // ES:SI points to descriptor table
160 // offset use initially comments
161 // ==============================================
162 // 00..07 Unused zeros Null descriptor
163 // 08..0f GDT zeros filled in by BIOS
164 // 10..17 source ssssssss source of data
165 // 18..1f dest dddddddd destination of data
166 // 20..27 CS zeros filled in by BIOS
167 // 28..2f SS zeros filled in by BIOS
168
169 //es:si
170 //eeee0
171 //0ssss
172 //-----
173
174// check for access rights of source & dest here
175
176 // Initialize GDT descriptor
177 u16 si = regs->si;
178 u16 base15_00 = (regs->es << 4) + si;
179 u16 base23_16 = regs->es >> 12;
180 if (base15_00 < (regs->es<<4))
181 base23_16++;
182 SET_VAR(ES, *(u16*)(si+0x08+0), 47); // limit 15:00 = 6 * 8bytes/descriptor
183 SET_VAR(ES, *(u16*)(si+0x08+2), base15_00);// base 15:00
184 SET_VAR(ES, *(u8 *)(si+0x08+4), base23_16);// base 23:16
185 SET_VAR(ES, *(u8 *)(si+0x08+5), 0x93); // access
186 SET_VAR(ES, *(u16*)(si+0x08+6), 0x0000); // base 31:24/reserved/limit 19:16
187
188 // Initialize CS descriptor
189 SET_VAR(ES, *(u16*)(si+0x20+0), 0xffff);// limit 15:00 = normal 64K limit
190 SET_VAR(ES, *(u16*)(si+0x20+2), 0x0000);// base 15:00
191 SET_VAR(ES, *(u8 *)(si+0x20+4), 0x000f);// base 23:16
192 SET_VAR(ES, *(u8 *)(si+0x20+5), 0x9b); // access
193 SET_VAR(ES, *(u16*)(si+0x20+6), 0x0000);// base 31:24/reserved/limit 19:16
194
195 // Initialize SS descriptor
196 u16 ss = GET_SEG(SS);
197 base15_00 = ss << 4;
198 base23_16 = ss >> 12;
199 SET_VAR(ES, *(u16*)(si+0x28+0), 0xffff); // limit 15:00 = normal 64K limit
200 SET_VAR(ES, *(u16*)(si+0x28+2), base15_00);// base 15:00
201 SET_VAR(ES, *(u8 *)(si+0x28+4), base23_16);// base 23:16
202 SET_VAR(ES, *(u8 *)(si+0x28+5), 0x93); // access
203 SET_VAR(ES, *(u16*)(si+0x28+6), 0x0000); // base 31:24/reserved/limit 19:16
204
205 asm volatile(
206 // Save registers
207 "pushw %%ds\n"
208 "pushw %%es\n"
209 "pushal\n"
210
211 // Load new descriptor tables
212 "lgdt %%es:(%1)\n"
213 "lidt %%cs:pmode_IDT_info\n"
214
215 // set PE bit in CR0
216 "movl %%cr0, %%eax\n"
217 "orb $0x01, %%al\n"
218 "movl %%eax, %%cr0\n"
219
220 // far jump to flush CPU queue after transition to protected mode
221 "ljmpw $0xf000, $1f\n"
222 "1:\n"
223
224 // GDT points to valid descriptor table, now load DS, ES
225 "movw $0x10, %%ax\n" // 010 000 = 2nd descriptor in table, TI=GDT, RPL=00
226 "movw %%ax, %%ds\n"
227 "movw $0x18, %%ax\n" // 011 000 = 3rd descriptor in table, TI=GDT, RPL=00
228 "movw %%ax, %%es\n"
229
230 // move CX words from DS:SI to ES:DI
231 "xorw %%si, %%si\n"
232 "xorw %%di, %%di\n"
233 "cld\n"
234 "rep movsw\n"
235
236 // reset PG bit in CR0 ???
237 "movl %%cr0, %%eax\n"
238 "andb $0xfe, %%al\n"
239 "movl %%eax, %%cr0\n"
240
241 // far jump to flush CPU queue after transition to real mode
242 "ljmpw $0xf000, $2f\n"
243 "2:\n"
244
245 // restore IDT to normal real-mode defaults
246 "lidt %%cs:rmode_IDT_info\n"
247
248 // restore regisers
249 "popal\n"
250 "popw %%es\n"
251 "popw %%ds\n" : : "c" (regs->cx), "r" (si + 8));
252
253 set_a20(prev_a20_enable);
254
255 irq_restore(flags);
256
257 handle_ret(regs, 0);
258}
259
260// Get the amount of extended memory (above 1M)
261static void
262handle_1588(struct bregs *regs)
263{
264 regs->al = inb_cmos(CMOS_EXTMEM_LOW);
265 regs->ah = inb_cmos(CMOS_EXTMEM_HIGH);
266 // According to Ralf Brown's interrupt the limit should be 15M,
267 // but real machines mostly return max. 63M.
268 if (regs->ax > 0xffc0)
269 regs->ax = 0xffc0;
270 set_cf(regs, 0);
271}
272
273// Device busy interrupt. Called by Int 16h when no key available
274static void
275handle_1590(struct bregs *regs)
276{
277}
278
279// Interrupt complete. Called by Int 16h when key becomes available
280static void
281handle_1591(struct bregs *regs)
282{
283}
284
285static void
286handle_15c0(struct bregs *regs)
287{
288 regs->es = SEG_BIOS;
289 regs->bx = (u16)&BIOS_CONFIG_TABLE;
290}
291
292static void
293handle_15c1(struct bregs *regs)
294{
295 regs->es = GET_BDA(ebda_seg);
296 set_cf(regs, 0);
297}
298
299static void
300handle_15e801(struct bregs *regs)
301{
302 // my real system sets ax and bx to 0
303 // this is confirmed by Ralph Brown list
304 // but syslinux v1.48 is known to behave
305 // strangely if ax is set to 0
306 // regs.u.r16.ax = 0;
307 // regs.u.r16.bx = 0;
308
309 // Get the amount of extended memory (above 1M)
310 regs->cl = inb_cmos(CMOS_EXTMEM_LOW);
311 regs->ch = inb_cmos(CMOS_EXTMEM_HIGH);
312
313 // limit to 15M
314 if (regs->cx > 0x3c00)
315 regs->cx = 0x3c00;
316
317 // Get the amount of extended memory above 16M in 64k blocs
318 regs->dl = inb_cmos(CMOS_EXTMEM2_LOW);
319 regs->dh = inb_cmos(CMOS_EXTMEM2_HIGH);
320
321 // Set configured memory equal to extended memory
322 regs->ax = regs->cx;
323 regs->bx = regs->dx;
324
325 set_cf(regs, 0);
326}
327
328#define ACPI_DATA_SIZE 0x00010000L
329
330static void
331set_e820_range(u16 DI, u32 start, u32 end, u16 type)
332{
333 SET_VAR(ES, *(u16*)(DI+0), start);
334 SET_VAR(ES, *(u16*)(DI+2), start >> 16);
335 SET_VAR(ES, *(u16*)(DI+4), 0x00);
336 SET_VAR(ES, *(u16*)(DI+6), 0x00);
337
338 end -= start;
339 SET_VAR(ES, *(u16*)(DI+8), end);
340 SET_VAR(ES, *(u16*)(DI+10), end >> 16);
341 SET_VAR(ES, *(u16*)(DI+12), 0x0000);
342 SET_VAR(ES, *(u16*)(DI+14), 0x0000);
343
344 SET_VAR(ES, *(u16*)(DI+16), type);
345 SET_VAR(ES, *(u16*)(DI+18), 0x0);
346}
347
348// XXX - should create e820 memory map in post and just copy it here.
349static void
350handle_15e820(struct bregs *regs)
351{
352 if (regs->edx != 0x534D4150) {
353 handle_ret(regs, RET_EUNSUPPORTED);
354 return;
355 }
356
357 u32 extended_memory_size = inb_cmos(CMOS_EXTMEM2_HIGH);
358 extended_memory_size <<= 8;
359 extended_memory_size |= inb_cmos(CMOS_EXTMEM2_LOW);
360 extended_memory_size *= 64;
361 // greater than EFF00000???
362 if (extended_memory_size > 0x3bc000)
363 // everything after this is reserved memory until we get to 0x100000000
364 extended_memory_size = 0x3bc000;
365 extended_memory_size *= 1024;
366 extended_memory_size += (16L * 1024 * 1024);
367
368 if (extended_memory_size <= (16L * 1024 * 1024)) {
369 extended_memory_size = inb_cmos(CMOS_EXTMEM_HIGH);
370 extended_memory_size <<= 8;
371 extended_memory_size |= inb_cmos(CMOS_EXTMEM_LOW);
372 extended_memory_size *= 1024;
373 }
374
375 switch (regs->bx) {
376 case 0:
377 set_e820_range(regs->di, 0x0000000L, 0x0009fc00L, 1);
378 regs->ebx = 1;
379 regs->eax = 0x534D4150;
380 regs->ecx = 0x14;
381 set_cf(regs, 0);
382 break;
383 case 1:
384 set_e820_range(regs->di, 0x0009fc00L, 0x000a0000L, 2);
385 regs->ebx = 2;
386 regs->eax = 0x534D4150;
387 regs->ecx = 0x14;
388 set_cf(regs, 0);
389 break;
390 case 2:
391 set_e820_range(regs->di, 0x000e8000L, 0x00100000L, 2);
392 regs->ebx = 3;
393 regs->eax = 0x534D4150;
394 regs->ecx = 0x14;
395 set_cf(regs, 0);
396 break;
397 case 3:
398 set_e820_range(regs->di, 0x00100000L,
399 extended_memory_size - ACPI_DATA_SIZE, 1);
400 regs->ebx = 4;
401 regs->eax = 0x534D4150;
402 regs->ecx = 0x14;
403 set_cf(regs, 0);
404 break;
405 case 4:
406 set_e820_range(regs->di,
407 extended_memory_size - ACPI_DATA_SIZE,
408 extended_memory_size, 3); // ACPI RAM
409 regs->ebx = 5;
410 regs->eax = 0x534D4150;
411 regs->ecx = 0x14;
412 set_cf(regs, 0);
413 break;
414 case 5:
415 /* 256KB BIOS area at the end of 4 GB */
416 set_e820_range(regs->di, 0xfffc0000L, 0x00000000L, 2);
417 regs->ebx = 0;
418 regs->eax = 0x534D4150;
419 regs->ecx = 0x14;
420 set_cf(regs, 0);
421 break;
422 default: /* AX=E820, DX=534D4150, BX unrecognized */
423 handle_ret(regs, RET_EUNSUPPORTED);
424 }
425}
426
427static void
428handle_15e8XX(struct bregs *regs)
429{
430 regs->al--;
431 handle_ret(regs, RET_EUNSUPPORTED);
432}
433
434static void
435handle_15XX(struct bregs *regs)
436{
437 regs->al--;
438 handle_ret(regs, RET_EUNSUPPORTED);
439}
440
441// INT 15h System Services Entry Point
442void VISIBLE
443handle_15(struct bregs *regs)
444{
445 debug_enter(regs);
446 switch (regs->ah) {
447 case 0x24:
448 switch (regs->al) {
449 case 0x00: handle_152400(regs); break;
450 case 0x01: handle_152401(regs); break;
451 case 0x02: handle_152402(regs); break;
452 case 0x03: handle_152403(regs); break;
453 default: handle_1524XX(regs); break;
454 }
455 break;
456 case 0x52: handle_1552(regs); break;
457 case 0x83:
458 switch (regs->al) {
459 case 0x00: handle_158300(regs); break;
460 case 0x01: handle_158301(regs); break;
461 default: handle_1583XX(regs); break;
462 }
463 break;
464 case 0x86: handle_1586(regs); break;
465 case 0x87: handle_1587(regs); break;
466 case 0x88: handle_1588(regs); break;
467 case 0x90: handle_1590(regs); break;
468 case 0x91: handle_1591(regs); break;
469 case 0xc0: handle_15c0(regs); break;
470 case 0xc1: handle_15c1(regs); break;
471 case 0xc2: handle_15c2(regs); break;
472 case 0xe8:
473 switch (regs->al) {
474 case 0x01: handle_15e801(regs); break;
475 case 0x20: handle_15e820(regs); break;
476 default: handle_15e8XX(regs); break;
477 }
478 break;
479 default: handle_15XX(regs); break;
480 }
481 debug_exit(regs);
482}
483
484// INT 12h Memory Size Service Entry Point
485void VISIBLE
486handle_12(struct bregs *regs)
487{
488 debug_enter(regs);
489 regs->ax = GET_BDA(mem_size_kb);
490 debug_exit(regs);
491}
492
493// INT 11h Equipment List Service Entry Point
494void VISIBLE
495handle_11(struct bregs *regs)
496{
497 debug_enter(regs);
498 regs->ax = GET_BDA(equipment_list_flags);
499 debug_exit(regs);
500}
501
502// INT 05h Print Screen Service Entry Point
503void VISIBLE
504handle_05(struct bregs *regs)
505{
506 debug_enter(regs);
507}
508
509// INT 10h Video Support Service Entry Point
510void VISIBLE
511handle_10(struct bregs *regs)
512{
513 debug_enter(regs);
514 // dont do anything, since the VGA BIOS handles int10h requests
515}
516
517void VISIBLE
518handle_nmi(struct bregs *regs)
519{
520 debug_enter(regs);
521 // XXX
522}
523
524// INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
525void VISIBLE
526handle_75(struct bregs *regs)
527{
528 debug_enter(regs);
529}