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Kevin O'Connore1e000b2011-12-31 03:30:40 -05001#include "vgabios.h" // struct vbe_modeinfo
Kevin O'Connor5108c692011-12-31 19:13:45 -05002#include "vbe.h" // VBE_MODE_VESA_DEFINED
3#include "bochsvga.h" // bochsvga_set_mode
4#include "util.h" // dprintf
Kevin O'Connore1e000b2011-12-31 03:30:40 -05005#include "config.h" // CONFIG_*
Julian Pidancet8bd766f2011-12-19 05:08:01 +00006#include "biosvar.h" // SET_BDA
Kevin O'Connored68e5b2011-12-31 04:15:12 -05007#include "stdvga.h" // VGAREG_SEQU_ADDRESS
Kevin O'Connor97cc3542012-01-14 16:59:21 -05008#include "pci.h" // pci_config_readl
9#include "pci_regs.h" // PCI_BASE_ADDRESS_0
Julian Pidancet87879e22011-12-19 05:08:00 +000010
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050011static struct bochsvga_mode
Julian Pidancet87879e22011-12-19 05:08:00 +000012{
13 u16 mode;
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050014 struct vgamode_s info;
Kevin O'Connorf1e217d2011-12-31 03:18:18 -050015} bochsvga_modes[] VAR16 = {
Julian Pidancet87879e22011-12-19 05:08:00 +000016 /* standard modes */
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050017 { 0x100, { MM_PACKED, 640, 400, 8 } },
18 { 0x101, { MM_PACKED, 640, 480, 8 } },
19 { 0x102, { MM_PLANAR, 800, 600, 4 } },
20 { 0x103, { MM_PACKED, 800, 600, 8 } },
21 { 0x104, { MM_PLANAR, 1024, 768, 4 } },
22 { 0x105, { MM_PACKED, 1024, 768, 8 } },
23 { 0x106, { MM_PLANAR, 1280, 1024, 4 } },
24 { 0x107, { MM_PACKED, 1280, 1024, 8 } },
25 { 0x10D, { MM_DIRECT, 320, 200, 15 } },
26 { 0x10E, { MM_DIRECT, 320, 200, 16 } },
27 { 0x10F, { MM_DIRECT, 320, 200, 24 } },
28 { 0x110, { MM_DIRECT, 640, 480, 15 } },
29 { 0x111, { MM_DIRECT, 640, 480, 16 } },
30 { 0x112, { MM_DIRECT, 640, 480, 24 } },
31 { 0x113, { MM_DIRECT, 800, 600, 15 } },
32 { 0x114, { MM_DIRECT, 800, 600, 16 } },
33 { 0x115, { MM_DIRECT, 800, 600, 24 } },
34 { 0x116, { MM_DIRECT, 1024, 768, 15 } },
35 { 0x117, { MM_DIRECT, 1024, 768, 16 } },
36 { 0x118, { MM_DIRECT, 1024, 768, 24 } },
37 { 0x119, { MM_DIRECT, 1280, 1024, 15 } },
38 { 0x11A, { MM_DIRECT, 1280, 1024, 16 } },
39 { 0x11B, { MM_DIRECT, 1280, 1024, 24 } },
40 { 0x11C, { MM_PACKED, 1600, 1200, 8 } },
41 { 0x11D, { MM_DIRECT, 1600, 1200, 15 } },
42 { 0x11E, { MM_DIRECT, 1600, 1200, 16 } },
43 { 0x11F, { MM_DIRECT, 1600, 1200, 24 } },
Julian Pidancet87879e22011-12-19 05:08:00 +000044 /* BOCHS modes */
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050045 { 0x140, { MM_DIRECT, 320, 200, 32 } },
46 { 0x141, { MM_DIRECT, 640, 400, 32 } },
47 { 0x142, { MM_DIRECT, 640, 480, 32 } },
48 { 0x143, { MM_DIRECT, 800, 600, 32 } },
49 { 0x144, { MM_DIRECT, 1024, 768, 32 } },
50 { 0x145, { MM_DIRECT, 1280, 1024, 32 } },
51 { 0x146, { MM_PACKED, 320, 200, 8 } },
52 { 0x147, { MM_DIRECT, 1600, 1200, 32 } },
53 { 0x148, { MM_PACKED, 1152, 864, 8 } },
54 { 0x149, { MM_DIRECT, 1152, 864, 15 } },
55 { 0x14a, { MM_DIRECT, 1152, 864, 16 } },
56 { 0x14b, { MM_DIRECT, 1152, 864, 24 } },
57 { 0x14c, { MM_DIRECT, 1152, 864, 32 } },
58 { 0x178, { MM_DIRECT, 1280, 800, 16 } },
59 { 0x179, { MM_DIRECT, 1280, 800, 24 } },
60 { 0x17a, { MM_DIRECT, 1280, 800, 32 } },
61 { 0x17b, { MM_DIRECT, 1280, 960, 16 } },
62 { 0x17c, { MM_DIRECT, 1280, 960, 24 } },
63 { 0x17d, { MM_DIRECT, 1280, 960, 32 } },
64 { 0x17e, { MM_DIRECT, 1440, 900, 16 } },
65 { 0x17f, { MM_DIRECT, 1440, 900, 24 } },
66 { 0x180, { MM_DIRECT, 1440, 900, 32 } },
67 { 0x181, { MM_DIRECT, 1400, 1050, 16 } },
68 { 0x182, { MM_DIRECT, 1400, 1050, 24 } },
69 { 0x183, { MM_DIRECT, 1400, 1050, 32 } },
70 { 0x184, { MM_DIRECT, 1680, 1050, 16 } },
71 { 0x185, { MM_DIRECT, 1680, 1050, 24 } },
72 { 0x186, { MM_DIRECT, 1680, 1050, 32 } },
73 { 0x187, { MM_DIRECT, 1920, 1200, 16 } },
74 { 0x188, { MM_DIRECT, 1920, 1200, 24 } },
75 { 0x189, { MM_DIRECT, 1920, 1200, 32 } },
76 { 0x18a, { MM_DIRECT, 2560, 1600, 16 } },
77 { 0x18b, { MM_DIRECT, 2560, 1600, 24 } },
78 { 0x18c, { MM_DIRECT, 2560, 1600, 32 } },
Julian Pidancet87879e22011-12-19 05:08:00 +000079};
80
Julian Pidancet8bd766f2011-12-19 05:08:01 +000081static u16 dispi_get_max_xres(void)
82{
83 u16 en;
84 u16 xres;
85
86 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
87
88 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
89 xres = dispi_read(VBE_DISPI_INDEX_XRES);
90 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
91
92 return xres;
93}
94
95static u16 dispi_get_max_bpp(void)
96{
97 u16 en;
98 u16 bpp;
99
100 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
101
102 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
103 bpp = dispi_read(VBE_DISPI_INDEX_BPP);
104 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
105
106 return bpp;
107}
108
Julian Pidancet87879e22011-12-19 05:08:00 +0000109/* Called only during POST */
110int
Kevin O'Connor161d2012011-12-31 19:42:21 -0500111bochsvga_init(void)
Julian Pidancet87879e22011-12-19 05:08:00 +0000112{
Kevin O'Connor161d2012011-12-31 19:42:21 -0500113 int ret = stdvga_init();
114 if (ret)
115 return ret;
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000116
117 /* Sanity checks */
118 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
119 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
120 dprintf(1, "No VBE DISPI interface detected\n");
121 return -1;
122 }
123
Kevin O'Connor3339c052012-01-13 20:00:35 -0500124 SET_VGA(VBE_enabled, 1);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000125 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
126
Kevin O'Connor161d2012011-12-31 19:42:21 -0500127 u32 lfb_addr;
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000128 if (CONFIG_VGA_PCI)
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500129 lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
130 & PCI_BASE_ADDRESS_MEM_MASK);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000131 else
132 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
133
Kevin O'Connor3339c052012-01-13 20:00:35 -0500134 SET_VGA(VBE_framebuffer, lfb_addr);
135 u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
136 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
137 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000138
Kevin O'Connor3339c052012-01-13 20:00:35 -0500139 dprintf(1, "VBE DISPI detected. lfb_addr=%x\n", lfb_addr);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000140
141 return 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000142}
143
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500144static int mode_valid(struct vgamode_s *vmode_g)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000145{
146 u16 max_xres = dispi_get_max_xres();
147 u16 max_bpp = dispi_get_max_bpp();
Kevin O'Connor3339c052012-01-13 20:00:35 -0500148 u32 max_mem = GET_GLOBAL(VBE_total_memory);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000149
Kevin O'Connor3339c052012-01-13 20:00:35 -0500150 u16 width = GET_GLOBAL(vmode_g->width);
151 u16 height = GET_GLOBAL(vmode_g->height);
152 u8 depth = GET_GLOBAL(vmode_g->depth);
153 u32 mem = width * height * DIV_ROUND_UP(depth, 8);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000154
Kevin O'Connor3339c052012-01-13 20:00:35 -0500155 return width <= max_xres && depth <= max_bpp && mem <= max_mem;
156}
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000157
Kevin O'Connor3339c052012-01-13 20:00:35 -0500158struct vgamode_s *bochsvga_find_mode(int mode)
159{
160 struct bochsvga_mode *m = bochsvga_modes;
161 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
162 if (GET_GLOBAL(m->mode) == mode) {
163 if (! mode_valid(&m->info))
164 return NULL;
165 return &m->info;
166 }
167 return stdvga_find_mode(mode);
Julian Pidancet87879e22011-12-19 05:08:00 +0000168}
169
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500170void
171bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
Julian Pidancet87879e22011-12-19 05:08:00 +0000172{
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500173 struct bochsvga_mode *m = bochsvga_modes;
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500174 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500175 if (!mode_valid(&m->info))
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000176 continue;
177
178 dprintf(1, "VBE found mode %x valid.\n", GET_GLOBAL(m->mode));
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500179 SET_FARVAR(seg, *dest, GET_GLOBAL(m->mode));
180 dest++;
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000181 }
Julian Pidancet87879e22011-12-19 05:08:00 +0000182
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500183 stdvga_list_modes(seg, dest, last);
Julian Pidancet87879e22011-12-19 05:08:00 +0000184}
185
Kevin O'Connor3339c052012-01-13 20:00:35 -0500186static void
Kevin O'Connorf1e217d2011-12-31 03:18:18 -0500187bochsvga_hires_enable(int enable)
Julian Pidancet87879e22011-12-19 05:08:00 +0000188{
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000189 u16 flags = enable ?
190 VBE_DISPI_ENABLED |
191 VBE_DISPI_LFB_ENABLED |
192 VBE_DISPI_NOCLEARMEM : 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000193
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000194 dispi_write(VBE_DISPI_INDEX_ENABLE, flags);
Julian Pidancet87879e22011-12-19 05:08:00 +0000195}
196
Kevin O'Connor3339c052012-01-13 20:00:35 -0500197static void
198bochsvga_clear_scr(void)
199{
200 u16 en;
201
202 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
203 en &= ~VBE_DISPI_NOCLEARMEM;
204 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
205}
206
Kevin O'Connor5108c692011-12-31 19:13:45 -0500207int
208bochsvga_set_mode(int mode, int flags)
Julian Pidancet87879e22011-12-19 05:08:00 +0000209{
Kevin O'Connor5108c692011-12-31 19:13:45 -0500210 if (!(mode & VBE_MODE_VESA_DEFINED)) {
211 dprintf(1, "set VGA mode %x\n", mode);
212
Kevin O'Connor3339c052012-01-13 20:00:35 -0500213 SET_BDA(vbe_mode, 0);
Kevin O'Connor5108c692011-12-31 19:13:45 -0500214 bochsvga_hires_enable(0);
215 return stdvga_set_mode(mode, flags);
216 }
217
Kevin O'Connor3339c052012-01-13 20:00:35 -0500218 struct vgamode_s *vmode_g = bochsvga_find_mode(mode);
219 if (!vmode_g) {
Kevin O'Connor5108c692011-12-31 19:13:45 -0500220 dprintf(1, "VBE mode %x not found\n", mode);
221 return VBE_RETURN_STATUS_FAILED;
222 }
223 bochsvga_hires_enable(1);
224
Kevin O'Connor3339c052012-01-13 20:00:35 -0500225 u8 depth = GET_GLOBAL(vmode_g->depth);
226 if (depth == 4)
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500227 stdvga_set_mode(0x6a, 0);
Kevin O'Connor3339c052012-01-13 20:00:35 -0500228 if (depth == 8)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000229 // XXX load_dac_palette(3);
230 ;
Julian Pidancet87879e22011-12-19 05:08:00 +0000231
Kevin O'Connor3339c052012-01-13 20:00:35 -0500232 dispi_write(VBE_DISPI_INDEX_BPP, depth);
233 u16 width = GET_GLOBAL(vmode_g->width);
234 u16 height = GET_GLOBAL(vmode_g->height);
235 dispi_write(VBE_DISPI_INDEX_XRES, width);
236 dispi_write(VBE_DISPI_INDEX_YRES, height);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000237 dispi_write(VBE_DISPI_INDEX_BANK, 0);
238
239 /* VGA compat setup */
240 //XXX: This probably needs some reverse engineering
Kevin O'Connor184705f2012-01-14 22:17:43 -0500241 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
242 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
243 stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1);
Kevin O'Connor3339c052012-01-13 20:00:35 -0500244 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, width);
Kevin O'Connor184705f2012-01-14 22:17:43 -0500245 stdvga_crtc_write(crtc_addr, 0x12, height - 1);
246 u8 v = 0;
247 if ((height - 1) & 0x0100)
248 v |= 0x02;
249 if ((height - 1) & 0x0200)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000250 v |= 0x40;
Kevin O'Connor184705f2012-01-14 22:17:43 -0500251 stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000252
Kevin O'Connor184705f2012-01-14 22:17:43 -0500253 stdvga_crtc_write(crtc_addr, 0x09, 0x00);
254 stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03);
255 stdvga_attr_mask(0x10, 0x00, 0x01);
256 stdvga_grdc_write(0x06, 0x05);
257 stdvga_sequ_write(0x02, 0x0f);
Kevin O'Connor3339c052012-01-13 20:00:35 -0500258 if (depth >= 8) {
Kevin O'Connor184705f2012-01-14 22:17:43 -0500259 stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40);
260 stdvga_attr_mask(0x10, 0x00, 0x40);
261 stdvga_sequ_mask(0x04, 0x00, 0x08);
262 stdvga_grdc_mask(0x05, 0x20, 0x40);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000263 }
264
Kevin O'Connor3339c052012-01-13 20:00:35 -0500265 SET_BDA(vbe_mode, mode | flags);
Kevin O'Connor5108c692011-12-31 19:13:45 -0500266
267 if (flags & MF_LINEARFB) {
268 /* Linear frame buffer */
269 /* XXX: ??? */
270 }
271 if (!(mode & MF_NOCLEARMEM)) {
272 bochsvga_clear_scr();
273 }
274
275 return 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000276}