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Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit code to handle system clocks.
2//
Kevin O'Connorabf31d32010-07-26 22:33:54 -04003// Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05004// Copyright (C) 2002 MandrakeSoft S.A.
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05007
Kevin O'Connor9521e262008-07-04 13:04:29 -04008#include "biosvar.h" // SET_BDA
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05009#include "util.h" // debug_enter
10#include "disk.h" // floppy_tick
Kevin O'Connor4b60c002008-02-25 22:29:55 -050011#include "cmos.h" // inb_cmos
Kevin O'Connord21c0892008-11-26 17:02:43 -050012#include "pic.h" // eoi_pic1
Kevin O'Connor9521e262008-07-04 13:04:29 -040013#include "bregs.h" // struct bregs
Kevin O'Connor15157a32008-12-13 11:10:37 -050014#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor0e885762010-05-01 22:14:40 -040015#include "usb-hid.h" // usb_check_event
Kevin O'Connor4b60c002008-02-25 22:29:55 -050016
Kevin O'Connor5be04902008-05-18 17:12:06 -040017// RTC register flags
18#define RTC_A_UIP 0x80
Kevin O'Connorf3587592009-02-15 13:02:56 -050019
20#define RTC_B_SET 0x80
21#define RTC_B_PIE 0x40
22#define RTC_B_AIE 0x20
23#define RTC_B_UIE 0x10
24#define RTC_B_BIN 0x04
25#define RTC_B_24HR 0x02
26#define RTC_B_DSE 0x01
27
Kevin O'Connor5be04902008-05-18 17:12:06 -040028
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050029// Bits for PORT_PS2_CTRLB
30#define PPCB_T2GATE (1<<0)
31#define PPCB_SPKR (1<<1)
32#define PPCB_T2OUT (1<<5)
33
34// Bits for PORT_PIT_MODE
35#define PM_SEL_TIMER0 (0<<6)
36#define PM_SEL_TIMER1 (1<<6)
37#define PM_SEL_TIMER2 (2<<6)
38#define PM_SEL_READBACK (3<<6)
39#define PM_ACCESS_LATCH (0<<4)
40#define PM_ACCESS_LOBYTE (1<<4)
41#define PM_ACCESS_HIBYTE (2<<4)
42#define PM_ACCESS_WORD (3<<4)
43#define PM_MODE0 (0<<1)
44#define PM_MODE1 (1<<1)
45#define PM_MODE2 (2<<1)
46#define PM_MODE3 (3<<1)
47#define PM_MODE4 (4<<1)
48#define PM_MODE5 (5<<1)
49#define PM_CNT_BINARY (0<<0)
50#define PM_CNT_BCD (1<<0)
Kevin O'Connor745de852012-01-29 14:15:14 -050051#define PM_READ_COUNTER0 (1<<1)
52#define PM_READ_COUNTER1 (1<<2)
53#define PM_READ_COUNTER2 (1<<3)
54#define PM_READ_STATUSVALUE (0<<4)
55#define PM_READ_VALUE (1<<4)
56#define PM_READ_STATUS (2<<4)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050057
58
59/****************************************************************
60 * TSC timer
61 ****************************************************************/
62
Kevin O'Connor6aee52d2009-09-27 20:07:40 -040063#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050064
Kevin O'Connor372e0712009-09-09 09:51:31 -040065u32 cpu_khz VAR16VISIBLE;
Kevin O'Connor745de852012-01-29 14:15:14 -050066u8 no_tsc VAR16VISIBLE;
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050067
68static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050069calibrate_tsc(void)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050070{
Kevin O'Connor745de852012-01-29 14:15:14 -050071 u32 eax, ebx, ecx, edx, cpuid_features = 0;
72 cpuid(0, &eax, &ebx, &ecx, &edx);
73 if (eax > 0)
74 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
75
76 if (!(cpuid_features & CPUID_TSC)) {
77 SET_GLOBAL(no_tsc, 1);
78 SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000);
79 dprintf(3, "386/486 class CPU. Using TSC emulation\n");
80 return;
81 }
82
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050083 // Setup "timer2"
84 u8 orig = inb(PORT_PS2_CTRLB);
85 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
86 /* binary, mode 0, LSB/MSB, Ch 2 */
87 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
88 /* LSB of ticks */
89 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
90 /* MSB of ticks */
91 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
92
93 u64 start = rdtscll();
94 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
95 ;
96 u64 end = rdtscll();
97
98 // Restore PORT_PS2_CTRLB
99 outb(orig, PORT_PS2_CTRLB);
100
101 // Store calibrated cpu khz.
102 u64 diff = end - start;
103 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
104 , (u32)start, (u32)end, (u32)diff);
105 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
Kevin O'Connor15157a32008-12-13 11:10:37 -0500106 SET_GLOBAL(cpu_khz, hz / 1000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500107
108 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
109}
110
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400111/* TSC emulation timekeepers */
112u64 TSC_8254 VARLOW;
113int Last_TSC_8254 VARLOW;
114
Kevin O'Connor745de852012-01-29 14:15:14 -0500115static u64
116emulate_tsc(void)
117{
Kevin O'Connor745de852012-01-29 14:15:14 -0500118 /* read timer 0 current count */
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400119 u64 ret = GET_LOW(TSC_8254);
120 /* readback mode has slightly shifted registers, works on all
121 * 8254, readback PIT0 latch */
Kevin O'Connor745de852012-01-29 14:15:14 -0500122 outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE);
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400123 int cnt = (inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8));
124 int d = GET_LOW(Last_TSC_8254) - cnt;
Kevin O'Connor745de852012-01-29 14:15:14 -0500125 /* Determine the ticks count from last invocation of this function */
126 ret += (d > 0) ? d : (PIT_TICK_INTERVAL + d);
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400127 SET_LOW(Last_TSC_8254, cnt);
128 SET_LOW(TSC_8254, ret);
Kevin O'Connor745de852012-01-29 14:15:14 -0500129 return ret;
130}
131
Gerd Hoffmann455a7c82012-09-06 08:01:00 +0200132u16 pmtimer_ioport VAR16VISIBLE;
133u32 pmtimer_wraps VARLOW;
134u32 pmtimer_last VARLOW;
135
136void pmtimer_init(u16 ioport, u32 khz)
137{
138 if (!CONFIG_PMTIMER)
139 return;
140 dprintf(1, "Using pmtimer, ioport 0x%x, freq %d kHz\n", ioport, khz);
141 SET_GLOBAL(pmtimer_ioport, ioport);
142 SET_GLOBAL(cpu_khz, khz);
143}
144
145static u64 pmtimer_get(void)
146{
147 u16 ioport = GET_GLOBAL(pmtimer_ioport);
148 u32 wraps = GET_LOW(pmtimer_wraps);
149 u32 pmtimer = inl(ioport) & 0xffffff;
150
151 if (pmtimer < GET_LOW(pmtimer_last)) {
152 wraps++;
153 SET_LOW(pmtimer_wraps, wraps);
154 }
155 SET_LOW(pmtimer_last, pmtimer);
156
157 dprintf(9, "pmtimer: %u:%u\n", wraps, pmtimer);
158 return (u64)wraps << 24 | pmtimer;
159}
160
Kevin O'Connor745de852012-01-29 14:15:14 -0500161static u64
162get_tsc(void)
163{
164 if (unlikely(GET_GLOBAL(no_tsc)))
165 return emulate_tsc();
Gerd Hoffmann455a7c82012-09-06 08:01:00 +0200166 if (CONFIG_PMTIMER && GET_GLOBAL(pmtimer_ioport))
167 return pmtimer_get();
Kevin O'Connor745de852012-01-29 14:15:14 -0500168 return rdtscll();
169}
170
171int
172check_tsc(u64 end)
173{
174 return (s64)(get_tsc() - end) > 0;
175}
176
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500177static void
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400178tscdelay(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500179{
Kevin O'Connor745de852012-01-29 14:15:14 -0500180 u64 start = get_tsc();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500181 u64 end = start + diff;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400182 while (!check_tsc(end))
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500183 cpu_relax();
184}
185
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400186static void
187tscsleep(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500188{
Kevin O'Connor745de852012-01-29 14:15:14 -0500189 u64 start = get_tsc();
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400190 u64 end = start + diff;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400191 while (!check_tsc(end))
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400192 yield();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500193}
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400194
195void ndelay(u32 count) {
196 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500197}
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400198void udelay(u32 count) {
199 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
200}
201void mdelay(u32 count) {
202 tscdelay(count * GET_GLOBAL(cpu_khz));
203}
204
205void nsleep(u32 count) {
206 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
207}
208void usleep(u32 count) {
209 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
210}
211void msleep(u32 count) {
212 tscsleep(count * GET_GLOBAL(cpu_khz));
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500213}
214
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500215// Return the TSC value that is 'msecs' time in the future.
216u64
217calc_future_tsc(u32 msecs)
218{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500219 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor745de852012-01-29 14:15:14 -0500220 return get_tsc() + ((u64)khz * msecs);
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500221}
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400222u64
223calc_future_tsc_usec(u32 usecs)
224{
225 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor745de852012-01-29 14:15:14 -0500226 return get_tsc() + ((u64)(khz/1000) * usecs);
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400227}
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500228
Kevin O'Connor5be04902008-05-18 17:12:06 -0400229
230/****************************************************************
231 * Init
232 ****************************************************************/
233
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500234static int
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500235rtc_updating(void)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500236{
237 // This function checks to see if the update-in-progress bit
238 // is set in CMOS Status Register A. If not, it returns 0.
239 // If it is set, it tries to wait until there is a transition
240 // to 0, and will return 0 if such a transition occurs. A -1
241 // is returned only after timing out. The maximum period
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500242 // that this bit should be set is constrained to (1984+244)
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500243 // useconds, but we wait for longer just to be sure.
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500244
Kevin O'Connorf3587592009-02-15 13:02:56 -0500245 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500246 return 0;
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500247 u64 end = calc_future_tsc(15);
248 for (;;) {
Kevin O'Connorf3587592009-02-15 13:02:56 -0500249 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500250 return 0;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400251 if (check_tsc(end))
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500252 // update-in-progress never transitioned to 0
253 return -1;
254 yield();
255 }
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500256}
257
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500258static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500259pit_setup(void)
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400260{
261 // timer0: binary count, 16bit count, mode 2
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500262 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400263 // maximum count of 0000H = 18.2Hz
264 outb(0x0, PORT_PIT_COUNTER0);
265 outb(0x0, PORT_PIT_COUNTER0);
266}
267
Kevin O'Connorf3587592009-02-15 13:02:56 -0500268static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500269init_rtc(void)
Kevin O'Connorf3587592009-02-15 13:02:56 -0500270{
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500271 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
Kevin O'Connorf3587592009-02-15 13:02:56 -0500272 u8 regB = inb_cmos(CMOS_STATUS_B);
273 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
274 inb_cmos(CMOS_STATUS_C);
275 inb_cmos(CMOS_STATUS_D);
276}
277
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400278static u32
279bcd2bin(u8 val)
280{
281 return (val & 0xf) + ((val >> 4) * 10);
282}
283
284void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500285timer_setup(void)
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400286{
Kevin O'Connor35192dd2008-06-08 19:18:33 -0400287 dprintf(3, "init timer\n");
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500288 calibrate_tsc();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400289 pit_setup();
290
Kevin O'Connorf3587592009-02-15 13:02:56 -0500291 init_rtc();
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500292 rtc_updating();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400293 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400294 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400295 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400296 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
297 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400298 SET_BDA(timer_counter, ticks);
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400299
Kevin O'Connorcc9e1bf2010-07-28 21:31:38 -0400300 enable_hwirq(0, FUNC16(entry_08));
301 enable_hwirq(8, FUNC16(entry_70));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400302}
303
Kevin O'Connor5be04902008-05-18 17:12:06 -0400304
305/****************************************************************
306 * Standard clock functions
307 ****************************************************************/
308
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400309#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
310
311// Calculate the timer value at 'count' number of full timer ticks in
312// the future.
313u32
314calc_future_timer_ticks(u32 count)
315{
316 return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
317}
Kevin O'Connorbb685912010-05-23 12:40:40 -0400318
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400319// Return the timer value that is 'msecs' time in the future.
320u32
321calc_future_timer(u32 msecs)
322{
Kevin O'Connorbb685912010-05-23 12:40:40 -0400323 if (!msecs)
324 return GET_BDA(timer_counter);
Kevin O'Connorabf31d32010-07-26 22:33:54 -0400325 u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400326 u32 ticks = DIV_ROUND_UP(kticks, 1000);
327 return calc_future_timer_ticks(ticks);
328}
Kevin O'Connorbb685912010-05-23 12:40:40 -0400329
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400330// Check if the given timer value has passed.
331int
332check_timer(u32 end)
333{
334 return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
335 < (TICKS_PER_DAY/2));
336}
337
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500338// get current clock count
339static void
340handle_1a00(struct bregs *regs)
341{
Kevin O'Connor68c51392010-03-13 22:23:44 -0500342 yield();
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500343 u32 ticks = GET_BDA(timer_counter);
344 regs->cx = ticks >> 16;
345 regs->dx = ticks;
346 regs->al = GET_BDA(timer_rollover);
347 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor6c781222008-03-09 12:19:23 -0400348 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500349}
350
351// Set Current Clock Count
352static void
353handle_1a01(struct bregs *regs)
354{
355 u32 ticks = (regs->cx << 16) | regs->dx;
356 SET_BDA(timer_counter, ticks);
357 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor15157a32008-12-13 11:10:37 -0500358 // XXX - should use set_code_success()?
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500359 regs->ah = 0;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400360 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500361}
362
363// Read CMOS Time
364static void
365handle_1a02(struct bregs *regs)
366{
367 if (rtc_updating()) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500368 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500369 return;
370 }
371
372 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
373 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
374 regs->ch = inb_cmos(CMOS_RTC_HOURS);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500375 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500376 regs->ah = 0;
377 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400378 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500379}
380
381// Set CMOS Time
382static void
383handle_1a03(struct bregs *regs)
384{
385 // Using a debugger, I notice the following masking/setting
386 // of bits in Status Register B, by setting Reg B to
387 // a few values and getting its value after INT 1A was called.
388 //
389 // try#1 try#2 try#3
390 // before 1111 1101 0111 1101 0000 0000
391 // after 0110 0010 0110 0010 0000 0010
392 //
393 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
394 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
395 if (rtc_updating()) {
396 init_rtc();
397 // fall through as if an update were not in progress
398 }
399 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
400 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
401 outb_cmos(regs->ch, CMOS_RTC_HOURS);
402 // Set Daylight Savings time enabled bit to requested value
Kevin O'Connorf3587592009-02-15 13:02:56 -0500403 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
404 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500405 outb_cmos(val8, CMOS_STATUS_B);
406 regs->ah = 0;
407 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400408 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500409}
410
411// Read CMOS Date
412static void
413handle_1a04(struct bregs *regs)
414{
415 regs->ah = 0;
416 if (rtc_updating()) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500417 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500418 return;
419 }
420 regs->cl = inb_cmos(CMOS_RTC_YEAR);
421 regs->dh = inb_cmos(CMOS_RTC_MONTH);
422 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500423 if (CONFIG_COREBOOT) {
424 if (regs->cl > 0x80)
425 regs->ch = 0x19;
426 else
427 regs->ch = 0x20;
428 } else {
429 regs->ch = inb_cmos(CMOS_CENTURY);
430 }
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500431 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400432 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500433}
434
435// Set CMOS Date
436static void
437handle_1a05(struct bregs *regs)
438{
439 // Using a debugger, I notice the following masking/setting
440 // of bits in Status Register B, by setting Reg B to
441 // a few values and getting its value after INT 1A was called.
442 //
443 // try#1 try#2 try#3 try#4
444 // before 1111 1101 0111 1101 0000 0010 0000 0000
445 // after 0110 1101 0111 1101 0000 0010 0000 0000
446 //
447 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
448 // My assumption: RegB = (RegB & 01111111b)
449 if (rtc_updating()) {
450 init_rtc();
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500451 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500452 return;
453 }
454 outb_cmos(regs->cl, CMOS_RTC_YEAR);
455 outb_cmos(regs->dh, CMOS_RTC_MONTH);
456 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500457 if (!CONFIG_COREBOOT)
458 outb_cmos(regs->ch, CMOS_CENTURY);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400459 // clear halt-clock bit
460 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500461 outb_cmos(val8, CMOS_STATUS_B);
462 regs->ah = 0;
463 regs->al = val8; // AL = val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400464 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500465}
466
467// Set Alarm Time in CMOS
468static void
469handle_1a06(struct bregs *regs)
470{
471 // Using a debugger, I notice the following masking/setting
472 // of bits in Status Register B, by setting Reg B to
473 // a few values and getting its value after INT 1A was called.
474 //
475 // try#1 try#2 try#3
476 // before 1101 1111 0101 1111 0000 0000
477 // after 0110 1111 0111 1111 0010 0000
478 //
479 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
480 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
481 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
482 regs->ax = 0;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500483 if (val8 & RTC_B_AIE) {
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500484 // Alarm interrupt enabled already
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500485 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500486 return;
487 }
488 if (rtc_updating()) {
489 init_rtc();
490 // fall through as if an update were not in progress
491 }
492 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
493 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
494 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500495 // enable Status Reg B alarm bit, clear halt clock bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400496 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
Kevin O'Connor6c781222008-03-09 12:19:23 -0400497 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500498}
499
500// Turn off Alarm
501static void
502handle_1a07(struct bregs *regs)
503{
504 // Using a debugger, I notice the following masking/setting
505 // of bits in Status Register B, by setting Reg B to
506 // a few values and getting its value after INT 1A was called.
507 //
508 // try#1 try#2 try#3 try#4
509 // before 1111 1101 0111 1101 0010 0000 0010 0010
510 // after 0100 0101 0101 0101 0000 0000 0000 0010
511 //
512 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
513 // My assumption: RegB = (RegB & 01010111b)
514 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
515 // clear clock-halt bit, disable alarm bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400516 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500517 regs->ah = 0;
518 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400519 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500520}
521
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500522// Unsupported
523static void
524handle_1aXX(struct bregs *regs)
525{
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500526 set_unimplemented(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500527}
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500528
529// INT 1Ah Time-of-day Service Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500530void VISIBLE16
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500531handle_1a(struct bregs *regs)
532{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400533 debug_enter(regs, DEBUG_HDL_1a);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500534 switch (regs->ah) {
535 case 0x00: handle_1a00(regs); break;
536 case 0x01: handle_1a01(regs); break;
537 case 0x02: handle_1a02(regs); break;
538 case 0x03: handle_1a03(regs); break;
539 case 0x04: handle_1a04(regs); break;
540 case 0x05: handle_1a05(regs); break;
541 case 0x06: handle_1a06(regs); break;
542 case 0x07: handle_1a07(regs); break;
543 case 0xb1: handle_1ab1(regs); break;
544 default: handle_1aXX(regs); break;
545 }
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500546}
547
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500548// INT 08h System Timer ISR Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500549void VISIBLE16
Kevin O'Connor1297e5d2012-06-02 20:30:58 -0400550handle_08(void)
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500551{
Kevin O'Connor1297e5d2012-06-02 20:30:58 -0400552 debug_isr(DEBUG_ISR_08);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500553
554 floppy_tick();
555
556 u32 counter = GET_BDA(timer_counter);
557 counter++;
558 // compare to one days worth of timer ticks at 18.2 hz
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400559 if (counter >= TICKS_PER_DAY) {
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500560 // there has been a midnight rollover at this point
561 counter = 0;
562 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
563 }
564
565 SET_BDA(timer_counter, counter);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500566
Kevin O'Connor0e885762010-05-01 22:14:40 -0400567 usb_check_event();
Kevin O'Connor114592f2009-09-28 21:32:08 -0400568
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500569 // chain to user timer tick INT #0x1c
Kevin O'Connorecdc6552012-05-28 14:25:15 -0400570 struct bregs br;
571 memset(&br, 0, sizeof(br));
572 br.flags = F_IF;
573 call16_int(0x1c, &br);
Kevin O'Connored128492008-03-11 11:14:59 -0400574
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400575 eoi_pic1();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500576}
577
Kevin O'Connor5be04902008-05-18 17:12:06 -0400578
579/****************************************************************
580 * Periodic timer
581 ****************************************************************/
582
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400583int RTCusers VARLOW;
584
Kevin O'Connorad901592009-12-13 11:25:25 -0500585void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500586useRTC(void)
Kevin O'Connorad901592009-12-13 11:25:25 -0500587{
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400588 int count = GET_LOW(RTCusers);
589 SET_LOW(RTCusers, count+1);
Kevin O'Connorad901592009-12-13 11:25:25 -0500590 if (count)
591 return;
592 // Turn on the Periodic Interrupt timer
593 u8 bRegister = inb_cmos(CMOS_STATUS_B);
594 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
595}
596
597void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500598releaseRTC(void)
Kevin O'Connorad901592009-12-13 11:25:25 -0500599{
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400600 int count = GET_LOW(RTCusers);
601 SET_LOW(RTCusers, count-1);
Kevin O'Connorad901592009-12-13 11:25:25 -0500602 if (count != 1)
603 return;
604 // Clear the Periodic Interrupt.
605 u8 bRegister = inb_cmos(CMOS_STATUS_B);
606 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
607}
608
Kevin O'Connor5be04902008-05-18 17:12:06 -0400609static int
Kevin O'Connor72743f12008-05-24 23:04:09 -0400610set_usertimer(u32 usecs, u16 seg, u16 offset)
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500611{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400612 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
613 return -1;
614
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500615 // Interval not already set.
616 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400617 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
Kevin O'Connor72743f12008-05-24 23:04:09 -0400618 SET_BDA(user_wait_timeout, usecs);
Kevin O'Connorad901592009-12-13 11:25:25 -0500619 useRTC();
Kevin O'Connor5be04902008-05-18 17:12:06 -0400620 return 0;
621}
622
623static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500624clear_usertimer(void)
Kevin O'Connor5be04902008-05-18 17:12:06 -0400625{
Kevin O'Connorad901592009-12-13 11:25:25 -0500626 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
627 return;
Kevin O'Connor5be04902008-05-18 17:12:06 -0400628 // Turn off status byte.
629 SET_BDA(rtc_wait_flag, 0);
Kevin O'Connorad901592009-12-13 11:25:25 -0500630 releaseRTC();
Kevin O'Connor5be04902008-05-18 17:12:06 -0400631}
632
Kevin O'Connor5be04902008-05-18 17:12:06 -0400633#define RET_ECLOCKINUSE 0x83
634
Kevin O'Connord21c0892008-11-26 17:02:43 -0500635// Wait for CX:DX microseconds
Kevin O'Connor5be04902008-05-18 17:12:06 -0400636void
637handle_1586(struct bregs *regs)
638{
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500639 // Use the rtc to wait for the specified time.
640 u8 statusflag = 0;
641 u32 count = (regs->cx << 16) | regs->dx;
642 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
643 if (ret) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500644 set_code_invalid(regs, RET_ECLOCKINUSE);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500645 return;
646 }
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500647 while (!statusflag)
Kevin O'Connor94c749c2012-05-28 11:44:02 -0400648 yield_toirq();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500649 set_success(regs);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400650}
651
652// Set Interval requested.
653static void
654handle_158300(struct bregs *regs)
655{
656 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
657 if (ret)
658 // Interval already set.
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500659 set_code_invalid(regs, RET_EUNSUPPORTED);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400660 else
661 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500662}
663
664// Clear interval requested
665static void
666handle_158301(struct bregs *regs)
667{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400668 clear_usertimer();
669 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500670}
671
672static void
673handle_1583XX(struct bregs *regs)
674{
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500675 set_code_unimplemented(regs, RET_EUNSUPPORTED);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500676 regs->al--;
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500677}
678
679void
680handle_1583(struct bregs *regs)
681{
682 switch (regs->al) {
683 case 0x00: handle_158300(regs); break;
684 case 0x01: handle_158301(regs); break;
685 default: handle_1583XX(regs); break;
686 }
687}
688
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400689#define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
690
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500691// int70h: IRQ8 - CMOS RTC
Kevin O'Connor19786762008-03-05 21:09:59 -0500692void VISIBLE16
Kevin O'Connor1297e5d2012-06-02 20:30:58 -0400693handle_70(void)
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500694{
Kevin O'Connor1297e5d2012-06-02 20:30:58 -0400695 debug_isr(DEBUG_ISR_70);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500696
697 // Check which modes are enabled and have occurred.
698 u8 registerB = inb_cmos(CMOS_STATUS_B);
699 u8 registerC = inb_cmos(CMOS_STATUS_C);
700
Kevin O'Connor5be04902008-05-18 17:12:06 -0400701 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500702 goto done;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500703 if (registerC & RTC_B_AIE) {
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500704 // Handle Alarm Interrupt.
Kevin O'Connorecdc6552012-05-28 14:25:15 -0400705 struct bregs br;
706 memset(&br, 0, sizeof(br));
707 br.flags = F_IF;
708 call16_int(0x4a, &br);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500709 }
Kevin O'Connorf3587592009-02-15 13:02:56 -0500710 if (!(registerC & RTC_B_PIE))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500711 goto done;
712
713 // Handle Periodic Interrupt.
714
Kevin O'Connorad901592009-12-13 11:25:25 -0500715 check_preempt();
716
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500717 if (!GET_BDA(rtc_wait_flag))
718 goto done;
719
720 // Wait Interval (Int 15, AH=83) active.
721 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400722 if (time < USEC_PER_RTC) {
Kevin O'Connor5be04902008-05-18 17:12:06 -0400723 // Done waiting - write to specified flag byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400724 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
725 u16 ptr_seg = segoff.seg;
726 u8 *ptr_far = (u8*)(segoff.offset+0);
727 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
728 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400729
730 clear_usertimer();
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500731 } else {
732 // Continue waiting.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400733 time -= USEC_PER_RTC;
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500734 SET_BDA(user_wait_timeout, time);
735 }
736
737done:
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400738 eoi_pic2();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500739}