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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
8#include "util.h" // dprintf
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -05009#include "pci.h" // pci_config_readl
Kevin O'Connor9521e262008-07-04 13:04:29 -040010#include "biosvar.h" // GET_EBDA
Kevin O'Connor2ed2f582008-11-08 15:53:36 -050011#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12#include "pci_regs.h" // PCI_COMMAND
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -040013#include "dev-i440fx.h"
Kevin O'Connor0525d292008-07-04 06:18:30 -040014
Kevin O'Connor0525d292008-07-04 06:18:30 -040015#define PCI_ROM_SLOT 6
16#define PCI_NUM_REGIONS 7
17
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090018static void pci_bios_init_device_in_bus(int bus);
19
Kevin O'Connor0525d292008-07-04 06:18:30 -040020static u32 pci_bios_io_addr;
21static u32 pci_bios_mem_addr;
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090022static u32 pci_bios_prefmem_addr;
Kevin O'Connor0525d292008-07-04 06:18:30 -040023/* host irqs corresponding to PCI irqs A-D */
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -040024const u8 pci_irqs[4] = {
Kevin O'Connor7061eb62009-01-04 21:48:22 -050025 10, 10, 11, 11
Kevin O'Connor7061eb62009-01-04 21:48:22 -050026};
Kevin O'Connor0525d292008-07-04 06:18:30 -040027
Isaku Yamahataa65821d2010-06-22 17:57:50 +090028static u32 pci_bar(u16 bdf, int region_num)
29{
30 if (region_num != PCI_ROM_SLOT) {
31 return PCI_BASE_ADDRESS_0 + region_num * 4;
32 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090033
34#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
35 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
36 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
37 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090038}
39
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050040static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
Kevin O'Connor0525d292008-07-04 06:18:30 -040041{
Isaku Yamahataeebe9492010-08-30 11:32:01 +090042 u32 ofs;
Kevin O'Connor0525d292008-07-04 06:18:30 -040043
Isaku Yamahataa65821d2010-06-22 17:57:50 +090044 ofs = pci_bar(bdf, region_num);
Kevin O'Connor0525d292008-07-04 06:18:30 -040045
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050046 pci_config_writel(bdf, ofs, addr);
Kevin O'Connor0525d292008-07-04 06:18:30 -040047 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
Kevin O'Connor0525d292008-07-04 06:18:30 -040048}
49
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +090050/*
51 * return value
52 * 0: 32bit BAR
53 * non 0: 64bit BAR
54 */
55static int pci_bios_allocate_region(u16 bdf, int region_num)
Isaku Yamahatab9e47212010-06-22 17:57:47 +090056{
57 u32 *paddr;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090058 u32 ofs = pci_bar(bdf, region_num);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090059
60 u32 old = pci_config_readl(bdf, ofs);
61 u32 mask;
62 if (region_num == PCI_ROM_SLOT) {
63 mask = PCI_ROM_ADDRESS_MASK;
64 pci_config_writel(bdf, ofs, mask);
65 } else {
66 if (old & PCI_BASE_ADDRESS_SPACE_IO)
67 mask = PCI_BASE_ADDRESS_IO_MASK;
68 else
69 mask = PCI_BASE_ADDRESS_MEM_MASK;
70 pci_config_writel(bdf, ofs, ~0);
71 }
72 u32 val = pci_config_readl(bdf, ofs);
73 pci_config_writel(bdf, ofs, old);
74
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090075 u32 size = (~(val & mask)) + 1;
Isaku Yamahatab9e47212010-06-22 17:57:47 +090076 if (val != 0) {
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090077 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
Isaku Yamahatab9e47212010-06-22 17:57:47 +090078 paddr = &pci_bios_io_addr;
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090079 if (ALIGN(*paddr, size) + size >= 64 * 1024) {
80 dprintf(1,
81 "io region of (bdf 0x%x bar %d) can't be mapped.\n",
82 bdf, region_num);
83 size = 0;
84 }
85 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
86 /* keep behaviour on bus = 0 */
87 pci_bdf_to_bus(bdf) != 0 &&
88 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
89 pci_bios_prefmem_addr != 0) {
90 paddr = &pci_bios_prefmem_addr;
91 if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
92 dprintf(1,
93 "prefmem region of (bdf 0x%x bar %d) can't be mapped. "
94 "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n",
95 bdf, region_num, BUILD_PCIPREFMEM_SIZE);
96 size = 0;
97 }
98 } else {
Isaku Yamahatab9e47212010-06-22 17:57:47 +090099 paddr = &pci_bios_mem_addr;
Isaku Yamahata0a8eada2010-06-22 17:57:49 +0900100 if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
101 dprintf(1,
102 "mem region of (bdf 0x%x bar %d) can't be mapped. "
103 "increase BUILD_PCIMEM_SIZE and recompile. size %x\n",
104 bdf, region_num, BUILD_PCIMEM_SIZE);
105 size = 0;
106 }
107 }
108 if (size > 0) {
109 *paddr = ALIGN(*paddr, size);
110 pci_set_io_region_addr(bdf, region_num, *paddr);
111 *paddr += size;
112 }
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900113 }
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +0900114
115 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
116 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
Isaku Yamahata1d5c3332010-07-26 14:02:45 +0900117 if (is_64bit && size > 0) {
118 pci_config_writel(bdf, ofs + 4, 0);
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +0900119 }
120 return is_64bit;
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900121}
122
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400123void pci_bios_allocate_regions(u16 bdf, void *arg)
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900124{
125 int i;
126 for (i = 0; i < PCI_NUM_REGIONS; i++) {
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +0900127 int is_64bit = pci_bios_allocate_region(bdf, i);
128 if (is_64bit){
129 i++;
130 }
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900131 }
132}
133
Kevin O'Connor0525d292008-07-04 06:18:30 -0400134/* return the global irq number corresponding to a given device irq
135 pin. We could also use the bus number to have a more precise
136 mapping. */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500137static int pci_slot_get_pirq(u16 bdf, int irq_num)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400138{
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500139 int slot_addend = pci_bdf_to_dev(bdf) - 1;
Kevin O'Connor0525d292008-07-04 06:18:30 -0400140 return (irq_num + slot_addend) & 3;
141}
142
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400143static const struct pci_device_id pci_isa_bridge_tbl[] = {
144 /* PIIX3/PIIX4 PCI to ISA bridge */
145 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
146 piix_isa_bridge_init),
147 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
148 piix_isa_bridge_init),
Kevin O'Connor0525d292008-07-04 06:18:30 -0400149
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400150 PCI_DEVICE_END
151};
Kevin O'Connor0525d292008-07-04 06:18:30 -0400152
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900153#define PCI_IO_ALIGN 4096
154#define PCI_IO_SHIFT 8
155#define PCI_MEMORY_ALIGN (1UL << 20)
156#define PCI_MEMORY_SHIFT 16
157#define PCI_PREF_MEMORY_ALIGN (1UL << 20)
158#define PCI_PREF_MEMORY_SHIFT 16
159
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400160static void pci_bios_init_device_bridge(u16 bdf, void *arg)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900161{
162 pci_bios_allocate_region(bdf, 0);
163 pci_bios_allocate_region(bdf, 1);
164 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
165
166 u32 io_old = pci_bios_io_addr;
167 u32 mem_old = pci_bios_mem_addr;
168 u32 prefmem_old = pci_bios_prefmem_addr;
169
170 /* IO BASE is assumed to be 16 bit */
171 pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN);
172 pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN);
173 pci_bios_prefmem_addr =
174 ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN);
175
176 u32 io_base = pci_bios_io_addr;
177 u32 mem_base = pci_bios_mem_addr;
178 u32 prefmem_base = pci_bios_prefmem_addr;
179
180 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
181 if (secbus > 0) {
182 pci_bios_init_device_in_bus(secbus);
183 }
184
185 pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN);
186 pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN);
187 pci_bios_prefmem_addr =
188 ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN);
189
190 u32 io_end = pci_bios_io_addr;
191 if (io_end == io_base) {
192 pci_bios_io_addr = io_old;
193 io_base = 0xffff;
194 io_end = 1;
195 }
196 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
197 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
198 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
199 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
200
201 u32 mem_end = pci_bios_mem_addr;
202 if (mem_end == mem_base) {
203 pci_bios_mem_addr = mem_old;
204 mem_base = 0xffffffff;
205 mem_end = 1;
206 }
207 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
208 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
209
210 u32 prefmem_end = pci_bios_prefmem_addr;
211 if (prefmem_end == prefmem_base) {
212 pci_bios_prefmem_addr = prefmem_old;
213 prefmem_base = 0xffffffff;
214 prefmem_end = 1;
215 }
216 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
217 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
218 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
219 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
220 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
221 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
222
223 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
224 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
225 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
226
227 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
228 cmd &= ~PCI_COMMAND_IO;
229 if (io_end > io_base) {
230 cmd |= PCI_COMMAND_IO;
231 }
232 cmd &= ~PCI_COMMAND_MEMORY;
233 if (mem_end > mem_base || prefmem_end > prefmem_base) {
234 cmd |= PCI_COMMAND_MEMORY;
235 }
236 cmd |= PCI_COMMAND_MASTER;
237 pci_config_writew(bdf, PCI_COMMAND, cmd);
238
239 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
240}
241
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400242static void storage_ide_init(u16 bdf, void *arg)
243{
244 /* IDE: we map it as in ISA mode */
245 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
246 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
247 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
248 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
249}
250
251static void pic_ibm_init(u16 bdf, void *arg)
252{
253 /* PIC, IBM, MPIC & MPIC2 */
254 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
255}
256
257static void apple_macio_init(u16 bdf, void *arg)
258{
259 /* macio bridge */
260 pci_set_io_region_addr(bdf, 0, 0x80800000);
261}
262
263static const struct pci_device_id pci_class_tbl[] = {
264 /* STORAGE IDE */
265 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
266 PCI_CLASS_STORAGE_IDE, piix_ide_init),
267 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
268 PCI_CLASS_STORAGE_IDE, piix_ide_init),
269 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
270 storage_ide_init),
271
272 /* PIC, IBM, MIPC & MPIC2 */
273 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
274 pic_ibm_init),
275 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
276 pic_ibm_init),
277
278 /* 0xff00 */
279 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
280 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
281
282 /* PCI bridge */
283 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
284 pci_bios_init_device_bridge),
285
286 /* default */
287 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
288
289 PCI_DEVICE_END,
290};
291
292static const struct pci_device_id pci_device_tbl[] = {
293 /* PIIX4 Power Management device (for ACPI) */
294 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
295 piix4_pm_init),
296
297 PCI_DEVICE_END,
298};
299
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500300static void pci_bios_init_device(u16 bdf)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400301{
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900302 int pin, pic_irq, vendor_id, device_id;
Kevin O'Connor0525d292008-07-04 06:18:30 -0400303
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500304 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
305 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
306 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
307 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400308 pci_init_device(pci_class_tbl, bdf, NULL);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400309
Kevin O'Connorb82a1e42009-10-12 10:34:51 -0400310 /* enable memory mappings */
311 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
312
Kevin O'Connor0525d292008-07-04 06:18:30 -0400313 /* map the interrupt */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500314 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400315 if (pin != 0) {
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500316 pin = pci_slot_get_pirq(bdf, pin - 1);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400317 pic_irq = pci_irqs[pin];
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500318 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400319 }
320
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400321 pci_init_device(pci_device_tbl, bdf, NULL);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400322}
323
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900324static void pci_bios_init_device_in_bus(int bus)
325{
326 int bdf, max;
327 foreachpci_in_bus(bdf, max, bus) {
328 pci_bios_init_device(bdf);
329 }
330}
331
Isaku Yamahataf4416662010-06-22 17:57:52 +0900332static void
333pci_bios_init_bus_rec(int bus, u8 *pci_bus)
334{
335 int bdf, max;
336 u16 class;
337
338 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
339
340 /* prevent accidental access to unintended devices */
341 foreachpci_in_bus(bdf, max, bus) {
342 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
343 if (class == PCI_CLASS_BRIDGE_PCI) {
344 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
345 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
346 }
347 }
348
349 foreachpci_in_bus(bdf, max, bus) {
350 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
351 if (class != PCI_CLASS_BRIDGE_PCI) {
352 continue;
353 }
354 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
355
356 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
357 if (pribus != bus) {
358 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
359 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
360 } else {
361 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
362 }
363
364 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
365 (*pci_bus)++;
366 if (*pci_bus != secbus) {
367 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
368 secbus, *pci_bus);
369 secbus = *pci_bus;
370 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
371 } else {
372 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
373 }
374
375 /* set to max for access to all subordinate buses.
376 later set it to accurate value */
377 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
378 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
379
380 pci_bios_init_bus_rec(secbus, pci_bus);
381
382 if (subbus != *pci_bus) {
383 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
384 subbus, *pci_bus);
385 subbus = *pci_bus;
386 } else {
387 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
388 }
389 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
390 }
391}
392
393static void
394pci_bios_init_bus(void)
395{
396 u8 pci_bus = 0;
397 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
398}
399
Kevin O'Connor0525d292008-07-04 06:18:30 -0400400void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400401pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400402{
403 if (CONFIG_COREBOOT)
404 // Already done by coreboot.
405 return;
406
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400407 dprintf(3, "pci setup\n");
408
Kevin O'Connor0525d292008-07-04 06:18:30 -0400409 pci_bios_io_addr = 0xc000;
Kevin O'Connor2d3f0f52010-01-28 20:33:20 -0500410 pci_bios_mem_addr = BUILD_PCIMEM_START;
Isaku Yamahata0a8eada2010-06-22 17:57:49 +0900411 pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START;
Kevin O'Connor0525d292008-07-04 06:18:30 -0400412
Isaku Yamahataf4416662010-06-22 17:57:52 +0900413 pci_bios_init_bus();
414
Kevin O'Connore6338322008-11-29 20:31:49 -0500415 int bdf, max;
Kevin O'Connor4132e022008-12-04 19:39:10 -0500416 foreachpci(bdf, max) {
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400417 pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
Kevin O'Connore6338322008-11-29 20:31:49 -0500418 }
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900419 pci_bios_init_device_in_bus(0 /* host bus */);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400420}