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Kevin O'Connorda4a6482008-06-08 13:48:06 -04001// Support for enabling/disabling BIOS ram shadowing.
2//
Kevin O'Connore7739302009-07-26 19:16:09 -04003// Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connorda4a6482008-06-08 13:48:06 -04004// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connorda4a6482008-06-08 13:48:06 -04007
8#include "util.h" // memcpy
9#include "pci.h" // pci_config_writeb
Kevin O'Connor9521e262008-07-04 13:04:29 -040010#include "config.h" // CONFIG_*
Kevin O'Connor2ed2f582008-11-08 15:53:36 -050011#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
Isaku Yamahata08328e72010-07-20 16:50:45 +090012#include "dev-i440fx.h"
Kevin O'Connorda4a6482008-06-08 13:48:06 -040013
Kevin O'Connorda4a6482008-06-08 13:48:06 -040014// Test if 'addr' is in the range from 'start'..'start+size'
15#define IN_RANGE(addr, start, size) ({ \
16 u32 __addr = (addr); \
17 u32 __start = (start); \
18 u32 __size = (size); \
19 (__addr - __start < __size); \
20 })
21
Kevin O'Connor35284962009-07-24 21:49:26 -040022// On the emulators, the bios at 0xf0000 is also at 0xffff0000
23#define BIOS_SRC_ADDR 0xffff0000
24
Kevin O'Connorda4a6482008-06-08 13:48:06 -040025// Enable shadowing and copy bios.
26static void
Isaku Yamahata08328e72010-07-20 16:50:45 +090027__make_bios_writable_intel(u16 bdf, u32 pam0)
Kevin O'Connorda4a6482008-06-08 13:48:06 -040028{
Kevin O'Connore7739302009-07-26 19:16:09 -040029 // Make ram from 0xc0000-0xf0000 writable
30 int clear = 0;
31 int i;
32 for (i=0; i<6; i++) {
Isaku Yamahata08328e72010-07-20 16:50:45 +090033 u32 pam = pam0 + 1 + i;
34 int reg = pci_config_readb(bdf, pam);
Anthony Liguori034ce4b2009-12-18 12:16:01 +010035 if ((reg & 0x11) != 0x11) {
36 // Need to copy optionroms to work around qemu implementation
37 void *mem = (void*)(BUILD_ROM_START + i * 32*1024);
38 memcpy((void*)BUILD_BIOS_TMP_ADDR, mem, 32*1024);
Isaku Yamahata08328e72010-07-20 16:50:45 +090039 pci_config_writeb(bdf, pam, 0x33);
Anthony Liguori034ce4b2009-12-18 12:16:01 +010040 memcpy(mem, (void*)BUILD_BIOS_TMP_ADDR, 32*1024);
41 clear = 1;
Kevin O'Connore7739302009-07-26 19:16:09 -040042 } else {
Isaku Yamahata08328e72010-07-20 16:50:45 +090043 pci_config_writeb(bdf, pam, 0x33);
Kevin O'Connore7739302009-07-26 19:16:09 -040044 }
45 }
46 if (clear)
47 memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
48
Kevin O'Connor5b8f8092009-09-20 19:47:45 -040049 // Make ram from 0xf0000-0x100000 writable
Isaku Yamahata08328e72010-07-20 16:50:45 +090050 int reg = pci_config_readb(bdf, pam0);
51 pci_config_writeb(bdf, pam0, 0x30);
Kevin O'Connor5b8f8092009-09-20 19:47:45 -040052 if (reg & 0x10)
53 // Ram already present.
54 return;
55
56 // Copy bios.
57 memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
58}
59
Isaku Yamahata08328e72010-07-20 16:50:45 +090060void
61make_bios_writable_intel(u16 bdf, u32 pam0)
62{
63 int reg = pci_config_readb(bdf, pam0);
64 if (!(reg & 0x10)) {
65 // QEMU doesn't fully implement the piix shadow capabilities -
66 // if ram isn't backing the bios segment when shadowing is
67 // disabled, the code itself wont be in memory. So, run the
68 // code from the high-memory flash location.
69 u32 pos = (u32)__make_bios_writable_intel - BUILD_BIOS_ADDR +
70 BIOS_SRC_ADDR;
71 void (*func)(u16 bdf, u32 pam0) = (void*)pos;
72 func(bdf, pam0);
73 return;
74 }
75 // Ram already present - just enable writes
76 __make_bios_writable_intel(bdf, pam0);
77}
78
79void
80make_bios_readonly_intel(u16 bdf, u32 pam0)
81{
82 // Flush any pending writes before locking memory.
83 wbinvd();
84
85 // Write protect roms from 0xc0000-0xf0000
86 int i;
87 for (i=0; i<6; i++) {
88 u32 mem = BUILD_ROM_START + i * 32*1024;
89 u32 pam = pam0 + 1 + i;
90 if (RomEnd <= mem + 16*1024) {
91 if (RomEnd > mem)
92 pci_config_writeb(bdf, pam, 0x31);
93 break;
94 }
95 pci_config_writeb(bdf, pam, 0x11);
96 }
97
98 // Write protect 0xf0000-0x100000
99 pci_config_writeb(bdf, pam0, 0x10);
100}
101
102static const struct pci_device_id dram_controller_make_writable_tbl[] = {
103 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
104 i440fx_bios_make_writable),
105 PCI_DEVICE_END
106};
107
Kevin O'Connor5b8f8092009-09-20 19:47:45 -0400108// Make the 0xc0000-0x100000 area read/writable.
109void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500110make_bios_writable(void)
Kevin O'Connor5b8f8092009-09-20 19:47:45 -0400111{
112 if (CONFIG_COREBOOT)
113 return;
114
115 dprintf(3, "enabling shadow ram\n");
116
Isaku Yamahata08328e72010-07-20 16:50:45 +0900117 // at this point, staticlly alloacted variable can't written.
118 // so stack should be used.
119
Kevin O'Connor5b8f8092009-09-20 19:47:45 -0400120 // Locate chip controlling ram shadowing.
Isaku Yamahata08328e72010-07-20 16:50:45 +0900121 int bdf = pci_find_init_device(dram_controller_make_writable_tbl, NULL);
Kevin O'Connor5b8f8092009-09-20 19:47:45 -0400122 if (bdf < 0) {
123 dprintf(1, "Unable to unlock ram - bridge not found\n");
Kevin O'Connor35284962009-07-24 21:49:26 -0400124 }
Kevin O'Connorda4a6482008-06-08 13:48:06 -0400125}
126
Isaku Yamahata08328e72010-07-20 16:50:45 +0900127static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
128 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
129 i440fx_bios_make_readonly),
130 PCI_DEVICE_END
131};
132
Kevin O'Connorda4a6482008-06-08 13:48:06 -0400133// Make the BIOS code segment area (0xf0000) read-only.
134void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500135make_bios_readonly(void)
Kevin O'Connorda4a6482008-06-08 13:48:06 -0400136{
137 if (CONFIG_COREBOOT)
138 return;
139
140 dprintf(3, "locking shadow ram\n");
Isaku Yamahata08328e72010-07-20 16:50:45 +0900141 int bdf = pci_find_init_device(dram_controller_make_readonly_tbl, NULL);
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500142 if (bdf < 0) {
Kevin O'Connorda4a6482008-06-08 13:48:06 -0400143 dprintf(1, "Unable to lock ram - bridge not found\n");
Kevin O'Connorda4a6482008-06-08 13:48:06 -0400144 }
Kevin O'Connorda4a6482008-06-08 13:48:06 -0400145}