blob: 18dfafa00d8327dc77dc3d0a690f8dbe5b7c0123 [file] [log] [blame]
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +01001/*
2 * Bochs/QEMU ACPI DSDT ASL definition
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
9 *
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19/*
20 * Copyright (c) 2010 Isaku Yamahata
21 * yamahata at valinux co jp
22 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
23 */
24
25DefinitionBlock (
26 "q35-acpi-dsdt.aml",// Output Filename
27 "DSDT", // Signature
28 0x01, // DSDT Compliance Revision
29 "BXPC", // OEMID
30 "BXDSDT", // TABLE ID
31 0x2 // OEM Revision
32 )
33{
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010034
Gerd Hoffmannbeaedaa2012-11-28 10:17:39 +010035#include "acpi-dsdt-dbug.dsl"
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010036
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050037 Scope(\_SB) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010038 OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
39 OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050040 Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010041 PCIB, 8,
42 }
43 }
44
45 /* Zero => PIC mode, One => APIC Mode */
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050046 Name(\PICF, Zero)
47 Method(\_PIC, 1, NotSerialized) {
48 Store(Arg0, \PICF)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010049 }
50
51 /* PCI Bus definition */
52 Scope(\_SB) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010053 Device(PCI0) {
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050054 Name(_HID, EisaId("PNP0A08"))
55 Name(_CID, EisaId("PNP0A03"))
56 Name(_ADR, 0x00)
57 Name(_UID, 1)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010058
59 // _OSC: based on sample of ACPI3.0b spec
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050060 Name(SUPP, 0) // PCI _OSC Support Field value
61 Name(CTRL, 0) // PCI _OSC Control Field value
62 Method(_OSC, 4) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010063 // Create DWORD-addressable fields from the Capabilities Buffer
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050064 CreateDWordField(Arg3, 0, CDW1)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010065
66 // Check for proper UUID
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050067 If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010068 // Create DWORD-addressable fields from the Capabilities Buffer
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050069 CreateDWordField(Arg3, 4, CDW2)
70 CreateDWordField(Arg3, 8, CDW3)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010071
72 // Save Capabilities DWORD2 & 3
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050073 Store(CDW2, SUPP)
74 Store(CDW3, CTRL)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010075
76 // Always allow native PME, AER (no dependencies)
77 // Never allow SHPC (no SHPC controller in this system)
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050078 And(CTRL, 0x1D, CTRL)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010079
80#if 0 // For now, nothing to do
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050081 If (Not(And(CDW1, 1))) { // Query flag clear?
82 // Disable GPEs for features granted native control.
83 If (And(CTRL, 0x01)) { // Hot plug control granted?
84 Store(0, HPCE) // clear the hot plug SCI enable bit
85 Store(1, HPCS) // clear the hot plug SCI status bit
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010086 }
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050087 If (And(CTRL, 0x04)) { // PME control granted?
88 Store(0, PMCE) // clear the PME SCI enable bit
89 Store(1, PMCS) // clear the PME SCI status bit
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010090 }
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050091 If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010092 // Set status to not restore PCI Express cap structure
93 // upon resume from S3
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050094 Store(1, S3CR)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010095 }
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010096 }
97#endif
Kevin O'Connore9e7ab42012-12-02 01:09:17 -050098 If (LNotEqual(Arg1, One)) {
99 // Unknown revision
100 Or(CDW1, 0x08, CDW1)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100101 }
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500102 If (LNotEqual(CDW3, CTRL)) {
103 // Capabilities bits were masked
104 Or(CDW1, 0x10, CDW1)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100105 }
106 // Update DWORD3 in the buffer
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500107 Store(CTRL, CDW3)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100108 } Else {
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500109 Or(CDW1, 4, CDW1) // Unrecognized UUID
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100110 }
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500111 Return (Arg3)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100112 }
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100113 }
114 }
115
Gerd Hoffmannaa3defc2012-11-28 10:17:43 +0100116#include "acpi-dsdt-pci-crs.dsl"
Gerd Hoffmann7464aea2012-11-28 10:17:41 +0100117#include "acpi-dsdt-hpet.dsl"
118
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100119 Scope(\_SB.PCI0) {
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500120 Device(VGA) {
121 Name(_ADR, 0x00010000)
122 Method(_S1D, 0, NotSerialized) {
123 Return (0x00)
124 }
125 Method(_S2D, 0, NotSerialized) {
126 Return (0x00)
127 }
128 Method(_S3D, 0, NotSerialized) {
129 Return (0x00)
130 }
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100131 }
132
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100133 /* PCI D31:f0 LPC ISA bridge */
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500134 Device(ISA) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100135 /* PCI D31:f0 */
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500136 Name(_ADR, 0x001f0000)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100137
138 /* ICH9 PCI to ISA irq remapping */
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500139 OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
140 Field(PIRQ, ByteAcc, NoLock, Preserve) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100141 PRQA, 8,
142 PRQB, 8,
143 PRQC, 8,
144 PRQD, 8,
145
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500146 Offset(0x08),
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100147 PRQE, 8,
148 PRQF, 8,
149 PRQG, 8,
150 PRQH, 8
151 }
152
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500153 OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
154 Field(LPCD, AnyAcc, NoLock, Preserve) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100155 COMA, 3,
156 , 1,
157 COMB, 3,
158
159 Offset(0x01),
160 LPTD, 2,
161 , 2,
162 FDCD, 2
163 }
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500164 OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
165 Field(LPCE, AnyAcc, NoLock, Preserve) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100166 CAEN, 1,
167 CBEN, 1,
168 LPEN, 1,
169 FDEN, 1
170 }
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100171 }
172 }
173
Gerd Hoffmannf051a762012-11-28 10:17:48 +0100174#include "acpi-dsdt-isa.dsl"
175
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100176 /* PCI IRQs */
177 Scope(\_SB) {
Kevin O'Connordabe1932012-12-02 01:30:27 -0500178 Scope(PCI0) {
179#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
180 Package() { nr##ffff, 0, lnk0, 0 }, \
181 Package() { nr##ffff, 1, lnk1, 0 }, \
182 Package() { nr##ffff, 2, lnk2, 0 }, \
183 Package() { nr##ffff, 3, lnk3, 0 }
184
185#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
186#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
187#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
188#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
189
190#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
191#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
192#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
193#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
194
195#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
196 Package() { nr##ffff, 0, gsi0, 0 }, \
197 Package() { nr##ffff, 1, gsi1, 0 }, \
198 Package() { nr##ffff, 2, gsi2, 0 }, \
199 Package() { nr##ffff, 3, gsi3, 0 }
200
201#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
202#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
203#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
204#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
205
206#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
207#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
208#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
209#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
210
211 Name(PRTP, package() {
212 prt_slot_lnkE(0x0000),
213 prt_slot_lnkF(0x0001),
214 prt_slot_lnkG(0x0002),
215 prt_slot_lnkH(0x0003),
216 prt_slot_lnkE(0x0004),
217 prt_slot_lnkF(0x0005),
218 prt_slot_lnkG(0x0006),
219 prt_slot_lnkH(0x0007),
220 prt_slot_lnkE(0x0008),
221 prt_slot_lnkF(0x0009),
222 prt_slot_lnkG(0x000a),
223 prt_slot_lnkH(0x000b),
224 prt_slot_lnkE(0x000c),
225 prt_slot_lnkF(0x000d),
226 prt_slot_lnkG(0x000e),
227 prt_slot_lnkH(0x000f),
228 prt_slot_lnkE(0x0010),
229 prt_slot_lnkF(0x0011),
230 prt_slot_lnkG(0x0012),
231 prt_slot_lnkH(0x0013),
232 prt_slot_lnkE(0x0014),
233 prt_slot_lnkF(0x0015),
234 prt_slot_lnkG(0x0016),
235 prt_slot_lnkH(0x0017),
236 prt_slot_lnkE(0x0018),
237
238 /* INTA -> PIRQA for slot 25 - 31
239 see the default value of D<N>IR */
240 prt_slot_lnkA(0x0019),
241 prt_slot_lnkA(0x001a),
242 prt_slot_lnkA(0x001b),
243 prt_slot_lnkA(0x001c),
244 prt_slot_lnkA(0x001d),
245
246 /* PCIe->PCI bridge. use PIRQ[E-H] */
247 prt_slot_lnkE(0x001e),
248
249 prt_slot_lnkA(0x001f)
250 })
251
252 Name(PRTA, package() {
253 prt_slot_gsiE(0x0000),
254 prt_slot_gsiF(0x0001),
255 prt_slot_gsiG(0x0002),
256 prt_slot_gsiH(0x0003),
257 prt_slot_gsiE(0x0004),
258 prt_slot_gsiF(0x0005),
259 prt_slot_gsiG(0x0006),
260 prt_slot_gsiH(0x0007),
261 prt_slot_gsiE(0x0008),
262 prt_slot_gsiF(0x0009),
263 prt_slot_gsiG(0x000a),
264 prt_slot_gsiH(0x000b),
265 prt_slot_gsiE(0x000c),
266 prt_slot_gsiF(0x000d),
267 prt_slot_gsiG(0x000e),
268 prt_slot_gsiH(0x000f),
269 prt_slot_gsiE(0x0010),
270 prt_slot_gsiF(0x0011),
271 prt_slot_gsiG(0x0012),
272 prt_slot_gsiH(0x0013),
273 prt_slot_gsiE(0x0014),
274 prt_slot_gsiF(0x0015),
275 prt_slot_gsiG(0x0016),
276 prt_slot_gsiH(0x0017),
277 prt_slot_gsiE(0x0018),
278
279 /* INTA -> PIRQA for slot 25 - 31, but 30
280 see the default value of D<N>IR */
281 prt_slot_gsiA(0x0019),
282 prt_slot_gsiA(0x001a),
283 prt_slot_gsiA(0x001b),
284 prt_slot_gsiA(0x001c),
285 prt_slot_gsiA(0x001d),
286
287 /* PCIe->PCI bridge. use PIRQ[E-H] */
288 prt_slot_gsiE(0x001e),
289
290 prt_slot_gsiA(0x001f)
291 })
292
293 Method(_PRT, 0, NotSerialized) {
294 /* PCI IRQ routing table, example from ACPI 2.0a specification,
295 section 6.2.8.1 */
296 /* Note: we provide the same info as the PCI routing
297 table of the Bochs BIOS */
298 If (LEqual(\PICF, Zero)) {
299 Return (PRTP)
300 } Else {
301 Return (PRTA)
302 }
303 }
304 }
305
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500306#define define_link(link, uid, reg) \
307 Device(link) { \
308 Name(_HID, EISAID("PNP0C0F")) \
309 Name(_UID, uid) \
310 Name(_PRS, ResourceTemplate() { \
311 Interrupt(, Level, ActiveHigh, Shared) { \
312 5, 10, 11 \
313 } \
314 }) \
315 Method(_STA, 0, NotSerialized) { \
316 Store(0x0B, Local0) \
317 If (And(0x80, reg, Local1)) { \
318 Store(0x09, Local0) \
319 } \
320 Return (Local0) \
321 } \
322 Method(_DIS, 0, NotSerialized) { \
323 Or(reg, 0x80, reg) \
324 } \
325 Method(_CRS, 0, NotSerialized) { \
326 Name(PRR0, ResourceTemplate() { \
327 Interrupt(, Level, ActiveHigh, Shared) { \
328 1 \
329 } \
330 }) \
331 CreateDWordField(PRR0, 0x05, TMP) \
332 And(reg, 0x0F, Local0) \
333 Store(Local0, TMP) \
334 Return (PRR0) \
335 } \
336 Method(_SRS, 1, NotSerialized) { \
337 CreateDWordField(Arg0, 0x05, TMP) \
338 Store(TMP, reg) \
339 } \
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100340 }
341
Gerd Hoffmannf051a762012-11-28 10:17:48 +0100342 define_link(LNKA, 0, \_SB.PCI0.ISA.PRQA)
343 define_link(LNKB, 1, \_SB.PCI0.ISA.PRQB)
344 define_link(LNKC, 2, \_SB.PCI0.ISA.PRQC)
345 define_link(LNKD, 3, \_SB.PCI0.ISA.PRQD)
346 define_link(LNKE, 4, \_SB.PCI0.ISA.PRQE)
347 define_link(LNKF, 5, \_SB.PCI0.ISA.PRQF)
348 define_link(LNKG, 6, \_SB.PCI0.ISA.PRQG)
349 define_link(LNKH, 7, \_SB.PCI0.ISA.PRQH)
Jan Kiszka2114f502012-11-28 10:17:37 +0100350
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500351#define define_gsi_link(link, uid, gsi) \
352 Device(link) { \
353 Name(_HID, EISAID("PNP0C0F")) \
354 Name(_UID, uid) \
355 Name(_PRS, ResourceTemplate() { \
356 Interrupt(, Level, ActiveHigh, Shared) { \
357 gsi \
358 } \
359 }) \
360 Method(_CRS, 0, NotSerialized) { \
361 Return (ResourceTemplate() { \
362 Interrupt(, Level, ActiveHigh, Shared) { \
363 gsi \
364 } \
365 }) \
366 } \
367 Method(_SRS, 1, NotSerialized) { \
368 } \
369 }
Jan Kiszka2114f502012-11-28 10:17:37 +0100370
371 define_gsi_link(GSIA, 0, 0x10)
372 define_gsi_link(GSIB, 0, 0x11)
373 define_gsi_link(GSIC, 0, 0x12)
374 define_gsi_link(GSID, 0, 0x13)
375 define_gsi_link(GSIE, 0, 0x14)
376 define_gsi_link(GSIF, 0, 0x15)
377 define_gsi_link(GSIG, 0, 0x16)
378 define_gsi_link(GSIH, 0, 0x17)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100379 }
380
Gerd Hoffmannf50a55c2012-11-28 10:17:45 +0100381#include "acpi-dsdt-cpu-hotplug.dsl"
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100382
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500383 Scope(\_GPE) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100384 Name(_HID, "ACPI0006")
385
386 Method(_L00) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100387 }
388 Method(_L01) {
Kevin O'Connore9e7ab42012-12-02 01:09:17 -0500389 // CPU hotplug event
390 \_SB.PRSC()
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100391 }
392 Method(_L02) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100393 }
394 Method(_L03) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100395 }
396 Method(_L04) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100397 }
398 Method(_L05) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100399 }
400 Method(_L06) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100401 }
402 Method(_L07) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100403 }
404 Method(_L08) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100405 }
406 Method(_L09) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100407 }
408 Method(_L0A) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100409 }
410 Method(_L0B) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100411 }
412 Method(_L0C) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100413 }
414 Method(_L0D) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100415 }
416 Method(_L0E) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100417 }
418 Method(_L0F) {
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100419 }
420 }
421}