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Kevin O'Connorc892b132009-08-11 21:59:37 -04001#ifndef __ATA_H
2#define __ATA_H
3
4#include "types.h" // u8
5#include "config.h" // CONFIG_MAX_ATA_INTERFACES
Kevin O'Connor8f469b92010-02-28 01:28:11 -05006#include "disk.h" // struct drive_s
Kevin O'Connorc892b132009-08-11 21:59:37 -04007
8struct ata_channel_s {
Kevin O'Connor4ccb2312009-12-05 11:25:09 -05009 u16 iobase1;
10 u16 iobase2;
Kevin O'Connor14021f22009-12-26 23:21:38 -050011 u16 iomaster;
Kevin O'Connor4ccb2312009-12-05 11:25:09 -050012 u8 irq;
Kevin O'Connor8f469b92010-02-28 01:28:11 -050013 u8 chanid;
Kevin O'Connor4ccb2312009-12-05 11:25:09 -050014 int pci_bdf;
Kevin O'Connor95b2e0c2011-07-09 14:42:11 -040015 struct pci_device *pci_tmp;
Kevin O'Connorc892b132009-08-11 21:59:37 -040016};
17
Kevin O'Connor8f469b92010-02-28 01:28:11 -050018struct atadrive_s {
19 struct drive_s drive;
20 struct ata_channel_s *chan_gf;
21 u8 slave;
22};
23
Kevin O'Connorc892b132009-08-11 21:59:37 -040024// ata.c
Gerd Hoffmann54fa8ec2010-11-29 09:42:12 +010025char *ata_extract_model(char *model, u32 size, u16 *buffer);
26int ata_extract_version(u16 *buffer);
Kevin O'Connorc892b132009-08-11 21:59:37 -040027int cdrom_read(struct disk_op_s *op);
Kevin O'Connor7d700252010-02-15 11:56:07 -050028int atapi_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize);
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050029void ata_setup(void);
Kevin O'Connorc892b132009-08-11 21:59:37 -040030int process_ata_op(struct disk_op_s *op);
Kevin O'Connorc892b132009-08-11 21:59:37 -040031
Kevin O'Connor1fcf1442008-03-11 19:42:41 -040032// Global defines -- ATA register and register bits.
33// command block & control block regs
34#define ATA_CB_DATA 0 // data reg in/out pio_base_addr1+0
35#define ATA_CB_ERR 1 // error in pio_base_addr1+1
36#define ATA_CB_FR 1 // feature reg out pio_base_addr1+1
37#define ATA_CB_SC 2 // sector count in/out pio_base_addr1+2
38#define ATA_CB_SN 3 // sector number in/out pio_base_addr1+3
39#define ATA_CB_CL 4 // cylinder low in/out pio_base_addr1+4
40#define ATA_CB_CH 5 // cylinder high in/out pio_base_addr1+5
41#define ATA_CB_DH 6 // device head in/out pio_base_addr1+6
42#define ATA_CB_STAT 7 // primary status in pio_base_addr1+7
43#define ATA_CB_CMD 7 // command out pio_base_addr1+7
Kevin O'Connor525219b2009-12-05 13:36:18 -050044
45#define ATA_CB_ASTAT 2 // alternate status in pio_base_addr2+2
46#define ATA_CB_DC 2 // device control out pio_base_addr2+2
47#define ATA_CB_DA 3 // device address in pio_base_addr2+3
Kevin O'Connor1fcf1442008-03-11 19:42:41 -040048
49#define ATA_CB_ER_ICRC 0x80 // ATA Ultra DMA bad CRC
50#define ATA_CB_ER_BBK 0x80 // ATA bad block
51#define ATA_CB_ER_UNC 0x40 // ATA uncorrected error
52#define ATA_CB_ER_MC 0x20 // ATA media change
53#define ATA_CB_ER_IDNF 0x10 // ATA id not found
54#define ATA_CB_ER_MCR 0x08 // ATA media change request
55#define ATA_CB_ER_ABRT 0x04 // ATA command aborted
56#define ATA_CB_ER_NTK0 0x02 // ATA track 0 not found
57#define ATA_CB_ER_NDAM 0x01 // ATA address mark not found
58
59#define ATA_CB_ER_P_SNSKEY 0xf0 // ATAPI sense key (mask)
60#define ATA_CB_ER_P_MCR 0x08 // ATAPI Media Change Request
61#define ATA_CB_ER_P_ABRT 0x04 // ATAPI command abort
62#define ATA_CB_ER_P_EOM 0x02 // ATAPI End of Media
63#define ATA_CB_ER_P_ILI 0x01 // ATAPI Illegal Length Indication
64
65// ATAPI Interrupt Reason bits in the Sector Count reg (CB_SC)
66#define ATA_CB_SC_P_TAG 0xf8 // ATAPI tag (mask)
67#define ATA_CB_SC_P_REL 0x04 // ATAPI release
68#define ATA_CB_SC_P_IO 0x02 // ATAPI I/O
69#define ATA_CB_SC_P_CD 0x01 // ATAPI C/D
70
71// bits 7-4 of the device/head (CB_DH) reg
72#define ATA_CB_DH_DEV0 0xa0 // select device 0
73#define ATA_CB_DH_DEV1 0xb0 // select device 1
74#define ATA_CB_DH_LBA 0x40 // use LBA
75
76// status reg (CB_STAT and CB_ASTAT) bits
77#define ATA_CB_STAT_BSY 0x80 // busy
78#define ATA_CB_STAT_RDY 0x40 // ready
79#define ATA_CB_STAT_DF 0x20 // device fault
80#define ATA_CB_STAT_WFT 0x20 // write fault (old name)
81#define ATA_CB_STAT_SKC 0x10 // seek complete
82#define ATA_CB_STAT_SERV 0x10 // service
83#define ATA_CB_STAT_DRQ 0x08 // data request
84#define ATA_CB_STAT_CORR 0x04 // corrected
85#define ATA_CB_STAT_IDX 0x02 // index
86#define ATA_CB_STAT_ERR 0x01 // error (ATA)
87#define ATA_CB_STAT_CHK 0x01 // check (ATAPI)
88
89// device control reg (CB_DC) bits
90#define ATA_CB_DC_HD15 0x08 // bit should always be set to one
91#define ATA_CB_DC_SRST 0x04 // soft reset
92#define ATA_CB_DC_NIEN 0x02 // disable interrupts
93
94// Most mandtory and optional ATA commands (from ATA-3),
Kevin O'Connor1fcf1442008-03-11 19:42:41 -040095#define ATA_CMD_NOP 0x00
Kevin O'Connor42157c82010-02-15 02:21:10 -050096#define ATA_CMD_CFA_REQUEST_EXT_ERR_CODE 0x03
97#define ATA_CMD_DEVICE_RESET 0x08
98#define ATA_CMD_RECALIBRATE 0x10
Kevin O'Connor1fcf1442008-03-11 19:42:41 -040099#define ATA_CMD_READ_SECTORS 0x20
Kevin O'Connord43e1782009-12-13 12:02:55 -0500100#define ATA_CMD_READ_SECTORS_EXT 0x24
Kevin O'Connor42157c82010-02-15 02:21:10 -0500101#define ATA_CMD_READ_DMA_EXT 0x25
102#define ATA_CMD_READ_DMA_QUEUED_EXT 0x26
103#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27
104#define ATA_CMD_READ_MULTIPLE_EXT 0x29
105#define ATA_CMD_READ_LOG_EXT 0x2F
Kevin O'Connor1fcf1442008-03-11 19:42:41 -0400106#define ATA_CMD_WRITE_SECTORS 0x30
Kevin O'Connord43e1782009-12-13 12:02:55 -0500107#define ATA_CMD_WRITE_SECTORS_EXT 0x34
Kevin O'Connor42157c82010-02-15 02:21:10 -0500108#define ATA_CMD_WRITE_DMA_EXT 0x35
109#define ATA_CMD_WRITE_DMA_QUEUED_EXT 0x36
110#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37
111#define ATA_CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38
112#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39
Kevin O'Connor1fcf1442008-03-11 19:42:41 -0400113#define ATA_CMD_WRITE_VERIFY 0x3C
Kevin O'Connor42157c82010-02-15 02:21:10 -0500114#define ATA_CMD_WRITE_LOG_EXT 0x3F
115#define ATA_CMD_READ_VERIFY_SECTORS 0x40
116#define ATA_CMD_READ_VERIFY_SECTORS_EXT 0x42
117#define ATA_CMD_FORMAT_TRACK 0x50
118#define ATA_CMD_SEEK 0x70
119#define ATA_CMD_CFA_TRANSLATE_SECTOR 0x87
120#define ATA_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90
121#define ATA_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91
122#define ATA_CMD_STANDBY_IMMEDIATE2 0x94
123#define ATA_CMD_IDLE_IMMEDIATE2 0x95
124#define ATA_CMD_STANDBY2 0x96
125#define ATA_CMD_IDLE2 0x97
126#define ATA_CMD_CHECK_POWER_MODE2 0x98
127#define ATA_CMD_SLEEP2 0x99
128#define ATA_CMD_PACKET 0xA0
129#define ATA_CMD_IDENTIFY_PACKET_DEVICE 0xA1
130#define ATA_CMD_CFA_ERASE_SECTORS 0xC0
131#define ATA_CMD_READ_MULTIPLE 0xC4
132#define ATA_CMD_WRITE_MULTIPLE 0xC5
133#define ATA_CMD_SET_MULTIPLE_MODE 0xC6
134#define ATA_CMD_READ_DMA_QUEUED 0xC7
135#define ATA_CMD_READ_DMA 0xC8
136#define ATA_CMD_WRITE_DMA 0xCA
137#define ATA_CMD_WRITE_DMA_QUEUED 0xCC
138#define ATA_CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD
139#define ATA_CMD_STANDBY_IMMEDIATE 0xE0
140#define ATA_CMD_IDLE_IMMEDIATE 0xE1
141#define ATA_CMD_STANDBY 0xE2
142#define ATA_CMD_IDLE 0xE3
143#define ATA_CMD_READ_BUFFER 0xE4
144#define ATA_CMD_CHECK_POWER_MODE 0xE5
145#define ATA_CMD_SLEEP 0xE6
146#define ATA_CMD_FLUSH_CACHE 0xE7
147#define ATA_CMD_WRITE_BUFFER 0xE8
148#define ATA_CMD_IDENTIFY_DEVICE 0xEC
149#define ATA_CMD_SET_FEATURES 0xEF
150#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xF8
151#define ATA_CMD_SET_MAX 0xF9
152
Kevin O'Connorc892b132009-08-11 21:59:37 -0400153#endif // ata.h