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Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit code to handle system clocks.
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2002 MandrakeSoft S.A.
5//
6// This file may be distributed under the terms of the GNU GPLv3 license.
7
8#include "biosvar.h" // struct bregs
9#include "util.h" // debug_enter
10#include "disk.h" // floppy_tick
Kevin O'Connor4b60c002008-02-25 22:29:55 -050011#include "cmos.h" // inb_cmos
12
Kevin O'Connorc65a3802008-03-02 13:58:23 -050013#define DEBUGF1(fmt, args...) bprintf(0, fmt , ##args)
14#define DEBUGF(fmt, args...)
15
Kevin O'Connor4b60c002008-02-25 22:29:55 -050016static void
17init_rtc()
18{
19 outb_cmos(0x26, CMOS_STATUS_A);
20 outb_cmos(0x02, CMOS_STATUS_B);
21 inb_cmos(CMOS_STATUS_C);
22 inb_cmos(CMOS_STATUS_D);
23}
24
25static u8
26rtc_updating()
27{
28 // This function checks to see if the update-in-progress bit
29 // is set in CMOS Status Register A. If not, it returns 0.
30 // If it is set, it tries to wait until there is a transition
31 // to 0, and will return 0 if such a transition occurs. A 1
32 // is returned only after timing out. The maximum period
33 // that this bit should be set is constrained to 244useconds.
34 // The count I use below guarantees coverage or more than
35 // this time, with any reasonable IPS setting.
36
37 u16 count = 25000;
38 while (--count != 0) {
39 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
40 return 0;
41 }
42 return 1; // update-in-progress never transitioned to 0
43}
44
45// get current clock count
46static void
47handle_1a00(struct bregs *regs)
48{
49 u32 ticks = GET_BDA(timer_counter);
50 regs->cx = ticks >> 16;
51 regs->dx = ticks;
52 regs->al = GET_BDA(timer_rollover);
53 SET_BDA(timer_rollover, 0); // reset flag
54 set_cf(regs, 0);
55}
56
57// Set Current Clock Count
58static void
59handle_1a01(struct bregs *regs)
60{
61 u32 ticks = (regs->cx << 16) | regs->dx;
62 SET_BDA(timer_counter, ticks);
63 SET_BDA(timer_rollover, 0); // reset flag
64 regs->ah = 0;
65 set_cf(regs, 0);
66}
67
68// Read CMOS Time
69static void
70handle_1a02(struct bregs *regs)
71{
72 if (rtc_updating()) {
73 set_cf(regs, 1);
74 return;
75 }
76
77 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
78 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
79 regs->ch = inb_cmos(CMOS_RTC_HOURS);
80 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
81 regs->ah = 0;
82 regs->al = regs->ch;
83 set_cf(regs, 0);
84}
85
86// Set CMOS Time
87static void
88handle_1a03(struct bregs *regs)
89{
90 // Using a debugger, I notice the following masking/setting
91 // of bits in Status Register B, by setting Reg B to
92 // a few values and getting its value after INT 1A was called.
93 //
94 // try#1 try#2 try#3
95 // before 1111 1101 0111 1101 0000 0000
96 // after 0110 0010 0110 0010 0000 0010
97 //
98 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
99 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
100 if (rtc_updating()) {
101 init_rtc();
102 // fall through as if an update were not in progress
103 }
104 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
105 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
106 outb_cmos(regs->ch, CMOS_RTC_HOURS);
107 // Set Daylight Savings time enabled bit to requested value
108 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
109 outb_cmos(val8, CMOS_STATUS_B);
110 regs->ah = 0;
111 regs->al = val8; // val last written to Reg B
112 set_cf(regs, 0);
113}
114
115// Read CMOS Date
116static void
117handle_1a04(struct bregs *regs)
118{
119 regs->ah = 0;
120 if (rtc_updating()) {
121 set_cf(regs, 1);
122 return;
123 }
124 regs->cl = inb_cmos(CMOS_RTC_YEAR);
125 regs->dh = inb_cmos(CMOS_RTC_MONTH);
126 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
127 regs->ch = inb_cmos(CMOS_CENTURY);
128 regs->al = regs->ch;
129 set_cf(regs, 0);
130}
131
132// Set CMOS Date
133static void
134handle_1a05(struct bregs *regs)
135{
136 // Using a debugger, I notice the following masking/setting
137 // of bits in Status Register B, by setting Reg B to
138 // a few values and getting its value after INT 1A was called.
139 //
140 // try#1 try#2 try#3 try#4
141 // before 1111 1101 0111 1101 0000 0010 0000 0000
142 // after 0110 1101 0111 1101 0000 0010 0000 0000
143 //
144 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
145 // My assumption: RegB = (RegB & 01111111b)
146 if (rtc_updating()) {
147 init_rtc();
148 set_cf(regs, 1);
149 return;
150 }
151 outb_cmos(regs->cl, CMOS_RTC_YEAR);
152 outb_cmos(regs->dh, CMOS_RTC_MONTH);
153 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
154 outb_cmos(regs->ch, CMOS_CENTURY);
155 u8 val8 = inb_cmos(CMOS_STATUS_B) & 0x7f; // clear halt-clock bit
156 outb_cmos(val8, CMOS_STATUS_B);
157 regs->ah = 0;
158 regs->al = val8; // AL = val last written to Reg B
159 set_cf(regs, 0);
160}
161
162// Set Alarm Time in CMOS
163static void
164handle_1a06(struct bregs *regs)
165{
166 // Using a debugger, I notice the following masking/setting
167 // of bits in Status Register B, by setting Reg B to
168 // a few values and getting its value after INT 1A was called.
169 //
170 // try#1 try#2 try#3
171 // before 1101 1111 0101 1111 0000 0000
172 // after 0110 1111 0111 1111 0010 0000
173 //
174 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
175 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
176 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
177 regs->ax = 0;
178 if (val8 & 0x20) {
179 // Alarm interrupt enabled already
180 set_cf(regs, 1);
181 return;
182 }
183 if (rtc_updating()) {
184 init_rtc();
185 // fall through as if an update were not in progress
186 }
187 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
188 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
189 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
190 outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
191 // enable Status Reg B alarm bit, clear halt clock bit
192 outb_cmos((val8 & 0x7f) | 0x20, CMOS_STATUS_B);
193 set_cf(regs, 0);
194}
195
196// Turn off Alarm
197static void
198handle_1a07(struct bregs *regs)
199{
200 // Using a debugger, I notice the following masking/setting
201 // of bits in Status Register B, by setting Reg B to
202 // a few values and getting its value after INT 1A was called.
203 //
204 // try#1 try#2 try#3 try#4
205 // before 1111 1101 0111 1101 0010 0000 0010 0010
206 // after 0100 0101 0101 0101 0000 0000 0000 0010
207 //
208 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
209 // My assumption: RegB = (RegB & 01010111b)
210 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
211 // clear clock-halt bit, disable alarm bit
212 outb_cmos(val8 & 0x57, CMOS_STATUS_B); // disable alarm bit
213 regs->ah = 0;
214 regs->al = val8; // val last written to Reg B
215 set_cf(regs, 0);
216}
217
218static void
219handle_1ab1(struct bregs *regs)
220{
221 // XXX - pcibios stuff
222 set_cf(regs, 1);
223}
224
225// Unsupported
226static void
227handle_1aXX(struct bregs *regs)
228{
229 set_cf(regs, 1);
230}
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500231
232// INT 1Ah Time-of-day Service Entry Point
233void VISIBLE
234handle_1a(struct bregs *regs)
235{
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500236 //debug_enter(regs);
237 switch (regs->ah) {
238 case 0x00: handle_1a00(regs); break;
239 case 0x01: handle_1a01(regs); break;
240 case 0x02: handle_1a02(regs); break;
241 case 0x03: handle_1a03(regs); break;
242 case 0x04: handle_1a04(regs); break;
243 case 0x05: handle_1a05(regs); break;
244 case 0x06: handle_1a06(regs); break;
245 case 0x07: handle_1a07(regs); break;
246 case 0xb1: handle_1ab1(regs); break;
247 default: handle_1aXX(regs); break;
248 }
249 debug_exit(regs);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500250}
251
252// User Timer Tick
253void VISIBLE
254handle_1c(struct bregs *regs)
255{
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500256 //debug_enter(regs);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500257}
258
259// INT 08h System Timer ISR Entry Point
260void VISIBLE
261handle_08(struct bregs *regs)
262{
Kevin O'Connorc65a3802008-03-02 13:58:23 -0500263// debug_isr(regs);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500264
265 floppy_tick();
266
267 u32 counter = GET_BDA(timer_counter);
268 counter++;
269 // compare to one days worth of timer ticks at 18.2 hz
270 if (counter >= 0x001800B0) {
271 // there has been a midnight rollover at this point
272 counter = 0;
273 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
274 }
275
276 SET_BDA(timer_counter, counter);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500277
278 // chain to user timer tick INT #0x1c
279 struct bregs br;
280 memset(&br, 0, sizeof(br));
281 call16_int(0x1c, &br);
282
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500283 eoi_master_pic();
284}
285
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500286// Set Interval requested.
287static void
288handle_158300(struct bregs *regs)
289{
290 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) {
291 // Interval already set.
292 DEBUGF("int15: Func 83h, failed, already waiting.\n" );
293 handle_ret(regs, RET_EUNSUPPORTED);
294 }
295 // Interval not already set.
296 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
297 u32 v = (regs->es << 16) | regs->bx;
298 SET_BDA(ptr_user_wait_complete_flag, v);
299 v = (regs->dx << 16) | regs->cx;
300 SET_BDA(user_wait_timeout, v);
301
302 // Unmask IRQ8 so INT70 will get through.
303 u8 irqDisable = inb(PORT_PIC2_DATA);
304 outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
305 // Turn on the Periodic Interrupt timer
306 u8 bRegister = inb_cmos(CMOS_STATUS_B);
307 outb_cmos(CMOS_STATUS_B, bRegister | CSB_EN_ALARM_IRQ);
308
309 set_cf(regs, 0); // XXX - no set ah?
310}
311
312// Clear interval requested
313static void
314handle_158301(struct bregs *regs)
315{
316 SET_BDA(rtc_wait_flag, 0); // Clear status byte
317 // Turn off the Periodic Interrupt timer
318 u8 bRegister = inb_cmos(CMOS_STATUS_B);
319 outb_cmos(CMOS_STATUS_B, bRegister & ~CSB_EN_ALARM_IRQ);
320 set_cf(regs, 0); // XXX - no set ah?
321}
322
323static void
324handle_1583XX(struct bregs *regs)
325{
326 regs->al--;
327 handle_ret(regs, RET_EUNSUPPORTED);
328}
329
330void
331handle_1583(struct bregs *regs)
332{
333 switch (regs->al) {
334 case 0x00: handle_158300(regs); break;
335 case 0x01: handle_158301(regs); break;
336 default: handle_1583XX(regs); break;
337 }
338}
339
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500340// int70h: IRQ8 - CMOS RTC
341void VISIBLE
342handle_70(struct bregs *regs)
343{
Kevin O'Connorc65a3802008-03-02 13:58:23 -0500344 debug_isr(regs);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500345
346 // Check which modes are enabled and have occurred.
347 u8 registerB = inb_cmos(CMOS_STATUS_B);
348 u8 registerC = inb_cmos(CMOS_STATUS_C);
349
350 if (!(registerB & 0x60))
351 goto done;
352 if (registerC & 0x20) {
353 // Handle Alarm Interrupt.
354 struct bregs br;
355 memset(&br, 0, sizeof(br));
356 call16_int(0x4a, &br);
357 }
358 if (!(registerC & 0x40))
359 goto done;
360
361 // Handle Periodic Interrupt.
362
363 if (!GET_BDA(rtc_wait_flag))
364 goto done;
365
366 // Wait Interval (Int 15, AH=83) active.
367 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
368 if (time < 0x3D1) {
369 // Done waiting.
370 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
371 u16 segment = segoff >> 16;
372 u16 offset = segoff & 0xffff;
373 // Turn off status byte.
374 SET_BDA(rtc_wait_flag, 0);
375 // Clear the Periodic Interrupt.
376 outb_cmos(registerB & 0x37, CMOS_STATUS_B);
377 // Write to specified flag byte.
378 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
379 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
380 } else {
381 // Continue waiting.
382 time -= 0x3D1;
383 SET_BDA(user_wait_timeout, time);
384 }
385
386done:
387 eoi_both_pics();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500388}