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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
8#include "util.h" // dprintf
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -05009#include "pci.h" // pci_config_readl
Kevin O'Connor9521e262008-07-04 13:04:29 -040010#include "biosvar.h" // GET_EBDA
Kevin O'Connor2ed2f582008-11-08 15:53:36 -050011#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12#include "pci_regs.h" // PCI_COMMAND
Ian Campbell74c78782011-06-01 11:00:29 +010013#include "xen.h" // usingXen
Kevin O'Connor0525d292008-07-04 06:18:30 -040014
Kevin O'Connor0525d292008-07-04 06:18:30 -040015#define PCI_ROM_SLOT 6
16#define PCI_NUM_REGIONS 7
17
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090018static void pci_bios_init_device_in_bus(int bus);
19
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090020static struct pci_region pci_bios_io_region;
21static struct pci_region pci_bios_mem_region;
22static struct pci_region pci_bios_prefmem_region;
23
Kevin O'Connor0525d292008-07-04 06:18:30 -040024/* host irqs corresponding to PCI irqs A-D */
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -040025const u8 pci_irqs[4] = {
Kevin O'Connor7061eb62009-01-04 21:48:22 -050026 10, 10, 11, 11
Kevin O'Connor7061eb62009-01-04 21:48:22 -050027};
Kevin O'Connor0525d292008-07-04 06:18:30 -040028
Isaku Yamahataa65821d2010-06-22 17:57:50 +090029static u32 pci_bar(u16 bdf, int region_num)
30{
31 if (region_num != PCI_ROM_SLOT) {
32 return PCI_BASE_ADDRESS_0 + region_num * 4;
33 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090034
35#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
36 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
37 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
38 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090039}
40
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050041static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
Kevin O'Connor0525d292008-07-04 06:18:30 -040042{
Isaku Yamahataeebe9492010-08-30 11:32:01 +090043 u32 ofs;
Kevin O'Connor0525d292008-07-04 06:18:30 -040044
Isaku Yamahataa65821d2010-06-22 17:57:50 +090045 ofs = pci_bar(bdf, region_num);
Kevin O'Connor0525d292008-07-04 06:18:30 -040046
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050047 pci_config_writel(bdf, ofs, addr);
Kevin O'Connor0525d292008-07-04 06:18:30 -040048 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
Kevin O'Connor0525d292008-07-04 06:18:30 -040049}
50
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +090051/*
52 * return value
53 * 0: 32bit BAR
54 * non 0: 64bit BAR
55 */
56static int pci_bios_allocate_region(u16 bdf, int region_num)
Isaku Yamahatab9e47212010-06-22 17:57:47 +090057{
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090058 struct pci_region *r;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090059 u32 ofs = pci_bar(bdf, region_num);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090060
61 u32 old = pci_config_readl(bdf, ofs);
62 u32 mask;
63 if (region_num == PCI_ROM_SLOT) {
64 mask = PCI_ROM_ADDRESS_MASK;
65 pci_config_writel(bdf, ofs, mask);
66 } else {
67 if (old & PCI_BASE_ADDRESS_SPACE_IO)
68 mask = PCI_BASE_ADDRESS_IO_MASK;
69 else
70 mask = PCI_BASE_ADDRESS_MEM_MASK;
71 pci_config_writel(bdf, ofs, ~0);
72 }
73 u32 val = pci_config_readl(bdf, ofs);
74 pci_config_writel(bdf, ofs, old);
75
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090076 u32 size = (~(val & mask)) + 1;
Isaku Yamahatab9e47212010-06-22 17:57:47 +090077 if (val != 0) {
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090078 const char *type;
79 const char *msg;
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090080 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090081 r = &pci_bios_io_region;
82 type = "io";
83 msg = "";
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090084 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090085 /* keep behaviour on bus = 0 */
86 pci_bdf_to_bus(bdf) != 0 &&
87 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
88 pci_region_addr(&pci_bios_prefmem_region) != 0) {
89 r = &pci_bios_prefmem_region;
90 type = "prefmem";
91 msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090092 } else {
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090093 r = &pci_bios_mem_region;
94 type = "mem";
95 msg = "increase BUILD_PCIMEM_SIZE and recompile.";
Isaku Yamahata0a8eada2010-06-22 17:57:49 +090096 }
Isaku Yamahatae2623fc2010-10-28 15:54:36 +090097 u32 addr = pci_region_alloc(r, size);
98 if (addr > 0) {
99 pci_set_io_region_addr(bdf, region_num, addr);
100 } else {
101 size = 0;
102 dprintf(1,
103 "%s region of (bdf 0x%x bar %d) can't be mapped. "
104 "%s size %x\n",
105 type, bdf, region_num, msg, pci_region_size(r));
Isaku Yamahata0a8eada2010-06-22 17:57:49 +0900106 }
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900107 }
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +0900108
109 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
110 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
Isaku Yamahata1d5c3332010-07-26 14:02:45 +0900111 if (is_64bit && size > 0) {
112 pci_config_writel(bdf, ofs + 4, 0);
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +0900113 }
114 return is_64bit;
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900115}
116
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400117static void pci_bios_allocate_regions(u16 bdf, void *arg)
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900118{
119 int i;
120 for (i = 0; i < PCI_NUM_REGIONS; i++) {
Isaku Yamahatadfd94fa2010-06-22 17:57:48 +0900121 int is_64bit = pci_bios_allocate_region(bdf, i);
122 if (is_64bit){
123 i++;
124 }
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900125 }
126}
127
Kevin O'Connor0525d292008-07-04 06:18:30 -0400128/* return the global irq number corresponding to a given device irq
129 pin. We could also use the bus number to have a more precise
130 mapping. */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500131static int pci_slot_get_pirq(u16 bdf, int irq_num)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400132{
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500133 int slot_addend = pci_bdf_to_dev(bdf) - 1;
Kevin O'Connor0525d292008-07-04 06:18:30 -0400134 return (irq_num + slot_addend) & 3;
135}
136
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400137/* PIIX3/PIIX4 PCI to ISA bridge */
138static void piix_isa_bridge_init(u16 bdf, void *arg)
139{
140 int i, irq;
141 u8 elcr[2];
142
143 elcr[0] = 0x00;
144 elcr[1] = 0x00;
145 for (i = 0; i < 4; i++) {
146 irq = pci_irqs[i];
147 /* set to trigger level */
148 elcr[irq >> 3] |= (1 << (irq & 7));
149 /* activate irq remapping in PIIX */
150 pci_config_writeb(bdf, 0x60 + i, irq);
151 }
152 outb(elcr[0], 0x4d0);
153 outb(elcr[1], 0x4d1);
154 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
155}
156
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400157static const struct pci_device_id pci_isa_bridge_tbl[] = {
158 /* PIIX3/PIIX4 PCI to ISA bridge */
159 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
160 piix_isa_bridge_init),
161 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
162 piix_isa_bridge_init),
Kevin O'Connor0525d292008-07-04 06:18:30 -0400163
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400164 PCI_DEVICE_END
165};
Kevin O'Connor0525d292008-07-04 06:18:30 -0400166
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900167#define PCI_IO_ALIGN 4096
168#define PCI_IO_SHIFT 8
169#define PCI_MEMORY_ALIGN (1UL << 20)
170#define PCI_MEMORY_SHIFT 16
171#define PCI_PREF_MEMORY_ALIGN (1UL << 20)
172#define PCI_PREF_MEMORY_SHIFT 16
173
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400174static void pci_bios_init_device_bridge(u16 bdf, void *arg)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900175{
176 pci_bios_allocate_region(bdf, 0);
177 pci_bios_allocate_region(bdf, 1);
178 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
179
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900180 u32 io_old = pci_region_addr(&pci_bios_io_region);
181 u32 mem_old = pci_region_addr(&pci_bios_mem_region);
182 u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900183
184 /* IO BASE is assumed to be 16 bit */
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900185 if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
186 pci_region_disable(&pci_bios_io_region);
187 }
188 if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
189 pci_region_disable(&pci_bios_mem_region);
190 }
191 if (pci_region_align(&pci_bios_prefmem_region,
192 PCI_PREF_MEMORY_ALIGN) == 0) {
193 pci_region_disable(&pci_bios_prefmem_region);
194 }
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900195
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900196 u32 io_base = pci_region_addr(&pci_bios_io_region);
197 u32 mem_base = pci_region_addr(&pci_bios_mem_region);
198 u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900199
200 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
201 if (secbus > 0) {
202 pci_bios_init_device_in_bus(secbus);
203 }
204
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900205 u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
206 if (io_end == 0) {
207 pci_region_revert(&pci_bios_io_region, io_old);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900208 io_base = 0xffff;
209 io_end = 1;
210 }
211 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
212 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
213 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
214 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
215
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900216 u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
217 if (mem_end == 0) {
218 pci_region_revert(&pci_bios_mem_region, mem_old);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900219 mem_base = 0xffffffff;
220 mem_end = 1;
221 }
222 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
223 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
224
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900225 u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
226 PCI_PREF_MEMORY_ALIGN);
227 if (prefmem_end == 0) {
228 pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900229 prefmem_base = 0xffffffff;
230 prefmem_end = 1;
231 }
232 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
233 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
234 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
235 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
236 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
237 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
238
239 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
240 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
241 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
242
243 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
244 cmd &= ~PCI_COMMAND_IO;
245 if (io_end > io_base) {
246 cmd |= PCI_COMMAND_IO;
247 }
248 cmd &= ~PCI_COMMAND_MEMORY;
249 if (mem_end > mem_base || prefmem_end > prefmem_base) {
250 cmd |= PCI_COMMAND_MEMORY;
251 }
252 cmd |= PCI_COMMAND_MASTER;
253 pci_config_writew(bdf, PCI_COMMAND, cmd);
254
255 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
256}
257
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400258static void storage_ide_init(u16 bdf, void *arg)
259{
260 /* IDE: we map it as in ISA mode */
261 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
262 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
263 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
264 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
265}
266
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400267/* PIIX3/PIIX4 IDE */
268static void piix_ide_init(u16 bdf, void *arg)
269{
270 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
271 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
272 pci_bios_allocate_regions(bdf, NULL);
273}
274
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400275static void pic_ibm_init(u16 bdf, void *arg)
276{
277 /* PIC, IBM, MPIC & MPIC2 */
278 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
279}
280
281static void apple_macio_init(u16 bdf, void *arg)
282{
283 /* macio bridge */
284 pci_set_io_region_addr(bdf, 0, 0x80800000);
285}
286
287static const struct pci_device_id pci_class_tbl[] = {
288 /* STORAGE IDE */
289 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
290 PCI_CLASS_STORAGE_IDE, piix_ide_init),
291 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
292 PCI_CLASS_STORAGE_IDE, piix_ide_init),
293 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
294 storage_ide_init),
295
296 /* PIC, IBM, MIPC & MPIC2 */
297 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
298 pic_ibm_init),
299 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
300 pic_ibm_init),
301
302 /* 0xff00 */
303 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
304 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
305
306 /* PCI bridge */
307 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
308 pci_bios_init_device_bridge),
309
310 /* default */
311 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
312
313 PCI_DEVICE_END,
314};
315
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400316/* PIIX4 Power Management device (for ACPI) */
317static void piix4_pm_init(u16 bdf, void *arg)
318{
319 // acpi sci is hardwired to 9
320 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
321
322 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
323 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
324 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
325 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
326}
327
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400328static const struct pci_device_id pci_device_tbl[] = {
329 /* PIIX4 Power Management device (for ACPI) */
330 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
331 piix4_pm_init),
332
333 PCI_DEVICE_END,
334};
335
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500336static void pci_bios_init_device(u16 bdf)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400337{
Isaku Yamahatab9e47212010-06-22 17:57:47 +0900338 int pin, pic_irq, vendor_id, device_id;
Kevin O'Connor0525d292008-07-04 06:18:30 -0400339
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500340 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
341 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
342 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
343 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400344 pci_init_device(pci_class_tbl, bdf, NULL);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400345
Kevin O'Connorb82a1e42009-10-12 10:34:51 -0400346 /* enable memory mappings */
347 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
348
Kevin O'Connor0525d292008-07-04 06:18:30 -0400349 /* map the interrupt */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500350 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400351 if (pin != 0) {
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500352 pin = pci_slot_get_pirq(bdf, pin - 1);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400353 pic_irq = pci_irqs[pin];
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500354 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400355 }
356
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400357 pci_init_device(pci_device_tbl, bdf, NULL);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400358}
359
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900360static void pci_bios_init_device_in_bus(int bus)
361{
362 int bdf, max;
Kevin O'Connorbaac6b62011-06-19 10:46:28 -0400363 foreachbdf_in_bus(bdf, max, bus) {
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900364 pci_bios_init_device(bdf);
365 }
366}
367
Isaku Yamahataf4416662010-06-22 17:57:52 +0900368static void
369pci_bios_init_bus_rec(int bus, u8 *pci_bus)
370{
371 int bdf, max;
372 u16 class;
373
374 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
375
376 /* prevent accidental access to unintended devices */
Kevin O'Connorbaac6b62011-06-19 10:46:28 -0400377 foreachbdf_in_bus(bdf, max, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900378 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
379 if (class == PCI_CLASS_BRIDGE_PCI) {
380 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
381 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
382 }
383 }
384
Kevin O'Connorbaac6b62011-06-19 10:46:28 -0400385 foreachbdf_in_bus(bdf, max, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900386 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
387 if (class != PCI_CLASS_BRIDGE_PCI) {
388 continue;
389 }
390 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
391
392 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
393 if (pribus != bus) {
394 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
395 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
396 } else {
397 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
398 }
399
400 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
401 (*pci_bus)++;
402 if (*pci_bus != secbus) {
403 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
404 secbus, *pci_bus);
405 secbus = *pci_bus;
406 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
407 } else {
408 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
409 }
410
411 /* set to max for access to all subordinate buses.
412 later set it to accurate value */
413 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
414 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
415
416 pci_bios_init_bus_rec(secbus, pci_bus);
417
418 if (subbus != *pci_bus) {
419 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
420 subbus, *pci_bus);
421 subbus = *pci_bus;
422 } else {
423 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
424 }
425 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
426 }
427}
428
429static void
430pci_bios_init_bus(void)
431{
432 u8 pci_bus = 0;
433 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
434}
435
Kevin O'Connor0525d292008-07-04 06:18:30 -0400436void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400437pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400438{
Ian Campbell74c78782011-06-01 11:00:29 +0100439 if (CONFIG_COREBOOT || usingXen())
440 // Already done by coreboot or Xen.
Kevin O'Connor0525d292008-07-04 06:18:30 -0400441 return;
442
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400443 dprintf(3, "pci setup\n");
444
Isaku Yamahata74fd9422010-12-24 10:51:08 +0900445 pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
Isaku Yamahatae2623fc2010-10-28 15:54:36 +0900446 pci_region_init(&pci_bios_mem_region,
447 BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
448 pci_region_init(&pci_bios_prefmem_region,
449 BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400450
Isaku Yamahataf4416662010-06-22 17:57:52 +0900451 pci_bios_init_bus();
452
Kevin O'Connore6338322008-11-29 20:31:49 -0500453 int bdf, max;
Kevin O'Connorbaac6b62011-06-19 10:46:28 -0400454 foreachbdf(bdf, max) {
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400455 pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
Kevin O'Connore6338322008-11-29 20:31:49 -0500456 }
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900457 pci_bios_init_device_in_bus(0 /* host bus */);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400458}