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Kevin O'Connor30853762009-01-17 18:49:20 -05001// Code for misc 16bit handlers and variables.
2//
Kevin O'Connor2929c352009-07-25 13:48:27 -04003// Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connor30853762009-01-17 18:49:20 -05004// Copyright (C) 2002 MandrakeSoft S.A.
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
Kevin O'Connor30853762009-01-17 18:49:20 -05008#include "biosvar.h" // GET_BDA
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04009#include "bregs.h" // struct bregs
Kevin O'Connor5d369d82013-09-02 20:48:46 -040010#include "hw/pic.h" // enable_hwirq
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040011#include "output.h" // debug_enter
Kevin O'Connor3df600b2013-09-14 19:28:55 -040012#include "stacks.h" // call16_int
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040013#include "string.h" // memset
Kevin O'Connor30853762009-01-17 18:49:20 -050014
Kevin O'Connor4ade5232013-09-18 21:41:48 -040015#define PORT_MATH_CLEAR 0x00f0
16
Kevin O'Connor6c68e7a2014-04-19 12:22:22 -040017// Indicator if POST phase has been started (and if it has completed).
18int HaveRunPost VARFSEG;
19
20int
21in_post(void)
22{
23 return GET_GLOBAL(HaveRunPost) == 1;
24}
25
Kevin O'Connor30853762009-01-17 18:49:20 -050026
27/****************************************************************
28 * Misc 16bit ISRs
29 ****************************************************************/
30
31// INT 12h Memory Size Service Entry Point
32void VISIBLE16
33handle_12(struct bregs *regs)
34{
35 debug_enter(regs, DEBUG_HDL_12);
36 regs->ax = GET_BDA(mem_size_kb);
37}
38
39// INT 11h Equipment List Service Entry Point
40void VISIBLE16
41handle_11(struct bregs *regs)
42{
43 debug_enter(regs, DEBUG_HDL_11);
44 regs->ax = GET_BDA(equipment_list_flags);
45}
46
47// INT 05h Print Screen Service Entry Point
48void VISIBLE16
49handle_05(struct bregs *regs)
50{
51 debug_enter(regs, DEBUG_HDL_05);
52}
53
54// INT 10h Video Support Service Entry Point
55void VISIBLE16
56handle_10(struct bregs *regs)
57{
58 debug_enter(regs, DEBUG_HDL_10);
59 // dont do anything, since the VGA BIOS handles int10h requests
60}
61
Kevin O'Connor75f49b32009-03-07 00:07:24 -050062// NMI handler
Kevin O'Connor30853762009-01-17 18:49:20 -050063void VISIBLE16
Kevin O'Connor1297e5d2012-06-02 20:30:58 -040064handle_02(void)
Kevin O'Connor30853762009-01-17 18:49:20 -050065{
Kevin O'Connor1297e5d2012-06-02 20:30:58 -040066 debug_isr(DEBUG_ISR_02);
Kevin O'Connor30853762009-01-17 18:49:20 -050067}
68
69void
Kevin O'Connor3a735ba2013-02-10 00:35:01 -050070mathcp_setup(void)
Kevin O'Connor30853762009-01-17 18:49:20 -050071{
72 dprintf(3, "math cp init\n");
73 // 80x87 coprocessor installed
Kevin O'Connore51316d2012-06-10 09:09:22 -040074 set_equipment_flags(0x02, 0x02);
Kevin O'Connorcc9e1bf2010-07-28 21:31:38 -040075 enable_hwirq(13, FUNC16(entry_75));
Kevin O'Connor30853762009-01-17 18:49:20 -050076}
77
78// INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
79void VISIBLE16
Kevin O'Connor1297e5d2012-06-02 20:30:58 -040080handle_75(void)
Kevin O'Connor30853762009-01-17 18:49:20 -050081{
Kevin O'Connor1297e5d2012-06-02 20:30:58 -040082 debug_isr(DEBUG_ISR_75);
Kevin O'Connor30853762009-01-17 18:49:20 -050083
84 // clear irq13
85 outb(0, PORT_MATH_CLEAR);
86 // clear interrupt
Kevin O'Connoraa7c2342013-07-14 15:07:21 -040087 pic_eoi2();
Kevin O'Connor30853762009-01-17 18:49:20 -050088 // legacy nmi call
Kevin O'Connorecdc6552012-05-28 14:25:15 -040089 struct bregs br;
90 memset(&br, 0, sizeof(br));
91 br.flags = F_IF;
92 call16_int(0x02, &br);
Kevin O'Connor30853762009-01-17 18:49:20 -050093}
94
95
96/****************************************************************
97 * BIOS_CONFIG_TABLE
98 ****************************************************************/
99
100// DMA channel 3 used by hard disk BIOS
101#define CBT_F1_DMA3USED (1<<7)
102// 2nd interrupt controller (8259) installed
103#define CBT_F1_2NDPIC (1<<6)
104// Real-Time Clock installed
105#define CBT_F1_RTC (1<<5)
106// INT 15/AH=4Fh called upon INT 09h
107#define CBT_F1_INT154F (1<<4)
108// wait for external event (INT 15/AH=41h) supported
109#define CBT_F1_WAITEXT (1<<3)
110// extended BIOS area allocated (usually at top of RAM)
111#define CBT_F1_EBDA (1<<2)
112// bus is Micro Channel instead of ISA
113#define CBT_F1_MCA (1<<1)
114// system has dual bus (Micro Channel + ISA)
115#define CBT_F1_MCAISA (1<<0)
116
117// INT 16/AH=09h (keyboard functionality) supported
118#define CBT_F2_INT1609 (1<<6)
119
Kevin O'Connorab482e02014-06-11 14:00:21 -0400120struct bios_config_table_s BIOS_CONFIG_TABLE VARFSEGFIXED(0xe6f5) = {
Kevin O'Connor30853762009-01-17 18:49:20 -0500121 .size = sizeof(BIOS_CONFIG_TABLE) - 2,
Kevin O'Connore52ad392013-02-20 23:48:22 -0500122 .model = BUILD_MODEL_ID,
123 .submodel = BUILD_SUBMODEL_ID,
124 .biosrev = BUILD_BIOS_REVISION,
Kevin O'Connor30853762009-01-17 18:49:20 -0500125 .feature1 = (
126 CBT_F1_2NDPIC | CBT_F1_RTC | CBT_F1_EBDA
127 | (CONFIG_KBD_CALL_INT15_4F ? CBT_F1_INT154F : 0)),
128 .feature2 = CBT_F2_INT1609,
129 .feature3 = 0,
130 .feature4 = 0,
131 .feature5 = 0,
132};
133
134
135/****************************************************************
136 * GDT and IDT tables
137 ****************************************************************/
138
Kevin O'Connor30853762009-01-17 18:49:20 -0500139// Real mode IDT descriptor
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500140struct descloc_s rmode_IDT_info VARFSEG = {
Kevin O'Connor30853762009-01-17 18:49:20 -0500141 .length = sizeof(struct rmode_IVT) - 1,
Kevin O'Connor35ae7262009-01-19 15:44:44 -0500142 .addr = (u32)MAKE_FLATPTR(SEG_IVT, 0),
Kevin O'Connor30853762009-01-17 18:49:20 -0500143};
144
145// Dummy IDT that forces a machine shutdown if an irq happens in
146// protected mode.
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500147u8 dummy_IDT VARFSEG;
Kevin O'Connor30853762009-01-17 18:49:20 -0500148
149// Protected mode IDT descriptor
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500150struct descloc_s pmode_IDT_info VARFSEG = {
Kevin O'Connor30853762009-01-17 18:49:20 -0500151 .length = sizeof(dummy_IDT) - 1,
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500152 .addr = (u32)&dummy_IDT,
Kevin O'Connor30853762009-01-17 18:49:20 -0500153};
154
155// GDT
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500156u64 rombios32_gdt[] VARFSEG __aligned(8) = {
Kevin O'Connor30853762009-01-17 18:49:20 -0500157 // First entry can't be used.
158 0x0000000000000000LL,
159 // 32 bit flat code segment (SEG32_MODE32_CS)
Kevin O'Connorae6924d2010-07-25 14:46:21 -0400160 GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_B,
Kevin O'Connor30853762009-01-17 18:49:20 -0500161 // 32 bit flat data segment (SEG32_MODE32_DS)
Kevin O'Connorae6924d2010-07-25 14:46:21 -0400162 GDT_GRANLIMIT(0xffffffff) | GDT_DATA | GDT_B,
Kevin O'Connor30853762009-01-17 18:49:20 -0500163 // 16 bit code segment base=0xf0000 limit=0xffff (SEG32_MODE16_CS)
Kevin O'Connor643062f2010-01-04 20:48:20 -0500164 GDT_LIMIT(BUILD_BIOS_SIZE-1) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
Kevin O'Connor30853762009-01-17 18:49:20 -0500165 // 16 bit data segment base=0x0 limit=0xffff (SEG32_MODE16_DS)
Kevin O'Connoreaa2e552009-08-10 00:03:04 -0400166 GDT_LIMIT(0x0ffff) | GDT_DATA,
Kevin O'Connor0f788892010-07-25 14:04:01 -0400167 // 16 bit code segment base=0xf0000 limit=0xffffffff (SEG32_MODE16BIG_CS)
Kevin O'Connorae6924d2010-07-25 14:46:21 -0400168 GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
Kevin O'Connor30853762009-01-17 18:49:20 -0500169 // 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS)
Kevin O'Connorae6924d2010-07-25 14:46:21 -0400170 GDT_GRANLIMIT(0xffffffff) | GDT_DATA,
Kevin O'Connor30853762009-01-17 18:49:20 -0500171};
172
173// GDT descriptor
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500174struct descloc_s rombios32_gdt_48 VARFSEG = {
Kevin O'Connor30853762009-01-17 18:49:20 -0500175 .length = sizeof(rombios32_gdt) - 1,
Kevin O'Connor89a2f962013-02-18 23:36:03 -0500176 .addr = (u32)rombios32_gdt,
Kevin O'Connor30853762009-01-17 18:49:20 -0500177};
178
179
180/****************************************************************
181 * Misc fixed vars
182 ****************************************************************/
183
Kevin O'Connor30853762009-01-17 18:49:20 -0500184// BIOS build date
Kevin O'Connorab482e02014-06-11 14:00:21 -0400185char BiosDate[] VARFSEGFIXED(0xfff5) = "06/23/99";
Kevin O'Connor30853762009-01-17 18:49:20 -0500186
Kevin O'Connorab482e02014-06-11 14:00:21 -0400187u8 BiosModelId VARFSEGFIXED(0xfffe) = BUILD_MODEL_ID;
Kevin O'Connor30853762009-01-17 18:49:20 -0500188
Kevin O'Connorab482e02014-06-11 14:00:21 -0400189u8 BiosChecksum VARFSEGFIXED(0xffff);
Kevin O'Connor30853762009-01-17 18:49:20 -0500190
Kevin O'Connorab482e02014-06-11 14:00:21 -0400191struct floppy_dbt_s diskette_param_table VARFSEGFIXED(0xefc7);
Kevin O'Connorca34ce52014-05-24 10:40:35 -0400192
193// Old Fixed Disk Parameter Table (newer tables are in the ebda).
Kevin O'Connorab482e02014-06-11 14:00:21 -0400194struct fdpt_s OldFDPT VARFSEGFIXED(0xe401);
Kevin O'Connorca34ce52014-05-24 10:40:35 -0400195
196// XXX - Baud Rate Generator Table
Kevin O'Connorab482e02014-06-11 14:00:21 -0400197u8 BaudTable[16] VARFSEGFIXED(0xe729);
Kevin O'Connorca34ce52014-05-24 10:40:35 -0400198
Kevin O'Connor30853762009-01-17 18:49:20 -0500199// XXX - Initial Interrupt Vector Offsets Loaded by POST
Kevin O'Connorab482e02014-06-11 14:00:21 -0400200u8 InitVectors[13] VARFSEGFIXED(0xfef3);
Kevin O'Connor30853762009-01-17 18:49:20 -0500201
202// XXX - INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES
Kevin O'Connorab482e02014-06-11 14:00:21 -0400203u8 VideoParams[88] VARFSEGFIXED(0xf0a4);