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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
6// This file may be distributed under the terms of the GNU GPLv3 license.
7
8#include "util.h" // dprintf
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -05009#include "pci.h" // pci_config_readl
Kevin O'Connor9521e262008-07-04 13:04:29 -040010#include "biosvar.h" // GET_EBDA
Kevin O'Connor2ed2f582008-11-08 15:53:36 -050011#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12#include "pci_regs.h" // PCI_COMMAND
Kevin O'Connor0525d292008-07-04 06:18:30 -040013
14#define PCI_ADDRESS_SPACE_MEM 0x00
15#define PCI_ADDRESS_SPACE_IO 0x01
16#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
17
18#define PCI_ROM_SLOT 6
19#define PCI_NUM_REGIONS 7
20
Kevin O'Connor0525d292008-07-04 06:18:30 -040021static u32 pci_bios_io_addr;
22static u32 pci_bios_mem_addr;
23static u32 pci_bios_bigmem_addr;
24/* host irqs corresponding to PCI irqs A-D */
25static u8 pci_irqs[4] = { 11, 9, 11, 9 };
26
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050027static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
Kevin O'Connor0525d292008-07-04 06:18:30 -040028{
29 u16 cmd;
30 u32 ofs, old_addr;
31
32 if ( region_num == PCI_ROM_SLOT ) {
33 ofs = 0x30;
34 }else{
35 ofs = 0x10 + region_num * 4;
36 }
37
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050038 old_addr = pci_config_readl(bdf, ofs);
Kevin O'Connor0525d292008-07-04 06:18:30 -040039
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050040 pci_config_writel(bdf, ofs, addr);
Kevin O'Connor0525d292008-07-04 06:18:30 -040041 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
42
43 /* enable memory mappings */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050044 cmd = pci_config_readw(bdf, PCI_COMMAND);
Kevin O'Connor0525d292008-07-04 06:18:30 -040045 if ( region_num == PCI_ROM_SLOT )
46 cmd |= 2;
47 else if (old_addr & PCI_ADDRESS_SPACE_IO)
48 cmd |= 1;
49 else
50 cmd |= 2;
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050051 pci_config_writew(bdf, PCI_COMMAND, cmd);
Kevin O'Connor0525d292008-07-04 06:18:30 -040052}
53
54/* return the global irq number corresponding to a given device irq
55 pin. We could also use the bus number to have a more precise
56 mapping. */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050057static int pci_slot_get_pirq(u16 bdf, int irq_num)
Kevin O'Connor0525d292008-07-04 06:18:30 -040058{
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050059 int slot_addend = pci_bdf_to_dev(bdf) - 1;
Kevin O'Connor0525d292008-07-04 06:18:30 -040060 return (irq_num + slot_addend) & 3;
61}
62
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050063static void pci_bios_init_bridges(u16 bdf)
Kevin O'Connor0525d292008-07-04 06:18:30 -040064{
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050065 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
66 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
Kevin O'Connor0525d292008-07-04 06:18:30 -040067
Kevin O'Connor415c2dc2008-10-25 14:35:59 -040068 if (vendor_id == PCI_VENDOR_ID_INTEL
Kevin O'Connor2f840e32008-10-25 15:23:23 -040069 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
70 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
Kevin O'Connor0525d292008-07-04 06:18:30 -040071 int i, irq;
72 u8 elcr[2];
73
Kevin O'Connor2f840e32008-10-25 15:23:23 -040074 /* PIIX3/PIIX4 PCI to ISA bridge */
Kevin O'Connor0525d292008-07-04 06:18:30 -040075
76 elcr[0] = 0x00;
77 elcr[1] = 0x00;
78 for(i = 0; i < 4; i++) {
79 irq = pci_irqs[i];
80 /* set to trigger level */
81 elcr[irq >> 3] |= (1 << (irq & 7));
82 /* activate irq remapping in PIIX */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050083 pci_config_writeb(bdf, 0x60 + i, irq);
Kevin O'Connor0525d292008-07-04 06:18:30 -040084 }
85 outb(elcr[0], 0x4d0);
86 outb(elcr[1], 0x4d1);
Kevin O'Connor2f840e32008-10-25 15:23:23 -040087 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
Kevin O'Connor0525d292008-07-04 06:18:30 -040088 elcr[0], elcr[1]);
89 }
90}
91
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050092static void pci_bios_init_device(u16 bdf)
Kevin O'Connor0525d292008-07-04 06:18:30 -040093{
94 int class;
95 u32 *paddr;
96 int i, pin, pic_irq, vendor_id, device_id;
97
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -050098 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
99 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
100 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
101 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
102 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400103 switch(class) {
104 case 0x0101:
Kevin O'Connor415c2dc2008-10-25 14:35:59 -0400105 if (vendor_id == PCI_VENDOR_ID_INTEL
Kevin O'Connor2f840e32008-10-25 15:23:23 -0400106 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
107 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
108 /* PIIX3/PIIX4 IDE */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500109 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
110 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
Kevin O'Connor0525d292008-07-04 06:18:30 -0400111 goto default_map;
112 } else {
113 /* IDE: we map it as in ISA mode */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500114 pci_set_io_region_addr(bdf, 0, 0x1f0);
115 pci_set_io_region_addr(bdf, 1, 0x3f4);
116 pci_set_io_region_addr(bdf, 2, 0x170);
117 pci_set_io_region_addr(bdf, 3, 0x374);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400118 }
119 break;
120 case 0x0300:
121 if (vendor_id != 0x1234)
122 goto default_map;
123 /* VGA: map frame buffer to default Bochs VBE address */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500124 pci_set_io_region_addr(bdf, 0, 0xE0000000);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400125 break;
126 case 0x0800:
127 /* PIC */
Kevin O'Connor415c2dc2008-10-25 14:35:59 -0400128 if (vendor_id == PCI_VENDOR_ID_IBM) {
Kevin O'Connor0525d292008-07-04 06:18:30 -0400129 /* IBM */
130 if (device_id == 0x0046 || device_id == 0xFFFF) {
131 /* MPIC & MPIC2 */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500132 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400133 }
134 }
135 break;
136 case 0xff00:
Kevin O'Connor415c2dc2008-10-25 14:35:59 -0400137 if (vendor_id == PCI_VENDOR_ID_APPLE &&
Kevin O'Connor0525d292008-07-04 06:18:30 -0400138 (device_id == 0x0017 || device_id == 0x0022)) {
139 /* macio bridge */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500140 pci_set_io_region_addr(bdf, 0, 0x80800000);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400141 }
142 break;
143 default:
144 default_map:
145 /* default memory mappings */
146 for(i = 0; i < PCI_NUM_REGIONS; i++) {
147 int ofs;
Kevin O'Connore06363e2008-08-29 21:12:03 -0400148 u32 val, size;
Kevin O'Connor0525d292008-07-04 06:18:30 -0400149
150 if (i == PCI_ROM_SLOT)
151 ofs = 0x30;
152 else
153 ofs = 0x10 + i * 4;
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500154 pci_config_writel(bdf, ofs, 0xffffffff);
155 val = pci_config_readl(bdf, ofs);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400156 if (val != 0) {
157 size = (~(val & ~0xf)) + 1;
158 if (val & PCI_ADDRESS_SPACE_IO)
159 paddr = &pci_bios_io_addr;
160 else if (size >= 0x04000000)
161 paddr = &pci_bios_bigmem_addr;
162 else
163 paddr = &pci_bios_mem_addr;
Kevin O'Connore06363e2008-08-29 21:12:03 -0400164 *paddr = ALIGN(*paddr, size);
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500165 pci_set_io_region_addr(bdf, i, *paddr);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400166 *paddr += size;
167 }
168 }
169 break;
170 }
171
172 /* map the interrupt */
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500173 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400174 if (pin != 0) {
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500175 pin = pci_slot_get_pirq(bdf, pin - 1);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400176 pic_irq = pci_irqs[pin];
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500177 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400178 }
179
Kevin O'Connor415c2dc2008-10-25 14:35:59 -0400180 if (vendor_id == PCI_VENDOR_ID_INTEL
181 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
Kevin O'Connor0525d292008-07-04 06:18:30 -0400182 /* PIIX4 Power Management device (for ACPI) */
183 u32 pm_io_base = BUILD_PM_IO_BASE;
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500184 pci_config_writel(bdf, 0x40, pm_io_base | 1);
185 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
Kevin O'Connor0525d292008-07-04 06:18:30 -0400186 u32 smb_io_base = BUILD_SMB_IO_BASE;
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500187 pci_config_writel(bdf, 0x90, smb_io_base | 1);
188 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
Kevin O'Connor0525d292008-07-04 06:18:30 -0400189 }
190}
191
Kevin O'Connor0525d292008-07-04 06:18:30 -0400192void
193pci_bios_setup(void)
194{
195 if (CONFIG_COREBOOT)
196 // Already done by coreboot.
197 return;
198
199 pci_bios_io_addr = 0xc000;
200 pci_bios_mem_addr = 0xf0000000;
201 pci_bios_bigmem_addr = GET_EBDA(ram_size);
202 if (pci_bios_bigmem_addr < 0x90000000)
203 pci_bios_bigmem_addr = 0x90000000;
204
Kevin O'Connore6338322008-11-29 20:31:49 -0500205 int bdf, max;
Kevin O'Connor4132e022008-12-04 19:39:10 -0500206 foreachpci(bdf, max) {
Kevin O'Connore6338322008-11-29 20:31:49 -0500207 pci_bios_init_bridges(bdf);
208 }
Kevin O'Connor4132e022008-12-04 19:39:10 -0500209 foreachpci(bdf, max) {
Kevin O'Connore6338322008-11-29 20:31:49 -0500210 pci_bios_init_device(bdf);
211 }
Kevin O'Connor0525d292008-07-04 06:18:30 -0400212}